Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.50 96.07 90.96 96.79 60.94 94.79 97.35 96.58


Total test records in report: 1832
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html
T235 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.414775754 May 21 02:07:15 PM PDT 24 May 21 02:07:17 PM PDT 24 44728566 ps
T1768 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3561650788 May 21 02:07:16 PM PDT 24 May 21 02:07:20 PM PDT 24 156889579 ps
T270 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3190642619 May 21 02:07:35 PM PDT 24 May 21 02:07:42 PM PDT 24 530306197 ps
T1769 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2338412369 May 21 02:07:29 PM PDT 24 May 21 02:07:32 PM PDT 24 107649717 ps
T266 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3185361039 May 21 02:07:32 PM PDT 24 May 21 02:07:36 PM PDT 24 304486914 ps
T1770 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.984361116 May 21 02:07:21 PM PDT 24 May 21 02:07:24 PM PDT 24 47178537 ps
T236 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1052891183 May 21 02:07:21 PM PDT 24 May 21 02:07:26 PM PDT 24 157950908 ps
T258 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2180293543 May 21 02:07:26 PM PDT 24 May 21 02:07:28 PM PDT 24 32821065 ps
T267 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.564462534 May 21 02:07:32 PM PDT 24 May 21 02:07:38 PM PDT 24 538832958 ps
T1771 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3588703920 May 21 02:07:26 PM PDT 24 May 21 02:07:29 PM PDT 24 63648282 ps
T237 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2814502938 May 21 02:07:14 PM PDT 24 May 21 02:07:16 PM PDT 24 38997405 ps
T1772 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1114388068 May 21 02:07:33 PM PDT 24 May 21 02:07:34 PM PDT 24 30210005 ps
T253 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.4002506637 May 21 02:07:42 PM PDT 24 May 21 02:07:44 PM PDT 24 66421718 ps
T1773 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2024933382 May 21 02:07:38 PM PDT 24 May 21 02:07:42 PM PDT 24 157943956 ps
T1774 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3221854346 May 21 02:07:16 PM PDT 24 May 21 02:07:19 PM PDT 24 92787551 ps
T238 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.16991619 May 21 02:07:07 PM PDT 24 May 21 02:07:14 PM PDT 24 729922228 ps
T1775 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3079021756 May 21 02:07:45 PM PDT 24 May 21 02:07:51 PM PDT 24 44226250 ps
T1776 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3993958409 May 21 02:07:15 PM PDT 24 May 21 02:07:20 PM PDT 24 154989512 ps
T1777 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1841867731 May 21 02:07:34 PM PDT 24 May 21 02:07:37 PM PDT 24 29698912 ps
T263 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2527787643 May 21 02:07:21 PM PDT 24 May 21 02:07:24 PM PDT 24 251285009 ps
T1778 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3206096320 May 21 02:07:15 PM PDT 24 May 21 02:07:20 PM PDT 24 105227278 ps
T1779 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2833882863 May 21 02:07:41 PM PDT 24 May 21 02:07:44 PM PDT 24 60753322 ps
T1780 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2500209759 May 21 02:07:27 PM PDT 24 May 21 02:07:29 PM PDT 24 101532579 ps
T1781 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1332759903 May 21 02:07:16 PM PDT 24 May 21 02:07:19 PM PDT 24 39584549 ps
T1782 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.320278590 May 21 02:07:21 PM PDT 24 May 21 02:07:25 PM PDT 24 165671440 ps
T1783 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3276298369 May 21 02:07:22 PM PDT 24 May 21 02:07:25 PM PDT 24 60142667 ps
T1784 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1345911133 May 21 02:07:38 PM PDT 24 May 21 02:07:43 PM PDT 24 87691483 ps
T268 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2579481311 May 21 02:07:20 PM PDT 24 May 21 02:07:24 PM PDT 24 555202134 ps
T1785 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2559793824 May 21 02:07:45 PM PDT 24 May 21 02:07:49 PM PDT 24 39160156 ps
T1786 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1210210715 May 21 02:07:09 PM PDT 24 May 21 02:07:15 PM PDT 24 370357703 ps
T206 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3742165611 May 21 02:07:36 PM PDT 24 May 21 02:07:40 PM PDT 24 136699056 ps
T269 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.793727598 May 21 02:07:41 PM PDT 24 May 21 02:07:47 PM PDT 24 615820347 ps
T259 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3284142159 May 21 02:07:46 PM PDT 24 May 21 02:07:52 PM PDT 24 38029949 ps
T1787 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2954457381 May 21 02:07:37 PM PDT 24 May 21 02:07:39 PM PDT 24 53889943 ps
T1788 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3069960135 May 21 02:07:15 PM PDT 24 May 21 02:07:17 PM PDT 24 47594539 ps
T260 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2527007459 May 21 02:07:47 PM PDT 24 May 21 02:07:55 PM PDT 24 37005268 ps
T1789 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3187719798 May 21 02:07:46 PM PDT 24 May 21 02:07:52 PM PDT 24 40030288 ps
T1790 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1467029298 May 21 02:07:13 PM PDT 24 May 21 02:07:23 PM PDT 24 1023120823 ps
T1791 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3631963024 May 21 02:07:34 PM PDT 24 May 21 02:07:37 PM PDT 24 51847067 ps
T1792 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.807138543 May 21 02:07:27 PM PDT 24 May 21 02:07:31 PM PDT 24 63724732 ps
T207 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1823781265 May 21 02:07:39 PM PDT 24 May 21 02:07:43 PM PDT 24 228069489 ps
T1793 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.300479885 May 21 02:07:34 PM PDT 24 May 21 02:07:36 PM PDT 24 193274669 ps
T264 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.4237148994 May 21 02:07:28 PM PDT 24 May 21 02:07:34 PM PDT 24 323932576 ps
T1794 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1144225624 May 21 02:07:26 PM PDT 24 May 21 02:07:28 PM PDT 24 114668794 ps
T1795 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.4257012310 May 21 02:07:15 PM PDT 24 May 21 02:07:21 PM PDT 24 700651247 ps
T1796 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3438328674 May 21 02:07:45 PM PDT 24 May 21 02:07:50 PM PDT 24 31930500 ps
T1797 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2144245110 May 21 02:07:22 PM PDT 24 May 21 02:07:27 PM PDT 24 162692902 ps
T1798 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1475883539 May 21 02:07:21 PM PDT 24 May 21 02:07:24 PM PDT 24 94884970 ps
T1799 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.133706789 May 21 02:07:27 PM PDT 24 May 21 02:07:29 PM PDT 24 97375399 ps
T1800 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.174758777 May 21 02:07:34 PM PDT 24 May 21 02:07:37 PM PDT 24 30996382 ps
T1801 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3274792644 May 21 02:07:26 PM PDT 24 May 21 02:07:28 PM PDT 24 80822801 ps
T1802 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1351508692 May 21 02:07:14 PM PDT 24 May 21 02:07:19 PM PDT 24 177663688 ps
T1803 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.77924231 May 21 02:07:47 PM PDT 24 May 21 02:07:54 PM PDT 24 105131720 ps
T1804 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3632543868 May 21 02:07:26 PM PDT 24 May 21 02:07:28 PM PDT 24 91257724 ps
T1805 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.617235885 May 21 02:07:09 PM PDT 24 May 21 02:07:12 PM PDT 24 52590951 ps
T1806 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3836788669 May 21 02:07:10 PM PDT 24 May 21 02:07:12 PM PDT 24 84401169 ps
T1807 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.638508975 May 21 02:07:21 PM PDT 24 May 21 02:07:24 PM PDT 24 27998545 ps
T1808 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2712752754 May 21 02:07:21 PM PDT 24 May 21 02:07:26 PM PDT 24 329829702 ps
T1809 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.717457392 May 21 02:07:34 PM PDT 24 May 21 02:07:40 PM PDT 24 325844259 ps
T1810 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.585827729 May 21 02:07:28 PM PDT 24 May 21 02:07:32 PM PDT 24 515924714 ps
T1811 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2483524732 May 21 02:07:08 PM PDT 24 May 21 02:07:12 PM PDT 24 229494186 ps
T1812 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1577224960 May 21 02:07:13 PM PDT 24 May 21 02:07:15 PM PDT 24 45012384 ps
T1813 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1249171788 May 21 02:07:28 PM PDT 24 May 21 02:07:31 PM PDT 24 157738066 ps
T1814 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2588459189 May 21 02:07:28 PM PDT 24 May 21 02:07:31 PM PDT 24 155077140 ps
T1815 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2434988986 May 21 02:07:38 PM PDT 24 May 21 02:07:42 PM PDT 24 183506937 ps
T1816 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1422580356 May 21 02:07:38 PM PDT 24 May 21 02:07:41 PM PDT 24 35702147 ps
T1817 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3501491057 May 21 02:07:20 PM PDT 24 May 21 02:07:25 PM PDT 24 471760097 ps
T1818 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3568887638 May 21 02:07:46 PM PDT 24 May 21 02:07:52 PM PDT 24 35789836 ps
T1819 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3734707057 May 21 02:07:50 PM PDT 24 May 21 02:07:57 PM PDT 24 33114799 ps
T1820 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3745593371 May 21 02:07:31 PM PDT 24 May 21 02:07:33 PM PDT 24 61471197 ps
T1821 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1964188059 May 21 02:07:41 PM PDT 24 May 21 02:07:46 PM PDT 24 100767284 ps
T1822 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3412443708 May 21 02:07:40 PM PDT 24 May 21 02:07:42 PM PDT 24 36121513 ps
T1823 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.684840593 May 21 02:07:41 PM PDT 24 May 21 02:07:44 PM PDT 24 27505584 ps
T1824 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.682851442 May 21 02:07:34 PM PDT 24 May 21 02:07:35 PM PDT 24 56515675 ps
T1825 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.782531083 May 21 02:07:35 PM PDT 24 May 21 02:07:40 PM PDT 24 92370405 ps
T1826 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2520869146 May 21 02:07:47 PM PDT 24 May 21 02:07:55 PM PDT 24 42739208 ps
T1827 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.947724390 May 21 02:07:14 PM PDT 24 May 21 02:07:19 PM PDT 24 777305848 ps
T1828 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1134822946 May 21 02:07:44 PM PDT 24 May 21 02:07:49 PM PDT 24 52929412 ps
T1829 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.742568000 May 21 02:07:16 PM PDT 24 May 21 02:07:20 PM PDT 24 68865617 ps
T1830 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3184990346 May 21 02:07:33 PM PDT 24 May 21 02:07:36 PM PDT 24 113703317 ps
T1831 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2356872467 May 21 02:07:47 PM PDT 24 May 21 02:07:54 PM PDT 24 68356556 ps
T1832 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3475249409 May 21 02:07:08 PM PDT 24 May 21 02:07:13 PM PDT 24 563058325 ps

Test location /workspace/coverage/default/22.usbdev_endpoint_access.1082048128
Short name T21
Test name
Test status
Simulation time 9083672602 ps
CPU time 13.84 seconds
Started May 21 01:08:45 PM PDT 24
Finished May 21 01:09:01 PM PDT 24
Peak memory 205300 kb
Host smart-8f57f4a3-4ec6-4a48-92bb-d11b9b643cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10820
48128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.1082048128
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1229794028
Short name T250
Test name
Test status
Simulation time 34656097 ps
CPU time 0.69 seconds
Started May 21 02:07:47 PM PDT 24
Finished May 21 02:07:54 PM PDT 24
Peak memory 203820 kb
Host smart-fa34f457-64ab-4b10-9a0e-3ddecf92926d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1229794028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1229794028
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.4131406077
Short name T75
Test name
Test status
Simulation time 531477212 ps
CPU time 3.16 seconds
Started May 21 02:07:42 PM PDT 24
Finished May 21 02:07:47 PM PDT 24
Peak memory 204812 kb
Host smart-94aaa722-f1f1-4449-b113-ef5cdfb3432d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4131406077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.4131406077
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/12.usbdev_smoke.3304366344
Short name T112
Test name
Test status
Simulation time 8443653625 ps
CPU time 12.05 seconds
Started May 21 01:06:58 PM PDT 24
Finished May 21 01:07:12 PM PDT 24
Peak memory 205392 kb
Host smart-b1552bb6-17a8-4cb8-a44c-ea536730b1ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33043
66344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3304366344
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.917452643
Short name T284
Test name
Test status
Simulation time 8425063883 ps
CPU time 11.85 seconds
Started May 21 01:04:20 PM PDT 24
Finished May 21 01:04:33 PM PDT 24
Peak memory 205264 kb
Host smart-11be171d-2733-4574-bc82-d68f1f620ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91745
2643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.917452643
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.435957210
Short name T252
Test name
Test status
Simulation time 31143849 ps
CPU time 0.69 seconds
Started May 21 02:07:22 PM PDT 24
Finished May 21 02:07:24 PM PDT 24
Peak memory 203872 kb
Host smart-5f143acb-38d2-4391-a719-bb0dc58c7467
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=435957210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.435957210
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.3396790671
Short name T5
Test name
Test status
Simulation time 11545166584 ps
CPU time 14.74 seconds
Started May 21 01:06:49 PM PDT 24
Finished May 21 01:07:05 PM PDT 24
Peak memory 205348 kb
Host smart-25a51d0b-5dbb-4c7b-9bd0-85b141db1d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33967
90671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.3396790671
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1675101031
Short name T77
Test name
Test status
Simulation time 317254213 ps
CPU time 3.63 seconds
Started May 21 02:07:35 PM PDT 24
Finished May 21 02:07:41 PM PDT 24
Peak memory 212856 kb
Host smart-ae8fa6d5-bf2d-46d9-90c7-335460f18095
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1675101031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.1675101031
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.2696972746
Short name T3
Test name
Test status
Simulation time 8396830958 ps
CPU time 13.15 seconds
Started May 21 01:05:10 PM PDT 24
Finished May 21 01:05:25 PM PDT 24
Peak memory 205308 kb
Host smart-119bc16b-5933-4047-b0f3-66159326f74f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26969
72746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.2696972746
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.2596011752
Short name T56
Test name
Test status
Simulation time 8455915302 ps
CPU time 11.68 seconds
Started May 21 01:07:43 PM PDT 24
Finished May 21 01:07:56 PM PDT 24
Peak memory 205308 kb
Host smart-2ccbe1d0-f3fc-4dd4-9c5a-a14f78f24fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25960
11752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.2596011752
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.1180593433
Short name T54
Test name
Test status
Simulation time 8367471014 ps
CPU time 11.2 seconds
Started May 21 01:04:18 PM PDT 24
Finished May 21 01:04:30 PM PDT 24
Peak memory 205308 kb
Host smart-49efdf40-0aeb-4939-9432-a9372fc7ee04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11805
93433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.1180593433
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.756744986
Short name T141
Test name
Test status
Simulation time 8504496966 ps
CPU time 14.37 seconds
Started May 21 01:08:02 PM PDT 24
Finished May 21 01:08:18 PM PDT 24
Peak memory 205292 kb
Host smart-aabab99e-0e64-4e8b-abee-e62ab28a8862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75674
4986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.756744986
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.2695371362
Short name T72
Test name
Test status
Simulation time 319735606 ps
CPU time 1.27 seconds
Started May 21 01:05:10 PM PDT 24
Finished May 21 01:05:13 PM PDT 24
Peak memory 222308 kb
Host smart-0ffea17d-4706-4e70-a53a-590dc9198a2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2695371362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2695371362
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.2502807106
Short name T10
Test name
Test status
Simulation time 8360885953 ps
CPU time 14.93 seconds
Started May 21 01:04:16 PM PDT 24
Finished May 21 01:04:33 PM PDT 24
Peak memory 205308 kb
Host smart-f2072bef-4f95-4e3c-a327-1cc74616987d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25028
07106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.2502807106
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.1761074655
Short name T43
Test name
Test status
Simulation time 9458630973 ps
CPU time 13.07 seconds
Started May 21 01:11:14 PM PDT 24
Finished May 21 01:11:29 PM PDT 24
Peak memory 205356 kb
Host smart-4b57ca87-7dcf-4033-9c90-9b9f2e56a9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17610
74655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.1761074655
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.1944841317
Short name T62
Test name
Test status
Simulation time 8369286754 ps
CPU time 12.18 seconds
Started May 21 01:12:44 PM PDT 24
Finished May 21 01:12:59 PM PDT 24
Peak memory 205380 kb
Host smart-c3b2b088-41d0-447e-a0e2-5c07f1402831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19448
41317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.1944841317
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2608107161
Short name T254
Test name
Test status
Simulation time 44694029 ps
CPU time 0.69 seconds
Started May 21 02:07:34 PM PDT 24
Finished May 21 02:07:37 PM PDT 24
Peak memory 203796 kb
Host smart-f8868649-3047-4b20-aaea-77b712782db4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2608107161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2608107161
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.981569070
Short name T64
Test name
Test status
Simulation time 8398681960 ps
CPU time 12.04 seconds
Started May 21 01:08:25 PM PDT 24
Finished May 21 01:08:38 PM PDT 24
Peak memory 205368 kb
Host smart-4b728ddb-df29-44d6-aaba-541330de4639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98156
9070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.981569070
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3235798577
Short name T230
Test name
Test status
Simulation time 35738919 ps
CPU time 0.91 seconds
Started May 21 02:07:35 PM PDT 24
Finished May 21 02:07:38 PM PDT 24
Peak memory 204492 kb
Host smart-eebbc663-db34-4772-98fe-65125dbfe922
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3235798577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3235798577
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.684769395
Short name T83
Test name
Test status
Simulation time 50317272 ps
CPU time 0.67 seconds
Started May 21 02:07:47 PM PDT 24
Finished May 21 02:07:54 PM PDT 24
Peak memory 203860 kb
Host smart-19ecf630-b73b-48fa-8d77-4a84bc8c4387
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=684769395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.684769395
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.2295384526
Short name T34
Test name
Test status
Simulation time 8382769599 ps
CPU time 11.86 seconds
Started May 21 01:07:10 PM PDT 24
Finished May 21 01:07:23 PM PDT 24
Peak memory 205264 kb
Host smart-70e88376-8be5-4634-b3ea-29fb70f14c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22953
84526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.2295384526
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.564462534
Short name T267
Test name
Test status
Simulation time 538832958 ps
CPU time 4.95 seconds
Started May 21 02:07:32 PM PDT 24
Finished May 21 02:07:38 PM PDT 24
Peak memory 204648 kb
Host smart-96f3b158-a3f0-423f-b6f5-8895cdd7ba06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=564462534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.564462534
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.1340904861
Short name T188
Test name
Test status
Simulation time 30058277046 ps
CPU time 58.39 seconds
Started May 21 01:12:01 PM PDT 24
Finished May 21 01:13:01 PM PDT 24
Peak memory 205444 kb
Host smart-d2a50090-a4c0-4caa-9665-4a4dbad27b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13409
04861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.1340904861
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3187439339
Short name T248
Test name
Test status
Simulation time 49556922 ps
CPU time 0.66 seconds
Started May 21 02:07:11 PM PDT 24
Finished May 21 02:07:13 PM PDT 24
Peak memory 203872 kb
Host smart-b53d4ea2-a6a4-40ed-8dcc-5ae1053ac44a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3187439339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3187439339
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/default/31.usbdev_enable.133675425
Short name T58
Test name
Test status
Simulation time 8377051671 ps
CPU time 13.33 seconds
Started May 21 01:10:09 PM PDT 24
Finished May 21 01:10:23 PM PDT 24
Peak memory 205364 kb
Host smart-1c882bdd-ede1-43d6-b2f6-023bdb140ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13367
5425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.133675425
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.4237148994
Short name T264
Test name
Test status
Simulation time 323932576 ps
CPU time 4.04 seconds
Started May 21 02:07:28 PM PDT 24
Finished May 21 02:07:34 PM PDT 24
Peak memory 204620 kb
Host smart-faa7eeb5-e20c-41a6-a993-0447786b7972
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4237148994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.4237148994
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.793727598
Short name T269
Test name
Test status
Simulation time 615820347 ps
CPU time 4.52 seconds
Started May 21 02:07:41 PM PDT 24
Finished May 21 02:07:47 PM PDT 24
Peak memory 204632 kb
Host smart-a0147e98-eda6-4bd1-a465-0492283d3977
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=793727598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.793727598
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.1078617690
Short name T202
Test name
Test status
Simulation time 5132462795 ps
CPU time 32.96 seconds
Started May 21 01:04:09 PM PDT 24
Finished May 21 01:04:43 PM PDT 24
Peak memory 205348 kb
Host smart-c3b3f8dd-ef91-4a7b-8679-3f1b4b05a115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10786
17690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.1078617690
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.1951498964
Short name T387
Test name
Test status
Simulation time 8419136469 ps
CPU time 14.85 seconds
Started May 21 01:10:58 PM PDT 24
Finished May 21 01:11:15 PM PDT 24
Peak memory 205300 kb
Host smart-edeb82f5-29cb-4042-ab44-0016ae2629df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19514
98964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.1951498964
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1082727330
Short name T81
Test name
Test status
Simulation time 71058968 ps
CPU time 0.95 seconds
Started May 21 02:07:10 PM PDT 24
Finished May 21 02:07:13 PM PDT 24
Peak memory 204300 kb
Host smart-3eb60bdd-1be8-4ff2-8dd5-33f0342b23ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1082727330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1082727330
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3631963024
Short name T1791
Test name
Test status
Simulation time 51847067 ps
CPU time 0.72 seconds
Started May 21 02:07:34 PM PDT 24
Finished May 21 02:07:37 PM PDT 24
Peak memory 203904 kb
Host smart-f5c400dd-08aa-422f-9556-b04628a6ad71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3631963024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3631963024
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.4038580600
Short name T1740
Test name
Test status
Simulation time 274395085 ps
CPU time 3.68 seconds
Started May 21 02:07:33 PM PDT 24
Finished May 21 02:07:38 PM PDT 24
Peak memory 212784 kb
Host smart-1a74ac95-2a39-40cb-9054-26d0b5504754
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4038580600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.4038580600
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.1838196799
Short name T558
Test name
Test status
Simulation time 8366384390 ps
CPU time 11.59 seconds
Started May 21 01:08:14 PM PDT 24
Finished May 21 01:08:27 PM PDT 24
Peak memory 205380 kb
Host smart-a0f2b739-c4cc-4fc4-b9bc-a842dee78171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18381
96799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.1838196799
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.3657382936
Short name T201
Test name
Test status
Simulation time 8411617564 ps
CPU time 12.16 seconds
Started May 21 01:04:18 PM PDT 24
Finished May 21 01:04:31 PM PDT 24
Peak memory 205396 kb
Host smart-31c30415-8940-4a60-9174-8c4bb33c9451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36573
82936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.3657382936
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.158747604
Short name T14
Test name
Test status
Simulation time 30093549731 ps
CPU time 57.52 seconds
Started May 21 01:09:29 PM PDT 24
Finished May 21 01:10:28 PM PDT 24
Peak memory 205448 kb
Host smart-699beeee-cb4b-49c8-8fbe-b8a83e823564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15874
7604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.158747604
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.95896128
Short name T192
Test name
Test status
Simulation time 8382837131 ps
CPU time 11.34 seconds
Started May 21 01:07:00 PM PDT 24
Finished May 21 01:07:14 PM PDT 24
Peak memory 205356 kb
Host smart-d93693a2-cb70-48b9-a725-09dfee78906e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95896
128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.95896128
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.4046625557
Short name T170
Test name
Test status
Simulation time 8383781482 ps
CPU time 14.03 seconds
Started May 21 01:07:12 PM PDT 24
Finished May 21 01:07:28 PM PDT 24
Peak memory 205396 kb
Host smart-2324a1f1-166e-4dbe-8f80-41bfb8bc89ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40466
25557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.4046625557
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.1137786204
Short name T196
Test name
Test status
Simulation time 8374490139 ps
CPU time 13.48 seconds
Started May 21 01:07:42 PM PDT 24
Finished May 21 01:07:57 PM PDT 24
Peak memory 205396 kb
Host smart-73435543-f1a2-43b8-9597-8b79a8c7a818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11377
86204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.1137786204
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.3707789002
Short name T190
Test name
Test status
Simulation time 8386132570 ps
CPU time 15.14 seconds
Started May 21 01:08:16 PM PDT 24
Finished May 21 01:08:33 PM PDT 24
Peak memory 205344 kb
Host smart-f9fe336a-c949-41e1-a6d1-e9cb92201ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37077
89002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.3707789002
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.2675253960
Short name T186
Test name
Test status
Simulation time 8410949865 ps
CPU time 12.22 seconds
Started May 21 01:08:23 PM PDT 24
Finished May 21 01:08:37 PM PDT 24
Peak memory 205256 kb
Host smart-30172bb6-94c8-4f51-aa4b-a1d895d94745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26752
53960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.2675253960
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.3746181288
Short name T912
Test name
Test status
Simulation time 8407906708 ps
CPU time 11.15 seconds
Started May 21 01:09:59 PM PDT 24
Finished May 21 01:10:11 PM PDT 24
Peak memory 205344 kb
Host smart-249c6d12-8910-427d-9b75-50714d75251b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37461
81288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.3746181288
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.4152280451
Short name T174
Test name
Test status
Simulation time 8410563446 ps
CPU time 11.3 seconds
Started May 21 01:11:03 PM PDT 24
Finished May 21 01:11:16 PM PDT 24
Peak memory 205348 kb
Host smart-e3cab2bd-b0a6-4174-9749-3a067d4f6af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41522
80451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.4152280451
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.3848864246
Short name T153
Test name
Test status
Simulation time 8414516657 ps
CPU time 12.15 seconds
Started May 21 01:09:46 PM PDT 24
Finished May 21 01:10:00 PM PDT 24
Peak memory 205324 kb
Host smart-1f10c29d-44ad-4b31-9a41-81d68f7d66bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38488
64246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.3848864246
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2352682877
Short name T1046
Test name
Test status
Simulation time 8424382710 ps
CPU time 12.6 seconds
Started May 21 01:04:19 PM PDT 24
Finished May 21 01:04:32 PM PDT 24
Peak memory 205328 kb
Host smart-10035582-6002-4665-be38-37aa985b6428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23526
82877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2352682877
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3539269699
Short name T350
Test name
Test status
Simulation time 8378579729 ps
CPU time 10.46 seconds
Started May 21 01:06:46 PM PDT 24
Finished May 21 01:06:57 PM PDT 24
Peak memory 205276 kb
Host smart-65fe390e-2a07-4e96-a25a-ef7fd1d7d93e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35392
69699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3539269699
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.2695973188
Short name T47
Test name
Test status
Simulation time 8465764073 ps
CPU time 10.92 seconds
Started May 21 01:07:12 PM PDT 24
Finished May 21 01:07:25 PM PDT 24
Peak memory 205444 kb
Host smart-f09e0b07-1e1e-4877-b2a8-b83aa5aa2899
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2695973188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.2695973188
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.2850761129
Short name T42
Test name
Test status
Simulation time 8399992747 ps
CPU time 11.72 seconds
Started May 21 01:07:34 PM PDT 24
Finished May 21 01:07:47 PM PDT 24
Peak memory 205280 kb
Host smart-807756bd-9493-47bc-a1ec-13e361d8beb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28507
61129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.2850761129
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_smoke.863424912
Short name T988
Test name
Test status
Simulation time 8446694643 ps
CPU time 12.42 seconds
Started May 21 01:09:37 PM PDT 24
Finished May 21 01:09:51 PM PDT 24
Peak memory 205264 kb
Host smart-d8983c83-cf77-4fc6-8819-678e40a55a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86342
4912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.863424912
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.354908557
Short name T125
Test name
Test status
Simulation time 8401533580 ps
CPU time 13.38 seconds
Started May 21 01:04:14 PM PDT 24
Finished May 21 01:04:28 PM PDT 24
Peak memory 205404 kb
Host smart-64fc5a0f-bb21-48ca-89fd-a4b2dcd2e28b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35490
8557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.354908557
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.524845328
Short name T144
Test name
Test status
Simulation time 8413225677 ps
CPU time 13.27 seconds
Started May 21 01:04:21 PM PDT 24
Finished May 21 01:04:35 PM PDT 24
Peak memory 205364 kb
Host smart-1a7751fe-9dea-4f6b-ba9e-d98ec420e1df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52484
5328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.524845328
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.1394124667
Short name T379
Test name
Test status
Simulation time 8400716412 ps
CPU time 13.23 seconds
Started May 21 01:04:44 PM PDT 24
Finished May 21 01:04:58 PM PDT 24
Peak memory 205280 kb
Host smart-69f73179-3174-4962-b46c-cafd7950370a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13941
24667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.1394124667
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.645347192
Short name T1589
Test name
Test status
Simulation time 8430366371 ps
CPU time 12.53 seconds
Started May 21 01:06:45 PM PDT 24
Finished May 21 01:06:58 PM PDT 24
Peak memory 205328 kb
Host smart-e11ee700-aa7f-4e7c-8b01-73ea273d588e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64534
7192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.645347192
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.3144531166
Short name T100
Test name
Test status
Simulation time 8372652100 ps
CPU time 11.58 seconds
Started May 21 01:07:01 PM PDT 24
Finished May 21 01:07:15 PM PDT 24
Peak memory 205316 kb
Host smart-179f3c3b-23dd-4f22-8b5a-de78f3805cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31445
31166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.3144531166
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.1386055593
Short name T129
Test name
Test status
Simulation time 8437817566 ps
CPU time 11.67 seconds
Started May 21 01:07:05 PM PDT 24
Finished May 21 01:07:19 PM PDT 24
Peak memory 205272 kb
Host smart-dcf6c560-c7e6-49a2-ab42-e24b13aebb4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13860
55593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1386055593
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.912592184
Short name T127
Test name
Test status
Simulation time 8401744911 ps
CPU time 12.9 seconds
Started May 21 01:07:16 PM PDT 24
Finished May 21 01:07:30 PM PDT 24
Peak memory 205240 kb
Host smart-034cb95a-53b8-4f19-b13e-13959878457e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91259
2184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.912592184
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.300680130
Short name T1555
Test name
Test status
Simulation time 8418315551 ps
CPU time 12.91 seconds
Started May 21 01:07:34 PM PDT 24
Finished May 21 01:07:48 PM PDT 24
Peak memory 205348 kb
Host smart-7da818f0-e673-4fb0-a6b6-cd543009a3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30068
0130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.300680130
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3311473563
Short name T149
Test name
Test status
Simulation time 8417460511 ps
CPU time 11.25 seconds
Started May 21 01:07:43 PM PDT 24
Finished May 21 01:07:56 PM PDT 24
Peak memory 205300 kb
Host smart-b080c6ab-b5b8-4cdb-ad67-c50166dd95f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33114
73563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3311473563
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.525238870
Short name T115
Test name
Test status
Simulation time 21913040190 ps
CPU time 43.07 seconds
Started May 21 01:07:43 PM PDT 24
Finished May 21 01:08:27 PM PDT 24
Peak memory 205364 kb
Host smart-d3315776-0ce9-4330-9bab-576a1ba9b3c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52523
8870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.525238870
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.1512433478
Short name T1452
Test name
Test status
Simulation time 8426505870 ps
CPU time 11.29 seconds
Started May 21 01:07:49 PM PDT 24
Finished May 21 01:08:01 PM PDT 24
Peak memory 205376 kb
Host smart-f7895788-f8a8-438d-ada0-e02613b59e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15124
33478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.1512433478
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.605266307
Short name T132
Test name
Test status
Simulation time 8408408433 ps
CPU time 11.67 seconds
Started May 21 01:05:04 PM PDT 24
Finished May 21 01:05:18 PM PDT 24
Peak memory 205364 kb
Host smart-0753636c-7472-499a-8d52-f385a504b274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60526
6307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.605266307
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.1661455888
Short name T39
Test name
Test status
Simulation time 8423304255 ps
CPU time 13.89 seconds
Started May 21 01:08:34 PM PDT 24
Finished May 21 01:08:49 PM PDT 24
Peak memory 205340 kb
Host smart-b2e8dedb-c5c2-4ba1-89d2-f5073f53784c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16614
55888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.1661455888
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.2978159708
Short name T140
Test name
Test status
Simulation time 8471910991 ps
CPU time 11.84 seconds
Started May 21 01:08:43 PM PDT 24
Finished May 21 01:08:56 PM PDT 24
Peak memory 205348 kb
Host smart-d572ffdd-d8f0-49c6-b2cd-e7b70e4c072c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29781
59708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.2978159708
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.3959166985
Short name T197
Test name
Test status
Simulation time 8435151084 ps
CPU time 13.16 seconds
Started May 21 01:09:04 PM PDT 24
Finished May 21 01:09:19 PM PDT 24
Peak memory 205404 kb
Host smart-a5782070-a829-4d9d-af85-d5f9b2e69f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39591
66985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.3959166985
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.1558925953
Short name T200
Test name
Test status
Simulation time 8410581721 ps
CPU time 12.9 seconds
Started May 21 01:09:30 PM PDT 24
Finished May 21 01:09:45 PM PDT 24
Peak memory 205328 kb
Host smart-4300d893-77dc-4552-86c0-77233b12721c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15589
25953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.1558925953
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.2765360164
Short name T148
Test name
Test status
Simulation time 8440225315 ps
CPU time 11.09 seconds
Started May 21 01:09:57 PM PDT 24
Finished May 21 01:10:10 PM PDT 24
Peak memory 205372 kb
Host smart-69db1f6d-0843-4943-8f52-4011a9ea984d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27653
60164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2765360164
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1465839696
Short name T123
Test name
Test status
Simulation time 8435051925 ps
CPU time 11.72 seconds
Started May 21 01:10:24 PM PDT 24
Finished May 21 01:10:38 PM PDT 24
Peak memory 205324 kb
Host smart-8bac3179-57a7-421b-a65a-1b4faf429f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14658
39696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1465839696
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1210210715
Short name T1786
Test name
Test status
Simulation time 370357703 ps
CPU time 3.66 seconds
Started May 21 02:07:09 PM PDT 24
Finished May 21 02:07:15 PM PDT 24
Peak memory 204548 kb
Host smart-84edf50c-a7af-410d-a221-06c4df5dc04e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1210210715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1210210715
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.16991619
Short name T238
Test name
Test status
Simulation time 729922228 ps
CPU time 4.57 seconds
Started May 21 02:07:07 PM PDT 24
Finished May 21 02:07:14 PM PDT 24
Peak memory 204476 kb
Host smart-c950adc2-71a7-4a61-ad5e-412fd6614b54
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=16991619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.16991619
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3927307613
Short name T1734
Test name
Test status
Simulation time 149459409 ps
CPU time 1.73 seconds
Started May 21 02:07:09 PM PDT 24
Finished May 21 02:07:13 PM PDT 24
Peak memory 212836 kb
Host smart-f660e211-4125-473f-8461-b4eaec639d3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927307613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.3927307613
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2490788064
Short name T1749
Test name
Test status
Simulation time 60730821 ps
CPU time 0.98 seconds
Started May 21 02:07:10 PM PDT 24
Finished May 21 02:07:12 PM PDT 24
Peak memory 204600 kb
Host smart-3b73f608-41e9-4056-8cd4-174054ad9feb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2490788064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2490788064
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.617235885
Short name T1805
Test name
Test status
Simulation time 52590951 ps
CPU time 1.31 seconds
Started May 21 02:07:09 PM PDT 24
Finished May 21 02:07:12 PM PDT 24
Peak memory 212840 kb
Host smart-a6499b66-65f7-4efb-af64-4b2cdff41e9b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=617235885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.617235885
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3261530043
Short name T1764
Test name
Test status
Simulation time 104279687 ps
CPU time 2.28 seconds
Started May 21 02:07:07 PM PDT 24
Finished May 21 02:07:12 PM PDT 24
Peak memory 204528 kb
Host smart-0785043d-4f12-4aa4-8a8c-e2b75b52f53e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3261530043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3261530043
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3836788669
Short name T1806
Test name
Test status
Simulation time 84401169 ps
CPU time 1.07 seconds
Started May 21 02:07:10 PM PDT 24
Finished May 21 02:07:12 PM PDT 24
Peak memory 204588 kb
Host smart-061c1bab-1ba8-4d63-83e0-0250221e3c89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3836788669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.3836788669
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2483524732
Short name T1811
Test name
Test status
Simulation time 229494186 ps
CPU time 2.22 seconds
Started May 21 02:07:08 PM PDT 24
Finished May 21 02:07:12 PM PDT 24
Peak memory 204700 kb
Host smart-fe34f3de-0d33-4a22-816b-79800c0c3b8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2483524732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2483524732
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3475249409
Short name T1832
Test name
Test status
Simulation time 563058325 ps
CPU time 3.15 seconds
Started May 21 02:07:08 PM PDT 24
Finished May 21 02:07:13 PM PDT 24
Peak memory 204684 kb
Host smart-acbd729a-d73d-40bf-869f-d9edeaf5d55b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3475249409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.3475249409
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1351508692
Short name T1802
Test name
Test status
Simulation time 177663688 ps
CPU time 3.52 seconds
Started May 21 02:07:14 PM PDT 24
Finished May 21 02:07:19 PM PDT 24
Peak memory 204540 kb
Host smart-aba153c5-27e0-4928-95ee-402264d272ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1351508692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1351508692
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3607013928
Short name T1742
Test name
Test status
Simulation time 405611048 ps
CPU time 4.55 seconds
Started May 21 02:07:14 PM PDT 24
Finished May 21 02:07:20 PM PDT 24
Peak memory 204588 kb
Host smart-d7134d9f-c96d-4844-895a-a1f3df37e254
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3607013928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.3607013928
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1332759903
Short name T1781
Test name
Test status
Simulation time 39584549 ps
CPU time 0.79 seconds
Started May 21 02:07:16 PM PDT 24
Finished May 21 02:07:19 PM PDT 24
Peak memory 204232 kb
Host smart-88c1cc41-8412-4958-952e-eed422d7a5c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1332759903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1332759903
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1007328471
Short name T119
Test name
Test status
Simulation time 82286547 ps
CPU time 1.28 seconds
Started May 21 02:07:14 PM PDT 24
Finished May 21 02:07:17 PM PDT 24
Peak memory 221048 kb
Host smart-bad7fc7f-ef22-4151-a686-94a05e37a456
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007328471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.1007328471
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2592077306
Short name T1752
Test name
Test status
Simulation time 41445933 ps
CPU time 0.94 seconds
Started May 21 02:07:17 PM PDT 24
Finished May 21 02:07:20 PM PDT 24
Peak memory 204316 kb
Host smart-84c7f1c7-ce3e-4ab1-9937-6e5f643a68b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2592077306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2592077306
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3985068798
Short name T251
Test name
Test status
Simulation time 30265372 ps
CPU time 0.65 seconds
Started May 21 02:07:14 PM PDT 24
Finished May 21 02:07:16 PM PDT 24
Peak memory 203872 kb
Host smart-ae1155e8-b398-48dd-bbc4-d759639173ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3985068798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3985068798
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.742568000
Short name T1829
Test name
Test status
Simulation time 68865617 ps
CPU time 2.24 seconds
Started May 21 02:07:16 PM PDT 24
Finished May 21 02:07:20 PM PDT 24
Peak memory 212684 kb
Host smart-13dcdfe3-632e-4c9d-b602-900791d6fbf6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=742568000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.742568000
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1470160384
Short name T1747
Test name
Test status
Simulation time 125021793 ps
CPU time 2.43 seconds
Started May 21 02:07:15 PM PDT 24
Finished May 21 02:07:19 PM PDT 24
Peak memory 204516 kb
Host smart-c49f9042-c969-4ae9-855d-d261422ebb1a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1470160384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1470160384
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4131316374
Short name T121
Test name
Test status
Simulation time 51275691 ps
CPU time 1.08 seconds
Started May 21 02:07:15 PM PDT 24
Finished May 21 02:07:18 PM PDT 24
Peak memory 204528 kb
Host smart-54fa8d60-9d0f-45e8-ab9a-d82f2754de1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4131316374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.4131316374
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3323001056
Short name T1753
Test name
Test status
Simulation time 307528451 ps
CPU time 3.24 seconds
Started May 21 02:07:14 PM PDT 24
Finished May 21 02:07:18 PM PDT 24
Peak memory 204588 kb
Host smart-b9864b3e-a593-41b8-a8f7-97f0acf8ac9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3323001056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3323001056
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2187773102
Short name T1757
Test name
Test status
Simulation time 331871944 ps
CPU time 2.46 seconds
Started May 21 02:07:21 PM PDT 24
Finished May 21 02:07:26 PM PDT 24
Peak memory 204624 kb
Host smart-305d8847-ddb3-4a58-badc-014f5c146e9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2187773102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.2187773102
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3274792644
Short name T1801
Test name
Test status
Simulation time 80822801 ps
CPU time 1.16 seconds
Started May 21 02:07:26 PM PDT 24
Finished May 21 02:07:28 PM PDT 24
Peak memory 220828 kb
Host smart-492bb10a-9fbc-484f-a69a-67733424bad4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274792644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.3274792644
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.644252809
Short name T240
Test name
Test status
Simulation time 56388480 ps
CPU time 0.96 seconds
Started May 21 02:07:26 PM PDT 24
Finished May 21 02:07:28 PM PDT 24
Peak memory 204512 kb
Host smart-466a2e83-df81-4c19-bc7c-d60b5cfae7b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=644252809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.644252809
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.896149089
Short name T1765
Test name
Test status
Simulation time 38140482 ps
CPU time 0.69 seconds
Started May 21 02:07:28 PM PDT 24
Finished May 21 02:07:30 PM PDT 24
Peak memory 203864 kb
Host smart-d8183a40-053e-4b4c-a1c5-d4b2971c1625
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=896149089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.896149089
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2518066691
Short name T1751
Test name
Test status
Simulation time 132025911 ps
CPU time 1.16 seconds
Started May 21 02:07:29 PM PDT 24
Finished May 21 02:07:31 PM PDT 24
Peak memory 204588 kb
Host smart-30bc676a-0992-4f2b-ad2f-549ee30e202c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2518066691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2518066691
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2693201717
Short name T205
Test name
Test status
Simulation time 173078181 ps
CPU time 2.7 seconds
Started May 21 02:07:28 PM PDT 24
Finished May 21 02:07:32 PM PDT 24
Peak memory 213060 kb
Host smart-8d5ad5e3-6f69-4818-9926-9d0b6e9429a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693201717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2693201717
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3061779352
Short name T1760
Test name
Test status
Simulation time 45148047 ps
CPU time 0.98 seconds
Started May 21 02:07:28 PM PDT 24
Finished May 21 02:07:30 PM PDT 24
Peak memory 204508 kb
Host smart-88feb5c4-22ad-440f-9735-d844b55b2a34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3061779352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3061779352
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3990361471
Short name T257
Test name
Test status
Simulation time 31121946 ps
CPU time 0.66 seconds
Started May 21 02:07:25 PM PDT 24
Finished May 21 02:07:26 PM PDT 24
Peak memory 203876 kb
Host smart-98d12e08-3b1f-46a1-b9ed-fae52f3c316f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3990361471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3990361471
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1144225624
Short name T1794
Test name
Test status
Simulation time 114668794 ps
CPU time 1.23 seconds
Started May 21 02:07:26 PM PDT 24
Finished May 21 02:07:28 PM PDT 24
Peak memory 204572 kb
Host smart-00ffb141-4d92-4a66-9af0-e55016d7fb04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1144225624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.1144225624
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.852575269
Short name T218
Test name
Test status
Simulation time 135278623 ps
CPU time 2.54 seconds
Started May 21 02:07:32 PM PDT 24
Finished May 21 02:07:36 PM PDT 24
Peak memory 204640 kb
Host smart-2f18bba2-164b-46ea-8b61-8f2cc9f0e772
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=852575269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.852575269
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1198490269
Short name T118
Test name
Test status
Simulation time 127516940 ps
CPU time 2.36 seconds
Started May 21 02:07:36 PM PDT 24
Finished May 21 02:07:40 PM PDT 24
Peak memory 212952 kb
Host smart-701b556e-e64e-456b-a128-c6a66edb2c27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198490269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.1198490269
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1114388068
Short name T1772
Test name
Test status
Simulation time 30210005 ps
CPU time 0.86 seconds
Started May 21 02:07:33 PM PDT 24
Finished May 21 02:07:34 PM PDT 24
Peak memory 204304 kb
Host smart-b073e76a-86aa-40d7-87fd-810d268cdc8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1114388068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1114388068
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.174758777
Short name T1800
Test name
Test status
Simulation time 30996382 ps
CPU time 0.66 seconds
Started May 21 02:07:34 PM PDT 24
Finished May 21 02:07:37 PM PDT 24
Peak memory 203840 kb
Host smart-39d333ee-b55c-4957-b1d5-66b5e8679927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=174758777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.174758777
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3184990346
Short name T1830
Test name
Test status
Simulation time 113703317 ps
CPU time 1.21 seconds
Started May 21 02:07:33 PM PDT 24
Finished May 21 02:07:36 PM PDT 24
Peak memory 204552 kb
Host smart-431ba2b2-7a85-46a7-a1fc-506c4378d159
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3184990346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3184990346
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2338412369
Short name T1769
Test name
Test status
Simulation time 107649717 ps
CPU time 2.62 seconds
Started May 21 02:07:29 PM PDT 24
Finished May 21 02:07:32 PM PDT 24
Peak memory 204704 kb
Host smart-97dd5fca-8d12-404a-aa55-6e2fb5db7539
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2338412369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2338412369
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.585827729
Short name T1810
Test name
Test status
Simulation time 515924714 ps
CPU time 3.02 seconds
Started May 21 02:07:28 PM PDT 24
Finished May 21 02:07:32 PM PDT 24
Peak memory 204612 kb
Host smart-1bd21741-9fd5-454b-b59c-058454e82511
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=585827729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.585827729
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2777524899
Short name T76
Test name
Test status
Simulation time 115110474 ps
CPU time 1.43 seconds
Started May 21 02:07:33 PM PDT 24
Finished May 21 02:07:36 PM PDT 24
Peak memory 212880 kb
Host smart-a3f2f324-9eae-45fd-ae4a-236bb6678ddd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777524899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.2777524899
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.847225679
Short name T1758
Test name
Test status
Simulation time 98748734 ps
CPU time 1.17 seconds
Started May 21 02:07:33 PM PDT 24
Finished May 21 02:07:35 PM PDT 24
Peak memory 204492 kb
Host smart-9e67a69b-7521-419f-995c-deef9b01e72b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=847225679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.847225679
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.782531083
Short name T1825
Test name
Test status
Simulation time 92370405 ps
CPU time 2.82 seconds
Started May 21 02:07:35 PM PDT 24
Finished May 21 02:07:40 PM PDT 24
Peak memory 204668 kb
Host smart-19c20954-83a1-43ca-abcf-3c57a2ebdd93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=782531083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.782531083
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.717457392
Short name T1809
Test name
Test status
Simulation time 325844259 ps
CPU time 3.92 seconds
Started May 21 02:07:34 PM PDT 24
Finished May 21 02:07:40 PM PDT 24
Peak memory 204604 kb
Host smart-5b82ccea-5157-4a9c-8ee2-509b69f1b7db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=717457392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.717457392
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3742165611
Short name T206
Test name
Test status
Simulation time 136699056 ps
CPU time 1.97 seconds
Started May 21 02:07:36 PM PDT 24
Finished May 21 02:07:40 PM PDT 24
Peak memory 212892 kb
Host smart-ca36702b-8071-442d-b83b-0bb99926100e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742165611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.3742165611
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.682851442
Short name T1824
Test name
Test status
Simulation time 56515675 ps
CPU time 0.85 seconds
Started May 21 02:07:34 PM PDT 24
Finished May 21 02:07:35 PM PDT 24
Peak memory 204332 kb
Host smart-5d12bbae-ccdb-4e3f-89ec-9ba1cf9255e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=682851442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.682851442
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2765542934
Short name T243
Test name
Test status
Simulation time 84587337 ps
CPU time 1.15 seconds
Started May 21 02:07:38 PM PDT 24
Finished May 21 02:07:41 PM PDT 24
Peak memory 204572 kb
Host smart-1e4d22a5-a9a4-45a8-9b6e-a95d7598e97f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2765542934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2765542934
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2819918590
Short name T245
Test name
Test status
Simulation time 338426343 ps
CPU time 2.79 seconds
Started May 21 02:07:35 PM PDT 24
Finished May 21 02:07:40 PM PDT 24
Peak memory 204628 kb
Host smart-058fd3bd-b79e-40b9-b44c-1131680f7289
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2819918590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.2819918590
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1345911133
Short name T1784
Test name
Test status
Simulation time 87691483 ps
CPU time 2.74 seconds
Started May 21 02:07:38 PM PDT 24
Finished May 21 02:07:43 PM PDT 24
Peak memory 212892 kb
Host smart-770de256-8a00-4d00-b733-31c92a2d6f6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345911133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.1345911133
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1066380697
Short name T1761
Test name
Test status
Simulation time 79276183 ps
CPU time 1.04 seconds
Started May 21 02:07:36 PM PDT 24
Finished May 21 02:07:39 PM PDT 24
Peak memory 204488 kb
Host smart-db5bcbd2-7d4b-4836-b881-22771b3a7c73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1066380697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1066380697
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1841867731
Short name T1777
Test name
Test status
Simulation time 29698912 ps
CPU time 0.65 seconds
Started May 21 02:07:34 PM PDT 24
Finished May 21 02:07:37 PM PDT 24
Peak memory 203844 kb
Host smart-c823a39b-87be-4366-b932-f450b624129c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1841867731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1841867731
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.300479885
Short name T1793
Test name
Test status
Simulation time 193274669 ps
CPU time 1.51 seconds
Started May 21 02:07:34 PM PDT 24
Finished May 21 02:07:36 PM PDT 24
Peak memory 204648 kb
Host smart-89c72995-4a45-485b-af0e-aedb889969ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=300479885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.300479885
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3364950680
Short name T1759
Test name
Test status
Simulation time 190428186 ps
CPU time 2.59 seconds
Started May 21 02:07:35 PM PDT 24
Finished May 21 02:07:40 PM PDT 24
Peak memory 212860 kb
Host smart-e106e5fd-a67f-43f9-b4eb-0a518ef7ff9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3364950680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3364950680
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3613106574
Short name T208
Test name
Test status
Simulation time 195102849 ps
CPU time 2.39 seconds
Started May 21 02:07:36 PM PDT 24
Finished May 21 02:07:40 PM PDT 24
Peak memory 204600 kb
Host smart-7306b8ff-70d4-4655-b01d-c6226153a59f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3613106574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3613106574
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1964188059
Short name T1821
Test name
Test status
Simulation time 100767284 ps
CPU time 2.5 seconds
Started May 21 02:07:41 PM PDT 24
Finished May 21 02:07:46 PM PDT 24
Peak memory 212800 kb
Host smart-7ddd8dc6-9e87-4354-bd58-55c7ffb0216c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964188059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.1964188059
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.935042350
Short name T1754
Test name
Test status
Simulation time 52636341 ps
CPU time 0.81 seconds
Started May 21 02:07:38 PM PDT 24
Finished May 21 02:07:41 PM PDT 24
Peak memory 204316 kb
Host smart-58769da5-a04f-47a1-865e-8bb4e76f0c28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=935042350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.935042350
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1762940557
Short name T1755
Test name
Test status
Simulation time 37399906 ps
CPU time 0.68 seconds
Started May 21 02:07:38 PM PDT 24
Finished May 21 02:07:40 PM PDT 24
Peak memory 203860 kb
Host smart-7c998c96-1dc1-4259-8ed3-92a240871267
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1762940557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1762940557
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2024933382
Short name T1773
Test name
Test status
Simulation time 157943956 ps
CPU time 1.61 seconds
Started May 21 02:07:38 PM PDT 24
Finished May 21 02:07:42 PM PDT 24
Peak memory 204528 kb
Host smart-a2eb0a98-16c8-4888-9a5e-b6db3af5d7e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2024933382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.2024933382
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1971038809
Short name T209
Test name
Test status
Simulation time 151707794 ps
CPU time 2 seconds
Started May 21 02:07:35 PM PDT 24
Finished May 21 02:07:39 PM PDT 24
Peak memory 204656 kb
Host smart-19883131-55af-4e49-bcdc-bfe30dba06f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1971038809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1971038809
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3190642619
Short name T270
Test name
Test status
Simulation time 530306197 ps
CPU time 4.58 seconds
Started May 21 02:07:35 PM PDT 24
Finished May 21 02:07:42 PM PDT 24
Peak memory 204648 kb
Host smart-2c8e846e-ebb3-4438-9eab-eae1d1c33255
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3190642619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3190642619
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2434988986
Short name T1815
Test name
Test status
Simulation time 183506937 ps
CPU time 2.01 seconds
Started May 21 02:07:38 PM PDT 24
Finished May 21 02:07:42 PM PDT 24
Peak memory 212896 kb
Host smart-57ab1b27-88b7-40a7-b130-76bc4c331485
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434988986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.2434988986
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.419551239
Short name T117
Test name
Test status
Simulation time 33903711 ps
CPU time 0.8 seconds
Started May 21 02:07:40 PM PDT 24
Finished May 21 02:07:42 PM PDT 24
Peak memory 204356 kb
Host smart-1575b557-8a24-4bec-91b2-d864f7884ae8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=419551239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.419551239
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3284142159
Short name T259
Test name
Test status
Simulation time 38029949 ps
CPU time 0.67 seconds
Started May 21 02:07:46 PM PDT 24
Finished May 21 02:07:52 PM PDT 24
Peak memory 203780 kb
Host smart-2c873e8c-bdaa-477e-9755-fc5111a88464
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3284142159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.3284142159
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.613761039
Short name T1735
Test name
Test status
Simulation time 59875073 ps
CPU time 1.09 seconds
Started May 21 02:07:44 PM PDT 24
Finished May 21 02:07:49 PM PDT 24
Peak memory 203988 kb
Host smart-a2d90079-3242-4285-bdb9-ce08978f0c7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=613761039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.613761039
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2538779756
Short name T220
Test name
Test status
Simulation time 125272434 ps
CPU time 1.61 seconds
Started May 21 02:07:37 PM PDT 24
Finished May 21 02:07:40 PM PDT 24
Peak memory 204648 kb
Host smart-a34baf62-5170-4434-92fb-144b5dccd337
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2538779756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2538779756
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2050330629
Short name T247
Test name
Test status
Simulation time 103717502 ps
CPU time 1.3 seconds
Started May 21 02:07:44 PM PDT 24
Finished May 21 02:07:49 PM PDT 24
Peak memory 212824 kb
Host smart-e7c2a645-4975-4873-ae7d-e169ceb2dd14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050330629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2050330629
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1134822946
Short name T1828
Test name
Test status
Simulation time 52929412 ps
CPU time 0.88 seconds
Started May 21 02:07:44 PM PDT 24
Finished May 21 02:07:49 PM PDT 24
Peak memory 203700 kb
Host smart-9ea6c834-1d51-4412-96da-3d2dc467a842
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1134822946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1134822946
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2954457381
Short name T1787
Test name
Test status
Simulation time 53889943 ps
CPU time 0.66 seconds
Started May 21 02:07:37 PM PDT 24
Finished May 21 02:07:39 PM PDT 24
Peak memory 203832 kb
Host smart-7e948b28-dc48-45ae-8ac3-451af67b13d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2954457381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.2954457381
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2406754610
Short name T79
Test name
Test status
Simulation time 67986937 ps
CPU time 1.5 seconds
Started May 21 02:07:41 PM PDT 24
Finished May 21 02:07:44 PM PDT 24
Peak memory 204644 kb
Host smart-7f816edf-03b6-4564-9fff-bcea63d4aeff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2406754610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2406754610
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1085204258
Short name T221
Test name
Test status
Simulation time 109883122 ps
CPU time 2.55 seconds
Started May 21 02:07:42 PM PDT 24
Finished May 21 02:07:47 PM PDT 24
Peak memory 204612 kb
Host smart-be607406-2021-4436-b0e6-359aadbce84e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1085204258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1085204258
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1823781265
Short name T207
Test name
Test status
Simulation time 228069489 ps
CPU time 2.52 seconds
Started May 21 02:07:39 PM PDT 24
Finished May 21 02:07:43 PM PDT 24
Peak memory 204620 kb
Host smart-88cf8938-fc93-481c-87d6-f5b9857caac2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1823781265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1823781265
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2595526565
Short name T219
Test name
Test status
Simulation time 102627771 ps
CPU time 2.42 seconds
Started May 21 02:07:45 PM PDT 24
Finished May 21 02:07:51 PM PDT 24
Peak memory 216228 kb
Host smart-10cc8d9e-623b-4809-9727-100a557c4481
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595526565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.2595526565
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2833882863
Short name T1779
Test name
Test status
Simulation time 60753322 ps
CPU time 1 seconds
Started May 21 02:07:41 PM PDT 24
Finished May 21 02:07:44 PM PDT 24
Peak memory 204540 kb
Host smart-8debdc50-7205-4087-a66c-fe96e60438af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2833882863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2833882863
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.4172435748
Short name T1745
Test name
Test status
Simulation time 46087664 ps
CPU time 0.73 seconds
Started May 21 02:07:39 PM PDT 24
Finished May 21 02:07:42 PM PDT 24
Peak memory 203912 kb
Host smart-3fe315a0-908d-45b1-84d0-7e8db1b69d20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4172435748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.4172435748
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1792828731
Short name T1744
Test name
Test status
Simulation time 63992410 ps
CPU time 1.51 seconds
Started May 21 02:07:41 PM PDT 24
Finished May 21 02:07:45 PM PDT 24
Peak memory 204600 kb
Host smart-56d71716-72a6-4e9b-94fe-bfc5ff6c566a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1792828731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.1792828731
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3954530010
Short name T215
Test name
Test status
Simulation time 308195714 ps
CPU time 3.32 seconds
Started May 21 02:07:39 PM PDT 24
Finished May 21 02:07:44 PM PDT 24
Peak memory 204640 kb
Host smart-70ed6873-3131-43a3-8811-716a19fe7dbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3954530010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3954530010
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3206096320
Short name T1778
Test name
Test status
Simulation time 105227278 ps
CPU time 3.41 seconds
Started May 21 02:07:15 PM PDT 24
Finished May 21 02:07:20 PM PDT 24
Peak memory 204532 kb
Host smart-aaeac7c2-4c84-47c9-b53a-58ca7dca065b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3206096320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3206096320
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.4257012310
Short name T1795
Test name
Test status
Simulation time 700651247 ps
CPU time 4.31 seconds
Started May 21 02:07:15 PM PDT 24
Finished May 21 02:07:21 PM PDT 24
Peak memory 204532 kb
Host smart-653071cb-dd59-42dc-8655-b841bcc73270
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4257012310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.4257012310
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.414775754
Short name T235
Test name
Test status
Simulation time 44728566 ps
CPU time 0.78 seconds
Started May 21 02:07:15 PM PDT 24
Finished May 21 02:07:17 PM PDT 24
Peak memory 204324 kb
Host smart-18b87109-9f5c-4a81-8f4b-606da7614a59
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=414775754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.414775754
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3561650788
Short name T1768
Test name
Test status
Simulation time 156889579 ps
CPU time 2.18 seconds
Started May 21 02:07:16 PM PDT 24
Finished May 21 02:07:20 PM PDT 24
Peak memory 212760 kb
Host smart-dad5cb92-acbb-4596-9dc1-2d39ddef07eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561650788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3561650788
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2814502938
Short name T237
Test name
Test status
Simulation time 38997405 ps
CPU time 0.94 seconds
Started May 21 02:07:14 PM PDT 24
Finished May 21 02:07:16 PM PDT 24
Peak memory 204532 kb
Host smart-363cd282-e897-4262-bfa4-85a1fc70fb0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2814502938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2814502938
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3069960135
Short name T1788
Test name
Test status
Simulation time 47594539 ps
CPU time 0.68 seconds
Started May 21 02:07:15 PM PDT 24
Finished May 21 02:07:17 PM PDT 24
Peak memory 203856 kb
Host smart-e4dbf7ec-5bc8-4279-a249-52b7191c3640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3069960135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3069960135
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1052891183
Short name T236
Test name
Test status
Simulation time 157950908 ps
CPU time 2.38 seconds
Started May 21 02:07:21 PM PDT 24
Finished May 21 02:07:26 PM PDT 24
Peak memory 212808 kb
Host smart-ba3a031b-c518-4d45-ada6-42ae3d1e9b9f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1052891183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1052891183
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3258075081
Short name T1739
Test name
Test status
Simulation time 92110169 ps
CPU time 2.27 seconds
Started May 21 02:07:16 PM PDT 24
Finished May 21 02:07:20 PM PDT 24
Peak memory 204524 kb
Host smart-6f80de6b-fb29-438b-b5a3-93720188ed4a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3258075081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3258075081
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.706116880
Short name T1738
Test name
Test status
Simulation time 89715676 ps
CPU time 1.58 seconds
Started May 21 02:07:17 PM PDT 24
Finished May 21 02:07:20 PM PDT 24
Peak memory 204440 kb
Host smart-412c8429-b7e0-43c7-94d2-a4c47c97c037
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=706116880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.706116880
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2199234976
Short name T1762
Test name
Test status
Simulation time 85579324 ps
CPU time 1.63 seconds
Started May 21 02:07:15 PM PDT 24
Finished May 21 02:07:18 PM PDT 24
Peak memory 204688 kb
Host smart-79f86337-81dd-430a-ac7c-8f25820efce4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2199234976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2199234976
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1452865593
Short name T265
Test name
Test status
Simulation time 565951683 ps
CPU time 2.71 seconds
Started May 21 02:07:21 PM PDT 24
Finished May 21 02:07:26 PM PDT 24
Peak memory 204548 kb
Host smart-9cf94083-d018-47a5-853f-388b4c61091a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1452865593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1452865593
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3582651186
Short name T1737
Test name
Test status
Simulation time 79639123 ps
CPU time 0.7 seconds
Started May 21 02:07:43 PM PDT 24
Finished May 21 02:07:46 PM PDT 24
Peak memory 203852 kb
Host smart-8b555c7c-4dc2-4ec5-a35e-15cc97ffb34a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3582651186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3582651186
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.4002506637
Short name T253
Test name
Test status
Simulation time 66421718 ps
CPU time 0.75 seconds
Started May 21 02:07:42 PM PDT 24
Finished May 21 02:07:44 PM PDT 24
Peak memory 203764 kb
Host smart-a4d5151e-9d7e-4d6c-b8e9-19d7132fb6c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4002506637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.4002506637
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3412443708
Short name T1822
Test name
Test status
Simulation time 36121513 ps
CPU time 0.67 seconds
Started May 21 02:07:40 PM PDT 24
Finished May 21 02:07:42 PM PDT 24
Peak memory 203936 kb
Host smart-3edc167b-2b7d-4dd4-b483-9e4fa4b6b5e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3412443708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.3412443708
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.588661207
Short name T256
Test name
Test status
Simulation time 26671387 ps
CPU time 0.67 seconds
Started May 21 02:07:46 PM PDT 24
Finished May 21 02:07:52 PM PDT 24
Peak memory 203872 kb
Host smart-e47c4f37-e5f2-44ee-a392-66d86ce888e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=588661207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.588661207
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3862839365
Short name T261
Test name
Test status
Simulation time 67930078 ps
CPU time 0.75 seconds
Started May 21 02:07:42 PM PDT 24
Finished May 21 02:07:45 PM PDT 24
Peak memory 203852 kb
Host smart-9811a2d9-4298-436f-a2d0-f91290f9d39f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3862839365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3862839365
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1422580356
Short name T1816
Test name
Test status
Simulation time 35702147 ps
CPU time 0.67 seconds
Started May 21 02:07:38 PM PDT 24
Finished May 21 02:07:41 PM PDT 24
Peak memory 203944 kb
Host smart-1e507566-31ca-4ae0-b4eb-43ebcc89a848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1422580356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1422580356
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1413922993
Short name T1748
Test name
Test status
Simulation time 34534213 ps
CPU time 0.65 seconds
Started May 21 02:07:37 PM PDT 24
Finished May 21 02:07:40 PM PDT 24
Peak memory 203808 kb
Host smart-d9484b4c-6a4d-450e-9c2e-ca962b7654fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1413922993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1413922993
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3438328674
Short name T1796
Test name
Test status
Simulation time 31930500 ps
CPU time 0.65 seconds
Started May 21 02:07:45 PM PDT 24
Finished May 21 02:07:50 PM PDT 24
Peak memory 203780 kb
Host smart-cdb18606-468f-48e1-95a3-30de2ca34f64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3438328674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3438328674
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.684840593
Short name T1823
Test name
Test status
Simulation time 27505584 ps
CPU time 0.65 seconds
Started May 21 02:07:41 PM PDT 24
Finished May 21 02:07:44 PM PDT 24
Peak memory 204104 kb
Host smart-7d5a179b-77ea-4b65-9442-bbc2d28833e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=684840593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.684840593
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2807592854
Short name T1741
Test name
Test status
Simulation time 29268695 ps
CPU time 0.66 seconds
Started May 21 02:07:45 PM PDT 24
Finished May 21 02:07:51 PM PDT 24
Peak memory 203936 kb
Host smart-3d7e90a2-6746-41ac-9eda-5eb038d969e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2807592854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2807592854
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2382262445
Short name T232
Test name
Test status
Simulation time 364494134 ps
CPU time 3.71 seconds
Started May 21 02:07:21 PM PDT 24
Finished May 21 02:07:26 PM PDT 24
Peak memory 204504 kb
Host smart-eae5d610-e103-4347-b7fc-3f049d5d4c8f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2382262445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2382262445
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1467029298
Short name T1790
Test name
Test status
Simulation time 1023120823 ps
CPU time 8.42 seconds
Started May 21 02:07:13 PM PDT 24
Finished May 21 02:07:23 PM PDT 24
Peak memory 204484 kb
Host smart-13cc8a35-c328-498d-81d3-b918ddcfe814
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1467029298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1467029298
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1537425272
Short name T78
Test name
Test status
Simulation time 78563185 ps
CPU time 0.79 seconds
Started May 21 02:07:17 PM PDT 24
Finished May 21 02:07:19 PM PDT 24
Peak memory 204332 kb
Host smart-98a80467-d0a6-42ba-8e82-5b73cb322d63
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1537425272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1537425272
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.320278590
Short name T1782
Test name
Test status
Simulation time 165671440 ps
CPU time 1.85 seconds
Started May 21 02:07:21 PM PDT 24
Finished May 21 02:07:25 PM PDT 24
Peak memory 212884 kb
Host smart-86a1a3a1-6d6a-4900-96c0-ef6da1dd54a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320278590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev
_csr_mem_rw_with_rand_reset.320278590
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.432617990
Short name T234
Test name
Test status
Simulation time 41888525 ps
CPU time 1 seconds
Started May 21 02:07:21 PM PDT 24
Finished May 21 02:07:24 PM PDT 24
Peak memory 204484 kb
Host smart-0e9ab501-e5b7-477c-97e9-2f7517b9a106
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=432617990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.432617990
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1577224960
Short name T1812
Test name
Test status
Simulation time 45012384 ps
CPU time 0.69 seconds
Started May 21 02:07:13 PM PDT 24
Finished May 21 02:07:15 PM PDT 24
Peak memory 203900 kb
Host smart-6fbe98ae-85d4-4c89-bc1a-ff1bdcb8e50b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1577224960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1577224960
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1907912809
Short name T229
Test name
Test status
Simulation time 110250701 ps
CPU time 1.54 seconds
Started May 21 02:07:14 PM PDT 24
Finished May 21 02:07:17 PM PDT 24
Peak memory 212716 kb
Host smart-24c95381-8d13-4c57-8d83-746d95c259f1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1907912809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1907912809
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3993958409
Short name T1776
Test name
Test status
Simulation time 154989512 ps
CPU time 4.01 seconds
Started May 21 02:07:15 PM PDT 24
Finished May 21 02:07:20 PM PDT 24
Peak memory 204528 kb
Host smart-ebef401e-3e8d-4552-8a28-6b161ed6ecec
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3993958409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3993958409
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2376680128
Short name T1746
Test name
Test status
Simulation time 49724374 ps
CPU time 1.02 seconds
Started May 21 02:07:26 PM PDT 24
Finished May 21 02:07:29 PM PDT 24
Peak memory 204604 kb
Host smart-e5a7a670-137b-47ca-8cdc-cc5b9fa78c23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2376680128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.2376680128
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3221854346
Short name T1774
Test name
Test status
Simulation time 92787551 ps
CPU time 1.45 seconds
Started May 21 02:07:16 PM PDT 24
Finished May 21 02:07:19 PM PDT 24
Peak memory 204600 kb
Host smart-685268d1-fea3-4bd5-9b85-7bfa4383b671
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3221854346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3221854346
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.947724390
Short name T1827
Test name
Test status
Simulation time 777305848 ps
CPU time 4.53 seconds
Started May 21 02:07:14 PM PDT 24
Finished May 21 02:07:19 PM PDT 24
Peak memory 204624 kb
Host smart-64f8f46c-740b-48b4-8250-9aed4bf33866
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=947724390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.947724390
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2527007459
Short name T260
Test name
Test status
Simulation time 37005268 ps
CPU time 0.73 seconds
Started May 21 02:07:47 PM PDT 24
Finished May 21 02:07:55 PM PDT 24
Peak memory 204020 kb
Host smart-7a35b2cb-4e61-4195-92c2-045601cedec7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2527007459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2527007459
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3187719798
Short name T1789
Test name
Test status
Simulation time 40030288 ps
CPU time 0.69 seconds
Started May 21 02:07:46 PM PDT 24
Finished May 21 02:07:52 PM PDT 24
Peak memory 203968 kb
Host smart-4e5575ad-f1e5-4ee6-b9f3-562b7255b5ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3187719798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3187719798
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3167447129
Short name T86
Test name
Test status
Simulation time 59310290 ps
CPU time 0.69 seconds
Started May 21 02:07:46 PM PDT 24
Finished May 21 02:07:53 PM PDT 24
Peak memory 203860 kb
Host smart-58f441ae-bc7c-4dd5-a416-a705f01c7786
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3167447129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3167447129
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3734707057
Short name T1819
Test name
Test status
Simulation time 33114799 ps
CPU time 0.68 seconds
Started May 21 02:07:50 PM PDT 24
Finished May 21 02:07:57 PM PDT 24
Peak memory 203864 kb
Host smart-29c0ca5f-dbe5-4833-9aa5-73115699f797
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3734707057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3734707057
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2559793824
Short name T1785
Test name
Test status
Simulation time 39160156 ps
CPU time 0.66 seconds
Started May 21 02:07:45 PM PDT 24
Finished May 21 02:07:49 PM PDT 24
Peak memory 203788 kb
Host smart-fa4ae3e0-2067-419d-9d7d-b97508848721
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2559793824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2559793824
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2543594749
Short name T88
Test name
Test status
Simulation time 26620572 ps
CPU time 0.73 seconds
Started May 21 02:07:43 PM PDT 24
Finished May 21 02:07:46 PM PDT 24
Peak memory 203916 kb
Host smart-8862826e-75b0-402c-beaf-24fc386986bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2543594749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2543594749
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2830771121
Short name T262
Test name
Test status
Simulation time 28104263 ps
CPU time 0.66 seconds
Started May 21 02:07:44 PM PDT 24
Finished May 21 02:07:48 PM PDT 24
Peak memory 203888 kb
Host smart-7786c6a5-d020-4688-9c97-380dc8600a16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2830771121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2830771121
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1728265263
Short name T1763
Test name
Test status
Simulation time 34959693 ps
CPU time 0.69 seconds
Started May 21 02:07:45 PM PDT 24
Finished May 21 02:07:50 PM PDT 24
Peak memory 203960 kb
Host smart-44de3962-3fa5-44f4-a883-f47d123d8dd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1728265263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1728265263
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2304407834
Short name T82
Test name
Test status
Simulation time 127511526 ps
CPU time 3.19 seconds
Started May 21 02:07:21 PM PDT 24
Finished May 21 02:07:26 PM PDT 24
Peak memory 204556 kb
Host smart-f3244db2-74b9-4aac-8467-df93b6bedf26
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2304407834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2304407834
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3501491057
Short name T1817
Test name
Test status
Simulation time 471760097 ps
CPU time 4.63 seconds
Started May 21 02:07:20 PM PDT 24
Finished May 21 02:07:25 PM PDT 24
Peak memory 204564 kb
Host smart-631b2ee7-7e4b-461d-bd17-5d3363905a5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3501491057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3501491057
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3276298369
Short name T1783
Test name
Test status
Simulation time 60142667 ps
CPU time 0.83 seconds
Started May 21 02:07:22 PM PDT 24
Finished May 21 02:07:25 PM PDT 24
Peak memory 204300 kb
Host smart-e6a27e6e-25c7-4a78-860e-ad136b4b259e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3276298369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3276298369
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2472492930
Short name T120
Test name
Test status
Simulation time 141609038 ps
CPU time 1.96 seconds
Started May 21 02:07:22 PM PDT 24
Finished May 21 02:07:26 PM PDT 24
Peak memory 212728 kb
Host smart-58af972f-70a3-44bf-94f8-a57eb3ddd3f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472492930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.2472492930
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1529958705
Short name T241
Test name
Test status
Simulation time 54966337 ps
CPU time 0.8 seconds
Started May 21 02:07:20 PM PDT 24
Finished May 21 02:07:21 PM PDT 24
Peak memory 204332 kb
Host smart-c42feccb-914b-41c0-8705-000c97cef894
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1529958705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1529958705
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.638508975
Short name T1807
Test name
Test status
Simulation time 27998545 ps
CPU time 0.64 seconds
Started May 21 02:07:21 PM PDT 24
Finished May 21 02:07:24 PM PDT 24
Peak memory 203836 kb
Host smart-400fc1b5-3369-40d2-a4f0-bee422b6f706
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=638508975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.638508975
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3981541299
Short name T231
Test name
Test status
Simulation time 153810662 ps
CPU time 2.41 seconds
Started May 21 02:07:22 PM PDT 24
Finished May 21 02:07:26 PM PDT 24
Peak memory 212840 kb
Host smart-6220c2ec-486a-4884-b5be-4cba178e08f9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3981541299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3981541299
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2712752754
Short name T1808
Test name
Test status
Simulation time 329829702 ps
CPU time 2.68 seconds
Started May 21 02:07:21 PM PDT 24
Finished May 21 02:07:26 PM PDT 24
Peak memory 204560 kb
Host smart-ae613b29-f860-483b-95d2-a2625b55e2f5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2712752754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2712752754
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2150375926
Short name T246
Test name
Test status
Simulation time 190231732 ps
CPU time 1.78 seconds
Started May 21 02:07:23 PM PDT 24
Finished May 21 02:07:27 PM PDT 24
Peak memory 204692 kb
Host smart-3d4530bc-f78e-433e-a9a9-7a5fe285df0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2150375926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2150375926
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1305236434
Short name T1743
Test name
Test status
Simulation time 192077618 ps
CPU time 2.47 seconds
Started May 21 02:07:23 PM PDT 24
Finished May 21 02:07:27 PM PDT 24
Peak memory 204680 kb
Host smart-6b26138a-5d50-48f3-bebc-bbb7bd71278b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1305236434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1305236434
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1975216600
Short name T210
Test name
Test status
Simulation time 991050327 ps
CPU time 5.57 seconds
Started May 21 02:07:21 PM PDT 24
Finished May 21 02:07:28 PM PDT 24
Peak memory 204624 kb
Host smart-2a140345-4783-4f33-badc-5816badd98a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1975216600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1975216600
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3079021756
Short name T1775
Test name
Test status
Simulation time 44226250 ps
CPU time 0.7 seconds
Started May 21 02:07:45 PM PDT 24
Finished May 21 02:07:51 PM PDT 24
Peak memory 203776 kb
Host smart-0cdba326-640a-4a30-855c-075156f20266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3079021756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3079021756
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2181314187
Short name T1736
Test name
Test status
Simulation time 56064385 ps
CPU time 0.71 seconds
Started May 21 02:07:48 PM PDT 24
Finished May 21 02:07:55 PM PDT 24
Peak memory 203912 kb
Host smart-2790c7b2-b620-4fdc-b025-46fe2e5ca131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2181314187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2181314187
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.500955692
Short name T249
Test name
Test status
Simulation time 62429513 ps
CPU time 0.71 seconds
Started May 21 02:07:45 PM PDT 24
Finished May 21 02:07:51 PM PDT 24
Peak memory 203772 kb
Host smart-95fda3dc-566b-4a74-8259-57073b9de7f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=500955692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.500955692
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3577763190
Short name T255
Test name
Test status
Simulation time 71179783 ps
CPU time 0.71 seconds
Started May 21 02:07:46 PM PDT 24
Finished May 21 02:07:53 PM PDT 24
Peak memory 204016 kb
Host smart-3bd48034-2f25-438a-9ed9-c887dd6b4af1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3577763190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3577763190
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2520869146
Short name T1826
Test name
Test status
Simulation time 42739208 ps
CPU time 0.7 seconds
Started May 21 02:07:47 PM PDT 24
Finished May 21 02:07:55 PM PDT 24
Peak memory 203908 kb
Host smart-6d9be949-1c06-4bee-b9b9-b09dadac5cd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2520869146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2520869146
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3682670612
Short name T85
Test name
Test status
Simulation time 33285295 ps
CPU time 0.66 seconds
Started May 21 02:07:47 PM PDT 24
Finished May 21 02:07:54 PM PDT 24
Peak memory 203848 kb
Host smart-c10d4cae-01f5-4d29-bd14-61354a5be69a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3682670612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.3682670612
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.77924231
Short name T1803
Test name
Test status
Simulation time 105131720 ps
CPU time 0.76 seconds
Started May 21 02:07:47 PM PDT 24
Finished May 21 02:07:54 PM PDT 24
Peak memory 203876 kb
Host smart-c0c50f48-623a-4002-875d-cf28f213fdfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=77924231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.77924231
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3568887638
Short name T1818
Test name
Test status
Simulation time 35789836 ps
CPU time 0.71 seconds
Started May 21 02:07:46 PM PDT 24
Finished May 21 02:07:52 PM PDT 24
Peak memory 203904 kb
Host smart-55c7aff9-3a1b-4f71-bb6d-3f6d1eba75cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3568887638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3568887638
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1088247737
Short name T87
Test name
Test status
Simulation time 39111520 ps
CPU time 0.68 seconds
Started May 21 02:07:45 PM PDT 24
Finished May 21 02:07:50 PM PDT 24
Peak memory 203860 kb
Host smart-eca94f5c-0df5-4f25-bb6c-e9f764085e82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1088247737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.1088247737
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2356872467
Short name T1831
Test name
Test status
Simulation time 68356556 ps
CPU time 0.68 seconds
Started May 21 02:07:47 PM PDT 24
Finished May 21 02:07:54 PM PDT 24
Peak memory 203828 kb
Host smart-a4177008-119e-4d64-8b5e-e02bbbc136c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2356872467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2356872467
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1475883539
Short name T1798
Test name
Test status
Simulation time 94884970 ps
CPU time 1.2 seconds
Started May 21 02:07:21 PM PDT 24
Finished May 21 02:07:24 PM PDT 24
Peak memory 212852 kb
Host smart-ea301090-1ee0-43b0-a92c-b29211a54b14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475883539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1475883539
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1275117421
Short name T239
Test name
Test status
Simulation time 38344706 ps
CPU time 0.87 seconds
Started May 21 02:07:24 PM PDT 24
Finished May 21 02:07:26 PM PDT 24
Peak memory 204324 kb
Host smart-24ef2b98-a583-4239-8657-bf7c3c12c7f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1275117421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1275117421
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1000930938
Short name T242
Test name
Test status
Simulation time 149402116 ps
CPU time 1.54 seconds
Started May 21 02:07:21 PM PDT 24
Finished May 21 02:07:25 PM PDT 24
Peak memory 204632 kb
Host smart-25ee18d5-e2eb-4adb-a743-0c1788513522
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1000930938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1000930938
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2305408203
Short name T1750
Test name
Test status
Simulation time 195208631 ps
CPU time 2.23 seconds
Started May 21 02:07:25 PM PDT 24
Finished May 21 02:07:29 PM PDT 24
Peak memory 204668 kb
Host smart-696ab6a5-4f21-4a4e-9adb-26f8ec12b543
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2305408203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2305408203
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2527787643
Short name T263
Test name
Test status
Simulation time 251285009 ps
CPU time 2.31 seconds
Started May 21 02:07:21 PM PDT 24
Finished May 21 02:07:24 PM PDT 24
Peak memory 204596 kb
Host smart-4c940ece-4fcc-483d-b2a4-b2e36352799f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2527787643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2527787643
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3105895667
Short name T1766
Test name
Test status
Simulation time 182592670 ps
CPU time 1.97 seconds
Started May 21 02:07:23 PM PDT 24
Finished May 21 02:07:26 PM PDT 24
Peak memory 212848 kb
Host smart-fec68964-6f0d-4f4a-89ca-94ef9037d868
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105895667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.3105895667
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4104625570
Short name T233
Test name
Test status
Simulation time 72730325 ps
CPU time 0.81 seconds
Started May 21 02:07:23 PM PDT 24
Finished May 21 02:07:25 PM PDT 24
Peak memory 204336 kb
Host smart-2bf46332-cae4-4760-b0a0-680d32e9c57e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4104625570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.4104625570
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.984361116
Short name T1770
Test name
Test status
Simulation time 47178537 ps
CPU time 0.71 seconds
Started May 21 02:07:21 PM PDT 24
Finished May 21 02:07:24 PM PDT 24
Peak memory 203868 kb
Host smart-3b89a51f-8d5c-495c-8ae3-09170f88ba46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=984361116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.984361116
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3098278935
Short name T1767
Test name
Test status
Simulation time 78759945 ps
CPU time 1.6 seconds
Started May 21 02:07:24 PM PDT 24
Finished May 21 02:07:27 PM PDT 24
Peak memory 204660 kb
Host smart-13c2219d-3e5e-4460-85ea-d340aebda2ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3098278935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3098278935
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2144245110
Short name T1797
Test name
Test status
Simulation time 162692902 ps
CPU time 2.43 seconds
Started May 21 02:07:22 PM PDT 24
Finished May 21 02:07:27 PM PDT 24
Peak memory 204640 kb
Host smart-d7c9cf5e-3d43-4c3e-8b74-dfe17aff19e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2144245110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2144245110
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2579481311
Short name T268
Test name
Test status
Simulation time 555202134 ps
CPU time 2.86 seconds
Started May 21 02:07:20 PM PDT 24
Finished May 21 02:07:24 PM PDT 24
Peak memory 204608 kb
Host smart-5f42421e-4ada-4880-bb75-fbc8d1866eb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2579481311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2579481311
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2122709239
Short name T1756
Test name
Test status
Simulation time 165259044 ps
CPU time 2.06 seconds
Started May 21 02:07:25 PM PDT 24
Finished May 21 02:07:29 PM PDT 24
Peak memory 216336 kb
Host smart-7a5f2f73-aea5-4582-9eb2-bd6a24108833
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122709239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.2122709239
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3632543868
Short name T1804
Test name
Test status
Simulation time 91257724 ps
CPU time 1 seconds
Started May 21 02:07:26 PM PDT 24
Finished May 21 02:07:28 PM PDT 24
Peak memory 204524 kb
Host smart-25b91366-7cdc-4261-a3b0-1c3b9ab908aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3632543868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3632543868
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.616246047
Short name T84
Test name
Test status
Simulation time 25722172 ps
CPU time 0.64 seconds
Started May 21 02:07:21 PM PDT 24
Finished May 21 02:07:23 PM PDT 24
Peak memory 203976 kb
Host smart-aaf1d418-f436-419a-b8e0-c3701d4ade4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=616246047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.616246047
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2588459189
Short name T1814
Test name
Test status
Simulation time 155077140 ps
CPU time 1.58 seconds
Started May 21 02:07:28 PM PDT 24
Finished May 21 02:07:31 PM PDT 24
Peak memory 204632 kb
Host smart-bee8baa3-8562-4c37-94a2-324c6ed3945a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2588459189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2588459189
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2757325314
Short name T216
Test name
Test status
Simulation time 209970453 ps
CPU time 2.86 seconds
Started May 21 02:07:22 PM PDT 24
Finished May 21 02:07:27 PM PDT 24
Peak memory 204612 kb
Host smart-2844c427-26f7-45a4-ae4b-61caa0b22b32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2757325314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2757325314
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2301404642
Short name T204
Test name
Test status
Simulation time 434369784 ps
CPU time 2.53 seconds
Started May 21 02:07:19 PM PDT 24
Finished May 21 02:07:23 PM PDT 24
Peak memory 204520 kb
Host smart-f40f8291-a051-47fc-af8d-862905e2532f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2301404642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.2301404642
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3745593371
Short name T1820
Test name
Test status
Simulation time 61471197 ps
CPU time 1.82 seconds
Started May 21 02:07:31 PM PDT 24
Finished May 21 02:07:33 PM PDT 24
Peak memory 212792 kb
Host smart-9f0493b7-bf8a-4a8d-bb1e-82c7940a93c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745593371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.3745593371
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2500209759
Short name T1780
Test name
Test status
Simulation time 101532579 ps
CPU time 1.06 seconds
Started May 21 02:07:27 PM PDT 24
Finished May 21 02:07:29 PM PDT 24
Peak memory 204564 kb
Host smart-cefcb86b-e5af-4bd8-b3d6-27123b563b6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2500209759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2500209759
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.133706789
Short name T1799
Test name
Test status
Simulation time 97375399 ps
CPU time 0.74 seconds
Started May 21 02:07:27 PM PDT 24
Finished May 21 02:07:29 PM PDT 24
Peak memory 203960 kb
Host smart-1a857622-0b52-4e57-858b-e7b7505001c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=133706789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.133706789
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3588703920
Short name T1771
Test name
Test status
Simulation time 63648282 ps
CPU time 1.15 seconds
Started May 21 02:07:26 PM PDT 24
Finished May 21 02:07:29 PM PDT 24
Peak memory 204696 kb
Host smart-0f919739-6ce0-408d-9de9-3e2e2cef9f85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3588703920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3588703920
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.310257304
Short name T217
Test name
Test status
Simulation time 99216766 ps
CPU time 1.41 seconds
Started May 21 02:07:28 PM PDT 24
Finished May 21 02:07:31 PM PDT 24
Peak memory 204640 kb
Host smart-99e2fdd8-6d08-497f-9905-e0208b7eb831
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=310257304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.310257304
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3185361039
Short name T266
Test name
Test status
Simulation time 304486914 ps
CPU time 2.49 seconds
Started May 21 02:07:32 PM PDT 24
Finished May 21 02:07:36 PM PDT 24
Peak memory 204660 kb
Host smart-9e31f330-a6ed-47e9-bc88-98d6e7602587
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3185361039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3185361039
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3310233362
Short name T222
Test name
Test status
Simulation time 245379578 ps
CPU time 1.71 seconds
Started May 21 02:07:28 PM PDT 24
Finished May 21 02:07:31 PM PDT 24
Peak memory 212884 kb
Host smart-a7d77b5e-2672-4793-a926-193785569518
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310233362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.3310233362
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2740399795
Short name T80
Test name
Test status
Simulation time 57552274 ps
CPU time 1 seconds
Started May 21 02:07:27 PM PDT 24
Finished May 21 02:07:30 PM PDT 24
Peak memory 204512 kb
Host smart-4724df9e-d529-4a44-8491-298280942c06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2740399795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2740399795
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2180293543
Short name T258
Test name
Test status
Simulation time 32821065 ps
CPU time 0.68 seconds
Started May 21 02:07:26 PM PDT 24
Finished May 21 02:07:28 PM PDT 24
Peak memory 203896 kb
Host smart-0addd1c4-a277-4634-bfd4-1ed881afbcf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2180293543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.2180293543
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1249171788
Short name T1813
Test name
Test status
Simulation time 157738066 ps
CPU time 1.59 seconds
Started May 21 02:07:28 PM PDT 24
Finished May 21 02:07:31 PM PDT 24
Peak memory 204628 kb
Host smart-a4b8d339-5a80-4a56-89ac-3bc46a11fdce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1249171788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1249171788
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.807138543
Short name T1792
Test name
Test status
Simulation time 63724732 ps
CPU time 1.98 seconds
Started May 21 02:07:27 PM PDT 24
Finished May 21 02:07:31 PM PDT 24
Peak memory 204668 kb
Host smart-03e6037c-512c-41b4-b6f2-a39742f20262
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=807138543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.807138543
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1375839792
Short name T223
Test name
Test status
Simulation time 517491475 ps
CPU time 3.11 seconds
Started May 21 02:07:33 PM PDT 24
Finished May 21 02:07:37 PM PDT 24
Peak memory 204524 kb
Host smart-cb777daa-7315-4251-8fee-0787e5d151e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1375839792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1375839792
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.3258273532
Short name T1516
Test name
Test status
Simulation time 8467779749 ps
CPU time 12.38 seconds
Started May 21 01:04:15 PM PDT 24
Finished May 21 01:04:29 PM PDT 24
Peak memory 205372 kb
Host smart-73c49c58-5e4a-4798-af17-b42f6aff7d20
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3258273532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.3258273532
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.2471499605
Short name T353
Test name
Test status
Simulation time 8380141092 ps
CPU time 12.7 seconds
Started May 21 01:04:18 PM PDT 24
Finished May 21 01:04:32 PM PDT 24
Peak memory 205316 kb
Host smart-8b2a1ae0-3022-4a2d-b2ab-aff8f72d4157
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2471499605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.2471499605
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.3537065775
Short name T461
Test name
Test status
Simulation time 8404849087 ps
CPU time 12.24 seconds
Started May 21 01:04:17 PM PDT 24
Finished May 21 01:04:31 PM PDT 24
Peak memory 205352 kb
Host smart-d4f75113-8d3a-4cef-a95c-afadd9c60dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35370
65775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.3537065775
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.1497884188
Short name T1543
Test name
Test status
Simulation time 8393196480 ps
CPU time 11.35 seconds
Started May 21 01:04:13 PM PDT 24
Finished May 21 01:04:25 PM PDT 24
Peak memory 205364 kb
Host smart-cc76d83c-b00f-4cf3-b4e3-b20ef3a9ca23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14978
84188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.1497884188
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.3310941205
Short name T664
Test name
Test status
Simulation time 8439988283 ps
CPU time 12.73 seconds
Started May 21 01:04:08 PM PDT 24
Finished May 21 01:04:22 PM PDT 24
Peak memory 205292 kb
Host smart-41287b68-846a-4a3c-a2a7-57f0f9e7a944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33109
41205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.3310941205
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.1543422355
Short name T1679
Test name
Test status
Simulation time 8386243289 ps
CPU time 11.06 seconds
Started May 21 01:04:19 PM PDT 24
Finished May 21 01:04:31 PM PDT 24
Peak memory 205404 kb
Host smart-c3c1cf94-574f-437d-a28b-480b884c96a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15434
22355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.1543422355
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.3370885067
Short name T1529
Test name
Test status
Simulation time 8376622058 ps
CPU time 13.14 seconds
Started May 21 01:04:10 PM PDT 24
Finished May 21 01:04:24 PM PDT 24
Peak memory 205388 kb
Host smart-c3f0d0f1-ee33-49e0-86c3-9ef6e680d0d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33708
85067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.3370885067
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.1425267499
Short name T448
Test name
Test status
Simulation time 8567376514 ps
CPU time 12.89 seconds
Started May 21 01:04:09 PM PDT 24
Finished May 21 01:04:24 PM PDT 24
Peak memory 205316 kb
Host smart-1df95f54-8d29-4643-b52c-5ba4fea00c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14252
67499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.1425267499
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.3089392351
Short name T513
Test name
Test status
Simulation time 8435045431 ps
CPU time 11.74 seconds
Started May 21 01:04:17 PM PDT 24
Finished May 21 01:04:30 PM PDT 24
Peak memory 205340 kb
Host smart-e2b1f4cb-e74f-4354-a2a0-cd0b7c370ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30893
92351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.3089392351
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.1861115903
Short name T758
Test name
Test status
Simulation time 8399821315 ps
CPU time 11.21 seconds
Started May 21 01:04:09 PM PDT 24
Finished May 21 01:04:22 PM PDT 24
Peak memory 205364 kb
Host smart-90f2e3a2-dea5-473e-960f-e669cf281aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18611
15903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.1861115903
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.127859829
Short name T806
Test name
Test status
Simulation time 8399603779 ps
CPU time 11.86 seconds
Started May 21 01:04:10 PM PDT 24
Finished May 21 01:04:23 PM PDT 24
Peak memory 205232 kb
Host smart-33119003-5c59-496b-91f2-494c68746470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12785
9829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.127859829
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.420338818
Short name T1063
Test name
Test status
Simulation time 11554846734 ps
CPU time 14.41 seconds
Started May 21 01:04:08 PM PDT 24
Finished May 21 01:04:22 PM PDT 24
Peak memory 205360 kb
Host smart-c05dd459-835b-4334-be48-5cf5fb5db09d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42033
8818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.420338818
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2106252797
Short name T789
Test name
Test status
Simulation time 8422169574 ps
CPU time 13.87 seconds
Started May 21 01:04:07 PM PDT 24
Finished May 21 01:04:21 PM PDT 24
Peak memory 205340 kb
Host smart-459929fc-6ea7-4a48-a706-b5d1be1d0da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21062
52797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2106252797
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2570429807
Short name T271
Test name
Test status
Simulation time 8388154221 ps
CPU time 12.08 seconds
Started May 21 01:04:18 PM PDT 24
Finished May 21 01:04:31 PM PDT 24
Peak memory 205460 kb
Host smart-237c9446-aefe-4224-a0ec-ee0fca5cb6c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25704
29807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2570429807
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.1984717469
Short name T971
Test name
Test status
Simulation time 8416639890 ps
CPU time 14.24 seconds
Started May 21 01:04:15 PM PDT 24
Finished May 21 01:04:30 PM PDT 24
Peak memory 205408 kb
Host smart-651768da-12f5-4412-af21-585ebb1d3642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19847
17469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.1984717469
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.4156962501
Short name T1082
Test name
Test status
Simulation time 8448825968 ps
CPU time 12.07 seconds
Started May 21 01:04:16 PM PDT 24
Finished May 21 01:04:29 PM PDT 24
Peak memory 205336 kb
Host smart-ae21d47e-d2b6-439b-9243-daadf3c2ea11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41569
62501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.4156962501
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2056674670
Short name T727
Test name
Test status
Simulation time 8391083616 ps
CPU time 14.21 seconds
Started May 21 01:04:17 PM PDT 24
Finished May 21 01:04:32 PM PDT 24
Peak memory 205376 kb
Host smart-ba982967-b708-4fb9-9e50-da65d70f65c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20566
74670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2056674670
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2157093101
Short name T552
Test name
Test status
Simulation time 8415982333 ps
CPU time 13.1 seconds
Started May 21 01:04:16 PM PDT 24
Finished May 21 01:04:31 PM PDT 24
Peak memory 205396 kb
Host smart-c95bd555-17aa-46b8-9bda-5239517db4bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21570
93101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.2157093101
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.383118714
Short name T783
Test name
Test status
Simulation time 8370855573 ps
CPU time 11.14 seconds
Started May 21 01:04:17 PM PDT 24
Finished May 21 01:04:30 PM PDT 24
Peak memory 205248 kb
Host smart-516fcba4-5efc-4ec2-8be1-c93a4bfcefac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38311
8714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.383118714
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.1681708518
Short name T1336
Test name
Test status
Simulation time 16617752835 ps
CPU time 29.55 seconds
Started May 21 01:04:17 PM PDT 24
Finished May 21 01:04:48 PM PDT 24
Peak memory 205424 kb
Host smart-9866e10d-829e-4a92-a3b8-91feabee680e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16817
08518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.1681708518
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.3813806977
Short name T734
Test name
Test status
Simulation time 8389544555 ps
CPU time 14.97 seconds
Started May 21 01:04:20 PM PDT 24
Finished May 21 01:04:35 PM PDT 24
Peak memory 205392 kb
Host smart-2ae441f8-dcbf-4ef4-800e-662c013708b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38138
06977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.3813806977
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1397010745
Short name T1401
Test name
Test status
Simulation time 8444729323 ps
CPU time 13.14 seconds
Started May 21 01:04:19 PM PDT 24
Finished May 21 01:04:33 PM PDT 24
Peak memory 205312 kb
Host smart-ffc49eb4-8833-47c2-82c8-661502c75800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13970
10745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1397010745
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.1615389701
Short name T1134
Test name
Test status
Simulation time 8422554272 ps
CPU time 12.22 seconds
Started May 21 01:04:21 PM PDT 24
Finished May 21 01:04:35 PM PDT 24
Peak memory 205276 kb
Host smart-c534eba4-9db6-4b03-acc9-06df922400a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16153
89701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.1615389701
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.89703762
Short name T640
Test name
Test status
Simulation time 8364772957 ps
CPU time 11.24 seconds
Started May 21 01:04:16 PM PDT 24
Finished May 21 01:04:29 PM PDT 24
Peak memory 205324 kb
Host smart-b33c4651-5e22-47e6-87b7-3514fa4b98fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89703
762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.89703762
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.535088380
Short name T74
Test name
Test status
Simulation time 565408769 ps
CPU time 1.51 seconds
Started May 21 01:04:19 PM PDT 24
Finished May 21 01:04:22 PM PDT 24
Peak memory 221216 kb
Host smart-0607cb87-33ea-4434-a808-7b7d7461ded4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=535088380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.535088380
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.715115173
Short name T643
Test name
Test status
Simulation time 8410042557 ps
CPU time 12.52 seconds
Started May 21 01:04:16 PM PDT 24
Finished May 21 01:04:29 PM PDT 24
Peak memory 205392 kb
Host smart-9501cb8b-9e3a-4aa7-9c1c-c39700c4ba70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71511
5173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.715115173
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.2917350836
Short name T695
Test name
Test status
Simulation time 8408291283 ps
CPU time 11.89 seconds
Started May 21 01:04:09 PM PDT 24
Finished May 21 01:04:22 PM PDT 24
Peak memory 205380 kb
Host smart-5aa99d23-da5d-42ae-a111-91ad1c20a895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29173
50836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.2917350836
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.3251009639
Short name T1068
Test name
Test status
Simulation time 8385500280 ps
CPU time 11.84 seconds
Started May 21 01:04:17 PM PDT 24
Finished May 21 01:04:30 PM PDT 24
Peak memory 205424 kb
Host smart-7eedc509-93ab-46f0-8731-74b6bb125e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32510
09639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.3251009639
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.902915995
Short name T561
Test name
Test status
Simulation time 8374317154 ps
CPU time 12.32 seconds
Started May 21 01:04:17 PM PDT 24
Finished May 21 01:04:31 PM PDT 24
Peak memory 205320 kb
Host smart-d6313ae4-c560-463a-a83b-e38211213c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90291
5995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.902915995
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.1532469435
Short name T1663
Test name
Test status
Simulation time 8467554196 ps
CPU time 13.93 seconds
Started May 21 01:04:52 PM PDT 24
Finished May 21 01:05:06 PM PDT 24
Peak memory 205316 kb
Host smart-b3de70db-536b-4bfc-b78b-ea0d9bae90bd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1532469435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.1532469435
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.3021922036
Short name T419
Test name
Test status
Simulation time 8385220945 ps
CPU time 13.05 seconds
Started May 21 01:04:51 PM PDT 24
Finished May 21 01:05:05 PM PDT 24
Peak memory 205420 kb
Host smart-8b895abe-93f6-4fcf-97a9-dd7e72514f0e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3021922036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.3021922036
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.2989281367
Short name T346
Test name
Test status
Simulation time 8455745776 ps
CPU time 11.86 seconds
Started May 21 01:04:51 PM PDT 24
Finished May 21 01:05:03 PM PDT 24
Peak memory 205408 kb
Host smart-2e1c8d93-34b6-462b-a882-b5b1f070a1d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29892
81367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.2989281367
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1133096316
Short name T110
Test name
Test status
Simulation time 8379905106 ps
CPU time 11.41 seconds
Started May 21 01:04:20 PM PDT 24
Finished May 21 01:04:32 PM PDT 24
Peak memory 205364 kb
Host smart-149cb8e5-df32-484a-8c8c-7ccea2ddd62c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11330
96316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1133096316
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.2656331642
Short name T832
Test name
Test status
Simulation time 9563327408 ps
CPU time 15.81 seconds
Started May 21 01:04:17 PM PDT 24
Finished May 21 01:04:34 PM PDT 24
Peak memory 205380 kb
Host smart-f511f1bb-549b-47d3-8041-f452433b708f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26563
31642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.2656331642
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.3979637634
Short name T866
Test name
Test status
Simulation time 8366623144 ps
CPU time 13.98 seconds
Started May 21 01:04:19 PM PDT 24
Finished May 21 01:04:34 PM PDT 24
Peak memory 205348 kb
Host smart-e4b3e687-a7bf-48fa-bf15-23870112ef59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39796
37634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.3979637634
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.2644391403
Short name T865
Test name
Test status
Simulation time 8388905234 ps
CPU time 10.69 seconds
Started May 21 01:04:18 PM PDT 24
Finished May 21 01:04:30 PM PDT 24
Peak memory 205272 kb
Host smart-0a2f7616-766e-41ae-a163-be12dce8f171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26443
91403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.2644391403
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.1558554920
Short name T1450
Test name
Test status
Simulation time 9156250931 ps
CPU time 15.33 seconds
Started May 21 01:04:16 PM PDT 24
Finished May 21 01:04:32 PM PDT 24
Peak memory 205280 kb
Host smart-632a7f8a-3974-4b18-afad-97dbedde618b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15585
54920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.1558554920
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.2686790861
Short name T898
Test name
Test status
Simulation time 8418833732 ps
CPU time 14.7 seconds
Started May 21 01:04:20 PM PDT 24
Finished May 21 01:04:35 PM PDT 24
Peak memory 205396 kb
Host smart-a1072cea-a85a-4195-906a-2c755ca10557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26867
90861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2686790861
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.19213942
Short name T936
Test name
Test status
Simulation time 8397264918 ps
CPU time 12.18 seconds
Started May 21 01:04:51 PM PDT 24
Finished May 21 01:05:04 PM PDT 24
Peak memory 205336 kb
Host smart-6bd1c6d0-f69a-48c1-9668-61df22360046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19213
942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.19213942
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3964848591
Short name T910
Test name
Test status
Simulation time 8396909729 ps
CPU time 12.42 seconds
Started May 21 01:04:45 PM PDT 24
Finished May 21 01:04:58 PM PDT 24
Peak memory 205352 kb
Host smart-80e7432c-adfa-4f5d-9f00-90b0be110a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39648
48591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3964848591
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.3066550910
Short name T1376
Test name
Test status
Simulation time 8422764676 ps
CPU time 12.3 seconds
Started May 21 01:04:17 PM PDT 24
Finished May 21 01:04:31 PM PDT 24
Peak memory 205360 kb
Host smart-00ed40a5-d3c1-426b-86d8-706c32f5056e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30665
50910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.3066550910
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.4161824454
Short name T1075
Test name
Test status
Simulation time 11490259786 ps
CPU time 17.95 seconds
Started May 21 01:04:21 PM PDT 24
Finished May 21 01:04:40 PM PDT 24
Peak memory 205432 kb
Host smart-aa0ca7f5-d2ed-4517-97c9-8cd5c94ec44f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41618
24454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.4161824454
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2595041384
Short name T1657
Test name
Test status
Simulation time 8438808484 ps
CPU time 15 seconds
Started May 21 01:04:21 PM PDT 24
Finished May 21 01:04:37 PM PDT 24
Peak memory 205632 kb
Host smart-81b94922-87e5-447f-8484-f9d293b5d649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25950
41384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2595041384
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.535535991
Short name T1251
Test name
Test status
Simulation time 8377454962 ps
CPU time 13.49 seconds
Started May 21 01:04:21 PM PDT 24
Finished May 21 01:04:36 PM PDT 24
Peak memory 205368 kb
Host smart-7efd1f77-9ca3-424e-ad26-e23cb7ab06ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53553
5991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.535535991
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.1937637724
Short name T928
Test name
Test status
Simulation time 8414277792 ps
CPU time 12.35 seconds
Started May 21 01:04:21 PM PDT 24
Finished May 21 01:04:34 PM PDT 24
Peak memory 205328 kb
Host smart-2962fcae-a6f0-4e90-ae29-dc93599aa862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19376
37724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.1937637724
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3747830939
Short name T456
Test name
Test status
Simulation time 8426098523 ps
CPU time 14.31 seconds
Started May 21 01:04:21 PM PDT 24
Finished May 21 01:04:36 PM PDT 24
Peak memory 205300 kb
Host smart-29718792-1044-4951-b35f-adf58b6dc816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37478
30939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3747830939
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_eop_single_bit_handling.4266992185
Short name T699
Test name
Test status
Simulation time 8404068484 ps
CPU time 13.33 seconds
Started May 21 01:04:40 PM PDT 24
Finished May 21 01:04:54 PM PDT 24
Peak memory 205372 kb
Host smart-2a2e743c-b0f6-43de-860c-4a95bd5efafd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42669
92185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_eop_single_bit_handling.4266992185
Directory /workspace/1.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.1234104579
Short name T862
Test name
Test status
Simulation time 8414672434 ps
CPU time 12.04 seconds
Started May 21 01:04:41 PM PDT 24
Finished May 21 01:04:54 PM PDT 24
Peak memory 205424 kb
Host smart-f8ec4bfb-9321-4afc-a658-8cba86c0ffc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12341
04579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.1234104579
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3267562442
Short name T730
Test name
Test status
Simulation time 8365395971 ps
CPU time 12.31 seconds
Started May 21 01:04:44 PM PDT 24
Finished May 21 01:04:57 PM PDT 24
Peak memory 205320 kb
Host smart-1a6b7a68-6f67-41e9-803a-369952204a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32675
62442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3267562442
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.2474933147
Short name T406
Test name
Test status
Simulation time 8465320314 ps
CPU time 11.11 seconds
Started May 21 01:04:28 PM PDT 24
Finished May 21 01:04:40 PM PDT 24
Peak memory 205308 kb
Host smart-389000c0-c399-491d-9513-1803ad40e8f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24749
33147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.2474933147
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1935398912
Short name T857
Test name
Test status
Simulation time 8468460580 ps
CPU time 12.7 seconds
Started May 21 01:04:26 PM PDT 24
Finished May 21 01:04:40 PM PDT 24
Peak memory 205308 kb
Host smart-e4034e14-73dc-42d1-8e87-1d06d72737de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19353
98912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1935398912
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.2116243156
Short name T1544
Test name
Test status
Simulation time 8403015844 ps
CPU time 11.42 seconds
Started May 21 01:04:28 PM PDT 24
Finished May 21 01:04:40 PM PDT 24
Peak memory 205272 kb
Host smart-0b74d9eb-40e6-4a5c-bcd6-383bb770c5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21162
43156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.2116243156
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.510762103
Short name T1195
Test name
Test status
Simulation time 8382868384 ps
CPU time 11.31 seconds
Started May 21 01:04:35 PM PDT 24
Finished May 21 01:04:48 PM PDT 24
Peak memory 205316 kb
Host smart-b9fbd4ac-4a6f-4989-994d-0e942b1eedbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51076
2103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.510762103
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.326710784
Short name T73
Test name
Test status
Simulation time 210206932 ps
CPU time 1.11 seconds
Started May 21 01:04:57 PM PDT 24
Finished May 21 01:05:00 PM PDT 24
Peak memory 221208 kb
Host smart-c3b306b4-64ed-4753-98e9-0b8fc78bcfee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=326710784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.326710784
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.2785480790
Short name T1604
Test name
Test status
Simulation time 8393241813 ps
CPU time 11.91 seconds
Started May 21 01:04:45 PM PDT 24
Finished May 21 01:04:58 PM PDT 24
Peak memory 205292 kb
Host smart-10feff5f-f752-4cb5-852d-8737147b785c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27854
80790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2785480790
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3624805427
Short name T437
Test name
Test status
Simulation time 8390851677 ps
CPU time 12.06 seconds
Started May 21 01:04:35 PM PDT 24
Finished May 21 01:04:48 PM PDT 24
Peak memory 205376 kb
Host smart-1037eee5-3d81-44a4-b1ab-852e991fb9b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36248
05427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3624805427
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3966707840
Short name T433
Test name
Test status
Simulation time 8452547296 ps
CPU time 15.13 seconds
Started May 21 01:04:16 PM PDT 24
Finished May 21 01:04:33 PM PDT 24
Peak memory 205372 kb
Host smart-130d60c9-9e38-40a2-8f2a-e1a98caa80c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39667
07840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3966707840
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.401217384
Short name T1099
Test name
Test status
Simulation time 8417327931 ps
CPU time 12.68 seconds
Started May 21 01:04:36 PM PDT 24
Finished May 21 01:04:49 PM PDT 24
Peak memory 205360 kb
Host smart-1ddb9cfb-d769-4362-9061-3a4d1941f796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40121
7384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.401217384
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.2789769328
Short name T1025
Test name
Test status
Simulation time 8402968206 ps
CPU time 12.49 seconds
Started May 21 01:04:36 PM PDT 24
Finished May 21 01:04:49 PM PDT 24
Peak memory 205360 kb
Host smart-e46f06b4-10ea-464f-a6a0-e746c9ea0f1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27897
69328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.2789769328
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.3211939057
Short name T1552
Test name
Test status
Simulation time 8469206440 ps
CPU time 10.98 seconds
Started May 21 01:06:54 PM PDT 24
Finished May 21 01:07:06 PM PDT 24
Peak memory 205316 kb
Host smart-c304e65d-7a8d-4b62-ad57-a8e759318c8a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3211939057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.3211939057
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.619066976
Short name T27
Test name
Test status
Simulation time 8415444270 ps
CPU time 11.15 seconds
Started May 21 01:06:53 PM PDT 24
Finished May 21 01:07:05 PM PDT 24
Peak memory 205344 kb
Host smart-cb78b67a-56c7-48d9-a837-d951733f5527
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=619066976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.619066976
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.2447947132
Short name T502
Test name
Test status
Simulation time 8439526886 ps
CPU time 14.77 seconds
Started May 21 01:06:57 PM PDT 24
Finished May 21 01:07:14 PM PDT 24
Peak memory 205408 kb
Host smart-54e78ca1-e694-4858-8675-42c57546ee75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24479
47132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.2447947132
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.1207137804
Short name T510
Test name
Test status
Simulation time 8375987332 ps
CPU time 11.49 seconds
Started May 21 01:06:41 PM PDT 24
Finished May 21 01:06:53 PM PDT 24
Peak memory 205244 kb
Host smart-f2bf2f98-5121-4f84-97b3-94e8e7c5f8eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12071
37804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.1207137804
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.3197734706
Short name T1331
Test name
Test status
Simulation time 8368130308 ps
CPU time 12.46 seconds
Started May 21 01:06:41 PM PDT 24
Finished May 21 01:06:54 PM PDT 24
Peak memory 205360 kb
Host smart-dc5e5e2b-382d-49a7-b17b-6ca210a56b74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31977
34706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.3197734706
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.4011974219
Short name T1006
Test name
Test status
Simulation time 9247060276 ps
CPU time 14.57 seconds
Started May 21 01:06:41 PM PDT 24
Finished May 21 01:06:57 PM PDT 24
Peak memory 205356 kb
Host smart-001c8bf8-6ffd-4565-b4d7-3583702644f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40119
74219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.4011974219
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.2892133449
Short name T1233
Test name
Test status
Simulation time 8365226364 ps
CPU time 13.48 seconds
Started May 21 01:06:46 PM PDT 24
Finished May 21 01:07:01 PM PDT 24
Peak memory 205356 kb
Host smart-bf8aa40f-f968-441c-9fa7-a4ffccfe5bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28921
33449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.2892133449
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.3323237858
Short name T761
Test name
Test status
Simulation time 8376578641 ps
CPU time 11.48 seconds
Started May 21 01:06:48 PM PDT 24
Finished May 21 01:07:02 PM PDT 24
Peak memory 205296 kb
Host smart-366b7d9d-d230-44b6-94b2-5904104b2fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33232
37858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.3323237858
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.1369753898
Short name T97
Test name
Test status
Simulation time 8990251154 ps
CPU time 13.33 seconds
Started May 21 01:06:45 PM PDT 24
Finished May 21 01:06:59 PM PDT 24
Peak memory 205332 kb
Host smart-794bf618-d4e9-4b4d-bd4b-60704978f02c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13697
53898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.1369753898
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.2144389226
Short name T1253
Test name
Test status
Simulation time 8528992968 ps
CPU time 13.91 seconds
Started May 21 01:06:47 PM PDT 24
Finished May 21 01:07:02 PM PDT 24
Peak memory 205372 kb
Host smart-0c2dd8ea-5b1a-41b4-8c8f-5aed4c73a781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21443
89226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2144389226
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.3383657148
Short name T1599
Test name
Test status
Simulation time 8398924966 ps
CPU time 14.05 seconds
Started May 21 01:06:51 PM PDT 24
Finished May 21 01:07:06 PM PDT 24
Peak memory 205372 kb
Host smart-d4f32550-0093-434c-a86f-b66f924b78bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33836
57148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.3383657148
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.3474137178
Short name T1383
Test name
Test status
Simulation time 8376663325 ps
CPU time 12.64 seconds
Started May 21 01:06:53 PM PDT 24
Finished May 21 01:07:07 PM PDT 24
Peak memory 205312 kb
Host smart-32653a1a-3d8a-445c-8f35-e7f7c8810d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34741
37178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3474137178
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.1238336290
Short name T1435
Test name
Test status
Simulation time 8524634439 ps
CPU time 12.65 seconds
Started May 21 01:06:48 PM PDT 24
Finished May 21 01:07:03 PM PDT 24
Peak memory 205268 kb
Host smart-87c2b612-7737-448e-8f98-8e5f27429e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12383
36290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.1238336290
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2306522310
Short name T404
Test name
Test status
Simulation time 8444615792 ps
CPU time 11.49 seconds
Started May 21 01:06:48 PM PDT 24
Finished May 21 01:07:01 PM PDT 24
Peak memory 205376 kb
Host smart-b1f460ec-ab3a-4740-969d-a9ccf24165f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23065
22310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2306522310
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2073561550
Short name T589
Test name
Test status
Simulation time 8376967116 ps
CPU time 12.24 seconds
Started May 21 01:06:45 PM PDT 24
Finished May 21 01:06:58 PM PDT 24
Peak memory 205308 kb
Host smart-3f0dc364-0a45-4f3e-ba30-0146f4eaa87c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20735
61550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2073561550
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.685407343
Short name T1453
Test name
Test status
Simulation time 8417563339 ps
CPU time 13.66 seconds
Started May 21 01:06:47 PM PDT 24
Finished May 21 01:07:02 PM PDT 24
Peak memory 205400 kb
Host smart-ae619516-c18f-4f3e-bf33-d53a63ef79bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68540
7343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.685407343
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.4168825998
Short name T1029
Test name
Test status
Simulation time 8415870509 ps
CPU time 12.57 seconds
Started May 21 01:06:47 PM PDT 24
Finished May 21 01:07:00 PM PDT 24
Peak memory 205348 kb
Host smart-8a428f47-a688-45cf-a8d3-753ff6505c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41688
25998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.4168825998
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.569923093
Short name T1031
Test name
Test status
Simulation time 8392481888 ps
CPU time 12.35 seconds
Started May 21 01:06:47 PM PDT 24
Finished May 21 01:07:00 PM PDT 24
Peak memory 205336 kb
Host smart-4c383d2a-f9c2-44df-bba3-2eac885b055a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56992
3093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.569923093
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.55034050
Short name T1169
Test name
Test status
Simulation time 8417176543 ps
CPU time 14.5 seconds
Started May 21 01:06:57 PM PDT 24
Finished May 21 01:07:13 PM PDT 24
Peak memory 205356 kb
Host smart-56b9f61f-5b11-4be2-a950-ec2e57a04e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55034
050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.55034050
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_eop_single_bit_handling.1336656032
Short name T1117
Test name
Test status
Simulation time 8420697575 ps
CPU time 13.12 seconds
Started May 21 01:06:53 PM PDT 24
Finished May 21 01:07:07 PM PDT 24
Peak memory 205376 kb
Host smart-f7ac8765-0c69-4c4f-8723-82d8631fa5ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13366
56032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_eop_single_bit_handling.1336656032
Directory /workspace/10.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.4112953337
Short name T1731
Test name
Test status
Simulation time 8385361175 ps
CPU time 11.96 seconds
Started May 21 01:06:47 PM PDT 24
Finished May 21 01:07:00 PM PDT 24
Peak memory 205320 kb
Host smart-1bf2dadf-f02c-4810-93ce-820bc729312c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41129
53337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.4112953337
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.3620385900
Short name T820
Test name
Test status
Simulation time 8368212737 ps
CPU time 11.76 seconds
Started May 21 01:06:53 PM PDT 24
Finished May 21 01:07:05 PM PDT 24
Peak memory 205396 kb
Host smart-42841e10-3f0d-4ecb-aa1e-850e2c7d5439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36203
85900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.3620385900
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.971193134
Short name T1280
Test name
Test status
Simulation time 23423125827 ps
CPU time 44.65 seconds
Started May 21 01:06:48 PM PDT 24
Finished May 21 01:07:35 PM PDT 24
Peak memory 205408 kb
Host smart-c89cd44d-06a9-4819-a624-8911a6473cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97119
3134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.971193134
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.2546316167
Short name T1254
Test name
Test status
Simulation time 8377435228 ps
CPU time 11.77 seconds
Started May 21 01:06:47 PM PDT 24
Finished May 21 01:07:00 PM PDT 24
Peak memory 205316 kb
Host smart-e541ede9-60e1-4361-848b-eded953015b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25463
16167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.2546316167
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.2177652533
Short name T1313
Test name
Test status
Simulation time 8418583182 ps
CPU time 12.1 seconds
Started May 21 01:06:57 PM PDT 24
Finished May 21 01:07:11 PM PDT 24
Peak memory 205380 kb
Host smart-21f68d43-b8f1-4895-a65e-ad3e388aba84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21776
52533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2177652533
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.1281505428
Short name T803
Test name
Test status
Simulation time 8383925437 ps
CPU time 11.55 seconds
Started May 21 01:06:49 PM PDT 24
Finished May 21 01:07:02 PM PDT 24
Peak memory 205332 kb
Host smart-77249e66-685e-4e7c-a37d-e19d610ffa59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12815
05428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.1281505428
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.2814055602
Short name T1513
Test name
Test status
Simulation time 8379503870 ps
CPU time 11.61 seconds
Started May 21 01:06:45 PM PDT 24
Finished May 21 01:06:58 PM PDT 24
Peak memory 205336 kb
Host smart-023f7ffc-99c3-4e7c-a0ca-094139e245ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28140
55602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.2814055602
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.1827390345
Short name T1130
Test name
Test status
Simulation time 8405697405 ps
CPU time 12.61 seconds
Started May 21 01:06:53 PM PDT 24
Finished May 21 01:07:07 PM PDT 24
Peak memory 205296 kb
Host smart-31a40fcb-8fef-4051-a4c7-2254318bad23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18273
90345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.1827390345
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_smoke.109781318
Short name T1444
Test name
Test status
Simulation time 8455837884 ps
CPU time 12.86 seconds
Started May 21 01:06:42 PM PDT 24
Finished May 21 01:06:56 PM PDT 24
Peak memory 205336 kb
Host smart-f80c2692-02ce-40a8-9f2a-68c08f4fe1df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10978
1318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.109781318
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.3355342706
Short name T1533
Test name
Test status
Simulation time 8385737350 ps
CPU time 12.92 seconds
Started May 21 01:06:48 PM PDT 24
Finished May 21 01:07:03 PM PDT 24
Peak memory 205348 kb
Host smart-4a864806-25b4-45aa-be27-7718f0f66343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33553
42706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3355342706
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.1424423574
Short name T320
Test name
Test status
Simulation time 8385390041 ps
CPU time 12.31 seconds
Started May 21 01:06:47 PM PDT 24
Finished May 21 01:07:00 PM PDT 24
Peak memory 205256 kb
Host smart-21f6b6b8-fa8b-40c0-b173-0ed0d2b3f624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14244
23574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.1424423574
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.2585668166
Short name T1733
Test name
Test status
Simulation time 8472618537 ps
CPU time 13.13 seconds
Started May 21 01:06:58 PM PDT 24
Finished May 21 01:07:14 PM PDT 24
Peak memory 205536 kb
Host smart-7ddfd9aa-1bf4-4d31-80fb-4b68ae2bfa01
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2585668166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.2585668166
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.3623315436
Short name T1022
Test name
Test status
Simulation time 8382827267 ps
CPU time 10.87 seconds
Started May 21 01:06:59 PM PDT 24
Finished May 21 01:07:12 PM PDT 24
Peak memory 205312 kb
Host smart-beebfa1b-3ef1-4557-b32e-d9cdbe1b68fb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3623315436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.3623315436
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.2643934399
Short name T1716
Test name
Test status
Simulation time 8402160467 ps
CPU time 13.82 seconds
Started May 21 01:06:59 PM PDT 24
Finished May 21 01:07:16 PM PDT 24
Peak memory 205272 kb
Host smart-5994537f-8a1b-4943-be7d-f454ad52bb27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26439
34399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.2643934399
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.3819884898
Short name T732
Test name
Test status
Simulation time 8413195221 ps
CPU time 11.99 seconds
Started May 21 01:06:53 PM PDT 24
Finished May 21 01:07:06 PM PDT 24
Peak memory 205364 kb
Host smart-f56a667d-f773-45b6-92ed-cdf09ebd8869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38198
84898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.3819884898
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.2537441897
Short name T1260
Test name
Test status
Simulation time 8985977879 ps
CPU time 13.02 seconds
Started May 21 01:06:53 PM PDT 24
Finished May 21 01:07:07 PM PDT 24
Peak memory 205376 kb
Host smart-dbf2b833-cf46-4ccd-9205-e409f82ef43d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25374
41897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.2537441897
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.1425429884
Short name T1284
Test name
Test status
Simulation time 8372783887 ps
CPU time 12.22 seconds
Started May 21 01:06:51 PM PDT 24
Finished May 21 01:07:04 PM PDT 24
Peak memory 205316 kb
Host smart-c15557ca-7df8-4612-8043-fc1f2df20b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14254
29884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1425429884
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.4192889530
Short name T682
Test name
Test status
Simulation time 8385149686 ps
CPU time 13.07 seconds
Started May 21 01:06:58 PM PDT 24
Finished May 21 01:07:13 PM PDT 24
Peak memory 205364 kb
Host smart-f99df254-539a-4bcc-9ea5-8de00f91f273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41928
89530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.4192889530
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.2927364021
Short name T1578
Test name
Test status
Simulation time 9154442836 ps
CPU time 13.39 seconds
Started May 21 01:06:52 PM PDT 24
Finished May 21 01:07:07 PM PDT 24
Peak memory 205412 kb
Host smart-f4043eda-cc30-4878-8198-3555dc0cc1d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29273
64021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.2927364021
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.1032637314
Short name T1332
Test name
Test status
Simulation time 8583837735 ps
CPU time 13.09 seconds
Started May 21 01:06:57 PM PDT 24
Finished May 21 01:07:12 PM PDT 24
Peak memory 205200 kb
Host smart-5640aed4-3a03-4bfd-a98a-56babbb6524c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10326
37314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.1032637314
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.1201628120
Short name T1086
Test name
Test status
Simulation time 8406558615 ps
CPU time 13.16 seconds
Started May 21 01:06:59 PM PDT 24
Finished May 21 01:07:15 PM PDT 24
Peak memory 205392 kb
Host smart-0ed0481e-6787-4dfa-a4e9-abfe052fe71c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12016
28120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.1201628120
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1924003538
Short name T933
Test name
Test status
Simulation time 8391481827 ps
CPU time 13.37 seconds
Started May 21 01:06:58 PM PDT 24
Finished May 21 01:07:14 PM PDT 24
Peak memory 205368 kb
Host smart-13b55e69-e522-4d34-903d-cfa3ae3d2006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19240
03538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1924003538
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.3174395986
Short name T299
Test name
Test status
Simulation time 8470106066 ps
CPU time 12.01 seconds
Started May 21 01:06:57 PM PDT 24
Finished May 21 01:07:10 PM PDT 24
Peak memory 205312 kb
Host smart-50dffaad-3270-4199-a93f-8387d2866cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31743
95986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.3174395986
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.656435616
Short name T1206
Test name
Test status
Simulation time 11546701274 ps
CPU time 14.53 seconds
Started May 21 01:06:58 PM PDT 24
Finished May 21 01:07:15 PM PDT 24
Peak memory 205400 kb
Host smart-7cde30f7-f5c9-48f7-956f-18302187b495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65643
5616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.656435616
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.3380184393
Short name T274
Test name
Test status
Simulation time 8425204547 ps
CPU time 11.29 seconds
Started May 21 01:06:58 PM PDT 24
Finished May 21 01:07:12 PM PDT 24
Peak memory 205352 kb
Host smart-b1a917b9-0d79-4c66-bd1f-6e7af273b43a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33801
84393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.3380184393
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.951415186
Short name T1534
Test name
Test status
Simulation time 8373236778 ps
CPU time 11.7 seconds
Started May 21 01:06:58 PM PDT 24
Finished May 21 01:07:11 PM PDT 24
Peak memory 205424 kb
Host smart-3ddd5439-1814-448c-aba0-2448c6d62547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95141
5186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.951415186
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.1265671697
Short name T1468
Test name
Test status
Simulation time 8418723368 ps
CPU time 11.84 seconds
Started May 21 01:06:58 PM PDT 24
Finished May 21 01:07:12 PM PDT 24
Peak memory 205348 kb
Host smart-c0db7555-e92b-4db0-b2b3-cf76c7c8244d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12656
71697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.1265671697
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.4066457296
Short name T303
Test name
Test status
Simulation time 8421744206 ps
CPU time 11.33 seconds
Started May 21 01:06:54 PM PDT 24
Finished May 21 01:07:07 PM PDT 24
Peak memory 205364 kb
Host smart-1bc0a08e-0c64-4c77-9da8-6c5a132679d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40664
57296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.4066457296
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1501086170
Short name T1209
Test name
Test status
Simulation time 8449393080 ps
CPU time 12.08 seconds
Started May 21 01:06:54 PM PDT 24
Finished May 21 01:07:07 PM PDT 24
Peak memory 205272 kb
Host smart-54780773-97fb-4ede-8cf5-6576925dd7c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15010
86170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1501086170
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.217676740
Short name T503
Test name
Test status
Simulation time 8389294629 ps
CPU time 11.57 seconds
Started May 21 01:06:57 PM PDT 24
Finished May 21 01:07:10 PM PDT 24
Peak memory 205284 kb
Host smart-68c00878-7137-4bd4-b03f-f04b27a0cf22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21767
6740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.217676740
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_eop_single_bit_handling.127281756
Short name T1475
Test name
Test status
Simulation time 8391768395 ps
CPU time 11.97 seconds
Started May 21 01:06:59 PM PDT 24
Finished May 21 01:07:13 PM PDT 24
Peak memory 205380 kb
Host smart-688b9b48-c47e-461c-9269-719ac9ba8aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12728
1756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_eop_single_bit_handling.127281756
Directory /workspace/11.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.2520185474
Short name T1351
Test name
Test status
Simulation time 8366504700 ps
CPU time 11.74 seconds
Started May 21 01:07:00 PM PDT 24
Finished May 21 01:07:14 PM PDT 24
Peak memory 205320 kb
Host smart-248c4fb0-1580-4503-a0fd-37264f087716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25201
85474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.2520185474
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.2918952155
Short name T848
Test name
Test status
Simulation time 14990109236 ps
CPU time 25.93 seconds
Started May 21 01:06:57 PM PDT 24
Finished May 21 01:07:24 PM PDT 24
Peak memory 205284 kb
Host smart-288bd72c-4f3f-44d6-b426-90addc46f6b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29189
52155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.2918952155
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.1386223437
Short name T1687
Test name
Test status
Simulation time 8397813689 ps
CPU time 12.2 seconds
Started May 21 01:06:59 PM PDT 24
Finished May 21 01:07:14 PM PDT 24
Peak memory 205376 kb
Host smart-3258e2a7-897f-413f-973d-8bd9cc0a10f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13862
23437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.1386223437
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.684825503
Short name T425
Test name
Test status
Simulation time 8468304049 ps
CPU time 11.81 seconds
Started May 21 01:07:02 PM PDT 24
Finished May 21 01:07:16 PM PDT 24
Peak memory 205320 kb
Host smart-3ecd84ee-a055-417a-9c78-fbce1b217f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68482
5503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.684825503
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.3353460411
Short name T627
Test name
Test status
Simulation time 8437280651 ps
CPU time 13.35 seconds
Started May 21 01:06:59 PM PDT 24
Finished May 21 01:07:15 PM PDT 24
Peak memory 205292 kb
Host smart-7a7ed232-a1fe-4bcc-91a0-8b0b65365727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33534
60411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.3353460411
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.405620916
Short name T955
Test name
Test status
Simulation time 8381645009 ps
CPU time 11.5 seconds
Started May 21 01:06:58 PM PDT 24
Finished May 21 01:07:12 PM PDT 24
Peak memory 205316 kb
Host smart-47a6ae7c-e91e-4b2e-a5bf-fa9bb7d0e722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40562
0916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.405620916
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.2286357235
Short name T163
Test name
Test status
Simulation time 8379485375 ps
CPU time 11.49 seconds
Started May 21 01:07:01 PM PDT 24
Finished May 21 01:07:14 PM PDT 24
Peak memory 205316 kb
Host smart-410e38e9-fee0-42c8-8dc4-8cc0b9106e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22863
57235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.2286357235
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2238341087
Short name T1711
Test name
Test status
Simulation time 8382331402 ps
CPU time 12.05 seconds
Started May 21 01:07:00 PM PDT 24
Finished May 21 01:07:15 PM PDT 24
Peak memory 205312 kb
Host smart-7fce6c59-73db-488d-a902-45bca4770d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22383
41087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2238341087
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.3133510486
Short name T1515
Test name
Test status
Simulation time 8405674910 ps
CPU time 12.97 seconds
Started May 21 01:06:55 PM PDT 24
Finished May 21 01:07:09 PM PDT 24
Peak memory 205284 kb
Host smart-2c2624b6-d678-464e-8b57-6031d509c890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31335
10486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.3133510486
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.3170224961
Short name T453
Test name
Test status
Simulation time 8397074012 ps
CPU time 13.16 seconds
Started May 21 01:07:02 PM PDT 24
Finished May 21 01:07:17 PM PDT 24
Peak memory 205312 kb
Host smart-9c7ce989-feea-4d35-9576-4f40c0010d17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31702
24961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.3170224961
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.2252218156
Short name T1732
Test name
Test status
Simulation time 8419513480 ps
CPU time 14.85 seconds
Started May 21 01:07:00 PM PDT 24
Finished May 21 01:07:17 PM PDT 24
Peak memory 205336 kb
Host smart-74df9186-845f-4d8c-8372-f988e3369e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22522
18156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.2252218156
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.474773517
Short name T1575
Test name
Test status
Simulation time 8382984884 ps
CPU time 12.01 seconds
Started May 21 01:07:11 PM PDT 24
Finished May 21 01:07:25 PM PDT 24
Peak memory 205444 kb
Host smart-efaaa782-f7c5-465a-95c7-8803a10a3ca6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=474773517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.474773517
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.4170207773
Short name T1497
Test name
Test status
Simulation time 8395121691 ps
CPU time 11.4 seconds
Started May 21 01:07:15 PM PDT 24
Finished May 21 01:07:27 PM PDT 24
Peak memory 205432 kb
Host smart-6e5b33d1-36f8-4268-acef-15a904cdd2c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41702
07773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.4170207773
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.4285128686
Short name T1101
Test name
Test status
Simulation time 8369843861 ps
CPU time 14.94 seconds
Started May 21 01:06:54 PM PDT 24
Finished May 21 01:07:10 PM PDT 24
Peak memory 205376 kb
Host smart-db685043-8408-4762-98d5-ff1eec398215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42851
28686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.4285128686
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.3364334034
Short name T1184
Test name
Test status
Simulation time 9253723821 ps
CPU time 13.76 seconds
Started May 21 01:06:59 PM PDT 24
Finished May 21 01:07:15 PM PDT 24
Peak memory 205388 kb
Host smart-3d7f228a-2a58-45de-b07f-158d3dd7462e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33643
34034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.3364334034
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.3085399212
Short name T7
Test name
Test status
Simulation time 8364174083 ps
CPU time 11.23 seconds
Started May 21 01:07:04 PM PDT 24
Finished May 21 01:07:16 PM PDT 24
Peak memory 205344 kb
Host smart-e3ae26c0-d025-4252-a4c9-0c8de9f95afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30853
99212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.3085399212
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.1268093392
Short name T962
Test name
Test status
Simulation time 8373157859 ps
CPU time 11.85 seconds
Started May 21 01:06:59 PM PDT 24
Finished May 21 01:07:13 PM PDT 24
Peak memory 205328 kb
Host smart-b05493d3-f874-438f-8bf7-38498b8bca34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12680
93392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.1268093392
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.826360255
Short name T694
Test name
Test status
Simulation time 9144164893 ps
CPU time 12.99 seconds
Started May 21 01:07:01 PM PDT 24
Finished May 21 01:07:16 PM PDT 24
Peak memory 205244 kb
Host smart-9f1caf86-03b7-4254-a724-3b89c5f7f6b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82636
0255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.826360255
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3861782572
Short name T1303
Test name
Test status
Simulation time 8457863308 ps
CPU time 12.56 seconds
Started May 21 01:07:02 PM PDT 24
Finished May 21 01:07:16 PM PDT 24
Peak memory 205364 kb
Host smart-7e585d2d-3ae6-4154-839c-484288dff8f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38617
82572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3861782572
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.3863644829
Short name T1495
Test name
Test status
Simulation time 8457315984 ps
CPU time 11.14 seconds
Started May 21 01:07:13 PM PDT 24
Finished May 21 01:07:26 PM PDT 24
Peak memory 205252 kb
Host smart-2fbca3f0-371f-4689-b054-6b7b751690a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38636
44829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3863644829
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.2324479880
Short name T598
Test name
Test status
Simulation time 8408021598 ps
CPU time 10.85 seconds
Started May 21 01:07:12 PM PDT 24
Finished May 21 01:07:25 PM PDT 24
Peak memory 205336 kb
Host smart-ea7062de-b71e-48ce-a67a-825be5aa6b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23244
79880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.2324479880
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.3359836750
Short name T1724
Test name
Test status
Simulation time 8431824091 ps
CPU time 13 seconds
Started May 21 01:07:00 PM PDT 24
Finished May 21 01:07:15 PM PDT 24
Peak memory 205432 kb
Host smart-3b7e6db6-99ab-4324-ab5d-c43027b43879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33598
36750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.3359836750
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.2932002795
Short name T1070
Test name
Test status
Simulation time 11534305305 ps
CPU time 14.24 seconds
Started May 21 01:07:06 PM PDT 24
Finished May 21 01:07:22 PM PDT 24
Peak memory 205396 kb
Host smart-21149ac2-4af0-42e1-a969-8363ac987b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29320
02795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.2932002795
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.3696373927
Short name T887
Test name
Test status
Simulation time 8412952556 ps
CPU time 12.17 seconds
Started May 21 01:07:05 PM PDT 24
Finished May 21 01:07:19 PM PDT 24
Peak memory 205380 kb
Host smart-5380c318-3793-4719-af65-71b02d6fb741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36963
73927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.3696373927
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.2657924502
Short name T573
Test name
Test status
Simulation time 8370037689 ps
CPU time 13.78 seconds
Started May 21 01:07:06 PM PDT 24
Finished May 21 01:07:21 PM PDT 24
Peak memory 205408 kb
Host smart-5dd7983a-8e03-43a5-a900-297c8c41d125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26579
24502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2657924502
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.3846937994
Short name T707
Test name
Test status
Simulation time 8415135448 ps
CPU time 13.49 seconds
Started May 21 01:07:05 PM PDT 24
Finished May 21 01:07:20 PM PDT 24
Peak memory 205336 kb
Host smart-e21b887b-238b-4830-b178-b6dad48901e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38469
37994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.3846937994
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.768284279
Short name T430
Test name
Test status
Simulation time 8400739195 ps
CPU time 11.64 seconds
Started May 21 01:07:06 PM PDT 24
Finished May 21 01:07:19 PM PDT 24
Peak memory 205412 kb
Host smart-161602d4-d510-4f66-a49a-15aacea4c85f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76828
4279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.768284279
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.3110516561
Short name T722
Test name
Test status
Simulation time 8388751909 ps
CPU time 11.66 seconds
Started May 21 01:07:03 PM PDT 24
Finished May 21 01:07:16 PM PDT 24
Peak memory 205456 kb
Host smart-1ba97081-331c-492d-a5e5-34e71c98acc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31105
16561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.3110516561
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.3131486233
Short name T821
Test name
Test status
Simulation time 8414315737 ps
CPU time 12.14 seconds
Started May 21 01:07:12 PM PDT 24
Finished May 21 01:07:26 PM PDT 24
Peak memory 205332 kb
Host smart-51163adc-e152-453c-8a2e-ee2f844e7314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31314
86233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.3131486233
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_eop_single_bit_handling.3307499397
Short name T949
Test name
Test status
Simulation time 8398442108 ps
CPU time 12.32 seconds
Started May 21 01:07:15 PM PDT 24
Finished May 21 01:07:28 PM PDT 24
Peak memory 205424 kb
Host smart-01e6607a-bae8-43e4-a1b1-814eb4da2b4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33074
99397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_eop_single_bit_handling.3307499397
Directory /workspace/12.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.81444095
Short name T522
Test name
Test status
Simulation time 8380323050 ps
CPU time 12.78 seconds
Started May 21 01:07:13 PM PDT 24
Finished May 21 01:07:28 PM PDT 24
Peak memory 205284 kb
Host smart-091f4209-40a0-4a4f-8177-21327e302672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81444
095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.81444095
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.2520575924
Short name T708
Test name
Test status
Simulation time 8362827543 ps
CPU time 12.84 seconds
Started May 21 01:07:11 PM PDT 24
Finished May 21 01:07:24 PM PDT 24
Peak memory 205300 kb
Host smart-9788184b-b54f-46cc-83d2-30580382bdb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25205
75924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.2520575924
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.162819089
Short name T987
Test name
Test status
Simulation time 8399807790 ps
CPU time 11.66 seconds
Started May 21 01:07:06 PM PDT 24
Finished May 21 01:07:19 PM PDT 24
Peak memory 205396 kb
Host smart-39af34b9-280e-4154-b1e4-037770bc026b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16281
9089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.162819089
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.1918597752
Short name T289
Test name
Test status
Simulation time 8420445208 ps
CPU time 11.52 seconds
Started May 21 01:07:12 PM PDT 24
Finished May 21 01:07:25 PM PDT 24
Peak memory 205360 kb
Host smart-e39f1707-ab6f-4695-92fe-524ef7a6d2f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19185
97752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1918597752
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.2682565704
Short name T276
Test name
Test status
Simulation time 8423580709 ps
CPU time 12.42 seconds
Started May 21 01:07:12 PM PDT 24
Finished May 21 01:07:27 PM PDT 24
Peak memory 205264 kb
Host smart-db235c65-14fd-4359-ae2e-9c5c94d2b51e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26825
65704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.2682565704
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.2217800314
Short name T432
Test name
Test status
Simulation time 8405429543 ps
CPU time 11.7 seconds
Started May 21 01:07:13 PM PDT 24
Finished May 21 01:07:27 PM PDT 24
Peak memory 205408 kb
Host smart-d2bfbcdf-2657-4453-8458-6f9f5f88553f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22178
00314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.2217800314
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.4143056380
Short name T1271
Test name
Test status
Simulation time 8407283137 ps
CPU time 11.64 seconds
Started May 21 01:07:12 PM PDT 24
Finished May 21 01:07:26 PM PDT 24
Peak memory 205340 kb
Host smart-67a1363b-207d-4ae7-b907-ec5bc8bb253b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41430
56380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.4143056380
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.3684654061
Short name T855
Test name
Test status
Simulation time 8399480600 ps
CPU time 11.63 seconds
Started May 21 01:07:15 PM PDT 24
Finished May 21 01:07:27 PM PDT 24
Peak memory 205412 kb
Host smart-4a079003-1b17-4a80-8e19-1164c35b4b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36846
54061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.3684654061
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.769364268
Short name T556
Test name
Test status
Simulation time 8477742572 ps
CPU time 11.94 seconds
Started May 21 01:07:22 PM PDT 24
Finished May 21 01:07:35 PM PDT 24
Peak memory 205444 kb
Host smart-95f34814-e413-4421-9a79-1fdcb1ec2852
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=769364268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.769364268
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.2498375818
Short name T91
Test name
Test status
Simulation time 8384359518 ps
CPU time 11.87 seconds
Started May 21 01:07:24 PM PDT 24
Finished May 21 01:07:37 PM PDT 24
Peak memory 205336 kb
Host smart-58624bcb-068a-4e43-885c-0c64eef4b7de
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2498375818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.2498375818
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.1571365605
Short name T1445
Test name
Test status
Simulation time 8451429322 ps
CPU time 11.76 seconds
Started May 21 01:07:27 PM PDT 24
Finished May 21 01:07:40 PM PDT 24
Peak memory 205240 kb
Host smart-e77ec24a-c7a3-44d8-8ff6-cba583582193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15713
65605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.1571365605
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.1176097575
Short name T553
Test name
Test status
Simulation time 8376114817 ps
CPU time 12.66 seconds
Started May 21 01:07:12 PM PDT 24
Finished May 21 01:07:27 PM PDT 24
Peak memory 205416 kb
Host smart-e5e63ad0-21d6-4d8c-b2f2-c8c6a1996841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11760
97575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.1176097575
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.3760736395
Short name T525
Test name
Test status
Simulation time 8557654996 ps
CPU time 13.36 seconds
Started May 21 01:07:13 PM PDT 24
Finished May 21 01:07:28 PM PDT 24
Peak memory 205392 kb
Host smart-fab0058a-5f59-4b2f-80dc-49b9df4d8ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37607
36395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.3760736395
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.3225541115
Short name T612
Test name
Test status
Simulation time 8363803532 ps
CPU time 13.88 seconds
Started May 21 01:07:19 PM PDT 24
Finished May 21 01:07:34 PM PDT 24
Peak memory 205364 kb
Host smart-7a79d60c-b604-41a2-aa7e-dd477fceb42f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32255
41115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.3225541115
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.1228146091
Short name T742
Test name
Test status
Simulation time 8379593128 ps
CPU time 15.7 seconds
Started May 21 01:07:12 PM PDT 24
Finished May 21 01:07:30 PM PDT 24
Peak memory 205412 kb
Host smart-991a6763-9846-47e0-a214-49cac01cb643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12281
46091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.1228146091
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.2731950144
Short name T798
Test name
Test status
Simulation time 9276622135 ps
CPU time 13.27 seconds
Started May 21 01:07:12 PM PDT 24
Finished May 21 01:07:27 PM PDT 24
Peak memory 205380 kb
Host smart-437e6d4b-fc17-4843-9ed0-aba5125e2d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27319
50144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.2731950144
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.1425594737
Short name T605
Test name
Test status
Simulation time 8444438025 ps
CPU time 12.72 seconds
Started May 21 01:07:11 PM PDT 24
Finished May 21 01:07:26 PM PDT 24
Peak memory 205308 kb
Host smart-63849943-14f5-4b94-b596-0a0acf6a9cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14255
94737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.1425594737
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.1659065363
Short name T1278
Test name
Test status
Simulation time 8460480985 ps
CPU time 13.94 seconds
Started May 21 01:07:23 PM PDT 24
Finished May 21 01:07:38 PM PDT 24
Peak memory 205432 kb
Host smart-d526b889-3896-4f0f-9a50-c22ef7882652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16590
65363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.1659065363
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.283458806
Short name T1113
Test name
Test status
Simulation time 8416307662 ps
CPU time 13.13 seconds
Started May 21 01:07:23 PM PDT 24
Finished May 21 01:07:37 PM PDT 24
Peak memory 205296 kb
Host smart-0249e955-c814-4571-84e4-b970ba6b15c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28345
8806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.283458806
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.559192691
Short name T535
Test name
Test status
Simulation time 8437753754 ps
CPU time 13.73 seconds
Started May 21 01:07:15 PM PDT 24
Finished May 21 01:07:29 PM PDT 24
Peak memory 205376 kb
Host smart-57234237-ba3a-4943-bfc2-40fcdc15d9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55919
2691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.559192691
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.3874502658
Short name T720
Test name
Test status
Simulation time 8421914256 ps
CPU time 10.97 seconds
Started May 21 01:07:11 PM PDT 24
Finished May 21 01:07:23 PM PDT 24
Peak memory 205284 kb
Host smart-a667b404-2eb9-4b61-b267-7875ee87da4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38745
02658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.3874502658
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.3951513315
Short name T929
Test name
Test status
Simulation time 11538403383 ps
CPU time 14.56 seconds
Started May 21 01:07:12 PM PDT 24
Finished May 21 01:07:28 PM PDT 24
Peak memory 205416 kb
Host smart-d6ccc776-8f66-4d3b-99a0-031b3fdccd15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39515
13315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.3951513315
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.881170218
Short name T436
Test name
Test status
Simulation time 8411641038 ps
CPU time 11.55 seconds
Started May 21 01:07:11 PM PDT 24
Finished May 21 01:07:23 PM PDT 24
Peak memory 205424 kb
Host smart-7887ca2d-2885-482e-b371-5e335e88283d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88117
0218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.881170218
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.3160248394
Short name T1140
Test name
Test status
Simulation time 8409690584 ps
CPU time 11.88 seconds
Started May 21 01:07:17 PM PDT 24
Finished May 21 01:07:29 PM PDT 24
Peak memory 205396 kb
Host smart-cbd4e7cc-77e7-4d13-89aa-48cd789ae6fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31602
48394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.3160248394
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.2859507765
Short name T941
Test name
Test status
Simulation time 8419483278 ps
CPU time 11.39 seconds
Started May 21 01:07:18 PM PDT 24
Finished May 21 01:07:31 PM PDT 24
Peak memory 205408 kb
Host smart-dc4d32bf-a36c-4613-8d54-03efb98e103a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28595
07765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.2859507765
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.3096244367
Short name T1443
Test name
Test status
Simulation time 8436117935 ps
CPU time 11.93 seconds
Started May 21 01:07:18 PM PDT 24
Finished May 21 01:07:31 PM PDT 24
Peak memory 205304 kb
Host smart-c0a5e6e8-1b8c-4414-ba41-fcc5ae035ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30962
44367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3096244367
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2813843317
Short name T1502
Test name
Test status
Simulation time 8385469813 ps
CPU time 11.87 seconds
Started May 21 01:07:18 PM PDT 24
Finished May 21 01:07:30 PM PDT 24
Peak memory 205404 kb
Host smart-2e32fc71-bba2-4626-8363-6944a77590f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28138
43317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2813843317
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.2875779042
Short name T1164
Test name
Test status
Simulation time 8407607066 ps
CPU time 11.51 seconds
Started May 21 01:07:24 PM PDT 24
Finished May 21 01:07:37 PM PDT 24
Peak memory 205428 kb
Host smart-7249d74c-4b3a-471a-9a98-98197c8dbe16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28757
79042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.2875779042
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_eop_single_bit_handling.1006446561
Short name T1648
Test name
Test status
Simulation time 8408841974 ps
CPU time 13.68 seconds
Started May 21 01:07:24 PM PDT 24
Finished May 21 01:07:38 PM PDT 24
Peak memory 205372 kb
Host smart-059c8aff-b165-4feb-90c2-640be3b73c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10064
46561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_eop_single_bit_handling.1006446561
Directory /workspace/13.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.3919917192
Short name T1374
Test name
Test status
Simulation time 8400607601 ps
CPU time 12.23 seconds
Started May 21 01:07:22 PM PDT 24
Finished May 21 01:07:35 PM PDT 24
Peak memory 205348 kb
Host smart-23110113-2a79-4f41-8f44-d13f53ad8ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39199
17192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.3919917192
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.1301448103
Short name T24
Test name
Test status
Simulation time 8365011496 ps
CPU time 11.21 seconds
Started May 21 01:07:26 PM PDT 24
Finished May 21 01:07:39 PM PDT 24
Peak memory 205244 kb
Host smart-1b7f7422-09e7-48f4-aca9-4944837fffca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13014
48103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.1301448103
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.3646595147
Short name T1565
Test name
Test status
Simulation time 18954630131 ps
CPU time 42.23 seconds
Started May 21 01:07:21 PM PDT 24
Finished May 21 01:08:04 PM PDT 24
Peak memory 205444 kb
Host smart-df44a2f4-732d-4840-adf8-507fd1ae2a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36465
95147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.3646595147
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.173710740
Short name T813
Test name
Test status
Simulation time 8473329649 ps
CPU time 12.86 seconds
Started May 21 01:07:18 PM PDT 24
Finished May 21 01:07:31 PM PDT 24
Peak memory 205412 kb
Host smart-2062e14f-7e43-4af6-a3e0-c20f13ccc839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17371
0740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.173710740
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.2872181655
Short name T371
Test name
Test status
Simulation time 8528923396 ps
CPU time 11.3 seconds
Started May 21 01:07:19 PM PDT 24
Finished May 21 01:07:32 PM PDT 24
Peak memory 205356 kb
Host smart-5f05258e-7fe8-4a2b-a769-6d4ba033df06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28721
81655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.2872181655
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.2971398500
Short name T1217
Test name
Test status
Simulation time 8409136081 ps
CPU time 14.61 seconds
Started May 21 01:07:20 PM PDT 24
Finished May 21 01:07:36 PM PDT 24
Peak memory 205448 kb
Host smart-ba3c5577-fbae-40e0-b0ec-9262c0e2ac66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29713
98500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.2971398500
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.1843065418
Short name T466
Test name
Test status
Simulation time 8397027095 ps
CPU time 11.64 seconds
Started May 21 01:07:24 PM PDT 24
Finished May 21 01:07:37 PM PDT 24
Peak memory 205312 kb
Host smart-eceed750-fe73-45fc-a254-df1847de5c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18430
65418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.1843065418
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.3947869306
Short name T1532
Test name
Test status
Simulation time 8378373340 ps
CPU time 12.1 seconds
Started May 21 01:07:23 PM PDT 24
Finished May 21 01:07:36 PM PDT 24
Peak memory 205272 kb
Host smart-a97ba032-4265-40ec-956f-846ddd732dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39478
69306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.3947869306
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.2047544784
Short name T973
Test name
Test status
Simulation time 8381726037 ps
CPU time 14.95 seconds
Started May 21 01:07:23 PM PDT 24
Finished May 21 01:07:39 PM PDT 24
Peak memory 205560 kb
Host smart-cc04f715-c218-45ac-ac2f-1191f56c487c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20475
44784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.2047544784
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1328817052
Short name T331
Test name
Test status
Simulation time 8445901178 ps
CPU time 13.83 seconds
Started May 21 01:07:12 PM PDT 24
Finished May 21 01:07:27 PM PDT 24
Peak memory 205324 kb
Host smart-8256a712-ebf3-4265-b08f-977fc314903d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13288
17052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1328817052
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1298560976
Short name T728
Test name
Test status
Simulation time 8397364643 ps
CPU time 10.77 seconds
Started May 21 01:07:23 PM PDT 24
Finished May 21 01:07:35 PM PDT 24
Peak memory 205352 kb
Host smart-45878edd-76f7-43c2-a21e-4395374ffcc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12985
60976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1298560976
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.45526036
Short name T541
Test name
Test status
Simulation time 8399677917 ps
CPU time 11.64 seconds
Started May 21 01:07:27 PM PDT 24
Finished May 21 01:07:40 PM PDT 24
Peak memory 205376 kb
Host smart-2f442a7a-3fbb-43ff-b512-9fa5eaaf1fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45526
036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.45526036
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.2845651031
Short name T886
Test name
Test status
Simulation time 8471333132 ps
CPU time 12.86 seconds
Started May 21 01:07:37 PM PDT 24
Finished May 21 01:07:51 PM PDT 24
Peak memory 205256 kb
Host smart-cdd59ab9-f38b-42e8-b3a1-5a1412b68548
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2845651031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.2845651031
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.2024443606
Short name T497
Test name
Test status
Simulation time 8421159324 ps
CPU time 11 seconds
Started May 21 01:07:36 PM PDT 24
Finished May 21 01:07:48 PM PDT 24
Peak memory 205428 kb
Host smart-ef0c49e8-660e-4ae1-bd60-1031e79afd6f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2024443606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.2024443606
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.522690423
Short name T1057
Test name
Test status
Simulation time 8447097222 ps
CPU time 11.22 seconds
Started May 21 01:07:43 PM PDT 24
Finished May 21 01:07:56 PM PDT 24
Peak memory 205312 kb
Host smart-f2f2e6a1-bd10-429c-87e1-53dfe3336ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52269
0423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.522690423
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2660574525
Short name T1581
Test name
Test status
Simulation time 8421423366 ps
CPU time 15.55 seconds
Started May 21 01:07:22 PM PDT 24
Finished May 21 01:07:39 PM PDT 24
Peak memory 205356 kb
Host smart-10f6c97e-2b1b-4c76-a789-677eb4818d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26605
74525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2660574525
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.3809653495
Short name T726
Test name
Test status
Simulation time 8476006853 ps
CPU time 13.3 seconds
Started May 21 01:07:24 PM PDT 24
Finished May 21 01:07:39 PM PDT 24
Peak memory 205340 kb
Host smart-7a3315c0-e065-4205-aab9-bf3a41be3581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38096
53495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.3809653495
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.3398295152
Short name T1409
Test name
Test status
Simulation time 9093985006 ps
CPU time 12.99 seconds
Started May 21 01:07:24 PM PDT 24
Finished May 21 01:07:39 PM PDT 24
Peak memory 205336 kb
Host smart-8a520b9d-5b34-4ec5-a3f9-084cc45090f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33982
95152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.3398295152
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.799210905
Short name T495
Test name
Test status
Simulation time 8364760239 ps
CPU time 11.35 seconds
Started May 21 01:07:33 PM PDT 24
Finished May 21 01:07:45 PM PDT 24
Peak memory 205352 kb
Host smart-be489516-1abf-4ad1-b35c-666fff0d967f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79921
0905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.799210905
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.3171080060
Short name T956
Test name
Test status
Simulation time 8380683168 ps
CPU time 13.5 seconds
Started May 21 01:07:23 PM PDT 24
Finished May 21 01:07:37 PM PDT 24
Peak memory 205412 kb
Host smart-d38ffa2e-225c-49f6-b035-9a520e1e18bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31710
80060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.3171080060
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.2115115922
Short name T1098
Test name
Test status
Simulation time 8397689591 ps
CPU time 12.83 seconds
Started May 21 01:07:30 PM PDT 24
Finished May 21 01:07:43 PM PDT 24
Peak memory 205376 kb
Host smart-54a9c74d-efab-47ce-836c-c25f2b74b57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21151
15922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.2115115922
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.330265545
Short name T1458
Test name
Test status
Simulation time 8413578398 ps
CPU time 12.29 seconds
Started May 21 01:07:38 PM PDT 24
Finished May 21 01:07:51 PM PDT 24
Peak memory 205288 kb
Host smart-bc2be053-708e-4405-8301-daea403a1c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33026
5545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.330265545
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3324171363
Short name T1684
Test name
Test status
Simulation time 8379048806 ps
CPU time 12 seconds
Started May 21 01:07:40 PM PDT 24
Finished May 21 01:07:53 PM PDT 24
Peak memory 205312 kb
Host smart-a31e6ce8-26e9-40f0-8594-d959ba49e9c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33241
71363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3324171363
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.84463644
Short name T519
Test name
Test status
Simulation time 8418888553 ps
CPU time 11.22 seconds
Started May 21 01:07:31 PM PDT 24
Finished May 21 01:07:43 PM PDT 24
Peak memory 205372 kb
Host smart-cae3d202-3200-47cd-8850-e8cf389e6cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84463
644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.84463644
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.4154131065
Short name T1080
Test name
Test status
Simulation time 8405362957 ps
CPU time 11.98 seconds
Started May 21 01:07:34 PM PDT 24
Finished May 21 01:07:47 PM PDT 24
Peak memory 205344 kb
Host smart-6809e255-73cf-486a-bd75-e753953b7057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41541
31065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.4154131065
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.1620560327
Short name T774
Test name
Test status
Simulation time 11531733606 ps
CPU time 16.46 seconds
Started May 21 01:07:32 PM PDT 24
Finished May 21 01:07:49 PM PDT 24
Peak memory 205344 kb
Host smart-d6f1bf28-df12-4870-a76f-6497ff1dd085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16205
60327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.1620560327
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.2966519998
Short name T835
Test name
Test status
Simulation time 8417202189 ps
CPU time 11.55 seconds
Started May 21 01:07:30 PM PDT 24
Finished May 21 01:07:43 PM PDT 24
Peak memory 205332 kb
Host smart-21de2907-868c-4ce0-928d-3fe6eff176e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29665
19998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.2966519998
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.3449803745
Short name T1051
Test name
Test status
Simulation time 8372506042 ps
CPU time 11.37 seconds
Started May 21 01:07:30 PM PDT 24
Finished May 21 01:07:42 PM PDT 24
Peak memory 205356 kb
Host smart-8b7ff091-9ffa-440e-abf6-84c2cfa41779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34498
03745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.3449803745
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.3093247227
Short name T952
Test name
Test status
Simulation time 8430540325 ps
CPU time 12.55 seconds
Started May 21 01:07:30 PM PDT 24
Finished May 21 01:07:43 PM PDT 24
Peak memory 205256 kb
Host smart-d3f17bff-0844-4d05-9e32-59990ac30886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30932
47227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.3093247227
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.2281219821
Short name T1573
Test name
Test status
Simulation time 8400863464 ps
CPU time 13.76 seconds
Started May 21 01:07:30 PM PDT 24
Finished May 21 01:07:45 PM PDT 24
Peak memory 205344 kb
Host smart-5eba0e7f-fc7d-4ef5-9a73-db24bdb4ba7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22812
19821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.2281219821
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.4266756729
Short name T1590
Test name
Test status
Simulation time 8391702730 ps
CPU time 12.81 seconds
Started May 21 01:07:29 PM PDT 24
Finished May 21 01:07:42 PM PDT 24
Peak memory 205316 kb
Host smart-fe292578-6866-48ee-b6c3-403106601b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42667
56729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.4266756729
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.3377624227
Short name T894
Test name
Test status
Simulation time 8377507837 ps
CPU time 11.49 seconds
Started May 21 01:07:35 PM PDT 24
Finished May 21 01:07:47 PM PDT 24
Peak memory 205420 kb
Host smart-5a68e722-5742-418b-bcd9-7dd0e0a6f30a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33776
24227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.3377624227
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_eop_single_bit_handling.2054252901
Short name T1523
Test name
Test status
Simulation time 8411831927 ps
CPU time 11.28 seconds
Started May 21 01:07:30 PM PDT 24
Finished May 21 01:07:42 PM PDT 24
Peak memory 205416 kb
Host smart-73b7635a-2118-46e5-ab86-f17313b8531a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20542
52901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_eop_single_bit_handling.2054252901
Directory /workspace/14.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.112087060
Short name T1121
Test name
Test status
Simulation time 8372838881 ps
CPU time 15.19 seconds
Started May 21 01:07:32 PM PDT 24
Finished May 21 01:07:48 PM PDT 24
Peak memory 205436 kb
Host smart-43a409c5-aa63-4c4e-9c5d-c885a6a945ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11208
7060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.112087060
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3889408580
Short name T1188
Test name
Test status
Simulation time 8369648221 ps
CPU time 13.44 seconds
Started May 21 01:07:37 PM PDT 24
Finished May 21 01:07:52 PM PDT 24
Peak memory 205300 kb
Host smart-156e03f8-27d4-4902-8802-91e9be988c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38894
08580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3889408580
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.1520103927
Short name T1043
Test name
Test status
Simulation time 15900076957 ps
CPU time 27.89 seconds
Started May 21 01:07:31 PM PDT 24
Finished May 21 01:08:00 PM PDT 24
Peak memory 205356 kb
Host smart-37cb07eb-a0f0-4a3a-8284-c0efb0989ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15201
03927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.1520103927
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3188244977
Short name T9
Test name
Test status
Simulation time 8404894312 ps
CPU time 11.47 seconds
Started May 21 01:07:31 PM PDT 24
Finished May 21 01:07:44 PM PDT 24
Peak memory 205564 kb
Host smart-42527604-bd8a-4db2-977c-8973bb68df81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31882
44977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3188244977
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.265795652
Short name T860
Test name
Test status
Simulation time 8422630389 ps
CPU time 10.65 seconds
Started May 21 01:07:31 PM PDT 24
Finished May 21 01:07:43 PM PDT 24
Peak memory 205352 kb
Host smart-c2f610df-f165-4643-b5c6-cadad41d3969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26579
5652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.265795652
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.1420993790
Short name T874
Test name
Test status
Simulation time 8441541507 ps
CPU time 12.61 seconds
Started May 21 01:07:32 PM PDT 24
Finished May 21 01:07:45 PM PDT 24
Peak memory 205364 kb
Host smart-52efba6d-92c3-4330-ab98-117e85ea7bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14209
93790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.1420993790
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.1400116775
Short name T475
Test name
Test status
Simulation time 8369518067 ps
CPU time 13.27 seconds
Started May 21 01:07:29 PM PDT 24
Finished May 21 01:07:43 PM PDT 24
Peak memory 205316 kb
Host smart-344c9f9b-3aff-465f-8526-d4ef9f73c4a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14001
16775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.1400116775
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.1959413672
Short name T326
Test name
Test status
Simulation time 8392063248 ps
CPU time 12.08 seconds
Started May 21 01:07:34 PM PDT 24
Finished May 21 01:07:47 PM PDT 24
Peak memory 205312 kb
Host smart-9ebf7b1d-e771-482a-9292-f8662f93d93e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19594
13672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1959413672
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.515826633
Short name T604
Test name
Test status
Simulation time 8393186804 ps
CPU time 10.89 seconds
Started May 21 01:07:33 PM PDT 24
Finished May 21 01:07:45 PM PDT 24
Peak memory 205432 kb
Host smart-8c44aba2-39e5-4395-a497-e8f5cf275ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51582
6633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.515826633
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.4107017194
Short name T1033
Test name
Test status
Simulation time 8460593776 ps
CPU time 12.59 seconds
Started May 21 01:07:25 PM PDT 24
Finished May 21 01:07:39 PM PDT 24
Peak memory 205316 kb
Host smart-43097172-a8b1-4d03-9abf-19d745311bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41070
17194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.4107017194
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.3220833335
Short name T713
Test name
Test status
Simulation time 8447228020 ps
CPU time 11.02 seconds
Started May 21 01:07:34 PM PDT 24
Finished May 21 01:07:46 PM PDT 24
Peak memory 205344 kb
Host smart-4eb79293-8314-4afc-95ac-1522ab4f21cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32208
33335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.3220833335
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.3548044001
Short name T1182
Test name
Test status
Simulation time 8392174009 ps
CPU time 12.04 seconds
Started May 21 01:07:33 PM PDT 24
Finished May 21 01:07:46 PM PDT 24
Peak memory 205332 kb
Host smart-7dcfffe4-42ca-41e5-9a9e-547ad3dd8c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35480
44001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.3548044001
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.3022691985
Short name T1226
Test name
Test status
Simulation time 8488871066 ps
CPU time 11.14 seconds
Started May 21 01:07:42 PM PDT 24
Finished May 21 01:07:55 PM PDT 24
Peak memory 205324 kb
Host smart-46243c72-bdee-463c-a0a9-53132906d87a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3022691985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.3022691985
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.1597940407
Short name T424
Test name
Test status
Simulation time 8402959183 ps
CPU time 11.28 seconds
Started May 21 01:07:48 PM PDT 24
Finished May 21 01:08:00 PM PDT 24
Peak memory 205304 kb
Host smart-aa7b93c3-a224-4ffd-bbc6-ee3737d79d87
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1597940407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.1597940407
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.980436446
Short name T1612
Test name
Test status
Simulation time 8391397688 ps
CPU time 10.76 seconds
Started May 21 01:07:44 PM PDT 24
Finished May 21 01:07:56 PM PDT 24
Peak memory 205408 kb
Host smart-77af3b5f-72c7-487e-ada3-f86db9119d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98043
6446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.980436446
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.406952472
Short name T804
Test name
Test status
Simulation time 8392779621 ps
CPU time 11.97 seconds
Started May 21 01:07:40 PM PDT 24
Finished May 21 01:07:53 PM PDT 24
Peak memory 205100 kb
Host smart-00b68c71-9115-4735-b9b1-9ec08d31ca7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40695
2472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.406952472
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2386727501
Short name T1299
Test name
Test status
Simulation time 8912850882 ps
CPU time 12.41 seconds
Started May 21 01:07:37 PM PDT 24
Finished May 21 01:07:51 PM PDT 24
Peak memory 205304 kb
Host smart-21ffa947-dc3d-410a-ba2e-dc01dc94d84f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23867
27501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2386727501
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.2288087049
Short name T298
Test name
Test status
Simulation time 8386469019 ps
CPU time 11.84 seconds
Started May 21 01:07:38 PM PDT 24
Finished May 21 01:07:51 PM PDT 24
Peak memory 205324 kb
Host smart-e8ec7eb5-f7aa-4228-9f4d-9cb7060dca82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22880
87049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.2288087049
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.2813912016
Short name T334
Test name
Test status
Simulation time 8371007958 ps
CPU time 11.46 seconds
Started May 21 01:07:40 PM PDT 24
Finished May 21 01:07:52 PM PDT 24
Peak memory 205180 kb
Host smart-7d8472a5-4295-41ee-9a42-6663549bcc51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28139
12016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.2813912016
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.175051077
Short name T683
Test name
Test status
Simulation time 9090448195 ps
CPU time 13.55 seconds
Started May 21 01:07:43 PM PDT 24
Finished May 21 01:07:58 PM PDT 24
Peak memory 205316 kb
Host smart-5dd8a430-57e6-460a-a63d-17000b66b995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17505
1077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.175051077
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.4224984929
Short name T995
Test name
Test status
Simulation time 8575674345 ps
CPU time 15.87 seconds
Started May 21 01:07:36 PM PDT 24
Finished May 21 01:07:53 PM PDT 24
Peak memory 205172 kb
Host smart-9baff8f8-6abb-481d-b632-28aae0005d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42249
84929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.4224984929
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3092945944
Short name T1307
Test name
Test status
Simulation time 8369281623 ps
CPU time 12.02 seconds
Started May 21 01:07:48 PM PDT 24
Finished May 21 01:08:01 PM PDT 24
Peak memory 205328 kb
Host smart-93ac56af-11c7-4471-9983-06b07def8e84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30929
45944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3092945944
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2940021787
Short name T342
Test name
Test status
Simulation time 8458730107 ps
CPU time 12.38 seconds
Started May 21 01:07:35 PM PDT 24
Finished May 21 01:07:48 PM PDT 24
Peak memory 205356 kb
Host smart-d29d9d41-7285-454b-acb9-39a61b8f6f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29400
21787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2940021787
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.3012159269
Short name T477
Test name
Test status
Simulation time 8418660718 ps
CPU time 11.34 seconds
Started May 21 01:07:38 PM PDT 24
Finished May 21 01:07:50 PM PDT 24
Peak memory 205352 kb
Host smart-3ce9781a-bd3e-42df-85df-82b52f04cc29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30121
59269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.3012159269
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.832110719
Short name T1089
Test name
Test status
Simulation time 11529422405 ps
CPU time 13.91 seconds
Started May 21 01:07:43 PM PDT 24
Finished May 21 01:07:58 PM PDT 24
Peak memory 205360 kb
Host smart-4e7fed4f-b6ab-43cb-b42b-6d4410a04977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83211
0719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.832110719
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.1342391737
Short name T721
Test name
Test status
Simulation time 8465293103 ps
CPU time 13.41 seconds
Started May 21 01:07:36 PM PDT 24
Finished May 21 01:07:51 PM PDT 24
Peak memory 205320 kb
Host smart-42514b69-47de-46ff-89e5-100b9e581a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13423
91737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.1342391737
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3348606525
Short name T826
Test name
Test status
Simulation time 8368164361 ps
CPU time 14.25 seconds
Started May 21 01:07:38 PM PDT 24
Finished May 21 01:07:54 PM PDT 24
Peak memory 205404 kb
Host smart-d6b5f13c-8885-49c8-a141-4f6671968fe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33486
06525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3348606525
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.3826680720
Short name T1015
Test name
Test status
Simulation time 8412852732 ps
CPU time 13.4 seconds
Started May 21 01:07:37 PM PDT 24
Finished May 21 01:07:51 PM PDT 24
Peak memory 205300 kb
Host smart-a6509bd8-4a64-47c3-88e5-1746b9873d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38266
80720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.3826680720
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1456193855
Short name T1411
Test name
Test status
Simulation time 8454942434 ps
CPU time 12.33 seconds
Started May 21 01:07:41 PM PDT 24
Finished May 21 01:07:55 PM PDT 24
Peak memory 205352 kb
Host smart-8d4703f2-cac0-4327-b9ed-8276c166ca08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14561
93855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1456193855
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3319806123
Short name T752
Test name
Test status
Simulation time 8428836033 ps
CPU time 13.42 seconds
Started May 21 01:07:49 PM PDT 24
Finished May 21 01:08:04 PM PDT 24
Peak memory 205288 kb
Host smart-25484e7a-1bbe-4ea2-ad66-9c67a64aef8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33198
06123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3319806123
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_eop_single_bit_handling.1980025883
Short name T784
Test name
Test status
Simulation time 8427424320 ps
CPU time 12.46 seconds
Started May 21 01:07:41 PM PDT 24
Finished May 21 01:07:55 PM PDT 24
Peak memory 205444 kb
Host smart-78c26039-ce3c-4673-a519-996b6ebf3c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19800
25883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_eop_single_bit_handling.1980025883
Directory /workspace/15.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.2535324098
Short name T1728
Test name
Test status
Simulation time 8394993784 ps
CPU time 13.49 seconds
Started May 21 01:07:42 PM PDT 24
Finished May 21 01:07:57 PM PDT 24
Peak memory 205392 kb
Host smart-788cdbb5-a2d6-454f-b128-29eabc9eaa86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25353
24098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.2535324098
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.274892692
Short name T32
Test name
Test status
Simulation time 8379294378 ps
CPU time 12.51 seconds
Started May 21 01:07:45 PM PDT 24
Finished May 21 01:07:58 PM PDT 24
Peak memory 205360 kb
Host smart-e2c6a86e-31ab-4a04-ba47-9d2f18101441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27489
2692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.274892692
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.160670148
Short name T398
Test name
Test status
Simulation time 8400276116 ps
CPU time 12.48 seconds
Started May 21 01:07:42 PM PDT 24
Finished May 21 01:07:56 PM PDT 24
Peak memory 205372 kb
Host smart-9a7573a7-ff3d-4030-a975-bb03ba77dfb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16067
0148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.160670148
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.1195044596
Short name T700
Test name
Test status
Simulation time 8386800785 ps
CPU time 11.73 seconds
Started May 21 01:07:44 PM PDT 24
Finished May 21 01:07:57 PM PDT 24
Peak memory 205368 kb
Host smart-5255c3be-c1a4-43fd-ade7-1faa9f5eafdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11950
44596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1195044596
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.811569692
Short name T1002
Test name
Test status
Simulation time 8410531193 ps
CPU time 11.99 seconds
Started May 21 01:07:43 PM PDT 24
Finished May 21 01:07:56 PM PDT 24
Peak memory 205424 kb
Host smart-37c1cfa3-2449-4744-9a06-54d197be2525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81156
9692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.811569692
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.2350152377
Short name T348
Test name
Test status
Simulation time 8368433564 ps
CPU time 11.84 seconds
Started May 21 01:07:48 PM PDT 24
Finished May 21 01:08:00 PM PDT 24
Peak memory 205236 kb
Host smart-7b0c25ac-03cd-4b1b-9760-104c58b37ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23501
52377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.2350152377
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.532348107
Short name T788
Test name
Test status
Simulation time 8439372182 ps
CPU time 11.25 seconds
Started May 21 01:07:46 PM PDT 24
Finished May 21 01:07:58 PM PDT 24
Peak memory 205284 kb
Host smart-8205b52c-f2a1-4296-9b2c-4b05d5bf437f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53234
8107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.532348107
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.3963453859
Short name T1228
Test name
Test status
Simulation time 8380217596 ps
CPU time 12.11 seconds
Started May 21 01:07:48 PM PDT 24
Finished May 21 01:08:01 PM PDT 24
Peak memory 205256 kb
Host smart-b2466ea0-9846-448b-aa76-983a5d682cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39634
53859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.3963453859
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.697710093
Short name T790
Test name
Test status
Simulation time 8421000877 ps
CPU time 11.88 seconds
Started May 21 01:07:41 PM PDT 24
Finished May 21 01:07:54 PM PDT 24
Peak memory 205336 kb
Host smart-c4b56f48-d70d-454c-9e03-d3a9f122c317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69771
0093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.697710093
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1215146615
Short name T531
Test name
Test status
Simulation time 8401669683 ps
CPU time 10.78 seconds
Started May 21 01:07:41 PM PDT 24
Finished May 21 01:07:52 PM PDT 24
Peak memory 205424 kb
Host smart-98fd4901-50c8-41fa-bb90-faf54d979d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12151
46615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1215146615
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.2636567322
Short name T464
Test name
Test status
Simulation time 8462501272 ps
CPU time 11.27 seconds
Started May 21 01:07:42 PM PDT 24
Finished May 21 01:07:54 PM PDT 24
Peak memory 205348 kb
Host smart-a2256451-8fbf-4407-8dc3-332ba6cf8784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26365
67322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.2636567322
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.3594259999
Short name T1200
Test name
Test status
Simulation time 8478168244 ps
CPU time 12.39 seconds
Started May 21 01:07:57 PM PDT 24
Finished May 21 01:08:12 PM PDT 24
Peak memory 205396 kb
Host smart-209a417d-1af8-494f-8780-941bb57769cb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3594259999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.3594259999
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.2895413810
Short name T367
Test name
Test status
Simulation time 8459556254 ps
CPU time 11.21 seconds
Started May 21 01:07:56 PM PDT 24
Finished May 21 01:08:10 PM PDT 24
Peak memory 205352 kb
Host smart-b469b3bf-70d6-4c46-a7a6-8c77f56c9f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28954
13810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.2895413810
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2494610620
Short name T1261
Test name
Test status
Simulation time 8375901813 ps
CPU time 12.5 seconds
Started May 21 01:07:50 PM PDT 24
Finished May 21 01:08:04 PM PDT 24
Peak memory 205348 kb
Host smart-00f6eda6-1e6a-4cf6-909f-c7f3eabd92f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24946
10620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2494610620
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1331987679
Short name T1483
Test name
Test status
Simulation time 9339882180 ps
CPU time 13.23 seconds
Started May 21 01:07:51 PM PDT 24
Finished May 21 01:08:06 PM PDT 24
Peak memory 205360 kb
Host smart-036e3c5a-7415-4677-9a42-54f2c6686901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13319
87679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1331987679
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.141526718
Short name T685
Test name
Test status
Simulation time 8368881500 ps
CPU time 11.25 seconds
Started May 21 01:07:52 PM PDT 24
Finished May 21 01:08:05 PM PDT 24
Peak memory 205296 kb
Host smart-753961b9-2e7a-453d-b73f-d8d95b72052e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14152
6718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.141526718
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1917359135
Short name T59
Test name
Test status
Simulation time 8412865388 ps
CPU time 12.32 seconds
Started May 21 01:07:49 PM PDT 24
Finished May 21 01:08:03 PM PDT 24
Peak memory 205412 kb
Host smart-19610512-e083-454c-9e4d-13d5f075242a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19173
59135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1917359135
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.763358572
Short name T1602
Test name
Test status
Simulation time 9010524592 ps
CPU time 12.93 seconds
Started May 21 01:07:51 PM PDT 24
Finished May 21 01:08:06 PM PDT 24
Peak memory 205616 kb
Host smart-66d104bf-a820-4401-b82b-303d4b8c4c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76335
8572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.763358572
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.466625617
Short name T1365
Test name
Test status
Simulation time 8389902683 ps
CPU time 11.71 seconds
Started May 21 01:07:52 PM PDT 24
Finished May 21 01:08:06 PM PDT 24
Peak memory 205348 kb
Host smart-f3096fdb-8830-41d8-afb5-c8e2ff013f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46662
5617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.466625617
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3509809555
Short name T1470
Test name
Test status
Simulation time 8386446146 ps
CPU time 10.83 seconds
Started May 21 01:07:55 PM PDT 24
Finished May 21 01:08:07 PM PDT 24
Peak memory 205392 kb
Host smart-44b06619-0c56-4d14-8a3b-ab463fa618df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35098
09555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3509809555
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.502474916
Short name T1481
Test name
Test status
Simulation time 8402188696 ps
CPU time 12.48 seconds
Started May 21 01:07:56 PM PDT 24
Finished May 21 01:08:11 PM PDT 24
Peak memory 205304 kb
Host smart-b1ae7547-b1a3-4df9-b8ed-f0f86fd07305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50247
4916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.502474916
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.1788175424
Short name T1415
Test name
Test status
Simulation time 8421105028 ps
CPU time 11.39 seconds
Started May 21 01:07:51 PM PDT 24
Finished May 21 01:08:05 PM PDT 24
Peak memory 205328 kb
Host smart-42c910c8-fa66-4fd7-82ea-56900be57176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17881
75424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1788175424
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.579246731
Short name T301
Test name
Test status
Simulation time 11561950955 ps
CPU time 16.57 seconds
Started May 21 01:07:51 PM PDT 24
Finished May 21 01:08:10 PM PDT 24
Peak memory 205264 kb
Host smart-d8271fa4-8a73-4b9e-bb01-6e1e9a5fa8e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57924
6731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.579246731
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.3868756708
Short name T1175
Test name
Test status
Simulation time 8420046503 ps
CPU time 11.53 seconds
Started May 21 01:07:51 PM PDT 24
Finished May 21 01:08:05 PM PDT 24
Peak memory 205280 kb
Host smart-c9963299-be60-476d-930e-b6f7d588958d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38687
56708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.3868756708
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3913629249
Short name T1008
Test name
Test status
Simulation time 8372242883 ps
CPU time 13.08 seconds
Started May 21 01:07:50 PM PDT 24
Finished May 21 01:08:06 PM PDT 24
Peak memory 205392 kb
Host smart-4109844a-ba14-4933-a549-c294aad92ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39136
29249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3913629249
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.2368171877
Short name T128
Test name
Test status
Simulation time 8413579562 ps
CPU time 12.11 seconds
Started May 21 01:07:53 PM PDT 24
Finished May 21 01:08:07 PM PDT 24
Peak memory 205404 kb
Host smart-0ed4e339-09e4-401c-af5b-80c7191aa1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23681
71877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2368171877
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.1906535441
Short name T1102
Test name
Test status
Simulation time 8456021735 ps
CPU time 11.04 seconds
Started May 21 01:07:55 PM PDT 24
Finished May 21 01:08:08 PM PDT 24
Peak memory 205312 kb
Host smart-d402a593-bf4a-4eac-b697-56dedd3e5fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19065
35441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.1906535441
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.2730756083
Short name T1690
Test name
Test status
Simulation time 8420242610 ps
CPU time 11.54 seconds
Started May 21 01:07:50 PM PDT 24
Finished May 21 01:08:03 PM PDT 24
Peak memory 205428 kb
Host smart-a250154d-3046-4757-9070-12ed28d41dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27307
56083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.2730756083
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.280398496
Short name T1720
Test name
Test status
Simulation time 8379101415 ps
CPU time 12.85 seconds
Started May 21 01:07:51 PM PDT 24
Finished May 21 01:08:06 PM PDT 24
Peak memory 205348 kb
Host smart-33979d30-a7ef-449d-8a6c-4d04579203c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28039
8496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.280398496
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_eop_single_bit_handling.1475724995
Short name T1717
Test name
Test status
Simulation time 8447969172 ps
CPU time 11.88 seconds
Started May 21 01:07:50 PM PDT 24
Finished May 21 01:08:03 PM PDT 24
Peak memory 205428 kb
Host smart-565a8fc7-b186-4882-8529-e6f46cd2f684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14757
24995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_eop_single_bit_handling.1475724995
Directory /workspace/16.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.3443108466
Short name T739
Test name
Test status
Simulation time 8377301005 ps
CPU time 11.56 seconds
Started May 21 01:07:52 PM PDT 24
Finished May 21 01:08:05 PM PDT 24
Peak memory 205376 kb
Host smart-8d3069e3-e90b-4a5b-80c2-079c808718bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34431
08466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.3443108466
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.611707956
Short name T405
Test name
Test status
Simulation time 8373220238 ps
CPU time 11.48 seconds
Started May 21 01:08:00 PM PDT 24
Finished May 21 01:08:13 PM PDT 24
Peak memory 205312 kb
Host smart-bf5f0ad6-3565-4f2f-a5a9-2a9b71fed87b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61170
7956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.611707956
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.1251088663
Short name T114
Test name
Test status
Simulation time 30363511132 ps
CPU time 72.07 seconds
Started May 21 01:07:54 PM PDT 24
Finished May 21 01:09:07 PM PDT 24
Peak memory 205384 kb
Host smart-051c5ac7-010a-4021-8430-7dbedc386ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12510
88663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.1251088663
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3319184865
Short name T1498
Test name
Test status
Simulation time 8413510118 ps
CPU time 11.49 seconds
Started May 21 01:07:49 PM PDT 24
Finished May 21 01:08:01 PM PDT 24
Peak memory 205304 kb
Host smart-57201e4f-0bc9-48ab-aae2-77c2c3d8dca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33191
84865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3319184865
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.3274240553
Short name T297
Test name
Test status
Simulation time 8410431341 ps
CPU time 11.74 seconds
Started May 21 01:07:51 PM PDT 24
Finished May 21 01:08:06 PM PDT 24
Peak memory 205336 kb
Host smart-8c2fd86a-3a90-447d-9235-e1e0f056d244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32742
40553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.3274240553
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.447549568
Short name T429
Test name
Test status
Simulation time 8403712562 ps
CPU time 13.19 seconds
Started May 21 01:07:50 PM PDT 24
Finished May 21 01:08:05 PM PDT 24
Peak memory 205320 kb
Host smart-5d0ccff9-030a-4085-b774-d51be80324e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44754
9568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.447549568
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.364725353
Short name T1479
Test name
Test status
Simulation time 8362343393 ps
CPU time 11.8 seconds
Started May 21 01:07:50 PM PDT 24
Finished May 21 01:08:04 PM PDT 24
Peak memory 205372 kb
Host smart-cb6cdc4a-2a06-43aa-9814-9b004d7cabf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36472
5353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.364725353
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.2227926568
Short name T779
Test name
Test status
Simulation time 8376963945 ps
CPU time 13.15 seconds
Started May 21 01:07:55 PM PDT 24
Finished May 21 01:08:11 PM PDT 24
Peak memory 205388 kb
Host smart-e3e1b350-31e0-4121-a99e-b9f4dafbb917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22279
26568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.2227926568
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_smoke.2799926038
Short name T715
Test name
Test status
Simulation time 8455757826 ps
CPU time 11.72 seconds
Started May 21 01:07:43 PM PDT 24
Finished May 21 01:07:56 PM PDT 24
Peak memory 205284 kb
Host smart-6ed577ee-47ad-4d7a-b310-020d60bc4c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27999
26038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2799926038
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.3007894772
Short name T309
Test name
Test status
Simulation time 8371421103 ps
CPU time 11.55 seconds
Started May 21 01:07:50 PM PDT 24
Finished May 21 01:08:03 PM PDT 24
Peak memory 205424 kb
Host smart-9f9d9500-c4b6-40fb-80aa-1a6723c26ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30078
94772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.3007894772
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.1571110019
Short name T1283
Test name
Test status
Simulation time 8393430351 ps
CPU time 12.73 seconds
Started May 21 01:07:53 PM PDT 24
Finished May 21 01:08:07 PM PDT 24
Peak memory 205340 kb
Host smart-113e9b5c-8f95-4ba1-9edc-9af9e2136603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15711
10019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.1571110019
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.4148408477
Short name T1496
Test name
Test status
Simulation time 8464894719 ps
CPU time 13.15 seconds
Started May 21 01:08:06 PM PDT 24
Finished May 21 01:08:20 PM PDT 24
Peak memory 205376 kb
Host smart-deecdab9-ffed-4cf4-a26b-54bc8ef88fd1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4148408477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.4148408477
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.2016722772
Short name T469
Test name
Test status
Simulation time 8378334927 ps
CPU time 12.12 seconds
Started May 21 01:08:09 PM PDT 24
Finished May 21 01:08:23 PM PDT 24
Peak memory 205348 kb
Host smart-c234b202-226b-4d01-b7ce-a5a2d67270cc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2016722772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.2016722772
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.1246703018
Short name T1673
Test name
Test status
Simulation time 8437614776 ps
CPU time 13.02 seconds
Started May 21 01:08:04 PM PDT 24
Finished May 21 01:08:18 PM PDT 24
Peak memory 205448 kb
Host smart-b680c365-253e-4cd0-9b95-b9906cb78d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12467
03018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.1246703018
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3026507911
Short name T540
Test name
Test status
Simulation time 8380827461 ps
CPU time 12.04 seconds
Started May 21 01:07:55 PM PDT 24
Finished May 21 01:08:09 PM PDT 24
Peak memory 205356 kb
Host smart-7bc032c0-15b2-45a9-a07b-6e12ad87c31c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30265
07911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3026507911
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.2435337181
Short name T1119
Test name
Test status
Simulation time 8413562458 ps
CPU time 12.09 seconds
Started May 21 01:07:55 PM PDT 24
Finished May 21 01:08:09 PM PDT 24
Peak memory 205200 kb
Host smart-10e43b4d-d5bb-4ab3-9b44-b55c40d9d927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24353
37181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.2435337181
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1334809796
Short name T1705
Test name
Test status
Simulation time 8628224859 ps
CPU time 13.72 seconds
Started May 21 01:07:57 PM PDT 24
Finished May 21 01:08:13 PM PDT 24
Peak memory 205348 kb
Host smart-b2441797-837b-4933-8389-c8aa3167e3ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13348
09796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1334809796
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.1962108268
Short name T1085
Test name
Test status
Simulation time 8371392793 ps
CPU time 12.69 seconds
Started May 21 01:07:53 PM PDT 24
Finished May 21 01:08:08 PM PDT 24
Peak memory 205396 kb
Host smart-48908197-7940-4cbc-8a54-17d1419cbdcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19621
08268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.1962108268
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.3492412752
Short name T344
Test name
Test status
Simulation time 8382864631 ps
CPU time 11.9 seconds
Started May 21 01:08:03 PM PDT 24
Finished May 21 01:08:16 PM PDT 24
Peak memory 205304 kb
Host smart-13b88243-9e91-4cac-95c1-765e1090a682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34924
12752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.3492412752
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.1005548257
Short name T754
Test name
Test status
Simulation time 9087899851 ps
CPU time 13.31 seconds
Started May 21 01:07:56 PM PDT 24
Finished May 21 01:08:12 PM PDT 24
Peak memory 205324 kb
Host smart-ffb3b5a8-a590-4376-a262-8a56cb8006fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10055
48257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.1005548257
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.12647469
Short name T1108
Test name
Test status
Simulation time 8387391650 ps
CPU time 11.97 seconds
Started May 21 01:07:58 PM PDT 24
Finished May 21 01:08:12 PM PDT 24
Peak memory 205392 kb
Host smart-909ac9e7-345a-4ee4-b0a5-6873a0cf069c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12647
469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.12647469
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.374061542
Short name T1266
Test name
Test status
Simulation time 8446868935 ps
CPU time 12.45 seconds
Started May 21 01:08:02 PM PDT 24
Finished May 21 01:08:15 PM PDT 24
Peak memory 205328 kb
Host smart-cb8ccf52-11b2-475a-b3ec-ad947b14f830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37406
1542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.374061542
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3097470684
Short name T1355
Test name
Test status
Simulation time 8399850329 ps
CPU time 11.68 seconds
Started May 21 01:08:01 PM PDT 24
Finished May 21 01:08:14 PM PDT 24
Peak memory 205212 kb
Host smart-8de5c235-8bb4-4cdf-8047-d98a1e2bbbf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30974
70684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3097470684
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.2016266975
Short name T1667
Test name
Test status
Simulation time 8473639487 ps
CPU time 11.74 seconds
Started May 21 01:08:03 PM PDT 24
Finished May 21 01:08:16 PM PDT 24
Peak memory 205316 kb
Host smart-70c87c48-02d2-4055-a4bf-2419fd2ac0d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20162
66975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.2016266975
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.1701670847
Short name T1395
Test name
Test status
Simulation time 8401744811 ps
CPU time 14.37 seconds
Started May 21 01:07:56 PM PDT 24
Finished May 21 01:08:12 PM PDT 24
Peak memory 205356 kb
Host smart-79872192-add5-4699-86b3-e1a564424c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17016
70847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.1701670847
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.3998605908
Short name T457
Test name
Test status
Simulation time 11557626442 ps
CPU time 15.42 seconds
Started May 21 01:07:56 PM PDT 24
Finished May 21 01:08:14 PM PDT 24
Peak memory 205292 kb
Host smart-6727f99d-70dc-4907-b45e-967b26e8a540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39986
05908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.3998605908
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.775807983
Short name T1264
Test name
Test status
Simulation time 8442771299 ps
CPU time 12.02 seconds
Started May 21 01:07:54 PM PDT 24
Finished May 21 01:08:08 PM PDT 24
Peak memory 205272 kb
Host smart-6b6dca7c-1123-41b4-acba-915a32d29c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77580
7983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.775807983
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.554896746
Short name T1172
Test name
Test status
Simulation time 8379852317 ps
CPU time 12.83 seconds
Started May 21 01:08:05 PM PDT 24
Finished May 21 01:08:19 PM PDT 24
Peak memory 205276 kb
Host smart-24a55d3f-6bad-4967-8d65-a3121c1be8eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55489
6746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.554896746
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.928066285
Short name T1482
Test name
Test status
Simulation time 8407992817 ps
CPU time 11.97 seconds
Started May 21 01:08:00 PM PDT 24
Finished May 21 01:08:13 PM PDT 24
Peak memory 205400 kb
Host smart-ea9c5491-b8c3-408d-b14f-35efc34912e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92806
6285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.928066285
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1244482779
Short name T1709
Test name
Test status
Simulation time 8395513695 ps
CPU time 12.28 seconds
Started May 21 01:07:55 PM PDT 24
Finished May 21 01:08:09 PM PDT 24
Peak memory 205408 kb
Host smart-13777055-1881-4f12-b36b-a35ec06479cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12444
82779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1244482779
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.285766105
Short name T155
Test name
Test status
Simulation time 8454464394 ps
CPU time 12.67 seconds
Started May 21 01:08:00 PM PDT 24
Finished May 21 01:08:14 PM PDT 24
Peak memory 205432 kb
Host smart-ff96ad6b-5a74-43da-9bfd-24e797299d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28576
6105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.285766105
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_eop_single_bit_handling.1767505078
Short name T1039
Test name
Test status
Simulation time 8439404411 ps
CPU time 11.25 seconds
Started May 21 01:08:00 PM PDT 24
Finished May 21 01:08:13 PM PDT 24
Peak memory 205380 kb
Host smart-578c79c6-bd17-41aa-9938-c69c4a31c4ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17675
05078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_eop_single_bit_handling.1767505078
Directory /workspace/17.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3953495013
Short name T641
Test name
Test status
Simulation time 8377234153 ps
CPU time 11.06 seconds
Started May 21 01:08:03 PM PDT 24
Finished May 21 01:08:16 PM PDT 24
Peak memory 205324 kb
Host smart-e2ef8e51-99c3-4939-a4cb-3c16e98bdba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39534
95013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.3953495013
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.1939869170
Short name T1342
Test name
Test status
Simulation time 8386849503 ps
CPU time 11.63 seconds
Started May 21 01:08:02 PM PDT 24
Finished May 21 01:08:15 PM PDT 24
Peak memory 205272 kb
Host smart-fa970ac4-cffb-446e-9415-bd5d1fbef4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19398
69170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.1939869170
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3729870432
Short name T1478
Test name
Test status
Simulation time 19641295750 ps
CPU time 39.88 seconds
Started May 21 01:07:56 PM PDT 24
Finished May 21 01:08:38 PM PDT 24
Peak memory 205440 kb
Host smart-7a86d68f-9b11-4d1a-b0fa-b2aef9ef6b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37298
70432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3729870432
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.3375756412
Short name T423
Test name
Test status
Simulation time 8387375354 ps
CPU time 11.44 seconds
Started May 21 01:08:01 PM PDT 24
Finished May 21 01:08:14 PM PDT 24
Peak memory 205348 kb
Host smart-c44f276e-a87d-4daa-81b8-700cb820bfba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33757
56412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.3375756412
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2109943901
Short name T460
Test name
Test status
Simulation time 8436439247 ps
CPU time 11.17 seconds
Started May 21 01:07:58 PM PDT 24
Finished May 21 01:08:11 PM PDT 24
Peak memory 205364 kb
Host smart-ea59c696-40a7-4960-947c-68f51d964989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21099
43901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2109943901
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.528270837
Short name T718
Test name
Test status
Simulation time 8387027003 ps
CPU time 12.83 seconds
Started May 21 01:07:57 PM PDT 24
Finished May 21 01:08:12 PM PDT 24
Peak memory 205336 kb
Host smart-31bfcb4d-f7e5-4601-8da9-9211b3a4941e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52827
0837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.528270837
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.3859894665
Short name T649
Test name
Test status
Simulation time 8366503352 ps
CPU time 14.1 seconds
Started May 21 01:08:01 PM PDT 24
Finished May 21 01:08:17 PM PDT 24
Peak memory 205356 kb
Host smart-7be184bd-fee1-4533-8943-c297467008fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38598
94665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.3859894665
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.2421382543
Short name T650
Test name
Test status
Simulation time 8379131407 ps
CPU time 13.98 seconds
Started May 21 01:08:03 PM PDT 24
Finished May 21 01:08:19 PM PDT 24
Peak memory 205336 kb
Host smart-7902d1cc-641d-4676-8ead-82e9713ceff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24213
82543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.2421382543
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.4267021614
Short name T1180
Test name
Test status
Simulation time 8376970774 ps
CPU time 12.54 seconds
Started May 21 01:08:03 PM PDT 24
Finished May 21 01:08:17 PM PDT 24
Peak memory 205400 kb
Host smart-4c8b8001-c6a5-4664-91b0-93baab5d2da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42670
21614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.4267021614
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3997234503
Short name T1669
Test name
Test status
Simulation time 8455988705 ps
CPU time 11.91 seconds
Started May 21 01:07:55 PM PDT 24
Finished May 21 01:08:08 PM PDT 24
Peak memory 205236 kb
Host smart-29c3e2c2-ebc2-4406-9f36-31f205364027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39972
34503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3997234503
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.3975536958
Short name T745
Test name
Test status
Simulation time 8438113076 ps
CPU time 12.72 seconds
Started May 21 01:08:03 PM PDT 24
Finished May 21 01:08:18 PM PDT 24
Peak memory 205364 kb
Host smart-8f7bc02a-7392-4c8d-881d-0ade339b6700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39755
36958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.3975536958
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2876486458
Short name T681
Test name
Test status
Simulation time 8390355618 ps
CPU time 11.83 seconds
Started May 21 01:08:09 PM PDT 24
Finished May 21 01:08:22 PM PDT 24
Peak memory 205332 kb
Host smart-e14c78e9-52dd-48ba-989d-51a47be37e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28764
86458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2876486458
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.3521107028
Short name T533
Test name
Test status
Simulation time 8472336699 ps
CPU time 12.87 seconds
Started May 21 01:08:16 PM PDT 24
Finished May 21 01:08:31 PM PDT 24
Peak memory 205320 kb
Host smart-e7f7a3e4-1224-4d91-baea-913d911d0b6b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3521107028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.3521107028
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.2868366390
Short name T1192
Test name
Test status
Simulation time 8386963879 ps
CPU time 11.08 seconds
Started May 21 01:08:19 PM PDT 24
Finished May 21 01:08:32 PM PDT 24
Peak memory 205312 kb
Host smart-26f91314-d601-419a-9fc6-6fcffc373511
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2868366390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.2868366390
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.3208663802
Short name T1662
Test name
Test status
Simulation time 8448504786 ps
CPU time 12.88 seconds
Started May 21 01:08:15 PM PDT 24
Finished May 21 01:08:28 PM PDT 24
Peak memory 205368 kb
Host smart-e0b3e4a3-4cfd-484d-a15d-8b3bd536fd9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32086
63802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.3208663802
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.3336956198
Short name T935
Test name
Test status
Simulation time 8382256664 ps
CPU time 11.22 seconds
Started May 21 01:08:02 PM PDT 24
Finished May 21 01:08:14 PM PDT 24
Peak memory 205432 kb
Host smart-5f919667-b557-45f3-ace3-75244599877c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33369
56198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.3336956198
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.4131111077
Short name T938
Test name
Test status
Simulation time 9346960276 ps
CPU time 13.57 seconds
Started May 21 01:08:04 PM PDT 24
Finished May 21 01:08:19 PM PDT 24
Peak memory 205296 kb
Host smart-a13fc017-722e-4bb8-a2d8-1c492e05abb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41311
11077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.4131111077
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.3862267418
Short name T511
Test name
Test status
Simulation time 8387162188 ps
CPU time 14.55 seconds
Started May 21 01:08:10 PM PDT 24
Finished May 21 01:08:26 PM PDT 24
Peak memory 205312 kb
Host smart-883ae81a-2626-46d9-90e0-f532dbb1f369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38622
67418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.3862267418
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.1495541099
Short name T829
Test name
Test status
Simulation time 8385539420 ps
CPU time 13.06 seconds
Started May 21 01:08:02 PM PDT 24
Finished May 21 01:08:17 PM PDT 24
Peak memory 205332 kb
Host smart-fa0b2d1c-59fc-4a87-95f9-b3490e4ce7e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14955
41099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1495541099
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.3507619305
Short name T1178
Test name
Test status
Simulation time 9022195962 ps
CPU time 12.64 seconds
Started May 21 01:08:05 PM PDT 24
Finished May 21 01:08:19 PM PDT 24
Peak memory 205284 kb
Host smart-448e906c-99af-4efd-9364-a3048d3a6482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35076
19305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.3507619305
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.239000055
Short name T913
Test name
Test status
Simulation time 8525863212 ps
CPU time 13.93 seconds
Started May 21 01:08:05 PM PDT 24
Finished May 21 01:08:20 PM PDT 24
Peak memory 205316 kb
Host smart-db49bb23-41cd-4663-8433-ca6573ca77f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23900
0055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.239000055
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.3628898037
Short name T729
Test name
Test status
Simulation time 8447950403 ps
CPU time 13.2 seconds
Started May 21 01:08:17 PM PDT 24
Finished May 21 01:08:32 PM PDT 24
Peak memory 205368 kb
Host smart-22c38341-aa1d-436f-9e83-08cea6a1683c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36288
98037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.3628898037
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3753586317
Short name T838
Test name
Test status
Simulation time 8394284960 ps
CPU time 11.44 seconds
Started May 21 01:08:16 PM PDT 24
Finished May 21 01:08:29 PM PDT 24
Peak memory 205384 kb
Host smart-64634d30-4898-42cb-8798-289faacc8a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37535
86317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3753586317
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.2741925004
Short name T1259
Test name
Test status
Simulation time 8476357332 ps
CPU time 13.34 seconds
Started May 21 01:08:10 PM PDT 24
Finished May 21 01:08:25 PM PDT 24
Peak memory 205248 kb
Host smart-3919e86c-0666-4c1b-8757-7a7ba23a0f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27419
25004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2741925004
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.292920170
Short name T1198
Test name
Test status
Simulation time 11530346783 ps
CPU time 15.45 seconds
Started May 21 01:08:08 PM PDT 24
Finished May 21 01:08:25 PM PDT 24
Peak memory 205348 kb
Host smart-8d2582a5-d65a-48ec-a738-320047ffade6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29292
0170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.292920170
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.809277791
Short name T1181
Test name
Test status
Simulation time 8422177492 ps
CPU time 12.38 seconds
Started May 21 01:08:09 PM PDT 24
Finished May 21 01:08:23 PM PDT 24
Peak memory 205400 kb
Host smart-b6a0fcab-cf8c-40a9-9db8-c7ba27d3753e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80927
7791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.809277791
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.838515861
Short name T751
Test name
Test status
Simulation time 8388644260 ps
CPU time 13.5 seconds
Started May 21 01:08:09 PM PDT 24
Finished May 21 01:08:24 PM PDT 24
Peak memory 205356 kb
Host smart-75663c36-7a3f-4bfa-bc2e-1e4f90b03533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83851
5861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.838515861
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.1344825528
Short name T1695
Test name
Test status
Simulation time 8483379242 ps
CPU time 11.76 seconds
Started May 21 01:08:09 PM PDT 24
Finished May 21 01:08:23 PM PDT 24
Peak memory 205360 kb
Host smart-1f56d253-c36a-4aaf-b49b-2c071df1e62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13448
25528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1344825528
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.4136012296
Short name T1317
Test name
Test status
Simulation time 8415448377 ps
CPU time 10.91 seconds
Started May 21 01:08:13 PM PDT 24
Finished May 21 01:08:24 PM PDT 24
Peak memory 205360 kb
Host smart-cece1c87-aed9-4f15-8f60-cbe23187625b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41360
12296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.4136012296
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.2617370286
Short name T621
Test name
Test status
Simulation time 8413379662 ps
CPU time 11.12 seconds
Started May 21 01:08:11 PM PDT 24
Finished May 21 01:08:23 PM PDT 24
Peak memory 205380 kb
Host smart-cde274c5-a165-4977-9688-61b56b645c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26173
70286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.2617370286
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.3972289086
Short name T402
Test name
Test status
Simulation time 8375215204 ps
CPU time 12.28 seconds
Started May 21 01:08:09 PM PDT 24
Finished May 21 01:08:22 PM PDT 24
Peak memory 205292 kb
Host smart-716e276f-8682-45f5-82c4-0d64e300e489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39722
89086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.3972289086
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_eop_single_bit_handling.445686595
Short name T1162
Test name
Test status
Simulation time 8422230272 ps
CPU time 13.94 seconds
Started May 21 01:08:18 PM PDT 24
Finished May 21 01:08:34 PM PDT 24
Peak memory 205288 kb
Host smart-4ec0100e-9413-4307-a986-54189b36d6c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44568
6595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_eop_single_bit_handling.445686595
Directory /workspace/18.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3724611998
Short name T1718
Test name
Test status
Simulation time 8388075934 ps
CPU time 11.54 seconds
Started May 21 01:08:10 PM PDT 24
Finished May 21 01:08:23 PM PDT 24
Peak memory 205352 kb
Host smart-6c1c5fa3-7f25-43d4-ade5-084dce946590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37246
11998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3724611998
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.2637323798
Short name T15
Test name
Test status
Simulation time 23351634368 ps
CPU time 45.12 seconds
Started May 21 01:08:13 PM PDT 24
Finished May 21 01:08:59 PM PDT 24
Peak memory 205384 kb
Host smart-62df434e-d208-4e66-b4be-a15a91144c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26373
23798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.2637323798
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.4218194167
Short name T1145
Test name
Test status
Simulation time 8454004982 ps
CPU time 12.53 seconds
Started May 21 01:08:09 PM PDT 24
Finished May 21 01:08:24 PM PDT 24
Peak memory 205408 kb
Host smart-1d0c4057-1bc2-4241-9fd3-dc8d594b923e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42181
94167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.4218194167
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.191620709
Short name T30
Test name
Test status
Simulation time 8464515199 ps
CPU time 14.2 seconds
Started May 21 01:08:12 PM PDT 24
Finished May 21 01:08:27 PM PDT 24
Peak memory 205388 kb
Host smart-20c647d9-1c5f-495b-8757-b073246e010a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19162
0709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.191620709
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.186078619
Short name T1427
Test name
Test status
Simulation time 8369716658 ps
CPU time 11.3 seconds
Started May 21 01:08:09 PM PDT 24
Finished May 21 01:08:23 PM PDT 24
Peak memory 205248 kb
Host smart-da49fde4-7a4d-44b2-9c60-e17ca35985f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18607
8619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.186078619
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.4289000794
Short name T965
Test name
Test status
Simulation time 8377115702 ps
CPU time 12.65 seconds
Started May 21 01:08:16 PM PDT 24
Finished May 21 01:08:30 PM PDT 24
Peak memory 205368 kb
Host smart-d714ca5f-7577-4db9-a193-64bef8e2edc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42890
00794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.4289000794
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.461207161
Short name T881
Test name
Test status
Simulation time 8379780595 ps
CPU time 11.69 seconds
Started May 21 01:08:10 PM PDT 24
Finished May 21 01:08:24 PM PDT 24
Peak memory 205360 kb
Host smart-45aac28b-ef88-44d5-9fcc-adc12f031580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46120
7161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.461207161
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.415122371
Short name T908
Test name
Test status
Simulation time 8458997831 ps
CPU time 14.52 seconds
Started May 21 01:08:09 PM PDT 24
Finished May 21 01:08:25 PM PDT 24
Peak memory 205272 kb
Host smart-980967d6-b86d-4b15-aa64-68a7c03e3ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41512
2371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.415122371
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.568181797
Short name T799
Test name
Test status
Simulation time 8386294627 ps
CPU time 12.16 seconds
Started May 21 01:08:08 PM PDT 24
Finished May 21 01:08:22 PM PDT 24
Peak memory 205336 kb
Host smart-efdcf3a8-c83a-4063-a66b-b6a5578a136b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56818
1797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.568181797
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.463823889
Short name T1243
Test name
Test status
Simulation time 8387992284 ps
CPU time 14.59 seconds
Started May 21 01:08:09 PM PDT 24
Finished May 21 01:08:26 PM PDT 24
Peak memory 205356 kb
Host smart-76925351-cf2c-4e85-8ce5-c6f3de4752e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46382
3889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.463823889
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.1214822158
Short name T1132
Test name
Test status
Simulation time 8465122606 ps
CPU time 12.37 seconds
Started May 21 01:08:24 PM PDT 24
Finished May 21 01:08:37 PM PDT 24
Peak memory 205336 kb
Host smart-507189ea-12b5-4af0-97d7-555711d30f63
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1214822158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.1214822158
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.3499936972
Short name T668
Test name
Test status
Simulation time 8376475684 ps
CPU time 11.8 seconds
Started May 21 01:08:27 PM PDT 24
Finished May 21 01:08:40 PM PDT 24
Peak memory 205376 kb
Host smart-fa7401fe-958e-490e-b584-6044ed85c03f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3499936972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.3499936972
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.2565319691
Short name T476
Test name
Test status
Simulation time 8414430919 ps
CPU time 11.07 seconds
Started May 21 01:08:22 PM PDT 24
Finished May 21 01:08:34 PM PDT 24
Peak memory 205356 kb
Host smart-1595eed4-60f2-4343-9567-39a6174c211d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25653
19691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.2565319691
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.100585028
Short name T1672
Test name
Test status
Simulation time 8384214722 ps
CPU time 11.89 seconds
Started May 21 01:08:17 PM PDT 24
Finished May 21 01:08:31 PM PDT 24
Peak memory 205272 kb
Host smart-0200f199-eb4b-4900-a47e-8f4ce099ef8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10058
5028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.100585028
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.1201929087
Short name T1626
Test name
Test status
Simulation time 8404836867 ps
CPU time 10.88 seconds
Started May 21 01:08:16 PM PDT 24
Finished May 21 01:08:29 PM PDT 24
Peak memory 205280 kb
Host smart-923936c6-bb44-4850-aafe-7d7e8616108e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12019
29087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.1201929087
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.3830407192
Short name T1570
Test name
Test status
Simulation time 8409640992 ps
CPU time 11.45 seconds
Started May 21 01:08:18 PM PDT 24
Finished May 21 01:08:31 PM PDT 24
Peak memory 205296 kb
Host smart-6d31b317-6189-4ec2-b5df-80cd722dffc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38304
07192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.3830407192
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.3476315191
Short name T1420
Test name
Test status
Simulation time 8374705746 ps
CPU time 11.32 seconds
Started May 21 01:08:17 PM PDT 24
Finished May 21 01:08:30 PM PDT 24
Peak memory 205288 kb
Host smart-f1ccf9b2-0225-4af1-b1df-a6efa853cddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34763
15191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.3476315191
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.539452511
Short name T845
Test name
Test status
Simulation time 8387081110 ps
CPU time 12.47 seconds
Started May 21 01:08:27 PM PDT 24
Finished May 21 01:08:41 PM PDT 24
Peak memory 205300 kb
Host smart-54d5c86a-5121-4198-b232-ab59c3cb62d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53945
2511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.539452511
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.311162854
Short name T1240
Test name
Test status
Simulation time 9251670025 ps
CPU time 16.4 seconds
Started May 21 01:08:18 PM PDT 24
Finished May 21 01:08:36 PM PDT 24
Peak memory 205276 kb
Host smart-3e0bf119-ca02-4b31-85a6-18f45326f75d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31116
2854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.311162854
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.407519741
Short name T496
Test name
Test status
Simulation time 8411099418 ps
CPU time 12.32 seconds
Started May 21 01:08:17 PM PDT 24
Finished May 21 01:08:32 PM PDT 24
Peak memory 205348 kb
Host smart-adb4f812-d844-4fcf-a375-35c3d0d9e00f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40751
9741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.407519741
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.2676147797
Short name T1312
Test name
Test status
Simulation time 8426281614 ps
CPU time 13.8 seconds
Started May 21 01:08:24 PM PDT 24
Finished May 21 01:08:38 PM PDT 24
Peak memory 205328 kb
Host smart-f307534a-79a0-4106-af83-2d01f5ae2e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26761
47797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.2676147797
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.26507436
Short name T1053
Test name
Test status
Simulation time 8372340398 ps
CPU time 11.63 seconds
Started May 21 01:08:23 PM PDT 24
Finished May 21 01:08:35 PM PDT 24
Peak memory 205220 kb
Host smart-2a71ddd1-3706-4c9a-acd5-48116c6cd1be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26507
436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.26507436
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.3077506040
Short name T282
Test name
Test status
Simulation time 8453984521 ps
CPU time 14.23 seconds
Started May 21 01:08:16 PM PDT 24
Finished May 21 01:08:33 PM PDT 24
Peak memory 205316 kb
Host smart-39ca67c8-4082-497d-94e2-a6282784925b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30775
06040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.3077506040
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.2768941465
Short name T536
Test name
Test status
Simulation time 8416094714 ps
CPU time 13.2 seconds
Started May 21 01:08:19 PM PDT 24
Finished May 21 01:08:34 PM PDT 24
Peak memory 205236 kb
Host smart-0923dbd1-db2f-40ee-8aef-42eb0531e014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27689
41465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.2768941465
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.1720650860
Short name T769
Test name
Test status
Simulation time 11535752663 ps
CPU time 18.05 seconds
Started May 21 01:08:16 PM PDT 24
Finished May 21 01:08:35 PM PDT 24
Peak memory 205356 kb
Host smart-fe146d02-d6a2-425a-91a9-e8398bc0c715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17206
50860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.1720650860
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.4092585030
Short name T1492
Test name
Test status
Simulation time 8433951552 ps
CPU time 12.81 seconds
Started May 21 01:08:16 PM PDT 24
Finished May 21 01:08:31 PM PDT 24
Peak memory 205368 kb
Host smart-84ae20b6-938e-46e0-862d-a0aa29bf6e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40925
85030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.4092585030
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.366757780
Short name T970
Test name
Test status
Simulation time 8395547306 ps
CPU time 13.42 seconds
Started May 21 01:08:16 PM PDT 24
Finished May 21 01:08:31 PM PDT 24
Peak memory 205380 kb
Host smart-55fbf214-e9f7-4823-a2a2-040dd2db339d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36675
7780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.366757780
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2553740607
Short name T1096
Test name
Test status
Simulation time 8409872655 ps
CPU time 10.78 seconds
Started May 21 01:08:15 PM PDT 24
Finished May 21 01:08:27 PM PDT 24
Peak memory 205344 kb
Host smart-c8cc8b0a-0e72-494e-ac1b-d9e9e2f8b14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25537
40607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2553740607
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.1263628471
Short name T471
Test name
Test status
Simulation time 8415964676 ps
CPU time 11.99 seconds
Started May 21 01:08:26 PM PDT 24
Finished May 21 01:08:39 PM PDT 24
Peak memory 205444 kb
Host smart-fd5c74bb-7ae6-4096-a804-e16016db9056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12636
28471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.1263628471
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3255564115
Short name T593
Test name
Test status
Simulation time 8401463350 ps
CPU time 12.18 seconds
Started May 21 01:08:22 PM PDT 24
Finished May 21 01:08:34 PM PDT 24
Peak memory 205272 kb
Host smart-4785cf3f-855d-4c4d-804d-f3c9c48ccd8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32555
64115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3255564115
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.939856077
Short name T942
Test name
Test status
Simulation time 8436598230 ps
CPU time 11.77 seconds
Started May 21 01:08:25 PM PDT 24
Finished May 21 01:08:38 PM PDT 24
Peak memory 205412 kb
Host smart-65a0f401-ab1f-4f55-b2a7-9979672a611c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93985
6077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.939856077
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_eop_single_bit_handling.1218632391
Short name T841
Test name
Test status
Simulation time 8416232508 ps
CPU time 11.71 seconds
Started May 21 01:08:26 PM PDT 24
Finished May 21 01:08:40 PM PDT 24
Peak memory 205380 kb
Host smart-01638cff-ebfa-4c1e-b74c-efbea67f4dc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12186
32391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_eop_single_bit_handling.1218632391
Directory /workspace/19.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.3274820498
Short name T1208
Test name
Test status
Simulation time 8372791943 ps
CPU time 11.74 seconds
Started May 21 01:08:26 PM PDT 24
Finished May 21 01:08:40 PM PDT 24
Peak memory 205280 kb
Host smart-a608776e-70af-4ab6-a6f1-9e151ec31483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32748
20498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.3274820498
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.552104330
Short name T666
Test name
Test status
Simulation time 8370536732 ps
CPU time 12.16 seconds
Started May 21 01:08:27 PM PDT 24
Finished May 21 01:08:40 PM PDT 24
Peak memory 205360 kb
Host smart-ad3206e2-e84d-45bb-9461-e3468671ede6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55210
4330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.552104330
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.2207176133
Short name T227
Test name
Test status
Simulation time 16453831102 ps
CPU time 28.89 seconds
Started May 21 01:08:24 PM PDT 24
Finished May 21 01:08:54 PM PDT 24
Peak memory 205412 kb
Host smart-08810c48-366d-4be8-a22e-011a34170fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22071
76133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.2207176133
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.1916529637
Short name T1442
Test name
Test status
Simulation time 8417717494 ps
CPU time 12.12 seconds
Started May 21 01:08:24 PM PDT 24
Finished May 21 01:08:38 PM PDT 24
Peak memory 205304 kb
Host smart-ec333442-8c0e-4f55-9383-a1810f0a6ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19165
29637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.1916529637
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.2782809279
Short name T211
Test name
Test status
Simulation time 8462362374 ps
CPU time 13.31 seconds
Started May 21 01:08:26 PM PDT 24
Finished May 21 01:08:40 PM PDT 24
Peak memory 205328 kb
Host smart-d2c2ace3-6639-4ef8-b43d-2be3dff3d347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27828
09279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.2782809279
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.3124327132
Short name T1685
Test name
Test status
Simulation time 8394997434 ps
CPU time 12.01 seconds
Started May 21 01:08:24 PM PDT 24
Finished May 21 01:08:37 PM PDT 24
Peak memory 205344 kb
Host smart-25b95586-a344-4670-aa4d-40751b023fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31243
27132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.3124327132
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.3132738679
Short name T850
Test name
Test status
Simulation time 8369132045 ps
CPU time 12.47 seconds
Started May 21 01:08:23 PM PDT 24
Finished May 21 01:08:36 PM PDT 24
Peak memory 205328 kb
Host smart-57f1f623-73a8-4014-8ea3-df177e2a4b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31327
38679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.3132738679
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.1769811365
Short name T343
Test name
Test status
Simulation time 8389765107 ps
CPU time 10.95 seconds
Started May 21 01:08:25 PM PDT 24
Finished May 21 01:08:37 PM PDT 24
Peak memory 205240 kb
Host smart-bdaae571-9356-4cfa-a622-cccbd4f58311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17698
11365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1769811365
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.1244704257
Short name T824
Test name
Test status
Simulation time 8381634320 ps
CPU time 11.83 seconds
Started May 21 01:08:22 PM PDT 24
Finished May 21 01:08:35 PM PDT 24
Peak memory 205392 kb
Host smart-d858bbe4-d49f-4b55-b9ba-66c127abb9cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12447
04257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1244704257
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.2754811713
Short name T889
Test name
Test status
Simulation time 8518844603 ps
CPU time 12.96 seconds
Started May 21 01:08:16 PM PDT 24
Finished May 21 01:08:31 PM PDT 24
Peak memory 205336 kb
Host smart-1a0bc0d8-ff6f-4230-b2de-f51d73ba086a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27548
11713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.2754811713
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.2750134125
Short name T1416
Test name
Test status
Simulation time 8391353016 ps
CPU time 12.71 seconds
Started May 21 01:08:24 PM PDT 24
Finished May 21 01:08:38 PM PDT 24
Peak memory 205564 kb
Host smart-1339ecd9-db78-4e5e-a460-e1d6d2a4c8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27501
34125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.2750134125
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.1460007772
Short name T1350
Test name
Test status
Simulation time 8402613786 ps
CPU time 11.91 seconds
Started May 21 01:08:24 PM PDT 24
Finished May 21 01:08:37 PM PDT 24
Peak memory 205368 kb
Host smart-8fe6cb18-07bd-497b-9d02-49ebf7862e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14600
07772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1460007772
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.1767600201
Short name T28
Test name
Test status
Simulation time 8474999907 ps
CPU time 13.21 seconds
Started May 21 01:05:12 PM PDT 24
Finished May 21 01:05:27 PM PDT 24
Peak memory 205372 kb
Host smart-3e93f3c7-52b2-48bf-98c7-cce830b13aa5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1767600201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.1767600201
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.3035842506
Short name T272
Test name
Test status
Simulation time 8380931938 ps
CPU time 12.62 seconds
Started May 21 01:05:10 PM PDT 24
Finished May 21 01:05:25 PM PDT 24
Peak memory 205428 kb
Host smart-055f053d-352c-4bc4-9aff-5a8e0be08433
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3035842506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.3035842506
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.227834137
Short name T212
Test name
Test status
Simulation time 8435627583 ps
CPU time 13.96 seconds
Started May 21 01:05:12 PM PDT 24
Finished May 21 01:05:28 PM PDT 24
Peak memory 205348 kb
Host smart-f85fa230-ce37-4e09-a271-7975fd51a4c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22783
4137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.227834137
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.235583327
Short name T777
Test name
Test status
Simulation time 8380740120 ps
CPU time 12.77 seconds
Started May 21 01:04:59 PM PDT 24
Finished May 21 01:05:13 PM PDT 24
Peak memory 205268 kb
Host smart-02ea1a37-fc82-4a95-8ed6-151909665cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23558
3327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.235583327
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.1745124419
Short name T40
Test name
Test status
Simulation time 9303161171 ps
CPU time 13.58 seconds
Started May 21 01:04:56 PM PDT 24
Finished May 21 01:05:11 PM PDT 24
Peak memory 205324 kb
Host smart-290b1627-fc45-4feb-938c-20310252640e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17451
24419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.1745124419
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.4204882079
Short name T1225
Test name
Test status
Simulation time 8367796741 ps
CPU time 11.89 seconds
Started May 21 01:05:05 PM PDT 24
Finished May 21 01:05:19 PM PDT 24
Peak memory 205396 kb
Host smart-015c8f6b-b220-47ee-b7b7-61623d5dbcef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42048
82079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.4204882079
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.1459526012
Short name T1267
Test name
Test status
Simulation time 8378847827 ps
CPU time 11.94 seconds
Started May 21 01:04:58 PM PDT 24
Finished May 21 01:05:12 PM PDT 24
Peak memory 205380 kb
Host smart-920421c0-623e-4051-a347-4907f091c4e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14595
26012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.1459526012
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.1045777131
Short name T1406
Test name
Test status
Simulation time 8388988997 ps
CPU time 14.1 seconds
Started May 21 01:04:58 PM PDT 24
Finished May 21 01:05:13 PM PDT 24
Peak memory 205368 kb
Host smart-f1ebb4fc-2bc4-4085-8630-1ef4e3c97835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10457
77131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.1045777131
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.3855834588
Short name T57
Test name
Test status
Simulation time 8439929567 ps
CPU time 12.88 seconds
Started May 21 01:05:10 PM PDT 24
Finished May 21 01:05:24 PM PDT 24
Peak memory 205392 kb
Host smart-04965ee4-9575-4b65-ad83-a40d969ac007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38558
34588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.3855834588
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2483495787
Short name T950
Test name
Test status
Simulation time 8416863757 ps
CPU time 10.85 seconds
Started May 21 01:05:13 PM PDT 24
Finished May 21 01:05:25 PM PDT 24
Peak memory 205344 kb
Host smart-ca52426c-3137-448b-a878-55c567b9a3f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24834
95787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2483495787
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.3898739130
Short name T1358
Test name
Test status
Simulation time 8390884316 ps
CPU time 12.2 seconds
Started May 21 01:04:59 PM PDT 24
Finished May 21 01:05:13 PM PDT 24
Peak memory 205272 kb
Host smart-683a2a6d-147a-47d2-a90a-9af4768b84fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38987
39130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.3898739130
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.2077026538
Short name T1110
Test name
Test status
Simulation time 8391745556 ps
CPU time 12.4 seconds
Started May 21 01:04:57 PM PDT 24
Finished May 21 01:05:10 PM PDT 24
Peak memory 205244 kb
Host smart-9eb62ec3-acf7-4fdc-a5ae-3dc910240ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20770
26538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.2077026538
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.1603561610
Short name T1037
Test name
Test status
Simulation time 11511329096 ps
CPU time 14.9 seconds
Started May 21 01:05:04 PM PDT 24
Finished May 21 01:05:21 PM PDT 24
Peak memory 205332 kb
Host smart-c8756da0-1c9c-45b6-a7b8-350e275d48d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16035
61610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.1603561610
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.275134459
Short name T2
Test name
Test status
Simulation time 8428679425 ps
CPU time 10.58 seconds
Started May 21 01:05:05 PM PDT 24
Finished May 21 01:05:18 PM PDT 24
Peak memory 205340 kb
Host smart-229ab9b7-4597-4bfc-a6c9-c9aa86b706a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27513
4459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.275134459
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3072691910
Short name T659
Test name
Test status
Simulation time 8415389940 ps
CPU time 11.48 seconds
Started May 21 01:05:03 PM PDT 24
Finished May 21 01:05:15 PM PDT 24
Peak memory 205360 kb
Host smart-70d08c7c-8086-4b46-977a-cb723f24c12e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30726
91910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3072691910
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.124681520
Short name T1040
Test name
Test status
Simulation time 8415701399 ps
CPU time 12.03 seconds
Started May 21 01:05:05 PM PDT 24
Finished May 21 01:05:19 PM PDT 24
Peak memory 205348 kb
Host smart-b8df4f4b-4e56-4034-8015-fade7b98bfe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12468
1520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.124681520
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.1674375040
Short name T1333
Test name
Test status
Simulation time 8400516745 ps
CPU time 12.43 seconds
Started May 21 01:05:04 PM PDT 24
Finished May 21 01:05:18 PM PDT 24
Peak memory 205284 kb
Host smart-8856583d-87c1-47fe-b150-9de73687da61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16743
75040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.1674375040
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.186698893
Short name T296
Test name
Test status
Simulation time 8383603076 ps
CPU time 14.39 seconds
Started May 21 01:05:05 PM PDT 24
Finished May 21 01:05:21 PM PDT 24
Peak memory 205400 kb
Host smart-1cf3b817-5de5-4ef7-9122-ebe64073fe23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18669
8893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.186698893
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.2998168302
Short name T1588
Test name
Test status
Simulation time 8402343471 ps
CPU time 11.62 seconds
Started May 21 01:05:10 PM PDT 24
Finished May 21 01:05:23 PM PDT 24
Peak memory 205384 kb
Host smart-633495f8-0624-4a2f-a9ef-f64c25fbb609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29981
68302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.2998168302
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_eop_single_bit_handling.4270873201
Short name T1463
Test name
Test status
Simulation time 8428663117 ps
CPU time 10.89 seconds
Started May 21 01:05:10 PM PDT 24
Finished May 21 01:05:21 PM PDT 24
Peak memory 205380 kb
Host smart-2ecc756b-aa05-493a-bc5a-d74cc72e18ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42708
73201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_eop_single_bit_handling.4270873201
Directory /workspace/2.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1142992573
Short name T1514
Test name
Test status
Simulation time 8377784184 ps
CPU time 13.16 seconds
Started May 21 01:05:10 PM PDT 24
Finished May 21 01:05:26 PM PDT 24
Peak memory 205312 kb
Host smart-4017b142-64a2-4382-8174-334a66101829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11429
92573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1142992573
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.1460335007
Short name T1356
Test name
Test status
Simulation time 8361344522 ps
CPU time 14.22 seconds
Started May 21 01:05:09 PM PDT 24
Finished May 21 01:05:24 PM PDT 24
Peak memory 205372 kb
Host smart-ddb12715-a3d5-49fd-a303-cc8cf4510a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14603
35007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.1460335007
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.2377196766
Short name T1078
Test name
Test status
Simulation time 24125974327 ps
CPU time 52.84 seconds
Started May 21 01:05:03 PM PDT 24
Finished May 21 01:05:57 PM PDT 24
Peak memory 205344 kb
Host smart-73948bb2-dbc4-444e-b10a-d946e6d7c27d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23771
96766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.2377196766
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.1673946642
Short name T317
Test name
Test status
Simulation time 8382782263 ps
CPU time 12.22 seconds
Started May 21 01:05:54 PM PDT 24
Finished May 21 01:06:07 PM PDT 24
Peak memory 205332 kb
Host smart-2c953269-66af-4f9a-806d-4edb96660441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16739
46642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.1673946642
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2864454879
Short name T1104
Test name
Test status
Simulation time 8419592054 ps
CPU time 13.67 seconds
Started May 21 01:05:05 PM PDT 24
Finished May 21 01:05:20 PM PDT 24
Peak memory 205392 kb
Host smart-9934d42a-3eaf-45c9-9be2-ff3678bca7b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28644
54879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2864454879
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.827897783
Short name T676
Test name
Test status
Simulation time 8403516209 ps
CPU time 12.3 seconds
Started May 21 01:05:05 PM PDT 24
Finished May 21 01:05:19 PM PDT 24
Peak memory 205324 kb
Host smart-afeda2b9-e5ab-4569-9ae7-633628ef1e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82789
7783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.827897783
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.350132299
Short name T1641
Test name
Test status
Simulation time 8388606631 ps
CPU time 12.28 seconds
Started May 21 01:05:13 PM PDT 24
Finished May 21 01:05:26 PM PDT 24
Peak memory 205380 kb
Host smart-19643faa-ec05-423e-a94c-db7110c2fe35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35013
2299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.350132299
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.690361733
Short name T746
Test name
Test status
Simulation time 8384537961 ps
CPU time 12.66 seconds
Started May 21 01:05:13 PM PDT 24
Finished May 21 01:05:27 PM PDT 24
Peak memory 205376 kb
Host smart-323e161a-7770-4af2-8821-436f143d9d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69036
1733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.690361733
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.2633644832
Short name T1554
Test name
Test status
Simulation time 8433135113 ps
CPU time 11.47 seconds
Started May 21 01:04:58 PM PDT 24
Finished May 21 01:05:10 PM PDT 24
Peak memory 205288 kb
Host smart-f072f965-b2f6-49fa-9c1a-b93d86b87f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26336
44832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.2633644832
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.1206211823
Short name T472
Test name
Test status
Simulation time 8450328378 ps
CPU time 12.14 seconds
Started May 21 01:05:11 PM PDT 24
Finished May 21 01:05:25 PM PDT 24
Peak memory 205412 kb
Host smart-23d36b4d-ce59-4216-9213-841188f49cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12062
11823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.1206211823
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.4136360567
Short name T1493
Test name
Test status
Simulation time 8395016749 ps
CPU time 12.84 seconds
Started May 21 01:05:04 PM PDT 24
Finished May 21 01:05:19 PM PDT 24
Peak memory 205348 kb
Host smart-93e962a7-82e7-428a-a9c3-d8be53401c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41363
60567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.4136360567
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.872044609
Short name T1083
Test name
Test status
Simulation time 8464793136 ps
CPU time 11.51 seconds
Started May 21 01:08:39 PM PDT 24
Finished May 21 01:08:51 PM PDT 24
Peak memory 205360 kb
Host smart-8a0d8791-3246-4bf7-a6d5-5fa78e826eeb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=872044609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.872044609
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.2657577262
Short name T499
Test name
Test status
Simulation time 8380415072 ps
CPU time 10.59 seconds
Started May 21 01:08:33 PM PDT 24
Finished May 21 01:08:44 PM PDT 24
Peak memory 205324 kb
Host smart-78a2b752-fc38-404c-8205-d2166ce007ac
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2657577262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.2657577262
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.3008182502
Short name T370
Test name
Test status
Simulation time 8383271396 ps
CPU time 11.92 seconds
Started May 21 01:08:33 PM PDT 24
Finished May 21 01:08:45 PM PDT 24
Peak memory 205428 kb
Host smart-11fb7b5f-db9c-4b88-a37c-d5a42a225c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30081
82502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.3008182502
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3558702548
Short name T512
Test name
Test status
Simulation time 8410864967 ps
CPU time 11.68 seconds
Started May 21 01:08:27 PM PDT 24
Finished May 21 01:08:40 PM PDT 24
Peak memory 205404 kb
Host smart-f91d0447-6ea2-4419-97ef-d9a70076e586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35587
02548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3558702548
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.3841619925
Short name T1471
Test name
Test status
Simulation time 8713118576 ps
CPU time 11.72 seconds
Started May 21 01:08:31 PM PDT 24
Finished May 21 01:08:43 PM PDT 24
Peak memory 205360 kb
Host smart-098878f3-740a-48a2-af27-b68959150cef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38416
19925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.3841619925
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.2131202133
Short name T1627
Test name
Test status
Simulation time 8372363953 ps
CPU time 12.44 seconds
Started May 21 01:08:27 PM PDT 24
Finished May 21 01:08:41 PM PDT 24
Peak memory 205320 kb
Host smart-5199d749-47e6-4901-a964-5b7c70738425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21312
02133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2131202133
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.74671516
Short name T325
Test name
Test status
Simulation time 8397454524 ps
CPU time 11.36 seconds
Started May 21 01:08:28 PM PDT 24
Finished May 21 01:08:40 PM PDT 24
Peak memory 205276 kb
Host smart-54dd7a48-5d53-4398-8125-cd3850de28e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74671
516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.74671516
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.2474218531
Short name T1556
Test name
Test status
Simulation time 9165885337 ps
CPU time 14.81 seconds
Started May 21 01:08:30 PM PDT 24
Finished May 21 01:08:45 PM PDT 24
Peak memory 205396 kb
Host smart-efd8dc81-0e59-4d11-84e5-bef6ccec16cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24742
18531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.2474218531
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.583651630
Short name T416
Test name
Test status
Simulation time 8441394161 ps
CPU time 12.22 seconds
Started May 21 01:08:36 PM PDT 24
Finished May 21 01:08:49 PM PDT 24
Peak memory 205392 kb
Host smart-b7c1e831-1420-49b3-9333-3a7099943844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58365
1630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.583651630
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.2769950526
Short name T17
Test name
Test status
Simulation time 8396716155 ps
CPU time 11.25 seconds
Started May 21 01:08:33 PM PDT 24
Finished May 21 01:08:44 PM PDT 24
Peak memory 205344 kb
Host smart-4ce2bf76-da65-49c2-9b9c-a9d0c08d7abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27699
50526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.2769950526
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.96484907
Short name T1047
Test name
Test status
Simulation time 8444675844 ps
CPU time 11.35 seconds
Started May 21 01:08:28 PM PDT 24
Finished May 21 01:08:41 PM PDT 24
Peak memory 205416 kb
Host smart-717a8120-2f17-498f-96ae-586482580071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96484
907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.96484907
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.439105304
Short name T4
Test name
Test status
Simulation time 11487347848 ps
CPU time 19.03 seconds
Started May 21 01:08:26 PM PDT 24
Finished May 21 01:08:46 PM PDT 24
Peak memory 205376 kb
Host smart-d0415886-bd1e-401b-82fc-48b91e8f95ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43910
5304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.439105304
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.4143957853
Short name T490
Test name
Test status
Simulation time 8418963078 ps
CPU time 14.59 seconds
Started May 21 01:08:30 PM PDT 24
Finished May 21 01:08:45 PM PDT 24
Peak memory 205376 kb
Host smart-ebc6650a-5142-47b7-bf14-161bafa01fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41439
57853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.4143957853
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1459605435
Short name T1300
Test name
Test status
Simulation time 8373415204 ps
CPU time 14.86 seconds
Started May 21 01:08:27 PM PDT 24
Finished May 21 01:08:44 PM PDT 24
Peak memory 205316 kb
Host smart-999fd6a9-9787-4e8c-b318-dd48c22b0505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14596
05435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1459605435
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.3394554039
Short name T766
Test name
Test status
Simulation time 8407507332 ps
CPU time 11.46 seconds
Started May 21 01:08:29 PM PDT 24
Finished May 21 01:08:41 PM PDT 24
Peak memory 205328 kb
Host smart-93c2b992-decc-4c77-b9b6-c8b5f7e4e733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33945
54039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.3394554039
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.3218858055
Short name T566
Test name
Test status
Simulation time 8411300913 ps
CPU time 11.77 seconds
Started May 21 01:08:31 PM PDT 24
Finished May 21 01:08:43 PM PDT 24
Peak memory 205392 kb
Host smart-782c6ee1-28e7-4e35-bd56-f139c73a77a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32188
58055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.3218858055
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.1206461467
Short name T1017
Test name
Test status
Simulation time 8397322693 ps
CPU time 12.13 seconds
Started May 21 01:08:30 PM PDT 24
Finished May 21 01:08:43 PM PDT 24
Peak memory 205372 kb
Host smart-6c5bae14-e0d6-4d0e-9403-83e13be62b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12064
61467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1206461467
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.2409646904
Short name T1678
Test name
Test status
Simulation time 8396773303 ps
CPU time 11.88 seconds
Started May 21 01:08:27 PM PDT 24
Finished May 21 01:08:41 PM PDT 24
Peak memory 205248 kb
Host smart-bc4b9632-27bb-4b36-9d14-d9dabb85b4a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24096
46904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.2409646904
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.1681399527
Short name T1624
Test name
Test status
Simulation time 8384118809 ps
CPU time 11.36 seconds
Started May 21 01:08:37 PM PDT 24
Finished May 21 01:08:49 PM PDT 24
Peak memory 205312 kb
Host smart-18a8b395-faeb-4b6e-bf22-7458000c8267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16813
99527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.1681399527
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_eop_single_bit_handling.4185313134
Short name T868
Test name
Test status
Simulation time 8423312892 ps
CPU time 14.07 seconds
Started May 21 01:08:36 PM PDT 24
Finished May 21 01:08:51 PM PDT 24
Peak memory 205100 kb
Host smart-f6b8a4a6-645a-4d61-b535-0c3d5989733a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41853
13134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_eop_single_bit_handling.4185313134
Directory /workspace/20.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.2620598643
Short name T69
Test name
Test status
Simulation time 8376520969 ps
CPU time 11.69 seconds
Started May 21 01:08:32 PM PDT 24
Finished May 21 01:08:44 PM PDT 24
Peak memory 205312 kb
Host smart-be4b0111-9886-466e-900f-34f900d2d4ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26205
98643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.2620598643
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.1939175417
Short name T1506
Test name
Test status
Simulation time 8361904548 ps
CPU time 12.69 seconds
Started May 21 01:08:35 PM PDT 24
Finished May 21 01:08:48 PM PDT 24
Peak memory 205352 kb
Host smart-e99ff954-c68c-4c12-8436-38f452a29e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19391
75417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.1939175417
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.1282633670
Short name T1649
Test name
Test status
Simulation time 25256615314 ps
CPU time 47.66 seconds
Started May 21 01:08:30 PM PDT 24
Finished May 21 01:09:18 PM PDT 24
Peak memory 205404 kb
Host smart-6f2bbe5c-eef0-4835-8b66-0b857e94cd84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12826
33670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.1282633670
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.1015953404
Short name T335
Test name
Test status
Simulation time 8398484073 ps
CPU time 12.22 seconds
Started May 21 01:08:34 PM PDT 24
Finished May 21 01:08:47 PM PDT 24
Peak memory 205348 kb
Host smart-98006997-e21a-49b4-9f01-d6676f3339b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10159
53404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.1015953404
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.2525871098
Short name T980
Test name
Test status
Simulation time 8418005557 ps
CPU time 11.86 seconds
Started May 21 01:08:34 PM PDT 24
Finished May 21 01:08:47 PM PDT 24
Peak memory 205292 kb
Host smart-ac3c5cea-b86b-4225-a5b5-f585c102f717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25258
71098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.2525871098
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.378896355
Short name T1076
Test name
Test status
Simulation time 8407257134 ps
CPU time 12.98 seconds
Started May 21 01:08:36 PM PDT 24
Finished May 21 01:08:50 PM PDT 24
Peak memory 205356 kb
Host smart-24460866-08f3-4f88-acfc-86573d4535e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37889
6355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.378896355
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.2796622289
Short name T637
Test name
Test status
Simulation time 8404954522 ps
CPU time 13.23 seconds
Started May 21 01:08:34 PM PDT 24
Finished May 21 01:08:48 PM PDT 24
Peak memory 205372 kb
Host smart-3303fcbf-312c-48d5-83b9-8f32a742ea94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27966
22289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.2796622289
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.986216708
Short name T1176
Test name
Test status
Simulation time 8377671689 ps
CPU time 11.53 seconds
Started May 21 01:08:32 PM PDT 24
Finished May 21 01:08:44 PM PDT 24
Peak memory 205184 kb
Host smart-1bc120f8-67dc-4d21-a6d7-a0a285e394a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98621
6708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.986216708
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2772484023
Short name T1273
Test name
Test status
Simulation time 8391848311 ps
CPU time 13.1 seconds
Started May 21 01:08:33 PM PDT 24
Finished May 21 01:08:47 PM PDT 24
Peak memory 205412 kb
Host smart-221bc924-8c88-427b-8140-82d2025e0168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27724
84023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2772484023
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.2848018848
Short name T1305
Test name
Test status
Simulation time 8466098894 ps
CPU time 12.8 seconds
Started May 21 01:08:26 PM PDT 24
Finished May 21 01:08:40 PM PDT 24
Peak memory 205368 kb
Host smart-4c7870f7-9f35-4a01-8d2b-cbebceede78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28480
18848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.2848018848
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.1878183253
Short name T1438
Test name
Test status
Simulation time 8389089917 ps
CPU time 11.01 seconds
Started May 21 01:08:34 PM PDT 24
Finished May 21 01:08:46 PM PDT 24
Peak memory 205388 kb
Host smart-cdac2332-80d8-4883-bd11-26e005f776d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18781
83253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1878183253
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.110305886
Short name T1622
Test name
Test status
Simulation time 8447936992 ps
CPU time 11.94 seconds
Started May 21 01:08:39 PM PDT 24
Finished May 21 01:08:52 PM PDT 24
Peak memory 205352 kb
Host smart-20afb812-8f92-4b22-9903-c3e1ea9b8114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11030
5886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.110305886
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.930727327
Short name T1319
Test name
Test status
Simulation time 8478929225 ps
CPU time 14.38 seconds
Started May 21 01:08:45 PM PDT 24
Finished May 21 01:09:02 PM PDT 24
Peak memory 205380 kb
Host smart-f891a195-72c9-4dca-85b5-dbefb426d73d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=930727327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.930727327
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.2585502747
Short name T414
Test name
Test status
Simulation time 8380966423 ps
CPU time 12.33 seconds
Started May 21 01:08:47 PM PDT 24
Finished May 21 01:09:01 PM PDT 24
Peak memory 205320 kb
Host smart-828b4ca0-f29d-412e-ac46-beea817ce59a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2585502747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.2585502747
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.3563066992
Short name T449
Test name
Test status
Simulation time 8488390362 ps
CPU time 11.88 seconds
Started May 21 01:08:39 PM PDT 24
Finished May 21 01:08:52 PM PDT 24
Peak memory 205324 kb
Host smart-fcbdffb4-2361-40d0-981c-836467f327d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35630
66992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.3563066992
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.69376723
Short name T479
Test name
Test status
Simulation time 8401313437 ps
CPU time 10.63 seconds
Started May 21 01:08:39 PM PDT 24
Finished May 21 01:08:50 PM PDT 24
Peak memory 205340 kb
Host smart-9b2b7c68-119b-4c5a-a762-52619a0b2907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69376
723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.69376723
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.3285563263
Short name T485
Test name
Test status
Simulation time 9404057714 ps
CPU time 14.51 seconds
Started May 21 01:08:39 PM PDT 24
Finished May 21 01:08:54 PM PDT 24
Peak memory 205352 kb
Host smart-21dd6268-3baf-4873-8c84-b561a3cc1702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32855
63263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.3285563263
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.1086641658
Short name T1715
Test name
Test status
Simulation time 8367960800 ps
CPU time 12.7 seconds
Started May 21 01:08:41 PM PDT 24
Finished May 21 01:08:55 PM PDT 24
Peak memory 205352 kb
Host smart-a31c625e-431d-41db-a578-42015ce87aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10866
41658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.1086641658
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.308280689
Short name T915
Test name
Test status
Simulation time 8444913915 ps
CPU time 12.75 seconds
Started May 21 01:08:42 PM PDT 24
Finished May 21 01:08:56 PM PDT 24
Peak memory 205252 kb
Host smart-51e4b5ff-018a-40d1-a5e2-22ecb4595d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30828
0689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.308280689
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.2943496132
Short name T756
Test name
Test status
Simulation time 8587479252 ps
CPU time 13.36 seconds
Started May 21 01:08:40 PM PDT 24
Finished May 21 01:08:55 PM PDT 24
Peak memory 205324 kb
Host smart-b949f887-4993-448a-a601-b3d279211c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29434
96132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.2943496132
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.1532562811
Short name T394
Test name
Test status
Simulation time 8369084339 ps
CPU time 11.92 seconds
Started May 21 01:08:44 PM PDT 24
Finished May 21 01:08:58 PM PDT 24
Peak memory 205344 kb
Host smart-2fddb554-ca48-48d9-badf-f61e8b775d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15325
62811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.1532562811
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.3390179207
Short name T963
Test name
Test status
Simulation time 8400619393 ps
CPU time 11.32 seconds
Started May 21 01:08:42 PM PDT 24
Finished May 21 01:08:54 PM PDT 24
Peak memory 205380 kb
Host smart-0104b64d-8265-4719-bd6c-a4e2b634dd83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33901
79207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.3390179207
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.3358384508
Short name T41
Test name
Test status
Simulation time 8427589299 ps
CPU time 11.48 seconds
Started May 21 01:08:45 PM PDT 24
Finished May 21 01:08:59 PM PDT 24
Peak memory 205324 kb
Host smart-8260f5fd-ed62-4224-b392-7673016b2122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33583
84508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.3358384508
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.4116130445
Short name T1518
Test name
Test status
Simulation time 11515090984 ps
CPU time 14.4 seconds
Started May 21 01:08:44 PM PDT 24
Finished May 21 01:09:00 PM PDT 24
Peak memory 205348 kb
Host smart-1ab07dcd-fcf9-4de3-a740-d691c684586c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41161
30445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.4116130445
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.520492640
Short name T897
Test name
Test status
Simulation time 8415408778 ps
CPU time 13.34 seconds
Started May 21 01:08:44 PM PDT 24
Finished May 21 01:08:59 PM PDT 24
Peak memory 205392 kb
Host smart-e47b08a7-56ee-4f1b-ab59-c2a2a36f15a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52049
2640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.520492640
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.2844689349
Short name T716
Test name
Test status
Simulation time 8377894139 ps
CPU time 11.39 seconds
Started May 21 01:08:40 PM PDT 24
Finished May 21 01:08:52 PM PDT 24
Peak memory 205412 kb
Host smart-68631383-f407-40cd-a5ae-fcbe5994b5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28446
89349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.2844689349
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.1454883179
Short name T1391
Test name
Test status
Simulation time 8411418296 ps
CPU time 13.82 seconds
Started May 21 01:08:39 PM PDT 24
Finished May 21 01:08:55 PM PDT 24
Peak memory 205444 kb
Host smart-ce2ed86e-1945-4ee5-8d45-1489be9bb395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14548
83179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.1454883179
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.1820879586
Short name T1242
Test name
Test status
Simulation time 8379528069 ps
CPU time 11.69 seconds
Started May 21 01:08:43 PM PDT 24
Finished May 21 01:08:56 PM PDT 24
Peak memory 205340 kb
Host smart-16f89bf2-d1f1-429b-9989-f619730c1916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18208
79586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.1820879586
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.2252697429
Short name T847
Test name
Test status
Simulation time 8405743241 ps
CPU time 14.76 seconds
Started May 21 01:08:43 PM PDT 24
Finished May 21 01:08:58 PM PDT 24
Peak memory 205284 kb
Host smart-558a1ea3-65a4-4d77-baba-d14ed7fb4858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22526
97429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.2252697429
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.1371612427
Short name T321
Test name
Test status
Simulation time 8415558970 ps
CPU time 11.1 seconds
Started May 21 01:08:43 PM PDT 24
Finished May 21 01:08:55 PM PDT 24
Peak memory 205352 kb
Host smart-65771969-dcd5-44f6-8d79-4543bff339aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13716
12427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.1371612427
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_eop_single_bit_handling.3727739347
Short name T493
Test name
Test status
Simulation time 8403892488 ps
CPU time 11.23 seconds
Started May 21 01:08:44 PM PDT 24
Finished May 21 01:08:56 PM PDT 24
Peak memory 205388 kb
Host smart-96e59d0b-8dda-415e-b9af-27adaa35b32c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37277
39347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_eop_single_bit_handling.3727739347
Directory /workspace/21.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.943297777
Short name T919
Test name
Test status
Simulation time 8374388721 ps
CPU time 11.69 seconds
Started May 21 01:08:43 PM PDT 24
Finished May 21 01:08:56 PM PDT 24
Peak memory 205260 kb
Host smart-e1f6df7c-0205-4ea2-86c6-c689ebeaf7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94329
7777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.943297777
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.3896747752
Short name T11
Test name
Test status
Simulation time 8380940457 ps
CPU time 14.56 seconds
Started May 21 01:08:45 PM PDT 24
Finished May 21 01:09:02 PM PDT 24
Peak memory 205296 kb
Host smart-cdfda656-0d9e-484d-8c50-46d8115d7215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38967
47752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.3896747752
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.276803436
Short name T224
Test name
Test status
Simulation time 17892697038 ps
CPU time 32.22 seconds
Started May 21 01:08:39 PM PDT 24
Finished May 21 01:09:12 PM PDT 24
Peak memory 205364 kb
Host smart-02163439-85b4-4bbb-8565-7dc6c4a0684e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27680
3436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.276803436
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.1756868794
Short name T1289
Test name
Test status
Simulation time 8405535342 ps
CPU time 11.49 seconds
Started May 21 01:08:40 PM PDT 24
Finished May 21 01:08:53 PM PDT 24
Peak memory 205364 kb
Host smart-ef9ce94b-8122-4198-b4d2-9ecc4d8968db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17568
68794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.1756868794
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1819519959
Short name T811
Test name
Test status
Simulation time 8418969702 ps
CPU time 11.76 seconds
Started May 21 01:08:43 PM PDT 24
Finished May 21 01:08:56 PM PDT 24
Peak memory 205400 kb
Host smart-b7a82373-2d03-4fa5-ae5b-65c079526a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18195
19959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1819519959
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.1205765617
Short name T1005
Test name
Test status
Simulation time 8388327754 ps
CPU time 11.41 seconds
Started May 21 01:08:44 PM PDT 24
Finished May 21 01:08:58 PM PDT 24
Peak memory 205296 kb
Host smart-907fca2a-ce40-45f0-b59c-76959359d7e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12057
65617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.1205765617
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.3554790990
Short name T967
Test name
Test status
Simulation time 8363587798 ps
CPU time 12.22 seconds
Started May 21 01:08:40 PM PDT 24
Finished May 21 01:08:54 PM PDT 24
Peak memory 205288 kb
Host smart-70bd72cc-8c21-433b-9857-5c57680e8d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35547
90990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.3554790990
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.1388227482
Short name T858
Test name
Test status
Simulation time 8375335671 ps
CPU time 11.24 seconds
Started May 21 01:08:42 PM PDT 24
Finished May 21 01:08:54 PM PDT 24
Peak memory 205344 kb
Host smart-8d445af7-ed55-4d73-8253-766d0f704f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13882
27482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.1388227482
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.444052331
Short name T283
Test name
Test status
Simulation time 8374795299 ps
CPU time 14.01 seconds
Started May 21 01:08:41 PM PDT 24
Finished May 21 01:08:57 PM PDT 24
Peak memory 205412 kb
Host smart-809a3fb6-5e9d-4b4b-9b0c-d51d18b04150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44405
2331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.444052331
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1778865195
Short name T179
Test name
Test status
Simulation time 8475004116 ps
CPU time 13.17 seconds
Started May 21 01:08:35 PM PDT 24
Finished May 21 01:08:49 PM PDT 24
Peak memory 205400 kb
Host smart-fecceb3a-fc87-455e-bfbc-8f22ddde211f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17788
65195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1778865195
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.824318773
Short name T931
Test name
Test status
Simulation time 8393628971 ps
CPU time 11.7 seconds
Started May 21 01:08:43 PM PDT 24
Finished May 21 01:08:56 PM PDT 24
Peak memory 205268 kb
Host smart-57beba5b-b342-49f8-85e0-019f42d0b04d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82431
8773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.824318773
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.1163719854
Short name T411
Test name
Test status
Simulation time 8411890455 ps
CPU time 12.49 seconds
Started May 21 01:08:40 PM PDT 24
Finished May 21 01:08:54 PM PDT 24
Peak memory 205340 kb
Host smart-8a1dd293-1f80-4633-a6d0-67345ba665d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11637
19854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.1163719854
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.2064916319
Short name T505
Test name
Test status
Simulation time 8475671978 ps
CPU time 14.27 seconds
Started May 21 01:08:52 PM PDT 24
Finished May 21 01:09:08 PM PDT 24
Peak memory 205336 kb
Host smart-84502d93-424b-423c-99ac-a941367b5869
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2064916319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.2064916319
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.171414758
Short name T1362
Test name
Test status
Simulation time 8415580154 ps
CPU time 12.52 seconds
Started May 21 01:08:53 PM PDT 24
Finished May 21 01:09:12 PM PDT 24
Peak memory 205380 kb
Host smart-797e79eb-2365-48c8-8053-d778ae9516d6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=171414758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.171414758
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.3911137924
Short name T1522
Test name
Test status
Simulation time 8406609669 ps
CPU time 13.67 seconds
Started May 21 01:08:58 PM PDT 24
Finished May 21 01:09:13 PM PDT 24
Peak memory 205356 kb
Host smart-a97a681c-758f-471b-b3e2-1e2e6084b1a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39111
37924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.3911137924
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.1128743387
Short name T986
Test name
Test status
Simulation time 8397375242 ps
CPU time 12.17 seconds
Started May 21 01:08:47 PM PDT 24
Finished May 21 01:09:01 PM PDT 24
Peak memory 205336 kb
Host smart-08f9c2f3-26f1-411b-b2f7-3c7cffe5c1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11287
43387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.1128743387
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.2984895086
Short name T447
Test name
Test status
Simulation time 9186583457 ps
CPU time 14.48 seconds
Started May 21 01:08:46 PM PDT 24
Finished May 21 01:09:03 PM PDT 24
Peak memory 205576 kb
Host smart-8e797685-44c4-466e-a35b-e8aa6eb00885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29848
95086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.2984895086
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.2100683250
Short name T822
Test name
Test status
Simulation time 8381381672 ps
CPU time 11.78 seconds
Started May 21 01:08:47 PM PDT 24
Finished May 21 01:09:01 PM PDT 24
Peak memory 205380 kb
Host smart-6457b308-2555-4761-aa94-ead9aff74ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21006
83250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.2100683250
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.3770418607
Short name T279
Test name
Test status
Simulation time 8385120023 ps
CPU time 12.28 seconds
Started May 21 01:08:45 PM PDT 24
Finished May 21 01:09:00 PM PDT 24
Peak memory 205344 kb
Host smart-9233b99e-00c3-46a3-a40f-d3484c366056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37704
18607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.3770418607
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.120195135
Short name T1341
Test name
Test status
Simulation time 8426827597 ps
CPU time 13.56 seconds
Started May 21 01:08:45 PM PDT 24
Finished May 21 01:09:01 PM PDT 24
Peak memory 205368 kb
Host smart-c69680f5-11fc-476c-9203-7b2d60dabc13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12019
5135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.120195135
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.3191808184
Short name T688
Test name
Test status
Simulation time 8376207001 ps
CPU time 14.42 seconds
Started May 21 01:08:55 PM PDT 24
Finished May 21 01:09:10 PM PDT 24
Peak memory 204736 kb
Host smart-a2319fbe-8bef-45a9-8f1f-f4699547a1d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31918
08184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.3191808184
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.3316579736
Short name T333
Test name
Test status
Simulation time 8444594762 ps
CPU time 11.88 seconds
Started May 21 01:08:54 PM PDT 24
Finished May 21 01:09:07 PM PDT 24
Peak memory 205332 kb
Host smart-33df23a8-7fcf-4b5f-b95e-66f6e1b87468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33165
79736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.3316579736
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.976655963
Short name T380
Test name
Test status
Simulation time 8457387700 ps
CPU time 11.31 seconds
Started May 21 01:08:48 PM PDT 24
Finished May 21 01:09:01 PM PDT 24
Peak memory 205372 kb
Host smart-12169b51-6d8c-4c78-909c-373c7764a0eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97665
5963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.976655963
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.2474411308
Short name T693
Test name
Test status
Simulation time 8397099116 ps
CPU time 12.62 seconds
Started May 21 01:08:44 PM PDT 24
Finished May 21 01:08:59 PM PDT 24
Peak memory 205232 kb
Host smart-dcc927fc-4c32-41f9-ac2f-ff127af34b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24744
11308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.2474411308
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.3945415606
Short name T663
Test name
Test status
Simulation time 11545738383 ps
CPU time 15.65 seconds
Started May 21 01:08:44 PM PDT 24
Finished May 21 01:09:01 PM PDT 24
Peak memory 205396 kb
Host smart-8c868733-e97b-4767-a69a-19ce0ea9de8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39454
15606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.3945415606
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3002498403
Short name T1210
Test name
Test status
Simulation time 8425717565 ps
CPU time 12.82 seconds
Started May 21 01:08:46 PM PDT 24
Finished May 21 01:09:01 PM PDT 24
Peak memory 205328 kb
Host smart-72ea7e81-1a17-4287-882d-cc0526b21cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30024
98403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3002498403
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.526276417
Short name T93
Test name
Test status
Simulation time 8389702983 ps
CPU time 15.04 seconds
Started May 21 01:08:46 PM PDT 24
Finished May 21 01:09:03 PM PDT 24
Peak memory 205432 kb
Host smart-e3940f1b-d441-4416-96ff-3aacc7a4fc26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52627
6417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.526276417
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.3639096831
Short name T126
Test name
Test status
Simulation time 8422116404 ps
CPU time 12.28 seconds
Started May 21 01:08:49 PM PDT 24
Finished May 21 01:09:03 PM PDT 24
Peak memory 205404 kb
Host smart-bc3ca1a2-7039-47af-8f39-a4e4e5f27e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36390
96831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3639096831
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.1064875340
Short name T103
Test name
Test status
Simulation time 8418829392 ps
CPU time 12.98 seconds
Started May 21 01:08:45 PM PDT 24
Finished May 21 01:09:00 PM PDT 24
Peak memory 205308 kb
Host smart-0741d737-1450-4e82-8315-b59c1d5d127d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10648
75340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.1064875340
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2475234400
Short name T1167
Test name
Test status
Simulation time 8380013370 ps
CPU time 13.35 seconds
Started May 21 01:08:47 PM PDT 24
Finished May 21 01:09:02 PM PDT 24
Peak memory 205404 kb
Host smart-2e5e84c5-ce84-4edf-800d-046f769b55ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24752
34400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2475234400
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.3222667515
Short name T812
Test name
Test status
Simulation time 8406171368 ps
CPU time 11.75 seconds
Started May 21 01:08:46 PM PDT 24
Finished May 21 01:09:00 PM PDT 24
Peak memory 205388 kb
Host smart-e0aa1d8d-2937-44d2-a02a-412b04848a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32226
67515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.3222667515
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.735692407
Short name T1396
Test name
Test status
Simulation time 8421040899 ps
CPU time 12.18 seconds
Started May 21 01:08:53 PM PDT 24
Finished May 21 01:09:07 PM PDT 24
Peak memory 205328 kb
Host smart-a1a53c1b-78fa-49f4-bce4-7308e0738107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73569
2407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.735692407
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_eop_single_bit_handling.3896071888
Short name T1153
Test name
Test status
Simulation time 8378697948 ps
CPU time 12.73 seconds
Started May 21 01:08:52 PM PDT 24
Finished May 21 01:09:06 PM PDT 24
Peak memory 205332 kb
Host smart-01b4c3f1-02fc-4be7-9b43-b9fd3e7d40b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38960
71888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_eop_single_bit_handling.3896071888
Directory /workspace/22.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.3753598298
Short name T1417
Test name
Test status
Simulation time 8371604512 ps
CPU time 11.9 seconds
Started May 21 01:08:54 PM PDT 24
Finished May 21 01:09:07 PM PDT 24
Peak memory 205240 kb
Host smart-714bcbda-5c64-4304-894b-36392d704821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37535
98298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.3753598298
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.388196689
Short name T1563
Test name
Test status
Simulation time 8364168467 ps
CPU time 12.43 seconds
Started May 21 01:08:53 PM PDT 24
Finished May 21 01:09:07 PM PDT 24
Peak memory 205340 kb
Host smart-63da7df2-de32-4620-aac8-fa4819797f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38819
6689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.388196689
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.3018882748
Short name T1507
Test name
Test status
Simulation time 27851298390 ps
CPU time 57.06 seconds
Started May 21 01:08:46 PM PDT 24
Finished May 21 01:09:45 PM PDT 24
Peak memory 205424 kb
Host smart-d3d98347-e963-4b8a-bd2c-e303d7088b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30188
82748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.3018882748
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.1680533624
Short name T939
Test name
Test status
Simulation time 8389672507 ps
CPU time 13.74 seconds
Started May 21 01:08:45 PM PDT 24
Finished May 21 01:09:00 PM PDT 24
Peak memory 205348 kb
Host smart-5fb9466f-3521-4238-8657-4a9851d25669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16805
33624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.1680533624
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2630220915
Short name T1548
Test name
Test status
Simulation time 8433097684 ps
CPU time 11.63 seconds
Started May 21 01:08:47 PM PDT 24
Finished May 21 01:09:01 PM PDT 24
Peak memory 205248 kb
Host smart-adeb3668-11b3-4ba9-b6c9-687292800362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26302
20915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2630220915
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.2726631484
Short name T94
Test name
Test status
Simulation time 8473472566 ps
CPU time 12.31 seconds
Started May 21 01:08:52 PM PDT 24
Finished May 21 01:09:05 PM PDT 24
Peak memory 205432 kb
Host smart-82dbd518-ebc4-40f8-835a-c9a5e080473b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27266
31484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.2726631484
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.3934811128
Short name T1152
Test name
Test status
Simulation time 8412887389 ps
CPU time 10.88 seconds
Started May 21 01:08:54 PM PDT 24
Finished May 21 01:09:06 PM PDT 24
Peak memory 205324 kb
Host smart-d72fdd09-8af5-4ecb-80f7-2aafe89f1f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39348
11128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.3934811128
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.1515115837
Short name T934
Test name
Test status
Simulation time 8387196484 ps
CPU time 10.84 seconds
Started May 21 01:08:51 PM PDT 24
Finished May 21 01:09:02 PM PDT 24
Peak memory 205260 kb
Host smart-8b26cc9b-22e6-4a9b-ba91-53563cf40535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15151
15837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.1515115837
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.4196337591
Short name T969
Test name
Test status
Simulation time 8387179032 ps
CPU time 10.77 seconds
Started May 21 01:08:55 PM PDT 24
Finished May 21 01:09:07 PM PDT 24
Peak memory 205308 kb
Host smart-10d2f884-dd3b-4000-b544-d79828e354e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41963
37591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.4196337591
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.3505545944
Short name T1282
Test name
Test status
Simulation time 8450395843 ps
CPU time 11.79 seconds
Started May 21 01:08:49 PM PDT 24
Finished May 21 01:09:02 PM PDT 24
Peak memory 205308 kb
Host smart-287cab85-15c0-4892-a77d-31947d195ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35055
45944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.3505545944
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.1445287928
Short name T1327
Test name
Test status
Simulation time 8421107000 ps
CPU time 14.55 seconds
Started May 21 01:08:52 PM PDT 24
Finished May 21 01:09:08 PM PDT 24
Peak memory 205448 kb
Host smart-bd142d57-d893-4f3d-a087-ef1f74cfa3a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14452
87928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.1445287928
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.609100057
Short name T1457
Test name
Test status
Simulation time 8401269466 ps
CPU time 12.83 seconds
Started May 21 01:08:55 PM PDT 24
Finished May 21 01:09:09 PM PDT 24
Peak memory 205356 kb
Host smart-16697930-f9fb-4dfe-88f0-7806be12cf9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60910
0057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.609100057
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.2655781272
Short name T671
Test name
Test status
Simulation time 8469368374 ps
CPU time 12.31 seconds
Started May 21 01:09:05 PM PDT 24
Finished May 21 01:09:19 PM PDT 24
Peak memory 205348 kb
Host smart-10e5998a-37dc-46e7-80f6-f7473f854464
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2655781272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.2655781272
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.2719584533
Short name T920
Test name
Test status
Simulation time 8377116220 ps
CPU time 11.59 seconds
Started May 21 01:09:01 PM PDT 24
Finished May 21 01:09:15 PM PDT 24
Peak memory 205420 kb
Host smart-e67c94e6-5f94-424c-97ba-fa72dab06b3c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2719584533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.2719584533
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.2485683127
Short name T646
Test name
Test status
Simulation time 8403492865 ps
CPU time 10.88 seconds
Started May 21 01:09:01 PM PDT 24
Finished May 21 01:09:15 PM PDT 24
Peak memory 205340 kb
Host smart-31a1ef09-e886-4048-8d09-9a690ee47716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24856
83127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.2485683127
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.1361350462
Short name T588
Test name
Test status
Simulation time 8406565576 ps
CPU time 13.36 seconds
Started May 21 01:08:51 PM PDT 24
Finished May 21 01:09:06 PM PDT 24
Peak memory 205296 kb
Host smart-63e8e414-748b-4563-9ec2-e9b419f6d780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13613
50462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.1361350462
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.2763598343
Short name T61
Test name
Test status
Simulation time 8499882008 ps
CPU time 11.19 seconds
Started May 21 01:08:52 PM PDT 24
Finished May 21 01:09:04 PM PDT 24
Peak memory 205324 kb
Host smart-b1dab725-bf08-4030-80f0-c9bcce6e9df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27635
98343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.2763598343
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.1770108828
Short name T44
Test name
Test status
Simulation time 8379612951 ps
CPU time 12.37 seconds
Started May 21 01:08:57 PM PDT 24
Finished May 21 01:09:10 PM PDT 24
Peak memory 205324 kb
Host smart-297cc6d6-513c-47cf-a998-949a41385fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17701
08828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.1770108828
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.2536133754
Short name T1023
Test name
Test status
Simulation time 8379101937 ps
CPU time 12.94 seconds
Started May 21 01:08:54 PM PDT 24
Finished May 21 01:09:08 PM PDT 24
Peak memory 205284 kb
Host smart-ac23e9a4-2460-4565-a4ce-43a3cce3992d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25361
33754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2536133754
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.1726740212
Short name T840
Test name
Test status
Simulation time 9245339682 ps
CPU time 15.53 seconds
Started May 21 01:08:55 PM PDT 24
Finished May 21 01:09:12 PM PDT 24
Peak memory 205380 kb
Host smart-21a71de9-d099-4f6e-9df5-85278e4aa2a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17267
40212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.1726740212
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3434287765
Short name T1232
Test name
Test status
Simulation time 8468306466 ps
CPU time 13.26 seconds
Started May 21 01:08:54 PM PDT 24
Finished May 21 01:09:09 PM PDT 24
Peak memory 205308 kb
Host smart-738d0afb-f968-4d0e-91fb-29865f4e3b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34342
87765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3434287765
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.2731821808
Short name T620
Test name
Test status
Simulation time 8470386577 ps
CPU time 13.99 seconds
Started May 21 01:08:59 PM PDT 24
Finished May 21 01:09:15 PM PDT 24
Peak memory 205296 kb
Host smart-703b6572-7eb5-4713-b4a0-b3753381db19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27318
21808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.2731821808
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.4192570029
Short name T549
Test name
Test status
Simulation time 8368771106 ps
CPU time 13.67 seconds
Started May 21 01:09:00 PM PDT 24
Finished May 21 01:09:16 PM PDT 24
Peak memory 205288 kb
Host smart-e3557a66-745c-4739-b3ab-d1ed94103afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41925
70029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.4192570029
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.2526559834
Short name T1379
Test name
Test status
Simulation time 8431654672 ps
CPU time 12 seconds
Started May 21 01:08:55 PM PDT 24
Finished May 21 01:09:08 PM PDT 24
Peak memory 204724 kb
Host smart-3ca4d228-b153-41e8-9123-d47bdfedbd4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25265
59834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.2526559834
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.2700410097
Short name T1352
Test name
Test status
Simulation time 8380688825 ps
CPU time 12.45 seconds
Started May 21 01:08:53 PM PDT 24
Finished May 21 01:09:07 PM PDT 24
Peak memory 205348 kb
Host smart-0d68c71c-c31b-4098-975d-0c97fb5a2ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27004
10097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.2700410097
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.2444217211
Short name T1118
Test name
Test status
Simulation time 11503325802 ps
CPU time 18.17 seconds
Started May 21 01:08:52 PM PDT 24
Finished May 21 01:09:12 PM PDT 24
Peak memory 205440 kb
Host smart-343e30d3-3a8c-42ee-a4bf-5d1b9c3d9949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24442
17211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.2444217211
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.177978646
Short name T1094
Test name
Test status
Simulation time 8427360544 ps
CPU time 13.15 seconds
Started May 21 01:09:01 PM PDT 24
Finished May 21 01:09:17 PM PDT 24
Peak memory 205368 kb
Host smart-cba7b0c5-8917-4e6c-9e68-12747a40342b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17797
8646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.177978646
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.670596595
Short name T1323
Test name
Test status
Simulation time 8371597193 ps
CPU time 15.18 seconds
Started May 21 01:08:58 PM PDT 24
Finished May 21 01:09:14 PM PDT 24
Peak memory 205340 kb
Host smart-70d1fc7c-b2f7-4b59-97b2-a35d0a437b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67059
6595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.670596595
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.156505600
Short name T997
Test name
Test status
Simulation time 8471002912 ps
CPU time 12.79 seconds
Started May 21 01:09:01 PM PDT 24
Finished May 21 01:09:16 PM PDT 24
Peak memory 205344 kb
Host smart-c73c84ed-1a2d-4c40-99b0-33b411714f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15650
5600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.156505600
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.716595502
Short name T1535
Test name
Test status
Simulation time 8417986358 ps
CPU time 11.39 seconds
Started May 21 01:09:02 PM PDT 24
Finished May 21 01:09:16 PM PDT 24
Peak memory 205352 kb
Host smart-6d6a1914-7e0c-4801-b3bf-4fa4af402e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71659
5502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.716595502
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.655817203
Short name T1361
Test name
Test status
Simulation time 8392470211 ps
CPU time 12.28 seconds
Started May 21 01:09:00 PM PDT 24
Finished May 21 01:09:15 PM PDT 24
Peak memory 205272 kb
Host smart-d5dc22b9-dbc4-4ec9-a7e7-2ddb5f2d4830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65581
7203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.655817203
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.2526932936
Short name T1335
Test name
Test status
Simulation time 8401927460 ps
CPU time 12.05 seconds
Started May 21 01:08:59 PM PDT 24
Finished May 21 01:09:13 PM PDT 24
Peak memory 205608 kb
Host smart-76275599-39bb-4095-b53b-bd9d611ccf18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25269
32936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.2526932936
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_eop_single_bit_handling.1645203230
Short name T690
Test name
Test status
Simulation time 8396963975 ps
CPU time 11.15 seconds
Started May 21 01:08:58 PM PDT 24
Finished May 21 01:09:11 PM PDT 24
Peak memory 205288 kb
Host smart-d8a4c4b4-aea8-43c1-a366-cf76c4486512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16452
03230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_eop_single_bit_handling.1645203230
Directory /workspace/23.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.2054303049
Short name T339
Test name
Test status
Simulation time 8395426859 ps
CPU time 11.74 seconds
Started May 21 01:09:03 PM PDT 24
Finished May 21 01:09:17 PM PDT 24
Peak memory 205340 kb
Host smart-07562451-9f0c-4919-ab73-21d81146c464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20543
03049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.2054303049
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2715980573
Short name T702
Test name
Test status
Simulation time 8395310856 ps
CPU time 11.2 seconds
Started May 21 01:08:57 PM PDT 24
Finished May 21 01:09:08 PM PDT 24
Peak memory 205360 kb
Host smart-06ec53fa-7bbb-466b-8a2b-90ca55c6c233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27159
80573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2715980573
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.160911301
Short name T1109
Test name
Test status
Simulation time 25899139747 ps
CPU time 48.38 seconds
Started May 21 01:09:03 PM PDT 24
Finished May 21 01:09:53 PM PDT 24
Peak memory 205424 kb
Host smart-af992e83-45ff-443d-8e1c-8f5a6688b4e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16091
1301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.160911301
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.2940624085
Short name T959
Test name
Test status
Simulation time 8377703541 ps
CPU time 11.78 seconds
Started May 21 01:08:59 PM PDT 24
Finished May 21 01:09:13 PM PDT 24
Peak memory 205412 kb
Host smart-c86f7b08-706b-402a-931e-bf2b6d63c59f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29406
24085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.2940624085
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2326073033
Short name T1124
Test name
Test status
Simulation time 8491094785 ps
CPU time 14.89 seconds
Started May 21 01:08:58 PM PDT 24
Finished May 21 01:09:14 PM PDT 24
Peak memory 205276 kb
Host smart-cc820b0d-6a17-426b-a39a-7ec0658d7f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23260
73033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2326073033
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.3128715936
Short name T1694
Test name
Test status
Simulation time 8386901718 ps
CPU time 12.15 seconds
Started May 21 01:09:00 PM PDT 24
Finished May 21 01:09:14 PM PDT 24
Peak memory 205340 kb
Host smart-2bb3dcf5-e8b7-4006-93cc-5ff32f51c4cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31287
15936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.3128715936
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2534323976
Short name T356
Test name
Test status
Simulation time 8369130029 ps
CPU time 12.73 seconds
Started May 21 01:08:58 PM PDT 24
Finished May 21 01:09:13 PM PDT 24
Peak memory 205344 kb
Host smart-5dc04e8d-e2c9-4491-9090-775ac095243d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25343
23976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2534323976
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.1437355538
Short name T1159
Test name
Test status
Simulation time 8371723898 ps
CPU time 11.76 seconds
Started May 21 01:08:56 PM PDT 24
Finished May 21 01:09:08 PM PDT 24
Peak memory 205316 kb
Host smart-01f84bb7-c466-421d-bbc8-7c68b0e0d179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14373
55538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1437355538
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2129774103
Short name T1258
Test name
Test status
Simulation time 8418579810 ps
CPU time 12.53 seconds
Started May 21 01:08:58 PM PDT 24
Finished May 21 01:09:11 PM PDT 24
Peak memory 205424 kb
Host smart-258b3711-7f5b-477d-bcee-f97c358b94f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21297
74103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2129774103
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.497244948
Short name T830
Test name
Test status
Simulation time 8453215623 ps
CPU time 12.31 seconds
Started May 21 01:08:52 PM PDT 24
Finished May 21 01:09:05 PM PDT 24
Peak memory 205440 kb
Host smart-973272a6-0307-42b9-afaf-a0500681c4b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49724
4948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.497244948
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.1402249483
Short name T1567
Test name
Test status
Simulation time 8397902248 ps
CPU time 14.8 seconds
Started May 21 01:08:56 PM PDT 24
Finished May 21 01:09:12 PM PDT 24
Peak memory 205308 kb
Host smart-ce4ec953-dfcc-4b1d-a6fe-b511b5978768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14022
49483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.1402249483
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.3168190594
Short name T844
Test name
Test status
Simulation time 8395750919 ps
CPU time 11.68 seconds
Started May 21 01:08:58 PM PDT 24
Finished May 21 01:09:12 PM PDT 24
Peak memory 205344 kb
Host smart-1543ced2-871d-4c5d-8677-283d26dd0b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31681
90594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.3168190594
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.892317036
Short name T1610
Test name
Test status
Simulation time 8462044681 ps
CPU time 12 seconds
Started May 21 01:09:09 PM PDT 24
Finished May 21 01:09:22 PM PDT 24
Peak memory 205324 kb
Host smart-1ce8f5f6-08c7-46e7-9bdb-da70a50ffa7b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=892317036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.892317036
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.1620287407
Short name T92
Test name
Test status
Simulation time 8374322637 ps
CPU time 11.34 seconds
Started May 21 01:09:08 PM PDT 24
Finished May 21 01:09:20 PM PDT 24
Peak memory 205424 kb
Host smart-1a1ab851-c6c7-4a67-860e-e507c8c7af68
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1620287407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.1620287407
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.2465511805
Short name T1638
Test name
Test status
Simulation time 8516665374 ps
CPU time 13.31 seconds
Started May 21 01:09:08 PM PDT 24
Finished May 21 01:09:22 PM PDT 24
Peak memory 205400 kb
Host smart-86570dea-fa9b-4e96-bbfa-c829cc9a6582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24655
11805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.2465511805
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.1957059216
Short name T286
Test name
Test status
Simulation time 8379185678 ps
CPU time 12.24 seconds
Started May 21 01:09:04 PM PDT 24
Finished May 21 01:09:18 PM PDT 24
Peak memory 205448 kb
Host smart-6c45656e-7573-4fe7-8327-dc57c277751f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19570
59216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.1957059216
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.1573441084
Short name T16
Test name
Test status
Simulation time 9541971191 ps
CPU time 14.1 seconds
Started May 21 01:09:05 PM PDT 24
Finished May 21 01:09:21 PM PDT 24
Peak memory 205376 kb
Host smart-720c4003-a8da-4833-b0be-8e7247f998fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15734
41084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.1573441084
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.762898559
Short name T791
Test name
Test status
Simulation time 8431229453 ps
CPU time 12.2 seconds
Started May 21 01:09:10 PM PDT 24
Finished May 21 01:09:24 PM PDT 24
Peak memory 205312 kb
Host smart-01a15e30-c959-4ea8-b29b-618b38e6b332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76289
8559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.762898559
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.383717034
Short name T474
Test name
Test status
Simulation time 8382102207 ps
CPU time 13.64 seconds
Started May 21 01:09:13 PM PDT 24
Finished May 21 01:09:28 PM PDT 24
Peak memory 205396 kb
Host smart-31c1d54e-ea5c-4b39-af21-b779d99de5fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38371
7034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.383717034
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.2229257225
Short name T961
Test name
Test status
Simulation time 9073415190 ps
CPU time 14.03 seconds
Started May 21 01:09:05 PM PDT 24
Finished May 21 01:09:21 PM PDT 24
Peak memory 205380 kb
Host smart-f76c5428-a08f-4a69-bbae-4f998eae04e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22292
57225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.2229257225
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.521376163
Short name T66
Test name
Test status
Simulation time 8550348069 ps
CPU time 13.31 seconds
Started May 21 01:09:03 PM PDT 24
Finished May 21 01:09:18 PM PDT 24
Peak memory 205320 kb
Host smart-327714ff-43e6-4121-98cf-0e75b56381fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52137
6163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.521376163
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.1792039220
Short name T1639
Test name
Test status
Simulation time 8404383203 ps
CPU time 12.25 seconds
Started May 21 01:09:11 PM PDT 24
Finished May 21 01:09:25 PM PDT 24
Peak memory 205336 kb
Host smart-62a77e59-6965-410f-88f4-7004bb53ab77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17920
39220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.1792039220
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.1547998543
Short name T817
Test name
Test status
Simulation time 8400175200 ps
CPU time 11.57 seconds
Started May 21 01:09:10 PM PDT 24
Finished May 21 01:09:23 PM PDT 24
Peak memory 205328 kb
Host smart-7b73641d-f80b-4ae7-bfc3-117df3ec849d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15479
98543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.1547998543
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.3490790367
Short name T384
Test name
Test status
Simulation time 8477432282 ps
CPU time 13.31 seconds
Started May 21 01:09:03 PM PDT 24
Finished May 21 01:09:19 PM PDT 24
Peak memory 205312 kb
Host smart-ed7debb4-fbb0-4b04-ba6e-85b1c8d1e70b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34907
90367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3490790367
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.2452953249
Short name T332
Test name
Test status
Simulation time 11488378222 ps
CPU time 15.5 seconds
Started May 21 01:09:09 PM PDT 24
Finished May 21 01:09:26 PM PDT 24
Peak memory 205384 kb
Host smart-32dbff43-8ca5-4762-a211-9d99da2e323c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24529
53249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.2452953249
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.1156521771
Short name T1032
Test name
Test status
Simulation time 8416974988 ps
CPU time 13.64 seconds
Started May 21 01:09:06 PM PDT 24
Finished May 21 01:09:21 PM PDT 24
Peak memory 205292 kb
Host smart-3cdf62fb-12e2-4a3a-b8f2-f0625c3e5e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11565
21771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.1156521771
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.291722972
Short name T373
Test name
Test status
Simulation time 8382506811 ps
CPU time 12.68 seconds
Started May 21 01:09:04 PM PDT 24
Finished May 21 01:09:19 PM PDT 24
Peak memory 205280 kb
Host smart-55a27bc7-d28c-4fda-99c1-efe136212b1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29172
2972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.291722972
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.2993958780
Short name T122
Test name
Test status
Simulation time 8448558159 ps
CPU time 13.46 seconds
Started May 21 01:09:08 PM PDT 24
Finished May 21 01:09:23 PM PDT 24
Peak memory 205356 kb
Host smart-30e32314-a5a7-454c-a715-62d1d59115a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29939
58780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.2993958780
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.2293290640
Short name T634
Test name
Test status
Simulation time 8424066751 ps
CPU time 12.9 seconds
Started May 21 01:09:09 PM PDT 24
Finished May 21 01:09:23 PM PDT 24
Peak memory 205320 kb
Host smart-f7242b87-e247-4838-a556-2fee60f511bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22932
90640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.2293290640
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.1908531507
Short name T1618
Test name
Test status
Simulation time 8401722240 ps
CPU time 12.68 seconds
Started May 21 01:09:10 PM PDT 24
Finished May 21 01:09:24 PM PDT 24
Peak memory 205408 kb
Host smart-06d1f58e-eec1-4430-8142-9de9141cb474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19085
31507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.1908531507
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.4045611422
Short name T1227
Test name
Test status
Simulation time 8424612526 ps
CPU time 13.85 seconds
Started May 21 01:09:16 PM PDT 24
Finished May 21 01:09:31 PM PDT 24
Peak memory 205368 kb
Host smart-13dbacf5-90a2-4492-b203-465600b92372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40456
11422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.4045611422
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.309811530
Short name T1727
Test name
Test status
Simulation time 8413110034 ps
CPU time 12.83 seconds
Started May 21 01:09:15 PM PDT 24
Finished May 21 01:09:30 PM PDT 24
Peak memory 205360 kb
Host smart-6ce42cbc-3a1b-4c9d-864e-ddd8c343608a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30981
1530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.309811530
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_eop_single_bit_handling.1590807153
Short name T932
Test name
Test status
Simulation time 8396962749 ps
CPU time 11.45 seconds
Started May 21 01:09:10 PM PDT 24
Finished May 21 01:09:23 PM PDT 24
Peak memory 205432 kb
Host smart-2db59641-fd65-4657-b64f-f144f3f561bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15908
07153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_eop_single_bit_handling.1590807153
Directory /workspace/24.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.4213948179
Short name T1659
Test name
Test status
Simulation time 8368751893 ps
CPU time 12.41 seconds
Started May 21 01:09:11 PM PDT 24
Finished May 21 01:09:25 PM PDT 24
Peak memory 205388 kb
Host smart-5ffaa3f2-54cf-427d-a635-2d885c1e5616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42139
48179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.4213948179
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2434623882
Short name T1197
Test name
Test status
Simulation time 8380820275 ps
CPU time 11.95 seconds
Started May 21 01:09:11 PM PDT 24
Finished May 21 01:09:24 PM PDT 24
Peak memory 205328 kb
Host smart-3f2a8d90-151d-4465-9b77-c91e453472fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24346
23882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2434623882
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.2437218939
Short name T1372
Test name
Test status
Simulation time 8399754494 ps
CPU time 12.77 seconds
Started May 21 01:09:08 PM PDT 24
Finished May 21 01:09:22 PM PDT 24
Peak memory 205360 kb
Host smart-b5d353c5-cec8-4b3d-9ea2-6def4cdf79f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24372
18939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.2437218939
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.86304551
Short name T622
Test name
Test status
Simulation time 8459720253 ps
CPU time 12.13 seconds
Started May 21 01:09:15 PM PDT 24
Finished May 21 01:09:28 PM PDT 24
Peak memory 205392 kb
Host smart-b9c6fc99-6a57-48a0-815f-d87904ddf9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86304
551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.86304551
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.2443912045
Short name T680
Test name
Test status
Simulation time 8416668377 ps
CPU time 11.83 seconds
Started May 21 01:09:09 PM PDT 24
Finished May 21 01:09:22 PM PDT 24
Peak memory 205300 kb
Host smart-401cf375-aaf7-42db-a14f-c2c3a5353c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24439
12045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.2443912045
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.1922519193
Short name T1474
Test name
Test status
Simulation time 8388315682 ps
CPU time 11.23 seconds
Started May 21 01:09:08 PM PDT 24
Finished May 21 01:09:20 PM PDT 24
Peak memory 205368 kb
Host smart-ad052d03-e7b2-4736-a99d-0141a4ca7db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19225
19193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.1922519193
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.971026472
Short name T1205
Test name
Test status
Simulation time 8411605763 ps
CPU time 12.4 seconds
Started May 21 01:09:10 PM PDT 24
Finished May 21 01:09:23 PM PDT 24
Peak memory 205376 kb
Host smart-894347a0-eb99-460c-b5ec-243ec11fb119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97102
6472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.971026472
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.4164573625
Short name T38
Test name
Test status
Simulation time 8377353675 ps
CPU time 13.04 seconds
Started May 21 01:09:16 PM PDT 24
Finished May 21 01:09:30 PM PDT 24
Peak memory 205408 kb
Host smart-200d399e-c41a-4b78-970e-6803e123e7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41645
73625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.4164573625
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.302048754
Short name T1296
Test name
Test status
Simulation time 8413299144 ps
CPU time 11.81 seconds
Started May 21 01:09:10 PM PDT 24
Finished May 21 01:09:23 PM PDT 24
Peak memory 205448 kb
Host smart-797f2e01-b49e-4544-a3a8-791ae1d33ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30204
8754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.302048754
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3199306177
Short name T1223
Test name
Test status
Simulation time 8414735781 ps
CPU time 11.49 seconds
Started May 21 01:09:09 PM PDT 24
Finished May 21 01:09:22 PM PDT 24
Peak memory 205408 kb
Host smart-81a12543-8d86-4068-b71d-0e56c1ce6203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31993
06177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3199306177
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.3727421823
Short name T831
Test name
Test status
Simulation time 8401747874 ps
CPU time 11.58 seconds
Started May 21 01:09:11 PM PDT 24
Finished May 21 01:09:24 PM PDT 24
Peak memory 205264 kb
Host smart-66c350c7-b2ea-4230-8c9c-d5c31e53f2bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37274
21823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.3727421823
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.3675718848
Short name T48
Test name
Test status
Simulation time 8486132453 ps
CPU time 12 seconds
Started May 21 01:09:20 PM PDT 24
Finished May 21 01:09:33 PM PDT 24
Peak memory 205304 kb
Host smart-a0674dc9-f5ae-4b93-b825-b7b798a0b67e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3675718848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.3675718848
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.2768504264
Short name T1194
Test name
Test status
Simulation time 8382566686 ps
CPU time 12.62 seconds
Started May 21 01:09:22 PM PDT 24
Finished May 21 01:09:36 PM PDT 24
Peak memory 205312 kb
Host smart-3bee6d99-ac10-4300-aa6b-7ae202dd4033
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2768504264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.2768504264
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.1295878769
Short name T1413
Test name
Test status
Simulation time 8454541806 ps
CPU time 13.02 seconds
Started May 21 01:09:20 PM PDT 24
Finished May 21 01:09:34 PM PDT 24
Peak memory 205432 kb
Host smart-0bfefc35-48c1-49b4-9832-1cf893b3f6dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12958
78769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.1295878769
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.2098181433
Short name T372
Test name
Test status
Simulation time 8373450593 ps
CPU time 13.54 seconds
Started May 21 01:09:14 PM PDT 24
Finished May 21 01:09:28 PM PDT 24
Peak memory 205300 kb
Host smart-ae4bf0a3-c1a0-4399-be5a-1fc2e9a7049e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20981
81433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2098181433
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.4190574676
Short name T1636
Test name
Test status
Simulation time 9366074241 ps
CPU time 14.23 seconds
Started May 21 01:09:16 PM PDT 24
Finished May 21 01:09:32 PM PDT 24
Peak memory 205356 kb
Host smart-27ebd5ac-9090-4163-96a9-e601424f2155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41905
74676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.4190574676
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.586286152
Short name T1400
Test name
Test status
Simulation time 8377876829 ps
CPU time 12.53 seconds
Started May 21 01:09:16 PM PDT 24
Finished May 21 01:09:30 PM PDT 24
Peak memory 205308 kb
Host smart-e8f397c4-4060-4012-b5ac-c71041d0f5c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58628
6152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.586286152
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.3610938793
Short name T996
Test name
Test status
Simulation time 8385389533 ps
CPU time 11.63 seconds
Started May 21 01:09:17 PM PDT 24
Finished May 21 01:09:31 PM PDT 24
Peak memory 205352 kb
Host smart-da32e70c-b141-4b46-bf74-b554511d85fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36109
38793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3610938793
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1497520624
Short name T1487
Test name
Test status
Simulation time 9151307349 ps
CPU time 13.19 seconds
Started May 21 01:09:16 PM PDT 24
Finished May 21 01:09:31 PM PDT 24
Peak memory 205372 kb
Host smart-5b3a6759-066b-41ed-b929-6f266d331dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14975
20624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1497520624
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.3207272143
Short name T633
Test name
Test status
Simulation time 8494695258 ps
CPU time 13.92 seconds
Started May 21 01:09:19 PM PDT 24
Finished May 21 01:09:34 PM PDT 24
Peak memory 205236 kb
Host smart-03d8a1ca-4db1-47c2-8430-bd77bb7e87b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32072
72143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.3207272143
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.1088227250
Short name T665
Test name
Test status
Simulation time 8482650577 ps
CPU time 12.73 seconds
Started May 21 01:09:22 PM PDT 24
Finished May 21 01:09:36 PM PDT 24
Peak memory 205372 kb
Host smart-71f54d6b-8e8e-4ce0-8a2c-8a00a964330a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10882
27250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.1088227250
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.4116462146
Short name T1009
Test name
Test status
Simulation time 8372695203 ps
CPU time 12.29 seconds
Started May 21 01:09:22 PM PDT 24
Finished May 21 01:09:36 PM PDT 24
Peak memory 205376 kb
Host smart-c8e1dac0-c76b-416b-888c-0cf74daca954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41164
62146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.4116462146
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3179240797
Short name T1281
Test name
Test status
Simulation time 8379229356 ps
CPU time 13.86 seconds
Started May 21 01:09:17 PM PDT 24
Finished May 21 01:09:33 PM PDT 24
Peak memory 205256 kb
Host smart-fdbd9c67-3070-465a-8e87-cc23dab559a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31792
40797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3179240797
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.2591446034
Short name T438
Test name
Test status
Simulation time 11552283576 ps
CPU time 14.53 seconds
Started May 21 01:09:18 PM PDT 24
Finished May 21 01:09:34 PM PDT 24
Peak memory 205236 kb
Host smart-6be1192a-2940-4f06-94bc-cdfdb9234421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25914
46034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.2591446034
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1123408313
Short name T327
Test name
Test status
Simulation time 8439969284 ps
CPU time 11 seconds
Started May 21 01:09:21 PM PDT 24
Finished May 21 01:09:34 PM PDT 24
Peak memory 205372 kb
Host smart-fe30991b-d019-42b5-9d90-19d4b2f56add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11234
08313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1123408313
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.3410841527
Short name T846
Test name
Test status
Simulation time 8378628890 ps
CPU time 10.8 seconds
Started May 21 01:09:21 PM PDT 24
Finished May 21 01:09:33 PM PDT 24
Peak memory 205408 kb
Host smart-82e4f0c1-3840-4578-bd1c-46e14240f751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34108
41527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.3410841527
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.2782010776
Short name T1598
Test name
Test status
Simulation time 8415769411 ps
CPU time 11.83 seconds
Started May 21 01:09:19 PM PDT 24
Finished May 21 01:09:32 PM PDT 24
Peak memory 205288 kb
Host smart-2fe8ce38-a8f5-44e2-8576-bfc36ee23357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27820
10776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.2782010776
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.1262156453
Short name T1065
Test name
Test status
Simulation time 8427150394 ps
CPU time 14.84 seconds
Started May 21 01:09:17 PM PDT 24
Finished May 21 01:09:34 PM PDT 24
Peak memory 205308 kb
Host smart-d76ca748-502e-4f28-8227-31d4aba9d80f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12621
56453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.1262156453
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3785144402
Short name T1277
Test name
Test status
Simulation time 8384806664 ps
CPU time 10.99 seconds
Started May 21 01:09:17 PM PDT 24
Finished May 21 01:09:30 PM PDT 24
Peak memory 205304 kb
Host smart-6770a3c4-5bc7-4bd2-9e9e-dd64477f08c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37851
44402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3785144402
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1035993582
Short name T486
Test name
Test status
Simulation time 8412069427 ps
CPU time 11.7 seconds
Started May 21 01:09:16 PM PDT 24
Finished May 21 01:09:30 PM PDT 24
Peak memory 205408 kb
Host smart-ab46f42d-e0d1-4947-b876-4bef660d695a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10359
93582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1035993582
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.211385021
Short name T165
Test name
Test status
Simulation time 8390141140 ps
CPU time 11.89 seconds
Started May 21 01:09:17 PM PDT 24
Finished May 21 01:09:31 PM PDT 24
Peak memory 205232 kb
Host smart-92081005-68e4-4d42-9179-2497feb530b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21138
5021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.211385021
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_eop_single_bit_handling.134116807
Short name T1165
Test name
Test status
Simulation time 8387946095 ps
CPU time 12.66 seconds
Started May 21 01:09:16 PM PDT 24
Finished May 21 01:09:31 PM PDT 24
Peak memory 205432 kb
Host smart-78ceddc5-a1d3-4806-bca0-a116bca192f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13411
6807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_eop_single_bit_handling.134116807
Directory /workspace/25.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.3930662320
Short name T1207
Test name
Test status
Simulation time 8376827721 ps
CPU time 13.24 seconds
Started May 21 01:09:22 PM PDT 24
Finished May 21 01:09:36 PM PDT 24
Peak memory 205340 kb
Host smart-c59e94d6-2679-41f2-9e92-0891bd2feb82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39306
62320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.3930662320
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2384541085
Short name T23
Test name
Test status
Simulation time 8374705484 ps
CPU time 11.03 seconds
Started May 21 01:09:21 PM PDT 24
Finished May 21 01:09:33 PM PDT 24
Peak memory 205308 kb
Host smart-285c6131-f593-414c-b714-34046845e7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23845
41085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2384541085
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1667200782
Short name T1330
Test name
Test status
Simulation time 8397745517 ps
CPU time 15.71 seconds
Started May 21 01:09:17 PM PDT 24
Finished May 21 01:09:35 PM PDT 24
Peak memory 205384 kb
Host smart-77429259-2900-4a56-9f80-cd696ff188c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16672
00782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1667200782
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.4075565256
Short name T1058
Test name
Test status
Simulation time 8389659214 ps
CPU time 14.38 seconds
Started May 21 01:09:14 PM PDT 24
Finished May 21 01:09:30 PM PDT 24
Peak memory 205360 kb
Host smart-1af0b22a-6db0-4fcb-a47c-cc3b47b844d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40755
65256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.4075565256
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.1703059655
Short name T776
Test name
Test status
Simulation time 8407085317 ps
CPU time 12.64 seconds
Started May 21 01:09:16 PM PDT 24
Finished May 21 01:09:30 PM PDT 24
Peak memory 205252 kb
Host smart-98206a1d-853f-451c-b815-97efb4a40409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17030
59655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.1703059655
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.322498917
Short name T891
Test name
Test status
Simulation time 8395650769 ps
CPU time 13.29 seconds
Started May 21 01:09:16 PM PDT 24
Finished May 21 01:09:31 PM PDT 24
Peak memory 205328 kb
Host smart-904bc94f-5981-48f6-b384-0b5c3369562c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32249
8917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.322498917
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.1940180482
Short name T1432
Test name
Test status
Simulation time 8380738888 ps
CPU time 11.52 seconds
Started May 21 01:09:16 PM PDT 24
Finished May 21 01:09:29 PM PDT 24
Peak memory 205240 kb
Host smart-87448664-622a-4a1c-bdbc-8b46ecba6a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19401
80482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.1940180482
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.2763415476
Short name T316
Test name
Test status
Simulation time 8381805554 ps
CPU time 11.63 seconds
Started May 21 01:09:17 PM PDT 24
Finished May 21 01:09:31 PM PDT 24
Peak memory 205448 kb
Host smart-c73cdab7-4dc6-4109-a879-df8daca6817c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27634
15476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.2763415476
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1307436936
Short name T1011
Test name
Test status
Simulation time 8394804217 ps
CPU time 11.3 seconds
Started May 21 01:09:14 PM PDT 24
Finished May 21 01:09:27 PM PDT 24
Peak memory 205368 kb
Host smart-283c1ee9-ed2b-4229-8f98-3ab406772aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13074
36936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1307436936
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.910653885
Short name T1215
Test name
Test status
Simulation time 8378994192 ps
CPU time 11.9 seconds
Started May 21 01:09:18 PM PDT 24
Finished May 21 01:09:32 PM PDT 24
Peak memory 205268 kb
Host smart-ce0b6793-a3fb-49c7-aa96-f42a10a80f37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91065
3885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.910653885
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.4078829079
Short name T340
Test name
Test status
Simulation time 8456223898 ps
CPU time 12.04 seconds
Started May 21 01:09:18 PM PDT 24
Finished May 21 01:09:32 PM PDT 24
Peak memory 205356 kb
Host smart-3826e891-18a1-4c91-ac3b-4f2075e1619a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40788
29079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.4078829079
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.2584875700
Short name T651
Test name
Test status
Simulation time 8374013051 ps
CPU time 11.31 seconds
Started May 21 01:09:37 PM PDT 24
Finished May 21 01:09:49 PM PDT 24
Peak memory 205348 kb
Host smart-a16462c6-f100-4180-bc48-3f0e1fcc96aa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2584875700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.2584875700
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.1865111414
Short name T1235
Test name
Test status
Simulation time 8462950936 ps
CPU time 11.4 seconds
Started May 21 01:09:38 PM PDT 24
Finished May 21 01:09:52 PM PDT 24
Peak memory 205256 kb
Host smart-167f3082-253e-489b-b2cc-fa541b2fbfa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18651
11414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.1865111414
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.613405411
Short name T451
Test name
Test status
Simulation time 8386328159 ps
CPU time 13.46 seconds
Started May 21 01:09:23 PM PDT 24
Finished May 21 01:09:37 PM PDT 24
Peak memory 205292 kb
Host smart-9592370e-dc30-4564-bb9b-a813f6662a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61340
5411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.613405411
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.1007479995
Short name T911
Test name
Test status
Simulation time 8396280855 ps
CPU time 11.36 seconds
Started May 21 01:09:22 PM PDT 24
Finished May 21 01:09:34 PM PDT 24
Peak memory 205320 kb
Host smart-08a95d1b-b63f-4ca6-92ac-f57f1d8ca977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10074
79995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.1007479995
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.907794292
Short name T390
Test name
Test status
Simulation time 9046907714 ps
CPU time 12.96 seconds
Started May 21 01:09:21 PM PDT 24
Finished May 21 01:09:36 PM PDT 24
Peak memory 205232 kb
Host smart-8c38183e-e0c5-49fd-8cbf-9380632b6457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90779
4292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.907794292
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.2223921317
Short name T1645
Test name
Test status
Simulation time 8441084741 ps
CPU time 11.63 seconds
Started May 21 01:09:31 PM PDT 24
Finished May 21 01:09:45 PM PDT 24
Peak memory 205380 kb
Host smart-f1b9d155-bb1a-443e-85c5-2b664631a07e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22239
21317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2223921317
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.1795243554
Short name T1062
Test name
Test status
Simulation time 8402949476 ps
CPU time 14.16 seconds
Started May 21 01:09:23 PM PDT 24
Finished May 21 01:09:38 PM PDT 24
Peak memory 205348 kb
Host smart-14a1217e-b4bd-4309-af1e-61ad8601157e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17952
43554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.1795243554
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.2578270248
Short name T597
Test name
Test status
Simulation time 9081538693 ps
CPU time 13.44 seconds
Started May 21 01:09:22 PM PDT 24
Finished May 21 01:09:37 PM PDT 24
Peak memory 205384 kb
Host smart-65e40134-0fe3-468a-b2f9-9fd47b3bf0ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25782
70248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.2578270248
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.2111021872
Short name T95
Test name
Test status
Simulation time 8383933782 ps
CPU time 12.71 seconds
Started May 21 01:09:29 PM PDT 24
Finished May 21 01:09:44 PM PDT 24
Peak memory 205320 kb
Host smart-55cc34de-d0fa-4004-8402-7e945d1a97fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21110
21872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.2111021872
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.1866747773
Short name T1125
Test name
Test status
Simulation time 8435196713 ps
CPU time 11.17 seconds
Started May 21 01:09:37 PM PDT 24
Finished May 21 01:09:51 PM PDT 24
Peak memory 205276 kb
Host smart-655c0297-f883-4d67-96bd-c8db3aafb676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18667
47773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.1866747773
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.3972015093
Short name T703
Test name
Test status
Simulation time 8372958880 ps
CPU time 11.76 seconds
Started May 21 01:09:34 PM PDT 24
Finished May 21 01:09:47 PM PDT 24
Peak memory 205344 kb
Host smart-7e2f5377-5783-490c-82cd-b256a296db03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39720
15093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.3972015093
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3076171819
Short name T385
Test name
Test status
Simulation time 8439551723 ps
CPU time 11.33 seconds
Started May 21 01:09:32 PM PDT 24
Finished May 21 01:09:45 PM PDT 24
Peak memory 205360 kb
Host smart-43092d5a-6eae-4a8e-8b31-63364d446eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30761
71819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3076171819
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.421591522
Short name T369
Test name
Test status
Simulation time 11532249041 ps
CPU time 15.64 seconds
Started May 21 01:09:29 PM PDT 24
Finished May 21 01:09:46 PM PDT 24
Peak memory 205312 kb
Host smart-7f8c676d-085e-4538-82d4-37744ba49c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42159
1522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.421591522
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.2248705419
Short name T1449
Test name
Test status
Simulation time 8485127051 ps
CPU time 13.82 seconds
Started May 21 01:09:30 PM PDT 24
Finished May 21 01:09:46 PM PDT 24
Peak memory 205408 kb
Host smart-f5f41e40-5b59-476b-a520-4097715018b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22487
05419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.2248705419
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2566808616
Short name T417
Test name
Test status
Simulation time 8382566311 ps
CPU time 13.07 seconds
Started May 21 01:09:31 PM PDT 24
Finished May 21 01:09:46 PM PDT 24
Peak memory 205356 kb
Host smart-ef564ba9-541b-4638-b78c-4d40e753d520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25668
08616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2566808616
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2456091338
Short name T145
Test name
Test status
Simulation time 8416114284 ps
CPU time 13.27 seconds
Started May 21 01:09:30 PM PDT 24
Finished May 21 01:09:45 PM PDT 24
Peak memory 205392 kb
Host smart-d658a790-80ee-421c-8865-bcf568486741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24560
91338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2456091338
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.321090586
Short name T647
Test name
Test status
Simulation time 8415065870 ps
CPU time 11.73 seconds
Started May 21 01:09:30 PM PDT 24
Finished May 21 01:09:44 PM PDT 24
Peak memory 205424 kb
Host smart-dc41c778-04d0-4c6c-b250-63aecfa142c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32109
0586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.321090586
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.3415192261
Short name T1354
Test name
Test status
Simulation time 8416906562 ps
CPU time 11.81 seconds
Started May 21 01:09:29 PM PDT 24
Finished May 21 01:09:41 PM PDT 24
Peak memory 205328 kb
Host smart-4dd2cc1a-97d7-4121-8e2d-55b48e5b075a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34151
92261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.3415192261
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.760645329
Short name T22
Test name
Test status
Simulation time 8405752970 ps
CPU time 14.39 seconds
Started May 21 01:09:31 PM PDT 24
Finished May 21 01:09:47 PM PDT 24
Peak memory 205412 kb
Host smart-3f33ef54-94d2-40f4-afd0-cac117768509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76064
5329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.760645329
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_eop_single_bit_handling.1804612253
Short name T1131
Test name
Test status
Simulation time 8416639529 ps
CPU time 12.67 seconds
Started May 21 01:09:31 PM PDT 24
Finished May 21 01:09:46 PM PDT 24
Peak memory 205360 kb
Host smart-74d7e789-88d3-47b6-b91c-c7c379519b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18046
12253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_eop_single_bit_handling.1804612253
Directory /workspace/26.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.224331041
Short name T972
Test name
Test status
Simulation time 8412280226 ps
CPU time 12.64 seconds
Started May 21 01:09:32 PM PDT 24
Finished May 21 01:09:46 PM PDT 24
Peak memory 205312 kb
Host smart-9a5d3206-38ce-4c83-99c4-acce2220e1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22433
1041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.224331041
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3181244243
Short name T1540
Test name
Test status
Simulation time 8464339785 ps
CPU time 12.94 seconds
Started May 21 01:09:29 PM PDT 24
Finished May 21 01:09:42 PM PDT 24
Peak memory 205340 kb
Host smart-3f518b89-9dcf-48df-8178-88924ccfc0c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31812
44243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3181244243
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.1726473463
Short name T364
Test name
Test status
Simulation time 8399806704 ps
CPU time 12.1 seconds
Started May 21 01:09:31 PM PDT 24
Finished May 21 01:09:45 PM PDT 24
Peak memory 205400 kb
Host smart-cb6dcb0c-26e6-4a2a-97cb-0eb42f739fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17264
73463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.1726473463
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2857008854
Short name T311
Test name
Test status
Simulation time 8435910451 ps
CPU time 13.05 seconds
Started May 21 01:09:32 PM PDT 24
Finished May 21 01:09:46 PM PDT 24
Peak memory 205352 kb
Host smart-7251f46a-d8dd-44ac-93a0-7821ba2aaf3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28570
08854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2857008854
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.3132280487
Short name T1397
Test name
Test status
Simulation time 8413002602 ps
CPU time 11.63 seconds
Started May 21 01:09:29 PM PDT 24
Finished May 21 01:09:43 PM PDT 24
Peak memory 205348 kb
Host smart-87617c57-c3eb-4ad4-bb9c-7c815d2dbfb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31322
80487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.3132280487
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1623480561
Short name T20
Test name
Test status
Simulation time 8371376166 ps
CPU time 11.35 seconds
Started May 21 01:09:30 PM PDT 24
Finished May 21 01:09:43 PM PDT 24
Peak memory 205316 kb
Host smart-4aa9025b-4909-4862-a019-ea7be780540a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16234
80561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1623480561
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3676439769
Short name T924
Test name
Test status
Simulation time 8393607477 ps
CPU time 13.12 seconds
Started May 21 01:09:31 PM PDT 24
Finished May 21 01:09:46 PM PDT 24
Peak memory 205364 kb
Host smart-e715103c-0770-480c-8a06-e7392d801814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36764
39769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3676439769
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.1952879647
Short name T1489
Test name
Test status
Simulation time 8397103912 ps
CPU time 11.8 seconds
Started May 21 01:09:33 PM PDT 24
Finished May 21 01:09:46 PM PDT 24
Peak memory 205372 kb
Host smart-5cd85f47-86d8-4ff7-a8a6-2ed57aea795c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19528
79647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.1952879647
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.1486771715
Short name T1168
Test name
Test status
Simulation time 8489528179 ps
CPU time 13.94 seconds
Started May 21 01:09:21 PM PDT 24
Finished May 21 01:09:37 PM PDT 24
Peak memory 205392 kb
Host smart-59956784-fe01-4019-88ef-931d94993881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14867
71715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1486771715
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.68890636
Short name T836
Test name
Test status
Simulation time 8411498737 ps
CPU time 11.89 seconds
Started May 21 01:09:30 PM PDT 24
Finished May 21 01:09:44 PM PDT 24
Peak memory 205320 kb
Host smart-ffea6612-af5a-46ba-80ca-2512b201036b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68890
636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.68890636
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.2538814372
Short name T652
Test name
Test status
Simulation time 8473703968 ps
CPU time 12.69 seconds
Started May 21 01:09:40 PM PDT 24
Finished May 21 01:09:55 PM PDT 24
Peak memory 205352 kb
Host smart-0cd68195-63b3-4d1d-9dab-f31b0232fe7b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2538814372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.2538814372
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.2660672544
Short name T859
Test name
Test status
Simulation time 8380907914 ps
CPU time 12.53 seconds
Started May 21 01:09:38 PM PDT 24
Finished May 21 01:09:53 PM PDT 24
Peak memory 205356 kb
Host smart-fac6ce0a-79a3-4b29-b304-e75aa6e80ab3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2660672544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.2660672544
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.3867642050
Short name T731
Test name
Test status
Simulation time 8417673951 ps
CPU time 11.43 seconds
Started May 21 01:09:38 PM PDT 24
Finished May 21 01:09:51 PM PDT 24
Peak memory 205356 kb
Host smart-b1eb9f5d-cd47-4efe-9c5c-eaff13174e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38676
42050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.3867642050
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.1450766941
Short name T1418
Test name
Test status
Simulation time 8432465544 ps
CPU time 12.24 seconds
Started May 21 01:09:37 PM PDT 24
Finished May 21 01:09:51 PM PDT 24
Peak memory 205348 kb
Host smart-ffbfe7e2-8861-4641-9489-501e3ad1b201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14507
66941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.1450766941
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.2976068465
Short name T661
Test name
Test status
Simulation time 8372107613 ps
CPU time 13.11 seconds
Started May 21 01:09:39 PM PDT 24
Finished May 21 01:09:55 PM PDT 24
Peak memory 204324 kb
Host smart-dc8292c5-f7e5-4cb2-a8c4-3709831cd0c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29760
68465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.2976068465
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.1614005840
Short name T1257
Test name
Test status
Simulation time 9109133289 ps
CPU time 12.92 seconds
Started May 21 01:09:32 PM PDT 24
Finished May 21 01:09:47 PM PDT 24
Peak memory 205392 kb
Host smart-4d6210cb-4d61-4ffa-9871-b99ef64bf506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16140
05840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.1614005840
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.1910317899
Short name T352
Test name
Test status
Simulation time 8362998099 ps
CPU time 10.95 seconds
Started May 21 01:09:33 PM PDT 24
Finished May 21 01:09:45 PM PDT 24
Peak memory 205344 kb
Host smart-42886cd0-d167-4c4c-b633-fe1100ff286d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19103
17899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.1910317899
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.2040714610
Short name T1683
Test name
Test status
Simulation time 8380232009 ps
CPU time 11.5 seconds
Started May 21 01:09:34 PM PDT 24
Finished May 21 01:09:46 PM PDT 24
Peak memory 205412 kb
Host smart-a99cfffc-44b8-4add-b3ab-f09aeebd864f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20407
14610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2040714610
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.2886717686
Short name T278
Test name
Test status
Simulation time 9128562813 ps
CPU time 12.46 seconds
Started May 21 01:09:34 PM PDT 24
Finished May 21 01:09:47 PM PDT 24
Peak memory 205284 kb
Host smart-47fd7944-7506-47f5-b326-8e3e305a36c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28867
17686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.2886717686
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.4205044189
Short name T1272
Test name
Test status
Simulation time 8484862907 ps
CPU time 14.81 seconds
Started May 21 01:09:38 PM PDT 24
Finished May 21 01:09:56 PM PDT 24
Peak memory 205312 kb
Host smart-3853bf53-a646-4da7-842f-6b58d90da245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42050
44189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.4205044189
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.1882041438
Short name T733
Test name
Test status
Simulation time 8445894104 ps
CPU time 11.17 seconds
Started May 21 01:09:38 PM PDT 24
Finished May 21 01:09:51 PM PDT 24
Peak memory 205332 kb
Host smart-c115b6b5-6e5f-4fb4-a4f2-192da5fc26c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18820
41438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.1882041438
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.1349690975
Short name T1146
Test name
Test status
Simulation time 8389401186 ps
CPU time 12.61 seconds
Started May 21 01:09:38 PM PDT 24
Finished May 21 01:09:53 PM PDT 24
Peak memory 205348 kb
Host smart-ea0e4398-0062-493b-9272-f7823cd41c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13496
90975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.1349690975
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.2273821173
Short name T1485
Test name
Test status
Simulation time 8390854081 ps
CPU time 14.65 seconds
Started May 21 01:09:39 PM PDT 24
Finished May 21 01:09:56 PM PDT 24
Peak memory 204396 kb
Host smart-de9b2ff4-9a8a-422d-a96e-723e61ca37b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22738
21173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.2273821173
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.940814677
Short name T883
Test name
Test status
Simulation time 11548715178 ps
CPU time 14.69 seconds
Started May 21 01:09:37 PM PDT 24
Finished May 21 01:09:53 PM PDT 24
Peak memory 205280 kb
Host smart-d8b40c2a-87af-4502-aa6d-033b154831dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94081
4677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.940814677
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.55906095
Short name T1377
Test name
Test status
Simulation time 8413981832 ps
CPU time 11.32 seconds
Started May 21 01:09:33 PM PDT 24
Finished May 21 01:09:45 PM PDT 24
Peak memory 205308 kb
Host smart-b924724a-7f8c-4bc8-8791-41df0cfbe5d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55906
095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.55906095
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2130540977
Short name T1123
Test name
Test status
Simulation time 8375191343 ps
CPU time 11.82 seconds
Started May 21 01:09:38 PM PDT 24
Finished May 21 01:09:52 PM PDT 24
Peak memory 205292 kb
Host smart-178c4b7a-8df9-48b8-9394-9998e1154523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21305
40977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2130540977
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1045725623
Short name T137
Test name
Test status
Simulation time 8476970757 ps
CPU time 11.23 seconds
Started May 21 01:09:34 PM PDT 24
Finished May 21 01:09:46 PM PDT 24
Peak memory 205372 kb
Host smart-74165399-809a-42ba-bec8-cdb46e9506aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10457
25623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1045725623
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.15993091
Short name T358
Test name
Test status
Simulation time 8430354286 ps
CPU time 11.64 seconds
Started May 21 01:09:38 PM PDT 24
Finished May 21 01:09:52 PM PDT 24
Peak memory 205352 kb
Host smart-c28a2e13-caa9-4f2b-991b-b1c1a2554dbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15993
091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.15993091
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1029993483
Short name T1714
Test name
Test status
Simulation time 8424252217 ps
CPU time 10.67 seconds
Started May 21 01:09:38 PM PDT 24
Finished May 21 01:09:50 PM PDT 24
Peak memory 205348 kb
Host smart-317c14e8-fa9c-43a6-9fee-ae5574b91116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10299
93483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1029993483
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.549084594
Short name T579
Test name
Test status
Simulation time 8410863241 ps
CPU time 12.74 seconds
Started May 21 01:09:33 PM PDT 24
Finished May 21 01:09:47 PM PDT 24
Peak memory 205328 kb
Host smart-7ad27120-a03a-4c25-bd3a-9ddc53e3d1dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54908
4594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.549084594
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.2008249536
Short name T1583
Test name
Test status
Simulation time 8382754535 ps
CPU time 13.85 seconds
Started May 21 01:09:38 PM PDT 24
Finished May 21 01:09:55 PM PDT 24
Peak memory 205340 kb
Host smart-3e0e2387-a241-4aea-99af-a87d13b2a478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20082
49536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.2008249536
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_eop_single_bit_handling.1914598537
Short name T294
Test name
Test status
Simulation time 8414655833 ps
CPU time 13.89 seconds
Started May 21 01:09:38 PM PDT 24
Finished May 21 01:09:55 PM PDT 24
Peak memory 205396 kb
Host smart-3ff9259a-09aa-4d15-9285-601df9df73da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19145
98537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_eop_single_bit_handling.1914598537
Directory /workspace/27.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.2295802005
Short name T1407
Test name
Test status
Simulation time 8374819923 ps
CPU time 11.6 seconds
Started May 21 01:09:39 PM PDT 24
Finished May 21 01:09:54 PM PDT 24
Peak memory 205296 kb
Host smart-90c38a77-46de-44c3-8c18-8b5cd2a842ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22958
02005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.2295802005
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.960666269
Short name T842
Test name
Test status
Simulation time 8367814047 ps
CPU time 11.73 seconds
Started May 21 01:09:39 PM PDT 24
Finished May 21 01:09:53 PM PDT 24
Peak memory 205308 kb
Host smart-a2014762-77d1-4a5d-9f53-973072cd54aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96066
6269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.960666269
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.296304009
Short name T113
Test name
Test status
Simulation time 29152891045 ps
CPU time 60.25 seconds
Started May 21 01:09:38 PM PDT 24
Finished May 21 01:10:41 PM PDT 24
Peak memory 205408 kb
Host smart-e3706771-e6ce-4b3f-917b-966932d1655b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29630
4009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.296304009
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.794006811
Short name T1551
Test name
Test status
Simulation time 8415599659 ps
CPU time 12.12 seconds
Started May 21 01:09:41 PM PDT 24
Finished May 21 01:09:55 PM PDT 24
Peak memory 205344 kb
Host smart-29e046b1-7b24-4db9-bad7-ff9e769de467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79400
6811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.794006811
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.2891540823
Short name T1144
Test name
Test status
Simulation time 8423939492 ps
CPU time 12.04 seconds
Started May 21 01:09:38 PM PDT 24
Finished May 21 01:09:53 PM PDT 24
Peak memory 205568 kb
Host smart-8f320a6c-84fe-444f-8506-32d8ea25e69b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28915
40823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2891540823
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.1821385380
Short name T1221
Test name
Test status
Simulation time 8414098515 ps
CPU time 14.52 seconds
Started May 21 01:09:38 PM PDT 24
Finished May 21 01:09:55 PM PDT 24
Peak memory 205376 kb
Host smart-98bf70aa-03b6-41a9-9aab-82b9fcea6d93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18213
85380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.1821385380
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.405285069
Short name T366
Test name
Test status
Simulation time 8370334164 ps
CPU time 12.15 seconds
Started May 21 01:09:41 PM PDT 24
Finished May 21 01:09:55 PM PDT 24
Peak memory 205372 kb
Host smart-b9f2962b-8914-4798-ac3a-284e43a86d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40528
5069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.405285069
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.1541419870
Short name T175
Test name
Test status
Simulation time 8390824069 ps
CPU time 13.48 seconds
Started May 21 01:09:40 PM PDT 24
Finished May 21 01:09:56 PM PDT 24
Peak memory 205316 kb
Host smart-de5b7af3-3e49-4def-b030-a0210bfea79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15414
19870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1541419870
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1728839025
Short name T1620
Test name
Test status
Simulation time 8407874608 ps
CPU time 13.39 seconds
Started May 21 01:09:39 PM PDT 24
Finished May 21 01:09:56 PM PDT 24
Peak memory 205380 kb
Host smart-7afcd28d-ee52-4845-adf4-3366fa8c9b02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17288
39025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1728839025
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3499653506
Short name T827
Test name
Test status
Simulation time 8427114005 ps
CPU time 11.67 seconds
Started May 21 01:09:40 PM PDT 24
Finished May 21 01:09:54 PM PDT 24
Peak memory 205420 kb
Host smart-8ac16569-fd67-4f8e-aac8-23ae2d51b0c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34996
53506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3499653506
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.3408630668
Short name T867
Test name
Test status
Simulation time 8393279713 ps
CPU time 12.14 seconds
Started May 21 01:09:39 PM PDT 24
Finished May 21 01:09:54 PM PDT 24
Peak memory 205376 kb
Host smart-b84fd364-fd16-4a2d-b670-6bff446178f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34086
30668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.3408630668
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.3287020731
Short name T1616
Test name
Test status
Simulation time 8462132456 ps
CPU time 13.18 seconds
Started May 21 01:09:52 PM PDT 24
Finished May 21 01:10:07 PM PDT 24
Peak memory 205420 kb
Host smart-1e89cde3-638e-470e-88ab-98fa1629edc6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3287020731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.3287020731
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.2509987401
Short name T657
Test name
Test status
Simulation time 8374375948 ps
CPU time 10.77 seconds
Started May 21 01:09:57 PM PDT 24
Finished May 21 01:10:09 PM PDT 24
Peak memory 205352 kb
Host smart-df50bb44-323e-40ba-a8b8-c0aaf7d6155a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2509987401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.2509987401
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.931657763
Short name T314
Test name
Test status
Simulation time 8450828043 ps
CPU time 14.78 seconds
Started May 21 01:09:53 PM PDT 24
Finished May 21 01:10:11 PM PDT 24
Peak memory 205284 kb
Host smart-8745e5cb-31c5-4d74-95ed-052b939b0802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93165
7763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.931657763
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3351104073
Short name T1520
Test name
Test status
Simulation time 8379922792 ps
CPU time 11.95 seconds
Started May 21 01:09:39 PM PDT 24
Finished May 21 01:09:54 PM PDT 24
Peak memory 205380 kb
Host smart-a9820b3d-4b4e-49cb-ae22-84eeffb8594c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33511
04073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3351104073
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.2444303795
Short name T1494
Test name
Test status
Simulation time 9646523569 ps
CPU time 13.37 seconds
Started May 21 01:09:41 PM PDT 24
Finished May 21 01:09:56 PM PDT 24
Peak memory 205316 kb
Host smart-eae69e9e-aa50-4417-a4d1-99f252fc1f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24443
03795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.2444303795
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.206889353
Short name T548
Test name
Test status
Simulation time 8367981002 ps
CPU time 12.01 seconds
Started May 21 01:09:47 PM PDT 24
Finished May 21 01:10:00 PM PDT 24
Peak memory 205320 kb
Host smart-41133baf-0997-41b9-857c-eeace00fa59c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20688
9353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.206889353
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.7875174
Short name T324
Test name
Test status
Simulation time 8378314545 ps
CPU time 14.3 seconds
Started May 21 01:09:41 PM PDT 24
Finished May 21 01:09:57 PM PDT 24
Peak memory 205352 kb
Host smart-6c572daf-32db-4474-afe8-00168a172d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78751
74 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.7875174
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.1331331678
Short name T354
Test name
Test status
Simulation time 9237684062 ps
CPU time 14.25 seconds
Started May 21 01:09:40 PM PDT 24
Finished May 21 01:09:57 PM PDT 24
Peak memory 205336 kb
Host smart-3dce4ad3-1e4d-420a-82ce-b26f6bc39c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13313
31678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.1331331678
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.1255244112
Short name T1549
Test name
Test status
Simulation time 8499061805 ps
CPU time 12.47 seconds
Started May 21 01:09:52 PM PDT 24
Finished May 21 01:10:07 PM PDT 24
Peak memory 205308 kb
Host smart-711b01cc-1ac2-4dc9-8f35-798b49c01f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12552
44112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.1255244112
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.78821746
Short name T1036
Test name
Test status
Simulation time 8444888963 ps
CPU time 13.39 seconds
Started May 21 01:09:54 PM PDT 24
Finished May 21 01:10:11 PM PDT 24
Peak memory 205340 kb
Host smart-6c278437-e755-492e-9063-3622480db2f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78821
746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.78821746
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.2458249154
Short name T1340
Test name
Test status
Simulation time 8367877759 ps
CPU time 13.67 seconds
Started May 21 01:09:48 PM PDT 24
Finished May 21 01:10:02 PM PDT 24
Peak memory 205372 kb
Host smart-8d20fc40-e522-484c-8293-e8865906937c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24582
49154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.2458249154
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.1757789153
Short name T1632
Test name
Test status
Simulation time 8385908900 ps
CPU time 11.32 seconds
Started May 21 01:10:00 PM PDT 24
Finished May 21 01:10:14 PM PDT 24
Peak memory 205380 kb
Host smart-e8f278c9-afe0-48d8-918f-aa297502148c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17577
89153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.1757789153
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.3133099923
Short name T937
Test name
Test status
Simulation time 8384578052 ps
CPU time 11.9 seconds
Started May 21 01:09:45 PM PDT 24
Finished May 21 01:09:57 PM PDT 24
Peak memory 205364 kb
Host smart-ea2901c5-be7f-4dc6-9ac0-8f860c0fca4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31330
99923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.3133099923
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.1386028771
Short name T1091
Test name
Test status
Simulation time 11545913237 ps
CPU time 14.01 seconds
Started May 21 01:09:59 PM PDT 24
Finished May 21 01:10:15 PM PDT 24
Peak memory 205428 kb
Host smart-42cdf6be-ec43-466b-89b4-ab69321a3ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13860
28771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.1386028771
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3435985732
Short name T687
Test name
Test status
Simulation time 8421104490 ps
CPU time 12.86 seconds
Started May 21 01:09:46 PM PDT 24
Finished May 21 01:10:01 PM PDT 24
Peak memory 205256 kb
Host smart-b8aaaccb-22d7-4f22-b8e2-09f87e327ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34359
85732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3435985732
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1736809154
Short name T1244
Test name
Test status
Simulation time 8378208925 ps
CPU time 12.46 seconds
Started May 21 01:09:45 PM PDT 24
Finished May 21 01:09:59 PM PDT 24
Peak memory 205356 kb
Host smart-2e33c326-54fe-455c-aadc-a59a70c076bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17368
09154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1736809154
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.1033141660
Short name T1560
Test name
Test status
Simulation time 8466353792 ps
CPU time 12.32 seconds
Started May 21 01:09:45 PM PDT 24
Finished May 21 01:09:59 PM PDT 24
Peak memory 205260 kb
Host smart-3ad62ea5-2c55-4146-97cf-3e9ca29a4153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10331
41660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.1033141660
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.121442906
Short name T1071
Test name
Test status
Simulation time 8415861244 ps
CPU time 12.62 seconds
Started May 21 01:09:59 PM PDT 24
Finished May 21 01:10:14 PM PDT 24
Peak memory 205312 kb
Host smart-8d4733c1-49e5-462b-bd57-672e495ea9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12144
2906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.121442906
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.719389189
Short name T567
Test name
Test status
Simulation time 8372761391 ps
CPU time 12.2 seconds
Started May 21 01:09:46 PM PDT 24
Finished May 21 01:10:00 PM PDT 24
Peak memory 205384 kb
Host smart-278c41d0-c01f-4f4f-90b8-270d8763f09a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71938
9189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.719389189
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.1725535044
Short name T581
Test name
Test status
Simulation time 8406068489 ps
CPU time 11.48 seconds
Started May 21 01:09:46 PM PDT 24
Finished May 21 01:09:59 PM PDT 24
Peak memory 205444 kb
Host smart-d7689a8d-cf9f-4f6f-9b2b-baefc84181e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17255
35044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.1725535044
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1772969872
Short name T199
Test name
Test status
Simulation time 8403554777 ps
CPU time 13 seconds
Started May 21 01:09:47 PM PDT 24
Finished May 21 01:10:01 PM PDT 24
Peak memory 205332 kb
Host smart-80d9d733-bd52-452c-9912-fd487efb277c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17729
69872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1772969872
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_eop_single_bit_handling.3790245962
Short name T458
Test name
Test status
Simulation time 8386357166 ps
CPU time 12.5 seconds
Started May 21 01:09:59 PM PDT 24
Finished May 21 01:10:14 PM PDT 24
Peak memory 205448 kb
Host smart-5be41fcb-4e6c-450b-b455-933202689183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37902
45962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_eop_single_bit_handling.3790245962
Directory /workspace/28.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.2136873313
Short name T70
Test name
Test status
Simulation time 8378512560 ps
CPU time 11.15 seconds
Started May 21 01:09:59 PM PDT 24
Finished May 21 01:10:13 PM PDT 24
Peak memory 205316 kb
Host smart-42f3f82b-17ab-4d78-bb79-dadd434a5d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21368
73313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.2136873313
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2751487266
Short name T1367
Test name
Test status
Simulation time 8367512446 ps
CPU time 12.13 seconds
Started May 21 01:09:47 PM PDT 24
Finished May 21 01:10:00 PM PDT 24
Peak memory 205340 kb
Host smart-4dc8ec63-1e44-44d4-93f4-b8a7cb554e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27514
87266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2751487266
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.1602575715
Short name T203
Test name
Test status
Simulation time 20740393408 ps
CPU time 40.95 seconds
Started May 21 01:10:00 PM PDT 24
Finished May 21 01:10:43 PM PDT 24
Peak memory 205428 kb
Host smart-f07a5caf-c263-4b85-a8f8-ddc9f353d69f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16025
75715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.1602575715
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2360866239
Short name T1623
Test name
Test status
Simulation time 8479487693 ps
CPU time 11.46 seconds
Started May 21 01:10:00 PM PDT 24
Finished May 21 01:10:14 PM PDT 24
Peak memory 205376 kb
Host smart-93d6deb0-e6dc-45d2-820f-02f409830336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23608
66239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2360866239
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2755146297
Short name T1013
Test name
Test status
Simulation time 8504228687 ps
CPU time 11.3 seconds
Started May 21 01:09:46 PM PDT 24
Finished May 21 01:09:58 PM PDT 24
Peak memory 205416 kb
Host smart-cde78f54-142e-4128-a76f-7a611cd12f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27551
46297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2755146297
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.3261153360
Short name T1460
Test name
Test status
Simulation time 8422892890 ps
CPU time 11.28 seconds
Started May 21 01:09:46 PM PDT 24
Finished May 21 01:09:59 PM PDT 24
Peak memory 205336 kb
Host smart-84026848-50b0-4bdb-8ef8-be78d6037761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32611
53360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.3261153360
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.1188712962
Short name T871
Test name
Test status
Simulation time 8371621475 ps
CPU time 11.89 seconds
Started May 21 01:09:47 PM PDT 24
Finished May 21 01:10:00 PM PDT 24
Peak memory 205292 kb
Host smart-ad022f79-3c1c-42e9-8e9f-7cf907249736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11887
12962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.1188712962
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.743572228
Short name T1128
Test name
Test status
Simulation time 8392732310 ps
CPU time 11.02 seconds
Started May 21 01:09:45 PM PDT 24
Finished May 21 01:09:58 PM PDT 24
Peak memory 205288 kb
Host smart-5a6c059b-238a-445b-ac7a-c40d37fde8c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74357
2228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.743572228
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1131164480
Short name T895
Test name
Test status
Simulation time 8382196439 ps
CPU time 11.13 seconds
Started May 21 01:09:46 PM PDT 24
Finished May 21 01:09:58 PM PDT 24
Peak memory 205436 kb
Host smart-c9b71575-ff38-4453-a704-bcbb13a2d453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11311
64480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1131164480
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3123099491
Short name T689
Test name
Test status
Simulation time 8414884149 ps
CPU time 13.58 seconds
Started May 21 01:09:39 PM PDT 24
Finished May 21 01:09:56 PM PDT 24
Peak memory 205240 kb
Host smart-58d7a911-9144-4aad-9e1d-81a3f0dd47e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31230
99491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3123099491
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.560366754
Short name T608
Test name
Test status
Simulation time 8390726269 ps
CPU time 12.02 seconds
Started May 21 01:09:59 PM PDT 24
Finished May 21 01:10:14 PM PDT 24
Peak memory 205376 kb
Host smart-24a1a0ab-dda3-4d88-a05e-dc007297f3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56036
6754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.560366754
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.3212266268
Short name T1311
Test name
Test status
Simulation time 8466043287 ps
CPU time 11.66 seconds
Started May 21 01:10:02 PM PDT 24
Finished May 21 01:10:15 PM PDT 24
Peak memory 205304 kb
Host smart-6d3a4f03-04aa-49fd-bb81-5f87a877006f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3212266268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.3212266268
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.3416860161
Short name T323
Test name
Test status
Simulation time 8385161533 ps
CPU time 11.07 seconds
Started May 21 01:10:00 PM PDT 24
Finished May 21 01:10:14 PM PDT 24
Peak memory 205304 kb
Host smart-16a75f25-5201-4ce4-9fb3-7a96fcefe6e1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3416860161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.3416860161
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.1200633970
Short name T1291
Test name
Test status
Simulation time 8395451356 ps
CPU time 12.1 seconds
Started May 21 01:09:58 PM PDT 24
Finished May 21 01:10:11 PM PDT 24
Peak memory 205356 kb
Host smart-abc6cf27-a936-47bc-8237-ab61dd4d4110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12006
33970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.1200633970
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1954218760
Short name T1700
Test name
Test status
Simulation time 8409686344 ps
CPU time 11.64 seconds
Started May 21 01:09:55 PM PDT 24
Finished May 21 01:10:09 PM PDT 24
Peak memory 205408 kb
Host smart-2099f757-cdde-4c99-a328-23db754524d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19542
18760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1954218760
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.2462200888
Short name T993
Test name
Test status
Simulation time 8402470715 ps
CPU time 12.49 seconds
Started May 21 01:09:53 PM PDT 24
Finished May 21 01:10:07 PM PDT 24
Peak memory 205312 kb
Host smart-8df2eb53-eb65-46e4-a4af-83c13e2175e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24622
00888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.2462200888
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.3992006191
Short name T757
Test name
Test status
Simulation time 9372568135 ps
CPU time 15.21 seconds
Started May 21 01:09:59 PM PDT 24
Finished May 21 01:10:16 PM PDT 24
Peak memory 205332 kb
Host smart-b9a5480a-0d17-44aa-b483-1828343108f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39920
06191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.3992006191
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.1996884674
Short name T609
Test name
Test status
Simulation time 8369220005 ps
CPU time 12.02 seconds
Started May 21 01:09:53 PM PDT 24
Finished May 21 01:10:08 PM PDT 24
Peak memory 205344 kb
Host smart-c07db4c0-3777-4bd4-afb3-10221ad9c62e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19968
84674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.1996884674
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.3180297156
Short name T773
Test name
Test status
Simulation time 8375561608 ps
CPU time 13.63 seconds
Started May 21 01:09:54 PM PDT 24
Finished May 21 01:10:11 PM PDT 24
Peak memory 205372 kb
Host smart-8c746392-7e7b-4580-afc9-2c939a1d3cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31802
97156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3180297156
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.3679400686
Short name T444
Test name
Test status
Simulation time 9129371554 ps
CPU time 12.66 seconds
Started May 21 01:09:54 PM PDT 24
Finished May 21 01:10:09 PM PDT 24
Peak memory 205364 kb
Host smart-cb660ef3-28a8-4d40-9f6d-43e38050f0c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36794
00686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3679400686
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2349687163
Short name T669
Test name
Test status
Simulation time 8435149573 ps
CPU time 12.83 seconds
Started May 21 01:09:53 PM PDT 24
Finished May 21 01:10:09 PM PDT 24
Peak memory 205324 kb
Host smart-3766dd06-f7b4-44c2-be16-acc798661fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23496
87163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2349687163
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.3132084323
Short name T1653
Test name
Test status
Simulation time 8463362977 ps
CPU time 11.36 seconds
Started May 21 01:10:00 PM PDT 24
Finished May 21 01:10:13 PM PDT 24
Peak memory 205356 kb
Host smart-debaf5e6-0520-4c00-9485-25a004e6ae6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31320
84323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.3132084323
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.807307128
Short name T596
Test name
Test status
Simulation time 8371005749 ps
CPU time 13.49 seconds
Started May 21 01:09:59 PM PDT 24
Finished May 21 01:10:15 PM PDT 24
Peak memory 205276 kb
Host smart-045a1a54-d1f3-4ea0-8ac5-6a399568cef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80730
7128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.807307128
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3788400185
Short name T1725
Test name
Test status
Simulation time 8441189892 ps
CPU time 11.98 seconds
Started May 21 01:09:56 PM PDT 24
Finished May 21 01:10:10 PM PDT 24
Peak memory 205608 kb
Host smart-544da0e8-38de-45b8-8543-deea643f7eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37884
00185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3788400185
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.1390800676
Short name T1287
Test name
Test status
Simulation time 11548551084 ps
CPU time 14.49 seconds
Started May 21 01:09:55 PM PDT 24
Finished May 21 01:10:12 PM PDT 24
Peak memory 205292 kb
Host smart-19e84cf8-97f7-4180-9b0a-df3112f213a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13908
00676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.1390800676
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3864040091
Short name T1615
Test name
Test status
Simulation time 8420043340 ps
CPU time 13.41 seconds
Started May 21 01:09:54 PM PDT 24
Finished May 21 01:10:10 PM PDT 24
Peak memory 205272 kb
Host smart-7ad4ef9e-fbad-4681-95b2-0c1d53e25423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38640
40091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3864040091
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.1035284950
Short name T341
Test name
Test status
Simulation time 8387809393 ps
CPU time 13.29 seconds
Started May 21 01:09:55 PM PDT 24
Finished May 21 01:10:11 PM PDT 24
Peak memory 205304 kb
Host smart-800e885e-05b8-40fb-9b5c-49b240fdf9c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10352
84950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.1035284950
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.4290022581
Short name T735
Test name
Test status
Simulation time 8459379847 ps
CPU time 11.44 seconds
Started May 21 01:09:53 PM PDT 24
Finished May 21 01:10:07 PM PDT 24
Peak memory 205332 kb
Host smart-22193530-1856-49ab-ac4c-c4c741a22a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42900
22581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.4290022581
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.923843622
Short name T896
Test name
Test status
Simulation time 8422225091 ps
CPU time 12.77 seconds
Started May 21 01:09:53 PM PDT 24
Finished May 21 01:10:07 PM PDT 24
Peak memory 205408 kb
Host smart-43002583-5b5b-4eab-aa65-4d6736a30fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92384
3622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.923843622
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.1436597159
Short name T392
Test name
Test status
Simulation time 8393944362 ps
CPU time 13.68 seconds
Started May 21 01:09:54 PM PDT 24
Finished May 21 01:10:10 PM PDT 24
Peak memory 205356 kb
Host smart-3c7714b4-d77a-4b6b-aca3-b128b41154e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14365
97159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.1436597159
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_eop_single_bit_handling.1584453994
Short name T954
Test name
Test status
Simulation time 8434121353 ps
CPU time 12.29 seconds
Started May 21 01:10:00 PM PDT 24
Finished May 21 01:10:14 PM PDT 24
Peak memory 205392 kb
Host smart-14d2f29f-1df3-40da-bd2a-be4f31b8169e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15844
53994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_eop_single_bit_handling.1584453994
Directory /workspace/29.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.615525174
Short name T1675
Test name
Test status
Simulation time 8372418224 ps
CPU time 12.6 seconds
Started May 21 01:10:01 PM PDT 24
Finished May 21 01:10:15 PM PDT 24
Peak memory 205360 kb
Host smart-a9e340af-5e52-4682-860b-dd7ae7b1d742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61552
5174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.615525174
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.1941957695
Short name T1112
Test name
Test status
Simulation time 8378723212 ps
CPU time 11.31 seconds
Started May 21 01:09:58 PM PDT 24
Finished May 21 01:10:10 PM PDT 24
Peak memory 205220 kb
Host smart-f07f34e0-a1f0-4391-84cb-cb91dd559144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19419
57695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.1941957695
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.1275382206
Short name T1410
Test name
Test status
Simulation time 26457002885 ps
CPU time 50.1 seconds
Started May 21 01:09:55 PM PDT 24
Finished May 21 01:10:48 PM PDT 24
Peak memory 205404 kb
Host smart-fa55fec2-56df-4c75-ae2c-87b38e4f30ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12753
82206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.1275382206
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.4064826506
Short name T741
Test name
Test status
Simulation time 8397073674 ps
CPU time 11.66 seconds
Started May 21 01:09:55 PM PDT 24
Finished May 21 01:10:09 PM PDT 24
Peak memory 205336 kb
Host smart-1a3ea1a8-2b2e-4cf2-a119-f785205cbebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40648
26506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.4064826506
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.975135635
Short name T506
Test name
Test status
Simulation time 8450742172 ps
CPU time 12.87 seconds
Started May 21 01:09:54 PM PDT 24
Finished May 21 01:10:10 PM PDT 24
Peak memory 205352 kb
Host smart-ffb68fa2-b927-441c-b03e-017591a3a329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97513
5635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.975135635
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.3118904424
Short name T1304
Test name
Test status
Simulation time 8378495651 ps
CPU time 12.68 seconds
Started May 21 01:10:01 PM PDT 24
Finished May 21 01:10:16 PM PDT 24
Peak memory 205308 kb
Host smart-322bede3-0a5e-41d0-895d-3189808f61e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31189
04424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.3118904424
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.1550784639
Short name T1509
Test name
Test status
Simulation time 8374837745 ps
CPU time 11.73 seconds
Started May 21 01:10:05 PM PDT 24
Finished May 21 01:10:17 PM PDT 24
Peak memory 205292 kb
Host smart-1c500209-3a03-43be-9bc3-88959e050524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15507
84639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.1550784639
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.3728820505
Short name T516
Test name
Test status
Simulation time 8380806377 ps
CPU time 12.37 seconds
Started May 21 01:10:01 PM PDT 24
Finished May 21 01:10:15 PM PDT 24
Peak memory 205344 kb
Host smart-c7eaafca-65c5-40c5-b047-8eb5d2d005b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37288
20505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.3728820505
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2296205452
Short name T1384
Test name
Test status
Simulation time 8372364267 ps
CPU time 11.65 seconds
Started May 21 01:10:00 PM PDT 24
Finished May 21 01:10:14 PM PDT 24
Peak memory 205404 kb
Host smart-e64f52ff-2281-4a11-8dfa-94e27a66cc5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22962
05452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2296205452
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.4256052392
Short name T435
Test name
Test status
Simulation time 8444791801 ps
CPU time 14.04 seconds
Started May 21 01:09:55 PM PDT 24
Finished May 21 01:10:11 PM PDT 24
Peak memory 205264 kb
Host smart-d5974ed0-faa5-408f-ba23-4530154df48b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42560
52392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.4256052392
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.978109288
Short name T319
Test name
Test status
Simulation time 8406725230 ps
CPU time 14.01 seconds
Started May 21 01:10:00 PM PDT 24
Finished May 21 01:10:16 PM PDT 24
Peak memory 205408 kb
Host smart-cbd9f2e9-9520-419f-b643-e9d555a1d298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97810
9288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.978109288
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.459828239
Short name T391
Test name
Test status
Simulation time 8392298976 ps
CPU time 12.36 seconds
Started May 21 01:10:00 PM PDT 24
Finished May 21 01:10:15 PM PDT 24
Peak memory 205252 kb
Host smart-a1b878e8-bf86-4678-926c-b9bd19559394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45982
8239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.459828239
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.3093727620
Short name T442
Test name
Test status
Simulation time 8464233365 ps
CPU time 13.16 seconds
Started May 21 01:05:23 PM PDT 24
Finished May 21 01:05:37 PM PDT 24
Peak memory 205372 kb
Host smart-0d1e0df7-d685-4a06-8269-848704a155a3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3093727620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.3093727620
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.1045071207
Short name T991
Test name
Test status
Simulation time 8392527944 ps
CPU time 13.49 seconds
Started May 21 01:05:18 PM PDT 24
Finished May 21 01:05:32 PM PDT 24
Peak memory 205316 kb
Host smart-8b902b1e-18e9-444c-afac-74ffff248ef1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1045071207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.1045071207
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.3900112560
Short name T1454
Test name
Test status
Simulation time 8399944932 ps
CPU time 12.47 seconds
Started May 21 01:05:16 PM PDT 24
Finished May 21 01:05:30 PM PDT 24
Peak memory 205400 kb
Host smart-dc165d1c-358f-4980-bee9-6523960baa6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39001
12560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.3900112560
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.3299860178
Short name T1263
Test name
Test status
Simulation time 8375887877 ps
CPU time 12.24 seconds
Started May 21 01:05:13 PM PDT 24
Finished May 21 01:05:27 PM PDT 24
Peak memory 205384 kb
Host smart-3bbee444-ed6a-4c75-bf5c-fa4322eb746a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32998
60178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.3299860178
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.209807866
Short name T388
Test name
Test status
Simulation time 8706546937 ps
CPU time 13.36 seconds
Started May 21 01:05:12 PM PDT 24
Finished May 21 01:05:27 PM PDT 24
Peak memory 205372 kb
Host smart-3ff7a917-37f8-4366-955c-0a9f544f6a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20980
7866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.209807866
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_enable.142965113
Short name T930
Test name
Test status
Simulation time 8380372378 ps
CPU time 12.05 seconds
Started May 21 01:05:15 PM PDT 24
Finished May 21 01:05:28 PM PDT 24
Peak memory 205380 kb
Host smart-b03e59a0-c13b-4dad-8810-31530d7e35dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14296
5113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.142965113
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.3413121632
Short name T1320
Test name
Test status
Simulation time 9006262069 ps
CPU time 12.37 seconds
Started May 21 01:05:10 PM PDT 24
Finished May 21 01:05:24 PM PDT 24
Peak memory 205364 kb
Host smart-0709e15b-42a0-4b3e-a925-37f63bfc2c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34131
21632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.3413121632
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3959894446
Short name T672
Test name
Test status
Simulation time 8463864036 ps
CPU time 13.97 seconds
Started May 21 01:05:10 PM PDT 24
Finished May 21 01:05:26 PM PDT 24
Peak memory 205336 kb
Host smart-5921d76f-e285-4a0d-a916-d125ba4d5dab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39598
94446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3959894446
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.102667594
Short name T55
Test name
Test status
Simulation time 8432818851 ps
CPU time 11.54 seconds
Started May 21 01:05:17 PM PDT 24
Finished May 21 01:05:30 PM PDT 24
Peak memory 205256 kb
Host smart-e812ba3f-cdb1-4916-99b8-b9d1e6a4b7d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10266
7594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.102667594
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.3404111019
Short name T1035
Test name
Test status
Simulation time 8377721609 ps
CPU time 12.32 seconds
Started May 21 01:05:16 PM PDT 24
Finished May 21 01:05:30 PM PDT 24
Peak memory 205348 kb
Host smart-b6cc6537-4c3a-4d03-b9cf-2e141061e77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34041
11019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3404111019
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1537048570
Short name T1229
Test name
Test status
Simulation time 8411624151 ps
CPU time 11.39 seconds
Started May 21 01:05:14 PM PDT 24
Finished May 21 01:05:27 PM PDT 24
Peak memory 205420 kb
Host smart-f25fdc2e-c909-45eb-8dbd-84eac4326559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15370
48570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1537048570
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.727570137
Short name T796
Test name
Test status
Simulation time 11501822018 ps
CPU time 17.75 seconds
Started May 21 01:05:12 PM PDT 24
Finished May 21 01:05:32 PM PDT 24
Peak memory 205280 kb
Host smart-5d004e95-eead-482f-b710-cb08c0588183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72757
0137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.727570137
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.819998493
Short name T964
Test name
Test status
Simulation time 8416774280 ps
CPU time 12.17 seconds
Started May 21 01:05:10 PM PDT 24
Finished May 21 01:05:24 PM PDT 24
Peak memory 205416 kb
Host smart-c48861d1-b986-4511-a999-e268509844b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81999
8493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.819998493
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2746490123
Short name T351
Test name
Test status
Simulation time 8391463438 ps
CPU time 12.69 seconds
Started May 21 01:05:09 PM PDT 24
Finished May 21 01:05:22 PM PDT 24
Peak memory 205304 kb
Host smart-968ddf35-5f37-435d-bb46-6233945185f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27464
90123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2746490123
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.2507760445
Short name T142
Test name
Test status
Simulation time 8458994916 ps
CPU time 13.37 seconds
Started May 21 01:05:10 PM PDT 24
Finished May 21 01:05:26 PM PDT 24
Peak memory 205392 kb
Host smart-17ae2ee7-6e48-489d-a877-3ea85d10b4c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25077
60445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2507760445
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.523821255
Short name T632
Test name
Test status
Simulation time 8419434717 ps
CPU time 13.71 seconds
Started May 21 01:05:14 PM PDT 24
Finished May 21 01:05:29 PM PDT 24
Peak memory 205344 kb
Host smart-6545b59b-b11d-4359-b745-7fb6e2569910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52382
1255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.523821255
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.418452128
Short name T292
Test name
Test status
Simulation time 8398188701 ps
CPU time 12.04 seconds
Started May 21 01:05:10 PM PDT 24
Finished May 21 01:05:24 PM PDT 24
Peak memory 205384 kb
Host smart-fa9793fd-04c3-46b1-b623-bc0ee2ed3a96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41845
2128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.418452128
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.2096055089
Short name T1660
Test name
Test status
Simulation time 8439936255 ps
CPU time 12.7 seconds
Started May 21 01:05:13 PM PDT 24
Finished May 21 01:05:27 PM PDT 24
Peak memory 205408 kb
Host smart-5f27a913-4066-421c-940c-3922d93ab9e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20960
55089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.2096055089
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.1230119816
Short name T434
Test name
Test status
Simulation time 8446679728 ps
CPU time 11.58 seconds
Started May 21 01:05:17 PM PDT 24
Finished May 21 01:05:30 PM PDT 24
Peak memory 205336 kb
Host smart-9b50f406-d921-4be9-a362-d87c28937c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12301
19816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.1230119816
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_eop_single_bit_handling.1229716469
Short name T1476
Test name
Test status
Simulation time 8382493813 ps
CPU time 14.94 seconds
Started May 21 01:05:15 PM PDT 24
Finished May 21 01:05:32 PM PDT 24
Peak memory 205412 kb
Host smart-6f75bc58-d787-45e0-ae08-ac6ddd872daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12297
16469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_eop_single_bit_handling.1229716469
Directory /workspace/3.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2979277337
Short name T795
Test name
Test status
Simulation time 8370246641 ps
CPU time 12.05 seconds
Started May 21 01:05:17 PM PDT 24
Finished May 21 01:05:30 PM PDT 24
Peak memory 205292 kb
Host smart-77191b68-bf0d-4df1-9a68-c2faf0dcdf41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29792
77337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2979277337
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2580644516
Short name T362
Test name
Test status
Simulation time 8363817201 ps
CPU time 12.87 seconds
Started May 21 01:05:18 PM PDT 24
Finished May 21 01:05:31 PM PDT 24
Peak memory 205268 kb
Host smart-4228f4f9-16af-4bb6-a359-afdb64475bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25806
44516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2580644516
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.1008030749
Short name T244
Test name
Test status
Simulation time 21891830867 ps
CPU time 39.55 seconds
Started May 21 01:05:10 PM PDT 24
Finished May 21 01:05:52 PM PDT 24
Peak memory 205396 kb
Host smart-8d52f098-2ce3-4ad2-8c52-d585a5cdff85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10080
30749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.1008030749
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.2702491932
Short name T1439
Test name
Test status
Simulation time 8432275475 ps
CPU time 12.94 seconds
Started May 21 01:05:14 PM PDT 24
Finished May 21 01:05:28 PM PDT 24
Peak memory 205372 kb
Host smart-77bc992b-9e53-4579-9d36-bd5af25705ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27024
91932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.2702491932
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2077398102
Short name T1363
Test name
Test status
Simulation time 8507408680 ps
CPU time 11.03 seconds
Started May 21 01:05:14 PM PDT 24
Finished May 21 01:05:26 PM PDT 24
Peak memory 205364 kb
Host smart-95174748-b792-480f-a2d3-257437028c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20773
98102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2077398102
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.789899076
Short name T1652
Test name
Test status
Simulation time 8396676063 ps
CPU time 14.39 seconds
Started May 21 01:05:16 PM PDT 24
Finished May 21 01:05:32 PM PDT 24
Peak memory 205400 kb
Host smart-4b11c982-8666-43a9-bb61-11329c87ce52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78989
9076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.789899076
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.3742186637
Short name T507
Test name
Test status
Simulation time 8425082783 ps
CPU time 13.78 seconds
Started May 21 01:05:18 PM PDT 24
Finished May 21 01:05:33 PM PDT 24
Peak memory 205300 kb
Host smart-b2a6d44d-7b66-4efc-98e3-ee2adcc10053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37421
86637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.3742186637
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.3182121083
Short name T89
Test name
Test status
Simulation time 274334365 ps
CPU time 1.18 seconds
Started May 21 01:05:22 PM PDT 24
Finished May 21 01:05:24 PM PDT 24
Peak memory 222448 kb
Host smart-2329d140-a67e-4e01-8b37-6550e5524c02
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3182121083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3182121083
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.237558677
Short name T1505
Test name
Test status
Simulation time 8376123705 ps
CPU time 14.29 seconds
Started May 21 01:05:16 PM PDT 24
Finished May 21 01:05:31 PM PDT 24
Peak memory 205324 kb
Host smart-fc09f0a2-e174-49e3-a252-219182cc22e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23755
8677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.237558677
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.3022673502
Short name T1074
Test name
Test status
Simulation time 8418737610 ps
CPU time 11.66 seconds
Started May 21 01:05:17 PM PDT 24
Finished May 21 01:05:29 PM PDT 24
Peak memory 205424 kb
Host smart-b05aa88c-3679-480d-8a47-cde87e245afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30226
73502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.3022673502
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2764607388
Short name T904
Test name
Test status
Simulation time 8485656239 ps
CPU time 11.86 seconds
Started May 21 01:05:10 PM PDT 24
Finished May 21 01:05:23 PM PDT 24
Peak memory 205412 kb
Host smart-c52fdbd6-a6e5-4b9d-8e65-3feb76faa5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27646
07388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2764607388
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.869460329
Short name T1441
Test name
Test status
Simulation time 8455628933 ps
CPU time 12.27 seconds
Started May 21 01:05:20 PM PDT 24
Finished May 21 01:05:33 PM PDT 24
Peak memory 205352 kb
Host smart-aafc9206-8fc4-4b0b-96c0-f9e696d9739d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86946
0329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.869460329
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2204427066
Short name T345
Test name
Test status
Simulation time 8403883728 ps
CPU time 12.84 seconds
Started May 21 01:05:18 PM PDT 24
Finished May 21 01:05:32 PM PDT 24
Peak memory 205564 kb
Host smart-6b7287aa-779c-49d7-9668-730ff004825d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22044
27066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2204427066
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.2428079183
Short name T611
Test name
Test status
Simulation time 8498840273 ps
CPU time 14.32 seconds
Started May 21 01:10:09 PM PDT 24
Finished May 21 01:10:25 PM PDT 24
Peak memory 205428 kb
Host smart-cb3f8779-41da-4e82-a664-8bf3b9676d2e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2428079183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.2428079183
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.2315685294
Short name T945
Test name
Test status
Simulation time 8388144310 ps
CPU time 13.28 seconds
Started May 21 01:10:06 PM PDT 24
Finished May 21 01:10:20 PM PDT 24
Peak memory 205356 kb
Host smart-6033054c-ea2c-4111-8f74-261ac481c998
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2315685294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.2315685294
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.2118229423
Short name T1609
Test name
Test status
Simulation time 8421536266 ps
CPU time 11.21 seconds
Started May 21 01:10:10 PM PDT 24
Finished May 21 01:10:23 PM PDT 24
Peak memory 204548 kb
Host smart-d9963047-883b-4eba-8bb0-9147caf1a945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21182
29423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.2118229423
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.1981301582
Short name T1012
Test name
Test status
Simulation time 8380894432 ps
CPU time 11.53 seconds
Started May 21 01:09:58 PM PDT 24
Finished May 21 01:10:11 PM PDT 24
Peak memory 205376 kb
Host smart-fca4e209-bc3f-4052-888c-dc177254dbc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19813
01582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1981301582
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.2449730541
Short name T994
Test name
Test status
Simulation time 8371388900 ps
CPU time 11.54 seconds
Started May 21 01:10:01 PM PDT 24
Finished May 21 01:10:14 PM PDT 24
Peak memory 205364 kb
Host smart-05184714-bb1d-42c3-883d-2f9b2c3eed6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24497
30541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.2449730541
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.4180981992
Short name T662
Test name
Test status
Simulation time 8439815151 ps
CPU time 12.39 seconds
Started May 21 01:10:01 PM PDT 24
Finished May 21 01:10:15 PM PDT 24
Peak memory 205332 kb
Host smart-952c494d-445b-4287-86e2-1f251f4c97ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41809
81992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.4180981992
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.821765904
Short name T856
Test name
Test status
Simulation time 9158146454 ps
CPU time 12.15 seconds
Started May 21 01:09:59 PM PDT 24
Finished May 21 01:10:12 PM PDT 24
Peak memory 205356 kb
Host smart-849c863f-52fc-474b-8480-1fb21212a1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82176
5904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.821765904
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.2725416227
Short name T426
Test name
Test status
Simulation time 8565304612 ps
CPU time 13.61 seconds
Started May 21 01:10:01 PM PDT 24
Finished May 21 01:10:17 PM PDT 24
Peak memory 205308 kb
Host smart-b213d7d8-7054-4960-983c-2187465f77ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27254
16227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2725416227
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.2162139694
Short name T1346
Test name
Test status
Simulation time 8425967130 ps
CPU time 11.51 seconds
Started May 21 01:10:09 PM PDT 24
Finished May 21 01:10:22 PM PDT 24
Peak memory 205384 kb
Host smart-a91fa6e6-d6eb-4c84-842e-23ee1ce63b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21621
39694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.2162139694
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.3415768833
Short name T396
Test name
Test status
Simulation time 8366514813 ps
CPU time 11.44 seconds
Started May 21 01:10:07 PM PDT 24
Finished May 21 01:10:20 PM PDT 24
Peak memory 205372 kb
Host smart-0e3447e6-5418-4924-9d92-d0e0cd7809f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34157
68833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.3415768833
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.434691948
Short name T575
Test name
Test status
Simulation time 8436347792 ps
CPU time 11.97 seconds
Started May 21 01:10:02 PM PDT 24
Finished May 21 01:10:15 PM PDT 24
Peak memory 205392 kb
Host smart-8443360f-5873-477c-8252-a8e74f7f41ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43469
1948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.434691948
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.4255521437
Short name T462
Test name
Test status
Simulation time 8479860710 ps
CPU time 13.5 seconds
Started May 21 01:09:59 PM PDT 24
Finished May 21 01:10:15 PM PDT 24
Peak memory 205332 kb
Host smart-eb41998f-086e-4adc-b9c2-31a154048ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42555
21437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.4255521437
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.2145297494
Short name T1574
Test name
Test status
Simulation time 11512736837 ps
CPU time 15.01 seconds
Started May 21 01:10:01 PM PDT 24
Finished May 21 01:10:18 PM PDT 24
Peak memory 205348 kb
Host smart-a62fdb5b-a9fe-455f-8a83-f51de3fd3f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21452
97494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.2145297494
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1284687729
Short name T1568
Test name
Test status
Simulation time 8475178490 ps
CPU time 12.37 seconds
Started May 21 01:10:01 PM PDT 24
Finished May 21 01:10:15 PM PDT 24
Peak memory 205400 kb
Host smart-635071e7-e1ba-4f33-9b14-74cdd38c75cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12846
87729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1284687729
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.2909359258
Short name T1606
Test name
Test status
Simulation time 8373193759 ps
CPU time 12.64 seconds
Started May 21 01:10:02 PM PDT 24
Finished May 21 01:10:16 PM PDT 24
Peak memory 205340 kb
Host smart-622af21a-d4dc-42cf-b536-e5d5d54231cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29093
59258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.2909359258
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.702533833
Short name T150
Test name
Test status
Simulation time 8396697108 ps
CPU time 12.55 seconds
Started May 21 01:09:59 PM PDT 24
Finished May 21 01:10:14 PM PDT 24
Peak memory 205400 kb
Host smart-648d9e2c-9b90-4efb-9974-c0003396606f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70253
3833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.702533833
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3473539268
Short name T1597
Test name
Test status
Simulation time 8431725260 ps
CPU time 13.86 seconds
Started May 21 01:10:02 PM PDT 24
Finished May 21 01:10:17 PM PDT 24
Peak memory 205320 kb
Host smart-75b8c578-0e1a-4f76-b488-fae0faa370aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34735
39268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3473539268
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.198722202
Short name T1422
Test name
Test status
Simulation time 8402832395 ps
CPU time 11.64 seconds
Started May 21 01:10:09 PM PDT 24
Finished May 21 01:10:22 PM PDT 24
Peak memory 205392 kb
Host smart-98e19fb2-1303-444b-b0f7-c77207167d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19872
2202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.198722202
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.2896658683
Short name T517
Test name
Test status
Simulation time 8437348708 ps
CPU time 11.83 seconds
Started May 21 01:10:06 PM PDT 24
Finished May 21 01:10:19 PM PDT 24
Peak memory 205352 kb
Host smart-f16d37e1-2549-4e78-bdf7-9a3f215025f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28966
58683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.2896658683
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3791433815
Short name T156
Test name
Test status
Simulation time 8447235351 ps
CPU time 11.75 seconds
Started May 21 01:10:10 PM PDT 24
Finished May 21 01:10:23 PM PDT 24
Peak memory 205352 kb
Host smart-14ff2577-f165-40d9-8ff7-d912fee3036c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37914
33815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3791433815
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_eop_single_bit_handling.2032926989
Short name T599
Test name
Test status
Simulation time 8406476737 ps
CPU time 12.62 seconds
Started May 21 01:10:08 PM PDT 24
Finished May 21 01:10:22 PM PDT 24
Peak memory 205412 kb
Host smart-921a516f-a7e1-4b97-9f68-903dac44f36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20329
26989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_eop_single_bit_handling.2032926989
Directory /workspace/30.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.3631298834
Short name T71
Test name
Test status
Simulation time 8375403584 ps
CPU time 12.86 seconds
Started May 21 01:10:08 PM PDT 24
Finished May 21 01:10:23 PM PDT 24
Peak memory 205380 kb
Host smart-08226cc0-505d-4d94-84f0-9f6b7937d42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36312
98834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.3631298834
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.292825583
Short name T1503
Test name
Test status
Simulation time 8361998982 ps
CPU time 12.39 seconds
Started May 21 01:10:07 PM PDT 24
Finished May 21 01:10:21 PM PDT 24
Peak memory 205352 kb
Host smart-e860c4fb-0824-4cbb-b4e0-6f88f6ffbbda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29282
5583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.292825583
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.3334703663
Short name T225
Test name
Test status
Simulation time 22969801819 ps
CPU time 45.01 seconds
Started May 21 01:10:15 PM PDT 24
Finished May 21 01:11:01 PM PDT 24
Peak memory 205360 kb
Host smart-1189388c-fe32-4bd2-8d6f-a98446bdc45c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33347
03663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.3334703663
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.414371774
Short name T946
Test name
Test status
Simulation time 8400796843 ps
CPU time 14.32 seconds
Started May 21 01:10:09 PM PDT 24
Finished May 21 01:10:25 PM PDT 24
Peak memory 205288 kb
Host smart-85bd0ef4-3161-4cfa-a786-164d0408235b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41437
1774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.414371774
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.1328833922
Short name T885
Test name
Test status
Simulation time 8448525906 ps
CPU time 11.88 seconds
Started May 21 01:10:09 PM PDT 24
Finished May 21 01:10:22 PM PDT 24
Peak memory 205392 kb
Host smart-d31f1778-ab08-450b-8bcd-a63a7c086856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13288
33922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1328833922
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.1867896478
Short name T863
Test name
Test status
Simulation time 8391987077 ps
CPU time 11.6 seconds
Started May 21 01:10:07 PM PDT 24
Finished May 21 01:10:20 PM PDT 24
Peak memory 205240 kb
Host smart-c3bc713a-53fb-4e83-bd64-b53d6f23559d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18678
96478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.1867896478
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.1646821610
Short name T35
Test name
Test status
Simulation time 8372164938 ps
CPU time 11.36 seconds
Started May 21 01:10:05 PM PDT 24
Finished May 21 01:10:17 PM PDT 24
Peak memory 205348 kb
Host smart-f366b257-bd69-4400-a5f7-dbdb85a2acf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16468
21610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.1646821610
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.1111888763
Short name T914
Test name
Test status
Simulation time 8378199409 ps
CPU time 12.05 seconds
Started May 21 01:10:06 PM PDT 24
Finished May 21 01:10:20 PM PDT 24
Peak memory 205532 kb
Host smart-79494914-4566-4da2-bcb6-86499ec7e9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11118
88763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1111888763
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1681623190
Short name T1275
Test name
Test status
Simulation time 8380538174 ps
CPU time 12.43 seconds
Started May 21 01:10:10 PM PDT 24
Finished May 21 01:10:24 PM PDT 24
Peak memory 204508 kb
Host smart-812b332e-215b-428c-a13b-dd4b4788b624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16816
23190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1681623190
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.537076061
Short name T182
Test name
Test status
Simulation time 8422449395 ps
CPU time 11.71 seconds
Started May 21 01:10:01 PM PDT 24
Finished May 21 01:10:14 PM PDT 24
Peak memory 205348 kb
Host smart-01e4ba26-370f-417c-b93a-0f778bae07da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53707
6061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.537076061
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.1205536035
Short name T445
Test name
Test status
Simulation time 8396297129 ps
CPU time 11.91 seconds
Started May 21 01:10:06 PM PDT 24
Finished May 21 01:10:19 PM PDT 24
Peak memory 205252 kb
Host smart-e477a721-66ab-473e-95d4-84d799ae8ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12055
36035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.1205536035
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.3242967086
Short name T359
Test name
Test status
Simulation time 8383819401 ps
CPU time 12.05 seconds
Started May 21 01:10:06 PM PDT 24
Finished May 21 01:10:18 PM PDT 24
Peak memory 205324 kb
Host smart-0c6a8eac-95ff-46e3-b71b-306fd8fafea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32429
67086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.3242967086
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.3847131568
Short name T656
Test name
Test status
Simulation time 8471713129 ps
CPU time 11.5 seconds
Started May 21 01:10:20 PM PDT 24
Finished May 21 01:10:32 PM PDT 24
Peak memory 205412 kb
Host smart-6553e093-b636-4991-92e3-47d3c5d44582
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3847131568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.3847131568
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.3726042366
Short name T338
Test name
Test status
Simulation time 8387520764 ps
CPU time 11.24 seconds
Started May 21 01:10:20 PM PDT 24
Finished May 21 01:10:32 PM PDT 24
Peak memory 205364 kb
Host smart-d7e57802-29b3-4962-a00e-ba69a2b196fc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3726042366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.3726042366
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.1744516596
Short name T1026
Test name
Test status
Simulation time 8451040276 ps
CPU time 11.54 seconds
Started May 21 01:10:21 PM PDT 24
Finished May 21 01:10:33 PM PDT 24
Peak memory 205448 kb
Host smart-44920272-9e93-4926-8662-9df1a7613d95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17445
16596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.1744516596
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1842835048
Short name T618
Test name
Test status
Simulation time 8388350174 ps
CPU time 12.91 seconds
Started May 21 01:10:09 PM PDT 24
Finished May 21 01:10:23 PM PDT 24
Peak memory 205304 kb
Host smart-d70c6906-de72-4120-bbf4-5200710c05ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18428
35048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1842835048
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.4167293210
Short name T755
Test name
Test status
Simulation time 8983726712 ps
CPU time 11.55 seconds
Started May 21 01:10:16 PM PDT 24
Finished May 21 01:10:29 PM PDT 24
Peak memory 205312 kb
Host smart-6e4d7311-43a0-4340-9f19-e843875a1f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41672
93210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.4167293210
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.4140109767
Short name T1213
Test name
Test status
Simulation time 8384991229 ps
CPU time 11.8 seconds
Started May 21 01:10:13 PM PDT 24
Finished May 21 01:10:27 PM PDT 24
Peak memory 205316 kb
Host smart-78822278-8186-43f7-a4cd-4cba098d715c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41401
09767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.4140109767
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.1078132386
Short name T526
Test name
Test status
Simulation time 9077058153 ps
CPU time 12.97 seconds
Started May 21 01:10:13 PM PDT 24
Finished May 21 01:10:28 PM PDT 24
Peak memory 205432 kb
Host smart-1971aa43-eae5-43e3-97b6-578b1d30af80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10781
32386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.1078132386
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.88039546
Short name T1301
Test name
Test status
Simulation time 8523911604 ps
CPU time 13.4 seconds
Started May 21 01:10:16 PM PDT 24
Finished May 21 01:10:31 PM PDT 24
Peak memory 205216 kb
Host smart-5993b6f7-2831-41e4-964c-4f2d1b1ac1f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88039
546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.88039546
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.1158039794
Short name T1508
Test name
Test status
Simulation time 8460890469 ps
CPU time 10.83 seconds
Started May 21 01:10:18 PM PDT 24
Finished May 21 01:10:29 PM PDT 24
Peak memory 205372 kb
Host smart-d107f2d3-1f72-4b63-ad0e-4ec2c1d776a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11580
39794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.1158039794
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.3564761113
Short name T1050
Test name
Test status
Simulation time 8364365339 ps
CPU time 11.7 seconds
Started May 21 01:10:14 PM PDT 24
Finished May 21 01:10:28 PM PDT 24
Peak memory 205348 kb
Host smart-10f4cae2-f59b-467c-8ccd-bbde9e332402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35647
61113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.3564761113
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.4044569588
Short name T1467
Test name
Test status
Simulation time 8458596497 ps
CPU time 12.18 seconds
Started May 21 01:10:07 PM PDT 24
Finished May 21 01:10:20 PM PDT 24
Peak memory 205296 kb
Host smart-03ab08cc-fec5-4a89-8d46-97f792e83bb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40445
69588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.4044569588
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.2704252109
Short name T421
Test name
Test status
Simulation time 11562217437 ps
CPU time 17.14 seconds
Started May 21 01:10:16 PM PDT 24
Finished May 21 01:10:34 PM PDT 24
Peak memory 205328 kb
Host smart-36b99ab4-2302-4707-b315-1ed7a4498a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27042
52109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2704252109
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.3549665434
Short name T1147
Test name
Test status
Simulation time 8410860276 ps
CPU time 12.18 seconds
Started May 21 01:10:17 PM PDT 24
Finished May 21 01:10:30 PM PDT 24
Peak memory 205380 kb
Host smart-4e484dce-10ca-4456-80c8-4168c64a2001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35496
65434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.3549665434
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.4263695666
Short name T1455
Test name
Test status
Simulation time 8368951663 ps
CPU time 13.34 seconds
Started May 21 01:10:16 PM PDT 24
Finished May 21 01:10:30 PM PDT 24
Peak memory 205316 kb
Host smart-c740ba27-e6f1-4d0d-bfb1-e9ed3423299d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42636
95666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.4263695666
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.552037343
Short name T130
Test name
Test status
Simulation time 8425833520 ps
CPU time 11.11 seconds
Started May 21 01:10:12 PM PDT 24
Finished May 21 01:10:25 PM PDT 24
Peak memory 205392 kb
Host smart-58ba1c2a-3d0c-4668-9bd0-50a374767bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55203
7343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.552037343
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.3724761845
Short name T1392
Test name
Test status
Simulation time 8409673717 ps
CPU time 13.92 seconds
Started May 21 01:10:12 PM PDT 24
Finished May 21 01:10:27 PM PDT 24
Peak memory 205392 kb
Host smart-2294b828-8552-4135-9a81-948ddb36175e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37247
61845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.3724761845
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.708863073
Short name T1349
Test name
Test status
Simulation time 8436930345 ps
CPU time 10.67 seconds
Started May 21 01:10:14 PM PDT 24
Finished May 21 01:10:27 PM PDT 24
Peak memory 205428 kb
Host smart-3b6f56c5-f2bd-4b92-8512-79e9cfbf5985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70886
3073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.708863073
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1545600359
Short name T105
Test name
Test status
Simulation time 8410826976 ps
CPU time 14.93 seconds
Started May 21 01:10:14 PM PDT 24
Finished May 21 01:10:31 PM PDT 24
Peak memory 205336 kb
Host smart-8a6142f3-2c71-4559-822d-03bb6e746414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15456
00359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1545600359
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3404089370
Short name T191
Test name
Test status
Simulation time 8400495398 ps
CPU time 11.83 seconds
Started May 21 01:10:12 PM PDT 24
Finished May 21 01:10:26 PM PDT 24
Peak memory 205312 kb
Host smart-e6390a87-5f4a-44a6-92c4-874fd88c7d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34040
89370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3404089370
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_eop_single_bit_handling.2648367499
Short name T306
Test name
Test status
Simulation time 8385395325 ps
CPU time 12.01 seconds
Started May 21 01:10:15 PM PDT 24
Finished May 21 01:10:28 PM PDT 24
Peak memory 205364 kb
Host smart-7781e781-299f-4062-ba79-e845777132c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26483
67499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_eop_single_bit_handling.2648367499
Directory /workspace/31.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.2732542582
Short name T1571
Test name
Test status
Simulation time 8368125474 ps
CPU time 12.36 seconds
Started May 21 01:10:12 PM PDT 24
Finished May 21 01:10:26 PM PDT 24
Peak memory 205348 kb
Host smart-db173b6d-627d-415b-b631-40ccd4d0e674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27325
42582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.2732542582
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.3815615809
Short name T1298
Test name
Test status
Simulation time 8367026314 ps
CPU time 11.83 seconds
Started May 21 01:10:12 PM PDT 24
Finished May 21 01:10:25 PM PDT 24
Peak memory 205180 kb
Host smart-de6f830f-9655-4ad6-95db-a3f42747d4b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38156
15809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.3815615809
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.3041862375
Short name T614
Test name
Test status
Simulation time 8427757115 ps
CPU time 11.42 seconds
Started May 21 01:10:14 PM PDT 24
Finished May 21 01:10:27 PM PDT 24
Peak memory 205320 kb
Host smart-ae43d4dd-2c31-4bb8-ab0c-f0d3cecde3c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30418
62375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.3041862375
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2970843169
Short name T1664
Test name
Test status
Simulation time 8460892400 ps
CPU time 15.34 seconds
Started May 21 01:10:13 PM PDT 24
Finished May 21 01:10:30 PM PDT 24
Peak memory 205332 kb
Host smart-b706f675-fb8d-4fd3-8ae3-15c01312a9f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29708
43169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2970843169
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.2466473257
Short name T1265
Test name
Test status
Simulation time 8382349171 ps
CPU time 15.34 seconds
Started May 21 01:10:13 PM PDT 24
Finished May 21 01:10:30 PM PDT 24
Peak memory 205344 kb
Host smart-42a73358-747a-47b7-8e11-3a7f8454666c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24664
73257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.2466473257
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.3656238499
Short name T638
Test name
Test status
Simulation time 8391816778 ps
CPU time 13.87 seconds
Started May 21 01:10:11 PM PDT 24
Finished May 21 01:10:26 PM PDT 24
Peak memory 205344 kb
Host smart-b92d29b4-3be9-4deb-8622-2b706ef1d725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36562
38499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.3656238499
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.2853634457
Short name T1218
Test name
Test status
Simulation time 8387837950 ps
CPU time 11.32 seconds
Started May 21 01:10:15 PM PDT 24
Finished May 21 01:10:27 PM PDT 24
Peak memory 205320 kb
Host smart-6958ebb5-0d4e-458a-b98d-c5c5c4a5c9b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28536
34457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.2853634457
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.1977875482
Short name T679
Test name
Test status
Simulation time 8377881741 ps
CPU time 11.53 seconds
Started May 21 01:10:13 PM PDT 24
Finished May 21 01:10:26 PM PDT 24
Peak memory 205344 kb
Host smart-05262fb2-fe2b-4833-a881-dcf0d3259913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19778
75482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.1977875482
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3766814715
Short name T116
Test name
Test status
Simulation time 8465135374 ps
CPU time 12.47 seconds
Started May 21 01:10:07 PM PDT 24
Finished May 21 01:10:21 PM PDT 24
Peak memory 205416 kb
Host smart-fb444db6-92e8-4b29-b570-bbb9e529974c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37668
14715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3766814715
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.3676059235
Short name T1329
Test name
Test status
Simulation time 8411448089 ps
CPU time 11.45 seconds
Started May 21 01:10:12 PM PDT 24
Finished May 21 01:10:25 PM PDT 24
Peak memory 205304 kb
Host smart-3d36020a-d63e-4809-a128-fd77af4ffefc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36760
59235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.3676059235
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1252139904
Short name T744
Test name
Test status
Simulation time 8406277010 ps
CPU time 11.18 seconds
Started May 21 01:10:12 PM PDT 24
Finished May 21 01:10:24 PM PDT 24
Peak memory 205356 kb
Host smart-abce4aef-2553-4fc1-bc92-cf6de531dd4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12521
39904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1252139904
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.1854533512
Short name T1569
Test name
Test status
Simulation time 8473920089 ps
CPU time 11.31 seconds
Started May 21 01:10:32 PM PDT 24
Finished May 21 01:10:45 PM PDT 24
Peak memory 205360 kb
Host smart-5b0f9095-45a6-4f65-866f-5df5bbe7e21b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1854533512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.1854533512
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.4016020135
Short name T586
Test name
Test status
Simulation time 8381472816 ps
CPU time 11.74 seconds
Started May 21 01:10:25 PM PDT 24
Finished May 21 01:10:38 PM PDT 24
Peak memory 205324 kb
Host smart-9f704fb4-e344-43c8-81b0-4206e7e2beba
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4016020135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.4016020135
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.616801285
Short name T1723
Test name
Test status
Simulation time 8430502277 ps
CPU time 11.55 seconds
Started May 21 01:10:25 PM PDT 24
Finished May 21 01:10:39 PM PDT 24
Peak memory 205376 kb
Host smart-ffd7770a-0410-4771-9461-759ded553204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61680
1285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.616801285
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.3165430982
Short name T1585
Test name
Test status
Simulation time 8375489280 ps
CPU time 11.39 seconds
Started May 21 01:10:17 PM PDT 24
Finished May 21 01:10:30 PM PDT 24
Peak memory 205336 kb
Host smart-912e36a7-2e29-4899-afb4-9f4e649393da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31654
30982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3165430982
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.3598854758
Short name T1607
Test name
Test status
Simulation time 8375991901 ps
CPU time 11.81 seconds
Started May 21 01:10:18 PM PDT 24
Finished May 21 01:10:31 PM PDT 24
Peak memory 205376 kb
Host smart-c3fc80a0-d5b9-4f7b-b4b7-8b5aa3a82cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35988
54758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.3598854758
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1573678948
Short name T636
Test name
Test status
Simulation time 9090803736 ps
CPU time 14.57 seconds
Started May 21 01:10:21 PM PDT 24
Finished May 21 01:10:36 PM PDT 24
Peak memory 205412 kb
Host smart-3f307260-7df7-4d91-bc8d-b67138aecb1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15736
78948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1573678948
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.3089146986
Short name T1247
Test name
Test status
Simulation time 8380606964 ps
CPU time 11.46 seconds
Started May 21 01:10:23 PM PDT 24
Finished May 21 01:10:36 PM PDT 24
Peak memory 205368 kb
Host smart-1f215760-1b69-4b2c-b51c-299630600d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30891
46986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.3089146986
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.332419499
Short name T849
Test name
Test status
Simulation time 8374714112 ps
CPU time 11.93 seconds
Started May 21 01:10:20 PM PDT 24
Finished May 21 01:10:32 PM PDT 24
Peak memory 205388 kb
Host smart-e2dca4c0-0830-418e-ab2b-6bbdf55abaac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33241
9499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.332419499
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.891867338
Short name T587
Test name
Test status
Simulation time 9050633423 ps
CPU time 12.05 seconds
Started May 21 01:10:21 PM PDT 24
Finished May 21 01:10:33 PM PDT 24
Peak memory 205348 kb
Host smart-abeed96b-90bd-4ef1-99cc-47d26de0b567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89186
7338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.891867338
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1447388323
Short name T383
Test name
Test status
Simulation time 8577288455 ps
CPU time 13.36 seconds
Started May 21 01:10:18 PM PDT 24
Finished May 21 01:10:33 PM PDT 24
Peak memory 205296 kb
Host smart-54eb15d6-6d33-45d3-95f0-9e6ac6ff0802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14473
88323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1447388323
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.3661627670
Short name T580
Test name
Test status
Simulation time 8455010817 ps
CPU time 11.75 seconds
Started May 21 01:10:26 PM PDT 24
Finished May 21 01:10:40 PM PDT 24
Peak memory 205332 kb
Host smart-09e87d52-d6fc-45b4-a4de-90621d7234c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36616
27670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.3661627670
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1154191001
Short name T613
Test name
Test status
Simulation time 8373715946 ps
CPU time 12.55 seconds
Started May 21 01:10:24 PM PDT 24
Finished May 21 01:10:38 PM PDT 24
Peak memory 205296 kb
Host smart-c29f0823-091c-4316-8e79-71dc99742fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11541
91001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1154191001
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.4142769779
Short name T1238
Test name
Test status
Simulation time 8450118152 ps
CPU time 11.59 seconds
Started May 21 01:10:25 PM PDT 24
Finished May 21 01:10:39 PM PDT 24
Peak memory 205320 kb
Host smart-e8d1f20b-4c55-46e5-8379-1c4eac6da3d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41427
69779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.4142769779
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.2763935337
Short name T864
Test name
Test status
Simulation time 11495123252 ps
CPU time 15.33 seconds
Started May 21 01:10:24 PM PDT 24
Finished May 21 01:10:41 PM PDT 24
Peak memory 205356 kb
Host smart-a15d5a0b-d95f-4108-a8d7-989e1c09ba69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27639
35337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.2763935337
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.579260581
Short name T1308
Test name
Test status
Simulation time 8416901608 ps
CPU time 11.54 seconds
Started May 21 01:10:24 PM PDT 24
Finished May 21 01:10:37 PM PDT 24
Peak memory 205456 kb
Host smart-5d9c1ee4-a27f-4397-8e85-eb48be025686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57926
0581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.579260581
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.2785122743
Short name T1710
Test name
Test status
Simulation time 8391426032 ps
CPU time 11.76 seconds
Started May 21 01:10:25 PM PDT 24
Finished May 21 01:10:38 PM PDT 24
Peak memory 205276 kb
Host smart-65334046-7f7d-4456-b3ca-a4735d83a1b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27851
22743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.2785122743
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.384852787
Short name T905
Test name
Test status
Simulation time 8418855694 ps
CPU time 10.96 seconds
Started May 21 01:10:26 PM PDT 24
Finished May 21 01:10:39 PM PDT 24
Peak memory 205424 kb
Host smart-23653558-41bc-4b67-ad1e-fc130e6eef23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38485
2787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.384852787
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1216468192
Short name T1052
Test name
Test status
Simulation time 8440014599 ps
CPU time 11.91 seconds
Started May 21 01:10:23 PM PDT 24
Finished May 21 01:10:36 PM PDT 24
Peak memory 205312 kb
Host smart-b46080a2-9ba8-4020-9f9e-91309fb444ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12164
68192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1216468192
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.3827892352
Short name T1185
Test name
Test status
Simulation time 8376356093 ps
CPU time 11.58 seconds
Started May 21 01:10:25 PM PDT 24
Finished May 21 01:10:38 PM PDT 24
Peak memory 205384 kb
Host smart-836585f3-4489-4a08-97c2-a9c487e368e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38278
92352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.3827892352
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.2128670209
Short name T68
Test name
Test status
Simulation time 8401034305 ps
CPU time 13.88 seconds
Started May 21 01:10:25 PM PDT 24
Finished May 21 01:10:41 PM PDT 24
Peak memory 205276 kb
Host smart-4ca259d3-810e-422a-b863-123840291c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21286
70209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2128670209
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_eop_single_bit_handling.2682534540
Short name T714
Test name
Test status
Simulation time 8416291688 ps
CPU time 11.82 seconds
Started May 21 01:10:26 PM PDT 24
Finished May 21 01:10:40 PM PDT 24
Peak memory 205372 kb
Host smart-718df61a-f9be-4d3b-85dd-69a1423b6bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26825
34540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_eop_single_bit_handling.2682534540
Directory /workspace/32.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.1695517172
Short name T1048
Test name
Test status
Simulation time 8372116200 ps
CPU time 12.02 seconds
Started May 21 01:10:24 PM PDT 24
Finished May 21 01:10:38 PM PDT 24
Peak memory 205260 kb
Host smart-af80de92-60cb-481b-851e-73245d098a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16955
17172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.1695517172
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.387478252
Short name T1286
Test name
Test status
Simulation time 8364602286 ps
CPU time 13.11 seconds
Started May 21 01:10:26 PM PDT 24
Finished May 21 01:10:41 PM PDT 24
Peak memory 205252 kb
Host smart-0cd22a3d-a8ff-461f-9cfe-860bb7e16152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38747
8252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.387478252
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3221062637
Short name T347
Test name
Test status
Simulation time 8383067346 ps
CPU time 11.89 seconds
Started May 21 01:10:25 PM PDT 24
Finished May 21 01:10:39 PM PDT 24
Peak memory 205412 kb
Host smart-4f316017-93ca-4f26-9ff0-24e300ca2eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32210
62637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3221062637
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.1766882966
Short name T1000
Test name
Test status
Simulation time 8420182871 ps
CPU time 13.18 seconds
Started May 21 01:10:24 PM PDT 24
Finished May 21 01:10:38 PM PDT 24
Peak memory 205376 kb
Host smart-16bf15ce-4fb4-4aff-8d3d-68e0753180b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17668
82966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.1766882966
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.1264112300
Short name T487
Test name
Test status
Simulation time 8385738069 ps
CPU time 11.03 seconds
Started May 21 01:10:28 PM PDT 24
Finished May 21 01:10:40 PM PDT 24
Peak memory 205416 kb
Host smart-6d0a2ba5-c9e1-4b14-8cb7-76851af080f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12641
12300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.1264112300
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.3570774676
Short name T1087
Test name
Test status
Simulation time 8365624664 ps
CPU time 11.28 seconds
Started May 21 01:10:25 PM PDT 24
Finished May 21 01:10:37 PM PDT 24
Peak memory 205284 kb
Host smart-c50c439d-3bfa-45e7-80aa-c912c219a91f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35707
74676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.3570774676
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.1272488685
Short name T1651
Test name
Test status
Simulation time 8386196189 ps
CPU time 15.52 seconds
Started May 21 01:10:24 PM PDT 24
Finished May 21 01:10:42 PM PDT 24
Peak memory 205364 kb
Host smart-c31dd5df-c4af-4548-9c60-42b56b1c76a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12724
88685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.1272488685
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2179099985
Short name T1412
Test name
Test status
Simulation time 8420968504 ps
CPU time 11.53 seconds
Started May 21 01:10:26 PM PDT 24
Finished May 21 01:10:39 PM PDT 24
Peak memory 205300 kb
Host smart-e02ad9d4-f492-4b5d-986e-bcb3b71bcca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21790
99985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2179099985
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1473115232
Short name T1337
Test name
Test status
Simulation time 8444884761 ps
CPU time 12.42 seconds
Started May 21 01:10:19 PM PDT 24
Finished May 21 01:10:32 PM PDT 24
Peak memory 205368 kb
Host smart-704bd7dc-a0c0-46bf-b26f-446a6cdadaba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14731
15232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1473115232
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.4052035165
Short name T152
Test name
Test status
Simulation time 8404538325 ps
CPU time 14.59 seconds
Started May 21 01:10:27 PM PDT 24
Finished May 21 01:10:43 PM PDT 24
Peak memory 205396 kb
Host smart-494c882e-3597-4732-b4d1-e0ad25606b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40520
35165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.4052035165
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.812880190
Short name T1491
Test name
Test status
Simulation time 8407037399 ps
CPU time 10.99 seconds
Started May 21 01:10:27 PM PDT 24
Finished May 21 01:10:40 PM PDT 24
Peak memory 205376 kb
Host smart-90fe5176-758b-4137-8246-fd01a33bb20f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81288
0190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.812880190
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.1679925927
Short name T753
Test name
Test status
Simulation time 8469297349 ps
CPU time 11.33 seconds
Started May 21 01:10:36 PM PDT 24
Finished May 21 01:10:49 PM PDT 24
Peak memory 205296 kb
Host smart-44f33f6f-3aac-46de-b609-d4afaaac2163
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1679925927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.1679925927
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.1424367543
Short name T1577
Test name
Test status
Simulation time 8382502368 ps
CPU time 11.66 seconds
Started May 21 01:10:37 PM PDT 24
Finished May 21 01:10:51 PM PDT 24
Peak memory 205444 kb
Host smart-6526b4fe-10d2-49a4-96c0-448580203ef9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1424367543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.1424367543
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.3919809962
Short name T906
Test name
Test status
Simulation time 8386166836 ps
CPU time 12.87 seconds
Started May 21 01:10:36 PM PDT 24
Finished May 21 01:10:51 PM PDT 24
Peak memory 205424 kb
Host smart-0aa4efde-77ab-48f2-b044-08283ee5efa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39198
09962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.3919809962
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.3474862296
Short name T1310
Test name
Test status
Simulation time 8393104957 ps
CPU time 11.64 seconds
Started May 21 01:10:31 PM PDT 24
Finished May 21 01:10:44 PM PDT 24
Peak memory 205532 kb
Host smart-aa6d3072-2456-449b-a7fb-7b6032c49891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34748
62296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3474862296
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.961902079
Short name T63
Test name
Test status
Simulation time 8397754666 ps
CPU time 12.01 seconds
Started May 21 01:10:35 PM PDT 24
Finished May 21 01:10:49 PM PDT 24
Peak memory 205312 kb
Host smart-3c8ba628-7dac-44f7-ab62-2a70a1404849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96190
2079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.961902079
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.179712422
Short name T482
Test name
Test status
Simulation time 8766574899 ps
CPU time 12.26 seconds
Started May 21 01:10:29 PM PDT 24
Finished May 21 01:10:42 PM PDT 24
Peak memory 205372 kb
Host smart-03aadc11-5508-45d1-9e6f-55fd922ac28b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17971
2422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.179712422
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.739604520
Short name T992
Test name
Test status
Simulation time 8378347124 ps
CPU time 12.16 seconds
Started May 21 01:10:31 PM PDT 24
Finished May 21 01:10:45 PM PDT 24
Peak memory 205324 kb
Host smart-4422ce36-a04d-45d6-b479-4cf5a5b5db08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73960
4520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.739604520
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.3996043387
Short name T1045
Test name
Test status
Simulation time 8375008454 ps
CPU time 11.74 seconds
Started May 21 01:10:33 PM PDT 24
Finished May 21 01:10:46 PM PDT 24
Peak memory 205272 kb
Host smart-361b14eb-2c48-4b49-ac2e-e11e8ba09d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39960
43387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.3996043387
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.554319441
Short name T918
Test name
Test status
Simulation time 8414179477 ps
CPU time 12.15 seconds
Started May 21 01:10:33 PM PDT 24
Finished May 21 01:10:46 PM PDT 24
Peak memory 205408 kb
Host smart-5d5f0c8f-ed05-4435-8679-bd911022e1da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55431
9441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.554319441
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.4177659764
Short name T427
Test name
Test status
Simulation time 8418341617 ps
CPU time 13.56 seconds
Started May 21 01:10:37 PM PDT 24
Finished May 21 01:10:52 PM PDT 24
Peak memory 205336 kb
Host smart-56d82f10-5685-4be8-9b9c-5fd70f843e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41776
59764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.4177659764
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2970987395
Short name T1499
Test name
Test status
Simulation time 8370550177 ps
CPU time 12.42 seconds
Started May 21 01:10:36 PM PDT 24
Finished May 21 01:10:51 PM PDT 24
Peak memory 205268 kb
Host smart-6db63587-22e3-49fd-a991-ba4ac6c4f77a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29709
87395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2970987395
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.1149583652
Short name T654
Test name
Test status
Simulation time 8395171796 ps
CPU time 11.77 seconds
Started May 21 01:10:31 PM PDT 24
Finished May 21 01:10:44 PM PDT 24
Peak memory 205344 kb
Host smart-4b15e185-95a6-4d01-b9b8-5db195be1a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11495
83652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1149583652
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.368231840
Short name T834
Test name
Test status
Simulation time 11596370311 ps
CPU time 15.32 seconds
Started May 21 01:10:34 PM PDT 24
Finished May 21 01:10:51 PM PDT 24
Peak memory 205336 kb
Host smart-95b9b568-4594-42da-b4ca-a67dfd102530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36823
1840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.368231840
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3718140884
Short name T1093
Test name
Test status
Simulation time 8423003089 ps
CPU time 11.46 seconds
Started May 21 01:10:33 PM PDT 24
Finished May 21 01:10:46 PM PDT 24
Peak memory 205368 kb
Host smart-26f4e04d-8812-42f3-bf64-0c0fb6d2cc4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37181
40884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3718140884
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.2911518373
Short name T539
Test name
Test status
Simulation time 8374514226 ps
CPU time 11.2 seconds
Started May 21 01:10:31 PM PDT 24
Finished May 21 01:10:44 PM PDT 24
Peak memory 205332 kb
Host smart-4516b2e9-ae84-41ff-bcb4-27b3df2e8932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29115
18373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2911518373
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3527686362
Short name T138
Test name
Test status
Simulation time 8425185096 ps
CPU time 13.09 seconds
Started May 21 01:10:31 PM PDT 24
Finished May 21 01:10:46 PM PDT 24
Peak memory 205336 kb
Host smart-ec2140cd-7518-480b-b527-fd0a2953c569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35276
86362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3527686362
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.2072937576
Short name T1203
Test name
Test status
Simulation time 8413438211 ps
CPU time 11.51 seconds
Started May 21 01:10:29 PM PDT 24
Finished May 21 01:10:41 PM PDT 24
Peak memory 205384 kb
Host smart-f60cb892-62ee-40f7-aedf-a0217f95c49f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20729
37576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.2072937576
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.270736187
Short name T978
Test name
Test status
Simulation time 8392846289 ps
CPU time 14.02 seconds
Started May 21 01:10:31 PM PDT 24
Finished May 21 01:10:47 PM PDT 24
Peak memory 205376 kb
Host smart-f4e15bf4-500e-423d-90c2-e82a7486b53c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27073
6187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.270736187
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.784992138
Short name T300
Test name
Test status
Simulation time 8398288983 ps
CPU time 13.22 seconds
Started May 21 01:10:34 PM PDT 24
Finished May 21 01:10:49 PM PDT 24
Peak memory 205388 kb
Host smart-7aaee6f9-40be-4a46-ab98-96d61864546c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78499
2138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.784992138
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_eop_single_bit_handling.3692161244
Short name T454
Test name
Test status
Simulation time 8429903860 ps
CPU time 11.39 seconds
Started May 21 01:10:33 PM PDT 24
Finished May 21 01:10:45 PM PDT 24
Peak memory 205408 kb
Host smart-0267d1e2-2d22-4819-b574-cbe735852f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36921
61244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_eop_single_bit_handling.3692161244
Directory /workspace/33.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.4279617001
Short name T99
Test name
Test status
Simulation time 8366870847 ps
CPU time 13.92 seconds
Started May 21 01:10:30 PM PDT 24
Finished May 21 01:10:46 PM PDT 24
Peak memory 205348 kb
Host smart-be598b30-97e0-4f46-81e4-9fa88c27cd4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42796
17001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.4279617001
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.3964632905
Short name T977
Test name
Test status
Simulation time 8365178358 ps
CPU time 13.02 seconds
Started May 21 01:10:36 PM PDT 24
Finished May 21 01:10:51 PM PDT 24
Peak memory 205348 kb
Host smart-6f67f746-f304-4031-af5c-e6a68b0ec315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39646
32905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.3964632905
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.2201532700
Short name T187
Test name
Test status
Simulation time 22967427309 ps
CPU time 43.64 seconds
Started May 21 01:10:34 PM PDT 24
Finished May 21 01:11:19 PM PDT 24
Peak memory 205416 kb
Host smart-b54296dd-7278-4d24-93a4-e4b103bfe851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22015
32700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.2201532700
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.3458294724
Short name T1538
Test name
Test status
Simulation time 8396433413 ps
CPU time 12.83 seconds
Started May 21 01:10:31 PM PDT 24
Finished May 21 01:10:46 PM PDT 24
Peak memory 205344 kb
Host smart-939418c7-5f56-4a8c-91db-a00e8dc5e5c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34582
94724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.3458294724
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.538383115
Short name T892
Test name
Test status
Simulation time 8394028051 ps
CPU time 13.32 seconds
Started May 21 01:10:35 PM PDT 24
Finished May 21 01:10:49 PM PDT 24
Peak memory 205352 kb
Host smart-208b1981-acd6-45dd-99ab-9bb47fea23ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53838
3115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.538383115
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.884929802
Short name T975
Test name
Test status
Simulation time 8385237369 ps
CPU time 11.53 seconds
Started May 21 01:10:33 PM PDT 24
Finished May 21 01:10:45 PM PDT 24
Peak memory 205356 kb
Host smart-660453ce-27df-4db5-9507-a2fc2bb388a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88492
9802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.884929802
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1434152756
Short name T1133
Test name
Test status
Simulation time 8366691087 ps
CPU time 14.39 seconds
Started May 21 01:10:30 PM PDT 24
Finished May 21 01:10:47 PM PDT 24
Peak memory 205312 kb
Host smart-a6a922ba-3b9e-46dd-8262-1627940db2b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14341
52756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1434152756
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.769109185
Short name T577
Test name
Test status
Simulation time 8370885705 ps
CPU time 12.11 seconds
Started May 21 01:10:31 PM PDT 24
Finished May 21 01:10:45 PM PDT 24
Peak memory 205340 kb
Host smart-31c24a41-0b22-452e-92d6-aedda80f0d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76910
9185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.769109185
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.235545905
Short name T37
Test name
Test status
Simulation time 8385665072 ps
CPU time 11.58 seconds
Started May 21 01:10:34 PM PDT 24
Finished May 21 01:10:47 PM PDT 24
Peak memory 205412 kb
Host smart-b1783e88-8c9c-41c6-8298-8b40621decb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23554
5905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.235545905
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.3480942649
Short name T157
Test name
Test status
Simulation time 8463728403 ps
CPU time 11.12 seconds
Started May 21 01:10:30 PM PDT 24
Finished May 21 01:10:43 PM PDT 24
Peak memory 205320 kb
Host smart-0f37abf2-7a40-43b4-91fc-a87366a3f65b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34809
42649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3480942649
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.550367920
Short name T1519
Test name
Test status
Simulation time 8389581848 ps
CPU time 13.04 seconds
Started May 21 01:10:28 PM PDT 24
Finished May 21 01:10:43 PM PDT 24
Peak memory 205364 kb
Host smart-631f7444-e5e0-40e6-a71d-2adc3b39d2bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55036
7920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.550367920
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.569317455
Short name T990
Test name
Test status
Simulation time 8425725995 ps
CPU time 11.32 seconds
Started May 21 01:10:34 PM PDT 24
Finished May 21 01:10:46 PM PDT 24
Peak memory 205396 kb
Host smart-947a1176-3148-4018-a395-6921c8e25d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56931
7455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.569317455
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.468384340
Short name T1546
Test name
Test status
Simulation time 8469104946 ps
CPU time 12.93 seconds
Started May 21 01:10:48 PM PDT 24
Finished May 21 01:11:03 PM PDT 24
Peak memory 205376 kb
Host smart-286d7059-4e00-463a-a216-5d687be4c55e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=468384340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.468384340
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.3774811597
Short name T1631
Test name
Test status
Simulation time 8382370596 ps
CPU time 11.5 seconds
Started May 21 01:10:48 PM PDT 24
Finished May 21 01:11:02 PM PDT 24
Peak memory 205392 kb
Host smart-53f7528a-e965-4459-8d8d-052006eecb44
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3774811597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.3774811597
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.3086241767
Short name T1510
Test name
Test status
Simulation time 8460684821 ps
CPU time 12.56 seconds
Started May 21 01:10:49 PM PDT 24
Finished May 21 01:11:04 PM PDT 24
Peak memory 205396 kb
Host smart-2c380461-fe5f-478d-8894-ed71c804d151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30862
41767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.3086241767
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.3391642895
Short name T1142
Test name
Test status
Simulation time 8378597912 ps
CPU time 12 seconds
Started May 21 01:10:37 PM PDT 24
Finished May 21 01:10:51 PM PDT 24
Peak memory 205348 kb
Host smart-d7299147-3fb1-45be-a17f-168248a0b446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33916
42895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.3391642895
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.2506974553
Short name T1077
Test name
Test status
Simulation time 8638674493 ps
CPU time 12.67 seconds
Started May 21 01:10:35 PM PDT 24
Finished May 21 01:10:50 PM PDT 24
Peak memory 205320 kb
Host smart-e508614b-33f8-42bc-9df1-904f41e9f75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25069
74553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.2506974553
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.781845779
Short name T1297
Test name
Test status
Simulation time 8371070289 ps
CPU time 12.16 seconds
Started May 21 01:10:39 PM PDT 24
Finished May 21 01:10:53 PM PDT 24
Peak memory 204956 kb
Host smart-40f975c0-eb13-45cf-a983-a5818cdcc13b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78184
5779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.781845779
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.4157586464
Short name T1691
Test name
Test status
Simulation time 8408028245 ps
CPU time 11.11 seconds
Started May 21 01:10:36 PM PDT 24
Finished May 21 01:10:49 PM PDT 24
Peak memory 205368 kb
Host smart-0c3e0c41-65d6-4652-a5a9-9b30677a1bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41575
86464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.4157586464
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.1599200474
Short name T467
Test name
Test status
Simulation time 8432314087 ps
CPU time 12.66 seconds
Started May 21 01:10:37 PM PDT 24
Finished May 21 01:10:52 PM PDT 24
Peak memory 205364 kb
Host smart-748d3b99-7210-48df-8e7f-76b505ae4bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15992
00474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.1599200474
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.2412957677
Short name T1322
Test name
Test status
Simulation time 8457536412 ps
CPU time 14.3 seconds
Started May 21 01:10:50 PM PDT 24
Finished May 21 01:11:07 PM PDT 24
Peak memory 205616 kb
Host smart-21214512-2836-45e4-8ad8-226d3f3098e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24129
57677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.2412957677
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.1800264549
Short name T1288
Test name
Test status
Simulation time 8368372374 ps
CPU time 14.59 seconds
Started May 21 01:10:49 PM PDT 24
Finished May 21 01:11:07 PM PDT 24
Peak memory 205316 kb
Host smart-eb47b91f-0252-45d7-91b7-8e739def52e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18002
64549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.1800264549
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.1036818329
Short name T1408
Test name
Test status
Simulation time 8400331392 ps
CPU time 12.85 seconds
Started May 21 01:10:36 PM PDT 24
Finished May 21 01:10:51 PM PDT 24
Peak memory 205412 kb
Host smart-8a107ad2-6b50-4271-a78d-bf929e89a879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10368
18329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.1036818329
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.2385275189
Short name T527
Test name
Test status
Simulation time 11560367369 ps
CPU time 14.14 seconds
Started May 21 01:10:39 PM PDT 24
Finished May 21 01:10:55 PM PDT 24
Peak memory 205068 kb
Host smart-3b920566-c240-4266-9b47-5f41623aecd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23852
75189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.2385275189
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.922860955
Short name T1712
Test name
Test status
Simulation time 8417248153 ps
CPU time 12.35 seconds
Started May 21 01:10:36 PM PDT 24
Finished May 21 01:10:50 PM PDT 24
Peak memory 205320 kb
Host smart-68718007-486b-4ce8-8878-2d46faa409d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92286
0955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.922860955
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.1263448374
Short name T551
Test name
Test status
Simulation time 8378371484 ps
CPU time 11.84 seconds
Started May 21 01:10:36 PM PDT 24
Finished May 21 01:10:50 PM PDT 24
Peak memory 205268 kb
Host smart-f2ca4111-d53e-482b-801a-ce1b9d277824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12634
48374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.1263448374
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.4177320485
Short name T139
Test name
Test status
Simulation time 8423972745 ps
CPU time 11.34 seconds
Started May 21 01:10:44 PM PDT 24
Finished May 21 01:10:56 PM PDT 24
Peak memory 205176 kb
Host smart-053e10d1-f61c-4d25-a141-0d33f0e81ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41773
20485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.4177320485
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.1136377689
Short name T1559
Test name
Test status
Simulation time 8418956245 ps
CPU time 11.75 seconds
Started May 21 01:10:46 PM PDT 24
Finished May 21 01:10:58 PM PDT 24
Peak memory 205276 kb
Host smart-275208e3-e297-4bbb-bebb-2e97c80da7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11363
77689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.1136377689
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.1841837650
Short name T1003
Test name
Test status
Simulation time 8429683185 ps
CPU time 12.65 seconds
Started May 21 01:10:44 PM PDT 24
Finished May 21 01:10:57 PM PDT 24
Peak memory 205348 kb
Host smart-222c768f-fd18-4aa8-8b0b-91b2c598e8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18418
37650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.1841837650
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1548296506
Short name T1530
Test name
Test status
Simulation time 8408724186 ps
CPU time 12.21 seconds
Started May 21 01:10:43 PM PDT 24
Finished May 21 01:10:56 PM PDT 24
Peak memory 205328 kb
Host smart-5aff26f0-b805-4a67-9827-df2d57ac06e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15482
96506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1548296506
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.785647052
Short name T1097
Test name
Test status
Simulation time 8409636455 ps
CPU time 12.28 seconds
Started May 21 01:10:48 PM PDT 24
Finished May 21 01:11:01 PM PDT 24
Peak memory 205296 kb
Host smart-f758b31d-300c-4c39-847f-651aa4ce48b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78564
7052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.785647052
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_eop_single_bit_handling.1481530277
Short name T109
Test name
Test status
Simulation time 8390443846 ps
CPU time 11.15 seconds
Started May 21 01:10:51 PM PDT 24
Finished May 21 01:11:05 PM PDT 24
Peak memory 205340 kb
Host smart-003a2757-ad61-4b80-ad89-d4b4cda995dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14815
30277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_eop_single_bit_handling.1481530277
Directory /workspace/34.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.1135126896
Short name T1595
Test name
Test status
Simulation time 8391250291 ps
CPU time 11.34 seconds
Started May 21 01:10:50 PM PDT 24
Finished May 21 01:11:04 PM PDT 24
Peak memory 205416 kb
Host smart-80a1d049-0a50-41bf-9de1-bcf7d4b5b595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11351
26896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.1135126896
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.431870883
Short name T1688
Test name
Test status
Simulation time 8377029847 ps
CPU time 11.65 seconds
Started May 21 01:10:48 PM PDT 24
Finished May 21 01:11:02 PM PDT 24
Peak memory 205280 kb
Host smart-f2d8226d-812b-4fdc-8196-098ff595ca2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43187
0883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.431870883
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.2629140953
Short name T194
Test name
Test status
Simulation time 28368695856 ps
CPU time 54.89 seconds
Started May 21 01:10:42 PM PDT 24
Finished May 21 01:11:38 PM PDT 24
Peak memory 205300 kb
Host smart-94df5802-078b-4076-9fd3-5c7ddf9fc8a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26291
40953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.2629140953
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.1207717758
Short name T878
Test name
Test status
Simulation time 8371843134 ps
CPU time 12.44 seconds
Started May 21 01:10:45 PM PDT 24
Finished May 21 01:10:58 PM PDT 24
Peak memory 205352 kb
Host smart-74774858-4f86-47c9-9b25-0d319f0003b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12077
17758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.1207717758
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.33662513
Short name T823
Test name
Test status
Simulation time 8500333816 ps
CPU time 11.66 seconds
Started May 21 01:10:47 PM PDT 24
Finished May 21 01:11:00 PM PDT 24
Peak memory 205348 kb
Host smart-8f2ac09e-7ac5-400a-b77e-017e0c6763b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33662
513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.33662513
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.1693813757
Short name T600
Test name
Test status
Simulation time 8378174056 ps
CPU time 11.89 seconds
Started May 21 01:10:43 PM PDT 24
Finished May 21 01:10:56 PM PDT 24
Peak memory 205448 kb
Host smart-3655d981-fbbe-48d3-8d45-e9f7260012fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16938
13757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.1693813757
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.428852417
Short name T926
Test name
Test status
Simulation time 8364589904 ps
CPU time 11.82 seconds
Started May 21 01:10:46 PM PDT 24
Finished May 21 01:10:58 PM PDT 24
Peak memory 205300 kb
Host smart-880b3850-c540-467a-aa83-acfd5de2b6c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42885
2417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.428852417
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.1519429699
Short name T1542
Test name
Test status
Simulation time 8393338432 ps
CPU time 11.04 seconds
Started May 21 01:10:49 PM PDT 24
Finished May 21 01:11:02 PM PDT 24
Peak memory 205388 kb
Host smart-ed905f6f-06c5-4960-8fbe-7f9c297e8a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15194
29699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.1519429699
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1546259790
Short name T36
Test name
Test status
Simulation time 8383815190 ps
CPU time 11.77 seconds
Started May 21 01:10:48 PM PDT 24
Finished May 21 01:11:02 PM PDT 24
Peak memory 205352 kb
Host smart-295db9f1-dfd6-426c-8687-f3b4919595cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15462
59790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1546259790
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.3680237475
Short name T1171
Test name
Test status
Simulation time 8445709637 ps
CPU time 11.59 seconds
Started May 21 01:10:35 PM PDT 24
Finished May 21 01:10:48 PM PDT 24
Peak memory 205340 kb
Host smart-eea3bf32-cda1-4882-865f-16134e4ed561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36802
37475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3680237475
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.3863567060
Short name T957
Test name
Test status
Simulation time 8389647248 ps
CPU time 11.07 seconds
Started May 21 01:10:49 PM PDT 24
Finished May 21 01:11:02 PM PDT 24
Peak memory 205348 kb
Host smart-ab871ea0-24ed-46bc-a7f8-0d2433b610bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38635
67060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.3863567060
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.2803034872
Short name T999
Test name
Test status
Simulation time 8411279179 ps
CPU time 12.41 seconds
Started May 21 01:10:43 PM PDT 24
Finished May 21 01:10:56 PM PDT 24
Peak memory 205364 kb
Host smart-0297f476-c6c7-43a0-bb5b-6c57a4727dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28030
34872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.2803034872
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.2613236804
Short name T819
Test name
Test status
Simulation time 8467645505 ps
CPU time 11.29 seconds
Started May 21 01:10:57 PM PDT 24
Finished May 21 01:11:11 PM PDT 24
Peak memory 205348 kb
Host smart-5fac3ae4-3296-40db-8ab9-525c613f2aa2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2613236804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.2613236804
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.2563528460
Short name T318
Test name
Test status
Simulation time 8374808060 ps
CPU time 11.57 seconds
Started May 21 01:10:59 PM PDT 24
Finished May 21 01:11:12 PM PDT 24
Peak memory 205400 kb
Host smart-221bcb78-8f53-4cf1-8193-73bc9643a06c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2563528460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.2563528460
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.1744205840
Short name T1387
Test name
Test status
Simulation time 8441529841 ps
CPU time 12.63 seconds
Started May 21 01:10:54 PM PDT 24
Finished May 21 01:11:10 PM PDT 24
Peak memory 205400 kb
Host smart-e28020b7-5f94-4392-9ca5-9bd49b82b8ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17442
05840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.1744205840
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1138443445
Short name T648
Test name
Test status
Simulation time 8377988345 ps
CPU time 12.68 seconds
Started May 21 01:10:52 PM PDT 24
Finished May 21 01:11:07 PM PDT 24
Peak memory 205392 kb
Host smart-347bd658-538d-4e7e-bbaa-a93ecd31989c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11384
43445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1138443445
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.748946310
Short name T884
Test name
Test status
Simulation time 9490315509 ps
CPU time 13.49 seconds
Started May 21 01:10:50 PM PDT 24
Finished May 21 01:11:06 PM PDT 24
Peak memory 205296 kb
Host smart-a99694cb-df8a-46b4-9187-3eb4073bd6f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74894
6310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.748946310
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.1835752560
Short name T1088
Test name
Test status
Simulation time 8368390288 ps
CPU time 10.67 seconds
Started May 21 01:10:49 PM PDT 24
Finished May 21 01:11:01 PM PDT 24
Peak memory 205324 kb
Host smart-f9ba1f50-2104-4406-b560-8a8e546215b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18357
52560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.1835752560
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.108230385
Short name T571
Test name
Test status
Simulation time 8376453855 ps
CPU time 11.62 seconds
Started May 21 01:10:49 PM PDT 24
Finished May 21 01:11:03 PM PDT 24
Peak memory 205328 kb
Host smart-72b9abce-a52b-4d76-be76-50cd1e4d06b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10823
0385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.108230385
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.546646237
Short name T1139
Test name
Test status
Simulation time 9181852366 ps
CPU time 13.18 seconds
Started May 21 01:10:50 PM PDT 24
Finished May 21 01:11:06 PM PDT 24
Peak memory 205352 kb
Host smart-a9c6e12a-58d8-412a-b2dd-cdf897449749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54664
6237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.546646237
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.2294665796
Short name T1524
Test name
Test status
Simulation time 8558409560 ps
CPU time 15.36 seconds
Started May 21 01:10:49 PM PDT 24
Finished May 21 01:11:08 PM PDT 24
Peak memory 205328 kb
Host smart-e6134e79-0ad0-45a4-9b41-7a90d9b905cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22946
65796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.2294665796
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.372235478
Short name T775
Test name
Test status
Simulation time 8413344146 ps
CPU time 12.57 seconds
Started May 21 01:10:56 PM PDT 24
Finished May 21 01:11:12 PM PDT 24
Peak memory 205448 kb
Host smart-e7522a9d-7726-4bfb-b16e-a13dffd9d8c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37223
5478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.372235478
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.2366751612
Short name T692
Test name
Test status
Simulation time 8419350253 ps
CPU time 12.06 seconds
Started May 21 01:10:59 PM PDT 24
Finished May 21 01:11:12 PM PDT 24
Peak memory 205216 kb
Host smart-d2eb1232-b212-4416-a57e-0a377723ec29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23667
51612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.2366751612
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3655041200
Short name T805
Test name
Test status
Simulation time 8450996357 ps
CPU time 11.6 seconds
Started May 21 01:10:51 PM PDT 24
Finished May 21 01:11:05 PM PDT 24
Peak memory 205364 kb
Host smart-70e5cf9c-315e-4c75-8916-4b06a7dad388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36550
41200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3655041200
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.256860122
Short name T1531
Test name
Test status
Simulation time 11502600557 ps
CPU time 15.47 seconds
Started May 21 01:10:48 PM PDT 24
Finished May 21 01:11:05 PM PDT 24
Peak memory 205348 kb
Host smart-a7736c52-77f0-46f2-a028-b353f5d0228e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25686
0122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.256860122
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2609380051
Short name T1386
Test name
Test status
Simulation time 8417556121 ps
CPU time 11.37 seconds
Started May 21 01:10:50 PM PDT 24
Finished May 21 01:11:05 PM PDT 24
Peak memory 205260 kb
Host smart-df05cbda-3d3e-4009-bb13-dcb742f76e6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26093
80051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2609380051
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.4191724739
Short name T574
Test name
Test status
Simulation time 8370280866 ps
CPU time 13.11 seconds
Started May 21 01:10:49 PM PDT 24
Finished May 21 01:11:05 PM PDT 24
Peak memory 205400 kb
Host smart-32b5aea2-8894-4611-82b0-aab274c54251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41917
24739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.4191724739
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2028894621
Short name T143
Test name
Test status
Simulation time 8465927163 ps
CPU time 14.85 seconds
Started May 21 01:10:48 PM PDT 24
Finished May 21 01:11:04 PM PDT 24
Peak memory 205272 kb
Host smart-ef8aec02-c75d-4a17-8506-3d0643365bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20288
94621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2028894621
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.2970661776
Short name T818
Test name
Test status
Simulation time 8443983071 ps
CPU time 12.27 seconds
Started May 21 01:10:51 PM PDT 24
Finished May 21 01:11:06 PM PDT 24
Peak memory 205376 kb
Host smart-00584072-93e5-4467-a29a-ee8649d3af3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29706
61776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.2970661776
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3424692165
Short name T537
Test name
Test status
Simulation time 8376588806 ps
CPU time 11.2 seconds
Started May 21 01:10:51 PM PDT 24
Finished May 21 01:11:05 PM PDT 24
Peak memory 205352 kb
Host smart-88779a45-2a38-4831-9047-ad9a24671918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34246
92165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3424692165
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.4017448081
Short name T1721
Test name
Test status
Simulation time 8424297295 ps
CPU time 12.12 seconds
Started May 21 01:10:50 PM PDT 24
Finished May 21 01:11:05 PM PDT 24
Peak memory 205272 kb
Host smart-ccda88ae-4dde-4aa2-a875-87efe583265b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40174
48081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.4017448081
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.3233239326
Short name T159
Test name
Test status
Simulation time 8398525690 ps
CPU time 13.24 seconds
Started May 21 01:10:55 PM PDT 24
Finished May 21 01:11:12 PM PDT 24
Peak memory 205404 kb
Host smart-b4467d64-35ea-4972-800a-1ebbea1cfd2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32332
39326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.3233239326
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_eop_single_bit_handling.803726876
Short name T1067
Test name
Test status
Simulation time 8376763825 ps
CPU time 11.58 seconds
Started May 21 01:10:54 PM PDT 24
Finished May 21 01:11:08 PM PDT 24
Peak memory 205392 kb
Host smart-021c6267-2d64-4324-9c44-6fd4ad1e0a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80372
6876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_eop_single_bit_handling.803726876
Directory /workspace/35.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.1475784151
Short name T1092
Test name
Test status
Simulation time 8399354112 ps
CPU time 15.1 seconds
Started May 21 01:10:58 PM PDT 24
Finished May 21 01:11:15 PM PDT 24
Peak memory 205296 kb
Host smart-0505c448-45aa-4fce-9fc7-fd9480c797fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14757
84151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.1475784151
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.2003595796
Short name T228
Test name
Test status
Simulation time 29295002596 ps
CPU time 54.65 seconds
Started May 21 01:10:50 PM PDT 24
Finished May 21 01:11:48 PM PDT 24
Peak memory 205412 kb
Host smart-8e7b88b7-eeec-4db2-ab62-2d5962e8d38f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20035
95796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.2003595796
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.3754473329
Short name T1592
Test name
Test status
Simulation time 8415553126 ps
CPU time 13.11 seconds
Started May 21 01:10:51 PM PDT 24
Finished May 21 01:11:07 PM PDT 24
Peak memory 205404 kb
Host smart-b35237de-bc6e-438d-8f9f-848e135fd5b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37544
73329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3754473329
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2039427500
Short name T1064
Test name
Test status
Simulation time 8453434960 ps
CPU time 12.9 seconds
Started May 21 01:10:52 PM PDT 24
Finished May 21 01:11:08 PM PDT 24
Peak memory 205324 kb
Host smart-ef40f8ee-ba86-4195-963b-125b018c2f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20394
27500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2039427500
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.2505926827
Short name T606
Test name
Test status
Simulation time 8417142280 ps
CPU time 11.18 seconds
Started May 21 01:10:52 PM PDT 24
Finished May 21 01:11:06 PM PDT 24
Peak memory 205336 kb
Host smart-b8f128c8-f816-48d2-9408-0c19da295917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25059
26827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.2505926827
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.3289833496
Short name T515
Test name
Test status
Simulation time 8369701173 ps
CPU time 12.14 seconds
Started May 21 01:10:55 PM PDT 24
Finished May 21 01:11:10 PM PDT 24
Peak memory 205344 kb
Host smart-9bcc2cc1-652e-47c2-a3fc-fa8d853fbd01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32898
33496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.3289833496
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.2438888200
Short name T1371
Test name
Test status
Simulation time 8400130640 ps
CPU time 11.96 seconds
Started May 21 01:10:55 PM PDT 24
Finished May 21 01:11:10 PM PDT 24
Peak memory 205284 kb
Host smart-08a40d37-1055-4734-9bd0-9c2138e569ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24388
88200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.2438888200
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.4182535669
Short name T1382
Test name
Test status
Simulation time 8374225971 ps
CPU time 12.43 seconds
Started May 21 01:10:55 PM PDT 24
Finished May 21 01:11:10 PM PDT 24
Peak memory 205352 kb
Host smart-9a779b44-077e-45f7-bad0-0eff4cce4db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41825
35669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.4182535669
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.3381671540
Short name T1697
Test name
Test status
Simulation time 8451779082 ps
CPU time 13.6 seconds
Started May 21 01:10:49 PM PDT 24
Finished May 21 01:11:05 PM PDT 24
Peak memory 205240 kb
Host smart-33dbb03d-d6cd-4e9b-8cdd-bc3845e7a4e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33816
71540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3381671540
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.2567687218
Short name T337
Test name
Test status
Simulation time 8472796382 ps
CPU time 11.74 seconds
Started May 21 01:10:55 PM PDT 24
Finished May 21 01:11:10 PM PDT 24
Peak memory 205288 kb
Host smart-b85c11a1-a115-4d35-8293-b0fe5d5dcd66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25676
87218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.2567687218
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.3064425847
Short name T389
Test name
Test status
Simulation time 8408472239 ps
CPU time 14.42 seconds
Started May 21 01:10:58 PM PDT 24
Finished May 21 01:11:14 PM PDT 24
Peak memory 205276 kb
Host smart-ac11b252-52a6-4315-8423-b47c77619dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30644
25847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.3064425847
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.2443290007
Short name T1016
Test name
Test status
Simulation time 8458841855 ps
CPU time 13.26 seconds
Started May 21 01:11:01 PM PDT 24
Finished May 21 01:11:16 PM PDT 24
Peak memory 205424 kb
Host smart-e2b93204-26a2-45fa-ab04-26bdb10c0461
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2443290007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.2443290007
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.2738371363
Short name T1042
Test name
Test status
Simulation time 8381942156 ps
CPU time 12.11 seconds
Started May 21 01:11:06 PM PDT 24
Finished May 21 01:11:19 PM PDT 24
Peak memory 205280 kb
Host smart-e293fac0-eb52-4ae4-953e-4d1b49ba3cc5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2738371363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.2738371363
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.2071512025
Short name T1127
Test name
Test status
Simulation time 8435061639 ps
CPU time 15.52 seconds
Started May 21 01:11:01 PM PDT 24
Finished May 21 01:11:19 PM PDT 24
Peak memory 205560 kb
Host smart-30bf60c6-42e2-483a-a2ad-73f5dc3daef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20715
12025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.2071512025
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1292832055
Short name T1451
Test name
Test status
Simulation time 8399992981 ps
CPU time 13.86 seconds
Started May 21 01:10:54 PM PDT 24
Finished May 21 01:11:10 PM PDT 24
Peak memory 205336 kb
Host smart-108d5e2c-9b80-4308-9eda-53db37d9f3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12928
32055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1292832055
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.2719583279
Short name T1399
Test name
Test status
Simulation time 8392043450 ps
CPU time 11.41 seconds
Started May 21 01:10:58 PM PDT 24
Finished May 21 01:11:11 PM PDT 24
Peak memory 205292 kb
Host smart-4c4f75e2-8569-459a-8aa3-9a617e273f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27195
83279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.2719583279
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.1058806840
Short name T1600
Test name
Test status
Simulation time 8457621606 ps
CPU time 11.54 seconds
Started May 21 01:10:54 PM PDT 24
Finished May 21 01:11:09 PM PDT 24
Peak memory 205268 kb
Host smart-e1cc1395-9c6d-421a-b225-f98b712091e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10588
06840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.1058806840
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.1274583707
Short name T1564
Test name
Test status
Simulation time 8370461658 ps
CPU time 11.51 seconds
Started May 21 01:10:56 PM PDT 24
Finished May 21 01:11:10 PM PDT 24
Peak memory 205396 kb
Host smart-7d1b2749-8dbc-44be-b17d-0a067d16b35e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12745
83707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.1274583707
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.4080151178
Short name T310
Test name
Test status
Simulation time 8382568605 ps
CPU time 11.42 seconds
Started May 21 01:10:58 PM PDT 24
Finished May 21 01:11:11 PM PDT 24
Peak memory 205328 kb
Host smart-e8fcb898-fee0-49dc-936e-7741889b69b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40801
51178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.4080151178
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.2119148355
Short name T492
Test name
Test status
Simulation time 8623626710 ps
CPU time 13.82 seconds
Started May 21 01:10:56 PM PDT 24
Finished May 21 01:11:13 PM PDT 24
Peak memory 205312 kb
Host smart-c9198d18-2f41-4f42-a454-587a4d05ebdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21191
48355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.2119148355
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.3581724513
Short name T1414
Test name
Test status
Simulation time 8454753833 ps
CPU time 12.05 seconds
Started May 21 01:11:06 PM PDT 24
Finished May 21 01:11:20 PM PDT 24
Peak memory 205352 kb
Host smart-1a27e976-fc69-4148-95bd-0feede67c9d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35817
24513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.3581724513
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.1238375177
Short name T330
Test name
Test status
Simulation time 8379635166 ps
CPU time 12.33 seconds
Started May 21 01:11:02 PM PDT 24
Finished May 21 01:11:16 PM PDT 24
Peak memory 205380 kb
Host smart-c8d9ccfc-c5b9-449f-ae54-b12e3b67832c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12383
75177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.1238375177
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.3591041025
Short name T1326
Test name
Test status
Simulation time 8390897984 ps
CPU time 12.38 seconds
Started May 21 01:10:55 PM PDT 24
Finished May 21 01:11:11 PM PDT 24
Peak memory 205348 kb
Host smart-541e34d8-6f27-43e6-8351-ecefdd86de84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35910
41025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.3591041025
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.1411315260
Short name T674
Test name
Test status
Simulation time 11535459209 ps
CPU time 17.28 seconds
Started May 21 01:10:59 PM PDT 24
Finished May 21 01:11:18 PM PDT 24
Peak memory 205252 kb
Host smart-f3a9b50b-73d7-421a-930e-be0127b4d16b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14113
15260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.1411315260
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.375315395
Short name T1393
Test name
Test status
Simulation time 8419696709 ps
CPU time 12.59 seconds
Started May 21 01:10:56 PM PDT 24
Finished May 21 01:11:12 PM PDT 24
Peak memory 205312 kb
Host smart-039a9845-6a67-4b3a-960b-7d50e6dcdcf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37531
5395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.375315395
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.1128259401
Short name T569
Test name
Test status
Simulation time 8387103072 ps
CPU time 12.23 seconds
Started May 21 01:10:56 PM PDT 24
Finished May 21 01:11:11 PM PDT 24
Peak memory 205420 kb
Host smart-397ead24-8f4c-4868-81a6-b9348f49f87b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11282
59401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.1128259401
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.3704542848
Short name T147
Test name
Test status
Simulation time 8405253466 ps
CPU time 12.89 seconds
Started May 21 01:10:55 PM PDT 24
Finished May 21 01:11:10 PM PDT 24
Peak memory 205396 kb
Host smart-3eca99be-2af8-4c80-97ac-225a9924216c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37045
42848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.3704542848
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.226616875
Short name T660
Test name
Test status
Simulation time 8413522402 ps
CPU time 12.12 seconds
Started May 21 01:10:54 PM PDT 24
Finished May 21 01:11:08 PM PDT 24
Peak memory 205324 kb
Host smart-8b2b759d-ab01-47c4-b607-031cc0aa012f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22661
6875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.226616875
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3564663377
Short name T374
Test name
Test status
Simulation time 8417331087 ps
CPU time 14.31 seconds
Started May 21 01:10:56 PM PDT 24
Finished May 21 01:11:13 PM PDT 24
Peak memory 205348 kb
Host smart-715898f7-5ef6-4128-a748-d447af069acd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35646
63377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3564663377
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2327235141
Short name T833
Test name
Test status
Simulation time 8407277600 ps
CPU time 11.99 seconds
Started May 21 01:10:56 PM PDT 24
Finished May 21 01:11:11 PM PDT 24
Peak memory 205372 kb
Host smart-7ba85947-94bc-4c47-b27e-8579c0121ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23272
35141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2327235141
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.1558972994
Short name T185
Test name
Test status
Simulation time 8435030054 ps
CPU time 11.48 seconds
Started May 21 01:11:03 PM PDT 24
Finished May 21 01:11:15 PM PDT 24
Peak memory 205416 kb
Host smart-35f1fba5-4d81-4fe5-a9f7-42be4fcd9303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15589
72994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1558972994
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_eop_single_bit_handling.606069422
Short name T1541
Test name
Test status
Simulation time 8395299189 ps
CPU time 12.9 seconds
Started May 21 01:11:04 PM PDT 24
Finished May 21 01:11:18 PM PDT 24
Peak memory 205312 kb
Host smart-5cae2ccb-36f5-4d88-8593-d52617b3019f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60606
9422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_eop_single_bit_handling.606069422
Directory /workspace/36.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.2098717786
Short name T357
Test name
Test status
Simulation time 8367176024 ps
CPU time 11.34 seconds
Started May 21 01:11:01 PM PDT 24
Finished May 21 01:11:14 PM PDT 24
Peak memory 205224 kb
Host smart-e6527dff-76f5-4197-94d2-9b7b54a213d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20987
17786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.2098717786
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.2827495287
Short name T1014
Test name
Test status
Simulation time 8378484496 ps
CPU time 11.09 seconds
Started May 21 01:11:01 PM PDT 24
Finished May 21 01:11:14 PM PDT 24
Peak memory 205372 kb
Host smart-8036a6ed-2157-47ec-9a0e-73c30962281f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28274
95287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.2827495287
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.954307883
Short name T1056
Test name
Test status
Simulation time 19685421685 ps
CPU time 36.99 seconds
Started May 21 01:11:00 PM PDT 24
Finished May 21 01:11:38 PM PDT 24
Peak memory 205424 kb
Host smart-80f17693-6d24-45d0-b15f-1e61ef27f9a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95430
7883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.954307883
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3455518992
Short name T1484
Test name
Test status
Simulation time 8419537162 ps
CPU time 10.59 seconds
Started May 21 01:11:05 PM PDT 24
Finished May 21 01:11:18 PM PDT 24
Peak memory 205316 kb
Host smart-936e4130-2874-4529-a6fd-5f91078bd0e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34555
18992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3455518992
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1260355380
Short name T1642
Test name
Test status
Simulation time 8418215628 ps
CPU time 11.69 seconds
Started May 21 01:11:04 PM PDT 24
Finished May 21 01:11:17 PM PDT 24
Peak memory 205444 kb
Host smart-c1115036-fb60-44d2-8b04-8da60ac4623e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12603
55380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1260355380
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.2007437353
Short name T1671
Test name
Test status
Simulation time 8395933875 ps
CPU time 11.47 seconds
Started May 21 01:11:05 PM PDT 24
Finished May 21 01:11:19 PM PDT 24
Peak memory 205352 kb
Host smart-580747dd-6209-40a8-8ed1-97dd39e50426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20074
37353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.2007437353
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.3875128213
Short name T534
Test name
Test status
Simulation time 8370586557 ps
CPU time 11.32 seconds
Started May 21 01:11:04 PM PDT 24
Finished May 21 01:11:17 PM PDT 24
Peak memory 205356 kb
Host smart-ba6cb9fa-b261-47bd-a19e-aad0a42a3a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38751
28213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.3875128213
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.208611795
Short name T67
Test name
Test status
Simulation time 8370971401 ps
CPU time 11.96 seconds
Started May 21 01:11:01 PM PDT 24
Finished May 21 01:11:15 PM PDT 24
Peak memory 205364 kb
Host smart-b1bf00b5-030b-43d8-bdc2-70e4fc787382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20861
1795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.208611795
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3228838088
Short name T686
Test name
Test status
Simulation time 8383170149 ps
CPU time 13.31 seconds
Started May 21 01:11:02 PM PDT 24
Finished May 21 01:11:17 PM PDT 24
Peak memory 205340 kb
Host smart-5d985065-bb12-4a6a-85c9-e42416b295cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32288
38088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3228838088
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.3045905846
Short name T158
Test name
Test status
Simulation time 8464948588 ps
CPU time 13.55 seconds
Started May 21 01:10:56 PM PDT 24
Finished May 21 01:11:12 PM PDT 24
Peak memory 205440 kb
Host smart-2c33123c-8aef-45e4-9d44-2dbc9195b3ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30459
05846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.3045905846
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.3635315419
Short name T781
Test name
Test status
Simulation time 8419323717 ps
CPU time 12.51 seconds
Started May 21 01:11:03 PM PDT 24
Finished May 21 01:11:17 PM PDT 24
Peak memory 205272 kb
Host smart-dc71604d-001b-40f7-abe7-584f21bfb088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36353
15419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.3635315419
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.397381680
Short name T1446
Test name
Test status
Simulation time 8409712729 ps
CPU time 14.53 seconds
Started May 21 01:11:03 PM PDT 24
Finished May 21 01:11:18 PM PDT 24
Peak memory 205392 kb
Host smart-d9ef1277-9217-415b-8c53-a25670389564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39738
1680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.397381680
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.413451021
Short name T814
Test name
Test status
Simulation time 8485091304 ps
CPU time 12.68 seconds
Started May 21 01:11:10 PM PDT 24
Finished May 21 01:11:25 PM PDT 24
Peak memory 204988 kb
Host smart-ca818594-c5bf-47d2-941f-cfdb6aa27726
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=413451021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.413451021
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.2521299545
Short name T287
Test name
Test status
Simulation time 8384910817 ps
CPU time 11.69 seconds
Started May 21 01:11:07 PM PDT 24
Finished May 21 01:11:21 PM PDT 24
Peak memory 205356 kb
Host smart-1f2c4bed-0b12-4e70-811e-5aa8791ebd27
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2521299545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.2521299545
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.332680278
Short name T909
Test name
Test status
Simulation time 8390667078 ps
CPU time 12.83 seconds
Started May 21 01:11:12 PM PDT 24
Finished May 21 01:11:26 PM PDT 24
Peak memory 205408 kb
Host smart-8eb4cab0-81e0-4ca9-b399-ceadcb66e3b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33268
0278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.332680278
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.1408565334
Short name T562
Test name
Test status
Simulation time 8386498062 ps
CPU time 11.7 seconds
Started May 21 01:11:01 PM PDT 24
Finished May 21 01:11:14 PM PDT 24
Peak memory 205268 kb
Host smart-26db89e7-f186-438e-8c56-a0790605c358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14085
65334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.1408565334
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.600644738
Short name T1562
Test name
Test status
Simulation time 8724518944 ps
CPU time 12.4 seconds
Started May 21 01:11:04 PM PDT 24
Finished May 21 01:11:18 PM PDT 24
Peak memory 205424 kb
Host smart-43b0538e-d136-497f-bc2f-42d086c7108d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60064
4738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.600644738
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.3485534702
Short name T8
Test name
Test status
Simulation time 8376785256 ps
CPU time 13.72 seconds
Started May 21 01:11:09 PM PDT 24
Finished May 21 01:11:26 PM PDT 24
Peak memory 205288 kb
Host smart-f393d39b-c53f-4055-a356-81bc13099fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34855
34702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.3485534702
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.155697431
Short name T843
Test name
Test status
Simulation time 8395461345 ps
CPU time 11.87 seconds
Started May 21 01:11:07 PM PDT 24
Finished May 21 01:11:21 PM PDT 24
Peak memory 205336 kb
Host smart-f1583264-b053-4d10-a799-1e84574728a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15569
7431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.155697431
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.292703310
Short name T468
Test name
Test status
Simulation time 9216600210 ps
CPU time 16.33 seconds
Started May 21 01:11:02 PM PDT 24
Finished May 21 01:11:19 PM PDT 24
Peak memory 205304 kb
Host smart-1e354a73-5cf5-4d7c-a0a9-01012aac66b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29270
3310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.292703310
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.233005521
Short name T65
Test name
Test status
Simulation time 8404302733 ps
CPU time 11.58 seconds
Started May 21 01:11:08 PM PDT 24
Finished May 21 01:11:22 PM PDT 24
Peak memory 205368 kb
Host smart-4bf78390-bd9d-4d5d-86a3-622cda09b1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23300
5521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.233005521
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.1258546630
Short name T355
Test name
Test status
Simulation time 8424262278 ps
CPU time 12.98 seconds
Started May 21 01:11:09 PM PDT 24
Finished May 21 01:11:24 PM PDT 24
Peak memory 205348 kb
Host smart-a292823d-6131-4d62-b7a7-601bdb72b79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12585
46630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.1258546630
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.2895145680
Short name T787
Test name
Test status
Simulation time 8443669385 ps
CPU time 11.46 seconds
Started May 21 01:11:17 PM PDT 24
Finished May 21 01:11:30 PM PDT 24
Peak memory 205276 kb
Host smart-8fd32b5a-fa1f-4423-9440-8ac5610150aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28951
45680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.2895145680
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3087392622
Short name T546
Test name
Test status
Simulation time 8440775144 ps
CPU time 11.74 seconds
Started May 21 01:11:12 PM PDT 24
Finished May 21 01:11:25 PM PDT 24
Peak memory 205336 kb
Host smart-09e4754a-e2b0-4356-bfc7-9cc847af1db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30873
92622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3087392622
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.3946068408
Short name T368
Test name
Test status
Simulation time 11588445734 ps
CPU time 18.1 seconds
Started May 21 01:11:09 PM PDT 24
Finished May 21 01:11:29 PM PDT 24
Peak memory 205428 kb
Host smart-b2671323-f45c-49eb-b26b-e98f76e12025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39460
68408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.3946068408
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1312902240
Short name T554
Test name
Test status
Simulation time 8417017003 ps
CPU time 12.52 seconds
Started May 21 01:11:08 PM PDT 24
Finished May 21 01:11:23 PM PDT 24
Peak memory 205276 kb
Host smart-6db98b2c-dbc7-4bda-a112-fabbb34156ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13129
02240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1312902240
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.2243692303
Short name T1637
Test name
Test status
Simulation time 8371751460 ps
CPU time 11.05 seconds
Started May 21 01:11:10 PM PDT 24
Finished May 21 01:11:23 PM PDT 24
Peak memory 205380 kb
Host smart-bdb0952d-d518-4346-8bc4-70e4201ea9e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22436
92303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.2243692303
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.1235317778
Short name T1526
Test name
Test status
Simulation time 8429997053 ps
CPU time 11.5 seconds
Started May 21 01:11:10 PM PDT 24
Finished May 21 01:11:24 PM PDT 24
Peak memory 205328 kb
Host smart-54579b92-fa62-4fab-9871-f85f128e6a96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12353
17778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.1235317778
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.2841326267
Short name T104
Test name
Test status
Simulation time 8414587220 ps
CPU time 13 seconds
Started May 21 01:11:07 PM PDT 24
Finished May 21 01:11:22 PM PDT 24
Peak memory 205408 kb
Host smart-ea31f78a-6c8e-471e-b35c-599b45626071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28413
26267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.2841326267
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.3993537464
Short name T1388
Test name
Test status
Simulation time 8397920373 ps
CPU time 12.04 seconds
Started May 21 01:11:10 PM PDT 24
Finished May 21 01:11:24 PM PDT 24
Peak memory 205300 kb
Host smart-730c4b53-d4ca-4bed-8c56-a6db3ebdc625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39935
37464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3993537464
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.1471670533
Short name T1202
Test name
Test status
Simulation time 8416832327 ps
CPU time 12.71 seconds
Started May 21 01:11:09 PM PDT 24
Finished May 21 01:11:24 PM PDT 24
Peak memory 205396 kb
Host smart-15e02ba8-798f-448b-b265-07add49707ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14716
70533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.1471670533
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.4182786166
Short name T514
Test name
Test status
Simulation time 8403505158 ps
CPU time 12.88 seconds
Started May 21 01:11:08 PM PDT 24
Finished May 21 01:11:23 PM PDT 24
Peak memory 205388 kb
Host smart-34a64c3d-f7c8-4e57-8a7a-b1d9b1982f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41827
86166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.4182786166
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_eop_single_bit_handling.3521910681
Short name T903
Test name
Test status
Simulation time 8410165179 ps
CPU time 11.01 seconds
Started May 21 01:11:10 PM PDT 24
Finished May 21 01:11:23 PM PDT 24
Peak memory 204852 kb
Host smart-f315effd-17a7-450c-8537-c33c3817cd1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35219
10681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_eop_single_bit_handling.3521910681
Directory /workspace/37.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3097624521
Short name T765
Test name
Test status
Simulation time 8376083554 ps
CPU time 12.1 seconds
Started May 21 01:11:08 PM PDT 24
Finished May 21 01:11:22 PM PDT 24
Peak memory 205412 kb
Host smart-8664d2ea-b3f6-418e-b79a-ecda68aab95d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30976
24521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3097624521
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.2456217466
Short name T12
Test name
Test status
Simulation time 8364874989 ps
CPU time 13.89 seconds
Started May 21 01:11:08 PM PDT 24
Finished May 21 01:11:24 PM PDT 24
Peak memory 205304 kb
Host smart-567f7a0a-4384-41e8-b4da-a98d5310265f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24562
17466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.2456217466
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3009750256
Short name T667
Test name
Test status
Simulation time 8406134829 ps
CPU time 13.58 seconds
Started May 21 01:11:18 PM PDT 24
Finished May 21 01:11:33 PM PDT 24
Peak memory 205308 kb
Host smart-72654ac4-bab2-4974-a5ef-fcd260bc1bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30097
50256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3009750256
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.3019616091
Short name T724
Test name
Test status
Simulation time 8466419415 ps
CPU time 11.46 seconds
Started May 21 01:11:17 PM PDT 24
Finished May 21 01:11:30 PM PDT 24
Peak memory 205308 kb
Host smart-c754aca1-2186-4761-a011-d83de63461c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30196
16091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.3019616091
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.586051061
Short name T808
Test name
Test status
Simulation time 8423217625 ps
CPU time 12.21 seconds
Started May 21 01:11:10 PM PDT 24
Finished May 21 01:11:24 PM PDT 24
Peak memory 205248 kb
Host smart-a34e7404-75a0-4946-a097-545d4d06e3dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58605
1061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.586051061
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.4181667942
Short name T639
Test name
Test status
Simulation time 8367181722 ps
CPU time 10.44 seconds
Started May 21 01:11:09 PM PDT 24
Finished May 21 01:11:21 PM PDT 24
Peak memory 205344 kb
Host smart-6e026e52-de26-4e53-aa12-fa2d00744a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41816
67942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.4181667942
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.2901347576
Short name T1174
Test name
Test status
Simulation time 8379764909 ps
CPU time 12.16 seconds
Started May 21 01:11:17 PM PDT 24
Finished May 21 01:11:31 PM PDT 24
Peak memory 205276 kb
Host smart-abb14d1a-5629-4e03-b322-f62bcc5593da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29013
47576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2901347576
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2075584783
Short name T1166
Test name
Test status
Simulation time 8377940187 ps
CPU time 10.7 seconds
Started May 21 01:11:10 PM PDT 24
Finished May 21 01:11:23 PM PDT 24
Peak memory 205396 kb
Host smart-0725f62f-f61e-4389-a958-1c38ab607fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20755
84783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2075584783
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.1263954732
Short name T1069
Test name
Test status
Simulation time 8473564532 ps
CPU time 12.65 seconds
Started May 21 01:11:03 PM PDT 24
Finished May 21 01:11:17 PM PDT 24
Peak memory 205376 kb
Host smart-de8e3095-f840-4cdc-ae77-8f7966bc1af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12639
54732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.1263954732
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.2327293374
Short name T408
Test name
Test status
Simulation time 8429614678 ps
CPU time 12.05 seconds
Started May 21 01:11:09 PM PDT 24
Finished May 21 01:11:23 PM PDT 24
Peak memory 205380 kb
Host smart-bd919e4c-ca58-444c-8880-3ccd8416fcbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23272
93374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.2327293374
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.1515594011
Short name T1594
Test name
Test status
Simulation time 8390868100 ps
CPU time 11.7 seconds
Started May 21 01:11:09 PM PDT 24
Finished May 21 01:11:23 PM PDT 24
Peak memory 205300 kb
Host smart-6627e332-644a-4080-ab00-6633f9502d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15155
94011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.1515594011
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.2247047431
Short name T750
Test name
Test status
Simulation time 8466836889 ps
CPU time 13.58 seconds
Started May 21 01:11:28 PM PDT 24
Finished May 21 01:11:44 PM PDT 24
Peak memory 205320 kb
Host smart-95c953d2-37a8-409d-bb8d-0cceb12a903d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2247047431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.2247047431
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.47553520
Short name T1343
Test name
Test status
Simulation time 8381649221 ps
CPU time 12.66 seconds
Started May 21 01:11:20 PM PDT 24
Finished May 21 01:11:34 PM PDT 24
Peak memory 205320 kb
Host smart-2d6db22d-e4dc-4ba5-aed2-51b45f45eaba
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=47553520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.47553520
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.1880727718
Short name T1586
Test name
Test status
Simulation time 8418508869 ps
CPU time 11.81 seconds
Started May 21 01:11:21 PM PDT 24
Finished May 21 01:11:34 PM PDT 24
Peak memory 205296 kb
Host smart-a20e7bab-7933-4836-bce4-f80dd0019a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18807
27718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.1880727718
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3921942762
Short name T872
Test name
Test status
Simulation time 8381828685 ps
CPU time 13.77 seconds
Started May 21 01:11:13 PM PDT 24
Finished May 21 01:11:29 PM PDT 24
Peak memory 205260 kb
Host smart-d609d9a3-0f3c-48ad-8a2a-8dda58d25290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39219
42762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3921942762
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.1311617397
Short name T1729
Test name
Test status
Simulation time 8387910130 ps
CPU time 11.69 seconds
Started May 21 01:11:15 PM PDT 24
Finished May 21 01:11:29 PM PDT 24
Peak memory 205240 kb
Host smart-653bca99-d942-4000-a943-0c13198a2a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13116
17397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.1311617397
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.1978321465
Short name T922
Test name
Test status
Simulation time 8404408311 ps
CPU time 11.71 seconds
Started May 21 01:11:13 PM PDT 24
Finished May 21 01:11:27 PM PDT 24
Peak memory 205372 kb
Host smart-004e49ff-087d-4a3d-9b00-bf18656bb361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19783
21465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.1978321465
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.3111279277
Short name T1028
Test name
Test status
Simulation time 9233708904 ps
CPU time 13.78 seconds
Started May 21 01:11:17 PM PDT 24
Finished May 21 01:11:33 PM PDT 24
Peak memory 205236 kb
Host smart-dbde4c3b-2851-4388-afb2-f74953884ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31112
79277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.3111279277
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1957064218
Short name T1465
Test name
Test status
Simulation time 8622218497 ps
CPU time 14.24 seconds
Started May 21 01:11:14 PM PDT 24
Finished May 21 01:11:31 PM PDT 24
Peak memory 205320 kb
Host smart-b9d408ac-54a8-48ca-b011-21f5c6939a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19570
64218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1957064218
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.1737492564
Short name T617
Test name
Test status
Simulation time 8442160688 ps
CPU time 11.52 seconds
Started May 21 01:11:23 PM PDT 24
Finished May 21 01:11:36 PM PDT 24
Peak memory 205404 kb
Host smart-ea8fb035-f485-49a8-92d3-35a169a149a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17374
92564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.1737492564
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.3366169742
Short name T459
Test name
Test status
Simulation time 8367806291 ps
CPU time 12.43 seconds
Started May 21 01:11:20 PM PDT 24
Finished May 21 01:11:34 PM PDT 24
Peak memory 205296 kb
Host smart-5b62d1b2-7159-4620-82ff-f65bea323e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33661
69742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3366169742
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.2956343649
Short name T26
Test name
Test status
Simulation time 8399715673 ps
CPU time 12.24 seconds
Started May 21 01:11:18 PM PDT 24
Finished May 21 01:11:31 PM PDT 24
Peak memory 205328 kb
Host smart-34311fa3-6333-428d-9d47-611cebff58c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29563
43649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.2956343649
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.3449197049
Short name T399
Test name
Test status
Simulation time 11560084852 ps
CPU time 14.8 seconds
Started May 21 01:11:16 PM PDT 24
Finished May 21 01:11:33 PM PDT 24
Peak memory 205304 kb
Host smart-5078a893-49f2-4ea9-8869-1fc148aa8ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34491
97049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.3449197049
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3181989399
Short name T907
Test name
Test status
Simulation time 8416430499 ps
CPU time 11.62 seconds
Started May 21 01:11:14 PM PDT 24
Finished May 21 01:11:28 PM PDT 24
Peak memory 205432 kb
Host smart-5d76f112-c27e-442d-8df1-ab2c6c94d2c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31819
89399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3181989399
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3518086710
Short name T1629
Test name
Test status
Simulation time 8389685294 ps
CPU time 11.32 seconds
Started May 21 01:11:18 PM PDT 24
Finished May 21 01:11:31 PM PDT 24
Peak memory 205468 kb
Host smart-4123a6a9-fec0-4c83-b5de-c72b161eb52c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35180
86710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3518086710
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.860005154
Short name T1689
Test name
Test status
Simulation time 8456469447 ps
CPU time 11.2 seconds
Started May 21 01:11:14 PM PDT 24
Finished May 21 01:11:28 PM PDT 24
Peak memory 205428 kb
Host smart-af67c929-1e6e-495a-a040-7af33c1e34aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86000
5154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.860005154
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.886902936
Short name T1433
Test name
Test status
Simulation time 8422176919 ps
CPU time 11.57 seconds
Started May 21 01:11:18 PM PDT 24
Finished May 21 01:11:31 PM PDT 24
Peak memory 205332 kb
Host smart-96454bb6-58c3-4b28-be9e-9642f3c75c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88690
2936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.886902936
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2500157357
Short name T106
Test name
Test status
Simulation time 8404324252 ps
CPU time 13.09 seconds
Started May 21 01:11:17 PM PDT 24
Finished May 21 01:11:32 PM PDT 24
Peak memory 205304 kb
Host smart-ea166e60-3215-473d-98c6-74c049604c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25001
57357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2500157357
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.171252997
Short name T899
Test name
Test status
Simulation time 8407918896 ps
CPU time 11.59 seconds
Started May 21 01:11:15 PM PDT 24
Finished May 21 01:11:29 PM PDT 24
Peak memory 205332 kb
Host smart-e5950940-5256-4424-b057-3391fe32e4f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17125
2997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.171252997
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.4007247443
Short name T958
Test name
Test status
Simulation time 8378580381 ps
CPU time 10.93 seconds
Started May 21 01:11:20 PM PDT 24
Finished May 21 01:11:33 PM PDT 24
Peak memory 205380 kb
Host smart-adc3ab65-9dfa-4242-8bc9-1b1417b3bf01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40072
47443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.4007247443
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_eop_single_bit_handling.820940460
Short name T940
Test name
Test status
Simulation time 8399914130 ps
CPU time 12.27 seconds
Started May 21 01:11:21 PM PDT 24
Finished May 21 01:11:34 PM PDT 24
Peak memory 205380 kb
Host smart-5baf6eaf-1d84-44d0-9a37-12ea196287ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82094
0460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_eop_single_bit_handling.820940460
Directory /workspace/38.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.2245699000
Short name T1204
Test name
Test status
Simulation time 8377486982 ps
CPU time 11.98 seconds
Started May 21 01:11:20 PM PDT 24
Finished May 21 01:11:33 PM PDT 24
Peak memory 205352 kb
Host smart-d116cd37-81d6-4cff-aaef-02f232e545af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22456
99000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.2245699000
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.2824229422
Short name T1135
Test name
Test status
Simulation time 8369769510 ps
CPU time 14.12 seconds
Started May 21 01:11:18 PM PDT 24
Finished May 21 01:11:34 PM PDT 24
Peak memory 205264 kb
Host smart-dd107066-7393-448a-82c4-8afb362be4ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28242
29422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.2824229422
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.3087257201
Short name T1557
Test name
Test status
Simulation time 8402242247 ps
CPU time 11.69 seconds
Started May 21 01:11:12 PM PDT 24
Finished May 21 01:11:25 PM PDT 24
Peak memory 205380 kb
Host smart-3a4e8a49-298d-41bf-96b3-7caccfdd18cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30872
57201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3087257201
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.2371242789
Short name T568
Test name
Test status
Simulation time 8467586011 ps
CPU time 12.11 seconds
Started May 21 01:11:17 PM PDT 24
Finished May 21 01:11:31 PM PDT 24
Peak memory 205236 kb
Host smart-9b9961dd-4117-48ea-9247-b4edae1d3185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23712
42789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.2371242789
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.1680556333
Short name T1105
Test name
Test status
Simulation time 8383569491 ps
CPU time 11.81 seconds
Started May 21 01:11:27 PM PDT 24
Finished May 21 01:11:41 PM PDT 24
Peak memory 205352 kb
Host smart-6920a64c-0fe0-4f9e-87d0-642e3401deb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16805
56333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.1680556333
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.1708341814
Short name T1252
Test name
Test status
Simulation time 8374833803 ps
CPU time 11.38 seconds
Started May 21 01:11:19 PM PDT 24
Finished May 21 01:11:32 PM PDT 24
Peak memory 205368 kb
Host smart-720c1550-a753-4c38-b330-ab65a29bb879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17083
41814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.1708341814
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3893339462
Short name T1459
Test name
Test status
Simulation time 8379107235 ps
CPU time 11.48 seconds
Started May 21 01:11:27 PM PDT 24
Finished May 21 01:11:41 PM PDT 24
Peak memory 205316 kb
Host smart-74003820-02b9-4ff6-ad69-754c46ee01a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38933
39462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3893339462
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.4103529143
Short name T1580
Test name
Test status
Simulation time 8423120248 ps
CPU time 13.59 seconds
Started May 21 01:11:22 PM PDT 24
Finished May 21 01:11:37 PM PDT 24
Peak memory 205432 kb
Host smart-6f6bd575-f1c8-42ff-9a00-0d9dc2fbb961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41035
29143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.4103529143
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.2793070411
Short name T161
Test name
Test status
Simulation time 8412893427 ps
CPU time 11.06 seconds
Started May 21 01:11:14 PM PDT 24
Finished May 21 01:11:27 PM PDT 24
Peak memory 205396 kb
Host smart-20e7a7fa-b4ca-4e84-8be9-8056a3092008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27930
70411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.2793070411
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.849653073
Short name T452
Test name
Test status
Simulation time 8396203855 ps
CPU time 13.1 seconds
Started May 21 01:11:21 PM PDT 24
Finished May 21 01:11:35 PM PDT 24
Peak memory 205380 kb
Host smart-ead9723d-1579-4979-91af-72f918b27533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84965
3073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.849653073
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.3777560411
Short name T544
Test name
Test status
Simulation time 8379433057 ps
CPU time 11.31 seconds
Started May 21 01:11:21 PM PDT 24
Finished May 21 01:11:33 PM PDT 24
Peak memory 205348 kb
Host smart-00af9c2b-49ac-418c-8a9c-787ba4415d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37775
60411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.3777560411
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.1367587263
Short name T917
Test name
Test status
Simulation time 8470326742 ps
CPU time 11.01 seconds
Started May 21 01:11:28 PM PDT 24
Finished May 21 01:11:41 PM PDT 24
Peak memory 205356 kb
Host smart-9c39a758-f7fa-44e4-83ed-b905801d99a5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1367587263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.1367587263
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.1471327719
Short name T711
Test name
Test status
Simulation time 8381450907 ps
CPU time 10.94 seconds
Started May 21 01:11:28 PM PDT 24
Finished May 21 01:11:41 PM PDT 24
Peak memory 205344 kb
Host smart-5b7d29e8-6765-4f33-9220-34ed35cd3178
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1471327719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.1471327719
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.1398005531
Short name T807
Test name
Test status
Simulation time 8462274262 ps
CPU time 13.84 seconds
Started May 21 01:11:27 PM PDT 24
Finished May 21 01:11:43 PM PDT 24
Peak memory 205252 kb
Host smart-5246ef8b-7f92-450e-806b-138770e8ab03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13980
05531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.1398005531
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.3072911853
Short name T281
Test name
Test status
Simulation time 8374341509 ps
CPU time 12.85 seconds
Started May 21 01:11:20 PM PDT 24
Finished May 21 01:11:34 PM PDT 24
Peak memory 205324 kb
Host smart-693b75bd-4962-4e0a-b044-d7a3bfc4ffd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30729
11853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3072911853
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.3734365076
Short name T1730
Test name
Test status
Simulation time 9137852000 ps
CPU time 13.59 seconds
Started May 21 01:11:20 PM PDT 24
Finished May 21 01:11:34 PM PDT 24
Peak memory 205372 kb
Host smart-235f2e37-7c3b-4157-ba9d-ca0ad8c07be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37343
65076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.3734365076
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.2475228521
Short name T1517
Test name
Test status
Simulation time 8370108462 ps
CPU time 12.2 seconds
Started May 21 01:11:28 PM PDT 24
Finished May 21 01:11:43 PM PDT 24
Peak memory 205312 kb
Host smart-7f031af8-b77f-4e83-860d-769e1346e8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24752
28521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.2475228521
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.366471512
Short name T1464
Test name
Test status
Simulation time 8387592064 ps
CPU time 11.87 seconds
Started May 21 01:11:19 PM PDT 24
Finished May 21 01:11:32 PM PDT 24
Peak memory 205336 kb
Host smart-40c5e33f-8469-4ea1-a2f8-182b2bd7578d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36647
1512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.366471512
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.2165857165
Short name T1061
Test name
Test status
Simulation time 9232810445 ps
CPU time 12.54 seconds
Started May 21 01:11:28 PM PDT 24
Finished May 21 01:11:43 PM PDT 24
Peak memory 205192 kb
Host smart-cbfd565d-f864-4230-a05e-49293897c302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21658
57165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.2165857165
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.2054536445
Short name T1054
Test name
Test status
Simulation time 8509279779 ps
CPU time 13.2 seconds
Started May 21 01:11:20 PM PDT 24
Finished May 21 01:11:34 PM PDT 24
Peak memory 205268 kb
Host smart-01afb272-9ed1-4efa-b315-24d1a745d8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20545
36445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.2054536445
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2929101463
Short name T1143
Test name
Test status
Simulation time 8441770259 ps
CPU time 12.82 seconds
Started May 21 01:11:27 PM PDT 24
Finished May 21 01:11:42 PM PDT 24
Peak memory 205348 kb
Host smart-8fbd11a7-b2ef-40b0-bc30-0be15b24b54d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29291
01463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2929101463
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.3274939964
Short name T543
Test name
Test status
Simulation time 8376386765 ps
CPU time 12.57 seconds
Started May 21 01:11:26 PM PDT 24
Finished May 21 01:11:39 PM PDT 24
Peak memory 205340 kb
Host smart-8fa9a2b6-d1b7-4867-9d30-f1eab1c5f20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32749
39964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.3274939964
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.946207633
Short name T1655
Test name
Test status
Simulation time 8401544288 ps
CPU time 14.36 seconds
Started May 21 01:11:20 PM PDT 24
Finished May 21 01:11:36 PM PDT 24
Peak memory 205424 kb
Host smart-5f43fe9b-ca9a-4d11-9d2e-31363986ef0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94620
7633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.946207633
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.4016703620
Short name T409
Test name
Test status
Simulation time 11572841493 ps
CPU time 17.42 seconds
Started May 21 01:11:23 PM PDT 24
Finished May 21 01:11:42 PM PDT 24
Peak memory 205400 kb
Host smart-49df1050-02b1-4eef-9298-cb2a11eb8c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40167
03620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.4016703620
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.570938007
Short name T1650
Test name
Test status
Simulation time 8415209877 ps
CPU time 11.24 seconds
Started May 21 01:11:27 PM PDT 24
Finished May 21 01:11:40 PM PDT 24
Peak memory 205424 kb
Host smart-14e4bb01-3f7d-4d47-ada3-8971ff22d9f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57093
8007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.570938007
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1038266271
Short name T328
Test name
Test status
Simulation time 8372874995 ps
CPU time 11.81 seconds
Started May 21 01:11:21 PM PDT 24
Finished May 21 01:11:34 PM PDT 24
Peak memory 205408 kb
Host smart-310bef4c-aeb8-4741-ac8f-1106a20954ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10382
66271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1038266271
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3219288944
Short name T815
Test name
Test status
Simulation time 8418997184 ps
CPU time 12.65 seconds
Started May 21 01:11:26 PM PDT 24
Finished May 21 01:11:40 PM PDT 24
Peak memory 205304 kb
Host smart-805424c6-3c07-449d-b60b-86aceac2dfbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32192
88944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3219288944
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.3014088046
Short name T102
Test name
Test status
Simulation time 8441774137 ps
CPU time 12.69 seconds
Started May 21 01:11:27 PM PDT 24
Finished May 21 01:11:42 PM PDT 24
Peak memory 205300 kb
Host smart-887f7115-e35e-4dc5-9580-faf63c069bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30140
88046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.3014088046
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.3102143779
Short name T740
Test name
Test status
Simulation time 8452047184 ps
CPU time 10.73 seconds
Started May 21 01:11:25 PM PDT 24
Finished May 21 01:11:36 PM PDT 24
Peak memory 205324 kb
Host smart-5ac9ff67-fcdf-4ead-8790-cc7e45e26663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31021
43779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.3102143779
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.2787941894
Short name T441
Test name
Test status
Simulation time 8376618497 ps
CPU time 13.7 seconds
Started May 21 01:11:28 PM PDT 24
Finished May 21 01:11:44 PM PDT 24
Peak memory 205424 kb
Host smart-932e151a-57f0-4b4b-8fa8-50099eb85fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27879
41894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.2787941894
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.4014611013
Short name T1566
Test name
Test status
Simulation time 8418814182 ps
CPU time 12.21 seconds
Started May 21 01:11:27 PM PDT 24
Finished May 21 01:11:41 PM PDT 24
Peak memory 205316 kb
Host smart-d475c926-b852-42da-9dc2-09828b2ff15e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40146
11013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.4014611013
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_eop_single_bit_handling.1341833162
Short name T1348
Test name
Test status
Simulation time 8411399354 ps
CPU time 12.48 seconds
Started May 21 01:11:28 PM PDT 24
Finished May 21 01:11:43 PM PDT 24
Peak memory 205384 kb
Host smart-6cf3c0ff-c7d3-4b26-9c82-c620f5f1a185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13418
33162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_eop_single_bit_handling.1341833162
Directory /workspace/39.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.3821566938
Short name T101
Test name
Test status
Simulation time 8387688019 ps
CPU time 12.94 seconds
Started May 21 01:11:29 PM PDT 24
Finished May 21 01:11:44 PM PDT 24
Peak memory 205324 kb
Host smart-9cb600c0-fc58-4c1e-ae29-65dd89888b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38215
66938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3821566938
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.2992297304
Short name T1680
Test name
Test status
Simulation time 8386402676 ps
CPU time 12.4 seconds
Started May 21 01:11:26 PM PDT 24
Finished May 21 01:11:39 PM PDT 24
Peak memory 205320 kb
Host smart-1899998c-7593-4f5c-8df0-66be59c0b26e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29922
97304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.2992297304
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.973002365
Short name T1661
Test name
Test status
Simulation time 28364775069 ps
CPU time 54.49 seconds
Started May 21 01:11:28 PM PDT 24
Finished May 21 01:12:25 PM PDT 24
Peak memory 205408 kb
Host smart-a4036c76-ad00-4ede-86e8-daf01f055aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97300
2365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.973002365
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.923026115
Short name T1024
Test name
Test status
Simulation time 8404382119 ps
CPU time 12.97 seconds
Started May 21 01:11:26 PM PDT 24
Finished May 21 01:11:41 PM PDT 24
Peak memory 205348 kb
Host smart-32953198-930f-4a5a-b21b-3fb273304290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92302
6115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.923026115
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1296020467
Short name T1060
Test name
Test status
Simulation time 8464299463 ps
CPU time 11.58 seconds
Started May 21 01:11:27 PM PDT 24
Finished May 21 01:11:41 PM PDT 24
Peak memory 205432 kb
Host smart-ffd74c2f-dfe1-425d-88f9-b5cbb3b7efaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12960
20467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1296020467
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.1934091405
Short name T376
Test name
Test status
Simulation time 8378387919 ps
CPU time 12.9 seconds
Started May 21 01:11:27 PM PDT 24
Finished May 21 01:11:41 PM PDT 24
Peak memory 205324 kb
Host smart-d7ef9498-76fa-4a45-8cb9-3f4c814e3cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19340
91405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.1934091405
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.2678913765
Short name T1353
Test name
Test status
Simulation time 8384428232 ps
CPU time 11.46 seconds
Started May 21 01:11:30 PM PDT 24
Finished May 21 01:11:43 PM PDT 24
Peak memory 205368 kb
Host smart-6f1acceb-b3e9-474a-9d1d-89098be1af01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26789
13765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.2678913765
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.478611927
Short name T760
Test name
Test status
Simulation time 8383223278 ps
CPU time 14.88 seconds
Started May 21 01:11:27 PM PDT 24
Finished May 21 01:11:43 PM PDT 24
Peak memory 205380 kb
Host smart-d858fd0d-1323-4368-92be-f1c573f76ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47861
1927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.478611927
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1692944300
Short name T532
Test name
Test status
Simulation time 8429831032 ps
CPU time 12.36 seconds
Started May 21 01:11:27 PM PDT 24
Finished May 21 01:11:42 PM PDT 24
Peak memory 205324 kb
Host smart-ac8ed9c6-b692-4f6d-b638-ab0ba54c994c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16929
44300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1692944300
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.882627680
Short name T678
Test name
Test status
Simulation time 8453755006 ps
CPU time 11.28 seconds
Started May 21 01:11:28 PM PDT 24
Finished May 21 01:11:41 PM PDT 24
Peak memory 205232 kb
Host smart-45dee829-2cbf-4559-ad16-ccddc40b066e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88262
7680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.882627680
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.4185891446
Short name T524
Test name
Test status
Simulation time 8430264987 ps
CPU time 12.71 seconds
Started May 21 01:11:28 PM PDT 24
Finished May 21 01:11:43 PM PDT 24
Peak memory 205364 kb
Host smart-cef3c0a6-516e-4929-b62c-ebcf88e87beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41858
91446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.4185891446
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.3211884080
Short name T785
Test name
Test status
Simulation time 8401571924 ps
CPU time 13.43 seconds
Started May 21 01:11:26 PM PDT 24
Finished May 21 01:11:42 PM PDT 24
Peak memory 205616 kb
Host smart-8fb50529-54bd-47de-a5b8-7770c3e47848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32118
84080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.3211884080
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.339947175
Short name T1596
Test name
Test status
Simulation time 8471816186 ps
CPU time 11.6 seconds
Started May 21 01:05:44 PM PDT 24
Finished May 21 01:05:57 PM PDT 24
Peak memory 205380 kb
Host smart-1aa2546d-e9d8-443e-a60d-647f8a7ed7d7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=339947175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.339947175
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.1697027806
Short name T1425
Test name
Test status
Simulation time 8388316684 ps
CPU time 12.08 seconds
Started May 21 01:05:41 PM PDT 24
Finished May 21 01:05:54 PM PDT 24
Peak memory 205408 kb
Host smart-82440932-5ca2-4732-8bd3-31987cd3d9e6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1697027806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.1697027806
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.1392721676
Short name T1154
Test name
Test status
Simulation time 8390695716 ps
CPU time 11.45 seconds
Started May 21 01:05:40 PM PDT 24
Finished May 21 01:05:52 PM PDT 24
Peak memory 205340 kb
Host smart-015fc8ee-1f83-4b77-be3e-fcf33732a731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13927
21676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.1392721676
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.278903041
Short name T465
Test name
Test status
Simulation time 8395216650 ps
CPU time 14.28 seconds
Started May 21 01:05:22 PM PDT 24
Finished May 21 01:05:37 PM PDT 24
Peak memory 205352 kb
Host smart-73cd902e-6ec7-494a-b453-4f3cc2c8692b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27890
3041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.278903041
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.1143527065
Short name T1276
Test name
Test status
Simulation time 8386540331 ps
CPU time 11.67 seconds
Started May 21 01:05:34 PM PDT 24
Finished May 21 01:05:46 PM PDT 24
Peak memory 205216 kb
Host smart-7ab543b3-6ae8-4551-bd20-202a2bcf0bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11435
27065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.1143527065
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.2956578081
Short name T400
Test name
Test status
Simulation time 8895883166 ps
CPU time 15.26 seconds
Started May 21 01:05:30 PM PDT 24
Finished May 21 01:05:46 PM PDT 24
Peak memory 205412 kb
Host smart-c08d0a90-a081-4f48-9cea-da8e44be7b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29565
78081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.2956578081
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.1241888434
Short name T491
Test name
Test status
Simulation time 8359774828 ps
CPU time 11.14 seconds
Started May 21 01:05:29 PM PDT 24
Finished May 21 01:05:41 PM PDT 24
Peak memory 205320 kb
Host smart-bb88a22d-d7ed-4d2c-b9ce-e89b62eec02b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12418
88434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.1241888434
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.1719428195
Short name T1693
Test name
Test status
Simulation time 8382432498 ps
CPU time 12.25 seconds
Started May 21 01:05:29 PM PDT 24
Finished May 21 01:05:42 PM PDT 24
Peak memory 205268 kb
Host smart-26b3049c-0381-4967-9ab9-485ab2efd30c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17194
28195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1719428195
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.4079189287
Short name T948
Test name
Test status
Simulation time 9065737698 ps
CPU time 12.49 seconds
Started May 21 01:05:27 PM PDT 24
Finished May 21 01:05:40 PM PDT 24
Peak memory 205312 kb
Host smart-25e137db-1ba0-437e-bc89-d24ba689f956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40791
89287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.4079189287
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.2619177292
Short name T111
Test name
Test status
Simulation time 8383478477 ps
CPU time 12.47 seconds
Started May 21 01:05:30 PM PDT 24
Finished May 21 01:05:44 PM PDT 24
Peak memory 205368 kb
Host smart-7525672d-e5c3-4913-a2fd-4deca09abfe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26191
77292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.2619177292
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.47208894
Short name T1158
Test name
Test status
Simulation time 8404731747 ps
CPU time 12.43 seconds
Started May 21 01:05:37 PM PDT 24
Finished May 21 01:05:50 PM PDT 24
Peak memory 205364 kb
Host smart-88000854-ea49-4868-ae82-6f42af9915c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47208
894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.47208894
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.2481693016
Short name T1617
Test name
Test status
Simulation time 8368844982 ps
CPU time 11.04 seconds
Started May 21 01:05:38 PM PDT 24
Finished May 21 01:05:50 PM PDT 24
Peak memory 205324 kb
Host smart-6a99e3da-3a4a-4afc-bbd1-d6550a443c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24816
93016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.2481693016
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.2671000225
Short name T1001
Test name
Test status
Simulation time 8387842520 ps
CPU time 12.96 seconds
Started May 21 01:05:30 PM PDT 24
Finished May 21 01:05:44 PM PDT 24
Peak memory 205440 kb
Host smart-9da0d620-8cd8-4d74-bdaf-5165bd04cd69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26710
00225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.2671000225
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.1082912463
Short name T723
Test name
Test status
Simulation time 8424852139 ps
CPU time 13.58 seconds
Started May 21 01:05:31 PM PDT 24
Finished May 21 01:05:45 PM PDT 24
Peak memory 205344 kb
Host smart-1fc9c70d-0723-4b33-ad64-c57e4473800d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10829
12463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.1082912463
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.3944004706
Short name T623
Test name
Test status
Simulation time 11566416860 ps
CPU time 13.84 seconds
Started May 21 01:05:30 PM PDT 24
Finished May 21 01:05:44 PM PDT 24
Peak memory 205328 kb
Host smart-c802b490-6dae-4d43-84fa-0f5205381479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39440
04706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.3944004706
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.3582815125
Short name T1239
Test name
Test status
Simulation time 8416708314 ps
CPU time 13.03 seconds
Started May 21 01:05:28 PM PDT 24
Finished May 21 01:05:41 PM PDT 24
Peak memory 205336 kb
Host smart-9956e80b-d318-4746-99c9-b85584df8129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35828
15125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.3582815125
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.900904781
Short name T1129
Test name
Test status
Simulation time 8393389125 ps
CPU time 13.24 seconds
Started May 21 01:05:29 PM PDT 24
Finished May 21 01:05:43 PM PDT 24
Peak memory 205344 kb
Host smart-f3c0dc56-3ce8-4e6d-a0bf-e32fc9781acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90090
4781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.900904781
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.1141604449
Short name T146
Test name
Test status
Simulation time 8431761602 ps
CPU time 11.38 seconds
Started May 21 01:05:29 PM PDT 24
Finished May 21 01:05:42 PM PDT 24
Peak memory 205368 kb
Host smart-adbd2faa-f63b-434c-82da-c3b79eadd9ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11416
04449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.1141604449
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.4247919740
Short name T1521
Test name
Test status
Simulation time 8428345336 ps
CPU time 13.86 seconds
Started May 21 01:05:32 PM PDT 24
Finished May 21 01:05:46 PM PDT 24
Peak memory 205560 kb
Host smart-66dd945a-00c7-4894-bd0a-435b65bf8a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42479
19740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.4247919740
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.542504807
Short name T1072
Test name
Test status
Simulation time 8390334033 ps
CPU time 12.14 seconds
Started May 21 01:05:31 PM PDT 24
Finished May 21 01:05:44 PM PDT 24
Peak memory 205568 kb
Host smart-f524e508-7bdb-4383-b146-b7c115cb29ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54250
4807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.542504807
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.1953160362
Short name T786
Test name
Test status
Simulation time 8401384707 ps
CPU time 13.09 seconds
Started May 21 01:05:30 PM PDT 24
Finished May 21 01:05:44 PM PDT 24
Peak memory 205324 kb
Host smart-4c1bbba3-098c-4a1b-b83c-4e231f6276ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19531
60362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.1953160362
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3403850066
Short name T193
Test name
Test status
Simulation time 8375538309 ps
CPU time 11.25 seconds
Started May 21 01:05:38 PM PDT 24
Finished May 21 01:05:49 PM PDT 24
Peak memory 205320 kb
Host smart-ae26b715-0b72-4445-8e6e-730382fef406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34038
50066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3403850066
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_eop_single_bit_handling.3018430292
Short name T1403
Test name
Test status
Simulation time 8393228426 ps
CPU time 11.14 seconds
Started May 21 01:05:40 PM PDT 24
Finished May 21 01:05:52 PM PDT 24
Peak memory 205412 kb
Host smart-10e1419e-4c61-4c46-a9e3-1918a36838a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30184
30292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_eop_single_bit_handling.3018430292
Directory /workspace/4.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.47777544
Short name T45
Test name
Test status
Simulation time 8370488536 ps
CPU time 10.86 seconds
Started May 21 01:05:36 PM PDT 24
Finished May 21 01:05:47 PM PDT 24
Peak memory 205348 kb
Host smart-30461596-17fe-4b39-8eda-473843093341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47777
544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.47777544
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.581798848
Short name T1324
Test name
Test status
Simulation time 8361714762 ps
CPU time 12.42 seconds
Started May 21 01:05:37 PM PDT 24
Finished May 21 01:05:50 PM PDT 24
Peak memory 205300 kb
Host smart-6ad83817-d7ef-4e96-a161-5441fefa418b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58179
8848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.581798848
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.1194143628
Short name T226
Test name
Test status
Simulation time 29284155367 ps
CPU time 56.02 seconds
Started May 21 01:05:30 PM PDT 24
Finished May 21 01:06:27 PM PDT 24
Peak memory 205408 kb
Host smart-5599ad15-7266-4e18-8412-1b38d17f4b10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11941
43628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.1194143628
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.1413544970
Short name T1528
Test name
Test status
Simulation time 8414439856 ps
CPU time 11.52 seconds
Started May 21 01:05:31 PM PDT 24
Finished May 21 01:05:43 PM PDT 24
Peak memory 205336 kb
Host smart-ee9fe6f0-1da2-41fc-8184-4d6b21b064fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14135
44970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.1413544970
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2739868734
Short name T635
Test name
Test status
Simulation time 8441690412 ps
CPU time 13.78 seconds
Started May 21 01:05:29 PM PDT 24
Finished May 21 01:05:43 PM PDT 24
Peak memory 205400 kb
Host smart-70f778c5-b205-4d33-8924-ce0abc5f59cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27398
68734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2739868734
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.3744907361
Short name T801
Test name
Test status
Simulation time 8373676887 ps
CPU time 11.58 seconds
Started May 21 01:05:38 PM PDT 24
Finished May 21 01:05:51 PM PDT 24
Peak memory 205404 kb
Host smart-378bd9f1-a0ff-4d5c-b406-031a7e1fef6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37449
07361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.3744907361
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.1220259755
Short name T1079
Test name
Test status
Simulation time 8359252843 ps
CPU time 13.34 seconds
Started May 21 01:05:39 PM PDT 24
Finished May 21 01:05:53 PM PDT 24
Peak memory 205376 kb
Host smart-e7ecc976-cde1-4e2c-9ce0-23804334eeff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12202
59755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.1220259755
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.3685079025
Short name T90
Test name
Test status
Simulation time 150158506 ps
CPU time 0.97 seconds
Started May 21 01:05:45 PM PDT 24
Finished May 21 01:05:47 PM PDT 24
Peak memory 221324 kb
Host smart-12c13b1a-fe6b-41eb-b08c-a5f863baf349
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3685079025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3685079025
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.3137712230
Short name T792
Test name
Test status
Simulation time 8383384886 ps
CPU time 15 seconds
Started May 21 01:05:38 PM PDT 24
Finished May 21 01:05:53 PM PDT 24
Peak memory 205240 kb
Host smart-4df2b6c9-7dd1-44aa-a20d-1b2cdce302c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31377
12230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.3137712230
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.719809005
Short name T595
Test name
Test status
Simulation time 8375399345 ps
CPU time 13.76 seconds
Started May 21 01:05:40 PM PDT 24
Finished May 21 01:05:54 PM PDT 24
Peak memory 205408 kb
Host smart-d81ba2db-905e-442e-8ac9-d2cc9266bbd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71980
9005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.719809005
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.2656853010
Short name T177
Test name
Test status
Simulation time 8506509933 ps
CPU time 15.14 seconds
Started May 21 01:05:21 PM PDT 24
Finished May 21 01:05:37 PM PDT 24
Peak memory 205340 kb
Host smart-9e907977-71bb-4e30-8e88-50046cc64921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26568
53010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2656853010
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.2152612689
Short name T1170
Test name
Test status
Simulation time 8377370168 ps
CPU time 12.19 seconds
Started May 21 01:05:36 PM PDT 24
Finished May 21 01:05:49 PM PDT 24
Peak memory 205332 kb
Host smart-b7ba0872-12ca-46b1-968e-c0fe2e7430a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21526
12689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.2152612689
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.2527796926
Short name T401
Test name
Test status
Simulation time 8422057821 ps
CPU time 13.28 seconds
Started May 21 01:05:37 PM PDT 24
Finished May 21 01:05:50 PM PDT 24
Peak memory 205280 kb
Host smart-0597d0b4-341f-4f2e-870e-3d6e0f699faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25277
96926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.2527796926
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.4110327720
Short name T861
Test name
Test status
Simulation time 8464901910 ps
CPU time 12.6 seconds
Started May 21 01:11:39 PM PDT 24
Finished May 21 01:11:53 PM PDT 24
Peak memory 205296 kb
Host smart-db9b4fe6-76cf-46e3-b3ce-290e0ed96d88
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4110327720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.4110327720
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.1294598448
Short name T547
Test name
Test status
Simulation time 8383938879 ps
CPU time 11.43 seconds
Started May 21 01:11:38 PM PDT 24
Finished May 21 01:11:50 PM PDT 24
Peak memory 205424 kb
Host smart-e3b51805-ff20-4f60-a726-54221ff1c2b5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1294598448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.1294598448
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.735549772
Short name T1512
Test name
Test status
Simulation time 8473264106 ps
CPU time 12.25 seconds
Started May 21 01:11:40 PM PDT 24
Finished May 21 01:11:53 PM PDT 24
Peak memory 205336 kb
Host smart-c1e8de27-3383-48f6-be6c-382b85481f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73554
9772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.735549772
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1102997184
Short name T1107
Test name
Test status
Simulation time 8417006495 ps
CPU time 11.36 seconds
Started May 21 01:11:27 PM PDT 24
Finished May 21 01:11:41 PM PDT 24
Peak memory 205364 kb
Host smart-b9c819b0-5e6c-474c-b9de-867612ccc49c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11029
97184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1102997184
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2268352756
Short name T717
Test name
Test status
Simulation time 9619901706 ps
CPU time 16.3 seconds
Started May 21 01:11:33 PM PDT 24
Finished May 21 01:11:50 PM PDT 24
Peak memory 205296 kb
Host smart-2c4dc5a6-b2dc-4c50-9951-eb6dc1d72f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22683
52756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2268352756
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.3277260753
Short name T1212
Test name
Test status
Simulation time 8400235432 ps
CPU time 11.75 seconds
Started May 21 01:11:33 PM PDT 24
Finished May 21 01:11:45 PM PDT 24
Peak memory 205348 kb
Host smart-970e00c1-a592-4c34-8ba0-3318fe0fbed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32772
60753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.3277260753
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.2917880678
Short name T1613
Test name
Test status
Simulation time 8378146835 ps
CPU time 12.29 seconds
Started May 21 01:11:32 PM PDT 24
Finished May 21 01:11:46 PM PDT 24
Peak memory 205396 kb
Host smart-fc1ecd00-e43b-47ab-b68e-152f02f4f14c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29178
80678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.2917880678
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.3115144354
Short name T154
Test name
Test status
Simulation time 8926174320 ps
CPU time 13.36 seconds
Started May 21 01:11:32 PM PDT 24
Finished May 21 01:11:46 PM PDT 24
Peak memory 205340 kb
Host smart-ff891cb3-78c0-4dd5-942f-ee5e4a78ed03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31151
44354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.3115144354
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.1674074459
Short name T719
Test name
Test status
Simulation time 8591021577 ps
CPU time 15.19 seconds
Started May 21 01:11:32 PM PDT 24
Finished May 21 01:11:48 PM PDT 24
Peak memory 205312 kb
Host smart-7fa3f44c-e765-49fe-b595-b5f6a0d54e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16740
74459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1674074459
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.1630694500
Short name T816
Test name
Test status
Simulation time 8462559383 ps
CPU time 12.56 seconds
Started May 21 01:11:38 PM PDT 24
Finished May 21 01:11:51 PM PDT 24
Peak memory 205404 kb
Host smart-3664f46b-1c10-4869-a02c-923873d76d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16306
94500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.1630694500
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.523362894
Short name T1256
Test name
Test status
Simulation time 8403337986 ps
CPU time 13.99 seconds
Started May 21 01:11:40 PM PDT 24
Finished May 21 01:11:55 PM PDT 24
Peak memory 205272 kb
Host smart-6df3c1fe-8d08-449b-9838-9b32408daade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52336
2894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.523362894
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.38896652
Short name T572
Test name
Test status
Simulation time 8392797414 ps
CPU time 11.84 seconds
Started May 21 01:11:34 PM PDT 24
Finished May 21 01:11:47 PM PDT 24
Peak memory 205392 kb
Host smart-efb5138b-e4cd-403c-9e25-dfb98f5f0bc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38896
652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.38896652
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.126884003
Short name T1120
Test name
Test status
Simulation time 11545319800 ps
CPU time 15.09 seconds
Started May 21 01:11:32 PM PDT 24
Finished May 21 01:11:48 PM PDT 24
Peak memory 205356 kb
Host smart-7d3f81f4-31b5-4699-9359-f8212c4e04f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12688
4003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.126884003
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.3484707471
Short name T1268
Test name
Test status
Simulation time 8427656440 ps
CPU time 14.28 seconds
Started May 21 01:11:33 PM PDT 24
Finished May 21 01:11:48 PM PDT 24
Peak memory 205332 kb
Host smart-aaf6e60c-90d9-4852-bf3d-6940043f0566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34847
07471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.3484707471
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2851144679
Short name T1428
Test name
Test status
Simulation time 8373397526 ps
CPU time 10.94 seconds
Started May 21 01:11:33 PM PDT 24
Finished May 21 01:11:45 PM PDT 24
Peak memory 205424 kb
Host smart-491e650f-fa9f-41a4-b324-4b045c5e973d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28511
44679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2851144679
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1451188096
Short name T1151
Test name
Test status
Simulation time 8444899207 ps
CPU time 12.22 seconds
Started May 21 01:11:32 PM PDT 24
Finished May 21 01:11:45 PM PDT 24
Peak memory 205368 kb
Host smart-f359c892-ce78-4d8f-9b75-ecea69a56327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14511
88096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1451188096
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.4001373089
Short name T625
Test name
Test status
Simulation time 8431382950 ps
CPU time 12.91 seconds
Started May 21 01:11:33 PM PDT 24
Finished May 21 01:11:47 PM PDT 24
Peak memory 205308 kb
Host smart-f2a41b91-baf0-4dd8-a087-d0650cb5a21c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40013
73089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.4001373089
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.3715081183
Short name T107
Test name
Test status
Simulation time 8412161407 ps
CPU time 11.94 seconds
Started May 21 01:11:34 PM PDT 24
Finished May 21 01:11:46 PM PDT 24
Peak memory 205336 kb
Host smart-a9152f5f-aa90-4805-a19f-c9a2f990d11b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37150
81183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.3715081183
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.585338726
Short name T601
Test name
Test status
Simulation time 8374927226 ps
CPU time 11.74 seconds
Started May 21 01:11:32 PM PDT 24
Finished May 21 01:11:45 PM PDT 24
Peak memory 205372 kb
Host smart-40606fc2-b103-4c6f-be21-3c5c29356745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58533
8726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.585338726
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.4196870043
Short name T51
Test name
Test status
Simulation time 8428403065 ps
CPU time 11.82 seconds
Started May 21 01:11:39 PM PDT 24
Finished May 21 01:11:51 PM PDT 24
Peak memory 205316 kb
Host smart-96d036fa-0501-4ede-887e-0ea13f485564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41968
70043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.4196870043
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_eop_single_bit_handling.3127768014
Short name T1501
Test name
Test status
Simulation time 8410571253 ps
CPU time 10.85 seconds
Started May 21 01:11:39 PM PDT 24
Finished May 21 01:11:50 PM PDT 24
Peak memory 205396 kb
Host smart-0a1cf096-9175-4d10-b068-1fd47c7bee19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31277
68014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_eop_single_bit_handling.3127768014
Directory /workspace/40.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.1623148495
Short name T653
Test name
Test status
Simulation time 8372567898 ps
CPU time 12.8 seconds
Started May 21 01:11:41 PM PDT 24
Finished May 21 01:11:56 PM PDT 24
Peak memory 205376 kb
Host smart-47589604-13d8-4c16-a81a-93add190a49e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16231
48495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.1623148495
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3432399457
Short name T393
Test name
Test status
Simulation time 8376795467 ps
CPU time 11.95 seconds
Started May 21 01:11:41 PM PDT 24
Finished May 21 01:11:54 PM PDT 24
Peak memory 205272 kb
Host smart-b54ce916-a323-41a7-9f6b-0dcb80079df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34323
99457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3432399457
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.3615178861
Short name T1558
Test name
Test status
Simulation time 25066456552 ps
CPU time 48.39 seconds
Started May 21 01:11:41 PM PDT 24
Finished May 21 01:12:31 PM PDT 24
Peak memory 205324 kb
Host smart-ef424896-3a8b-4af7-9e61-831812b4406e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36151
78861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.3615178861
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.4161769273
Short name T870
Test name
Test status
Simulation time 8453013191 ps
CPU time 12.22 seconds
Started May 21 01:11:39 PM PDT 24
Finished May 21 01:11:51 PM PDT 24
Peak memory 205420 kb
Host smart-9bfef967-4588-430c-b4d9-786c742af0ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41617
69273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.4161769273
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.2864665638
Short name T631
Test name
Test status
Simulation time 8441272382 ps
CPU time 13.33 seconds
Started May 21 01:11:38 PM PDT 24
Finished May 21 01:11:52 PM PDT 24
Peak memory 205368 kb
Host smart-35625d52-7182-41fe-bd00-c55bde906737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28646
65638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2864665638
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.4211019791
Short name T1389
Test name
Test status
Simulation time 8381456297 ps
CPU time 12.25 seconds
Started May 21 01:11:39 PM PDT 24
Finished May 21 01:11:52 PM PDT 24
Peak memory 205380 kb
Host smart-474ac58e-6989-48a6-bf8e-2812b568c732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42110
19791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.4211019791
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.2335842880
Short name T1027
Test name
Test status
Simulation time 8370955260 ps
CPU time 12.36 seconds
Started May 21 01:11:43 PM PDT 24
Finished May 21 01:11:56 PM PDT 24
Peak memory 205304 kb
Host smart-9f65a43f-5d05-4e8c-bb3c-b62e374a00fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23358
42880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.2335842880
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.1382028991
Short name T1654
Test name
Test status
Simulation time 8379697467 ps
CPU time 13.29 seconds
Started May 21 01:11:43 PM PDT 24
Finished May 21 01:11:57 PM PDT 24
Peak memory 205304 kb
Host smart-8e5c1fee-bf40-45ce-bb1d-d968e1469b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13820
28991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.1382028991
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.216283308
Short name T446
Test name
Test status
Simulation time 8437730704 ps
CPU time 11.37 seconds
Started May 21 01:11:39 PM PDT 24
Finished May 21 01:11:51 PM PDT 24
Peak memory 205216 kb
Host smart-44783981-6b82-471f-b87a-0ade18161ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21628
3308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.216283308
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2674673331
Short name T1038
Test name
Test status
Simulation time 8456270778 ps
CPU time 14.55 seconds
Started May 21 01:11:26 PM PDT 24
Finished May 21 01:11:42 PM PDT 24
Peak memory 205304 kb
Host smart-c77d63b2-9354-4205-9131-a42283a880df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26746
73331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2674673331
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.3724340466
Short name T1149
Test name
Test status
Simulation time 8405490648 ps
CPU time 12.16 seconds
Started May 21 01:11:43 PM PDT 24
Finished May 21 01:11:56 PM PDT 24
Peak memory 205412 kb
Host smart-18b6e007-cc7a-4caa-bb1b-fde28ef2800a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37243
40466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.3724340466
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.2825072988
Short name T984
Test name
Test status
Simulation time 8399496117 ps
CPU time 11.56 seconds
Started May 21 01:11:40 PM PDT 24
Finished May 21 01:11:53 PM PDT 24
Peak memory 205376 kb
Host smart-a960cbba-ff1d-4669-97c2-e48a483441f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28250
72988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.2825072988
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.3704359122
Short name T1633
Test name
Test status
Simulation time 8469715361 ps
CPU time 11.9 seconds
Started May 21 01:11:51 PM PDT 24
Finished May 21 01:12:04 PM PDT 24
Peak memory 205212 kb
Host smart-b5ae8055-d15f-4a28-9690-1a115acb5c1a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3704359122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.3704359122
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.2074297159
Short name T214
Test name
Test status
Simulation time 8378773903 ps
CPU time 12.26 seconds
Started May 21 01:11:49 PM PDT 24
Finished May 21 01:12:02 PM PDT 24
Peak memory 205268 kb
Host smart-72931f1f-c428-4ca7-bfc6-9cd45a8675ed
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2074297159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.2074297159
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.1995706645
Short name T852
Test name
Test status
Simulation time 8431327716 ps
CPU time 10.69 seconds
Started May 21 01:11:51 PM PDT 24
Finished May 21 01:12:03 PM PDT 24
Peak memory 205428 kb
Host smart-74c18829-f2b7-48be-a616-972618431cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19957
06645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.1995706645
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2883090251
Short name T302
Test name
Test status
Simulation time 8405946821 ps
CPU time 12.96 seconds
Started May 21 01:11:47 PM PDT 24
Finished May 21 01:12:01 PM PDT 24
Peak memory 205344 kb
Host smart-4fa54aff-f086-4608-b519-f5dbdc4d139f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28830
90251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2883090251
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.3166643880
Short name T1183
Test name
Test status
Simulation time 8702166677 ps
CPU time 13.33 seconds
Started May 21 01:11:45 PM PDT 24
Finished May 21 01:11:59 PM PDT 24
Peak memory 205340 kb
Host smart-9a2430ab-eb31-4d55-942a-725c4e41dd5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31666
43880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.3166643880
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.2141168071
Short name T1658
Test name
Test status
Simulation time 8370658384 ps
CPU time 11.67 seconds
Started May 21 01:11:49 PM PDT 24
Finished May 21 01:12:02 PM PDT 24
Peak memory 205312 kb
Host smart-6597238c-5f69-4a63-83c9-0db26971f3d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21411
68071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.2141168071
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.3527668203
Short name T782
Test name
Test status
Simulation time 8376447814 ps
CPU time 14.03 seconds
Started May 21 01:11:52 PM PDT 24
Finished May 21 01:12:08 PM PDT 24
Peak memory 205364 kb
Host smart-932b763b-fda1-4bce-aad6-0580d83f8f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35276
68203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3527668203
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.1647955115
Short name T873
Test name
Test status
Simulation time 9095127445 ps
CPU time 12.42 seconds
Started May 21 01:11:52 PM PDT 24
Finished May 21 01:12:07 PM PDT 24
Peak memory 205320 kb
Host smart-c7a572f8-0421-49c3-9a59-981cab3b59d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16479
55115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.1647955115
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.196694242
Short name T797
Test name
Test status
Simulation time 8442951119 ps
CPU time 11.65 seconds
Started May 21 01:11:53 PM PDT 24
Finished May 21 01:12:06 PM PDT 24
Peak memory 205212 kb
Host smart-64f7a8a8-8600-416b-8e38-1eeebd2f9ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19669
4242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.196694242
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.3589165207
Short name T1726
Test name
Test status
Simulation time 8540843142 ps
CPU time 11.57 seconds
Started May 21 01:11:54 PM PDT 24
Finished May 21 01:12:07 PM PDT 24
Peak memory 205380 kb
Host smart-212a22d5-3894-410c-8c93-c791fa096762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35891
65207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.3589165207
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.3978403796
Short name T305
Test name
Test status
Simulation time 8367609687 ps
CPU time 12.5 seconds
Started May 21 01:11:52 PM PDT 24
Finished May 21 01:12:07 PM PDT 24
Peak memory 205268 kb
Host smart-ec085536-5d6d-49a0-8436-e0a2fcb3b598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39784
03796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.3978403796
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.2878813543
Short name T397
Test name
Test status
Simulation time 8533287682 ps
CPU time 11.4 seconds
Started May 21 01:11:45 PM PDT 24
Finished May 21 01:11:57 PM PDT 24
Peak memory 205300 kb
Host smart-8a02521b-533e-4a39-ac10-4fdf5701003d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28788
13543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.2878813543
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.488356283
Short name T709
Test name
Test status
Simulation time 11531719556 ps
CPU time 14.75 seconds
Started May 21 01:11:44 PM PDT 24
Finished May 21 01:12:00 PM PDT 24
Peak memory 205388 kb
Host smart-6fc2ebfb-e906-49ac-84fe-bfa51d3a33d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48835
6283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.488356283
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.3522027401
Short name T1186
Test name
Test status
Simulation time 8418337818 ps
CPU time 11.72 seconds
Started May 21 01:11:46 PM PDT 24
Finished May 21 01:11:59 PM PDT 24
Peak memory 205384 kb
Host smart-f06dd018-17c2-49ec-a95e-ba2e2f55c85c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35220
27401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.3522027401
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.3997308973
Short name T1338
Test name
Test status
Simulation time 8402322431 ps
CPU time 11.63 seconds
Started May 21 01:11:53 PM PDT 24
Finished May 21 01:12:06 PM PDT 24
Peak memory 205320 kb
Host smart-da9e255a-c429-4030-807b-66b3a5341f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39973
08973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.3997308973
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.335181404
Short name T1611
Test name
Test status
Simulation time 8412115117 ps
CPU time 11.84 seconds
Started May 21 01:11:55 PM PDT 24
Finished May 21 01:12:08 PM PDT 24
Peak memory 205344 kb
Host smart-91fcbe12-dfd8-416b-bd03-aeb0336dbf17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33518
1404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.335181404
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.2592257236
Short name T771
Test name
Test status
Simulation time 8483074937 ps
CPU time 12.86 seconds
Started May 21 01:11:46 PM PDT 24
Finished May 21 01:12:00 PM PDT 24
Peak memory 205328 kb
Host smart-dc9897d7-589f-42a6-8f78-49f2e380c695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25922
57236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.2592257236
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.338127335
Short name T1201
Test name
Test status
Simulation time 8398315741 ps
CPU time 11.94 seconds
Started May 21 01:11:44 PM PDT 24
Finished May 21 01:11:56 PM PDT 24
Peak memory 205300 kb
Host smart-cbd6e1e2-cafe-45b7-9ca4-42c87ef71716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33812
7335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.338127335
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.505592859
Short name T1628
Test name
Test status
Simulation time 8379713768 ps
CPU time 11.2 seconds
Started May 21 01:11:46 PM PDT 24
Finished May 21 01:11:59 PM PDT 24
Peak memory 205320 kb
Host smart-e8d12371-cc3f-4409-8f91-bf580c129eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50559
2859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.505592859
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.2672755513
Short name T96
Test name
Test status
Simulation time 8390721371 ps
CPU time 11.9 seconds
Started May 21 01:11:49 PM PDT 24
Finished May 21 01:12:02 PM PDT 24
Peak memory 205344 kb
Host smart-d83b4f28-4cab-4c9f-99c9-1b8ee139e68c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26727
55513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2672755513
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_eop_single_bit_handling.2962658690
Short name T1708
Test name
Test status
Simulation time 8404952673 ps
CPU time 12.52 seconds
Started May 21 01:11:48 PM PDT 24
Finished May 21 01:12:02 PM PDT 24
Peak memory 205380 kb
Host smart-c5064b2f-26f2-4264-8b7e-55d687112ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29626
58690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_eop_single_bit_handling.2962658690
Directory /workspace/41.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.7367866
Short name T645
Test name
Test status
Simulation time 8366218161 ps
CPU time 12.4 seconds
Started May 21 01:11:48 PM PDT 24
Finished May 21 01:12:02 PM PDT 24
Peak memory 205356 kb
Host smart-195fa2ad-b214-4ae5-991f-7ee65ca5b9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73678
66 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.7367866
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.1806288072
Short name T705
Test name
Test status
Simulation time 8364307288 ps
CPU time 11.27 seconds
Started May 21 01:11:45 PM PDT 24
Finished May 21 01:11:58 PM PDT 24
Peak memory 205356 kb
Host smart-db50fbe6-4e67-4337-b4f9-0ccf0ddda424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18062
88072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.1806288072
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.2439825676
Short name T1699
Test name
Test status
Simulation time 18133676395 ps
CPU time 32.72 seconds
Started May 21 01:11:47 PM PDT 24
Finished May 21 01:12:21 PM PDT 24
Peak memory 205416 kb
Host smart-c87f3670-a2c4-4af2-9c3d-4f19f77730fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24398
25676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.2439825676
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.2308491946
Short name T1347
Test name
Test status
Simulation time 8388442662 ps
CPU time 13.21 seconds
Started May 21 01:11:46 PM PDT 24
Finished May 21 01:12:00 PM PDT 24
Peak memory 205320 kb
Host smart-bd1adce1-7bcc-43d6-9d3d-73b79dabffef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23084
91946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.2308491946
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3779699456
Short name T285
Test name
Test status
Simulation time 8410479873 ps
CPU time 11.97 seconds
Started May 21 01:11:47 PM PDT 24
Finished May 21 01:12:00 PM PDT 24
Peak memory 205324 kb
Host smart-11bec4c5-b2a6-4b31-8637-26cc7a55e1ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37796
99456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3779699456
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.1504869281
Short name T98
Test name
Test status
Simulation time 8406436122 ps
CPU time 11.77 seconds
Started May 21 01:11:52 PM PDT 24
Finished May 21 01:12:06 PM PDT 24
Peak memory 205384 kb
Host smart-4f5308ae-3dfb-488c-8725-2c2ad9d228c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15048
69281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.1504869281
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.3395771639
Short name T1488
Test name
Test status
Simulation time 8381409142 ps
CPU time 11.53 seconds
Started May 21 01:11:43 PM PDT 24
Finished May 21 01:11:55 PM PDT 24
Peak memory 205296 kb
Host smart-94664e93-35b9-4fa0-9079-2b57539e8a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33957
71639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.3395771639
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.1688556137
Short name T1041
Test name
Test status
Simulation time 8382642299 ps
CPU time 11.78 seconds
Started May 21 01:11:46 PM PDT 24
Finished May 21 01:11:59 PM PDT 24
Peak memory 205328 kb
Host smart-e54093e0-7c25-4cab-96cf-9aefd40b6ccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16885
56137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.1688556137
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.2980771934
Short name T538
Test name
Test status
Simulation time 8398463980 ps
CPU time 11.86 seconds
Started May 21 01:11:47 PM PDT 24
Finished May 21 01:12:00 PM PDT 24
Peak memory 205364 kb
Host smart-4db3e347-9851-48a9-82a2-218a725882c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29807
71934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.2980771934
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.241589194
Short name T463
Test name
Test status
Simulation time 8462003798 ps
CPU time 12.06 seconds
Started May 21 01:11:40 PM PDT 24
Finished May 21 01:11:54 PM PDT 24
Peak memory 205388 kb
Host smart-bbe60811-3914-46b1-8667-05a15c36b88e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24158
9194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.241589194
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2822335861
Short name T794
Test name
Test status
Simulation time 8391133020 ps
CPU time 13.6 seconds
Started May 21 01:11:48 PM PDT 24
Finished May 21 01:12:03 PM PDT 24
Peak memory 205384 kb
Host smart-641dcd60-c1ea-4414-a495-62bc2740e178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28223
35861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2822335861
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.1324292005
Short name T440
Test name
Test status
Simulation time 8413705842 ps
CPU time 13.78 seconds
Started May 21 01:11:47 PM PDT 24
Finished May 21 01:12:02 PM PDT 24
Peak memory 205312 kb
Host smart-41bfa616-54fd-4c78-9c63-d75dfb27dec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13242
92005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.1324292005
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.2208186046
Short name T982
Test name
Test status
Simulation time 8466368357 ps
CPU time 12.19 seconds
Started May 21 01:12:02 PM PDT 24
Finished May 21 01:12:16 PM PDT 24
Peak memory 205336 kb
Host smart-58e1354e-e6bf-47b3-8fed-d070d4da459d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2208186046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.2208186046
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.2471950226
Short name T902
Test name
Test status
Simulation time 8378913934 ps
CPU time 11.72 seconds
Started May 21 01:12:03 PM PDT 24
Finished May 21 01:12:16 PM PDT 24
Peak memory 205344 kb
Host smart-a2e09744-881c-41e1-92ca-1e899559124d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2471950226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.2471950226
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.3476594774
Short name T981
Test name
Test status
Simulation time 8453593010 ps
CPU time 11.53 seconds
Started May 21 01:11:59 PM PDT 24
Finished May 21 01:12:12 PM PDT 24
Peak memory 205304 kb
Host smart-a44162bb-8877-4a9f-bf99-8d57ea667e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34765
94774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.3476594774
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.3377466802
Short name T1703
Test name
Test status
Simulation time 8400828653 ps
CPU time 11.29 seconds
Started May 21 01:11:54 PM PDT 24
Finished May 21 01:12:07 PM PDT 24
Peak memory 205360 kb
Host smart-53817aae-ac66-4896-ae48-8f322ea8d5e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33774
66802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3377466802
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.3775198912
Short name T1511
Test name
Test status
Simulation time 8369620738 ps
CPU time 12.27 seconds
Started May 21 01:11:54 PM PDT 24
Finished May 21 01:12:08 PM PDT 24
Peak memory 205328 kb
Host smart-ad066d57-7085-480c-afd3-1e59fbf262ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37751
98912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.3775198912
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.399842936
Short name T195
Test name
Test status
Simulation time 8930702753 ps
CPU time 14 seconds
Started May 21 01:11:52 PM PDT 24
Finished May 21 01:12:07 PM PDT 24
Peak memory 205404 kb
Host smart-d9d9e939-d045-40f3-b8c5-b461186c0788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39984
2936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.399842936
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.2695122615
Short name T418
Test name
Test status
Simulation time 8377708588 ps
CPU time 11.48 seconds
Started May 21 01:11:53 PM PDT 24
Finished May 21 01:12:07 PM PDT 24
Peak memory 205344 kb
Host smart-8fff7393-259d-436c-8b96-667b78a2e3d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26951
22615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.2695122615
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.2842095583
Short name T564
Test name
Test status
Simulation time 8382588149 ps
CPU time 11.64 seconds
Started May 21 01:11:53 PM PDT 24
Finished May 21 01:12:07 PM PDT 24
Peak memory 205328 kb
Host smart-a508c622-1ea2-451d-b00a-9a9e2f7f7a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28420
95583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.2842095583
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.2666005749
Short name T1601
Test name
Test status
Simulation time 9267443615 ps
CPU time 15.34 seconds
Started May 21 01:11:52 PM PDT 24
Finished May 21 01:12:09 PM PDT 24
Peak memory 205376 kb
Host smart-0148eb11-332d-49e4-9ff9-c7cb60cff3d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26660
05749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.2666005749
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.954735428
Short name T1138
Test name
Test status
Simulation time 8409430330 ps
CPU time 13.78 seconds
Started May 21 01:11:53 PM PDT 24
Finished May 21 01:12:08 PM PDT 24
Peak memory 205372 kb
Host smart-66733dcb-76ef-4669-a6eb-258e5ac6500d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95473
5428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.954735428
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.4244222199
Short name T749
Test name
Test status
Simulation time 8417184134 ps
CPU time 11.8 seconds
Started May 21 01:11:59 PM PDT 24
Finished May 21 01:12:11 PM PDT 24
Peak memory 205448 kb
Host smart-ae8b941f-b900-4b31-b5b2-0a50f1f0c655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42442
22199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.4244222199
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1315999890
Short name T583
Test name
Test status
Simulation time 8370797237 ps
CPU time 12.36 seconds
Started May 21 01:12:05 PM PDT 24
Finished May 21 01:12:18 PM PDT 24
Peak memory 205316 kb
Host smart-d7885c90-f9ba-443b-bbf1-21ce39d260d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13159
99890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1315999890
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2248719674
Short name T839
Test name
Test status
Simulation time 8410177650 ps
CPU time 11.96 seconds
Started May 21 01:11:53 PM PDT 24
Finished May 21 01:12:07 PM PDT 24
Peak memory 205336 kb
Host smart-5649a18c-7862-4c81-90d8-7f0ec4f662cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22487
19674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2248719674
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.3462327429
Short name T800
Test name
Test status
Simulation time 11568482014 ps
CPU time 15.81 seconds
Started May 21 01:11:54 PM PDT 24
Finished May 21 01:12:12 PM PDT 24
Peak memory 205348 kb
Host smart-abd274f8-4a00-4d1b-be2c-240449c69ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34623
27429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.3462327429
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3004326107
Short name T420
Test name
Test status
Simulation time 8449845867 ps
CPU time 11.14 seconds
Started May 21 01:11:55 PM PDT 24
Finished May 21 01:12:07 PM PDT 24
Peak memory 205332 kb
Host smart-6513ae3b-9969-4fe9-ba95-06f04d1a7e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30043
26107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3004326107
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.2689030529
Short name T629
Test name
Test status
Simulation time 8382616029 ps
CPU time 11.89 seconds
Started May 21 01:11:53 PM PDT 24
Finished May 21 01:12:06 PM PDT 24
Peak memory 205348 kb
Host smart-e7530b77-9d69-4246-8923-1e0ecb42959d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26890
30529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.2689030529
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3452359649
Short name T1587
Test name
Test status
Simulation time 8491309819 ps
CPU time 12.58 seconds
Started May 21 01:11:52 PM PDT 24
Finished May 21 01:12:06 PM PDT 24
Peak memory 205616 kb
Host smart-bfefb512-3c7c-4395-a8ab-05a34f880748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34523
59649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3452359649
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.2647273966
Short name T1630
Test name
Test status
Simulation time 8416703193 ps
CPU time 12.43 seconds
Started May 21 01:11:52 PM PDT 24
Finished May 21 01:12:06 PM PDT 24
Peak memory 205428 kb
Host smart-0b12556c-f730-4045-8a33-df84d8be08f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26472
73966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.2647273966
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.1604376759
Short name T747
Test name
Test status
Simulation time 8394544170 ps
CPU time 14.52 seconds
Started May 21 01:11:52 PM PDT 24
Finished May 21 01:12:08 PM PDT 24
Peak memory 205384 kb
Host smart-edaee311-5bdc-41b8-a4e0-e5e979528c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16043
76759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.1604376759
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.2496596206
Short name T1155
Test name
Test status
Simulation time 8392515232 ps
CPU time 13.48 seconds
Started May 21 01:11:55 PM PDT 24
Finished May 21 01:12:10 PM PDT 24
Peak memory 205364 kb
Host smart-82e147c1-88fc-47d1-b88f-3ba151c90c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24965
96206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2496596206
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.1697562263
Short name T168
Test name
Test status
Simulation time 8442923843 ps
CPU time 14.98 seconds
Started May 21 01:12:00 PM PDT 24
Finished May 21 01:12:15 PM PDT 24
Peak memory 205336 kb
Host smart-44d2bcc2-630a-4a97-a5e9-a160ffe927a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16975
62263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.1697562263
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_eop_single_bit_handling.2272239620
Short name T944
Test name
Test status
Simulation time 8393529972 ps
CPU time 11.78 seconds
Started May 21 01:12:02 PM PDT 24
Finished May 21 01:12:15 PM PDT 24
Peak memory 205380 kb
Host smart-f47dbef5-b327-4639-b9be-00a544006c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22722
39620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_eop_single_bit_handling.2272239620
Directory /workspace/42.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.3187909183
Short name T698
Test name
Test status
Simulation time 8371241579 ps
CPU time 11.98 seconds
Started May 21 01:11:56 PM PDT 24
Finished May 21 01:12:09 PM PDT 24
Peak memory 205300 kb
Host smart-56664a23-584f-4e52-95b9-c514bfd7dcc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31879
09183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.3187909183
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.4075572803
Short name T738
Test name
Test status
Simulation time 8360962602 ps
CPU time 12.05 seconds
Started May 21 01:12:05 PM PDT 24
Finished May 21 01:12:18 PM PDT 24
Peak memory 205380 kb
Host smart-61eede84-bb54-45da-b6de-398961ac9900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40755
72803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.4075572803
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.2629689657
Short name T184
Test name
Test status
Simulation time 30680977050 ps
CPU time 62.34 seconds
Started May 21 01:11:54 PM PDT 24
Finished May 21 01:12:58 PM PDT 24
Peak memory 205404 kb
Host smart-d0e6568b-e105-442b-bec9-7823c3a14b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26296
89657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.2629689657
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.551072506
Short name T1137
Test name
Test status
Simulation time 8387471529 ps
CPU time 14.75 seconds
Started May 21 01:11:53 PM PDT 24
Finished May 21 01:12:10 PM PDT 24
Peak memory 205384 kb
Host smart-e53bbfea-1039-4584-a0db-f933514463b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55107
2506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.551072506
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.1972974768
Short name T1477
Test name
Test status
Simulation time 8464319271 ps
CPU time 13.39 seconds
Started May 21 01:11:51 PM PDT 24
Finished May 21 01:12:06 PM PDT 24
Peak memory 205348 kb
Host smart-89aca61a-9ffb-4c57-8586-4a7503a52118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19729
74768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.1972974768
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.3725617457
Short name T528
Test name
Test status
Simulation time 8416065257 ps
CPU time 12.74 seconds
Started May 21 01:11:54 PM PDT 24
Finished May 21 01:12:09 PM PDT 24
Peak memory 205416 kb
Host smart-af64037b-6fa9-4a70-b827-0613e603a90a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37256
17457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.3725617457
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1600201057
Short name T1640
Test name
Test status
Simulation time 8370386424 ps
CPU time 11.62 seconds
Started May 21 01:11:54 PM PDT 24
Finished May 21 01:12:07 PM PDT 24
Peak memory 205364 kb
Host smart-dab90e16-d175-4f1f-954f-7b00b23bc258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16002
01057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1600201057
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.3526085501
Short name T178
Test name
Test status
Simulation time 8394994015 ps
CPU time 11.69 seconds
Started May 21 01:12:00 PM PDT 24
Finished May 21 01:12:13 PM PDT 24
Peak memory 205376 kb
Host smart-a192d671-f1fc-44af-87cf-41f6a33a1a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35260
85501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.3526085501
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2450848174
Short name T578
Test name
Test status
Simulation time 8384301908 ps
CPU time 12.2 seconds
Started May 21 01:11:56 PM PDT 24
Finished May 21 01:12:09 PM PDT 24
Peak memory 205408 kb
Host smart-0ab8217c-5081-4d24-8bc0-43fc3b140bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24508
48174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2450848174
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.4267674981
Short name T1073
Test name
Test status
Simulation time 8448171972 ps
CPU time 11.73 seconds
Started May 21 01:11:55 PM PDT 24
Finished May 21 01:12:08 PM PDT 24
Peak memory 205328 kb
Host smart-4c31f683-c2a3-4757-b2ad-24c369e3141e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42676
74981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.4267674981
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2424964730
Short name T943
Test name
Test status
Simulation time 8402232004 ps
CPU time 12.32 seconds
Started May 21 01:11:53 PM PDT 24
Finished May 21 01:12:07 PM PDT 24
Peak memory 205468 kb
Host smart-d6d6fe6d-4d8a-400e-9842-9e9cb5aedc1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24249
64730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2424964730
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.1541584630
Short name T921
Test name
Test status
Simulation time 8408226842 ps
CPU time 11.74 seconds
Started May 21 01:11:55 PM PDT 24
Finished May 21 01:12:08 PM PDT 24
Peak memory 205376 kb
Host smart-17c1eeee-2c18-42ad-90d0-6b9da107a2b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15415
84630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.1541584630
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.2945227945
Short name T1704
Test name
Test status
Simulation time 8469244782 ps
CPU time 13.64 seconds
Started May 21 01:12:09 PM PDT 24
Finished May 21 01:12:24 PM PDT 24
Peak memory 205444 kb
Host smart-250bff58-8c60-4aa9-8285-7f01b7e2e5a9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2945227945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.2945227945
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.2349389211
Short name T825
Test name
Test status
Simulation time 8379913299 ps
CPU time 11.08 seconds
Started May 21 01:12:10 PM PDT 24
Finished May 21 01:12:23 PM PDT 24
Peak memory 205328 kb
Host smart-a8a19d20-e130-423f-a5f4-13b2e4452862
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2349389211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.2349389211
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.3636282124
Short name T213
Test name
Test status
Simulation time 8431874846 ps
CPU time 12.27 seconds
Started May 21 01:12:09 PM PDT 24
Finished May 21 01:12:22 PM PDT 24
Peak memory 205384 kb
Host smart-52fc9950-d266-4ce2-8da2-21db0e2a3ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36362
82124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.3636282124
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.252398447
Short name T1007
Test name
Test status
Simulation time 8375401175 ps
CPU time 12.6 seconds
Started May 21 01:12:00 PM PDT 24
Finished May 21 01:12:13 PM PDT 24
Peak memory 205432 kb
Host smart-887b9741-77bc-42a5-b502-299cdbc19050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25239
8447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.252398447
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.2953481542
Short name T953
Test name
Test status
Simulation time 8670786460 ps
CPU time 15.05 seconds
Started May 21 01:12:03 PM PDT 24
Finished May 21 01:12:19 PM PDT 24
Peak memory 205292 kb
Host smart-f3bb9c66-e576-4a58-8206-d1147ad026b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29534
81542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.2953481542
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.4159292360
Short name T901
Test name
Test status
Simulation time 8393997397 ps
CPU time 11.17 seconds
Started May 21 01:12:04 PM PDT 24
Finished May 21 01:12:16 PM PDT 24
Peak memory 205532 kb
Host smart-73b5cde6-54de-403d-97cf-db5597562659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41592
92360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.4159292360
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.1630133046
Short name T1635
Test name
Test status
Simulation time 8389280563 ps
CPU time 12.89 seconds
Started May 21 01:12:02 PM PDT 24
Finished May 21 01:12:16 PM PDT 24
Peak memory 205324 kb
Host smart-d25f1a99-a7e7-49c7-9661-f1b9dfd7c3ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16301
33046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1630133046
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3245137268
Short name T582
Test name
Test status
Simulation time 8517815236 ps
CPU time 12.97 seconds
Started May 21 01:12:01 PM PDT 24
Finished May 21 01:12:15 PM PDT 24
Peak memory 205288 kb
Host smart-96b0ba47-313b-4cc4-a4f7-2edfaa546e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32451
37268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3245137268
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.4245668796
Short name T377
Test name
Test status
Simulation time 8482036997 ps
CPU time 13.85 seconds
Started May 21 01:12:06 PM PDT 24
Finished May 21 01:12:22 PM PDT 24
Peak memory 205336 kb
Host smart-967a7dc8-9679-41f0-840c-62e82fa06900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42456
68796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.4245668796
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.1690247617
Short name T329
Test name
Test status
Simulation time 8368537996 ps
CPU time 10.94 seconds
Started May 21 01:12:07 PM PDT 24
Finished May 21 01:12:19 PM PDT 24
Peak memory 205304 kb
Host smart-342b389b-c41b-4247-8c74-726b8e3658cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16902
47617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.1690247617
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.101679878
Short name T1621
Test name
Test status
Simulation time 8422389455 ps
CPU time 13.92 seconds
Started May 21 01:12:00 PM PDT 24
Finished May 21 01:12:14 PM PDT 24
Peak memory 205340 kb
Host smart-20755ac9-d00a-473f-8501-69e2085a566e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10167
9878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.101679878
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.3918635566
Short name T1480
Test name
Test status
Simulation time 11534792399 ps
CPU time 16.69 seconds
Started May 21 01:12:02 PM PDT 24
Finished May 21 01:12:20 PM PDT 24
Peak memory 205304 kb
Host smart-31369cb5-5e8e-4566-b6a1-0c7dfe671c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39186
35566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.3918635566
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.1830546690
Short name T1345
Test name
Test status
Simulation time 8422741011 ps
CPU time 13.12 seconds
Started May 21 01:12:03 PM PDT 24
Finished May 21 01:12:17 PM PDT 24
Peak memory 205252 kb
Host smart-c12f3b63-9a24-4756-a3fa-e7f967b5ca49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18305
46690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.1830546690
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.3082440535
Short name T590
Test name
Test status
Simulation time 8375188755 ps
CPU time 14.36 seconds
Started May 21 01:12:24 PM PDT 24
Finished May 21 01:12:40 PM PDT 24
Peak memory 205428 kb
Host smart-6822c453-74c5-4ca8-9875-0b72de09dbdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30824
40535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.3082440535
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.3337832284
Short name T133
Test name
Test status
Simulation time 8407362222 ps
CPU time 12.92 seconds
Started May 21 01:12:00 PM PDT 24
Finished May 21 01:12:14 PM PDT 24
Peak memory 205364 kb
Host smart-2cf9e70a-9e95-4c2e-9ee8-97a7886b38c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33378
32284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.3337832284
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.3354871921
Short name T307
Test name
Test status
Simulation time 8427532926 ps
CPU time 11.76 seconds
Started May 21 01:11:59 PM PDT 24
Finished May 21 01:12:11 PM PDT 24
Peak memory 205276 kb
Host smart-ef861c31-4c13-4ae4-8f85-dabe9331e87b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33548
71921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.3354871921
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.988702292
Short name T1561
Test name
Test status
Simulation time 8389463932 ps
CPU time 11.65 seconds
Started May 21 01:12:01 PM PDT 24
Finished May 21 01:12:14 PM PDT 24
Peak memory 205400 kb
Host smart-139e7f26-f617-4a8e-8063-0e7bf9ba3caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98870
2292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.988702292
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3916014939
Short name T1269
Test name
Test status
Simulation time 8409676544 ps
CPU time 12.54 seconds
Started May 21 01:12:02 PM PDT 24
Finished May 21 01:12:16 PM PDT 24
Peak memory 205352 kb
Host smart-19109c54-1717-4680-abd6-4232f6d2a809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39160
14939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3916014939
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.1319450646
Short name T1527
Test name
Test status
Simulation time 8441795118 ps
CPU time 11.4 seconds
Started May 21 01:12:05 PM PDT 24
Finished May 21 01:12:18 PM PDT 24
Peak memory 205404 kb
Host smart-86d17848-767e-4ffe-aaa2-dccbd587ec77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13194
50646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.1319450646
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_eop_single_bit_handling.895625426
Short name T313
Test name
Test status
Simulation time 8410152787 ps
CPU time 12.13 seconds
Started May 21 01:12:07 PM PDT 24
Finished May 21 01:12:21 PM PDT 24
Peak memory 205372 kb
Host smart-dbaf28bd-bcaf-4c0a-b9d3-895df97e266d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89562
5426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_eop_single_bit_handling.895625426
Directory /workspace/43.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.1235391628
Short name T1020
Test name
Test status
Simulation time 8382206389 ps
CPU time 11.23 seconds
Started May 21 01:12:07 PM PDT 24
Finished May 21 01:12:20 PM PDT 24
Peak memory 205352 kb
Host smart-8ab37c46-307c-4156-9853-20dbc19cbaae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12353
91628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.1235391628
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.1485725194
Short name T1103
Test name
Test status
Simulation time 8391968404 ps
CPU time 11.43 seconds
Started May 21 01:12:10 PM PDT 24
Finished May 21 01:12:24 PM PDT 24
Peak memory 205388 kb
Host smart-130875a9-fa26-4cbf-8c09-5f875bf9433d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14857
25194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.1485725194
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.1678744758
Short name T1292
Test name
Test status
Simulation time 8425840078 ps
CPU time 11.94 seconds
Started May 21 01:12:08 PM PDT 24
Finished May 21 01:12:21 PM PDT 24
Peak memory 205288 kb
Host smart-5fe24878-d746-479e-9ed4-b080dbb3cd3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16787
44758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.1678744758
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2027351012
Short name T626
Test name
Test status
Simulation time 8428372762 ps
CPU time 10.49 seconds
Started May 21 01:12:07 PM PDT 24
Finished May 21 01:12:20 PM PDT 24
Peak memory 205420 kb
Host smart-e533b845-1948-4022-b2aa-b9baf3ecfa19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20273
51012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2027351012
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.3442422938
Short name T1279
Test name
Test status
Simulation time 8459621501 ps
CPU time 13.69 seconds
Started May 21 01:12:11 PM PDT 24
Finished May 21 01:12:26 PM PDT 24
Peak memory 205364 kb
Host smart-2c074c9e-a36e-40fa-acce-3008880227c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34424
22938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.3442422938
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.989635967
Short name T925
Test name
Test status
Simulation time 8365413449 ps
CPU time 13.72 seconds
Started May 21 01:12:13 PM PDT 24
Finished May 21 01:12:27 PM PDT 24
Peak memory 205328 kb
Host smart-9796049e-a9f9-4cc2-924d-36dd834cb2cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98963
5967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.989635967
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.4284920988
Short name T1634
Test name
Test status
Simulation time 8380280926 ps
CPU time 10.84 seconds
Started May 21 01:12:08 PM PDT 24
Finished May 21 01:12:21 PM PDT 24
Peak memory 205344 kb
Host smart-acb5f1cb-d753-4c9c-b75b-4bda08f8c270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42849
20988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.4284920988
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.1304396525
Short name T1090
Test name
Test status
Simulation time 8378614160 ps
CPU time 12.4 seconds
Started May 21 01:12:07 PM PDT 24
Finished May 21 01:12:21 PM PDT 24
Peak memory 205396 kb
Host smart-494331c4-b833-4552-afac-2a58c740d401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13043
96525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.1304396525
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.3685172579
Short name T642
Test name
Test status
Simulation time 8427870428 ps
CPU time 12.38 seconds
Started May 21 01:12:02 PM PDT 24
Finished May 21 01:12:16 PM PDT 24
Peak memory 205324 kb
Host smart-d938fd32-5900-475d-abb9-fdc11a1c4b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36851
72579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.3685172579
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.2245574439
Short name T563
Test name
Test status
Simulation time 8397986018 ps
CPU time 11.05 seconds
Started May 21 01:12:10 PM PDT 24
Finished May 21 01:12:23 PM PDT 24
Peak memory 205356 kb
Host smart-cb703c27-095e-4e7b-a383-6558950fa922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22455
74439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.2245574439
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.3910389235
Short name T483
Test name
Test status
Simulation time 8399531217 ps
CPU time 12.09 seconds
Started May 21 01:12:06 PM PDT 24
Finished May 21 01:12:20 PM PDT 24
Peak memory 205328 kb
Host smart-45b0e72f-16d7-4bdf-9e21-3a2b8438847d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39103
89235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.3910389235
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.869141678
Short name T521
Test name
Test status
Simulation time 8471202124 ps
CPU time 12.25 seconds
Started May 21 01:12:11 PM PDT 24
Finished May 21 01:12:25 PM PDT 24
Peak memory 205372 kb
Host smart-acac55f7-51e5-4625-9a0b-aa7a1d6aaf48
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=869141678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.869141678
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.1045414239
Short name T802
Test name
Test status
Simulation time 8382638778 ps
CPU time 11.48 seconds
Started May 21 01:12:13 PM PDT 24
Finished May 21 01:12:26 PM PDT 24
Peak memory 205392 kb
Host smart-27659d12-4fcc-4942-9535-5f2bd8c97652
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1045414239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.1045414239
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.3830537680
Short name T673
Test name
Test status
Simulation time 8395579095 ps
CPU time 12.1 seconds
Started May 21 01:12:14 PM PDT 24
Finished May 21 01:12:27 PM PDT 24
Peak memory 205300 kb
Host smart-078f7e95-3ee4-43d7-b4d6-3e9ad6d8f3d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38305
37680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.3830537680
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.1028154602
Short name T1306
Test name
Test status
Simulation time 8385816365 ps
CPU time 11.59 seconds
Started May 21 01:12:10 PM PDT 24
Finished May 21 01:12:23 PM PDT 24
Peak memory 205356 kb
Host smart-b3f110e6-dbaf-4752-b28c-24a05f74677e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10281
54602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.1028154602
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.114792098
Short name T1100
Test name
Test status
Simulation time 8457574442 ps
CPU time 14.3 seconds
Started May 21 01:12:06 PM PDT 24
Finished May 21 01:12:22 PM PDT 24
Peak memory 205360 kb
Host smart-4b565f71-6027-44ed-ad95-135fda4a45c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11479
2098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.114792098
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.3098661202
Short name T736
Test name
Test status
Simulation time 8415914193 ps
CPU time 12.56 seconds
Started May 21 01:12:06 PM PDT 24
Finished May 21 01:12:20 PM PDT 24
Peak memory 205340 kb
Host smart-b6365047-ba42-44eb-8fd6-79c9714b8786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30986
61202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.3098661202
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.3354129143
Short name T879
Test name
Test status
Simulation time 8382411667 ps
CPU time 11.77 seconds
Started May 21 01:12:10 PM PDT 24
Finished May 21 01:12:24 PM PDT 24
Peak memory 205340 kb
Host smart-061cfefe-16f0-4afe-86d8-8d5fbb62597e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33541
29143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.3354129143
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.649647234
Short name T630
Test name
Test status
Simulation time 9087945536 ps
CPU time 13.27 seconds
Started May 21 01:12:11 PM PDT 24
Finished May 21 01:12:26 PM PDT 24
Peak memory 205356 kb
Host smart-b74bce6e-88f3-4a0e-9063-a13c02afd6ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64964
7234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.649647234
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.1884054217
Short name T951
Test name
Test status
Simulation time 8414155716 ps
CPU time 13.8 seconds
Started May 21 01:12:06 PM PDT 24
Finished May 21 01:12:22 PM PDT 24
Peak memory 205316 kb
Host smart-17c4f22a-1d90-449d-84bb-14610785d012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18840
54217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.1884054217
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.204599904
Short name T1163
Test name
Test status
Simulation time 8444241630 ps
CPU time 11.9 seconds
Started May 21 01:12:12 PM PDT 24
Finished May 21 01:12:25 PM PDT 24
Peak memory 205364 kb
Host smart-0989530f-b380-4458-8c08-1158d99e2df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20459
9904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.204599904
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.1288082130
Short name T1222
Test name
Test status
Simulation time 8373493048 ps
CPU time 12.66 seconds
Started May 21 01:12:11 PM PDT 24
Finished May 21 01:12:25 PM PDT 24
Peak memory 205340 kb
Host smart-f9e47329-a36c-47b9-92f8-d910686f60f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12880
82130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.1288082130
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.2070969125
Short name T312
Test name
Test status
Simulation time 8388272533 ps
CPU time 12.7 seconds
Started May 21 01:12:09 PM PDT 24
Finished May 21 01:12:23 PM PDT 24
Peak memory 205444 kb
Host smart-a749289f-7fce-4f30-985d-defec7e28363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20709
69125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2070969125
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.335884886
Short name T1148
Test name
Test status
Simulation time 11553415777 ps
CPU time 15.14 seconds
Started May 21 01:12:09 PM PDT 24
Finished May 21 01:12:26 PM PDT 24
Peak memory 205464 kb
Host smart-9ff76157-eeab-47c4-8fb8-b6e953850fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33588
4886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.335884886
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.186869846
Short name T280
Test name
Test status
Simulation time 8419669503 ps
CPU time 13.08 seconds
Started May 21 01:12:05 PM PDT 24
Finished May 21 01:12:19 PM PDT 24
Peak memory 205284 kb
Host smart-70142b74-a823-4710-983f-0be6b1a726a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18686
9846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.186869846
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1058275365
Short name T500
Test name
Test status
Simulation time 8380940823 ps
CPU time 12.06 seconds
Started May 21 01:12:10 PM PDT 24
Finished May 21 01:12:24 PM PDT 24
Peak memory 205452 kb
Host smart-52b6106f-f05a-4082-906d-a41b6b106e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10582
75365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1058275365
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.3473145715
Short name T1504
Test name
Test status
Simulation time 8419042719 ps
CPU time 12.93 seconds
Started May 21 01:12:09 PM PDT 24
Finished May 21 01:12:23 PM PDT 24
Peak memory 205264 kb
Host smart-24e2411d-29fc-4924-8603-3fd8f7d04574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34731
45715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3473145715
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.2986172716
Short name T1405
Test name
Test status
Simulation time 8413916944 ps
CPU time 11.37 seconds
Started May 21 01:12:10 PM PDT 24
Finished May 21 01:12:23 PM PDT 24
Peak memory 205404 kb
Host smart-e254c212-07cb-41a0-b598-2c4b1fd9ad92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29861
72716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2986172716
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.1507670325
Short name T1161
Test name
Test status
Simulation time 8386498130 ps
CPU time 11.29 seconds
Started May 21 01:12:08 PM PDT 24
Finished May 21 01:12:21 PM PDT 24
Peak memory 205376 kb
Host smart-d22f7042-66d5-4ccb-a813-324c105c0e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15076
70325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.1507670325
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.1422088982
Short name T1536
Test name
Test status
Simulation time 8404504106 ps
CPU time 12.07 seconds
Started May 21 01:12:10 PM PDT 24
Finished May 21 01:12:24 PM PDT 24
Peak memory 205412 kb
Host smart-f2bbf025-fafd-4cfc-893d-b2994c7dbb67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14220
88982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.1422088982
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.1945127287
Short name T828
Test name
Test status
Simulation time 8401564105 ps
CPU time 12.66 seconds
Started May 21 01:12:13 PM PDT 24
Finished May 21 01:12:27 PM PDT 24
Peak memory 205392 kb
Host smart-5ebe8715-2983-4c8d-90ff-db19f3825412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19451
27287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.1945127287
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_eop_single_bit_handling.2770476920
Short name T19
Test name
Test status
Simulation time 8392356012 ps
CPU time 12.67 seconds
Started May 21 01:12:13 PM PDT 24
Finished May 21 01:12:27 PM PDT 24
Peak memory 205380 kb
Host smart-5687e62e-06e3-4aec-af0e-67eea31d9adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27704
76920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_eop_single_bit_handling.2770476920
Directory /workspace/44.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3823250175
Short name T725
Test name
Test status
Simulation time 8371860817 ps
CPU time 11.6 seconds
Started May 21 01:12:14 PM PDT 24
Finished May 21 01:12:27 PM PDT 24
Peak memory 205392 kb
Host smart-e3ff0060-ab51-410a-8012-a22a077bd15f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38232
50175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3823250175
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3883632551
Short name T1434
Test name
Test status
Simulation time 8399399898 ps
CPU time 13.76 seconds
Started May 21 01:12:14 PM PDT 24
Finished May 21 01:12:29 PM PDT 24
Peak memory 205412 kb
Host smart-688eed3d-e916-4c64-89dc-c7c1cf3ac66a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38836
32551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3883632551
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2651576347
Short name T183
Test name
Test status
Simulation time 21020415378 ps
CPU time 37 seconds
Started May 21 01:12:07 PM PDT 24
Finished May 21 01:12:46 PM PDT 24
Peak memory 205340 kb
Host smart-45afc3b2-aac7-4ace-9e6a-f5e23f6290b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26515
76347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2651576347
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.1167030447
Short name T768
Test name
Test status
Simulation time 8404730824 ps
CPU time 12.23 seconds
Started May 21 01:12:08 PM PDT 24
Finished May 21 01:12:22 PM PDT 24
Peak memory 205264 kb
Host smart-0272124b-ad86-401d-a54a-ce3e0f19fb2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11670
30447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.1167030447
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.2860619613
Short name T1447
Test name
Test status
Simulation time 8420974172 ps
CPU time 11.38 seconds
Started May 21 01:12:09 PM PDT 24
Finished May 21 01:12:22 PM PDT 24
Peak memory 205320 kb
Host smart-40b4111c-4c74-47e9-9649-68c8479e878b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28606
19613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2860619613
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.2530244430
Short name T439
Test name
Test status
Simulation time 8380226240 ps
CPU time 11.76 seconds
Started May 21 01:12:06 PM PDT 24
Finished May 21 01:12:19 PM PDT 24
Peak memory 205304 kb
Host smart-d96000b6-ef6e-46c6-81d6-7426aef038ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25302
44430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.2530244430
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.3996133517
Short name T1004
Test name
Test status
Simulation time 8367366262 ps
CPU time 11.3 seconds
Started May 21 01:12:12 PM PDT 24
Finished May 21 01:12:25 PM PDT 24
Peak memory 205240 kb
Host smart-508686e2-830c-418d-a9f3-8bc4dc68f58f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39961
33517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.3996133517
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.3853069405
Short name T559
Test name
Test status
Simulation time 8388469401 ps
CPU time 10.97 seconds
Started May 21 01:12:13 PM PDT 24
Finished May 21 01:12:25 PM PDT 24
Peak memory 205200 kb
Host smart-179652fc-2341-4d9e-b6ef-fe9ae174812e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38530
69405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.3853069405
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.2684395724
Short name T1545
Test name
Test status
Simulation time 8388833701 ps
CPU time 11.81 seconds
Started May 21 01:12:15 PM PDT 24
Finished May 21 01:12:28 PM PDT 24
Peak memory 205340 kb
Host smart-cc1196b2-4934-41d7-bad0-9cd6cb9126e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26843
95724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.2684395724
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.452387797
Short name T160
Test name
Test status
Simulation time 8468281560 ps
CPU time 11.49 seconds
Started May 21 01:12:10 PM PDT 24
Finished May 21 01:12:23 PM PDT 24
Peak memory 205392 kb
Host smart-4645e52d-306a-472b-b963-b17c5b273973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45238
7797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.452387797
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.176647277
Short name T545
Test name
Test status
Simulation time 8419702369 ps
CPU time 11.93 seconds
Started May 21 01:12:11 PM PDT 24
Finished May 21 01:12:25 PM PDT 24
Peak memory 205240 kb
Host smart-41a486eb-32bf-411e-aef6-16d9b5eefb3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17664
7277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.176647277
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.4053642794
Short name T108
Test name
Test status
Simulation time 8399601749 ps
CPU time 11.58 seconds
Started May 21 01:12:11 PM PDT 24
Finished May 21 01:12:24 PM PDT 24
Peak memory 205348 kb
Host smart-e7cca282-0f71-4b50-9795-115663243d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40536
42794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.4053642794
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.1574320035
Short name T375
Test name
Test status
Simulation time 8470691204 ps
CPU time 11.21 seconds
Started May 21 01:12:20 PM PDT 24
Finished May 21 01:12:34 PM PDT 24
Peak memory 205376 kb
Host smart-81ba5c83-aba9-4cb3-a3fb-9a39b5b12e56
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1574320035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.1574320035
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.1905197271
Short name T701
Test name
Test status
Simulation time 8410502511 ps
CPU time 11.24 seconds
Started May 21 01:12:22 PM PDT 24
Finished May 21 01:12:35 PM PDT 24
Peak memory 205280 kb
Host smart-56ebd7db-d1ac-45fd-8b28-3bb0c897e78d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1905197271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.1905197271
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.3580983958
Short name T1250
Test name
Test status
Simulation time 8430585155 ps
CPU time 12.15 seconds
Started May 21 01:12:23 PM PDT 24
Finished May 21 01:12:37 PM PDT 24
Peak memory 205352 kb
Host smart-10dc0c37-b473-40c8-b2d3-2cbe9fe454f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35809
83958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.3580983958
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.2853425614
Short name T1321
Test name
Test status
Simulation time 8392628892 ps
CPU time 12.91 seconds
Started May 21 01:12:15 PM PDT 24
Finished May 21 01:12:29 PM PDT 24
Peak memory 205312 kb
Host smart-4cb93369-ce90-444e-ae71-9a346b1873f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28534
25614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.2853425614
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.683509684
Short name T644
Test name
Test status
Simulation time 9177603185 ps
CPU time 13.93 seconds
Started May 21 01:12:11 PM PDT 24
Finished May 21 01:12:26 PM PDT 24
Peak memory 205352 kb
Host smart-eb487ff4-f4e9-4725-ad6a-f6a47c2d7bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68350
9684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.683509684
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.2532359505
Short name T412
Test name
Test status
Simulation time 8395633601 ps
CPU time 12.39 seconds
Started May 21 01:12:20 PM PDT 24
Finished May 21 01:12:35 PM PDT 24
Peak memory 205328 kb
Host smart-2f960327-58d6-44e0-bea9-cd6be97a6ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25323
59505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.2532359505
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.3092131375
Short name T1713
Test name
Test status
Simulation time 8435429347 ps
CPU time 11.92 seconds
Started May 21 01:12:14 PM PDT 24
Finished May 21 01:12:27 PM PDT 24
Peak memory 205320 kb
Host smart-81db8a34-cb19-4dc2-9aa1-7c253e621d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30921
31375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.3092131375
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.3352105004
Short name T615
Test name
Test status
Simulation time 9205104726 ps
CPU time 13.27 seconds
Started May 21 01:12:13 PM PDT 24
Finished May 21 01:12:28 PM PDT 24
Peak memory 205388 kb
Host smart-f5e9cb49-b12a-466f-b835-b891ffb57534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33521
05004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.3352105004
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.4005281659
Short name T875
Test name
Test status
Simulation time 8458072535 ps
CPU time 12.06 seconds
Started May 21 01:12:15 PM PDT 24
Finished May 21 01:12:29 PM PDT 24
Peak memory 205268 kb
Host smart-833cb800-96cf-4299-b5a8-dad326cd3ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40052
81659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.4005281659
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.3217657951
Short name T428
Test name
Test status
Simulation time 8416396561 ps
CPU time 12.27 seconds
Started May 21 01:12:22 PM PDT 24
Finished May 21 01:12:36 PM PDT 24
Peak memory 205272 kb
Host smart-17e71933-eb2b-4ecf-9d32-9dfafbd3550b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32176
57951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.3217657951
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.2504008563
Short name T1236
Test name
Test status
Simulation time 8371896470 ps
CPU time 13.61 seconds
Started May 21 01:12:20 PM PDT 24
Finished May 21 01:12:35 PM PDT 24
Peak memory 205292 kb
Host smart-0c897182-952c-4d25-8e50-d639ed68f34b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25040
08563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.2504008563
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3845194470
Short name T363
Test name
Test status
Simulation time 8454656558 ps
CPU time 14.11 seconds
Started May 21 01:12:13 PM PDT 24
Finished May 21 01:12:28 PM PDT 24
Peak memory 205328 kb
Host smart-0e5884b0-a016-4ee9-94b0-aa22fde6c202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38451
94470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3845194470
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.1478212911
Short name T1220
Test name
Test status
Simulation time 11513616786 ps
CPU time 15.32 seconds
Started May 21 01:12:12 PM PDT 24
Finished May 21 01:12:28 PM PDT 24
Peak memory 205348 kb
Host smart-b77116b4-5a73-4262-a3ca-dcb8a0af7437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14782
12911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.1478212911
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.4025250439
Short name T1081
Test name
Test status
Simulation time 8426638034 ps
CPU time 11.59 seconds
Started May 21 01:12:19 PM PDT 24
Finished May 21 01:12:33 PM PDT 24
Peak memory 205336 kb
Host smart-4f34c09b-0ee0-426f-af9c-4f807602d0f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40252
50439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.4025250439
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.658510711
Short name T1619
Test name
Test status
Simulation time 8375522923 ps
CPU time 12.33 seconds
Started May 21 01:12:19 PM PDT 24
Finished May 21 01:12:33 PM PDT 24
Peak memory 205296 kb
Host smart-5bbeb031-7eb0-4533-9992-e2f515d1f7d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65851
0711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.658510711
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.226233259
Short name T136
Test name
Test status
Simulation time 8442013073 ps
CPU time 12.57 seconds
Started May 21 01:12:20 PM PDT 24
Finished May 21 01:12:35 PM PDT 24
Peak memory 205304 kb
Host smart-ed7a3b4c-b1d9-4474-92a9-02829e81b219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22623
3259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.226233259
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.4175274678
Short name T489
Test name
Test status
Simulation time 8415153302 ps
CPU time 14.1 seconds
Started May 21 01:12:20 PM PDT 24
Finished May 21 01:12:36 PM PDT 24
Peak memory 205272 kb
Host smart-e16a505a-269c-4474-bdde-63a21f4a359c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41752
74678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.4175274678
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.1953017058
Short name T450
Test name
Test status
Simulation time 8392397903 ps
CPU time 13.4 seconds
Started May 21 01:12:20 PM PDT 24
Finished May 21 01:12:36 PM PDT 24
Peak memory 205616 kb
Host smart-892a0741-f0e8-4155-8b76-c66218788d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19530
17058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.1953017058
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3760610774
Short name T1437
Test name
Test status
Simulation time 8377286601 ps
CPU time 12.41 seconds
Started May 21 01:12:23 PM PDT 24
Finished May 21 01:12:37 PM PDT 24
Peak memory 205348 kb
Host smart-c2f67c5f-31e1-490d-b578-ff266f79fb63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37606
10774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3760610774
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.37713199
Short name T176
Test name
Test status
Simulation time 8376436614 ps
CPU time 12.02 seconds
Started May 21 01:12:20 PM PDT 24
Finished May 21 01:12:34 PM PDT 24
Peak memory 205336 kb
Host smart-ead8252f-1beb-4751-b915-3ec85fe16f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37713
199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.37713199
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_eop_single_bit_handling.107390557
Short name T1390
Test name
Test status
Simulation time 8454593779 ps
CPU time 12.92 seconds
Started May 21 01:12:19 PM PDT 24
Finished May 21 01:12:34 PM PDT 24
Peak memory 205412 kb
Host smart-c007a0ad-1199-446a-8a98-2d37c672cc22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10739
0557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_eop_single_bit_handling.107390557
Directory /workspace/45.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.1493603959
Short name T1682
Test name
Test status
Simulation time 8370320128 ps
CPU time 13.93 seconds
Started May 21 01:12:21 PM PDT 24
Finished May 21 01:12:37 PM PDT 24
Peak memory 205400 kb
Host smart-ed46d940-524e-47ad-91d8-c6bc67ad91bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14936
03959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.1493603959
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.2550442758
Short name T33
Test name
Test status
Simulation time 8378045583 ps
CPU time 11.24 seconds
Started May 21 01:12:22 PM PDT 24
Finished May 21 01:12:35 PM PDT 24
Peak memory 205340 kb
Host smart-ebec7f02-40ea-422f-bb95-bbecb718f3b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25504
42758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.2550442758
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.2728693418
Short name T1196
Test name
Test status
Simulation time 8376757571 ps
CPU time 12 seconds
Started May 21 01:12:21 PM PDT 24
Finished May 21 01:12:35 PM PDT 24
Peak memory 205336 kb
Host smart-01fca396-826f-4ff8-8d9c-7a66ef697a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27286
93418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.2728693418
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.3481490832
Short name T675
Test name
Test status
Simulation time 8470823970 ps
CPU time 12.26 seconds
Started May 21 01:12:22 PM PDT 24
Finished May 21 01:12:36 PM PDT 24
Peak memory 205272 kb
Host smart-fe7533d4-fd4a-4fcf-98b3-7bb2df555fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34814
90832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.3481490832
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.295577752
Short name T624
Test name
Test status
Simulation time 8384846255 ps
CPU time 11.21 seconds
Started May 21 01:12:20 PM PDT 24
Finished May 21 01:12:33 PM PDT 24
Peak memory 205372 kb
Host smart-f6a176df-ddeb-4138-ab3f-d542af15b3da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29557
7752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.295577752
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.2681721912
Short name T763
Test name
Test status
Simulation time 8369021451 ps
CPU time 12.43 seconds
Started May 21 01:12:23 PM PDT 24
Finished May 21 01:12:37 PM PDT 24
Peak memory 205204 kb
Host smart-764fd1fc-8c8b-42ba-b927-4caafee8b496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26817
21912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.2681721912
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.4081740493
Short name T1234
Test name
Test status
Simulation time 8395858394 ps
CPU time 12.84 seconds
Started May 21 01:12:20 PM PDT 24
Finished May 21 01:12:35 PM PDT 24
Peak memory 205312 kb
Host smart-29b4c879-4d0c-4639-b681-19d2eb796915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40817
40493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.4081740493
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3049459722
Short name T1325
Test name
Test status
Simulation time 8375081273 ps
CPU time 12.81 seconds
Started May 21 01:12:20 PM PDT 24
Finished May 21 01:12:35 PM PDT 24
Peak memory 205392 kb
Host smart-25243e1d-e2bf-48b8-9c7a-b2d44ca9db2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30494
59722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3049459722
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3734285466
Short name T1448
Test name
Test status
Simulation time 8467447447 ps
CPU time 12.73 seconds
Started May 21 01:12:13 PM PDT 24
Finished May 21 01:12:27 PM PDT 24
Peak memory 205340 kb
Host smart-4bc05028-5488-4189-a211-21281f069aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37342
85466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3734285466
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.3073447391
Short name T1553
Test name
Test status
Simulation time 8386602397 ps
CPU time 12.09 seconds
Started May 21 01:12:20 PM PDT 24
Finished May 21 01:12:35 PM PDT 24
Peak memory 205252 kb
Host smart-e184997d-7796-4655-ba46-ac414379c5ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30734
47391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.3073447391
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.3655723663
Short name T555
Test name
Test status
Simulation time 8501260565 ps
CPU time 11.65 seconds
Started May 21 01:12:31 PM PDT 24
Finished May 21 01:12:44 PM PDT 24
Peak memory 205336 kb
Host smart-1b87bfc3-44cb-4ef8-b633-09e3a904971e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3655723663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.3655723663
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.571848327
Short name T1419
Test name
Test status
Simulation time 8380710328 ps
CPU time 12.09 seconds
Started May 21 01:12:37 PM PDT 24
Finished May 21 01:12:50 PM PDT 24
Peak memory 205320 kb
Host smart-c2fe0931-5843-4d15-9f54-ed4b94819cbc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=571848327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.571848327
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.2353646345
Short name T529
Test name
Test status
Simulation time 8451304865 ps
CPU time 12.14 seconds
Started May 21 01:12:33 PM PDT 24
Finished May 21 01:12:46 PM PDT 24
Peak memory 205356 kb
Host smart-03b5e0aa-12b0-49b4-9461-c2ef3f6c2492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23536
46345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.2353646345
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.731722615
Short name T1696
Test name
Test status
Simulation time 8378500807 ps
CPU time 11.59 seconds
Started May 21 01:12:22 PM PDT 24
Finished May 21 01:12:35 PM PDT 24
Peak memory 205408 kb
Host smart-e1357191-545d-434d-90fe-ec1af30533af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73172
2615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.731722615
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.1410947862
Short name T1676
Test name
Test status
Simulation time 9441797511 ps
CPU time 14.85 seconds
Started May 21 01:12:24 PM PDT 24
Finished May 21 01:12:41 PM PDT 24
Peak memory 205268 kb
Host smart-e101826f-5963-42ba-b880-71beec1fbc5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14109
47862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.1410947862
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.154022602
Short name T764
Test name
Test status
Simulation time 8380347138 ps
CPU time 13.26 seconds
Started May 21 01:12:31 PM PDT 24
Finished May 21 01:12:46 PM PDT 24
Peak memory 205368 kb
Host smart-d806e11a-9eae-4cfa-bfc9-4aa6a12c8ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15402
2602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.154022602
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.2339819415
Short name T1316
Test name
Test status
Simulation time 8429060647 ps
CPU time 12.12 seconds
Started May 21 01:12:23 PM PDT 24
Finished May 21 01:12:37 PM PDT 24
Peak memory 205296 kb
Host smart-266ab893-c290-4a07-b28f-367caabb6448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23398
19415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2339819415
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.659632991
Short name T1126
Test name
Test status
Simulation time 9104057031 ps
CPU time 14.07 seconds
Started May 21 01:13:22 PM PDT 24
Finished May 21 01:13:38 PM PDT 24
Peak memory 205400 kb
Host smart-4f70817d-906c-494a-90fe-11bb5ad8d57f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65963
2991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.659632991
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.3555510851
Short name T1246
Test name
Test status
Simulation time 8383609482 ps
CPU time 11.63 seconds
Started May 21 01:12:19 PM PDT 24
Finished May 21 01:12:33 PM PDT 24
Peak memory 205388 kb
Host smart-cd8d34a4-27bb-48a9-950b-c465c7693ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35555
10851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3555510851
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.225296665
Short name T520
Test name
Test status
Simulation time 8444401344 ps
CPU time 11.03 seconds
Started May 21 01:12:31 PM PDT 24
Finished May 21 01:12:44 PM PDT 24
Peak memory 205424 kb
Host smart-fdff76f3-056e-463d-af8f-a50b4121f3b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22529
6665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.225296665
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.542399694
Short name T53
Test name
Test status
Simulation time 8369546437 ps
CPU time 11.83 seconds
Started May 21 01:12:31 PM PDT 24
Finished May 21 01:12:44 PM PDT 24
Peak memory 205380 kb
Host smart-80e7ce73-2471-4b41-932b-def1c93fb2e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54239
9694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.542399694
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.3838875045
Short name T691
Test name
Test status
Simulation time 8423737183 ps
CPU time 11.7 seconds
Started May 21 01:12:20 PM PDT 24
Finished May 21 01:12:34 PM PDT 24
Peak memory 205276 kb
Host smart-4cdfa975-3b21-4a31-a397-8b599b4bd038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38388
75045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.3838875045
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.97609176
Short name T1591
Test name
Test status
Simulation time 8416384194 ps
CPU time 12.23 seconds
Started May 21 01:12:30 PM PDT 24
Finished May 21 01:12:43 PM PDT 24
Peak memory 205356 kb
Host smart-073e5b95-2fa6-4c96-9ce2-59815f876731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97609
176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.97609176
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.21524827
Short name T1111
Test name
Test status
Simulation time 11525485545 ps
CPU time 17.39 seconds
Started May 21 01:12:28 PM PDT 24
Finished May 21 01:12:46 PM PDT 24
Peak memory 205436 kb
Host smart-6f172c15-b4b8-4cc8-8b72-27f289561a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21524
827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.21524827
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1183474774
Short name T322
Test name
Test status
Simulation time 8414278730 ps
CPU time 13.94 seconds
Started May 21 01:12:27 PM PDT 24
Finished May 21 01:12:42 PM PDT 24
Peak memory 205352 kb
Host smart-19677521-f371-45b5-9568-76ed9a0d5b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11834
74774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1183474774
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.4125712695
Short name T684
Test name
Test status
Simulation time 8385971859 ps
CPU time 11.97 seconds
Started May 21 01:12:27 PM PDT 24
Finished May 21 01:12:40 PM PDT 24
Peak memory 205460 kb
Host smart-9e892c8d-d04a-468d-9e65-79400996d863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41257
12695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.4125712695
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1937294650
Short name T135
Test name
Test status
Simulation time 8454587641 ps
CPU time 12.29 seconds
Started May 21 01:12:26 PM PDT 24
Finished May 21 01:12:40 PM PDT 24
Peak memory 205304 kb
Host smart-3f953ffe-4231-4589-bd01-59a77ec217ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19372
94650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1937294650
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.418025177
Short name T704
Test name
Test status
Simulation time 8412936988 ps
CPU time 13.36 seconds
Started May 21 01:12:31 PM PDT 24
Finished May 21 01:12:46 PM PDT 24
Peak memory 205352 kb
Host smart-f3dba347-a3c3-46e6-948e-a910db60030e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41802
5177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.418025177
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.905152321
Short name T697
Test name
Test status
Simulation time 8374586943 ps
CPU time 11.27 seconds
Started May 21 01:12:25 PM PDT 24
Finished May 21 01:12:37 PM PDT 24
Peak memory 205364 kb
Host smart-f1362a7d-bd0c-45f4-b359-8641de6bba0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90515
2321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.905152321
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3108146026
Short name T315
Test name
Test status
Simulation time 8388708699 ps
CPU time 12.78 seconds
Started May 21 01:12:26 PM PDT 24
Finished May 21 01:12:40 PM PDT 24
Peak memory 205408 kb
Host smart-e4fe62b7-2a8b-4aa5-878e-9b05dc8bb964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31081
46026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3108146026
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.490633583
Short name T198
Test name
Test status
Simulation time 8381809781 ps
CPU time 12.25 seconds
Started May 21 01:12:25 PM PDT 24
Finished May 21 01:12:38 PM PDT 24
Peak memory 205420 kb
Host smart-11398218-f750-45fb-a513-49db9195d003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49063
3583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.490633583
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_eop_single_bit_handling.3887482795
Short name T290
Test name
Test status
Simulation time 8403070823 ps
CPU time 11.67 seconds
Started May 21 01:12:28 PM PDT 24
Finished May 21 01:12:40 PM PDT 24
Peak memory 205400 kb
Host smart-22663815-623b-4289-8408-3b5831705668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38874
82795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_eop_single_bit_handling.3887482795
Directory /workspace/46.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.2395090642
Short name T748
Test name
Test status
Simulation time 8369281300 ps
CPU time 12.36 seconds
Started May 21 01:12:24 PM PDT 24
Finished May 21 01:12:38 PM PDT 24
Peak memory 205388 kb
Host smart-3f23b0d7-725c-4d65-9d18-9a4349801dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23950
90642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.2395090642
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1465984531
Short name T1368
Test name
Test status
Simulation time 8368018400 ps
CPU time 14.31 seconds
Started May 21 01:12:33 PM PDT 24
Finished May 21 01:12:49 PM PDT 24
Peak memory 205324 kb
Host smart-56420a14-e140-4545-b274-82db3f67ba41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14659
84531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1465984531
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.3069038585
Short name T1150
Test name
Test status
Simulation time 15335206219 ps
CPU time 30.73 seconds
Started May 21 01:12:24 PM PDT 24
Finished May 21 01:12:56 PM PDT 24
Peak memory 205392 kb
Host smart-234fb007-50c0-419c-a4e8-a8107b2fd37a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30690
38585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.3069038585
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.3191778686
Short name T431
Test name
Test status
Simulation time 8404702414 ps
CPU time 11.64 seconds
Started May 21 01:12:36 PM PDT 24
Finished May 21 01:12:49 PM PDT 24
Peak memory 205356 kb
Host smart-59e6b9ac-46b0-4d74-9f9b-bd29388f9b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31917
78686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3191778686
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.3183248283
Short name T1375
Test name
Test status
Simulation time 8456783626 ps
CPU time 11.96 seconds
Started May 21 01:12:31 PM PDT 24
Finished May 21 01:12:45 PM PDT 24
Peak memory 205348 kb
Host smart-03c67281-d43a-460d-813b-d5389c884838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31832
48283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.3183248283
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.3210510701
Short name T498
Test name
Test status
Simulation time 8373534879 ps
CPU time 13.18 seconds
Started May 21 01:12:27 PM PDT 24
Finished May 21 01:12:41 PM PDT 24
Peak memory 205452 kb
Host smart-5d9a162f-f29d-4bc2-b457-278edfccd074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32105
10701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.3210510701
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.2997710862
Short name T1116
Test name
Test status
Simulation time 8373393800 ps
CPU time 12.05 seconds
Started May 21 01:12:24 PM PDT 24
Finished May 21 01:12:38 PM PDT 24
Peak memory 205316 kb
Host smart-072e60c1-6594-4581-afd9-a3d4b6eab42f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29977
10862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.2997710862
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.1173297471
Short name T1677
Test name
Test status
Simulation time 8379946930 ps
CPU time 12.24 seconds
Started May 21 01:12:25 PM PDT 24
Finished May 21 01:12:39 PM PDT 24
Peak memory 205332 kb
Host smart-87b51a0a-8d4e-40a2-a68d-0547ae72e392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11732
97471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1173297471
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.4281632601
Short name T304
Test name
Test status
Simulation time 8388903374 ps
CPU time 12.89 seconds
Started May 21 01:12:23 PM PDT 24
Finished May 21 01:12:38 PM PDT 24
Peak memory 205308 kb
Host smart-e2e4ee31-3cb4-4907-b32b-63995638373c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42816
32601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.4281632601
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.957424795
Short name T180
Test name
Test status
Simulation time 8441883397 ps
CPU time 11.18 seconds
Started May 21 01:12:22 PM PDT 24
Finished May 21 01:12:34 PM PDT 24
Peak memory 205392 kb
Host smart-11a2b435-2ae4-4c07-8ff8-3ad62fa131bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95742
4795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.957424795
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.1637826768
Short name T869
Test name
Test status
Simulation time 8379346421 ps
CPU time 11.21 seconds
Started May 21 01:12:31 PM PDT 24
Finished May 21 01:12:44 PM PDT 24
Peak memory 205356 kb
Host smart-6c22c9f0-afcd-4971-92e7-47fb43be6c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16378
26768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.1637826768
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2144902624
Short name T508
Test name
Test status
Simulation time 8389222644 ps
CPU time 12.23 seconds
Started May 21 01:12:23 PM PDT 24
Finished May 21 01:12:37 PM PDT 24
Peak memory 205376 kb
Host smart-e740201a-f24e-4dc1-bf9b-757cffd43def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21449
02624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2144902624
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.2230098719
Short name T603
Test name
Test status
Simulation time 8477526171 ps
CPU time 11.66 seconds
Started May 21 01:12:37 PM PDT 24
Finished May 21 01:12:51 PM PDT 24
Peak memory 205276 kb
Host smart-ee102526-af77-4eef-9c57-10ca27004dec
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2230098719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.2230098719
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.582079445
Short name T810
Test name
Test status
Simulation time 8380372747 ps
CPU time 11.98 seconds
Started May 21 01:12:36 PM PDT 24
Finished May 21 01:12:49 PM PDT 24
Peak memory 205412 kb
Host smart-95230eb7-8316-4db9-bae7-b5fad38f3ef0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=582079445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.582079445
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.599500137
Short name T1656
Test name
Test status
Simulation time 8477064224 ps
CPU time 11.95 seconds
Started May 21 01:12:43 PM PDT 24
Finished May 21 01:12:58 PM PDT 24
Peak memory 205388 kb
Host smart-1d564ae7-a3e4-44ad-8005-b49a1a4b85d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59950
0137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.599500137
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.4264227264
Short name T530
Test name
Test status
Simulation time 8379639708 ps
CPU time 11.9 seconds
Started May 21 01:12:30 PM PDT 24
Finished May 21 01:12:44 PM PDT 24
Peak memory 205360 kb
Host smart-21828e95-c783-47f8-a09e-aa0a7f623304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42642
27264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.4264227264
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.1832070741
Short name T576
Test name
Test status
Simulation time 8843810838 ps
CPU time 12.64 seconds
Started May 21 01:12:32 PM PDT 24
Finished May 21 01:12:47 PM PDT 24
Peak memory 205324 kb
Host smart-e71a835d-4521-424b-8b26-579a96b89433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18320
70741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.1832070741
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.3232168578
Short name T1698
Test name
Test status
Simulation time 8368189624 ps
CPU time 14.12 seconds
Started May 21 01:12:41 PM PDT 24
Finished May 21 01:12:57 PM PDT 24
Peak memory 205356 kb
Host smart-28af7e31-3aea-4569-a1b1-5adcfdd749d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32321
68578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.3232168578
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.3460697048
Short name T1241
Test name
Test status
Simulation time 8376671730 ps
CPU time 13.12 seconds
Started May 21 01:12:32 PM PDT 24
Finished May 21 01:12:47 PM PDT 24
Peak memory 205368 kb
Host smart-905ef74a-8e39-4c3c-a0df-3288a1831209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34606
97048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3460697048
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.1591978583
Short name T989
Test name
Test status
Simulation time 9147263238 ps
CPU time 12.84 seconds
Started May 21 01:12:31 PM PDT 24
Finished May 21 01:12:46 PM PDT 24
Peak memory 205384 kb
Host smart-cfcbf563-97ae-42c5-a784-d7774234e36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15919
78583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.1591978583
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.1882350897
Short name T550
Test name
Test status
Simulation time 8495099653 ps
CPU time 11.73 seconds
Started May 21 01:12:33 PM PDT 24
Finished May 21 01:12:46 PM PDT 24
Peak memory 205312 kb
Host smart-af865010-6690-4c76-badb-b1057317b36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18823
50897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.1882350897
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.2745110658
Short name T1290
Test name
Test status
Simulation time 8422108095 ps
CPU time 13.04 seconds
Started May 21 01:12:39 PM PDT 24
Finished May 21 01:12:54 PM PDT 24
Peak memory 205220 kb
Host smart-04bbc9d4-388d-41a7-80ae-a4ff4a383ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27451
10658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.2745110658
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.3073486009
Short name T1603
Test name
Test status
Simulation time 8384525068 ps
CPU time 13.01 seconds
Started May 21 01:12:44 PM PDT 24
Finished May 21 01:12:59 PM PDT 24
Peak memory 205276 kb
Host smart-43296f0f-c3eb-4a71-b8f5-7ce9755eb536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30734
86009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.3073486009
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.1490525121
Short name T1122
Test name
Test status
Simulation time 8477462570 ps
CPU time 14.03 seconds
Started May 21 01:12:31 PM PDT 24
Finished May 21 01:12:47 PM PDT 24
Peak memory 205392 kb
Host smart-493389a6-4e3f-47a8-a2a8-f4c1c147402c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14905
25121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.1490525121
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.3898503681
Short name T778
Test name
Test status
Simulation time 11491942398 ps
CPU time 14.68 seconds
Started May 21 01:12:33 PM PDT 24
Finished May 21 01:12:49 PM PDT 24
Peak memory 205408 kb
Host smart-87e9cc0d-0afe-4fc1-9fe5-316f1435193d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38985
03681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.3898503681
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.2753236969
Short name T504
Test name
Test status
Simulation time 8416936392 ps
CPU time 12.66 seconds
Started May 21 01:12:32 PM PDT 24
Finished May 21 01:12:47 PM PDT 24
Peak memory 205352 kb
Host smart-d7949863-7a55-4afe-a438-6769e3527126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27532
36969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.2753236969
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.2357507632
Short name T1114
Test name
Test status
Simulation time 8405187181 ps
CPU time 10.77 seconds
Started May 21 01:12:42 PM PDT 24
Finished May 21 01:12:55 PM PDT 24
Peak memory 205372 kb
Host smart-ee3102be-0200-4230-8bf1-f8eed707873f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23575
07632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.2357507632
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.2727386831
Short name T360
Test name
Test status
Simulation time 8417580627 ps
CPU time 13.21 seconds
Started May 21 01:12:37 PM PDT 24
Finished May 21 01:12:53 PM PDT 24
Peak memory 205384 kb
Host smart-164ae087-c2fe-497c-9b33-f8db3bae3258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27273
86831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.2727386831
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.726951582
Short name T1318
Test name
Test status
Simulation time 8395737297 ps
CPU time 11.8 seconds
Started May 21 01:12:37 PM PDT 24
Finished May 21 01:12:51 PM PDT 24
Peak memory 205328 kb
Host smart-27bb1cdd-a577-4ce9-8aef-e13f9851929f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72695
1582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.726951582
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.486451012
Short name T1219
Test name
Test status
Simulation time 8403248597 ps
CPU time 11.13 seconds
Started May 21 01:12:44 PM PDT 24
Finished May 21 01:12:57 PM PDT 24
Peak memory 205360 kb
Host smart-24cfe087-9085-4d8a-bff1-93fb60b46033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48645
1012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.486451012
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.2965480900
Short name T50
Test name
Test status
Simulation time 8405221039 ps
CPU time 12 seconds
Started May 21 01:12:36 PM PDT 24
Finished May 21 01:12:49 PM PDT 24
Peak memory 205376 kb
Host smart-55f37db3-c81a-4d7d-bc66-66ccdc3d0d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29654
80900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.2965480900
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_eop_single_bit_handling.2341002854
Short name T1177
Test name
Test status
Simulation time 8379041381 ps
CPU time 10.79 seconds
Started May 21 01:13:34 PM PDT 24
Finished May 21 01:13:45 PM PDT 24
Peak memory 205412 kb
Host smart-16494567-7a59-4884-a677-e28cb9c8115b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23410
02854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_eop_single_bit_handling.2341002854
Directory /workspace/47.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.3531389735
Short name T481
Test name
Test status
Simulation time 8371091969 ps
CPU time 11.86 seconds
Started May 21 01:12:40 PM PDT 24
Finished May 21 01:12:53 PM PDT 24
Peak memory 205380 kb
Host smart-95abd785-40ca-471f-bd8f-44ef6ec12ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35313
89735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.3531389735
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.1384240618
Short name T658
Test name
Test status
Simulation time 8374067576 ps
CPU time 11.48 seconds
Started May 21 01:12:36 PM PDT 24
Finished May 21 01:12:49 PM PDT 24
Peak memory 205288 kb
Host smart-e0120736-0722-4976-8dc0-8911c3904b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13842
40618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.1384240618
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2514242749
Short name T1231
Test name
Test status
Simulation time 17994003133 ps
CPU time 34.62 seconds
Started May 21 01:12:38 PM PDT 24
Finished May 21 01:13:14 PM PDT 24
Peak memory 205416 kb
Host smart-1962dcf3-0c0d-4663-bf67-e1e71ec9a403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25142
42749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2514242749
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.3521020615
Short name T1608
Test name
Test status
Simulation time 8436249257 ps
CPU time 12.63 seconds
Started May 21 01:12:39 PM PDT 24
Finished May 21 01:12:53 PM PDT 24
Peak memory 205268 kb
Host smart-5d07f57c-8537-46bf-969c-fa2c0898cdbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35210
20615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.3521020615
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.710475502
Short name T1248
Test name
Test status
Simulation time 8450203736 ps
CPU time 12.51 seconds
Started May 21 01:12:37 PM PDT 24
Finished May 21 01:12:52 PM PDT 24
Peak memory 205400 kb
Host smart-a3e76485-0583-4b79-9ba2-de7723fc8cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71047
5502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.710475502
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.1711763074
Short name T1547
Test name
Test status
Simulation time 8413540254 ps
CPU time 11.08 seconds
Started May 21 01:12:37 PM PDT 24
Finished May 21 01:12:51 PM PDT 24
Peak memory 205332 kb
Host smart-ccd815e1-1276-4fee-b57b-98fd34e6c769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17117
63074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.1711763074
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.3390272358
Short name T1582
Test name
Test status
Simulation time 8381491842 ps
CPU time 11.21 seconds
Started May 21 01:12:37 PM PDT 24
Finished May 21 01:12:50 PM PDT 24
Peak memory 205396 kb
Host smart-fcfe4cf0-353e-4f9a-b228-3cf669890f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33902
72358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.3390272358
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.1790430617
Short name T1614
Test name
Test status
Simulation time 8378856590 ps
CPU time 11.13 seconds
Started May 21 01:12:40 PM PDT 24
Finished May 21 01:12:52 PM PDT 24
Peak memory 205292 kb
Host smart-e73f1ff2-5d2e-4cf4-9612-a1a392d4021a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17904
30617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1790430617
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.4112866905
Short name T1440
Test name
Test status
Simulation time 8376919553 ps
CPU time 14.51 seconds
Started May 21 01:12:37 PM PDT 24
Finished May 21 01:12:54 PM PDT 24
Peak memory 205380 kb
Host smart-e29bcb00-57a1-48b0-b727-8588bc7ee771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41128
66905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.4112866905
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.766101716
Short name T1605
Test name
Test status
Simulation time 8436778778 ps
CPU time 11.82 seconds
Started May 21 01:12:31 PM PDT 24
Finished May 21 01:12:45 PM PDT 24
Peak memory 205264 kb
Host smart-b4410f75-24e3-453d-bbf0-14d0c7754c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76610
1716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.766101716
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.4231738523
Short name T1486
Test name
Test status
Simulation time 8500427332 ps
CPU time 11.64 seconds
Started May 21 01:12:37 PM PDT 24
Finished May 21 01:12:51 PM PDT 24
Peak memory 205376 kb
Host smart-1f9ff509-3cae-43b5-aca5-dec8278d76c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42317
38523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.4231738523
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.3245255219
Short name T277
Test name
Test status
Simulation time 8440598014 ps
CPU time 12.9 seconds
Started May 21 01:12:41 PM PDT 24
Finished May 21 01:12:56 PM PDT 24
Peak memory 205388 kb
Host smart-7c531388-3908-4193-a22a-3aeee187e30d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32452
55219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.3245255219
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.1633119906
Short name T381
Test name
Test status
Simulation time 8473572210 ps
CPU time 11.45 seconds
Started May 21 01:12:51 PM PDT 24
Finished May 21 01:13:06 PM PDT 24
Peak memory 205320 kb
Host smart-6061da9d-5b0a-400c-abe9-aadb3df578a8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1633119906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.1633119906
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.3237702570
Short name T1430
Test name
Test status
Simulation time 8378458009 ps
CPU time 13.77 seconds
Started May 21 01:12:51 PM PDT 24
Finished May 21 01:13:08 PM PDT 24
Peak memory 205356 kb
Host smart-df3ff180-92c3-435d-9b8c-044cf549de95
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3237702570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.3237702570
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.527651669
Short name T1216
Test name
Test status
Simulation time 8465715752 ps
CPU time 13.07 seconds
Started May 21 01:12:51 PM PDT 24
Finished May 21 01:13:07 PM PDT 24
Peak memory 205340 kb
Host smart-dc316dc6-fef0-4189-9388-ba86825ed12c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52765
1669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.527651669
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.3200908657
Short name T1211
Test name
Test status
Simulation time 8379105526 ps
CPU time 11.16 seconds
Started May 21 01:12:43 PM PDT 24
Finished May 21 01:12:57 PM PDT 24
Peak memory 205304 kb
Host smart-e01c5cd5-06d0-482d-87ea-b4a31b0d983a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32009
08657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.3200908657
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.1639430733
Short name T1500
Test name
Test status
Simulation time 9232967027 ps
CPU time 13.84 seconds
Started May 21 01:12:44 PM PDT 24
Finished May 21 01:13:00 PM PDT 24
Peak memory 205332 kb
Host smart-9aba72b4-b8b5-4346-a5b3-8cdca4f40c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16394
30733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.1639430733
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.3247379943
Short name T484
Test name
Test status
Simulation time 8409538277 ps
CPU time 11.54 seconds
Started May 21 01:12:45 PM PDT 24
Finished May 21 01:12:59 PM PDT 24
Peak memory 205312 kb
Host smart-b09b8a50-7fae-4821-b33c-88bdac989831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32473
79943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.3247379943
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.884074343
Short name T1285
Test name
Test status
Simulation time 8372624674 ps
CPU time 12.6 seconds
Started May 21 01:12:42 PM PDT 24
Finished May 21 01:12:58 PM PDT 24
Peak memory 205344 kb
Host smart-22288cd2-4b5c-4bee-87ab-510799288c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88407
4343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.884074343
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.1536365384
Short name T570
Test name
Test status
Simulation time 8500293059 ps
CPU time 12.13 seconds
Started May 21 01:12:40 PM PDT 24
Finished May 21 01:12:54 PM PDT 24
Peak memory 205292 kb
Host smart-9157a02b-e9a1-4bde-8261-3b7bcfd9fa49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15363
65384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1536365384
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.2285465300
Short name T1136
Test name
Test status
Simulation time 8425799211 ps
CPU time 11.39 seconds
Started May 21 01:12:47 PM PDT 24
Finished May 21 01:13:00 PM PDT 24
Peak memory 205384 kb
Host smart-cfc9e6fe-41c8-4c5f-a0cb-0e2e95404c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22854
65300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.2285465300
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.3503356591
Short name T1019
Test name
Test status
Simulation time 8400007780 ps
CPU time 11.69 seconds
Started May 21 01:12:51 PM PDT 24
Finished May 21 01:13:06 PM PDT 24
Peak memory 205292 kb
Host smart-0aecdcd2-1420-4981-a347-805f1cc3c1c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35033
56591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.3503356591
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.210823258
Short name T291
Test name
Test status
Simulation time 8446840143 ps
CPU time 11.69 seconds
Started May 21 01:12:43 PM PDT 24
Finished May 21 01:12:57 PM PDT 24
Peak memory 205408 kb
Host smart-3a727e50-c7a4-4230-a413-a413e752ba48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21082
3258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.210823258
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.2836829029
Short name T880
Test name
Test status
Simulation time 8422504387 ps
CPU time 12.06 seconds
Started May 21 01:12:42 PM PDT 24
Finished May 21 01:12:57 PM PDT 24
Peak memory 205376 kb
Host smart-ef0f0eda-8f36-44bb-9589-462252e3b11f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28368
29029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.2836829029
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.1484038202
Short name T6
Test name
Test status
Simulation time 11565713592 ps
CPU time 14.08 seconds
Started May 21 01:12:44 PM PDT 24
Finished May 21 01:13:01 PM PDT 24
Peak memory 205364 kb
Host smart-b15105ed-cfcb-48fa-9d1c-f9388d5f9ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14840
38202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.1484038202
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3703851453
Short name T455
Test name
Test status
Simulation time 8453565441 ps
CPU time 10.97 seconds
Started May 21 01:12:42 PM PDT 24
Finished May 21 01:12:56 PM PDT 24
Peak memory 205404 kb
Host smart-f14204ad-7988-4a0f-b9bc-cd01ff3e1c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37038
51453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3703851453
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2813930388
Short name T1010
Test name
Test status
Simulation time 8367873808 ps
CPU time 13.87 seconds
Started May 21 01:12:42 PM PDT 24
Finished May 21 01:12:58 PM PDT 24
Peak memory 205384 kb
Host smart-3716ed7a-de24-4a99-af35-c1b10e0ab1e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28139
30388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2813930388
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.3692073797
Short name T131
Test name
Test status
Simulation time 8447853529 ps
CPU time 11.7 seconds
Started May 21 01:12:48 PM PDT 24
Finished May 21 01:13:01 PM PDT 24
Peak memory 205308 kb
Host smart-d138c781-57fc-43ca-b94a-7d3ee0118786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36920
73797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.3692073797
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.2966519720
Short name T670
Test name
Test status
Simulation time 8414434057 ps
CPU time 13.91 seconds
Started May 21 01:12:43 PM PDT 24
Finished May 21 01:13:00 PM PDT 24
Peak memory 205300 kb
Host smart-af4dd9c0-e94a-4f5a-bda0-47aab8710089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29665
19720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.2966519720
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.704144824
Short name T1472
Test name
Test status
Simulation time 8424622137 ps
CPU time 13.21 seconds
Started May 21 01:12:44 PM PDT 24
Finished May 21 01:13:00 PM PDT 24
Peak memory 205264 kb
Host smart-5c034c0e-01cd-40c6-83cc-443c0278814b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70414
4824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.704144824
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2837258221
Short name T518
Test name
Test status
Simulation time 8398948012 ps
CPU time 10.62 seconds
Started May 21 01:12:42 PM PDT 24
Finished May 21 01:12:55 PM PDT 24
Peak memory 205424 kb
Host smart-62aa5f41-debd-4950-99e0-2fb11dd0a7ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28372
58221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2837258221
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.2149395175
Short name T171
Test name
Test status
Simulation time 8411430386 ps
CPU time 11.1 seconds
Started May 21 01:12:43 PM PDT 24
Finished May 21 01:12:57 PM PDT 24
Peak memory 205380 kb
Host smart-0cc0bd19-52b8-455a-87b0-6e3667f6d32d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21493
95175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.2149395175
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_eop_single_bit_handling.3764359860
Short name T1021
Test name
Test status
Simulation time 8408563041 ps
CPU time 11.97 seconds
Started May 21 01:12:45 PM PDT 24
Finished May 21 01:12:59 PM PDT 24
Peak memory 205616 kb
Host smart-8a63e814-6eb0-449d-835b-31292c0857e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37643
59860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_eop_single_bit_handling.3764359860
Directory /workspace/48.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.4163754419
Short name T1398
Test name
Test status
Simulation time 8393889349 ps
CPU time 11.52 seconds
Started May 21 01:12:47 PM PDT 24
Finished May 21 01:13:00 PM PDT 24
Peak memory 205408 kb
Host smart-d6993cc7-c74f-4cad-b866-fed79a0042d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41637
54419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.4163754419
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.2716944162
Short name T31
Test name
Test status
Simulation time 8366483391 ps
CPU time 11.62 seconds
Started May 21 01:12:43 PM PDT 24
Finished May 21 01:12:57 PM PDT 24
Peak memory 205220 kb
Host smart-a3ec289b-0fc1-4d4e-90db-2170d9e55baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27169
44162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.2716944162
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2528764275
Short name T882
Test name
Test status
Simulation time 8388001053 ps
CPU time 12.51 seconds
Started May 21 01:12:42 PM PDT 24
Finished May 21 01:12:57 PM PDT 24
Peak memory 205348 kb
Host smart-02a17819-c559-4b9e-8500-c59caecccc2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25287
64275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2528764275
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.2791714956
Short name T542
Test name
Test status
Simulation time 8429400275 ps
CPU time 11.9 seconds
Started May 21 01:12:46 PM PDT 24
Finished May 21 01:13:00 PM PDT 24
Peak memory 205404 kb
Host smart-98e859b0-56e4-4e6e-bdca-4ff33be3d824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27917
14956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2791714956
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.1491147003
Short name T1364
Test name
Test status
Simulation time 8393378255 ps
CPU time 12.58 seconds
Started May 21 01:12:48 PM PDT 24
Finished May 21 01:13:02 PM PDT 24
Peak memory 205320 kb
Host smart-52c2f92a-1783-4041-875f-d9d66b0624ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14911
47003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.1491147003
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.651505293
Short name T1625
Test name
Test status
Simulation time 8432015768 ps
CPU time 11.61 seconds
Started May 21 01:12:42 PM PDT 24
Finished May 21 01:12:56 PM PDT 24
Peak memory 205328 kb
Host smart-b161d316-2248-4182-8147-cec2533549f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65150
5293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.651505293
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3880612361
Short name T1293
Test name
Test status
Simulation time 8382609851 ps
CPU time 11.74 seconds
Started May 21 01:12:46 PM PDT 24
Finished May 21 01:13:00 PM PDT 24
Peak memory 205276 kb
Host smart-66743e9c-3ab8-4f59-b945-c437df014405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38806
12361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3880612361
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.1825007188
Short name T1692
Test name
Test status
Simulation time 8376551563 ps
CPU time 11.9 seconds
Started May 21 01:12:44 PM PDT 24
Finished May 21 01:12:58 PM PDT 24
Peak memory 205316 kb
Host smart-ce4b5cd7-5141-47d1-95f5-a679d545e1a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18250
07188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1825007188
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.3239190601
Short name T1214
Test name
Test status
Simulation time 8453454708 ps
CPU time 13.3 seconds
Started May 21 01:12:42 PM PDT 24
Finished May 21 01:12:57 PM PDT 24
Peak memory 205196 kb
Host smart-0b1c6b16-5982-4339-8d17-b21534473357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32391
90601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.3239190601
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.1296992403
Short name T893
Test name
Test status
Simulation time 8427209700 ps
CPU time 12.2 seconds
Started May 21 01:12:46 PM PDT 24
Finished May 21 01:13:00 PM PDT 24
Peak memory 205348 kb
Host smart-2dcac405-6c8e-4a70-b697-c182613f7e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12969
92403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.1296992403
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.855402166
Short name T361
Test name
Test status
Simulation time 8402943828 ps
CPU time 11.06 seconds
Started May 21 01:12:47 PM PDT 24
Finished May 21 01:12:59 PM PDT 24
Peak memory 205348 kb
Host smart-d137b5dc-93e1-4e63-b0e2-61cd61ed1b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85540
2166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.855402166
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.3391260374
Short name T947
Test name
Test status
Simulation time 8462636608 ps
CPU time 13.96 seconds
Started May 21 01:12:54 PM PDT 24
Finished May 21 01:13:11 PM PDT 24
Peak memory 205372 kb
Host smart-c552864b-39db-4c20-b535-0bc10dd7ed92
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3391260374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.3391260374
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.491340386
Short name T1224
Test name
Test status
Simulation time 8394456564 ps
CPU time 11.42 seconds
Started May 21 01:12:55 PM PDT 24
Finished May 21 01:13:09 PM PDT 24
Peak memory 205264 kb
Host smart-6664fd59-3d41-47ec-b05c-e93cd6394232
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=491340386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.491340386
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.2165388423
Short name T1334
Test name
Test status
Simulation time 8439608285 ps
CPU time 12.89 seconds
Started May 21 01:12:53 PM PDT 24
Finished May 21 01:13:09 PM PDT 24
Peak memory 205344 kb
Host smart-8ea023f4-c31f-4cbd-a27b-2f7acf59ec1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21653
88423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.2165388423
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3336350905
Short name T696
Test name
Test status
Simulation time 8378865864 ps
CPU time 12.44 seconds
Started May 21 01:12:51 PM PDT 24
Finished May 21 01:13:07 PM PDT 24
Peak memory 205396 kb
Host smart-85300303-15b9-4e09-a1b5-9b5f222662b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33363
50905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3336350905
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.4142080599
Short name T60
Test name
Test status
Simulation time 8373752023 ps
CPU time 11.8 seconds
Started May 21 01:13:35 PM PDT 24
Finished May 21 01:13:47 PM PDT 24
Peak memory 205368 kb
Host smart-b2564d82-283b-443d-be57-bfd82e8584ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41420
80599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.4142080599
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.3364871816
Short name T1686
Test name
Test status
Simulation time 8388245856 ps
CPU time 10.87 seconds
Started May 21 01:12:52 PM PDT 24
Finished May 21 01:13:06 PM PDT 24
Peak memory 205296 kb
Host smart-80a1f88f-9af4-47c6-beea-86219b5db9cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33648
71816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.3364871816
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.781172738
Short name T1537
Test name
Test status
Simulation time 8421338291 ps
CPU time 13.21 seconds
Started May 21 01:12:51 PM PDT 24
Finished May 21 01:13:08 PM PDT 24
Peak memory 205336 kb
Host smart-c9cbf19b-e2d5-423f-b5d4-7760e28f1eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78117
2738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.781172738
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.2136971715
Short name T1255
Test name
Test status
Simulation time 9049163696 ps
CPU time 12.43 seconds
Started May 21 01:12:48 PM PDT 24
Finished May 21 01:13:02 PM PDT 24
Peak memory 205280 kb
Host smart-c885b356-277c-4b73-b5e5-7d07adb6a113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21369
71715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.2136971715
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.3941526332
Short name T1584
Test name
Test status
Simulation time 8547279769 ps
CPU time 13.28 seconds
Started May 21 01:12:51 PM PDT 24
Finished May 21 01:13:07 PM PDT 24
Peak memory 205288 kb
Host smart-f7459744-2ffb-4d00-8243-9276400e3d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39415
26332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3941526332
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.574064578
Short name T1550
Test name
Test status
Simulation time 8438257419 ps
CPU time 11.45 seconds
Started May 21 01:12:54 PM PDT 24
Finished May 21 01:13:08 PM PDT 24
Peak memory 205324 kb
Host smart-2e7ff86f-bc37-4dc0-87c6-4103c175cd94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57406
4578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.574064578
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.33189695
Short name T1701
Test name
Test status
Simulation time 8372158616 ps
CPU time 12.72 seconds
Started May 21 01:12:57 PM PDT 24
Finished May 21 01:13:11 PM PDT 24
Peak memory 205360 kb
Host smart-0bbcf111-68d7-481e-bed3-84d9ae3ca68d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33189
695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.33189695
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3635113255
Short name T1681
Test name
Test status
Simulation time 8416626880 ps
CPU time 11.72 seconds
Started May 21 01:12:50 PM PDT 24
Finished May 21 01:13:05 PM PDT 24
Peak memory 205396 kb
Host smart-debae1a1-3b14-404f-89e3-30b64eb9b911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36351
13255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3635113255
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.1719874542
Short name T1357
Test name
Test status
Simulation time 11525399952 ps
CPU time 13.8 seconds
Started May 21 01:12:47 PM PDT 24
Finished May 21 01:13:02 PM PDT 24
Peak memory 205352 kb
Host smart-e92e1ab7-8808-4bf1-acb6-0a0f0a3c57e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17198
74542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.1719874542
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.4012476417
Short name T979
Test name
Test status
Simulation time 8427223222 ps
CPU time 11.24 seconds
Started May 21 01:12:52 PM PDT 24
Finished May 21 01:13:07 PM PDT 24
Peak memory 205340 kb
Host smart-ea777bc1-0bac-464e-8d76-89662f8b4679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40124
76417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.4012476417
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3023008109
Short name T923
Test name
Test status
Simulation time 8375838928 ps
CPU time 11.91 seconds
Started May 21 01:12:49 PM PDT 24
Finished May 21 01:13:04 PM PDT 24
Peak memory 205420 kb
Host smart-95c093bc-facc-4615-8080-0c4bedbff85b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30230
08109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3023008109
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.81802002
Short name T1593
Test name
Test status
Simulation time 8415649616 ps
CPU time 11.22 seconds
Started May 21 01:12:48 PM PDT 24
Finished May 21 01:13:01 PM PDT 24
Peak memory 205392 kb
Host smart-fa4349bb-376f-4e71-8bfc-4065ab815066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81802
002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.81802002
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.3127351910
Short name T308
Test name
Test status
Simulation time 8416343227 ps
CPU time 12.46 seconds
Started May 21 01:13:00 PM PDT 24
Finished May 21 01:13:14 PM PDT 24
Peak memory 205320 kb
Host smart-8d6c2126-2837-4e85-bb38-0e71d5bcb005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31273
51910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.3127351910
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1951683018
Short name T1643
Test name
Test status
Simulation time 8377654330 ps
CPU time 13.09 seconds
Started May 21 01:12:58 PM PDT 24
Finished May 21 01:13:12 PM PDT 24
Peak memory 205364 kb
Host smart-11c9ba09-d343-42ca-8792-d179d1ff4c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19516
83018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1951683018
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2969861706
Short name T584
Test name
Test status
Simulation time 8403774523 ps
CPU time 11.89 seconds
Started May 21 01:12:55 PM PDT 24
Finished May 21 01:13:10 PM PDT 24
Peak memory 205348 kb
Host smart-18e5b5a9-eb7f-4684-abee-ee1d691d62a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29698
61706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2969861706
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.3937337715
Short name T172
Test name
Test status
Simulation time 8403062272 ps
CPU time 11.49 seconds
Started May 21 01:12:59 PM PDT 24
Finished May 21 01:13:11 PM PDT 24
Peak memory 205312 kb
Host smart-e92ca173-b332-4405-abcf-d1550ad306d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39373
37715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.3937337715
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_eop_single_bit_handling.1618651075
Short name T1344
Test name
Test status
Simulation time 8432571824 ps
CPU time 11.29 seconds
Started May 21 01:13:00 PM PDT 24
Finished May 21 01:13:12 PM PDT 24
Peak memory 205348 kb
Host smart-2868fd10-c6a9-4310-bb3b-dfbf4f56ae4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16186
51075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_eop_single_bit_handling.1618651075
Directory /workspace/49.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3633411481
Short name T1665
Test name
Test status
Simulation time 8407216744 ps
CPU time 12.42 seconds
Started May 21 01:12:55 PM PDT 24
Finished May 21 01:13:10 PM PDT 24
Peak memory 205348 kb
Host smart-662eac0b-ec5a-4027-ac88-f0931553e8b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36334
11481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3633411481
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1530069715
Short name T1034
Test name
Test status
Simulation time 8376437019 ps
CPU time 11.46 seconds
Started May 21 01:12:55 PM PDT 24
Finished May 21 01:13:09 PM PDT 24
Peak memory 205372 kb
Host smart-c4d9f322-b028-445a-b4b1-fec915493e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15300
69715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1530069715
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.1341423412
Short name T13
Test name
Test status
Simulation time 15502986746 ps
CPU time 28.79 seconds
Started May 21 01:12:56 PM PDT 24
Finished May 21 01:13:27 PM PDT 24
Peak memory 205416 kb
Host smart-75323cff-3a90-4d4d-8ca5-0de09eb6d871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13414
23412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.1341423412
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1875232490
Short name T983
Test name
Test status
Simulation time 8414860534 ps
CPU time 12.9 seconds
Started May 21 01:13:34 PM PDT 24
Finished May 21 01:13:47 PM PDT 24
Peak memory 205328 kb
Host smart-075129a6-aa83-49a8-9bae-511f1a154581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18752
32490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1875232490
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.429422617
Short name T677
Test name
Test status
Simulation time 8460259956 ps
CPU time 12.13 seconds
Started May 21 01:12:54 PM PDT 24
Finished May 21 01:13:09 PM PDT 24
Peak memory 205296 kb
Host smart-fda944d9-5074-4609-896c-11146ed236b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42942
2617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.429422617
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.2734081928
Short name T1719
Test name
Test status
Simulation time 8419585008 ps
CPU time 14.87 seconds
Started May 21 01:12:55 PM PDT 24
Finished May 21 01:13:12 PM PDT 24
Peak memory 205420 kb
Host smart-856f5f39-f179-4a61-98ca-521e233da9d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27340
81928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.2734081928
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.3622428956
Short name T1190
Test name
Test status
Simulation time 8369328043 ps
CPU time 12.8 seconds
Started May 21 01:13:37 PM PDT 24
Finished May 21 01:13:50 PM PDT 24
Peak memory 205344 kb
Host smart-bfd9d935-fae1-401b-98f2-497a9e4b902b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36224
28956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.3622428956
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.512440497
Short name T166
Test name
Test status
Simulation time 8382071089 ps
CPU time 11.74 seconds
Started May 21 01:12:58 PM PDT 24
Finished May 21 01:13:11 PM PDT 24
Peak memory 205344 kb
Host smart-730805c8-2464-4dad-8db6-e2836b8f5017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51244
0497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.512440497
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.484074813
Short name T413
Test name
Test status
Simulation time 8382905533 ps
CPU time 13.97 seconds
Started May 21 01:12:55 PM PDT 24
Finished May 21 01:13:12 PM PDT 24
Peak memory 205252 kb
Host smart-75682c18-8bc7-40e6-b7e3-33244f320bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48407
4813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.484074813
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.1258277753
Short name T164
Test name
Test status
Simulation time 8520085133 ps
CPU time 13.03 seconds
Started May 21 01:12:51 PM PDT 24
Finished May 21 01:13:07 PM PDT 24
Peak memory 205396 kb
Host smart-21275ba1-20c6-41db-893a-01ffd38b7812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12582
77753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1258277753
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.1457544968
Short name T854
Test name
Test status
Simulation time 8408385114 ps
CPU time 12.5 seconds
Started May 21 01:12:58 PM PDT 24
Finished May 21 01:13:12 PM PDT 24
Peak memory 205308 kb
Host smart-85eb8b4b-deba-42a8-9550-d095c0c1e9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14575
44968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.1457544968
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.3299802180
Short name T772
Test name
Test status
Simulation time 8426770237 ps
CPU time 12.56 seconds
Started May 21 01:12:57 PM PDT 24
Finished May 21 01:13:11 PM PDT 24
Peak memory 205272 kb
Host smart-cb347225-48d0-4526-89f6-0ddcb9dc6bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32998
02180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.3299802180
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.2372941289
Short name T619
Test name
Test status
Simulation time 8478763132 ps
CPU time 12.65 seconds
Started May 21 01:05:57 PM PDT 24
Finished May 21 01:06:10 PM PDT 24
Peak memory 205440 kb
Host smart-52bb919b-44a2-449e-a353-2e932b1fe9b9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2372941289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.2372941289
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.3592906119
Short name T1084
Test name
Test status
Simulation time 8382018604 ps
CPU time 11.7 seconds
Started May 21 01:05:58 PM PDT 24
Finished May 21 01:06:10 PM PDT 24
Peak memory 205408 kb
Host smart-f83f24f3-4064-4d29-b1aa-4c81cd0ded36
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3592906119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.3592906119
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.2040349714
Short name T851
Test name
Test status
Simulation time 8413649053 ps
CPU time 11.19 seconds
Started May 21 01:05:57 PM PDT 24
Finished May 21 01:06:09 PM PDT 24
Peak memory 205340 kb
Host smart-4c2d2b9f-1dd2-4367-a41f-b47cbb98c019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20403
49714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.2040349714
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.2107152478
Short name T1044
Test name
Test status
Simulation time 8384715845 ps
CPU time 11.73 seconds
Started May 21 01:05:43 PM PDT 24
Finished May 21 01:05:57 PM PDT 24
Peak memory 205252 kb
Host smart-bf271cf7-f4e6-41e5-a192-230a6d5bfaec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21071
52478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2107152478
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.1423063270
Short name T610
Test name
Test status
Simulation time 8984770532 ps
CPU time 13.97 seconds
Started May 21 01:05:45 PM PDT 24
Finished May 21 01:06:00 PM PDT 24
Peak memory 205376 kb
Host smart-5944d0f8-da78-47d5-b161-df7f94fc5b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14230
63270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.1423063270
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.1827350899
Short name T1572
Test name
Test status
Simulation time 8433474111 ps
CPU time 13.72 seconds
Started May 21 01:05:53 PM PDT 24
Finished May 21 01:06:07 PM PDT 24
Peak memory 205316 kb
Host smart-d3392f59-992a-4d91-8fce-5fdf7f812b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18273
50899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.1827350899
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.175624009
Short name T1431
Test name
Test status
Simulation time 8392278545 ps
CPU time 12.45 seconds
Started May 21 01:05:46 PM PDT 24
Finished May 21 01:06:00 PM PDT 24
Peak memory 205352 kb
Host smart-bc15100e-b1a3-46d2-80c5-b4b133fe87ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17562
4009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.175624009
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.601814821
Short name T1
Test name
Test status
Simulation time 9253499045 ps
CPU time 14.17 seconds
Started May 21 01:05:43 PM PDT 24
Finished May 21 01:05:59 PM PDT 24
Peak memory 205360 kb
Host smart-94b02751-442d-40ec-8678-d635828a7393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60181
4821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.601814821
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.4149757210
Short name T1646
Test name
Test status
Simulation time 8392807243 ps
CPU time 12.89 seconds
Started May 21 01:05:43 PM PDT 24
Finished May 21 01:05:58 PM PDT 24
Peak memory 205348 kb
Host smart-4c6402d5-cb5a-4e26-b0ef-969e9ef9cb15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41497
57210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.4149757210
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.970727679
Short name T1262
Test name
Test status
Simulation time 8466581268 ps
CPU time 10.99 seconds
Started May 21 01:05:56 PM PDT 24
Finished May 21 01:06:07 PM PDT 24
Peak memory 205296 kb
Host smart-b2500f55-ed85-4fad-9274-df8d251eef88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97072
7679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.970727679
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.467528481
Short name T395
Test name
Test status
Simulation time 8378007562 ps
CPU time 12.39 seconds
Started May 21 01:05:58 PM PDT 24
Finished May 21 01:06:11 PM PDT 24
Peak memory 205412 kb
Host smart-c7b5b8ad-7be3-451f-aec5-64020dcfcf85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46752
8481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.467528481
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.4072164960
Short name T1245
Test name
Test status
Simulation time 8446872394 ps
CPU time 14.52 seconds
Started May 21 01:05:44 PM PDT 24
Finished May 21 01:06:00 PM PDT 24
Peak memory 205320 kb
Host smart-28f25254-cb33-4f9b-a958-a2de3efe752a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40721
64960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.4072164960
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.3182306219
Short name T443
Test name
Test status
Simulation time 11497510259 ps
CPU time 14.99 seconds
Started May 21 01:05:44 PM PDT 24
Finished May 21 01:06:01 PM PDT 24
Peak memory 205348 kb
Host smart-4243140b-c598-41b8-81bf-2768f6a05f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31823
06219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.3182306219
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.2100491272
Short name T877
Test name
Test status
Simulation time 8446398495 ps
CPU time 12.22 seconds
Started May 21 01:05:42 PM PDT 24
Finished May 21 01:05:55 PM PDT 24
Peak memory 205396 kb
Host smart-aaa027a4-b889-4068-8e9d-d60f5db0eb12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21004
91272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.2100491272
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.3302323342
Short name T523
Test name
Test status
Simulation time 8382036607 ps
CPU time 13.08 seconds
Started May 21 01:05:53 PM PDT 24
Finished May 21 01:06:07 PM PDT 24
Peak memory 205380 kb
Host smart-9fbbeed4-8f21-4d86-b20d-a3552c4991c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33023
23342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.3302323342
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.2840178261
Short name T1141
Test name
Test status
Simulation time 8409452120 ps
CPU time 13.32 seconds
Started May 21 01:05:53 PM PDT 24
Finished May 21 01:06:07 PM PDT 24
Peak memory 205364 kb
Host smart-676de034-69c7-4bff-96ae-337c62e07190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28401
78261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2840178261
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.4122294388
Short name T1666
Test name
Test status
Simulation time 8420693342 ps
CPU time 12.57 seconds
Started May 21 01:05:51 PM PDT 24
Finished May 21 01:06:04 PM PDT 24
Peak memory 205248 kb
Host smart-76fd0219-5996-4a17-9152-04f859f2f6e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41222
94388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.4122294388
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.3885214843
Short name T382
Test name
Test status
Simulation time 8399097202 ps
CPU time 11.56 seconds
Started May 21 01:05:52 PM PDT 24
Finished May 21 01:06:04 PM PDT 24
Peak memory 205432 kb
Host smart-77b23025-2734-4f68-bce7-2feffcbbf611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38852
14843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3885214843
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2086181444
Short name T1360
Test name
Test status
Simulation time 8390760714 ps
CPU time 16.02 seconds
Started May 21 01:05:51 PM PDT 24
Finished May 21 01:06:07 PM PDT 24
Peak memory 205368 kb
Host smart-e95adb6d-07ad-4110-963e-37e09561e073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20861
81444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2086181444
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3793300298
Short name T173
Test name
Test status
Simulation time 8400398712 ps
CPU time 12.22 seconds
Started May 21 01:05:55 PM PDT 24
Finished May 21 01:06:08 PM PDT 24
Peak memory 205348 kb
Host smart-2d89a054-fb56-465b-9836-682abf99c2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37933
00298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3793300298
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_eop_single_bit_handling.3871173337
Short name T293
Test name
Test status
Simulation time 8387449946 ps
CPU time 11.75 seconds
Started May 21 01:05:56 PM PDT 24
Finished May 21 01:06:09 PM PDT 24
Peak memory 205304 kb
Host smart-77873c4d-0885-4e34-bb09-4f268077622e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38711
73337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_eop_single_bit_handling.3871173337
Directory /workspace/5.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.3962739242
Short name T46
Test name
Test status
Simulation time 8375701785 ps
CPU time 11.66 seconds
Started May 21 01:05:58 PM PDT 24
Finished May 21 01:06:10 PM PDT 24
Peak memory 205252 kb
Host smart-f17e0f93-9c34-4362-ac8d-af1954ea8df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39627
39242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.3962739242
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.1139534137
Short name T1179
Test name
Test status
Simulation time 8363829493 ps
CPU time 11.05 seconds
Started May 21 01:05:57 PM PDT 24
Finished May 21 01:06:09 PM PDT 24
Peak memory 205240 kb
Host smart-4fe666c3-49f6-49fd-81c0-730dd5959184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11395
34137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.1139534137
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.3730737020
Short name T1274
Test name
Test status
Simulation time 29760850492 ps
CPU time 61.43 seconds
Started May 21 01:05:50 PM PDT 24
Finished May 21 01:06:52 PM PDT 24
Peak memory 205412 kb
Host smart-8105d7b7-a461-4f79-ad80-c8aa6102c486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37307
37020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3730737020
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.776630571
Short name T1702
Test name
Test status
Simulation time 8382118042 ps
CPU time 12.74 seconds
Started May 21 01:05:52 PM PDT 24
Finished May 21 01:06:05 PM PDT 24
Peak memory 205352 kb
Host smart-16b8e927-1154-46ae-b532-f14317b10002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77663
0571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.776630571
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.3961145334
Short name T1402
Test name
Test status
Simulation time 8382896153 ps
CPU time 12.91 seconds
Started May 21 01:05:51 PM PDT 24
Finished May 21 01:06:04 PM PDT 24
Peak memory 205256 kb
Host smart-094a7aa7-f3d5-4e7c-8737-80ea215c55c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39611
45334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.3961145334
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.958774430
Short name T809
Test name
Test status
Simulation time 8392252424 ps
CPU time 11.38 seconds
Started May 21 01:05:50 PM PDT 24
Finished May 21 01:06:02 PM PDT 24
Peak memory 205296 kb
Host smart-31ae822c-5910-4136-88d3-a790e84f3128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95877
4430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.958774430
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.2897096108
Short name T1370
Test name
Test status
Simulation time 8370781901 ps
CPU time 12.59 seconds
Started May 21 01:05:52 PM PDT 24
Finished May 21 01:06:05 PM PDT 24
Peak memory 205280 kb
Host smart-16bdafd8-c723-4076-b69e-2e2910beeaa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28970
96108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.2897096108
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.3948344028
Short name T1328
Test name
Test status
Simulation time 8378573155 ps
CPU time 11.93 seconds
Started May 21 01:05:57 PM PDT 24
Finished May 21 01:06:10 PM PDT 24
Peak memory 205316 kb
Host smart-d9bed890-4e33-4d84-82cb-f76df48f601c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39483
44028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.3948344028
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3866891317
Short name T1315
Test name
Test status
Simulation time 8436188653 ps
CPU time 15.04 seconds
Started May 21 01:05:54 PM PDT 24
Finished May 21 01:06:10 PM PDT 24
Peak memory 205308 kb
Host smart-67e0fef4-db32-48f4-bb4d-290c7af01323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38668
91317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3866891317
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2732720434
Short name T162
Test name
Test status
Simulation time 8411428227 ps
CPU time 12.01 seconds
Started May 21 01:05:43 PM PDT 24
Finished May 21 01:05:56 PM PDT 24
Peak memory 205360 kb
Host smart-414d0f89-b483-4062-938c-9c5d47a3dbfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27327
20434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2732720434
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.1679669917
Short name T1394
Test name
Test status
Simulation time 8397189552 ps
CPU time 12.53 seconds
Started May 21 01:06:00 PM PDT 24
Finished May 21 01:06:13 PM PDT 24
Peak memory 205280 kb
Host smart-3662acf5-d7c4-4280-b812-fcaa4a57b82c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16796
69917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1679669917
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.1142796432
Short name T295
Test name
Test status
Simulation time 8386118357 ps
CPU time 12.07 seconds
Started May 21 01:05:50 PM PDT 24
Finished May 21 01:06:03 PM PDT 24
Peak memory 205332 kb
Host smart-bd252e20-e429-4e92-8268-e30a67bdea56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11427
96432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.1142796432
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.1073136020
Short name T900
Test name
Test status
Simulation time 8477725617 ps
CPU time 12.75 seconds
Started May 21 01:06:04 PM PDT 24
Finished May 21 01:06:18 PM PDT 24
Peak memory 205444 kb
Host smart-5a531709-0975-45be-9c6c-0bc5e4c722a4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1073136020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.1073136020
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.457553374
Short name T1106
Test name
Test status
Simulation time 8380755888 ps
CPU time 11.15 seconds
Started May 21 01:06:10 PM PDT 24
Finished May 21 01:06:23 PM PDT 24
Peak memory 205336 kb
Host smart-9249c428-0327-4e1d-b7ba-d0548ddf13bb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=457553374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.457553374
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.2121629498
Short name T407
Test name
Test status
Simulation time 8442448474 ps
CPU time 12.24 seconds
Started May 21 01:06:05 PM PDT 24
Finished May 21 01:06:19 PM PDT 24
Peak memory 205428 kb
Host smart-d7cea56d-aecb-4b7f-ab7f-f6a0fc16449f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21216
29498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.2121629498
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2238895015
Short name T501
Test name
Test status
Simulation time 8380160295 ps
CPU time 12.58 seconds
Started May 21 01:05:56 PM PDT 24
Finished May 21 01:06:09 PM PDT 24
Peak memory 205336 kb
Host smart-bd9feb03-1ae6-4e92-862d-7f0045b344a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22388
95015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2238895015
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.1340731857
Short name T1066
Test name
Test status
Simulation time 8380742920 ps
CPU time 12.05 seconds
Started May 21 01:05:56 PM PDT 24
Finished May 21 01:06:09 PM PDT 24
Peak memory 205336 kb
Host smart-e16b0bd0-fc59-4958-a010-fd85939cc166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13407
31857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.1340731857
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.3300507122
Short name T470
Test name
Test status
Simulation time 9212696370 ps
CPU time 15.74 seconds
Started May 21 01:05:58 PM PDT 24
Finished May 21 01:06:15 PM PDT 24
Peak memory 205316 kb
Host smart-d03bcff4-dca2-4a1c-a3c1-5c23511bd7fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33005
07122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.3300507122
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.1397856566
Short name T876
Test name
Test status
Simulation time 8367585696 ps
CPU time 12.11 seconds
Started May 21 01:06:05 PM PDT 24
Finished May 21 01:06:19 PM PDT 24
Peak memory 205396 kb
Host smart-39e702c8-4880-4418-8474-9e9102eb3741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13978
56566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.1397856566
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.20587072
Short name T1707
Test name
Test status
Simulation time 8378405760 ps
CPU time 11.46 seconds
Started May 21 01:06:06 PM PDT 24
Finished May 21 01:06:19 PM PDT 24
Peak memory 205388 kb
Host smart-a6fc3c37-8288-4e51-b996-833fa471432c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20587
072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.20587072
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.1630902353
Short name T1191
Test name
Test status
Simulation time 9237705400 ps
CPU time 14.95 seconds
Started May 21 01:05:58 PM PDT 24
Finished May 21 01:06:14 PM PDT 24
Peak memory 205300 kb
Host smart-b25f44d3-9c06-4e3a-8de8-504952d188ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16309
02353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.1630902353
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.4218399924
Short name T1199
Test name
Test status
Simulation time 8521943458 ps
CPU time 12.42 seconds
Started May 21 01:06:05 PM PDT 24
Finished May 21 01:06:19 PM PDT 24
Peak memory 205276 kb
Host smart-3d757426-36a0-40d1-8e67-7bb52e986cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42183
99924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.4218399924
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.3237398446
Short name T767
Test name
Test status
Simulation time 8423960718 ps
CPU time 12.11 seconds
Started May 21 01:06:05 PM PDT 24
Finished May 21 01:06:19 PM PDT 24
Peak memory 205412 kb
Host smart-7e767d83-a7db-49c5-b273-6dbc73fea949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32373
98446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.3237398446
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.4152910933
Short name T473
Test name
Test status
Simulation time 8372101179 ps
CPU time 11.33 seconds
Started May 21 01:06:10 PM PDT 24
Finished May 21 01:06:23 PM PDT 24
Peak memory 205324 kb
Host smart-eb3ca427-fdf8-4b3a-bcc9-d30b56613748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41529
10933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.4152910933
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2228908402
Short name T1059
Test name
Test status
Simulation time 8430838461 ps
CPU time 11.69 seconds
Started May 21 01:06:06 PM PDT 24
Finished May 21 01:06:19 PM PDT 24
Peak memory 205364 kb
Host smart-110d665d-a340-4f87-b0be-9d74fae0511a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22289
08402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2228908402
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.1257980672
Short name T480
Test name
Test status
Simulation time 11568395617 ps
CPU time 17.18 seconds
Started May 21 01:06:04 PM PDT 24
Finished May 21 01:06:23 PM PDT 24
Peak memory 205392 kb
Host smart-9d711800-69be-4ae9-8187-754c2f807108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12579
80672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.1257980672
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.293372049
Short name T770
Test name
Test status
Simulation time 8420190501 ps
CPU time 12.36 seconds
Started May 21 01:06:04 PM PDT 24
Finished May 21 01:06:17 PM PDT 24
Peak memory 205340 kb
Host smart-fc4470ad-7a2b-48e2-ad3f-d1506381862e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29337
2049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.293372049
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.64439558
Short name T1339
Test name
Test status
Simulation time 8381163049 ps
CPU time 12.82 seconds
Started May 21 01:06:04 PM PDT 24
Finished May 21 01:06:17 PM PDT 24
Peak memory 205356 kb
Host smart-dd4a3ca0-79bf-4f12-b306-faae6577325a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64439
558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.64439558
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.4200721261
Short name T124
Test name
Test status
Simulation time 8395199269 ps
CPU time 11.37 seconds
Started May 21 01:06:04 PM PDT 24
Finished May 21 01:06:17 PM PDT 24
Peak memory 205272 kb
Host smart-9fabdd61-377e-498c-9e19-3ab6fea6d1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42007
21261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.4200721261
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.3673046997
Short name T712
Test name
Test status
Simulation time 8423920919 ps
CPU time 14.02 seconds
Started May 21 01:06:03 PM PDT 24
Finished May 21 01:06:19 PM PDT 24
Peak memory 205316 kb
Host smart-8b02ed3c-7085-4b0c-ae1f-009c46e2c7ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36730
46997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.3673046997
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.1035225260
Short name T853
Test name
Test status
Simulation time 8396223290 ps
CPU time 14.05 seconds
Started May 21 01:06:02 PM PDT 24
Finished May 21 01:06:16 PM PDT 24
Peak memory 205356 kb
Host smart-7875cf7b-92f6-4afc-a4d1-4669d9ffa298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10352
25260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.1035225260
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1373681978
Short name T1579
Test name
Test status
Simulation time 8378765187 ps
CPU time 12 seconds
Started May 21 01:06:02 PM PDT 24
Finished May 21 01:06:15 PM PDT 24
Peak memory 205328 kb
Host smart-de5e4c29-408e-4e13-9826-0f7b9bc69769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13736
81978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1373681978
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.3953784584
Short name T1230
Test name
Test status
Simulation time 8393592438 ps
CPU time 10.58 seconds
Started May 21 01:06:05 PM PDT 24
Finished May 21 01:06:17 PM PDT 24
Peak memory 205360 kb
Host smart-f73860d7-095d-4588-8b8f-58e60632fd4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39537
84584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.3953784584
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_eop_single_bit_handling.4266904303
Short name T410
Test name
Test status
Simulation time 8370298565 ps
CPU time 13.59 seconds
Started May 21 01:06:03 PM PDT 24
Finished May 21 01:06:17 PM PDT 24
Peak memory 205444 kb
Host smart-b1dc79c6-ab70-41db-8b85-2cf7568fe73c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42669
04303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_eop_single_bit_handling.4266904303
Directory /workspace/6.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.2754940709
Short name T1309
Test name
Test status
Simulation time 8377972976 ps
CPU time 13.55 seconds
Started May 21 01:06:04 PM PDT 24
Finished May 21 01:06:19 PM PDT 24
Peak memory 205240 kb
Host smart-63505bc6-4d64-4225-a4a0-de6a95276bca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27549
40709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2754940709
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.4090331912
Short name T710
Test name
Test status
Simulation time 8366808230 ps
CPU time 11.45 seconds
Started May 21 01:06:04 PM PDT 24
Finished May 21 01:06:16 PM PDT 24
Peak memory 205324 kb
Host smart-ae5cba9e-786f-4a17-8832-37c8c621e945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40903
31912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.4090331912
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1980769433
Short name T888
Test name
Test status
Simulation time 16839763446 ps
CPU time 30.31 seconds
Started May 21 01:06:04 PM PDT 24
Finished May 21 01:06:36 PM PDT 24
Peak memory 205424 kb
Host smart-ba05dd95-e643-4e24-9a88-d2782259cafa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19807
69433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1980769433
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.2111183819
Short name T1294
Test name
Test status
Simulation time 8379027879 ps
CPU time 11.49 seconds
Started May 21 01:06:04 PM PDT 24
Finished May 21 01:06:18 PM PDT 24
Peak memory 205344 kb
Host smart-a7273df0-d773-4e44-be76-1eca6f3a1049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21111
83819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.2111183819
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.4247814591
Short name T1295
Test name
Test status
Simulation time 8452136649 ps
CPU time 12.17 seconds
Started May 21 01:06:05 PM PDT 24
Finished May 21 01:06:19 PM PDT 24
Peak memory 205272 kb
Host smart-3ae65487-6b9b-4599-bbf5-c3840a765aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42478
14591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.4247814591
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.3196766774
Short name T1378
Test name
Test status
Simulation time 8419511731 ps
CPU time 12.15 seconds
Started May 21 01:06:02 PM PDT 24
Finished May 21 01:06:15 PM PDT 24
Peak memory 205388 kb
Host smart-d9a36bff-dd94-42f7-abc7-1e9ac3a87031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31967
66774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.3196766774
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.2055679620
Short name T1426
Test name
Test status
Simulation time 8387819883 ps
CPU time 13.52 seconds
Started May 21 01:06:11 PM PDT 24
Finished May 21 01:06:25 PM PDT 24
Peak memory 205324 kb
Host smart-300221e0-0e10-420e-aef4-935485ee454b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20556
79620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.2055679620
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.1141025256
Short name T1674
Test name
Test status
Simulation time 8377002694 ps
CPU time 12.14 seconds
Started May 21 01:06:12 PM PDT 24
Finished May 21 01:06:25 PM PDT 24
Peak memory 205316 kb
Host smart-1d40bdd4-a9b3-4f27-a932-56415d5709e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11410
25256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.1141025256
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.116722296
Short name T1421
Test name
Test status
Simulation time 8389176509 ps
CPU time 10.8 seconds
Started May 21 01:06:07 PM PDT 24
Finished May 21 01:06:19 PM PDT 24
Peak memory 205368 kb
Host smart-bfa7d8d2-3e6a-4a9c-bad7-0d5476bf5509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11672
2296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.116722296
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.186956767
Short name T181
Test name
Test status
Simulation time 8405371921 ps
CPU time 11.73 seconds
Started May 21 01:05:55 PM PDT 24
Finished May 21 01:06:07 PM PDT 24
Peak memory 205416 kb
Host smart-d43c5e26-5ee4-4794-852c-0c2d9d2cc161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18695
6767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.186956767
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.534919665
Short name T591
Test name
Test status
Simulation time 8399181353 ps
CPU time 15.31 seconds
Started May 21 01:06:05 PM PDT 24
Finished May 21 01:06:22 PM PDT 24
Peak memory 205340 kb
Host smart-493ac7bf-5561-4fd2-b176-91f149994495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53491
9665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.534919665
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.2007855152
Short name T1249
Test name
Test status
Simulation time 8416248513 ps
CPU time 14.22 seconds
Started May 21 01:06:04 PM PDT 24
Finished May 21 01:06:20 PM PDT 24
Peak memory 205376 kb
Host smart-3c371d9f-aec6-464b-8a78-af2ba621b5d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20078
55152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.2007855152
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.61683167
Short name T1030
Test name
Test status
Simulation time 8472170453 ps
CPU time 12.3 seconds
Started May 21 01:06:20 PM PDT 24
Finished May 21 01:06:33 PM PDT 24
Peak memory 205292 kb
Host smart-865ed4b4-076f-4cd8-b550-7f054633565a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=61683167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.61683167
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.381405914
Short name T890
Test name
Test status
Simulation time 8393047337 ps
CPU time 13.82 seconds
Started May 21 01:06:16 PM PDT 24
Finished May 21 01:06:31 PM PDT 24
Peak memory 205372 kb
Host smart-54d88692-0381-4ada-9825-75b3748cebfa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=381405914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.381405914
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.3380030410
Short name T1423
Test name
Test status
Simulation time 8426751327 ps
CPU time 12.22 seconds
Started May 21 01:06:17 PM PDT 24
Finished May 21 01:06:30 PM PDT 24
Peak memory 205348 kb
Host smart-b8212c38-1cb1-4424-ac40-7bab46986c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33800
30410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.3380030410
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.3435374195
Short name T1115
Test name
Test status
Simulation time 8381677507 ps
CPU time 13.6 seconds
Started May 21 01:06:04 PM PDT 24
Finished May 21 01:06:19 PM PDT 24
Peak memory 205376 kb
Host smart-5214f9a2-533e-46af-b462-68398c2ec9b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34353
74195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3435374195
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.2747578227
Short name T189
Test name
Test status
Simulation time 9717267664 ps
CPU time 14.53 seconds
Started May 21 01:06:04 PM PDT 24
Finished May 21 01:06:21 PM PDT 24
Peak memory 205388 kb
Host smart-b8ee1727-5787-45ce-a1a0-53309f29351d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27475
78227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.2747578227
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.3007428556
Short name T557
Test name
Test status
Simulation time 8367785105 ps
CPU time 11.91 seconds
Started May 21 01:06:08 PM PDT 24
Finished May 21 01:06:21 PM PDT 24
Peak memory 205248 kb
Host smart-0e62db8f-87ad-4812-959f-36a7afefdba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30074
28556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.3007428556
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.3719606158
Short name T1302
Test name
Test status
Simulation time 8382293279 ps
CPU time 13.21 seconds
Started May 21 01:06:07 PM PDT 24
Finished May 21 01:06:21 PM PDT 24
Peak memory 205392 kb
Host smart-120fc5fc-f100-4fb9-9ef0-3e7f1f25e76e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37196
06158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3719606158
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.2382871966
Short name T1466
Test name
Test status
Simulation time 9178747450 ps
CPU time 12.68 seconds
Started May 21 01:06:10 PM PDT 24
Finished May 21 01:06:24 PM PDT 24
Peak memory 205408 kb
Host smart-8af98402-ce2d-48a4-8b85-7bb21a0f8eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23828
71966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.2382871966
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1196991825
Short name T1187
Test name
Test status
Simulation time 8425037285 ps
CPU time 12.3 seconds
Started May 21 01:06:09 PM PDT 24
Finished May 21 01:06:22 PM PDT 24
Peak memory 205372 kb
Host smart-9e9481b5-c84a-4ae7-bcb8-4bff7bc10b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11969
91825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1196991825
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.2475499799
Short name T403
Test name
Test status
Simulation time 8393459843 ps
CPU time 13.3 seconds
Started May 21 01:06:18 PM PDT 24
Finished May 21 01:06:32 PM PDT 24
Peak memory 205396 kb
Host smart-c011e748-6e8f-4389-b407-6383b04e5bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24754
99799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2475499799
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.1998950686
Short name T415
Test name
Test status
Simulation time 8363953419 ps
CPU time 11.56 seconds
Started May 21 01:06:17 PM PDT 24
Finished May 21 01:06:29 PM PDT 24
Peak memory 205308 kb
Host smart-a11b8aeb-d21a-4993-8e14-1f357a3febd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19989
50686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.1998950686
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.4287050064
Short name T365
Test name
Test status
Simulation time 8461092180 ps
CPU time 14.18 seconds
Started May 21 01:06:09 PM PDT 24
Finished May 21 01:06:25 PM PDT 24
Peak memory 205348 kb
Host smart-b8dcd888-f900-4d46-9f68-30385d982cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42870
50064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.4287050064
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.3593190591
Short name T1366
Test name
Test status
Simulation time 11548326853 ps
CPU time 14.98 seconds
Started May 21 01:06:07 PM PDT 24
Finished May 21 01:06:23 PM PDT 24
Peak memory 205340 kb
Host smart-8a8a2b13-64da-4510-852e-6de7919d8426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35931
90591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.3593190591
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.1583352693
Short name T628
Test name
Test status
Simulation time 8422169710 ps
CPU time 11.53 seconds
Started May 21 01:06:09 PM PDT 24
Finished May 21 01:06:22 PM PDT 24
Peak memory 205400 kb
Host smart-7c6d21a8-f6e0-4c6b-aff8-2a52cc37f1cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15833
52693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.1583352693
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.3390544408
Short name T976
Test name
Test status
Simulation time 8368574011 ps
CPU time 10.73 seconds
Started May 21 01:06:09 PM PDT 24
Finished May 21 01:06:21 PM PDT 24
Peak memory 205388 kb
Host smart-ae6d9901-1cec-462f-a21f-d86e993fb360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33905
44408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.3390544408
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.817440290
Short name T1668
Test name
Test status
Simulation time 8392303048 ps
CPU time 11.3 seconds
Started May 21 01:06:08 PM PDT 24
Finished May 21 01:06:21 PM PDT 24
Peak memory 205352 kb
Host smart-bc981cb0-2848-4fe4-a082-e07016319e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81744
0290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.817440290
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.772172962
Short name T1670
Test name
Test status
Simulation time 8420656546 ps
CPU time 12.75 seconds
Started May 21 01:06:08 PM PDT 24
Finished May 21 01:06:23 PM PDT 24
Peak memory 205348 kb
Host smart-15d6e496-8aaa-43d2-9a38-93aebba7ba9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77217
2962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.772172962
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.3366433708
Short name T780
Test name
Test status
Simulation time 8391596309 ps
CPU time 13.25 seconds
Started May 21 01:06:11 PM PDT 24
Finished May 21 01:06:25 PM PDT 24
Peak memory 205432 kb
Host smart-91082da2-b1b7-4766-b86c-e766dbace7ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33664
33708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.3366433708
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.375832725
Short name T478
Test name
Test status
Simulation time 8457783000 ps
CPU time 12.06 seconds
Started May 21 01:06:08 PM PDT 24
Finished May 21 01:06:21 PM PDT 24
Peak memory 205392 kb
Host smart-e7a04000-6bfd-442a-9a78-d0ee4fdc9904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37583
2725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.375832725
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.3740585533
Short name T167
Test name
Test status
Simulation time 8414671243 ps
CPU time 11.35 seconds
Started May 21 01:06:22 PM PDT 24
Finished May 21 01:06:35 PM PDT 24
Peak memory 205416 kb
Host smart-a9df7b25-2b66-4be1-b95b-a4506dfbd22b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37405
85533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.3740585533
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_eop_single_bit_handling.2201340032
Short name T1189
Test name
Test status
Simulation time 8382557939 ps
CPU time 11.13 seconds
Started May 21 01:06:18 PM PDT 24
Finished May 21 01:06:30 PM PDT 24
Peak memory 205352 kb
Host smart-c54265ef-4717-458c-9d7e-9dd9655bef52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22013
40032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_eop_single_bit_handling.2201340032
Directory /workspace/7.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2288988305
Short name T1404
Test name
Test status
Simulation time 8411132280 ps
CPU time 13.74 seconds
Started May 21 01:06:17 PM PDT 24
Finished May 21 01:06:32 PM PDT 24
Peak memory 205436 kb
Host smart-cdee26d1-a95d-4d4d-9d94-b37feddc15f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22889
88305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2288988305
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.3698582927
Short name T592
Test name
Test status
Simulation time 8379505224 ps
CPU time 13.61 seconds
Started May 21 01:06:14 PM PDT 24
Finished May 21 01:06:29 PM PDT 24
Peak memory 205316 kb
Host smart-9d3d4ffe-2479-4454-a2fe-a61af15212bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36985
82927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.3698582927
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.1771465210
Short name T706
Test name
Test status
Simulation time 23394847266 ps
CPU time 47.3 seconds
Started May 21 01:06:12 PM PDT 24
Finished May 21 01:07:00 PM PDT 24
Peak memory 205360 kb
Host smart-6bd61065-b719-459a-9185-127247cc7f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17714
65210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.1771465210
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.3980711152
Short name T1373
Test name
Test status
Simulation time 8410937392 ps
CPU time 13.17 seconds
Started May 21 01:06:08 PM PDT 24
Finished May 21 01:06:23 PM PDT 24
Peak memory 205336 kb
Host smart-f58adce4-923f-43a4-8a58-699923dffbf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39807
11152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.3980711152
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.2249631954
Short name T737
Test name
Test status
Simulation time 8406168585 ps
CPU time 11.99 seconds
Started May 21 01:06:09 PM PDT 24
Finished May 21 01:06:22 PM PDT 24
Peak memory 205368 kb
Host smart-4cf6afb5-49fa-418a-b67b-7f9c66e84a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22496
31954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.2249631954
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.3870569325
Short name T1706
Test name
Test status
Simulation time 8389113178 ps
CPU time 12.7 seconds
Started May 21 01:06:11 PM PDT 24
Finished May 21 01:06:25 PM PDT 24
Peak memory 205304 kb
Host smart-63c29a78-9f4e-4c0a-b5c7-ebc7aba61664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38705
69325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.3870569325
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.1130203460
Short name T1461
Test name
Test status
Simulation time 8401281172 ps
CPU time 11.01 seconds
Started May 21 01:06:09 PM PDT 24
Finished May 21 01:06:22 PM PDT 24
Peak memory 205532 kb
Host smart-5f7c5dcd-e398-4344-b14d-deb0b4484183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11302
03460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.1130203460
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.3488010141
Short name T1436
Test name
Test status
Simulation time 8377975832 ps
CPU time 11.78 seconds
Started May 21 01:06:16 PM PDT 24
Finished May 21 01:06:28 PM PDT 24
Peak memory 205324 kb
Host smart-77137e19-b17c-4eda-bba0-9269a64a9d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34880
10141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.3488010141
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3820731465
Short name T378
Test name
Test status
Simulation time 8385535679 ps
CPU time 13.26 seconds
Started May 21 01:06:09 PM PDT 24
Finished May 21 01:06:24 PM PDT 24
Peak memory 205256 kb
Host smart-ea0d32ca-7c46-4c6a-bfed-817bc5699a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38207
31465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3820731465
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.370656272
Short name T52
Test name
Test status
Simulation time 8437959148 ps
CPU time 13.04 seconds
Started May 21 01:06:04 PM PDT 24
Finished May 21 01:06:19 PM PDT 24
Peak memory 205324 kb
Host smart-86599092-c138-49b2-b2d0-13a365ad393f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37065
6272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.370656272
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.773487090
Short name T1385
Test name
Test status
Simulation time 8392191433 ps
CPU time 13.02 seconds
Started May 21 01:06:14 PM PDT 24
Finished May 21 01:06:28 PM PDT 24
Peak memory 205352 kb
Host smart-04a0b429-228e-4ba3-be98-62159cbdc72c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77348
7090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.773487090
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.407378584
Short name T275
Test name
Test status
Simulation time 8415769005 ps
CPU time 12.63 seconds
Started May 21 01:06:09 PM PDT 24
Finished May 21 01:06:23 PM PDT 24
Peak memory 205380 kb
Host smart-416cf99e-bf0b-402b-9c66-e6f5c21d1038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40737
8584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.407378584
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.2284598519
Short name T560
Test name
Test status
Simulation time 8545497018 ps
CPU time 12.91 seconds
Started May 21 01:06:31 PM PDT 24
Finished May 21 01:06:45 PM PDT 24
Peak memory 205436 kb
Host smart-9955fc7c-9ad5-4c31-8e69-db28b75d2fed
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2284598519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.2284598519
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.1132395340
Short name T1525
Test name
Test status
Simulation time 8389329170 ps
CPU time 11.3 seconds
Started May 21 01:06:32 PM PDT 24
Finished May 21 01:06:44 PM PDT 24
Peak memory 205348 kb
Host smart-4f477fb9-e759-48bb-84c8-0e918c4f889e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1132395340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.1132395340
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.1654794397
Short name T1722
Test name
Test status
Simulation time 8441042702 ps
CPU time 12.21 seconds
Started May 21 01:06:32 PM PDT 24
Finished May 21 01:06:45 PM PDT 24
Peak memory 205332 kb
Host smart-a9672e78-ea44-468a-9734-65217fc5475a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16547
94397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.1654794397
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.493550961
Short name T743
Test name
Test status
Simulation time 8375191485 ps
CPU time 11.39 seconds
Started May 21 01:06:22 PM PDT 24
Finished May 21 01:06:35 PM PDT 24
Peak memory 205216 kb
Host smart-cc40bc72-178c-4881-a392-2c39de8bb29b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49355
0961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.493550961
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.3351088882
Short name T49
Test name
Test status
Simulation time 8627485909 ps
CPU time 12.19 seconds
Started May 21 01:06:20 PM PDT 24
Finished May 21 01:06:33 PM PDT 24
Peak memory 205404 kb
Host smart-36eddc31-957d-4340-8c30-314ce96b32d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33510
88882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.3351088882
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.206142642
Short name T1160
Test name
Test status
Simulation time 8388187539 ps
CPU time 11.78 seconds
Started May 21 01:06:26 PM PDT 24
Finished May 21 01:06:38 PM PDT 24
Peak memory 205332 kb
Host smart-a3885f0b-5216-489c-9568-2acc0ee0d65e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20614
2642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.206142642
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.4179740449
Short name T985
Test name
Test status
Simulation time 8382924295 ps
CPU time 11.83 seconds
Started May 21 01:06:23 PM PDT 24
Finished May 21 01:06:36 PM PDT 24
Peak memory 205320 kb
Host smart-e2ee86b2-c36e-444b-ae83-d691147f56dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41797
40449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.4179740449
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.1098970632
Short name T1469
Test name
Test status
Simulation time 9238612841 ps
CPU time 13.99 seconds
Started May 21 01:06:21 PM PDT 24
Finished May 21 01:06:35 PM PDT 24
Peak memory 205320 kb
Host smart-c3d02014-ad70-48cf-8da9-4ed4a94f7eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10989
70632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.1098970632
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.396315714
Short name T1490
Test name
Test status
Simulation time 8531714978 ps
CPU time 13.17 seconds
Started May 21 01:06:22 PM PDT 24
Finished May 21 01:06:37 PM PDT 24
Peak memory 205324 kb
Host smart-8533bf79-5035-4a2b-9856-41be2bf485eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39631
5714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.396315714
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.942149168
Short name T1647
Test name
Test status
Simulation time 8434644429 ps
CPU time 12.37 seconds
Started May 21 01:06:31 PM PDT 24
Finished May 21 01:06:44 PM PDT 24
Peak memory 205296 kb
Host smart-5812ac11-7134-4070-a5a2-066d89ef6140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94214
9168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.942149168
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1117107504
Short name T1156
Test name
Test status
Simulation time 8368442747 ps
CPU time 11.37 seconds
Started May 21 01:06:30 PM PDT 24
Finished May 21 01:06:42 PM PDT 24
Peak memory 205300 kb
Host smart-508c9455-2f1b-4b77-9007-b9dec48602c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11171
07504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1117107504
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.4161258865
Short name T585
Test name
Test status
Simulation time 8396876668 ps
CPU time 11.96 seconds
Started May 21 01:06:23 PM PDT 24
Finished May 21 01:06:37 PM PDT 24
Peak memory 205360 kb
Host smart-3b1d52ab-75f5-49dc-9427-5b4d30d46f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41612
58865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.4161258865
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.1347526206
Short name T1095
Test name
Test status
Simulation time 8413636706 ps
CPU time 11.4 seconds
Started May 21 01:06:22 PM PDT 24
Finished May 21 01:06:35 PM PDT 24
Peak memory 205272 kb
Host smart-0f1ec7a2-0f64-4790-94c7-fb2ce1dca8ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13475
26206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.1347526206
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.527659848
Short name T1576
Test name
Test status
Simulation time 11565208234 ps
CPU time 15.17 seconds
Started May 21 01:06:26 PM PDT 24
Finished May 21 01:06:42 PM PDT 24
Peak memory 205364 kb
Host smart-6c76e2d7-1c1d-4419-9209-8bc133d1ae72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52765
9848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.527659848
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.464457360
Short name T1359
Test name
Test status
Simulation time 8419755139 ps
CPU time 11.38 seconds
Started May 21 01:06:18 PM PDT 24
Finished May 21 01:06:30 PM PDT 24
Peak memory 205368 kb
Host smart-bac110fc-1c2d-420b-98b4-c0a5d4fde2f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46445
7360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.464457360
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.2793429549
Short name T18
Test name
Test status
Simulation time 8392407657 ps
CPU time 11.7 seconds
Started May 21 01:06:24 PM PDT 24
Finished May 21 01:06:37 PM PDT 24
Peak memory 205532 kb
Host smart-27869370-dce5-42af-8bd8-ce89dfcac166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27934
29549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.2793429549
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.570194090
Short name T151
Test name
Test status
Simulation time 8426325743 ps
CPU time 14.22 seconds
Started May 21 01:06:24 PM PDT 24
Finished May 21 01:06:40 PM PDT 24
Peak memory 205620 kb
Host smart-97376bb1-4388-43da-9e2b-8922b7ca7850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57019
4090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.570194090
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.4098471042
Short name T509
Test name
Test status
Simulation time 8412026987 ps
CPU time 11.64 seconds
Started May 21 01:06:22 PM PDT 24
Finished May 21 01:06:36 PM PDT 24
Peak memory 205416 kb
Host smart-8f1461a3-dc07-4acd-87da-6ef139e001f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40984
71042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.4098471042
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.29981398
Short name T1381
Test name
Test status
Simulation time 8471704563 ps
CPU time 13.91 seconds
Started May 21 01:06:23 PM PDT 24
Finished May 21 01:06:39 PM PDT 24
Peak memory 205328 kb
Host smart-ed3fe83f-c75c-4f77-912a-98fcd437889f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29981
398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.29981398
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.560202515
Short name T594
Test name
Test status
Simulation time 8379083676 ps
CPU time 11.75 seconds
Started May 21 01:06:22 PM PDT 24
Finished May 21 01:06:35 PM PDT 24
Peak memory 205392 kb
Host smart-40ae1b09-1aa1-49db-b3ce-fbcb160b4f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56020
2515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.560202515
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.2940382991
Short name T759
Test name
Test status
Simulation time 8384456241 ps
CPU time 12.93 seconds
Started May 21 01:06:31 PM PDT 24
Finished May 21 01:06:45 PM PDT 24
Peak memory 205404 kb
Host smart-64cd012b-26d7-4145-95ab-b3302bf16f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29403
82991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.2940382991
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_eop_single_bit_handling.2688959419
Short name T386
Test name
Test status
Simulation time 8418620679 ps
CPU time 11.09 seconds
Started May 21 01:06:31 PM PDT 24
Finished May 21 01:06:43 PM PDT 24
Peak memory 205412 kb
Host smart-b33379d0-ef55-4ecf-8de3-604b87bc025b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26889
59419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_eop_single_bit_handling.2688959419
Directory /workspace/8.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.1660983028
Short name T916
Test name
Test status
Simulation time 8375254339 ps
CPU time 12.95 seconds
Started May 21 01:06:22 PM PDT 24
Finished May 21 01:06:37 PM PDT 24
Peak memory 205308 kb
Host smart-6181997a-f496-4284-a69c-f244e4b4ddc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16609
83028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.1660983028
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3297488349
Short name T1314
Test name
Test status
Simulation time 8394865709 ps
CPU time 14.75 seconds
Started May 21 01:06:34 PM PDT 24
Finished May 21 01:06:50 PM PDT 24
Peak memory 205396 kb
Host smart-6d026559-9421-4d54-bfd4-74353001c894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32974
88349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3297488349
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.577788698
Short name T1237
Test name
Test status
Simulation time 31076887329 ps
CPU time 65.08 seconds
Started May 21 01:06:25 PM PDT 24
Finished May 21 01:07:31 PM PDT 24
Peak memory 205356 kb
Host smart-e9817bb8-f29e-4b3f-a0dc-63cc2136b6bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57778
8698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.577788698
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.2605815846
Short name T793
Test name
Test status
Simulation time 8403909970 ps
CPU time 11.84 seconds
Started May 21 01:06:20 PM PDT 24
Finished May 21 01:06:33 PM PDT 24
Peak memory 205440 kb
Host smart-72168327-cef9-4ee6-a3a9-d8e651fd85ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26058
15846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.2605815846
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3147438058
Short name T1424
Test name
Test status
Simulation time 8395891193 ps
CPU time 13.87 seconds
Started May 21 01:06:22 PM PDT 24
Finished May 21 01:06:38 PM PDT 24
Peak memory 205324 kb
Host smart-230b7732-8533-454e-a720-87feef793c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31474
38058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3147438058
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.2088114487
Short name T1173
Test name
Test status
Simulation time 8382944968 ps
CPU time 11.45 seconds
Started May 21 01:06:23 PM PDT 24
Finished May 21 01:06:36 PM PDT 24
Peak memory 205204 kb
Host smart-53196b1f-604a-48d3-a202-86f04c1f0d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20881
14487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.2088114487
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.1723196397
Short name T762
Test name
Test status
Simulation time 8379219181 ps
CPU time 11.53 seconds
Started May 21 01:06:22 PM PDT 24
Finished May 21 01:06:35 PM PDT 24
Peak memory 205348 kb
Host smart-26b671d5-166f-4227-a74d-be593991dd60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17231
96397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.1723196397
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.3625674954
Short name T1157
Test name
Test status
Simulation time 8386022791 ps
CPU time 11.96 seconds
Started May 21 01:06:33 PM PDT 24
Finished May 21 01:06:46 PM PDT 24
Peak memory 205344 kb
Host smart-0e8c071c-7bf5-45dd-9962-1e9c013fc80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36256
74954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.3625674954
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2890178915
Short name T1539
Test name
Test status
Simulation time 8390748955 ps
CPU time 12.02 seconds
Started May 21 01:06:22 PM PDT 24
Finished May 21 01:06:36 PM PDT 24
Peak memory 205448 kb
Host smart-abe4df0f-ece0-4db0-b4a2-50ef7f03683b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28901
78915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2890178915
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.2747323048
Short name T968
Test name
Test status
Simulation time 8445551677 ps
CPU time 11.98 seconds
Started May 21 01:06:22 PM PDT 24
Finished May 21 01:06:35 PM PDT 24
Peak memory 205392 kb
Host smart-fbba0863-642b-47ee-be39-453f99d448a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27473
23048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2747323048
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.2119348857
Short name T998
Test name
Test status
Simulation time 8426205159 ps
CPU time 13 seconds
Started May 21 01:06:21 PM PDT 24
Finished May 21 01:06:35 PM PDT 24
Peak memory 205456 kb
Host smart-b5990a4f-1002-4684-abf9-9effe3ed6bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21193
48857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.2119348857
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.1954853492
Short name T1429
Test name
Test status
Simulation time 8463419247 ps
CPU time 13.71 seconds
Started May 21 01:06:40 PM PDT 24
Finished May 21 01:06:55 PM PDT 24
Peak memory 205412 kb
Host smart-4759a231-bf3e-4b43-bb46-cb31c85fde9e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1954853492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.1954853492
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.1853437812
Short name T602
Test name
Test status
Simulation time 8427176395 ps
CPU time 10.76 seconds
Started May 21 01:06:39 PM PDT 24
Finished May 21 01:06:50 PM PDT 24
Peak memory 205352 kb
Host smart-96451adc-9a33-4079-8600-d02849cc203a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1853437812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.1853437812
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.4265872932
Short name T960
Test name
Test status
Simulation time 8407150700 ps
CPU time 11.49 seconds
Started May 21 01:06:42 PM PDT 24
Finished May 21 01:06:54 PM PDT 24
Peak memory 205364 kb
Host smart-1f91c10f-209c-4806-b3bd-30995ec3a4c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42658
72932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.4265872932
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.4073036032
Short name T1462
Test name
Test status
Simulation time 8383670495 ps
CPU time 12.82 seconds
Started May 21 01:06:30 PM PDT 24
Finished May 21 01:06:44 PM PDT 24
Peak memory 205332 kb
Host smart-31187121-a286-42f8-8fa9-cc0541f4a8a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40730
36032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.4073036032
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.1880852903
Short name T927
Test name
Test status
Simulation time 8723936799 ps
CPU time 13.34 seconds
Started May 21 01:06:29 PM PDT 24
Finished May 21 01:06:44 PM PDT 24
Peak memory 205392 kb
Host smart-5dcb6837-e536-4ff8-990e-2cce95a73391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18808
52903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.1880852903
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.1663078033
Short name T565
Test name
Test status
Simulation time 8371931467 ps
CPU time 11.53 seconds
Started May 21 01:06:34 PM PDT 24
Finished May 21 01:06:47 PM PDT 24
Peak memory 205348 kb
Host smart-315d3929-3ac1-42ca-85e4-360ddc696d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16630
78033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1663078033
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.3044564345
Short name T336
Test name
Test status
Simulation time 8376460402 ps
CPU time 11.25 seconds
Started May 21 01:06:31 PM PDT 24
Finished May 21 01:06:44 PM PDT 24
Peak memory 205352 kb
Host smart-86b56a28-2440-44e3-a091-ef4addf12b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30445
64345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.3044564345
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.3106028982
Short name T488
Test name
Test status
Simulation time 9101874524 ps
CPU time 13.7 seconds
Started May 21 01:06:31 PM PDT 24
Finished May 21 01:06:46 PM PDT 24
Peak memory 205344 kb
Host smart-aea79f13-9f6d-4936-9409-55b43b0a8a28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31060
28982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.3106028982
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.3132433716
Short name T1456
Test name
Test status
Simulation time 8403599953 ps
CPU time 13.58 seconds
Started May 21 01:06:31 PM PDT 24
Finished May 21 01:06:46 PM PDT 24
Peak memory 205412 kb
Host smart-be4e030c-8b86-4bbe-bd1b-146dbea8e09c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31324
33716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.3132433716
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.1861375518
Short name T1644
Test name
Test status
Simulation time 8417772722 ps
CPU time 14.2 seconds
Started May 21 01:06:42 PM PDT 24
Finished May 21 01:06:57 PM PDT 24
Peak memory 205428 kb
Host smart-ce6cbc4a-f4ef-4cbe-a8d4-2b9b96cd6c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18613
75518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.1861375518
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.2546161113
Short name T974
Test name
Test status
Simulation time 8371053104 ps
CPU time 12.47 seconds
Started May 21 01:06:45 PM PDT 24
Finished May 21 01:06:58 PM PDT 24
Peak memory 205320 kb
Host smart-645e2cbd-8ad7-4441-b1dc-8fda890e67a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25461
61113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.2546161113
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.1893238860
Short name T29
Test name
Test status
Simulation time 8430149725 ps
CPU time 12.86 seconds
Started May 21 01:06:36 PM PDT 24
Finished May 21 01:06:50 PM PDT 24
Peak memory 205340 kb
Host smart-b846d321-84cd-4683-9b25-4747ba243441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18932
38860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.1893238860
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.1044359186
Short name T966
Test name
Test status
Simulation time 11480910350 ps
CPU time 14.47 seconds
Started May 21 01:06:35 PM PDT 24
Finished May 21 01:06:51 PM PDT 24
Peak memory 205272 kb
Host smart-4c588d0d-2509-4eb6-8361-ac7f499d27a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10443
59186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.1044359186
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.2935850229
Short name T655
Test name
Test status
Simulation time 8416990742 ps
CPU time 10.85 seconds
Started May 21 01:06:35 PM PDT 24
Finished May 21 01:06:47 PM PDT 24
Peak memory 205436 kb
Host smart-2e9a32a8-8b2b-4a80-901a-3216db3c8ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29358
50229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.2935850229
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3630882948
Short name T349
Test name
Test status
Simulation time 8375501980 ps
CPU time 11.78 seconds
Started May 21 01:06:36 PM PDT 24
Finished May 21 01:06:49 PM PDT 24
Peak memory 205284 kb
Host smart-35ae7098-0e22-426b-beb9-d35ee99ea7bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36308
82948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3630882948
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.4286046603
Short name T134
Test name
Test status
Simulation time 8432130158 ps
CPU time 14.34 seconds
Started May 21 01:06:36 PM PDT 24
Finished May 21 01:06:52 PM PDT 24
Peak memory 205240 kb
Host smart-828eda92-056a-478d-84e5-a183b80613fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42860
46603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.4286046603
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.824682424
Short name T837
Test name
Test status
Simulation time 8410159768 ps
CPU time 14.3 seconds
Started May 21 01:06:38 PM PDT 24
Finished May 21 01:06:53 PM PDT 24
Peak memory 205388 kb
Host smart-2119c71a-24c2-4f0e-a822-4222310a5613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82468
2424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.824682424
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.3980878162
Short name T1055
Test name
Test status
Simulation time 8390474063 ps
CPU time 12.45 seconds
Started May 21 01:06:38 PM PDT 24
Finished May 21 01:06:51 PM PDT 24
Peak memory 205348 kb
Host smart-ec5c42d2-505e-4544-8842-0cc3693e4511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39808
78162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.3980878162
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.2503976402
Short name T25
Test name
Test status
Simulation time 8378320338 ps
CPU time 11.15 seconds
Started May 21 01:06:34 PM PDT 24
Finished May 21 01:06:47 PM PDT 24
Peak memory 205372 kb
Host smart-4908863a-2ced-4b62-b515-82c2ee9970f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25039
76402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.2503976402
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.1875613207
Short name T169
Test name
Test status
Simulation time 8384508782 ps
CPU time 12.19 seconds
Started May 21 01:06:41 PM PDT 24
Finished May 21 01:06:55 PM PDT 24
Peak memory 205324 kb
Host smart-74c0dcb9-65b6-4ba0-a7c2-a4ab4748c45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18756
13207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.1875613207
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_eop_single_bit_handling.1718085513
Short name T1380
Test name
Test status
Simulation time 8372944395 ps
CPU time 12.55 seconds
Started May 21 01:06:46 PM PDT 24
Finished May 21 01:06:59 PM PDT 24
Peak memory 205408 kb
Host smart-719f2808-f190-4831-ae62-117f9df9ea16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17180
85513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_eop_single_bit_handling.1718085513
Directory /workspace/9.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.370372000
Short name T607
Test name
Test status
Simulation time 8371159121 ps
CPU time 12.48 seconds
Started May 21 01:06:43 PM PDT 24
Finished May 21 01:06:56 PM PDT 24
Peak memory 205372 kb
Host smart-aabb6c39-89dd-41f5-818b-c263016a8ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37037
2000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.370372000
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1239139919
Short name T1369
Test name
Test status
Simulation time 8369018671 ps
CPU time 11.99 seconds
Started May 21 01:06:41 PM PDT 24
Finished May 21 01:06:54 PM PDT 24
Peak memory 205296 kb
Host smart-ac0e8041-6d58-4ca7-816e-089403973329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12391
39919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1239139919
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.1672521312
Short name T1193
Test name
Test status
Simulation time 21308424130 ps
CPU time 38.58 seconds
Started May 21 01:06:36 PM PDT 24
Finished May 21 01:07:16 PM PDT 24
Peak memory 205400 kb
Host smart-cf1419e6-f25c-4057-9e29-93a61b97d586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16725
21312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.1672521312
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.3108359295
Short name T1049
Test name
Test status
Simulation time 8439519572 ps
CPU time 12.67 seconds
Started May 21 01:06:37 PM PDT 24
Finished May 21 01:06:51 PM PDT 24
Peak memory 205332 kb
Host smart-ed3183a6-2795-4572-b5c0-26bf9ed6760b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31083
59295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3108359295
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.3957541944
Short name T273
Test name
Test status
Simulation time 8402079384 ps
CPU time 11.59 seconds
Started May 21 01:06:36 PM PDT 24
Finished May 21 01:06:49 PM PDT 24
Peak memory 205304 kb
Host smart-eb69bf6e-e1c3-4f05-94d1-261503ff21a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39575
41944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.3957541944
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.3558940565
Short name T1270
Test name
Test status
Simulation time 8416657356 ps
CPU time 10.98 seconds
Started May 21 01:06:39 PM PDT 24
Finished May 21 01:06:50 PM PDT 24
Peak memory 205348 kb
Host smart-d93d9d32-6781-4b25-ac87-6f73adbadd86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35589
40565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.3558940565
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.4201118597
Short name T422
Test name
Test status
Simulation time 8364797203 ps
CPU time 11.96 seconds
Started May 21 01:06:35 PM PDT 24
Finished May 21 01:06:49 PM PDT 24
Peak memory 205376 kb
Host smart-f3d7fadf-70c2-42a2-b273-ca60e3d0c4ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42011
18597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.4201118597
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.2354670066
Short name T1018
Test name
Test status
Simulation time 8388346243 ps
CPU time 11.11 seconds
Started May 21 01:06:40 PM PDT 24
Finished May 21 01:06:52 PM PDT 24
Peak memory 205344 kb
Host smart-aebd2559-7f04-4bfd-8225-d63ae8525a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23546
70066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.2354670066
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.91384787
Short name T494
Test name
Test status
Simulation time 8400051187 ps
CPU time 12.17 seconds
Started May 21 01:06:37 PM PDT 24
Finished May 21 01:06:50 PM PDT 24
Peak memory 205332 kb
Host smart-9a2ae93c-3de9-49cb-b443-acb3c5b70c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91384
787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.91384787
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.3747731569
Short name T1473
Test name
Test status
Simulation time 8472888925 ps
CPU time 12.18 seconds
Started May 21 01:06:31 PM PDT 24
Finished May 21 01:06:44 PM PDT 24
Peak memory 205380 kb
Host smart-4bcda75d-63d1-4e86-8138-edd1b8d01222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37477
31569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.3747731569
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.1260618227
Short name T288
Test name
Test status
Simulation time 8406981453 ps
CPU time 12.17 seconds
Started May 21 01:06:41 PM PDT 24
Finished May 21 01:06:54 PM PDT 24
Peak memory 205252 kb
Host smart-6ca315f2-0daa-42f1-960c-a12f104fd7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12606
18227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.1260618227
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.4285498097
Short name T616
Test name
Test status
Simulation time 8394908264 ps
CPU time 11.66 seconds
Started May 21 01:06:35 PM PDT 24
Finished May 21 01:06:48 PM PDT 24
Peak memory 205368 kb
Host smart-e47c53a8-018f-4741-a8a9-cad6163bf957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42854
98097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.4285498097
Directory /workspace/9.usbdev_stall_trans/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%