Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	39152	1		T1	4		T2	3		T3	2
all_values[1]	39152	1		T1	4		T2	3		T3	2
all_values[2]	39152	1		T1	4		T2	3		T3	2
all_values[3]	39152	1		T1	4		T2	3		T3	2
all_values[4]	39152	1		T1	4		T2	3		T3	2
all_values[5]	39152	1		T1	4		T2	3		T3	2
all_values[6]	39152	1		T1	4		T2	3		T3	2
all_values[7]	39152	1		T1	4		T2	3		T3	2
all_values[8]	39152	1		T1	4		T2	3		T3	2
all_values[9]	39152	1		T1	4		T2	3		T3	2
all_values[10]	39152	1		T1	4		T2	3		T3	2
all_values[11]	39152	1		T1	4		T2	3		T3	2
all_values[12]	39152	1		T1	4		T2	3		T3	2
all_values[13]	39152	1		T1	4		T2	3		T3	2
all_values[14]	39152	1		T1	4		T2	3		T3	2
all_values[15]	39152	1		T1	4		T2	3		T3	2
all_values[16]	39152	1		T1	4		T2	3		T3	2
all_values[17]	39152	1		T1	4		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	698537	1		T1	68		T2	54		T3	36
auto[1]	6199	1		T1	4		T26	2		T4	4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	699778	1		T1	72		T2	54		T3	36
auto[1]	4958	1		T99	62		T100	75		T101	76

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	38153	1		T1	4		T2	3		T3	2
all_values[0]	auto[0]	auto[1]	129	1		T101	1		T204	4		T205	1
all_values[0]	auto[1]	auto[0]	737	1		T19	3		T67	4		T44	3
all_values[0]	auto[1]	auto[1]	133	1		T99	3		T100	3		T101	4
all_values[1]	auto[0]	auto[0]	36520	1		T2	3		T3	2		T26	2
all_values[1]	auto[0]	auto[1]	129	1		T99	3		T101	1		T204	1
all_values[1]	auto[1]	auto[0]	2364	1		T1	4		T4	4		T5	4
all_values[1]	auto[1]	auto[1]	139	1		T99	1		T100	3		T101	3
all_values[2]	auto[0]	auto[0]	38753	1		T1	4		T2	3		T3	2
all_values[2]	auto[0]	auto[1]	143	1		T100	4		T204	1		T205	4
all_values[2]	auto[1]	auto[0]	131	1		T15	2		T32	2		T34	2
all_values[2]	auto[1]	auto[1]	125	1		T100	1		T204	3		T205	1
all_values[3]	auto[0]	auto[0]	38840	1		T1	4		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	152	1		T100	3		T101	4		T204	4
all_values[3]	auto[1]	auto[0]	32	1		T99	2		T100	1		T278	1
all_values[3]	auto[1]	auto[1]	128	1		T101	1		T204	1		T205	4
all_values[4]	auto[0]	auto[0]	38849	1		T1	4		T2	3		T3	2
all_values[4]	auto[0]	auto[1]	138	1		T99	4		T101	1		T204	5
all_values[4]	auto[1]	auto[0]	29	1		T290	2		T278	1		T280	4
all_values[4]	auto[1]	auto[1]	136	1		T99	1		T100	3		T101	3
all_values[5]	auto[0]	auto[0]	38842	1		T1	4		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	144	1		T100	4		T204	1		T205	1
all_values[5]	auto[1]	auto[0]	24	1		T205	1		T290	1		T291	3
all_values[5]	auto[1]	auto[1]	142	1		T99	5		T100	1		T101	5
all_values[6]	auto[0]	auto[0]	38852	1		T1	4		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	115	1		T99	3		T101	1		T205	3
all_values[6]	auto[1]	auto[0]	33	1		T290	1		T206	1		T292	1
all_values[6]	auto[1]	auto[1]	152	1		T99	1		T100	5		T101	4
all_values[7]	auto[0]	auto[0]	38837	1		T1	4		T2	3		T3	2
all_values[7]	auto[0]	auto[1]	148	1		T99	4		T205	3		T290	3
all_values[7]	auto[1]	auto[0]	25	1		T204	1		T206	1		T291	1
all_values[7]	auto[1]	auto[1]	142	1		T100	5		T101	5		T204	4
all_values[8]	auto[0]	auto[0]	38846	1		T1	4		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	133	1		T99	3		T100	3		T101	3
all_values[8]	auto[1]	auto[0]	21	1		T99	2		T101	1		T205	1
all_values[8]	auto[1]	auto[1]	152	1		T100	2		T204	1		T290	1
all_values[9]	auto[0]	auto[0]	38849	1		T1	4		T2	3		T3	2
all_values[9]	auto[0]	auto[1]	131	1		T99	1		T100	3		T101	1
all_values[9]	auto[1]	auto[0]	33	1		T99	1		T205	1		T278	4
all_values[9]	auto[1]	auto[1]	139	1		T99	3		T100	1		T101	4
all_values[10]	auto[0]	auto[0]	38847	1		T1	4		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	174	1		T99	1		T100	3		T204	3
all_values[10]	auto[1]	auto[0]	11	1		T100	1		T204	1		T278	2
all_values[10]	auto[1]	auto[1]	120	1		T99	4		T101	5		T206	1
all_values[11]	auto[0]	auto[0]	38755	1		T1	4		T2	3		T3	2
all_values[11]	auto[0]	auto[1]	142	1		T100	3		T101	1		T204	5
all_values[11]	auto[1]	auto[0]	120	1		T26	2		T42	2		T43	2
all_values[11]	auto[1]	auto[1]	135	1		T100	1		T101	4		T278	3
all_values[12]	auto[0]	auto[0]	38852	1		T1	4		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	126	1		T99	3		T100	1		T204	1
all_values[12]	auto[1]	auto[0]	30	1		T99	1		T290	1		T280	2
all_values[12]	auto[1]	auto[1]	144	1		T100	4		T101	3		T204	4
all_values[13]	auto[0]	auto[0]	38847	1		T1	4		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	134	1		T99	3		T100	4		T101	3
all_values[13]	auto[1]	auto[0]	27	1		T204	1		T278	1		T293	1
all_values[13]	auto[1]	auto[1]	144	1		T99	1		T100	1		T101	2
all_values[14]	auto[0]	auto[0]	38850	1		T1	4		T2	3		T3	2
all_values[14]	auto[0]	auto[1]	139	1		T99	4		T100	5		T101	4
all_values[14]	auto[1]	auto[0]	20	1		T101	1		T278	1		T294	1
all_values[14]	auto[1]	auto[1]	143	1		T99	1		T204	2		T205	4
all_values[15]	auto[0]	auto[0]	38871	1		T1	4		T2	3		T3	2
all_values[15]	auto[0]	auto[1]	131	1		T99	4		T100	4		T101	4
all_values[15]	auto[1]	auto[0]	39	1		T101	1		T206	3		T279	1
all_values[15]	auto[1]	auto[1]	111	1		T99	1		T100	1		T204	5
all_values[16]	auto[0]	auto[0]	38849	1		T1	4		T2	3		T3	2
all_values[16]	auto[0]	auto[1]	116	1		T100	4		T101	2		T204	3
all_values[16]	auto[1]	auto[0]	28	1		T99	1		T204	2		T205	1
all_values[16]	auto[1]	auto[1]	159	1		T99	4		T101	3		T205	3
all_values[17]	auto[0]	auto[0]	38845	1		T1	4		T2	3		T3	2
all_values[17]	auto[0]	auto[1]	156	1		T99	4		T101	4		T204	3
all_values[17]	auto[1]	auto[0]	17	1		T99	1		T100	2		T206	2
all_values[17]	auto[1]	auto[1]	134	1		T100	3		T204	2		T205	4