Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	39152	1		T1	4		T2	3		T3	2
all_pins[1]	39152	1		T1	4		T2	3		T3	2
all_pins[2]	39152	1		T1	4		T2	3		T3	2
all_pins[3]	39152	1		T1	4		T2	3		T3	2
all_pins[4]	39152	1		T1	4		T2	3		T3	2
all_pins[5]	39152	1		T1	4		T2	3		T3	2
all_pins[6]	39152	1		T1	4		T2	3		T3	2
all_pins[7]	39152	1		T1	4		T2	3		T3	2
all_pins[8]	39152	1		T1	4		T2	3		T3	2
all_pins[9]	39152	1		T1	4		T2	3		T3	2
all_pins[10]	39152	1		T1	4		T2	3		T3	2
all_pins[11]	39152	1		T1	4		T2	3		T3	2
all_pins[12]	39152	1		T1	4		T2	3		T3	2
all_pins[13]	39152	1		T1	4		T2	3		T3	2
all_pins[14]	39152	1		T1	4		T2	3		T3	2
all_pins[15]	39152	1		T1	4		T2	3		T3	2
all_pins[16]	39152	1		T1	4		T2	3		T3	2
all_pins[17]	39152	1		T1	4		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	702221	1		T1	71		T2	54		T3	36
values[0x1]	2515	1		T1	1		T26	1		T4	1
transitions[0x0=>0x1]	2238	1		T1	1		T26	1		T4	1
transitions[0x1=>0x0]	2251	1		T1	1		T26	1		T4	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	38991	1		T1	4		T2	3		T3	2
all_pins[0]	values[0x1]	161	1		T67	1		T295	1		T296	1
all_pins[0]	transitions[0x0=>0x1]	143	1		T67	1		T295	1		T296	1
all_pins[0]	transitions[0x1=>0x0]	1199	1		T1	1		T4	1		T5	1
all_pins[1]	values[0x0]	37935	1		T1	3		T2	3		T3	2
all_pins[1]	values[0x1]	1217	1		T1	1		T4	1		T5	1
all_pins[1]	transitions[0x0=>0x1]	1200	1		T1	1		T4	1		T5	1
all_pins[1]	transitions[0x1=>0x0]	112	1		T15	1		T32	1		T34	1
all_pins[2]	values[0x0]	39023	1		T1	4		T2	3		T3	2
all_pins[2]	values[0x1]	129	1		T15	1		T32	1		T34	1
all_pins[2]	transitions[0x0=>0x1]	113	1		T15	1		T32	1		T34	1
all_pins[2]	transitions[0x1=>0x0]	31	1		T279	2		T291	4		T297	1
all_pins[3]	values[0x0]	39105	1		T1	4		T2	3		T3	2
all_pins[3]	values[0x1]	47	1		T204	1		T278	2		T206	1
all_pins[3]	transitions[0x0=>0x1]	33	1		T204	1		T206	1		T279	2
all_pins[3]	transitions[0x1=>0x0]	44	1		T99	1		T100	2		T205	1
all_pins[4]	values[0x0]	39094	1		T1	4		T2	3		T3	2
all_pins[4]	values[0x1]	58	1		T99	1		T100	2		T205	1
all_pins[4]	transitions[0x0=>0x1]	43	1		T99	1		T100	2		T205	1
all_pins[4]	transitions[0x1=>0x0]	66	1		T99	2		T100	1		T101	4
all_pins[5]	values[0x0]	39071	1		T1	4		T2	3		T3	2
all_pins[5]	values[0x1]	81	1		T99	2		T100	1		T101	4
all_pins[5]	transitions[0x0=>0x1]	57	1		T99	2		T101	3		T204	1
all_pins[5]	transitions[0x1=>0x0]	54	1		T99	1		T100	2		T204	3
all_pins[6]	values[0x0]	39074	1		T1	4		T2	3		T3	2
all_pins[6]	values[0x1]	78	1		T99	1		T100	3		T101	1
all_pins[6]	transitions[0x0=>0x1]	70	1		T99	1		T100	2		T204	2
all_pins[6]	transitions[0x1=>0x0]	41	1		T101	2		T204	1		T205	1
all_pins[7]	values[0x0]	39103	1		T1	4		T2	3		T3	2
all_pins[7]	values[0x1]	49	1		T100	1		T101	3		T204	2
all_pins[7]	transitions[0x0=>0x1]	34	1		T101	3		T204	1		T205	2
all_pins[7]	transitions[0x1=>0x0]	48	1		T206	1		T279	1		T280	1
all_pins[8]	values[0x0]	39089	1		T1	4		T2	3		T3	2
all_pins[8]	values[0x1]	63	1		T100	1		T204	1		T290	1
all_pins[8]	transitions[0x0=>0x1]	45	1		T100	1		T204	1		T279	1
all_pins[8]	transitions[0x1=>0x0]	42	1		T206	1		T279	1		T280	2
all_pins[9]	values[0x0]	39092	1		T1	4		T2	3		T3	2
all_pins[9]	values[0x1]	60	1		T290	1		T206	2		T279	1
all_pins[9]	transitions[0x0=>0x1]	47	1		T290	1		T206	2		T279	1
all_pins[9]	transitions[0x1=>0x0]	48	1		T99	1		T101	2		T206	1
all_pins[10]	values[0x0]	39091	1		T1	4		T2	3		T3	2
all_pins[10]	values[0x1]	61	1		T99	1		T101	2		T206	1
all_pins[10]	transitions[0x0=>0x1]	47	1		T99	1		T101	2		T206	1
all_pins[10]	transitions[0x1=>0x0]	105	1		T26	1		T42	1		T43	1
all_pins[11]	values[0x0]	39033	1		T1	4		T2	3		T3	2
all_pins[11]	values[0x1]	119	1		T26	1		T42	1		T43	1
all_pins[11]	transitions[0x0=>0x1]	107	1		T26	1		T42	1		T43	1
all_pins[11]	transitions[0x1=>0x0]	60	1		T100	2		T204	3		T290	3
all_pins[12]	values[0x0]	39080	1		T1	4		T2	3		T3	2
all_pins[12]	values[0x1]	72	1		T100	3		T101	2		T204	3
all_pins[12]	transitions[0x0=>0x1]	62	1		T100	3		T101	2		T204	3
all_pins[12]	transitions[0x1=>0x0]	51	1		T100	1		T101	1		T278	1
all_pins[13]	values[0x0]	39091	1		T1	4		T2	3		T3	2
all_pins[13]	values[0x1]	61	1		T100	1		T101	1		T278	1
all_pins[13]	transitions[0x0=>0x1]	44	1		T100	1		T101	1		T278	1
all_pins[13]	transitions[0x1=>0x0]	52	1		T99	1		T204	2		T205	1
all_pins[14]	values[0x0]	39083	1		T1	4		T2	3		T3	2
all_pins[14]	values[0x1]	69	1		T99	1		T204	2		T205	1
all_pins[14]	transitions[0x0=>0x1]	59	1		T99	1		T205	1		T278	2
all_pins[14]	transitions[0x1=>0x0]	46	1		T100	1		T205	2		T290	1
all_pins[15]	values[0x0]	39096	1		T1	4		T2	3		T3	2
all_pins[15]	values[0x1]	56	1		T100	1		T204	2		T205	2
all_pins[15]	transitions[0x0=>0x1]	42	1		T100	1		T204	2		T205	2
all_pins[15]	transitions[0x1=>0x0]	65	1		T99	1		T101	2		T278	2
all_pins[16]	values[0x0]	39073	1		T1	4		T2	3		T3	2
all_pins[16]	values[0x1]	79	1		T99	1		T101	2		T290	1
all_pins[16]	transitions[0x0=>0x1]	63	1		T99	1		T101	2		T290	1
all_pins[16]	transitions[0x1=>0x0]	39	1		T100	1		T204	1		T205	2
all_pins[17]	values[0x0]	39097	1		T1	4		T2	3		T3	2
all_pins[17]	values[0x1]	55	1		T100	1		T204	1		T205	2
all_pins[17]	transitions[0x0=>0x1]	29	1		T100	1		T205	2		T290	1
all_pins[17]	transitions[0x1=>0x0]	148	1		T67	1		T295	1		T296	1