Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1		T99	4		T100	4		T101	4
all_values[1]	281	1		T99	4		T100	4		T101	4
all_values[2]	281	1		T99	4		T100	4		T101	4
all_values[3]	281	1		T99	4		T100	4		T101	4
all_values[4]	281	1		T99	4		T100	4		T101	4
all_values[5]	281	1		T99	4		T100	4		T101	4
all_values[6]	281	1		T99	4		T100	4		T101	4
all_values[7]	281	1		T99	4		T100	4		T101	4
all_values[8]	281	1		T99	4		T100	4		T101	4
all_values[9]	281	1		T99	4		T100	4		T101	4
all_values[10]	281	1		T99	4		T100	4		T101	4
all_values[11]	281	1		T99	4		T100	4		T101	4
all_values[12]	281	1		T99	4		T100	4		T101	4
all_values[13]	281	1		T99	4		T100	4		T101	4
all_values[14]	281	1		T99	4		T100	4		T101	4
all_values[15]	281	1		T99	4		T100	4		T101	4
all_values[16]	281	1		T99	4		T100	4		T101	4
all_values[17]	281	1		T99	4		T100	4		T101	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2792	1		T99	51		T100	38		T101	44
auto[1]	2266	1		T99	21		T100	34		T101	28

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	935	1		T99	25		T100	15		T101	13
auto[1]	4123	1		T99	47		T100	57		T101	59

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3007	1		T99	52		T100	38		T101	44
auto[1]	2051	1		T99	20		T100	34		T101	28

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	35	1		T99	2		T100	1		T205	1
all_values[0]	auto[0]	auto[0]	auto[1]	48	1		T101	1		T204	1		T205	1
all_values[0]	auto[0]	auto[1]	auto[0]	28	1		T100	1		T290	3		T278	4
all_values[0]	auto[0]	auto[1]	auto[1]	50	1		T99	1		T100	1		T101	2
all_values[0]	auto[1]	auto[0]	auto[1]	69	1		T101	1		T204	3		T205	1
all_values[0]	auto[1]	auto[1]	auto[1]	51	1		T99	1		T100	1		T206	1
all_values[1]	auto[0]	auto[0]	auto[0]	38	1		T99	1		T100	1		T101	1
all_values[1]	auto[0]	auto[0]	auto[1]	58	1		T99	2		T101	1		T205	2
all_values[1]	auto[0]	auto[1]	auto[0]	20	1		T100	1		T290	1		T297	1
all_values[1]	auto[0]	auto[1]	auto[1]	55	1		T100	1		T101	1		T204	2
all_values[1]	auto[1]	auto[0]	auto[1]	54	1		T101	1		T204	1		T205	2
all_values[1]	auto[1]	auto[1]	auto[1]	56	1		T99	1		T100	1		T204	1
all_values[2]	auto[0]	auto[0]	auto[0]	40	1		T99	3		T101	3		T204	1
all_values[2]	auto[0]	auto[0]	auto[1]	59	1		T100	1		T204	1		T205	2
all_values[2]	auto[0]	auto[1]	auto[0]	19	1		T99	1		T101	1		T279	1
all_values[2]	auto[0]	auto[1]	auto[1]	48	1		T204	1		T290	1		T278	2
all_values[2]	auto[1]	auto[0]	auto[1]	56	1		T100	2		T204	1		T205	2
all_values[2]	auto[1]	auto[1]	auto[1]	59	1		T100	1		T290	1		T278	2
all_values[3]	auto[0]	auto[0]	auto[0]	27	1		T99	3		T100	1		T280	1
all_values[3]	auto[0]	auto[0]	auto[1]	60	1		T100	1		T101	2		T204	2
all_values[3]	auto[0]	auto[1]	auto[0]	21	1		T99	1		T100	1		T278	1
all_values[3]	auto[0]	auto[1]	auto[1]	54	1		T205	1		T278	2		T206	1
all_values[3]	auto[1]	auto[0]	auto[1]	67	1		T100	1		T101	1		T204	2
all_values[3]	auto[1]	auto[1]	auto[1]	52	1		T101	1		T205	2		T278	1
all_values[4]	auto[0]	auto[0]	auto[0]	31	1		T100	2		T101	1		T290	1
all_values[4]	auto[0]	auto[0]	auto[1]	61	1		T99	2		T204	3		T205	3
all_values[4]	auto[0]	auto[1]	auto[0]	22	1		T290	1		T278	1		T280	1
all_values[4]	auto[0]	auto[1]	auto[1]	57	1		T100	1		T101	1		T290	1
all_values[4]	auto[1]	auto[0]	auto[1]	62	1		T99	2		T101	2		T204	1
all_values[4]	auto[1]	auto[1]	auto[1]	48	1		T100	1		T290	1		T278	2
all_values[5]	auto[0]	auto[0]	auto[0]	20	1		T205	1		T290	3		T206	1
all_values[5]	auto[0]	auto[0]	auto[1]	59	1		T100	1		T278	2		T206	1
all_values[5]	auto[0]	auto[1]	auto[0]	22	1		T290	1		T291	4		T294	1
all_values[5]	auto[0]	auto[1]	auto[1]	62	1		T99	2		T101	3		T204	2
all_values[5]	auto[1]	auto[0]	auto[1]	65	1		T99	1		T100	2		T101	1
all_values[5]	auto[1]	auto[1]	auto[1]	53	1		T99	1		T100	1		T204	1
all_values[6]	auto[0]	auto[0]	auto[0]	36	1		T99	1		T290	4		T206	1
all_values[6]	auto[0]	auto[0]	auto[1]	47	1		T99	2		T101	1		T205	1
all_values[6]	auto[0]	auto[1]	auto[0]	22	1		T298	4		T299	2		T300	2
all_values[6]	auto[0]	auto[1]	auto[1]	58	1		T100	1		T101	2		T204	2
all_values[6]	auto[1]	auto[0]	auto[1]	69	1		T99	1		T101	1		T204	1
all_values[6]	auto[1]	auto[1]	auto[1]	49	1		T100	3		T204	1		T205	2
all_values[7]	auto[0]	auto[0]	auto[0]	22	1		T99	1		T204	1		T278	1
all_values[7]	auto[0]	auto[0]	auto[1]	65	1		T99	2		T205	1		T290	1
all_values[7]	auto[0]	auto[1]	auto[0]	17	1		T292	1		T301	2		T298	2
all_values[7]	auto[0]	auto[1]	auto[1]	66	1		T100	3		T101	1		T204	1
all_values[7]	auto[1]	auto[0]	auto[1]	66	1		T99	1		T101	1		T205	1
all_values[7]	auto[1]	auto[1]	auto[1]	45	1		T100	1		T101	2		T204	2
all_values[8]	auto[0]	auto[0]	auto[0]	32	1		T99	1		T101	2		T204	1
all_values[8]	auto[0]	auto[0]	auto[1]	49	1		T99	1		T100	1		T101	1
all_values[8]	auto[0]	auto[1]	auto[0]	13	1		T99	1		T278	2		T206	1
all_values[8]	auto[0]	auto[1]	auto[1]	63	1		T100	1		T290	1		T206	2
all_values[8]	auto[1]	auto[0]	auto[1]	70	1		T99	1		T100	1		T205	1
all_values[8]	auto[1]	auto[1]	auto[1]	54	1		T100	1		T101	1		T204	2
all_values[9]	auto[0]	auto[0]	auto[0]	38	1		T99	1		T100	1		T205	1
all_values[9]	auto[0]	auto[0]	auto[1]	57	1		T100	1		T101	1		T204	1
all_values[9]	auto[0]	auto[1]	auto[0]	19	1		T278	2		T293	4		T280	1
all_values[9]	auto[0]	auto[1]	auto[1]	66	1		T99	2		T101	1		T204	1
all_values[9]	auto[1]	auto[0]	auto[1]	54	1		T100	1		T101	1		T204	2
all_values[9]	auto[1]	auto[1]	auto[1]	47	1		T99	1		T100	1		T101	1
all_values[10]	auto[0]	auto[0]	auto[0]	28	1		T100	1		T204	2		T205	1
all_values[10]	auto[0]	auto[0]	auto[1]	71	1		T100	1		T204	1		T205	2
all_values[10]	auto[0]	auto[1]	auto[0]	9	1		T100	1		T278	2		T302	1
all_values[10]	auto[0]	auto[1]	auto[1]	52	1		T99	2		T101	3		T280	1
all_values[10]	auto[1]	auto[0]	auto[1]	82	1		T99	1		T100	1		T101	1
all_values[10]	auto[1]	auto[1]	auto[1]	39	1		T99	1		T206	1		T279	2
all_values[11]	auto[0]	auto[0]	auto[0]	38	1		T99	3		T205	4		T290	1
all_values[11]	auto[0]	auto[0]	auto[1]	62	1		T100	1		T101	1		T204	2
all_values[11]	auto[0]	auto[1]	auto[0]	12	1		T99	1		T100	1		T293	1
all_values[11]	auto[0]	auto[1]	auto[1]	53	1		T101	1		T278	2		T206	1
all_values[11]	auto[1]	auto[0]	auto[1]	65	1		T100	1		T101	1		T204	2
all_values[11]	auto[1]	auto[1]	auto[1]	51	1		T100	1		T101	1		T206	1
all_values[12]	auto[0]	auto[0]	auto[0]	37	1		T99	2		T101	2		T205	4
all_values[12]	auto[0]	auto[0]	auto[1]	58	1		T99	1		T278	1		T206	3
all_values[12]	auto[0]	auto[1]	auto[0]	19	1		T280	1		T291	1		T303	1
all_values[12]	auto[0]	auto[1]	auto[1]	59	1		T100	2		T101	1		T204	2
all_values[12]	auto[1]	auto[0]	auto[1]	54	1		T99	1		T100	1		T101	1
all_values[12]	auto[1]	auto[1]	auto[1]	54	1		T100	1		T204	1		T290	2
all_values[13]	auto[0]	auto[0]	auto[0]	34	1		T99	1		T204	1		T206	1
all_values[13]	auto[0]	auto[0]	auto[1]	59	1		T99	2		T100	2		T101	1
all_values[13]	auto[0]	auto[1]	auto[0]	18	1		T278	1		T280	1		T303	1
all_values[13]	auto[0]	auto[1]	auto[1]	67	1		T101	2		T204	2		T290	1
all_values[13]	auto[1]	auto[0]	auto[1]	62	1		T99	1		T100	1		T101	1
all_values[13]	auto[1]	auto[1]	auto[1]	41	1		T100	1		T204	1		T290	1
all_values[14]	auto[0]	auto[0]	auto[0]	29	1		T101	1		T205	1		T294	1
all_values[14]	auto[0]	auto[0]	auto[1]	65	1		T99	2		T100	1		T101	1
all_values[14]	auto[0]	auto[1]	auto[0]	17	1		T278	2		T303	3		T304	3
all_values[14]	auto[0]	auto[1]	auto[1]	61	1		T99	1		T204	2		T205	2
all_values[14]	auto[1]	auto[0]	auto[1]	66	1		T99	1		T100	3		T101	1
all_values[14]	auto[1]	auto[1]	auto[1]	43	1		T101	1		T205	1		T278	1
all_values[15]	auto[0]	auto[0]	auto[0]	47	1		T101	1		T206	4		T291	1
all_values[15]	auto[0]	auto[0]	auto[1]	54	1		T99	2		T100	1		T101	1
all_values[15]	auto[0]	auto[1]	auto[0]	35	1		T206	1		T279	1		T303	2
all_values[15]	auto[0]	auto[1]	auto[1]	38	1		T204	2		T205	1		T278	2
all_values[15]	auto[1]	auto[0]	auto[1]	62	1		T99	2		T100	2		T101	1
all_values[15]	auto[1]	auto[1]	auto[1]	45	1		T100	1		T101	1		T204	1
all_values[16]	auto[0]	auto[0]	auto[0]	35	1		T99	1		T100	1		T204	1
all_values[16]	auto[0]	auto[0]	auto[1]	45	1		T100	1		T204	1		T205	1
all_values[16]	auto[0]	auto[1]	auto[0]	16	1		T204	1		T297	1		T281	2
all_values[16]	auto[0]	auto[1]	auto[1]	62	1		T99	2		T101	1		T205	1
all_values[16]	auto[1]	auto[0]	auto[1]	62	1		T100	2		T101	3		T205	1
all_values[16]	auto[1]	auto[1]	auto[1]	61	1		T99	1		T204	1		T278	1
all_values[17]	auto[0]	auto[0]	auto[0]	26	1		T99	1		T101	1		T290	2
all_values[17]	auto[0]	auto[0]	auto[1]	69	1		T99	1		T101	1		T204	1
all_values[17]	auto[0]	auto[1]	auto[0]	13	1		T100	2		T206	2		T291	1
all_values[17]	auto[0]	auto[1]	auto[1]	55	1		T100	1		T204	1		T205	1
all_values[17]	auto[1]	auto[0]	auto[1]	68	1		T99	1		T101	2		T204	1
all_values[17]	auto[1]	auto[1]	auto[1]	50	1		T99	1		T100	1		T204	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal