Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	31815	1		T1	2		T2	4		T3	2
all_values[1]	31815	1		T1	2		T2	4		T3	2
all_values[2]	31815	1		T1	2		T2	4		T3	2
all_values[3]	31815	1		T1	2		T2	4		T3	2
all_values[4]	31815	1		T1	2		T2	4		T3	2
all_values[5]	31815	1		T1	2		T2	4		T3	2
all_values[6]	31815	1		T1	2		T2	4		T3	2
all_values[7]	31815	1		T1	2		T2	4		T3	2
all_values[8]	31815	1		T1	2		T2	4		T3	2
all_values[9]	31815	1		T1	2		T2	4		T3	2
all_values[10]	31815	1		T1	2		T2	4		T3	2
all_values[11]	31815	1		T1	2		T2	4		T3	2
all_values[12]	31815	1		T1	2		T2	4		T3	2
all_values[13]	31815	1		T1	2		T2	4		T3	2
all_values[14]	31815	1		T1	2		T2	4		T3	2
all_values[15]	31815	1		T1	2		T2	4		T3	2
all_values[16]	31815	1		T1	2		T2	4		T3	2
all_values[17]	31815	1		T1	2		T2	4		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	566699	1		T1	36		T2	72		T3	36
auto[1]	5971	1		T25	3		T26	4		T33	18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	567875	1		T1	36		T2	72		T3	36
auto[1]	4795	1		T96	80		T97	129		T99	122

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	30819	1		T1	2		T2	4		T3	2
all_values[0]	auto[0]	auto[1]	139	1		T97	4		T99	2		T214	4
all_values[0]	auto[1]	auto[0]	720	1		T26	4		T72	4		T73	4
all_values[0]	auto[1]	auto[1]	137	1		T96	5		T97	4		T99	6
all_values[1]	auto[0]	auto[0]	29274	1		T1	2		T2	4		T3	2
all_values[1]	auto[0]	auto[1]	127	1		T96	3		T97	6		T99	2
all_values[1]	auto[1]	auto[0]	2266	1		T25	3		T33	18		T38	4
all_values[1]	auto[1]	auto[1]	148	1		T96	1		T97	2		T99	5
all_values[2]	auto[0]	auto[0]	31416	1		T1	2		T2	4		T3	2
all_values[2]	auto[0]	auto[1]	159	1		T96	3		T97	3		T99	4
all_values[2]	auto[1]	auto[0]	125	1		T48	2		T52	2		T53	2
all_values[2]	auto[1]	auto[1]	115	1		T96	1		T97	4		T213	6
all_values[3]	auto[0]	auto[0]	31527	1		T1	2		T2	4		T3	2
all_values[3]	auto[0]	auto[1]	126	1		T96	2		T97	3		T99	2
all_values[3]	auto[1]	auto[0]	35	1		T214	1		T215	1		T281	1
all_values[3]	auto[1]	auto[1]	127	1		T96	3		T97	4		T99	6
all_values[4]	auto[0]	auto[0]	31519	1		T1	2		T2	4		T3	2
all_values[4]	auto[0]	auto[1]	114	1		T96	5		T97	5		T214	1
all_values[4]	auto[1]	auto[0]	43	1		T99	1		T215	2		T282	1
all_values[4]	auto[1]	auto[1]	139	1		T97	3		T99	3		T214	3
all_values[5]	auto[0]	auto[0]	31517	1		T1	2		T2	4		T3	2
all_values[5]	auto[0]	auto[1]	128	1		T96	1		T97	6		T99	7
all_values[5]	auto[1]	auto[0]	32	1		T214	3		T215	1		T213	2
all_values[5]	auto[1]	auto[1]	138	1		T96	4		T97	2		T99	1
all_values[6]	auto[0]	auto[0]	31515	1		T1	2		T2	4		T3	2
all_values[6]	auto[0]	auto[1]	150	1		T96	4		T97	2		T99	1
all_values[6]	auto[1]	auto[0]	32	1		T99	3		T214	2		T283	1
all_values[6]	auto[1]	auto[1]	118	1		T96	1		T97	5		T99	4
all_values[7]	auto[0]	auto[0]	31526	1		T1	2		T2	4		T3	2
all_values[7]	auto[0]	auto[1]	133	1		T97	7		T99	5		T215	3
all_values[7]	auto[1]	auto[0]	36	1		T96	3		T215	1		T213	1
all_values[7]	auto[1]	auto[1]	120	1		T97	1		T99	1		T214	4
all_values[8]	auto[0]	auto[0]	31511	1		T1	2		T2	4		T3	2
all_values[8]	auto[0]	auto[1]	160	1		T96	4		T97	6		T99	3
all_values[8]	auto[1]	auto[0]	27	1		T214	1		T215	1		T213	1
all_values[8]	auto[1]	auto[1]	117	1		T96	1		T97	2		T99	5
all_values[9]	auto[0]	auto[0]	31512	1		T1	2		T2	4		T3	2
all_values[9]	auto[0]	auto[1]	137	1		T96	5		T97	6		T99	1
all_values[9]	auto[1]	auto[0]	27	1		T282	1		T284	1		T285	2
all_values[9]	auto[1]	auto[1]	139	1		T97	2		T99	6		T214	3
all_values[10]	auto[0]	auto[0]	31518	1		T1	2		T2	4		T3	2
all_values[10]	auto[0]	auto[1]	150	1		T97	7		T99	4		T214	1
all_values[10]	auto[1]	auto[0]	27	1		T96	1		T283	4		T286	2
all_values[10]	auto[1]	auto[1]	120	1		T96	4		T99	4		T214	4
all_values[11]	auto[0]	auto[0]	31404	1		T1	2		T2	4		T3	2
all_values[11]	auto[0]	auto[1]	163	1		T96	1		T97	5		T99	5
all_values[11]	auto[1]	auto[0]	117	1		T56	2		T57	2		T58	2
all_values[11]	auto[1]	auto[1]	131	1		T96	3		T97	3		T99	3
all_values[12]	auto[0]	auto[0]	31520	1		T1	2		T2	4		T3	2
all_values[12]	auto[0]	auto[1]	134	1		T96	4		T97	5		T99	6
all_values[12]	auto[1]	auto[0]	33	1		T215	1		T281	1		T287	2
all_values[12]	auto[1]	auto[1]	128	1		T96	1		T97	3		T99	2
all_values[13]	auto[0]	auto[0]	31521	1		T1	2		T2	4		T3	2
all_values[13]	auto[0]	auto[1]	137	1		T96	4		T97	5		T99	1
all_values[13]	auto[1]	auto[0]	31	1		T281	1		T288	1		T289	3
all_values[13]	auto[1]	auto[1]	126	1		T96	1		T97	2		T99	7
all_values[14]	auto[0]	auto[0]	31531	1		T1	2		T2	4		T3	2
all_values[14]	auto[0]	auto[1]	129	1		T96	4		T97	1		T99	3
all_values[14]	auto[1]	auto[0]	31	1		T97	1		T284	1		T290	1
all_values[14]	auto[1]	auto[1]	124	1		T96	1		T97	6		T99	5
all_values[15]	auto[0]	auto[0]	31531	1		T1	2		T2	4		T3	2
all_values[15]	auto[0]	auto[1]	122	1		T96	3		T99	5		T215	2
all_values[15]	auto[1]	auto[0]	38	1		T97	2		T214	4		T284	1
all_values[15]	auto[1]	auto[1]	124	1		T96	2		T99	3		T215	3
all_values[16]	auto[0]	auto[0]	31528	1		T1	2		T2	4		T3	2
all_values[16]	auto[0]	auto[1]	151	1		T97	8		T214	4		T213	7
all_values[16]	auto[1]	auto[0]	27	1		T214	1		T215	1		T282	4
all_values[16]	auto[1]	auto[1]	109	1		T96	5		T99	4		T215	3
all_values[17]	auto[0]	auto[0]	31514	1		T1	2		T2	4		T3	2
all_values[17]	auto[0]	auto[1]	137	1		T96	3		T97	5		T99	2
all_values[17]	auto[1]	auto[0]	25	1		T96	1		T97	1		T99	1
all_values[17]	auto[1]	auto[1]	139	1		T96	1		T97	2		T99	4