Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	31815	1		T1	2		T2	4		T3	2
all_pins[1]	31815	1		T1	2		T2	4		T3	2
all_pins[2]	31815	1		T1	2		T2	4		T3	2
all_pins[3]	31815	1		T1	2		T2	4		T3	2
all_pins[4]	31815	1		T1	2		T2	4		T3	2
all_pins[5]	31815	1		T1	2		T2	4		T3	2
all_pins[6]	31815	1		T1	2		T2	4		T3	2
all_pins[7]	31815	1		T1	2		T2	4		T3	2
all_pins[8]	31815	1		T1	2		T2	4		T3	2
all_pins[9]	31815	1		T1	2		T2	4		T3	2
all_pins[10]	31815	1		T1	2		T2	4		T3	2
all_pins[11]	31815	1		T1	2		T2	4		T3	2
all_pins[12]	31815	1		T1	2		T2	4		T3	2
all_pins[13]	31815	1		T1	2		T2	4		T3	2
all_pins[14]	31815	1		T1	2		T2	4		T3	2
all_pins[15]	31815	1		T1	2		T2	4		T3	2
all_pins[16]	31815	1		T1	2		T2	4		T3	2
all_pins[17]	31815	1		T1	2		T2	4		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	570267	1		T1	36		T2	72		T3	36
values[0x1]	2403	1		T25	1		T26	1		T33	16
transitions[0x0=>0x1]	2117	1		T25	1		T26	1		T33	16
transitions[0x1=>0x0]	2131	1		T25	1		T26	1		T33	16

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	31657	1		T1	2		T2	4		T3	2
all_pins[0]	values[0x1]	158	1		T26	1		T72	1		T73	1
all_pins[0]	transitions[0x0=>0x1]	144	1		T26	1		T72	1		T73	1
all_pins[0]	transitions[0x1=>0x0]	1175	1		T25	1		T33	16		T38	1
all_pins[1]	values[0x0]	30626	1		T1	2		T2	4		T3	2
all_pins[1]	values[0x1]	1189	1		T25	1		T33	16		T38	1
all_pins[1]	transitions[0x0=>0x1]	1168	1		T25	1		T33	16		T38	1
all_pins[1]	transitions[0x1=>0x0]	86	1		T48	1		T52	1		T53	1
all_pins[2]	values[0x0]	31708	1		T1	2		T2	4		T3	2
all_pins[2]	values[0x1]	107	1		T48	1		T52	1		T53	1
all_pins[2]	transitions[0x0=>0x1]	100	1		T48	1		T52	1		T53	1
all_pins[2]	transitions[0x1=>0x0]	51	1		T96	2		T97	3		T99	2
all_pins[3]	values[0x0]	31757	1		T1	2		T2	4		T3	2
all_pins[3]	values[0x1]	58	1		T96	2		T97	3		T99	2
all_pins[3]	transitions[0x0=>0x1]	43	1		T96	2		T97	3		T99	2
all_pins[3]	transitions[0x1=>0x0]	43	1		T97	1		T99	2		T282	2
all_pins[4]	values[0x0]	31757	1		T1	2		T2	4		T3	2
all_pins[4]	values[0x1]	58	1		T97	1		T99	2		T213	2
all_pins[4]	transitions[0x0=>0x1]	48	1		T97	1		T99	2		T213	2
all_pins[4]	transitions[0x1=>0x0]	50	1		T97	2		T281	2		T282	1
all_pins[5]	values[0x0]	31755	1		T1	2		T2	4		T3	2
all_pins[5]	values[0x1]	60	1		T97	2		T281	2		T282	3
all_pins[5]	transitions[0x0=>0x1]	46	1		T97	2		T281	2		T282	1
all_pins[5]	transitions[0x1=>0x0]	38	1		T97	3		T99	3		T213	4
all_pins[6]	values[0x0]	31763	1		T1	2		T2	4		T3	2
all_pins[6]	values[0x1]	52	1		T97	3		T99	3		T213	4
all_pins[6]	transitions[0x0=>0x1]	41	1		T97	3		T99	3		T213	4
all_pins[6]	transitions[0x1=>0x0]	34	1		T214	1		T283	1		T284	3
all_pins[7]	values[0x0]	31770	1		T1	2		T2	4		T3	2
all_pins[7]	values[0x1]	45	1		T214	1		T283	3		T284	3
all_pins[7]	transitions[0x0=>0x1]	36	1		T214	1		T283	3		T284	3
all_pins[7]	transitions[0x1=>0x0]	47	1		T96	1		T97	1		T99	1
all_pins[8]	values[0x0]	31759	1		T1	2		T2	4		T3	2
all_pins[8]	values[0x1]	56	1		T96	1		T97	1		T99	1
all_pins[8]	transitions[0x0=>0x1]	41	1		T96	1		T97	1		T213	2
all_pins[8]	transitions[0x1=>0x0]	52	1		T99	3		T215	3		T281	1
all_pins[9]	values[0x0]	31748	1		T1	2		T2	4		T3	2
all_pins[9]	values[0x1]	67	1		T99	4		T215	4		T281	1
all_pins[9]	transitions[0x0=>0x1]	42	1		T99	4		T215	4		T282	2
all_pins[9]	transitions[0x1=>0x0]	37	1		T96	3		T99	2		T214	3
all_pins[10]	values[0x0]	31753	1		T1	2		T2	4		T3	2
all_pins[10]	values[0x1]	62	1		T96	3		T99	2		T214	3
all_pins[10]	transitions[0x0=>0x1]	45	1		T96	1		T99	1		T214	3
all_pins[10]	transitions[0x1=>0x0]	105	1		T56	1		T57	1		T58	1
all_pins[11]	values[0x0]	31693	1		T1	2		T2	4		T3	2
all_pins[11]	values[0x1]	122	1		T56	1		T57	1		T58	1
all_pins[11]	transitions[0x0=>0x1]	103	1		T56	1		T57	1		T58	1
all_pins[11]	transitions[0x1=>0x0]	41	1		T96	1		T97	2		T214	1
all_pins[12]	values[0x0]	31755	1		T1	2		T2	4		T3	2
all_pins[12]	values[0x1]	60	1		T96	1		T97	2		T99	1
all_pins[12]	transitions[0x0=>0x1]	47	1		T96	1		T97	2		T99	1
all_pins[12]	transitions[0x1=>0x0]	42	1		T97	1		T99	6		T215	2
all_pins[13]	values[0x0]	31760	1		T1	2		T2	4		T3	2
all_pins[13]	values[0x1]	55	1		T97	1		T99	6		T215	2
all_pins[13]	transitions[0x0=>0x1]	40	1		T97	1		T99	5		T213	2
all_pins[13]	transitions[0x1=>0x0]	47	1		T97	2		T99	1		T214	2
all_pins[14]	values[0x0]	31753	1		T1	2		T2	4		T3	2
all_pins[14]	values[0x1]	62	1		T97	2		T99	2		T214	2
all_pins[14]	transitions[0x0=>0x1]	46	1		T97	2		T214	2		T215	1
all_pins[14]	transitions[0x1=>0x0]	38	1		T96	1		T281	4		T282	1
all_pins[15]	values[0x0]	31761	1		T1	2		T2	4		T3	2
all_pins[15]	values[0x1]	54	1		T96	1		T99	2		T215	2
all_pins[15]	transitions[0x0=>0x1]	40	1		T96	1		T99	2		T213	2
all_pins[15]	transitions[0x1=>0x0]	57	1		T96	3		T99	3		T281	2
all_pins[16]	values[0x0]	31744	1		T1	2		T2	4		T3	2
all_pins[16]	values[0x1]	71	1		T96	3		T99	3		T215	2
all_pins[16]	transitions[0x0=>0x1]	50	1		T96	2		T99	3		T215	2
all_pins[16]	transitions[0x1=>0x0]	46	1		T97	1		T214	1		T213	1
all_pins[17]	values[0x0]	31748	1		T1	2		T2	4		T3	2
all_pins[17]	values[0x1]	67	1		T96	1		T97	1		T214	1
all_pins[17]	transitions[0x0=>0x1]	37	1		T97	1		T214	1		T284	1
all_pins[17]	transitions[0x1=>0x0]	142	1		T26	1		T72	1		T73	1