Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1		T96	4		T97	7		T99	7
all_values[1]	272	1		T96	4		T97	7		T99	7
all_values[2]	272	1		T96	4		T97	7		T99	7
all_values[3]	272	1		T96	4		T97	7		T99	7
all_values[4]	272	1		T96	4		T97	7		T99	7
all_values[5]	272	1		T96	4		T97	7		T99	7
all_values[6]	272	1		T96	4		T97	7		T99	7
all_values[7]	272	1		T96	4		T97	7		T99	7
all_values[8]	272	1		T96	4		T97	7		T99	7
all_values[9]	272	1		T96	4		T97	7		T99	7
all_values[10]	272	1		T96	4		T97	7		T99	7
all_values[11]	272	1		T96	4		T97	7		T99	7
all_values[12]	272	1		T96	4		T97	7		T99	7
all_values[13]	272	1		T96	4		T97	7		T99	7
all_values[14]	272	1		T96	4		T97	7		T99	7
all_values[15]	272	1		T96	4		T97	7		T99	7
all_values[16]	272	1		T96	4		T97	7		T99	7
all_values[17]	272	1		T96	4		T97	7		T99	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2687	1		T96	45		T97	76		T99	61
auto[1]	2209	1		T96	27		T97	50		T99	65

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	934	1		T96	9		T97	14		T99	22
auto[1]	3962	1		T96	63		T97	112		T99	104

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2891	1		T96	38		T97	70		T99	74
auto[1]	2005	1		T96	34		T97	56		T99	52

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	29	1		T214	1		T213	2		T281	3
all_values[0]	auto[0]	auto[0]	auto[1]	61	1		T97	2		T99	1		T214	1
all_values[0]	auto[0]	auto[1]	auto[0]	14	1		T284	1		T285	1		T291	1
all_values[0]	auto[0]	auto[1]	auto[1]	53	1		T96	2		T97	2		T99	2
all_values[0]	auto[1]	auto[0]	auto[1]	64	1		T96	1		T99	1		T214	2
all_values[0]	auto[1]	auto[1]	auto[1]	51	1		T96	1		T97	3		T99	3
all_values[1]	auto[0]	auto[0]	auto[0]	30	1		T96	1		T99	1		T213	1
all_values[1]	auto[0]	auto[0]	auto[1]	48	1		T96	1		T97	2		T99	2
all_values[1]	auto[0]	auto[1]	auto[0]	13	1		T288	1		T292	1		T293	1
all_values[1]	auto[0]	auto[1]	auto[1]	56	1		T96	1		T97	1		T99	1
all_values[1]	auto[1]	auto[0]	auto[1]	66	1		T97	2		T214	1		T215	1
all_values[1]	auto[1]	auto[1]	auto[1]	59	1		T96	1		T97	2		T99	3
all_values[2]	auto[0]	auto[0]	auto[0]	27	1		T96	1		T99	2		T213	1
all_values[2]	auto[0]	auto[0]	auto[1]	66	1		T96	1		T97	2		T99	1
all_values[2]	auto[0]	auto[1]	auto[0]	19	1		T97	1		T99	2		T282	1
all_values[2]	auto[0]	auto[1]	auto[1]	49	1		T97	1		T213	3		T281	1
all_values[2]	auto[1]	auto[0]	auto[1]	73	1		T97	2		T99	2		T214	1
all_values[2]	auto[1]	auto[1]	auto[1]	38	1		T96	2		T97	1		T213	2
all_values[3]	auto[0]	auto[0]	auto[0]	34	1		T97	1		T214	3		T215	1
all_values[3]	auto[0]	auto[0]	auto[1]	50	1		T96	1		T99	1		T213	1
all_values[3]	auto[0]	auto[1]	auto[0]	29	1		T214	1		T215	1		T281	1
all_values[3]	auto[0]	auto[1]	auto[1]	64	1		T96	1		T97	1		T99	3
all_values[3]	auto[1]	auto[0]	auto[1]	55	1		T96	2		T97	3		T99	1
all_values[3]	auto[1]	auto[1]	auto[1]	40	1		T97	2		T99	2		T215	1
all_values[4]	auto[0]	auto[0]	auto[0]	32	1		T99	4		T214	1		T215	3
all_values[4]	auto[0]	auto[0]	auto[1]	45	1		T96	1		T97	1		T214	1
all_values[4]	auto[0]	auto[1]	auto[0]	33	1		T99	1		T215	1		T285	4
all_values[4]	auto[0]	auto[1]	auto[1]	62	1		T97	2		T99	1		T214	1
all_values[4]	auto[1]	auto[0]	auto[1]	48	1		T96	3		T97	2		T214	1
all_values[4]	auto[1]	auto[1]	auto[1]	52	1		T97	2		T99	1		T213	1
all_values[5]	auto[0]	auto[0]	auto[0]	31	1		T214	3		T215	1		T213	4
all_values[5]	auto[0]	auto[0]	auto[1]	51	1		T97	2		T99	3		T215	2
all_values[5]	auto[0]	auto[1]	auto[0]	21	1		T214	1		T213	1		T281	1
all_values[5]	auto[0]	auto[1]	auto[1]	58	1		T96	3		T99	1		T213	1
all_values[5]	auto[1]	auto[0]	auto[1]	61	1		T96	1		T97	3		T99	3
all_values[5]	auto[1]	auto[1]	auto[1]	50	1		T97	2		T215	1		T213	1
all_values[6]	auto[0]	auto[0]	auto[0]	26	1		T97	1		T214	2		T283	1
all_values[6]	auto[0]	auto[0]	auto[1]	53	1		T96	1		T215	2		T213	1
all_values[6]	auto[0]	auto[1]	auto[0]	26	1		T99	3		T214	2		T284	2
all_values[6]	auto[0]	auto[1]	auto[1]	57	1		T96	1		T97	2		T99	1
all_values[6]	auto[1]	auto[0]	auto[1]	69	1		T96	1		T97	2		T99	1
all_values[6]	auto[1]	auto[1]	auto[1]	41	1		T96	1		T97	2		T99	2
all_values[7]	auto[0]	auto[0]	auto[0]	35	1		T96	3		T99	2		T214	1
all_values[7]	auto[0]	auto[0]	auto[1]	64	1		T97	4		T99	2		T215	1
all_values[7]	auto[0]	auto[1]	auto[0]	28	1		T96	1		T282	1		T284	2
all_values[7]	auto[0]	auto[1]	auto[1]	53	1		T97	1		T99	1		T214	2
all_values[7]	auto[1]	auto[0]	auto[1]	51	1		T97	2		T99	2		T214	1
all_values[7]	auto[1]	auto[1]	auto[1]	41	1		T213	1		T283	3		T284	3
all_values[8]	auto[0]	auto[0]	auto[0]	24	1		T214	3		T215	1		T213	2
all_values[8]	auto[0]	auto[0]	auto[1]	59	1		T96	1		T97	2		T99	2
all_values[8]	auto[0]	auto[1]	auto[0]	19	1		T214	1		T282	2		T284	3
all_values[8]	auto[0]	auto[1]	auto[1]	48	1		T96	1		T97	2		T99	3
all_values[8]	auto[1]	auto[0]	auto[1]	69	1		T96	1		T97	2		T99	1
all_values[8]	auto[1]	auto[1]	auto[1]	53	1		T96	1		T97	1		T99	1
all_values[9]	auto[0]	auto[0]	auto[0]	24	1		T99	1		T282	1		T286	1
all_values[9]	auto[0]	auto[0]	auto[1]	62	1		T96	2		T97	3		T99	1
all_values[9]	auto[0]	auto[1]	auto[0]	20	1		T282	1		T284	1		T285	3
all_values[9]	auto[0]	auto[1]	auto[1]	60	1		T97	2		T99	2		T214	1
all_values[9]	auto[1]	auto[0]	auto[1]	51	1		T96	2		T97	1		T214	2
all_values[9]	auto[1]	auto[1]	auto[1]	55	1		T97	1		T99	3		T215	1
all_values[10]	auto[0]	auto[0]	auto[0]	32	1		T96	1		T97	1		T213	1
all_values[10]	auto[0]	auto[0]	auto[1]	64	1		T97	3		T99	2		T215	2
all_values[10]	auto[0]	auto[1]	auto[0]	18	1		T283	3		T286	2		T294	1
all_values[10]	auto[0]	auto[1]	auto[1]	46	1		T96	1		T214	1		T213	2
all_values[10]	auto[1]	auto[0]	auto[1]	65	1		T97	3		T99	1		T214	2
all_values[10]	auto[1]	auto[1]	auto[1]	47	1		T96	2		T99	4		T214	1
all_values[11]	auto[0]	auto[0]	auto[0]	14	1		T96	1		T213	1		T290	1
all_values[11]	auto[0]	auto[0]	auto[1]	68	1		T96	1		T97	3		T99	1
all_values[11]	auto[0]	auto[1]	auto[0]	13	1		T284	1		T290	1		T286	1
all_values[11]	auto[0]	auto[1]	auto[1]	44	1		T96	1		T97	1		T99	1
all_values[11]	auto[1]	auto[0]	auto[1]	61	1		T96	1		T97	3		T99	3
all_values[11]	auto[1]	auto[1]	auto[1]	72	1		T99	2		T214	1		T215	1
all_values[12]	auto[0]	auto[0]	auto[0]	30	1		T215	2		T282	1		T287	2
all_values[12]	auto[0]	auto[0]	auto[1]	57	1		T96	1		T97	2		T99	3
all_values[12]	auto[0]	auto[1]	auto[0]	25	1		T281	2		T287	2		T295	1
all_values[12]	auto[0]	auto[1]	auto[1]	58	1		T97	2		T99	2		T213	3
all_values[12]	auto[1]	auto[0]	auto[1]	66	1		T96	3		T97	1		T99	2
all_values[12]	auto[1]	auto[1]	auto[1]	36	1		T97	2		T214	1		T213	1
all_values[13]	auto[0]	auto[0]	auto[0]	34	1		T97	1		T281	2		T283	1
all_values[13]	auto[0]	auto[0]	auto[1]	50	1		T96	1		T97	1		T99	1
all_values[13]	auto[0]	auto[1]	auto[0]	20	1		T289	2		T296	4		T294	1
all_values[13]	auto[0]	auto[1]	auto[1]	53	1		T97	1		T99	3		T215	1
all_values[13]	auto[1]	auto[0]	auto[1]	73	1		T96	3		T97	3		T214	1
all_values[13]	auto[1]	auto[1]	auto[1]	42	1		T97	1		T99	3		T215	2
all_values[14]	auto[0]	auto[0]	auto[0]	38	1		T281	4		T282	2		T290	4
all_values[14]	auto[0]	auto[0]	auto[1]	56	1		T96	2		T99	2		T213	2
all_values[14]	auto[0]	auto[1]	auto[0]	26	1		T97	1		T284	1		T285	2
all_values[14]	auto[0]	auto[1]	auto[1]	45	1		T97	4		T99	2		T214	1
all_values[14]	auto[1]	auto[0]	auto[1]	61	1		T96	2		T97	1		T99	1
all_values[14]	auto[1]	auto[1]	auto[1]	46	1		T97	1		T99	2		T214	1
all_values[15]	auto[0]	auto[0]	auto[0]	41	1		T97	5		T214	2		T283	1
all_values[15]	auto[0]	auto[0]	auto[1]	46	1		T96	1		T99	2		T213	1
all_values[15]	auto[0]	auto[1]	auto[0]	30	1		T97	2		T214	2		T284	1
all_values[15]	auto[0]	auto[1]	auto[1]	49	1		T96	1		T99	1		T215	1
all_values[15]	auto[1]	auto[0]	auto[1]	66	1		T96	1		T99	2		T215	2
all_values[15]	auto[1]	auto[1]	auto[1]	40	1		T96	1		T99	2		T215	1
all_values[16]	auto[0]	auto[0]	auto[0]	37	1		T99	4		T214	1		T215	1
all_values[16]	auto[0]	auto[0]	auto[1]	55	1		T97	4		T214	1		T213	2
all_values[16]	auto[0]	auto[1]	auto[0]	18	1		T215	1		T282	2		T289	1
all_values[16]	auto[0]	auto[1]	auto[1]	38	1		T96	1		T99	1		T215	1
all_values[16]	auto[1]	auto[0]	auto[1]	70	1		T96	1		T97	3		T214	1
all_values[16]	auto[1]	auto[1]	auto[1]	54	1		T96	2		T99	2		T214	1
all_values[17]	auto[0]	auto[0]	auto[0]	26	1		T96	1		T99	1		T214	1
all_values[17]	auto[0]	auto[0]	auto[1]	59	1		T96	1		T97	2		T214	1
all_values[17]	auto[0]	auto[1]	auto[0]	18	1		T97	1		T99	1		T215	1
all_values[17]	auto[0]	auto[1]	auto[1]	50	1		T96	1		T97	1		T99	3
all_values[17]	auto[1]	auto[0]	auto[1]	60	1		T97	1		T99	2		T213	1
all_values[17]	auto[1]	auto[1]	auto[1]	59	1		T96	1		T97	2		T214	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal