Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	39130	1		T1	5		T2	2		T3	2
all_values[1]	39130	1		T1	5		T2	2		T3	2
all_values[2]	39130	1		T1	5		T2	2		T3	2
all_values[3]	39130	1		T1	5		T2	2		T3	2
all_values[4]	39130	1		T1	5		T2	2		T3	2
all_values[5]	39130	1		T1	5		T2	2		T3	2
all_values[6]	39130	1		T1	5		T2	2		T3	2
all_values[7]	39130	1		T1	5		T2	2		T3	2
all_values[8]	39130	1		T1	5		T2	2		T3	2
all_values[9]	39130	1		T1	5		T2	2		T3	2
all_values[10]	39130	1		T1	5		T2	2		T3	2
all_values[11]	39130	1		T1	5		T2	2		T3	2
all_values[12]	39130	1		T1	5		T2	2		T3	2
all_values[13]	39130	1		T1	5		T2	2		T3	2
all_values[14]	39130	1		T1	5		T2	2		T3	2
all_values[15]	39130	1		T1	5		T2	2		T3	2
all_values[16]	39130	1		T1	5		T2	2		T3	2
all_values[17]	39130	1		T1	5		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	698119	1		T1	90		T2	36		T3	36
auto[1]	6221	1		T25	3		T30	3		T33	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	699522	1		T1	90		T2	36		T3	36
auto[1]	4818	1		T95	72		T96	135		T97	73

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	38134	1		T1	5		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	103	1		T95	3		T96	5		T97	1
all_values[0]	auto[1]	auto[0]	722	1		T25	3		T30	3		T68	4
all_values[0]	auto[1]	auto[1]	171	1		T95	1		T96	2		T97	4
all_values[1]	auto[0]	auto[0]	36432	1		T1	5		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	144	1		T96	4		T202	1		T204	1
all_values[1]	auto[1]	auto[0]	2430	1		T33	3		T69	38		T4	4
all_values[1]	auto[1]	auto[1]	124	1		T95	3		T96	3		T97	4
all_values[2]	auto[0]	auto[0]	38730	1		T1	5		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	126	1		T95	4		T96	7		T97	2
all_values[2]	auto[1]	auto[0]	127	1		T39	2		T40	2		T41	2
all_values[2]	auto[1]	auto[1]	147	1		T95	1		T97	3		T202	6
all_values[3]	auto[0]	auto[0]	38831	1		T1	5		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	138	1		T96	5		T202	6		T204	5
all_values[3]	auto[1]	auto[0]	32	1		T95	4		T262	1		T261	1
all_values[3]	auto[1]	auto[1]	129	1		T96	3		T202	2		T203	4
all_values[4]	auto[0]	auto[0]	38843	1		T1	5		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	133	1		T96	4		T202	3		T204	5
all_values[4]	auto[1]	auto[0]	22	1		T203	1		T261	1		T263	1
all_values[4]	auto[1]	auto[1]	132	1		T95	4		T96	4		T97	4
all_values[5]	auto[0]	auto[0]	38838	1		T1	5		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	139	1		T95	3		T96	5		T97	4
all_values[5]	auto[1]	auto[0]	25	1		T203	1		T260	2		T263	1
all_values[5]	auto[1]	auto[1]	128	1		T95	2		T96	3		T97	1
all_values[6]	auto[0]	auto[0]	38834	1		T1	5		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	134	1		T95	4		T96	3		T97	3
all_values[6]	auto[1]	auto[0]	23	1		T97	1		T264	1		T265	1
all_values[6]	auto[1]	auto[1]	139	1		T95	1		T96	5		T202	3
all_values[7]	auto[0]	auto[0]	38832	1		T1	5		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	131	1		T95	3		T96	2		T97	1
all_values[7]	auto[1]	auto[0]	25	1		T95	1		T202	1		T265	3
all_values[7]	auto[1]	auto[1]	142	1		T95	1		T96	6		T97	4
all_values[8]	auto[0]	auto[0]	38838	1		T1	5		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	147	1		T95	4		T96	8		T97	5
all_values[8]	auto[1]	auto[0]	28	1		T266	1		T203	1		T264	2
all_values[8]	auto[1]	auto[1]	117	1		T95	1		T202	3		T204	1
all_values[9]	auto[0]	auto[0]	38828	1		T1	5		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	131	1		T95	4		T96	2		T97	3
all_values[9]	auto[1]	auto[0]	31	1		T97	1		T260	1		T261	4
all_values[9]	auto[1]	auto[1]	140	1		T95	1		T96	6		T202	6
all_values[10]	auto[0]	auto[0]	38829	1		T1	5		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	124	1		T96	1		T97	3		T202	7
all_values[10]	auto[1]	auto[0]	30	1		T95	2		T96	3		T264	1
all_values[10]	auto[1]	auto[1]	147	1		T96	3		T97	2		T202	1
all_values[11]	auto[0]	auto[0]	38744	1		T1	5		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	129	1		T95	1		T96	4		T97	1
all_values[11]	auto[1]	auto[0]	124	1		T50	2		T51	2		T52	2
all_values[11]	auto[1]	auto[1]	133	1		T95	4		T96	3		T97	4
all_values[12]	auto[0]	auto[0]	38834	1		T1	5		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	136	1		T95	1		T96	1		T97	3
all_values[12]	auto[1]	auto[0]	29	1		T202	1		T266	1		T262	1
all_values[12]	auto[1]	auto[1]	131	1		T95	4		T96	7		T97	2
all_values[13]	auto[0]	auto[0]	38851	1		T1	5		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	131	1		T95	3		T96	6		T97	4
all_values[13]	auto[1]	auto[0]	26	1		T97	1		T202	2		T264	1
all_values[13]	auto[1]	auto[1]	122	1		T95	2		T96	2		T204	1
all_values[14]	auto[0]	auto[0]	38839	1		T1	5		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	128	1		T95	4		T96	6		T202	5
all_values[14]	auto[1]	auto[0]	34	1		T95	1		T96	1		T97	1
all_values[14]	auto[1]	auto[1]	129	1		T96	1		T97	4		T203	2
all_values[15]	auto[0]	auto[0]	38835	1		T1	5		T2	2		T3	2
all_values[15]	auto[0]	auto[1]	109	1		T95	1		T96	3		T97	1
all_values[15]	auto[1]	auto[0]	19	1		T265	3		T267	1		T268	1
all_values[15]	auto[1]	auto[1]	167	1		T95	4		T96	5		T97	3
all_values[16]	auto[0]	auto[0]	38837	1		T1	5		T2	2		T3	2
all_values[16]	auto[0]	auto[1]	145	1		T95	1		T96	6		T97	3
all_values[16]	auto[1]	auto[0]	19	1		T262	1		T260	1		T261	1
all_values[16]	auto[1]	auto[1]	129	1		T95	4		T96	2		T202	2
all_values[17]	auto[0]	auto[0]	38840	1		T1	5		T2	2		T3	2
all_values[17]	auto[0]	auto[1]	142	1		T96	6		T97	4		T202	4
all_values[17]	auto[1]	auto[0]	27	1		T264	1		T265	2		T263	2
all_values[17]	auto[1]	auto[1]	121	1		T95	3		T96	2		T202	4