Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	39130	1		T1	5		T2	2		T3	2
all_pins[1]	39130	1		T1	5		T2	2		T3	2
all_pins[2]	39130	1		T1	5		T2	2		T3	2
all_pins[3]	39130	1		T1	5		T2	2		T3	2
all_pins[4]	39130	1		T1	5		T2	2		T3	2
all_pins[5]	39130	1		T1	5		T2	2		T3	2
all_pins[6]	39130	1		T1	5		T2	2		T3	2
all_pins[7]	39130	1		T1	5		T2	2		T3	2
all_pins[8]	39130	1		T1	5		T2	2		T3	2
all_pins[9]	39130	1		T1	5		T2	2		T3	2
all_pins[10]	39130	1		T1	5		T2	2		T3	2
all_pins[11]	39130	1		T1	5		T2	2		T3	2
all_pins[12]	39130	1		T1	5		T2	2		T3	2
all_pins[13]	39130	1		T1	5		T2	2		T3	2
all_pins[14]	39130	1		T1	5		T2	2		T3	2
all_pins[15]	39130	1		T1	5		T2	2		T3	2
all_pins[16]	39130	1		T1	5		T2	2		T3	2
all_pins[17]	39130	1		T1	5		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	701778	1		T1	90		T2	36		T3	36
values[0x1]	2562	1		T33	1		T68	1		T69	24
transitions[0x0=>0x1]	2295	1		T33	1		T68	1		T69	24
transitions[0x1=>0x0]	2304	1		T33	1		T68	1		T69	24

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	38956	1		T1	5		T2	2		T3	2
all_pins[0]	values[0x1]	174	1		T68	1		T219	1		T269	1
all_pins[0]	transitions[0x0=>0x1]	160	1		T68	1		T219	1		T269	1
all_pins[0]	transitions[0x1=>0x0]	1238	1		T33	1		T69	24		T4	1
all_pins[1]	values[0x0]	37878	1		T1	5		T2	2		T3	2
all_pins[1]	values[0x1]	1252	1		T33	1		T69	24		T4	1
all_pins[1]	transitions[0x0=>0x1]	1242	1		T33	1		T69	24		T4	1
all_pins[1]	transitions[0x1=>0x0]	123	1		T39	1		T40	1		T41	1
all_pins[2]	values[0x0]	38997	1		T1	5		T2	2		T3	2
all_pins[2]	values[0x1]	133	1		T39	1		T40	1		T41	1
all_pins[2]	transitions[0x0=>0x1]	114	1		T39	1		T40	1		T41	1
all_pins[2]	transitions[0x1=>0x0]	46	1		T96	2		T202	1		T203	1
all_pins[3]	values[0x0]	39065	1		T1	5		T2	2		T3	2
all_pins[3]	values[0x1]	65	1		T96	2		T202	1		T203	1
all_pins[3]	transitions[0x0=>0x1]	50	1		T96	2		T203	1		T264	2
all_pins[3]	transitions[0x1=>0x0]	54	1		T95	3		T96	1		T97	3
all_pins[4]	values[0x0]	39061	1		T1	5		T2	2		T3	2
all_pins[4]	values[0x1]	69	1		T95	3		T96	1		T97	3
all_pins[4]	transitions[0x0=>0x1]	49	1		T95	2		T96	1		T97	2
all_pins[4]	transitions[0x1=>0x0]	41	1		T96	1		T202	2		T262	1
all_pins[5]	values[0x0]	39069	1		T1	5		T2	2		T3	2
all_pins[5]	values[0x1]	61	1		T95	1		T96	1		T97	1
all_pins[5]	transitions[0x0=>0x1]	40	1		T96	1		T97	1		T202	3
all_pins[5]	transitions[0x1=>0x0]	55	1		T96	4		T266	3		T203	3
all_pins[6]	values[0x0]	39054	1		T1	5		T2	2		T3	2
all_pins[6]	values[0x1]	76	1		T95	1		T96	4		T266	3
all_pins[6]	transitions[0x0=>0x1]	58	1		T96	2		T266	1		T203	3
all_pins[6]	transitions[0x1=>0x0]	42	1		T97	1		T202	1		T204	1
all_pins[7]	values[0x0]	39070	1		T1	5		T2	2		T3	2
all_pins[7]	values[0x1]	60	1		T95	1		T96	2		T97	1
all_pins[7]	transitions[0x0=>0x1]	50	1		T95	1		T96	2		T97	1
all_pins[7]	transitions[0x1=>0x0]	31	1		T95	1		T262	2		T260	1
all_pins[8]	values[0x0]	39089	1		T1	5		T2	2		T3	2
all_pins[8]	values[0x1]	41	1		T95	1		T204	1		T266	1
all_pins[8]	transitions[0x0=>0x1]	31	1		T95	1		T204	1		T266	1
all_pins[8]	transitions[0x1=>0x0]	54	1		T96	4		T202	2		T204	1
all_pins[9]	values[0x0]	39066	1		T1	5		T2	2		T3	2
all_pins[9]	values[0x1]	64	1		T96	4		T202	2		T204	1
all_pins[9]	transitions[0x0=>0x1]	47	1		T96	2		T202	2		T203	1
all_pins[9]	transitions[0x1=>0x0]	54	1		T97	2		T202	1		T204	2
all_pins[10]	values[0x0]	39059	1		T1	5		T2	2		T3	2
all_pins[10]	values[0x1]	71	1		T96	2		T97	2		T202	1
all_pins[10]	transitions[0x0=>0x1]	61	1		T96	2		T97	1		T202	1
all_pins[10]	transitions[0x1=>0x0]	108	1		T50	1		T51	1		T52	1
all_pins[11]	values[0x0]	39012	1		T1	5		T2	2		T3	2
all_pins[11]	values[0x1]	118	1		T50	1		T51	1		T52	1
all_pins[11]	transitions[0x0=>0x1]	108	1		T50	1		T51	1		T52	1
all_pins[11]	transitions[0x1=>0x0]	43	1		T96	2		T202	1		T203	2
all_pins[12]	values[0x0]	39077	1		T1	5		T2	2		T3	2
all_pins[12]	values[0x1]	53	1		T96	3		T202	1		T203	2
all_pins[12]	transitions[0x0=>0x1]	41	1		T96	3		T202	1		T261	4
all_pins[12]	transitions[0x1=>0x0]	47	1		T95	1		T96	1		T204	1
all_pins[13]	values[0x0]	39071	1		T1	5		T2	2		T3	2
all_pins[13]	values[0x1]	59	1		T95	1		T96	1		T204	1
all_pins[13]	transitions[0x0=>0x1]	47	1		T95	1		T96	1		T204	1
all_pins[13]	transitions[0x1=>0x0]	61	1		T96	1		T97	3		T203	2
all_pins[14]	values[0x0]	39057	1		T1	5		T2	2		T3	2
all_pins[14]	values[0x1]	73	1		T96	1		T97	3		T203	2
all_pins[14]	transitions[0x0=>0x1]	51	1		T96	1		T97	3		T203	2
all_pins[14]	transitions[0x1=>0x0]	56	1		T95	2		T96	2		T266	2
all_pins[15]	values[0x0]	39052	1		T1	5		T2	2		T3	2
all_pins[15]	values[0x1]	78	1		T95	2		T96	2		T266	2
all_pins[15]	transitions[0x0=>0x1]	62	1		T95	2		T96	1		T266	2
all_pins[15]	transitions[0x1=>0x0]	51	1		T96	1		T202	2		T203	1
all_pins[16]	values[0x0]	39063	1		T1	5		T2	2		T3	2
all_pins[16]	values[0x1]	67	1		T96	2		T202	2		T203	1
all_pins[16]	transitions[0x0=>0x1]	58	1		T96	2		T202	1		T203	1
all_pins[16]	transitions[0x1=>0x0]	39	1		T95	1		T96	1		T202	1
all_pins[17]	values[0x0]	39082	1		T1	5		T2	2		T3	2
all_pins[17]	values[0x1]	48	1		T95	1		T96	1		T202	2
all_pins[17]	transitions[0x0=>0x1]	26	1		T96	1		T202	1		T204	1
all_pins[17]	transitions[0x1=>0x0]	161	1		T68	1		T219	1		T269	1