Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1		T95	4		T96	7		T97	4
all_values[1]	272	1		T95	4		T96	7		T97	4
all_values[2]	272	1		T95	4		T96	7		T97	4
all_values[3]	272	1		T95	4		T96	7		T97	4
all_values[4]	272	1		T95	4		T96	7		T97	4
all_values[5]	272	1		T95	4		T96	7		T97	4
all_values[6]	272	1		T95	4		T96	7		T97	4
all_values[7]	272	1		T95	4		T96	7		T97	4
all_values[8]	272	1		T95	4		T96	7		T97	4
all_values[9]	272	1		T95	4		T96	7		T97	4
all_values[10]	272	1		T95	4		T96	7		T97	4
all_values[11]	272	1		T95	4		T96	7		T97	4
all_values[12]	272	1		T95	4		T96	7		T97	4
all_values[13]	272	1		T95	4		T96	7		T97	4
all_values[14]	272	1		T95	4		T96	7		T97	4
all_values[15]	272	1		T95	4		T96	7		T97	4
all_values[16]	272	1		T95	4		T96	7		T97	4
all_values[17]	272	1		T95	4		T96	7		T97	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2609	1		T95	35		T96	75		T97	48
auto[1]	2287	1		T95	37		T96	51		T97	24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	915	1		T95	16		T96	9		T97	16
auto[1]	3981	1		T95	56		T96	117		T97	56

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2875	1		T95	44		T96	76		T97	45
auto[1]	2021	1		T95	28		T96	50		T97	27

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	28	1		T95	1		T96	1		T202	1
all_values[0]	auto[0]	auto[0]	auto[1]	37	1		T95	1		T96	4		T202	2
all_values[0]	auto[0]	auto[1]	auto[0]	17	1		T202	1		T265	1		T267	2
all_values[0]	auto[0]	auto[1]	auto[1]	69	1		T95	1		T96	1		T97	2
all_values[0]	auto[1]	auto[0]	auto[1]	56	1		T95	1		T97	1		T203	1
all_values[0]	auto[1]	auto[1]	auto[1]	65	1		T96	1		T97	1		T202	1
all_values[1]	auto[0]	auto[0]	auto[0]	32	1		T95	2		T96	1		T97	1
all_values[1]	auto[0]	auto[0]	auto[1]	51	1		T96	3		T262	1		T260	1
all_values[1]	auto[0]	auto[1]	auto[0]	19	1		T204	1		T264	1		T265	1
all_values[1]	auto[0]	auto[1]	auto[1]	51	1		T95	1		T96	1		T97	2
all_values[1]	auto[1]	auto[0]	auto[1]	70	1		T97	1		T202	1		T204	1
all_values[1]	auto[1]	auto[1]	auto[1]	49	1		T95	1		T96	2		T202	1
all_values[2]	auto[0]	auto[0]	auto[0]	24	1		T96	1		T266	1		T264	2
all_values[2]	auto[0]	auto[0]	auto[1]	51	1		T95	1		T96	4		T97	1
all_values[2]	auto[0]	auto[1]	auto[0]	22	1		T264	2		T265	1		T270	1
all_values[2]	auto[0]	auto[1]	auto[1]	68	1		T95	1		T97	1		T202	3
all_values[2]	auto[1]	auto[0]	auto[1]	55	1		T95	2		T96	2		T97	1
all_values[2]	auto[1]	auto[1]	auto[1]	52	1		T97	1		T202	2		T262	1
all_values[3]	auto[0]	auto[0]	auto[0]	30	1		T95	2		T97	4		T260	1
all_values[3]	auto[0]	auto[0]	auto[1]	64	1		T96	3		T202	2		T204	3
all_values[3]	auto[0]	auto[1]	auto[0]	21	1		T95	2		T262	1		T264	1
all_values[3]	auto[0]	auto[1]	auto[1]	57	1		T96	3		T202	1		T203	2
all_values[3]	auto[1]	auto[0]	auto[1]	47	1		T96	1		T202	2		T204	1
all_values[3]	auto[1]	auto[1]	auto[1]	53	1		T202	2		T203	1		T262	1
all_values[4]	auto[0]	auto[0]	auto[0]	36	1		T95	1		T97	1		T266	4
all_values[4]	auto[0]	auto[0]	auto[1]	52	1		T96	2		T202	1		T204	2
all_values[4]	auto[0]	auto[1]	auto[0]	17	1		T261	1		T270	1		T271	2
all_values[4]	auto[0]	auto[1]	auto[1]	52	1		T95	1		T96	2		T97	1
all_values[4]	auto[1]	auto[0]	auto[1]	71	1		T95	1		T96	1		T97	1
all_values[4]	auto[1]	auto[1]	auto[1]	44	1		T95	1		T96	2		T97	1
all_values[5]	auto[0]	auto[0]	auto[0]	33	1		T202	1		T203	4		T261	1
all_values[5]	auto[0]	auto[0]	auto[1]	56	1		T95	1		T96	3		T97	1
all_values[5]	auto[0]	auto[1]	auto[0]	18	1		T260	2		T263	1		T270	2
all_values[5]	auto[0]	auto[1]	auto[1]	51	1		T95	1		T96	1		T202	3
all_values[5]	auto[1]	auto[0]	auto[1]	65	1		T96	2		T97	3		T202	1
all_values[5]	auto[1]	auto[1]	auto[1]	49	1		T95	2		T96	1		T202	2
all_values[6]	auto[0]	auto[0]	auto[0]	28	1		T97	1		T261	4		T264	1
all_values[6]	auto[0]	auto[0]	auto[1]	62	1		T95	1		T96	2		T97	1
all_values[6]	auto[0]	auto[1]	auto[0]	16	1		T97	1		T264	1		T265	1
all_values[6]	auto[0]	auto[1]	auto[1]	55	1		T96	1		T202	3		T204	1
all_values[6]	auto[1]	auto[0]	auto[1]	55	1		T95	2		T96	2		T97	1
all_values[6]	auto[1]	auto[1]	auto[1]	56	1		T95	1		T96	2		T204	2
all_values[7]	auto[0]	auto[0]	auto[0]	28	1		T202	1		T203	1		T262	1
all_values[7]	auto[0]	auto[0]	auto[1]	44	1		T95	1		T96	1		T204	1
all_values[7]	auto[0]	auto[1]	auto[0]	19	1		T95	1		T202	1		T265	3
all_values[7]	auto[0]	auto[1]	auto[1]	60	1		T95	1		T96	2		T97	2
all_values[7]	auto[1]	auto[0]	auto[1]	67	1		T96	2		T97	1		T202	2
all_values[7]	auto[1]	auto[1]	auto[1]	54	1		T95	1		T96	2		T97	1
all_values[8]	auto[0]	auto[0]	auto[0]	38	1		T203	1		T261	1		T267	1
all_values[8]	auto[0]	auto[0]	auto[1]	59	1		T95	1		T96	4		T97	2
all_values[8]	auto[0]	auto[1]	auto[0]	16	1		T266	1		T264	3		T263	1
all_values[8]	auto[0]	auto[1]	auto[1]	56	1		T202	4		T266	1		T203	2
all_values[8]	auto[1]	auto[0]	auto[1]	58	1		T95	1		T96	3		T97	2
all_values[8]	auto[1]	auto[1]	auto[1]	45	1		T95	2		T204	2		T266	1
all_values[9]	auto[0]	auto[0]	auto[0]	22	1		T97	2		T204	1		T260	2
all_values[9]	auto[0]	auto[0]	auto[1]	52	1		T95	2		T97	1		T266	1
all_values[9]	auto[0]	auto[1]	auto[0]	25	1		T260	2		T261	3		T267	1
all_values[9]	auto[0]	auto[1]	auto[1]	54	1		T96	2		T202	2		T204	1
all_values[9]	auto[1]	auto[0]	auto[1]	70	1		T95	1		T96	4		T97	1
all_values[9]	auto[1]	auto[1]	auto[1]	49	1		T95	1		T96	1		T202	2
all_values[10]	auto[0]	auto[0]	auto[0]	24	1		T95	1		T96	2		T204	1
all_values[10]	auto[0]	auto[0]	auto[1]	52	1		T97	2		T202	4		T262	1
all_values[10]	auto[0]	auto[1]	auto[0]	24	1		T95	3		T96	2		T264	1
all_values[10]	auto[0]	auto[1]	auto[1]	55	1		T96	1		T97	1		T204	2
all_values[10]	auto[1]	auto[0]	auto[1]	53	1		T96	2		T97	1		T202	2
all_values[10]	auto[1]	auto[1]	auto[1]	64	1		T202	1		T266	1		T203	2
all_values[11]	auto[0]	auto[0]	auto[0]	38	1		T96	1		T204	2		T260	1
all_values[11]	auto[0]	auto[0]	auto[1]	55	1		T95	1		T96	2		T202	2
all_values[11]	auto[0]	auto[1]	auto[0]	18	1		T262	1		T265	1		T271	1
all_values[11]	auto[0]	auto[1]	auto[1]	54	1		T95	1		T96	2		T97	2
all_values[11]	auto[1]	auto[0]	auto[1]	57	1		T97	1		T202	3		T204	1
all_values[11]	auto[1]	auto[1]	auto[1]	50	1		T95	2		T96	2		T97	1
all_values[12]	auto[0]	auto[0]	auto[0]	30	1		T266	3		T264	1		T265	1
all_values[12]	auto[0]	auto[0]	auto[1]	57	1		T95	1		T97	2		T202	2
all_values[12]	auto[0]	auto[1]	auto[0]	20	1		T202	1		T266	1		T262	1
all_values[12]	auto[0]	auto[1]	auto[1]	60	1		T95	2		T96	4		T97	1
all_values[12]	auto[1]	auto[0]	auto[1]	61	1		T95	1		T96	1		T97	1
all_values[12]	auto[1]	auto[1]	auto[1]	44	1		T96	2		T202	1		T204	1
all_values[13]	auto[0]	auto[0]	auto[0]	43	1		T97	1		T202	4		T260	1
all_values[13]	auto[0]	auto[0]	auto[1]	52	1		T95	1		T96	2		T97	1
all_values[13]	auto[0]	auto[1]	auto[0]	22	1		T202	1		T265	1		T270	2
all_values[13]	auto[0]	auto[1]	auto[1]	49	1		T95	2		T96	2		T203	2
all_values[13]	auto[1]	auto[0]	auto[1]	56	1		T96	2		T97	1		T204	2
all_values[13]	auto[1]	auto[1]	auto[1]	50	1		T95	1		T96	1		T97	1
all_values[14]	auto[0]	auto[0]	auto[0]	36	1		T96	1		T97	1		T202	1
all_values[14]	auto[0]	auto[0]	auto[1]	46	1		T95	1		T96	2		T202	3
all_values[14]	auto[0]	auto[1]	auto[0]	24	1		T95	1		T202	2		T204	2
all_values[14]	auto[0]	auto[1]	auto[1]	51	1		T96	1		T97	1		T262	1
all_values[14]	auto[1]	auto[0]	auto[1]	57	1		T95	1		T96	2		T202	1
all_values[14]	auto[1]	auto[1]	auto[1]	58	1		T95	1		T96	1		T97	2
all_values[15]	auto[0]	auto[0]	auto[0]	28	1		T97	1		T203	2		T265	1
all_values[15]	auto[0]	auto[0]	auto[1]	43	1		T96	1		T202	1		T204	1
all_values[15]	auto[0]	auto[1]	auto[0]	17	1		T265	3		T268	2		T272	4
all_values[15]	auto[0]	auto[1]	auto[1]	70	1		T95	1		T96	4		T97	2
all_values[15]	auto[1]	auto[0]	auto[1]	59	1		T95	1		T96	1		T97	1
all_values[15]	auto[1]	auto[1]	auto[1]	55	1		T95	2		T96	1		T202	1
all_values[16]	auto[0]	auto[0]	auto[0]	33	1		T97	2		T203	1		T260	1
all_values[16]	auto[0]	auto[0]	auto[1]	61	1		T95	1		T96	3		T97	1
all_values[16]	auto[0]	auto[1]	auto[0]	14	1		T262	1		T260	1		T264	1
all_values[16]	auto[0]	auto[1]	auto[1]	52	1		T95	2		T96	1		T202	3
all_values[16]	auto[1]	auto[0]	auto[1]	64	1		T95	1		T96	2		T97	1
all_values[16]	auto[1]	auto[1]	auto[1]	48	1		T96	1		T204	2		T203	1
all_values[17]	auto[0]	auto[0]	auto[0]	34	1		T95	2		T97	1		T266	1
all_values[17]	auto[0]	auto[0]	auto[1]	58	1		T96	3		T97	2		T266	1
all_values[17]	auto[0]	auto[1]	auto[0]	21	1		T264	1		T265	2		T263	2
all_values[17]	auto[0]	auto[1]	auto[1]	44	1		T95	1		T202	1		T204	1
all_values[17]	auto[1]	auto[0]	auto[1]	71	1		T95	1		T96	2		T97	1
all_values[17]	auto[1]	auto[1]	auto[1]	44	1		T96	2		T202	2		T204	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal