Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	31795	1		T1	4		T2	4		T3	3
all_values[1]	31795	1		T1	4		T2	4		T3	3
all_values[2]	31795	1		T1	4		T2	4		T3	3
all_values[3]	31795	1		T1	4		T2	4		T3	3
all_values[4]	31795	1		T1	4		T2	4		T3	3
all_values[5]	31795	1		T1	4		T2	4		T3	3
all_values[6]	31795	1		T1	4		T2	4		T3	3
all_values[7]	31795	1		T1	4		T2	4		T3	3
all_values[8]	31795	1		T1	4		T2	4		T3	3
all_values[9]	31795	1		T1	4		T2	4		T3	3
all_values[10]	31795	1		T1	4		T2	4		T3	3
all_values[11]	31795	1		T1	4		T2	4		T3	3
all_values[12]	31795	1		T1	4		T2	4		T3	3
all_values[13]	31795	1		T1	4		T2	4		T3	3
all_values[14]	31795	1		T1	4		T2	4		T3	3
all_values[15]	31795	1		T1	4		T2	4		T3	3
all_values[16]	31795	1		T1	4		T2	4		T3	3
all_values[17]	31795	1		T1	4		T2	4		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	566353	1		T1	72		T2	68		T3	51
auto[1]	5957	1		T2	4		T3	3		T29	38

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	567565	1		T1	72		T2	72		T3	54
auto[1]	4745	1		T97	69		T98	76		T99	69

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	30800	1		T1	4		T29	38		T30	2
all_values[0]	auto[0]	auto[1]	137	1		T97	4		T98	3		T99	5
all_values[0]	auto[1]	auto[0]	722	1		T2	4		T3	3		T39	3
all_values[0]	auto[1]	auto[1]	136	1		T97	1		T98	1		T204	5
all_values[1]	auto[0]	auto[0]	29283	1		T1	4		T2	4		T3	3
all_values[1]	auto[0]	auto[1]	136	1		T204	1		T205	5		T269	5
all_values[1]	auto[1]	auto[0]	2256	1		T29	38		T36	4		T47	4
all_values[1]	auto[1]	auto[1]	120	1		T99	4		T204	7		T206	5
all_values[2]	auto[0]	auto[0]	31409	1		T1	4		T2	4		T3	3
all_values[2]	auto[0]	auto[1]	132	1		T97	4		T98	4		T99	3
all_values[2]	auto[1]	auto[0]	130	1		T48	2		T49	2		T51	2
all_values[2]	auto[1]	auto[1]	124	1		T98	1		T99	1		T204	1
all_values[3]	auto[0]	auto[0]	31502	1		T1	4		T2	4		T3	3
all_values[3]	auto[0]	auto[1]	141	1		T97	4		T98	4		T99	3
all_values[3]	auto[1]	auto[0]	30	1		T270	1		T271	1		T267	2
all_values[3]	auto[1]	auto[1]	122	1		T97	1		T99	2		T204	2
all_values[4]	auto[0]	auto[0]	31500	1		T1	4		T2	4		T3	3
all_values[4]	auto[0]	auto[1]	151	1		T98	4		T99	2		T206	5
all_values[4]	auto[1]	auto[0]	14	1		T205	1		T269	1		T272	1
all_values[4]	auto[1]	auto[1]	130	1		T97	5		T98	1		T99	3
all_values[5]	auto[0]	auto[0]	31495	1		T1	4		T2	4		T3	3
all_values[5]	auto[0]	auto[1]	121	1		T97	5		T98	3		T99	3
all_values[5]	auto[1]	auto[0]	31	1		T98	1		T99	2		T270	3
all_values[5]	auto[1]	auto[1]	148	1		T98	1		T204	4		T206	4
all_values[6]	auto[0]	auto[0]	31499	1		T1	4		T2	4		T3	3
all_values[6]	auto[0]	auto[1]	151	1		T97	4		T98	4		T99	3
all_values[6]	auto[1]	auto[0]	28	1		T98	1		T99	1		T269	1
all_values[6]	auto[1]	auto[1]	117	1		T97	1		T204	5		T206	5
all_values[7]	auto[0]	auto[0]	31497	1		T1	4		T2	4		T3	3
all_values[7]	auto[0]	auto[1]	134	1		T97	2		T98	3		T204	6
all_values[7]	auto[1]	auto[0]	20	1		T206	1		T205	1		T270	4
all_values[7]	auto[1]	auto[1]	144	1		T97	3		T99	5		T204	2
all_values[8]	auto[0]	auto[0]	31515	1		T1	4		T2	4		T3	3
all_values[8]	auto[0]	auto[1]	133	1		T97	1		T98	1		T99	3
all_values[8]	auto[1]	auto[0]	21	1		T97	1		T273	1		T274	1
all_values[8]	auto[1]	auto[1]	126	1		T97	3		T98	4		T99	1
all_values[9]	auto[0]	auto[0]	31506	1		T1	4		T2	4		T3	3
all_values[9]	auto[0]	auto[1]	110	1		T98	4		T204	3		T205	2
all_values[9]	auto[1]	auto[0]	29	1		T97	2		T99	2		T272	1
all_values[9]	auto[1]	auto[1]	150	1		T97	3		T98	1		T99	3
all_values[10]	auto[0]	auto[0]	31502	1		T1	4		T2	4		T3	3
all_values[10]	auto[0]	auto[1]	121	1		T204	3		T206	3		T205	5
all_values[10]	auto[1]	auto[0]	28	1		T99	3		T206	1		T270	1
all_values[10]	auto[1]	auto[1]	144	1		T97	5		T98	5		T204	5
all_values[11]	auto[0]	auto[0]	31412	1		T1	4		T2	4		T3	3
all_values[11]	auto[0]	auto[1]	129	1		T98	3		T99	4		T204	5
all_values[11]	auto[1]	auto[0]	140	1		T52	2		T60	2		T61	2
all_values[11]	auto[1]	auto[1]	114	1		T97	3		T98	2		T99	1
all_values[12]	auto[0]	auto[0]	31519	1		T1	4		T2	4		T3	3
all_values[12]	auto[0]	auto[1]	129	1		T97	3		T98	2		T204	6
all_values[12]	auto[1]	auto[0]	21	1		T99	1		T274	1		T267	3
all_values[12]	auto[1]	auto[1]	126	1		T97	1		T98	3		T99	3
all_values[13]	auto[0]	auto[0]	31496	1		T1	4		T2	4		T3	3
all_values[13]	auto[0]	auto[1]	149	1		T98	4		T99	3		T204	2
all_values[13]	auto[1]	auto[0]	24	1		T97	1		T204	1		T205	1
all_values[13]	auto[1]	auto[1]	126	1		T98	1		T99	2		T204	5
all_values[14]	auto[0]	auto[0]	31507	1		T1	4		T2	4		T3	3
all_values[14]	auto[0]	auto[1]	133	1		T97	4		T204	2		T206	3
all_values[14]	auto[1]	auto[0]	26	1		T97	1		T98	1		T99	3
all_values[14]	auto[1]	auto[1]	129	1		T98	3		T204	6		T206	2
all_values[15]	auto[0]	auto[0]	31508	1		T1	4		T2	4		T3	3
all_values[15]	auto[0]	auto[1]	131	1		T97	2		T98	1		T99	4
all_values[15]	auto[1]	auto[0]	29	1		T98	1		T206	1		T271	1
all_values[15]	auto[1]	auto[1]	127	1		T97	3		T98	3		T99	1
all_values[16]	auto[0]	auto[0]	31500	1		T1	4		T2	4		T3	3
all_values[16]	auto[0]	auto[1]	127	1		T97	3		T98	4		T99	5
all_values[16]	auto[1]	auto[0]	36	1		T97	1		T206	1		T269	1
all_values[16]	auto[1]	auto[1]	132	1		T98	1		T204	4		T205	4
all_values[17]	auto[0]	auto[0]	31496	1		T1	4		T2	4		T3	3
all_values[17]	auto[0]	auto[1]	142	1		T98	5		T204	3		T206	1
all_values[17]	auto[1]	auto[0]	34	1		T204	4		T206	1		T205	1
all_values[17]	auto[1]	auto[1]	123	1		T97	4		T99	5		T206	3