Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	31795	1		T1	4		T2	4		T3	3
all_pins[1]	31795	1		T1	4		T2	4		T3	3
all_pins[2]	31795	1		T1	4		T2	4		T3	3
all_pins[3]	31795	1		T1	4		T2	4		T3	3
all_pins[4]	31795	1		T1	4		T2	4		T3	3
all_pins[5]	31795	1		T1	4		T2	4		T3	3
all_pins[6]	31795	1		T1	4		T2	4		T3	3
all_pins[7]	31795	1		T1	4		T2	4		T3	3
all_pins[8]	31795	1		T1	4		T2	4		T3	3
all_pins[9]	31795	1		T1	4		T2	4		T3	3
all_pins[10]	31795	1		T1	4		T2	4		T3	3
all_pins[11]	31795	1		T1	4		T2	4		T3	3
all_pins[12]	31795	1		T1	4		T2	4		T3	3
all_pins[13]	31795	1		T1	4		T2	4		T3	3
all_pins[14]	31795	1		T1	4		T2	4		T3	3
all_pins[15]	31795	1		T1	4		T2	4		T3	3
all_pins[16]	31795	1		T1	4		T2	4		T3	3
all_pins[17]	31795	1		T1	4		T2	4		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	569858	1		T1	72		T2	71		T3	54
values[0x1]	2452	1		T2	1		T29	24		T48	1
transitions[0x0=>0x1]	2169	1		T2	1		T29	24		T48	1
transitions[0x1=>0x0]	2180	1		T2	1		T29	24		T48	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	31639	1		T1	4		T2	3		T3	3
all_pins[0]	values[0x1]	156	1		T2	1		T89	1		T275	1
all_pins[0]	transitions[0x0=>0x1]	140	1		T2	1		T89	1		T275	1
all_pins[0]	transitions[0x1=>0x0]	1232	1		T29	24		T36	1		T47	1
all_pins[1]	values[0x0]	30547	1		T1	4		T2	4		T3	3
all_pins[1]	values[0x1]	1248	1		T29	24		T36	1		T47	1
all_pins[1]	transitions[0x0=>0x1]	1235	1		T29	24		T36	1		T47	1
all_pins[1]	transitions[0x1=>0x0]	104	1		T48	1		T49	1		T51	1
all_pins[2]	values[0x0]	31678	1		T1	4		T2	4		T3	3
all_pins[2]	values[0x1]	117	1		T48	1		T49	1		T51	1
all_pins[2]	transitions[0x0=>0x1]	95	1		T48	1		T49	1		T51	1
all_pins[2]	transitions[0x1=>0x0]	26	1		T97	1		T204	1		T206	1
all_pins[3]	values[0x0]	31747	1		T1	4		T2	4		T3	3
all_pins[3]	values[0x1]	48	1		T97	1		T99	1		T204	2
all_pins[3]	transitions[0x0=>0x1]	35	1		T97	1		T99	1		T204	1
all_pins[3]	transitions[0x1=>0x0]	45	1		T97	1		T204	2		T269	1
all_pins[4]	values[0x0]	31737	1		T1	4		T2	4		T3	3
all_pins[4]	values[0x1]	58	1		T97	1		T204	3		T205	2
all_pins[4]	transitions[0x0=>0x1]	43	1		T97	1		T204	2		T205	2
all_pins[4]	transitions[0x1=>0x0]	51	1		T206	3		T205	1		T269	2
all_pins[5]	values[0x0]	31729	1		T1	4		T2	4		T3	3
all_pins[5]	values[0x1]	66	1		T204	1		T206	3		T205	1
all_pins[5]	transitions[0x0=>0x1]	53	1		T206	2		T205	1		T269	3
all_pins[5]	transitions[0x1=>0x0]	46	1		T97	1		T204	2		T206	1
all_pins[6]	values[0x0]	31736	1		T1	4		T2	4		T3	3
all_pins[6]	values[0x1]	59	1		T97	1		T204	3		T206	2
all_pins[6]	transitions[0x0=>0x1]	43	1		T97	1		T204	2		T206	1
all_pins[6]	transitions[0x1=>0x0]	44	1		T97	1		T99	2		T269	2
all_pins[7]	values[0x0]	31735	1		T1	4		T2	4		T3	3
all_pins[7]	values[0x1]	60	1		T97	1		T99	2		T204	1
all_pins[7]	transitions[0x0=>0x1]	46	1		T99	2		T204	1		T206	1
all_pins[7]	transitions[0x1=>0x0]	37	1		T98	1		T99	1		T206	1
all_pins[8]	values[0x0]	31744	1		T1	4		T2	4		T3	3
all_pins[8]	values[0x1]	51	1		T97	1		T98	1		T99	1
all_pins[8]	transitions[0x0=>0x1]	35	1		T97	1		T99	1		T269	1
all_pins[8]	transitions[0x1=>0x0]	52	1		T204	4		T205	2		T269	1
all_pins[9]	values[0x0]	31727	1		T1	4		T2	4		T3	3
all_pins[9]	values[0x1]	68	1		T98	1		T204	4		T206	1
all_pins[9]	transitions[0x0=>0x1]	45	1		T204	4		T206	1		T205	2
all_pins[9]	transitions[0x1=>0x0]	44	1		T97	4		T98	1		T204	2
all_pins[10]	values[0x0]	31728	1		T1	4		T2	4		T3	3
all_pins[10]	values[0x1]	67	1		T97	4		T98	2		T204	2
all_pins[10]	transitions[0x0=>0x1]	53	1		T97	4		T204	1		T269	3
all_pins[10]	transitions[0x1=>0x0]	83	1		T52	1		T60	1		T61	1
all_pins[11]	values[0x0]	31698	1		T1	4		T2	4		T3	3
all_pins[11]	values[0x1]	97	1		T52	1		T60	1		T61	1
all_pins[11]	transitions[0x0=>0x1]	89	1		T52	1		T60	1		T61	1
all_pins[11]	transitions[0x1=>0x0]	51	1		T97	1		T98	2		T99	2
all_pins[12]	values[0x0]	31736	1		T1	4		T2	4		T3	3
all_pins[12]	values[0x1]	59	1		T97	1		T98	2		T99	2
all_pins[12]	transitions[0x0=>0x1]	44	1		T97	1		T98	2		T99	2
all_pins[12]	transitions[0x1=>0x0]	47	1		T98	1		T204	2		T206	1
all_pins[13]	values[0x0]	31733	1		T1	4		T2	4		T3	3
all_pins[13]	values[0x1]	62	1		T98	1		T204	3		T206	2
all_pins[13]	transitions[0x0=>0x1]	41	1		T98	1		T204	1		T270	2
all_pins[13]	transitions[0x1=>0x0]	45	1		T98	2		T204	3		T205	1
all_pins[14]	values[0x0]	31729	1		T1	4		T2	4		T3	3
all_pins[14]	values[0x1]	66	1		T98	2		T204	5		T206	2
all_pins[14]	transitions[0x0=>0x1]	52	1		T98	2		T204	5		T206	1
all_pins[14]	transitions[0x1=>0x0]	46	1		T97	2		T204	2		T205	2
all_pins[15]	values[0x0]	31735	1		T1	4		T2	4		T3	3
all_pins[15]	values[0x1]	60	1		T97	2		T204	2		T206	1
all_pins[15]	transitions[0x0=>0x1]	41	1		T97	2		T204	2		T206	1
all_pins[15]	transitions[0x1=>0x0]	42	1		T204	1		T205	1		T269	2
all_pins[16]	values[0x0]	31734	1		T1	4		T2	4		T3	3
all_pins[16]	values[0x1]	61	1		T204	1		T205	3		T269	3
all_pins[16]	transitions[0x0=>0x1]	53	1		T204	1		T205	3		T269	3
all_pins[16]	transitions[0x1=>0x0]	41	1		T97	2		T99	2		T206	1
all_pins[17]	values[0x0]	31746	1		T1	4		T2	4		T3	3
all_pins[17]	values[0x1]	49	1		T97	2		T99	2		T206	1
all_pins[17]	transitions[0x0=>0x1]	26	1		T97	1		T99	1		T269	1
all_pins[17]	transitions[0x1=>0x0]	144	1		T2	1		T89	1		T275	1