Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	266	1		T97	4		T98	4		T99	4
all_values[1]	266	1		T97	4		T98	4		T99	4
all_values[2]	266	1		T97	4		T98	4		T99	4
all_values[3]	266	1		T97	4		T98	4		T99	4
all_values[4]	266	1		T97	4		T98	4		T99	4
all_values[5]	266	1		T97	4		T98	4		T99	4
all_values[6]	266	1		T97	4		T98	4		T99	4
all_values[7]	266	1		T97	4		T98	4		T99	4
all_values[8]	266	1		T97	4		T98	4		T99	4
all_values[9]	266	1		T97	4		T98	4		T99	4
all_values[10]	266	1		T97	4		T98	4		T99	4
all_values[11]	266	1		T97	4		T98	4		T99	4
all_values[12]	266	1		T97	4		T98	4		T99	4
all_values[13]	266	1		T97	4		T98	4		T99	4
all_values[14]	266	1		T97	4		T98	4		T99	4
all_values[15]	266	1		T97	4		T98	4		T99	4
all_values[16]	266	1		T97	4		T98	4		T99	4
all_values[17]	266	1		T97	4		T98	4		T99	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2597	1		T97	37		T98	52		T99	31
auto[1]	2191	1		T97	35		T98	20		T99	41

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	882	1		T97	19		T98	13		T99	19
auto[1]	3906	1		T97	53		T98	59		T99	53

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2841	1		T97	43		T98	39		T99	46
auto[1]	1947	1		T97	29		T98	33		T99	26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	24	1		T98	1		T269	1		T270	3
all_values[0]	auto[0]	auto[0]	auto[1]	54	1		T97	2		T98	1		T99	2
all_values[0]	auto[0]	auto[1]	auto[0]	18	1		T270	1		T276	1		T277	2
all_values[0]	auto[0]	auto[1]	auto[1]	59	1		T204	3		T206	2		T205	2
all_values[0]	auto[1]	auto[0]	auto[1]	71	1		T97	1		T98	2		T99	2
all_values[0]	auto[1]	auto[1]	auto[1]	40	1		T97	1		T204	1		T206	2
all_values[1]	auto[0]	auto[0]	auto[0]	33	1		T97	1		T98	3		T273	1
all_values[1]	auto[0]	auto[0]	auto[1]	48	1		T205	1		T269	2		T270	1
all_values[1]	auto[0]	auto[1]	auto[0]	21	1		T97	3		T98	1		T99	1
all_values[1]	auto[0]	auto[1]	auto[1]	47	1		T99	2		T204	3		T206	1
all_values[1]	auto[1]	auto[0]	auto[1]	61	1		T205	3		T269	2		T270	1
all_values[1]	auto[1]	auto[1]	auto[1]	56	1		T99	1		T204	4		T206	3
all_values[2]	auto[0]	auto[0]	auto[0]	36	1		T97	1		T204	3		T206	1
all_values[2]	auto[0]	auto[0]	auto[1]	43	1		T97	2		T98	1		T99	1
all_values[2]	auto[0]	auto[1]	auto[0]	22	1		T99	1		T206	1		T269	1
all_values[2]	auto[0]	auto[1]	auto[1]	51	1		T204	2		T269	1		T270	1
all_values[2]	auto[1]	auto[0]	auto[1]	61	1		T97	1		T98	2		T204	1
all_values[2]	auto[1]	auto[1]	auto[1]	53	1		T98	1		T99	2		T269	2
all_values[3]	auto[0]	auto[0]	auto[0]	24	1		T98	1		T271	1		T268	2
all_values[3]	auto[0]	auto[0]	auto[1]	56	1		T97	1		T98	1		T99	1
all_values[3]	auto[0]	auto[1]	auto[0]	25	1		T270	1		T267	2		T278	1
all_values[3]	auto[0]	auto[1]	auto[1]	55	1		T97	2		T99	1		T204	1
all_values[3]	auto[1]	auto[0]	auto[1]	59	1		T97	1		T98	2		T204	4
all_values[3]	auto[1]	auto[1]	auto[1]	47	1		T99	2		T204	1		T206	2
all_values[4]	auto[0]	auto[0]	auto[0]	19	1		T204	1		T205	1		T269	1
all_values[4]	auto[0]	auto[0]	auto[1]	64	1		T98	3		T99	2		T206	2
all_values[4]	auto[0]	auto[1]	auto[0]	13	1		T205	1		T269	1		T272	1
all_values[4]	auto[0]	auto[1]	auto[1]	56	1		T97	3		T99	1		T204	5
all_values[4]	auto[1]	auto[0]	auto[1]	73	1		T98	1		T99	1		T204	1
all_values[4]	auto[1]	auto[1]	auto[1]	41	1		T97	1		T205	1		T269	1
all_values[5]	auto[0]	auto[0]	auto[0]	24	1		T98	1		T273	1		T272	1
all_values[5]	auto[0]	auto[0]	auto[1]	47	1		T97	2		T98	1		T99	1
all_values[5]	auto[0]	auto[1]	auto[0]	21	1		T99	2		T270	3		T279	2
all_values[5]	auto[0]	auto[1]	auto[1]	60	1		T204	1		T206	2		T205	2
all_values[5]	auto[1]	auto[0]	auto[1]	66	1		T97	2		T98	1		T204	1
all_values[5]	auto[1]	auto[1]	auto[1]	48	1		T98	1		T99	1		T204	4
all_values[6]	auto[0]	auto[0]	auto[0]	27	1		T98	1		T99	1		T205	1
all_values[6]	auto[0]	auto[0]	auto[1]	59	1		T97	1		T98	1		T99	1
all_values[6]	auto[0]	auto[1]	auto[0]	18	1		T99	1		T269	1		T271	1
all_values[6]	auto[0]	auto[1]	auto[1]	50	1		T204	1		T206	2		T205	1
all_values[6]	auto[1]	auto[0]	auto[1]	64	1		T97	2		T98	1		T204	4
all_values[6]	auto[1]	auto[1]	auto[1]	48	1		T97	1		T98	1		T99	1
all_values[7]	auto[0]	auto[0]	auto[0]	26	1		T98	2		T205	1		T272	1
all_values[7]	auto[0]	auto[0]	auto[1]	62	1		T98	1		T204	3		T206	2
all_values[7]	auto[0]	auto[1]	auto[0]	11	1		T206	1		T270	4		T278	1
all_values[7]	auto[0]	auto[1]	auto[1]	59	1		T97	1		T99	2		T204	1
all_values[7]	auto[1]	auto[0]	auto[1]	55	1		T97	3		T98	1		T204	3
all_values[7]	auto[1]	auto[1]	auto[1]	53	1		T99	2		T206	1		T269	3
all_values[8]	auto[0]	auto[0]	auto[0]	37	1		T99	1		T205	4		T270	2
all_values[8]	auto[0]	auto[0]	auto[1]	52	1		T99	1		T204	5		T269	1
all_values[8]	auto[0]	auto[1]	auto[0]	16	1		T97	1		T273	1		T274	1
all_values[8]	auto[0]	auto[1]	auto[1]	56	1		T97	1		T98	2		T204	1
all_values[8]	auto[1]	auto[0]	auto[1]	60	1		T97	2		T98	2		T204	1
all_values[8]	auto[1]	auto[1]	auto[1]	45	1		T99	2		T206	1		T269	2
all_values[9]	auto[0]	auto[0]	auto[0]	32	1		T269	2		T273	1		T272	1
all_values[9]	auto[0]	auto[0]	auto[1]	46	1		T98	1		T204	1		T205	1
all_values[9]	auto[0]	auto[1]	auto[0]	18	1		T97	2		T99	2		T277	1
all_values[9]	auto[0]	auto[1]	auto[1]	55	1		T97	1		T99	1		T204	2
all_values[9]	auto[1]	auto[0]	auto[1]	59	1		T98	3		T204	3		T205	1
all_values[9]	auto[1]	auto[1]	auto[1]	56	1		T97	1		T99	1		T204	1
all_values[10]	auto[0]	auto[0]	auto[0]	28	1		T99	3		T206	1		T270	1
all_values[10]	auto[0]	auto[0]	auto[1]	52	1		T206	1		T205	2		T269	2
all_values[10]	auto[0]	auto[1]	auto[0]	20	1		T99	1		T206	1		T270	1
all_values[10]	auto[0]	auto[1]	auto[1]	52	1		T97	1		T98	2		T204	2
all_values[10]	auto[1]	auto[0]	auto[1]	58	1		T98	1		T204	3		T206	1
all_values[10]	auto[1]	auto[1]	auto[1]	56	1		T97	3		T98	1		T204	2
all_values[11]	auto[0]	auto[0]	auto[0]	42	1		T97	1		T204	2		T206	3
all_values[11]	auto[0]	auto[0]	auto[1]	52	1		T98	2		T99	1		T204	2
all_values[11]	auto[0]	auto[1]	auto[0]	23	1		T97	1		T206	1		T269	2
all_values[11]	auto[0]	auto[1]	auto[1]	55	1		T97	1		T98	1		T99	1
all_values[11]	auto[1]	auto[0]	auto[1]	49	1		T97	1		T98	1		T99	1
all_values[11]	auto[1]	auto[1]	auto[1]	45	1		T99	1		T204	1		T269	2
all_values[12]	auto[0]	auto[0]	auto[0]	37	1		T97	1		T99	1		T206	1
all_values[12]	auto[0]	auto[0]	auto[1]	59	1		T97	1		T98	1		T204	3
all_values[12]	auto[0]	auto[1]	auto[0]	20	1		T99	1		T274	1		T267	2
all_values[12]	auto[0]	auto[1]	auto[1]	52	1		T98	1		T99	1		T204	1
all_values[12]	auto[1]	auto[0]	auto[1]	59	1		T98	1		T204	1		T205	1
all_values[12]	auto[1]	auto[1]	auto[1]	39	1		T97	2		T98	1		T99	1
all_values[13]	auto[0]	auto[0]	auto[0]	22	1		T97	2		T205	1		T271	1
all_values[13]	auto[0]	auto[0]	auto[1]	58	1		T98	1		T99	1		T204	1
all_values[13]	auto[0]	auto[1]	auto[0]	16	1		T97	2		T204	1		T274	2
all_values[13]	auto[0]	auto[1]	auto[1]	56	1		T99	2		T204	3		T206	1
all_values[13]	auto[1]	auto[0]	auto[1]	61	1		T98	2		T204	1		T206	1
all_values[13]	auto[1]	auto[1]	auto[1]	53	1		T98	1		T99	1		T204	1
all_values[14]	auto[0]	auto[0]	auto[0]	30	1		T98	1		T99	3		T205	1
all_values[14]	auto[0]	auto[0]	auto[1]	57	1		T97	1		T204	1		T206	2
all_values[14]	auto[0]	auto[1]	auto[0]	22	1		T97	1		T98	1		T99	1
all_values[14]	auto[0]	auto[1]	auto[1]	55	1		T98	1		T204	2		T206	1
all_values[14]	auto[1]	auto[0]	auto[1]	59	1		T97	2		T205	1		T269	2
all_values[14]	auto[1]	auto[1]	auto[1]	43	1		T98	1		T204	4		T206	1
all_values[15]	auto[0]	auto[0]	auto[0]	36	1		T98	1		T269	1		T271	1
all_values[15]	auto[0]	auto[0]	auto[1]	58	1		T97	1		T99	2		T204	4
all_values[15]	auto[0]	auto[1]	auto[0]	18	1		T206	1		T271	1		T279	1
all_values[15]	auto[0]	auto[1]	auto[1]	53	1		T97	1		T98	2		T205	2
all_values[15]	auto[1]	auto[0]	auto[1]	55	1		T97	2		T99	1		T205	1
all_values[15]	auto[1]	auto[1]	auto[1]	46	1		T98	1		T99	1		T204	3
all_values[16]	auto[0]	auto[0]	auto[0]	27	1		T97	1		T205	1		T270	2
all_values[16]	auto[0]	auto[0]	auto[1]	47	1		T97	1		T98	1		T99	1
all_values[16]	auto[0]	auto[1]	auto[0]	27	1		T97	1		T206	1		T269	1
all_values[16]	auto[0]	auto[1]	auto[1]	56	1		T98	1		T204	3		T205	1
all_values[16]	auto[1]	auto[0]	auto[1]	64	1		T98	2		T99	3		T204	3
all_values[16]	auto[1]	auto[1]	auto[1]	45	1		T97	1		T205	2		T269	3
all_values[17]	auto[0]	auto[0]	auto[0]	29	1		T97	1		T205	1		T270	1
all_values[17]	auto[0]	auto[0]	auto[1]	64	1		T98	1		T204	1		T205	2
all_values[17]	auto[0]	auto[1]	auto[0]	20	1		T204	5		T206	1		T272	3
all_values[17]	auto[0]	auto[1]	auto[1]	54	1		T97	1		T99	2		T206	1
all_values[17]	auto[1]	auto[0]	auto[1]	52	1		T98	3		T206	1		T205	1
all_values[17]	auto[1]	auto[1]	auto[1]	47	1		T97	2		T99	2		T204	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal