Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.43 97.48 92.37 97.86 68.75 95.77 98.17 96.58


Total test records in report: 2133
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html
T240 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2644388035 Jun 02 02:14:57 PM PDT 24 Jun 02 02:14:59 PM PDT 24 177977835 ps
T274 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2301564528 Jun 02 02:15:08 PM PDT 24 Jun 02 02:15:09 PM PDT 24 64195049 ps
T261 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1588767905 Jun 02 02:14:33 PM PDT 24 Jun 02 02:14:35 PM PDT 24 110000445 ps
T262 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3549674673 Jun 02 02:15:04 PM PDT 24 Jun 02 02:15:06 PM PDT 24 259764007 ps
T267 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1524140328 Jun 02 02:14:58 PM PDT 24 Jun 02 02:14:59 PM PDT 24 57142900 ps
T263 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1265295716 Jun 02 02:15:02 PM PDT 24 Jun 02 02:15:04 PM PDT 24 120147202 ps
T241 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2510280266 Jun 02 02:15:04 PM PDT 24 Jun 02 02:15:06 PM PDT 24 138538079 ps
T257 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.327316253 Jun 02 02:14:33 PM PDT 24 Jun 02 02:14:35 PM PDT 24 140041835 ps
T272 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3396210184 Jun 02 02:15:02 PM PDT 24 Jun 02 02:15:03 PM PDT 24 50190986 ps
T226 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.776509310 Jun 02 02:14:56 PM PDT 24 Jun 02 02:14:58 PM PDT 24 68430842 ps
T268 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.4023190804 Jun 02 02:15:06 PM PDT 24 Jun 02 02:15:07 PM PDT 24 36219759 ps
T227 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1930161584 Jun 02 02:14:50 PM PDT 24 Jun 02 02:14:52 PM PDT 24 176712996 ps
T264 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2194244618 Jun 02 02:14:48 PM PDT 24 Jun 02 02:14:49 PM PDT 24 71223517 ps
T265 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2389175803 Jun 02 02:14:35 PM PDT 24 Jun 02 02:14:37 PM PDT 24 156847453 ps
T279 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1124233024 Jun 02 02:15:10 PM PDT 24 Jun 02 02:15:11 PM PDT 24 51573657 ps
T2035 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.4290938574 Jun 02 02:14:30 PM PDT 24 Jun 02 02:14:33 PM PDT 24 325979445 ps
T2036 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2593005397 Jun 02 02:14:36 PM PDT 24 Jun 02 02:14:38 PM PDT 24 58084583 ps
T229 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2221104226 Jun 02 02:14:50 PM PDT 24 Jun 02 02:14:53 PM PDT 24 95242221 ps
T228 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3977206529 Jun 02 02:14:47 PM PDT 24 Jun 02 02:14:50 PM PDT 24 127998554 ps
T2037 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2042473822 Jun 02 02:14:57 PM PDT 24 Jun 02 02:14:58 PM PDT 24 41457841 ps
T266 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1662402173 Jun 02 02:14:32 PM PDT 24 Jun 02 02:14:33 PM PDT 24 109051623 ps
T2038 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1915327314 Jun 02 02:14:37 PM PDT 24 Jun 02 02:14:39 PM PDT 24 93826830 ps
T2039 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3906916882 Jun 02 02:14:41 PM PDT 24 Jun 02 02:14:44 PM PDT 24 293730052 ps
T230 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3877684228 Jun 02 02:14:47 PM PDT 24 Jun 02 02:14:50 PM PDT 24 133023841 ps
T2040 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3756411209 Jun 02 02:14:48 PM PDT 24 Jun 02 02:14:50 PM PDT 24 91506443 ps
T280 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1748272354 Jun 02 02:15:07 PM PDT 24 Jun 02 02:15:10 PM PDT 24 767490924 ps
T281 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1956643828 Jun 02 02:14:42 PM PDT 24 Jun 02 02:14:45 PM PDT 24 405698327 ps
T2041 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.266974429 Jun 02 02:14:49 PM PDT 24 Jun 02 02:14:50 PM PDT 24 44560191 ps
T2042 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.270983347 Jun 02 02:15:04 PM PDT 24 Jun 02 02:15:06 PM PDT 24 49146938 ps
T233 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2345699413 Jun 02 02:14:51 PM PDT 24 Jun 02 02:14:53 PM PDT 24 186874851 ps
T2043 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.694926436 Jun 02 02:14:50 PM PDT 24 Jun 02 02:14:52 PM PDT 24 230749342 ps
T232 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2288529319 Jun 02 02:14:33 PM PDT 24 Jun 02 02:14:35 PM PDT 24 185485736 ps
T2044 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.200086123 Jun 02 02:15:00 PM PDT 24 Jun 02 02:15:02 PM PDT 24 122303961 ps
T276 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1594082277 Jun 02 02:15:02 PM PDT 24 Jun 02 02:15:03 PM PDT 24 83160888 ps
T2045 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.506041821 Jun 02 02:14:31 PM PDT 24 Jun 02 02:14:36 PM PDT 24 482188960 ps
T2046 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3149816201 Jun 02 02:14:50 PM PDT 24 Jun 02 02:14:51 PM PDT 24 66130896 ps
T2047 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.924045590 Jun 02 02:14:55 PM PDT 24 Jun 02 02:14:57 PM PDT 24 120143746 ps
T277 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1541478078 Jun 02 02:15:01 PM PDT 24 Jun 02 02:15:02 PM PDT 24 78716745 ps
T2048 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3234316070 Jun 02 02:14:41 PM PDT 24 Jun 02 02:14:42 PM PDT 24 81516996 ps
T2049 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3262976814 Jun 02 02:14:30 PM PDT 24 Jun 02 02:14:36 PM PDT 24 1193969828 ps
T278 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3394015201 Jun 02 02:14:49 PM PDT 24 Jun 02 02:14:50 PM PDT 24 31700405 ps
T2050 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2003648066 Jun 02 02:14:51 PM PDT 24 Jun 02 02:14:52 PM PDT 24 41443684 ps
T2051 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1332401410 Jun 02 02:14:51 PM PDT 24 Jun 02 02:14:53 PM PDT 24 265540674 ps
T2052 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3945231490 Jun 02 02:15:12 PM PDT 24 Jun 02 02:15:13 PM PDT 24 34992907 ps
T2053 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3551230508 Jun 02 02:14:58 PM PDT 24 Jun 02 02:15:00 PM PDT 24 159036685 ps
T2054 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.235721702 Jun 02 02:14:56 PM PDT 24 Jun 02 02:14:57 PM PDT 24 56061414 ps
T286 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2419468094 Jun 02 02:14:54 PM PDT 24 Jun 02 02:14:59 PM PDT 24 514782533 ps
T2055 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2146729673 Jun 02 02:15:09 PM PDT 24 Jun 02 02:15:10 PM PDT 24 63779720 ps
T234 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.4236636703 Jun 02 02:15:02 PM PDT 24 Jun 02 02:15:05 PM PDT 24 85526809 ps
T2056 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1118759881 Jun 02 02:15:08 PM PDT 24 Jun 02 02:15:09 PM PDT 24 39964613 ps
T287 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3890344274 Jun 02 02:14:57 PM PDT 24 Jun 02 02:15:01 PM PDT 24 1257540111 ps
T2057 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.281133679 Jun 02 02:14:35 PM PDT 24 Jun 02 02:14:36 PM PDT 24 75642763 ps
T2058 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.367230877 Jun 02 02:14:54 PM PDT 24 Jun 02 02:14:57 PM PDT 24 244019390 ps
T2059 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2743683298 Jun 02 02:14:59 PM PDT 24 Jun 02 02:15:01 PM PDT 24 130934328 ps
T2060 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.4222538192 Jun 02 02:14:47 PM PDT 24 Jun 02 02:14:49 PM PDT 24 96379122 ps
T2061 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2292165748 Jun 02 02:14:54 PM PDT 24 Jun 02 02:14:56 PM PDT 24 129072621 ps
T2062 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2582610421 Jun 02 02:15:05 PM PDT 24 Jun 02 02:15:07 PM PDT 24 68259923 ps
T2063 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1333563688 Jun 02 02:15:06 PM PDT 24 Jun 02 02:15:08 PM PDT 24 51241551 ps
T2064 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1072492280 Jun 02 02:14:51 PM PDT 24 Jun 02 02:14:53 PM PDT 24 154112890 ps
T2065 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.874107213 Jun 02 02:14:47 PM PDT 24 Jun 02 02:14:49 PM PDT 24 105413288 ps
T2066 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2514762213 Jun 02 02:14:30 PM PDT 24 Jun 02 02:14:34 PM PDT 24 146115766 ps
T2067 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3037312189 Jun 02 02:14:30 PM PDT 24 Jun 02 02:14:31 PM PDT 24 47275242 ps
T2068 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3654047377 Jun 02 02:14:40 PM PDT 24 Jun 02 02:14:43 PM PDT 24 154269155 ps
T2069 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.4255899244 Jun 02 02:15:03 PM PDT 24 Jun 02 02:15:04 PM PDT 24 47336515 ps
T2070 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2216978997 Jun 02 02:14:48 PM PDT 24 Jun 02 02:14:50 PM PDT 24 162611107 ps
T2071 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1891795831 Jun 02 02:14:58 PM PDT 24 Jun 02 02:15:00 PM PDT 24 294640625 ps
T2072 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1621520610 Jun 02 02:14:57 PM PDT 24 Jun 02 02:14:58 PM PDT 24 117561323 ps
T2073 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.733730412 Jun 02 02:14:36 PM PDT 24 Jun 02 02:14:38 PM PDT 24 222329244 ps
T2074 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3583917786 Jun 02 02:14:47 PM PDT 24 Jun 02 02:14:56 PM PDT 24 666621377 ps
T2075 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1889054710 Jun 02 02:14:47 PM PDT 24 Jun 02 02:14:52 PM PDT 24 704697305 ps
T224 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.258556678 Jun 02 02:14:43 PM PDT 24 Jun 02 02:14:46 PM PDT 24 188629083 ps
T2076 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1806548997 Jun 02 02:15:01 PM PDT 24 Jun 02 02:15:02 PM PDT 24 61613000 ps
T2077 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3032150398 Jun 02 02:15:04 PM PDT 24 Jun 02 02:15:05 PM PDT 24 57520715 ps
T2078 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.170930388 Jun 02 02:15:01 PM PDT 24 Jun 02 02:15:03 PM PDT 24 105824461 ps
T2079 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2114678618 Jun 02 02:14:36 PM PDT 24 Jun 02 02:14:37 PM PDT 24 35729214 ps
T2080 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.696020392 Jun 02 02:14:51 PM PDT 24 Jun 02 02:14:53 PM PDT 24 85551336 ps
T2081 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1941298538 Jun 02 02:15:02 PM PDT 24 Jun 02 02:15:03 PM PDT 24 42752932 ps
T285 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1807683134 Jun 02 02:14:51 PM PDT 24 Jun 02 02:14:57 PM PDT 24 1222085993 ps
T2082 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.474270492 Jun 02 02:14:48 PM PDT 24 Jun 02 02:14:50 PM PDT 24 88895798 ps
T2083 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1226926542 Jun 02 02:14:44 PM PDT 24 Jun 02 02:14:47 PM PDT 24 171622238 ps
T2084 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1135611092 Jun 02 02:14:33 PM PDT 24 Jun 02 02:14:35 PM PDT 24 89174456 ps
T2085 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3608683219 Jun 02 02:14:35 PM PDT 24 Jun 02 02:14:36 PM PDT 24 52745041 ps
T284 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3634350481 Jun 02 02:14:41 PM PDT 24 Jun 02 02:14:48 PM PDT 24 1979328544 ps
T2086 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2572976610 Jun 02 02:15:06 PM PDT 24 Jun 02 02:15:07 PM PDT 24 97973974 ps
T2087 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2419652317 Jun 02 02:14:32 PM PDT 24 Jun 02 02:14:34 PM PDT 24 126109942 ps
T2088 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1117343491 Jun 02 02:14:47 PM PDT 24 Jun 02 02:14:48 PM PDT 24 55542854 ps
T2089 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.139622480 Jun 02 02:14:56 PM PDT 24 Jun 02 02:14:58 PM PDT 24 85345802 ps
T2090 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3178652815 Jun 02 02:14:50 PM PDT 24 Jun 02 02:14:52 PM PDT 24 236990306 ps
T2091 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1639616347 Jun 02 02:14:56 PM PDT 24 Jun 02 02:14:58 PM PDT 24 169891084 ps
T2092 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2923753820 Jun 02 02:14:49 PM PDT 24 Jun 02 02:14:52 PM PDT 24 266049300 ps
T2093 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2675276136 Jun 02 02:14:54 PM PDT 24 Jun 02 02:14:55 PM PDT 24 93222043 ps
T2094 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.221474148 Jun 02 02:14:53 PM PDT 24 Jun 02 02:14:55 PM PDT 24 103842247 ps
T2095 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3541253756 Jun 02 02:14:42 PM PDT 24 Jun 02 02:14:43 PM PDT 24 78818715 ps
T2096 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.116314496 Jun 02 02:14:45 PM PDT 24 Jun 02 02:14:47 PM PDT 24 81996911 ps
T282 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.523933585 Jun 02 02:14:53 PM PDT 24 Jun 02 02:14:58 PM PDT 24 472461589 ps
T2097 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1454855166 Jun 02 02:15:04 PM PDT 24 Jun 02 02:15:05 PM PDT 24 59587773 ps
T2098 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.323949268 Jun 02 02:15:08 PM PDT 24 Jun 02 02:15:09 PM PDT 24 38092602 ps
T2099 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.146833405 Jun 02 02:14:34 PM PDT 24 Jun 02 02:14:38 PM PDT 24 306147862 ps
T2100 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2812899523 Jun 02 02:14:47 PM PDT 24 Jun 02 02:14:53 PM PDT 24 1288818538 ps
T2101 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.991868901 Jun 02 02:14:58 PM PDT 24 Jun 02 02:14:59 PM PDT 24 33464710 ps
T2102 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3490606226 Jun 02 02:15:07 PM PDT 24 Jun 02 02:15:08 PM PDT 24 78112462 ps
T2103 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1792731801 Jun 02 02:14:41 PM PDT 24 Jun 02 02:14:44 PM PDT 24 86703724 ps
T2104 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1073493885 Jun 02 02:15:04 PM PDT 24 Jun 02 02:15:10 PM PDT 24 979941862 ps
T2105 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3539159044 Jun 02 02:15:09 PM PDT 24 Jun 02 02:15:10 PM PDT 24 70835493 ps
T2106 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2898240679 Jun 02 02:14:55 PM PDT 24 Jun 02 02:14:59 PM PDT 24 410256914 ps
T2107 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.178922669 Jun 02 02:14:56 PM PDT 24 Jun 02 02:14:58 PM PDT 24 240882135 ps
T2108 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3556909179 Jun 02 02:15:03 PM PDT 24 Jun 02 02:15:04 PM PDT 24 44021913 ps
T2109 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1354150006 Jun 02 02:15:08 PM PDT 24 Jun 02 02:15:09 PM PDT 24 66812884 ps
T2110 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4102894550 Jun 02 02:14:51 PM PDT 24 Jun 02 02:14:56 PM PDT 24 791018305 ps
T2111 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1758899483 Jun 02 02:15:03 PM PDT 24 Jun 02 02:15:04 PM PDT 24 48190325 ps
T2112 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2170085899 Jun 02 02:15:07 PM PDT 24 Jun 02 02:15:09 PM PDT 24 32233292 ps
T2113 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.919759115 Jun 02 02:15:06 PM PDT 24 Jun 02 02:15:08 PM PDT 24 34847446 ps
T2114 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4280515686 Jun 02 02:14:48 PM PDT 24 Jun 02 02:14:50 PM PDT 24 81892968 ps
T2115 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3569465295 Jun 02 02:14:53 PM PDT 24 Jun 02 02:14:55 PM PDT 24 280817033 ps
T2116 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1434887703 Jun 02 02:15:03 PM PDT 24 Jun 02 02:15:04 PM PDT 24 76192981 ps
T2117 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3398996394 Jun 02 02:15:09 PM PDT 24 Jun 02 02:15:10 PM PDT 24 64320259 ps
T2118 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3001077049 Jun 02 02:14:53 PM PDT 24 Jun 02 02:14:54 PM PDT 24 115301908 ps
T283 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.4218613773 Jun 02 02:14:34 PM PDT 24 Jun 02 02:14:40 PM PDT 24 1184205707 ps
T2119 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2951100677 Jun 02 02:14:48 PM PDT 24 Jun 02 02:14:51 PM PDT 24 230436875 ps
T2120 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1115770062 Jun 02 02:14:34 PM PDT 24 Jun 02 02:14:38 PM PDT 24 224511797 ps
T2121 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2794354351 Jun 02 02:14:45 PM PDT 24 Jun 02 02:14:47 PM PDT 24 133738303 ps
T2122 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2300026433 Jun 02 02:14:46 PM PDT 24 Jun 02 02:14:48 PM PDT 24 153604669 ps
T2123 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1486139830 Jun 02 02:14:55 PM PDT 24 Jun 02 02:14:58 PM PDT 24 155754427 ps
T2124 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.4164474811 Jun 02 02:14:41 PM PDT 24 Jun 02 02:14:43 PM PDT 24 187306298 ps
T2125 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1858410174 Jun 02 02:14:49 PM PDT 24 Jun 02 02:14:50 PM PDT 24 36191093 ps
T2126 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2953437111 Jun 02 02:14:54 PM PDT 24 Jun 02 02:14:56 PM PDT 24 87755882 ps
T2127 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.703881739 Jun 02 02:15:02 PM PDT 24 Jun 02 02:15:07 PM PDT 24 514783402 ps
T2128 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3796910049 Jun 02 02:14:48 PM PDT 24 Jun 02 02:14:52 PM PDT 24 415453975 ps
T2129 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1526092770 Jun 02 02:14:40 PM PDT 24 Jun 02 02:14:42 PM PDT 24 118024219 ps
T2130 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4253676742 Jun 02 02:15:03 PM PDT 24 Jun 02 02:15:04 PM PDT 24 42985730 ps
T2131 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.339183946 Jun 02 02:14:34 PM PDT 24 Jun 02 02:14:35 PM PDT 24 96197928 ps
T2132 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2819979904 Jun 02 02:15:02 PM PDT 24 Jun 02 02:15:03 PM PDT 24 72087479 ps
T2133 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1059072554 Jun 02 02:14:35 PM PDT 24 Jun 02 02:14:37 PM PDT 24 135962792 ps

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.2531875051
Short name T30
Test name
Test status
Simulation time 29679773983 ps
CPU time 55.73 seconds
Started Jun 02 03:27:38 PM PDT 24
Finished Jun 02 03:28:34 PM PDT 24
Peak memory 205704 kb
Host smart-3b21b8e9-2fb2-4b34-affb-eebaa9913b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25318
75051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.2531875051
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1130877187
Short name T270
Test name
Test status
Simulation time 59239241 ps
CPU time 0.7 seconds
Started Jun 02 02:15:05 PM PDT 24
Finished Jun 02 02:15:06 PM PDT 24
Peak memory 204548 kb
Host smart-7925d416-d128-4cce-a993-781920039d8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1130877187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1130877187
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.1281596106
Short name T7
Test name
Test status
Simulation time 14013184955 ps
CPU time 17.23 seconds
Started Jun 02 03:28:55 PM PDT 24
Finished Jun 02 03:29:13 PM PDT 24
Peak memory 205688 kb
Host smart-a48a2024-2ac2-4f69-9277-d22629e81912
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1281596106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.1281596106
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_smoke.749466806
Short name T35
Test name
Test status
Simulation time 10105834518 ps
CPU time 14.06 seconds
Started Jun 02 03:30:09 PM PDT 24
Finished Jun 02 03:30:24 PM PDT 24
Peak memory 205668 kb
Host smart-01589303-f319-4c6e-bb78-6d07946120e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74946
6806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.749466806
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1431101143
Short name T201
Test name
Test status
Simulation time 922017373 ps
CPU time 4.94 seconds
Started Jun 02 02:14:49 PM PDT 24
Finished Jun 02 02:14:54 PM PDT 24
Peak memory 204832 kb
Host smart-113a2ca8-2770-4213-baf2-a6ced265fc88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1431101143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1431101143
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.1461013633
Short name T38
Test name
Test status
Simulation time 10066926734 ps
CPU time 14.46 seconds
Started Jun 02 03:30:51 PM PDT 24
Finished Jun 02 03:31:07 PM PDT 24
Peak memory 205664 kb
Host smart-ce0a0d1e-f185-4461-bbe4-14d72eaae0a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14610
13633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.1461013633
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3396210184
Short name T272
Test name
Test status
Simulation time 50190986 ps
CPU time 0.72 seconds
Started Jun 02 02:15:02 PM PDT 24
Finished Jun 02 02:15:03 PM PDT 24
Peak memory 204496 kb
Host smart-6e49cdce-d891-47c0-a1e5-6c92540d44c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3396210184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3396210184
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.810180755
Short name T84
Test name
Test status
Simulation time 10094258885 ps
CPU time 13.38 seconds
Started Jun 02 03:28:08 PM PDT 24
Finished Jun 02 03:28:22 PM PDT 24
Peak memory 205684 kb
Host smart-0a4329d8-06fc-4bbb-8056-bb07eb0532ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81018
0755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.810180755
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.2545465939
Short name T62
Test name
Test status
Simulation time 10035391886 ps
CPU time 15.15 seconds
Started Jun 02 03:31:39 PM PDT 24
Finished Jun 02 03:31:55 PM PDT 24
Peak memory 205684 kb
Host smart-2ba68b70-20de-42b2-9e15-03fbd791fb59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25454
65939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.2545465939
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.1877242923
Short name T87
Test name
Test status
Simulation time 10107633456 ps
CPU time 12.85 seconds
Started Jun 02 03:29:49 PM PDT 24
Finished Jun 02 03:30:02 PM PDT 24
Peak memory 205468 kb
Host smart-076b36d7-fbf0-4244-ac71-00a0c444558f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18772
42923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.1877242923
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.960251387
Short name T22
Test name
Test status
Simulation time 10144871613 ps
CPU time 14.93 seconds
Started Jun 02 03:28:28 PM PDT 24
Finished Jun 02 03:28:44 PM PDT 24
Peak memory 205652 kb
Host smart-dbca9e04-345e-49a1-9f4b-0e41b6148831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96025
1387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.960251387
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3322220282
Short name T225
Test name
Test status
Simulation time 255150117 ps
CPU time 2.66 seconds
Started Jun 02 02:14:50 PM PDT 24
Finished Jun 02 02:14:53 PM PDT 24
Peak memory 204788 kb
Host smart-13f7e2fd-3804-4cac-b316-85dc20abd991
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3322220282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3322220282
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.669433336
Short name T26
Test name
Test status
Simulation time 10069619465 ps
CPU time 14.91 seconds
Started Jun 02 03:30:47 PM PDT 24
Finished Jun 02 03:31:03 PM PDT 24
Peak memory 205720 kb
Host smart-a9a63f34-0fb2-4482-86eb-25078f6cd614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66943
3336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.669433336
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1312019172
Short name T252
Test name
Test status
Simulation time 92044406 ps
CPU time 1.02 seconds
Started Jun 02 02:14:42 PM PDT 24
Finished Jun 02 02:14:43 PM PDT 24
Peak memory 204888 kb
Host smart-06b056ed-4ee1-40c1-bbff-eaa90c40e808
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1312019172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1312019172
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.2243227304
Short name T54
Test name
Test status
Simulation time 10446772803 ps
CPU time 16.9 seconds
Started Jun 02 03:31:37 PM PDT 24
Finished Jun 02 03:31:54 PM PDT 24
Peak memory 205700 kb
Host smart-67529fe1-1724-4c57-8f78-17ae9a723401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22432
27304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.2243227304
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.1403728957
Short name T56
Test name
Test status
Simulation time 10052325409 ps
CPU time 16.19 seconds
Started Jun 02 03:27:51 PM PDT 24
Finished Jun 02 03:28:08 PM PDT 24
Peak memory 205656 kb
Host smart-437a79e0-de1d-4ae6-ad2e-41ae262b4288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14037
28957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.1403728957
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.2869021787
Short name T207
Test name
Test status
Simulation time 741753195 ps
CPU time 1.51 seconds
Started Jun 02 03:26:27 PM PDT 24
Finished Jun 02 03:26:30 PM PDT 24
Peak memory 221756 kb
Host smart-c8292ccf-fa48-4fbc-a8ca-0ae2272c93c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2869021787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2869021787
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.1336879529
Short name T11
Test name
Test status
Simulation time 23298916681 ps
CPU time 23.9 seconds
Started Jun 02 03:26:32 PM PDT 24
Finished Jun 02 03:26:56 PM PDT 24
Peak memory 205808 kb
Host smart-7a29c61d-f3dd-4b92-a89d-4b7db31a3a50
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1336879529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.1336879529
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2679858844
Short name T97
Test name
Test status
Simulation time 103070311 ps
CPU time 0.71 seconds
Started Jun 02 02:15:07 PM PDT 24
Finished Jun 02 02:15:08 PM PDT 24
Peak memory 204516 kb
Host smart-cb4be25e-0ee6-484d-9cc6-fec8618f8c84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2679858844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2679858844
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.1907531719
Short name T189
Test name
Test status
Simulation time 10206837427 ps
CPU time 14.08 seconds
Started Jun 02 03:32:05 PM PDT 24
Finished Jun 02 03:32:20 PM PDT 24
Peak memory 205696 kb
Host smart-e1d1b3c3-32bd-4180-9066-8925c9a39c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19075
31719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.1907531719
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.338020867
Short name T52
Test name
Test status
Simulation time 10070926763 ps
CPU time 12.82 seconds
Started Jun 02 03:32:46 PM PDT 24
Finished Jun 02 03:32:59 PM PDT 24
Peak memory 205724 kb
Host smart-6107b443-6b03-422a-8a68-e3c42df0f645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33802
0867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.338020867
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.453580215
Short name T223
Test name
Test status
Simulation time 1226024493 ps
CPU time 5.07 seconds
Started Jun 02 02:14:30 PM PDT 24
Finished Jun 02 02:14:36 PM PDT 24
Peak memory 204852 kb
Host smart-f6e71c12-4b60-40c0-afac-d9864a57474d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=453580215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.453580215
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1124233024
Short name T279
Test name
Test status
Simulation time 51573657 ps
CPU time 0.66 seconds
Started Jun 02 02:15:10 PM PDT 24
Finished Jun 02 02:15:11 PM PDT 24
Peak memory 204552 kb
Host smart-b29e5e71-917f-4296-8731-0c48bfed67d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1124233024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1124233024
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/default/10.usbdev_enable.2008066273
Short name T2
Test name
Test status
Simulation time 10079913046 ps
CPU time 12.44 seconds
Started Jun 02 03:28:03 PM PDT 24
Finished Jun 02 03:28:17 PM PDT 24
Peak memory 205688 kb
Host smart-02b9e4d8-8eeb-43bd-b558-75f12fe44517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20080
66273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.2008066273
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.523933585
Short name T282
Test name
Test status
Simulation time 472461589 ps
CPU time 4.17 seconds
Started Jun 02 02:14:53 PM PDT 24
Finished Jun 02 02:14:58 PM PDT 24
Peak memory 204820 kb
Host smart-256f016c-1d53-4d79-8586-cd920982c6ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=523933585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.523933585
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.3972567560
Short name T162
Test name
Test status
Simulation time 36906060690 ps
CPU time 172.13 seconds
Started Jun 02 03:27:23 PM PDT 24
Finished Jun 02 03:30:16 PM PDT 24
Peak memory 205764 kb
Host smart-c7da32c7-8542-44d3-ae08-67ba6629bf33
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3972567560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.3972567560
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.235721702
Short name T2054
Test name
Test status
Simulation time 56061414 ps
CPU time 0.74 seconds
Started Jun 02 02:14:56 PM PDT 24
Finished Jun 02 02:14:57 PM PDT 24
Peak memory 204484 kb
Host smart-cc62fe15-d216-486c-965f-7be023451d01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=235721702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.235721702
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.3673289332
Short name T6
Test name
Test status
Simulation time 30825464323 ps
CPU time 512.39 seconds
Started Jun 02 03:26:37 PM PDT 24
Finished Jun 02 03:35:10 PM PDT 24
Peak memory 205768 kb
Host smart-4819588c-ff80-4301-807f-86e4931cf81f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3673289332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.3673289332
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.1628735464
Short name T218
Test name
Test status
Simulation time 5119837252 ps
CPU time 32.95 seconds
Started Jun 02 03:25:53 PM PDT 24
Finished Jun 02 03:26:27 PM PDT 24
Peak memory 205712 kb
Host smart-3b6ea5dd-a1a6-4754-bd13-31a96e27c685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16287
35464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.1628735464
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.1329966114
Short name T182
Test name
Test status
Simulation time 26299574786 ps
CPU time 137.33 seconds
Started Jun 02 03:26:30 PM PDT 24
Finished Jun 02 03:28:48 PM PDT 24
Peak memory 205856 kb
Host smart-928591d9-0207-4c38-9791-67cc945969a5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1329966114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.1329966114
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.698923484
Short name T175
Test name
Test status
Simulation time 28955732143 ps
CPU time 174.45 seconds
Started Jun 02 03:27:36 PM PDT 24
Finished Jun 02 03:30:31 PM PDT 24
Peak memory 205788 kb
Host smart-01324f73-15eb-4905-af4e-73b7c892c6a5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=698923484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.698923484
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2514762213
Short name T2066
Test name
Test status
Simulation time 146115766 ps
CPU time 3.06 seconds
Started Jun 02 02:14:30 PM PDT 24
Finished Jun 02 02:14:34 PM PDT 24
Peak memory 220540 kb
Host smart-af712ee9-7d44-4130-862e-3215931244a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2514762213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2514762213
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.16322194
Short name T186
Test name
Test status
Simulation time 26045942073 ps
CPU time 50.22 seconds
Started Jun 02 03:29:42 PM PDT 24
Finished Jun 02 03:30:34 PM PDT 24
Peak memory 205656 kb
Host smart-300c156e-8f4e-4933-9a46-c350bf08722c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16322
194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.16322194
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.3358017563
Short name T88
Test name
Test status
Simulation time 10959801244 ps
CPU time 14.49 seconds
Started Jun 02 03:29:51 PM PDT 24
Finished Jun 02 03:30:06 PM PDT 24
Peak memory 205740 kb
Host smart-0ebc9d49-68ea-49f7-a65e-b44603c91b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33580
17563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.3358017563
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.2659399807
Short name T77
Test name
Test status
Simulation time 10101801686 ps
CPU time 13.6 seconds
Started Jun 02 03:30:01 PM PDT 24
Finished Jun 02 03:30:15 PM PDT 24
Peak memory 205664 kb
Host smart-3427ad8b-4b72-4543-b922-9afda7e622af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26593
99807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.2659399807
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.110420583
Short name T63
Test name
Test status
Simulation time 10053146303 ps
CPU time 14 seconds
Started Jun 02 03:28:10 PM PDT 24
Finished Jun 02 03:28:25 PM PDT 24
Peak memory 205784 kb
Host smart-683583a9-002f-4b57-a95a-02ace5329d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11042
0583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.110420583
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.1980377547
Short name T145
Test name
Test status
Simulation time 10052286160 ps
CPU time 14.62 seconds
Started Jun 02 03:26:09 PM PDT 24
Finished Jun 02 03:26:24 PM PDT 24
Peak memory 205704 kb
Host smart-f0aecf1e-5271-4406-91e1-c67464fa97b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19803
77547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.1980377547
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.457621141
Short name T153
Test name
Test status
Simulation time 10060868228 ps
CPU time 15.78 seconds
Started Jun 02 03:28:08 PM PDT 24
Finished Jun 02 03:28:25 PM PDT 24
Peak memory 205680 kb
Host smart-24e6a61d-bf02-4f59-ae2e-16ec60ed9822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45762
1141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.457621141
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3519125106
Short name T957
Test name
Test status
Simulation time 31352564764 ps
CPU time 55.19 seconds
Started Jun 02 03:26:44 PM PDT 24
Finished Jun 02 03:27:40 PM PDT 24
Peak memory 205692 kb
Host smart-cf96d22b-ae4a-4394-b672-deb369ea7b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35191
25106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3519125106
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.3889767772
Short name T295
Test name
Test status
Simulation time 10084561443 ps
CPU time 13.21 seconds
Started Jun 02 03:26:28 PM PDT 24
Finished Jun 02 03:26:42 PM PDT 24
Peak memory 205788 kb
Host smart-1ffec973-ddb3-45e2-aed1-b128dfb3cacd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38897
67772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.3889767772
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.528073231
Short name T188
Test name
Test status
Simulation time 10099368748 ps
CPU time 13.44 seconds
Started Jun 02 03:26:12 PM PDT 24
Finished Jun 02 03:26:26 PM PDT 24
Peak memory 205596 kb
Host smart-e683d0fe-f57b-4e1c-b645-d6a9cfa42f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52807
3231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.528073231
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.3532782461
Short name T58
Test name
Test status
Simulation time 10096722308 ps
CPU time 13.87 seconds
Started Jun 02 03:26:18 PM PDT 24
Finished Jun 02 03:26:33 PM PDT 24
Peak memory 205672 kb
Host smart-cabd819e-8d33-4cd0-bea6-093433d216d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35327
82461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.3532782461
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1422675349
Short name T28
Test name
Test status
Simulation time 10043802925 ps
CPU time 13.25 seconds
Started Jun 02 03:26:28 PM PDT 24
Finished Jun 02 03:26:42 PM PDT 24
Peak memory 205668 kb
Host smart-cf489be0-be37-44f8-b3cc-4ef26514325d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14226
75349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1422675349
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.786702049
Short name T1717
Test name
Test status
Simulation time 10061695224 ps
CPU time 13.02 seconds
Started Jun 02 03:26:27 PM PDT 24
Finished Jun 02 03:26:41 PM PDT 24
Peak memory 205644 kb
Host smart-9c41ede2-be09-4e88-936e-8cd1801b8eb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78670
2049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.786702049
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2906580867
Short name T141
Test name
Test status
Simulation time 10097589671 ps
CPU time 13.41 seconds
Started Jun 02 03:27:59 PM PDT 24
Finished Jun 02 03:28:14 PM PDT 24
Peak memory 205612 kb
Host smart-21809c51-cf5d-46b1-9c52-f312a934d9d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29065
80867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2906580867
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.631988414
Short name T1340
Test name
Test status
Simulation time 10097051062 ps
CPU time 14.76 seconds
Started Jun 02 03:28:12 PM PDT 24
Finished Jun 02 03:28:28 PM PDT 24
Peak memory 205768 kb
Host smart-bc76bf12-6663-4462-b2f8-fed7b42d52f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63198
8414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.631988414
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1364489922
Short name T1864
Test name
Test status
Simulation time 10060823874 ps
CPU time 14.76 seconds
Started Jun 02 03:28:12 PM PDT 24
Finished Jun 02 03:28:28 PM PDT 24
Peak memory 205680 kb
Host smart-9653353f-5cc0-40ba-bf79-9c17adb77ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13644
89922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1364489922
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.28192327
Short name T68
Test name
Test status
Simulation time 10069104604 ps
CPU time 16.43 seconds
Started Jun 02 03:28:12 PM PDT 24
Finished Jun 02 03:28:30 PM PDT 24
Peak memory 205684 kb
Host smart-c65b3d03-ad8f-4163-a8db-8612a0c0b1e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28192
327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.28192327
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1693205815
Short name T869
Test name
Test status
Simulation time 10162722393 ps
CPU time 13.5 seconds
Started Jun 02 03:28:22 PM PDT 24
Finished Jun 02 03:28:37 PM PDT 24
Peak memory 205732 kb
Host smart-49bccb34-2382-440a-ab10-7ec8c8023755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16932
05815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1693205815
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.3729342776
Short name T881
Test name
Test status
Simulation time 10087164943 ps
CPU time 13.1 seconds
Started Jun 02 03:28:48 PM PDT 24
Finished Jun 02 03:29:02 PM PDT 24
Peak memory 205720 kb
Host smart-8d4ba0e3-0649-4867-bbd9-61a2d8cc76e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37293
42776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.3729342776
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.2109283251
Short name T173
Test name
Test status
Simulation time 10066106778 ps
CPU time 12.73 seconds
Started Jun 02 03:28:54 PM PDT 24
Finished Jun 02 03:29:07 PM PDT 24
Peak memory 205692 kb
Host smart-0b506f21-508d-468f-bf82-9cd40b2a93db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21092
83251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.2109283251
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_smoke.94207626
Short name T1579
Test name
Test status
Simulation time 10107084136 ps
CPU time 14.41 seconds
Started Jun 02 03:29:15 PM PDT 24
Finished Jun 02 03:29:31 PM PDT 24
Peak memory 205688 kb
Host smart-53e5bd8d-1669-48f0-8b0e-6d8bf784a0a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94207
626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.94207626
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.312815503
Short name T1055
Test name
Test status
Simulation time 30886794084 ps
CPU time 56.66 seconds
Started Jun 02 03:30:09 PM PDT 24
Finished Jun 02 03:31:06 PM PDT 24
Peak memory 205708 kb
Host smart-51f7f5b9-3a86-4e12-9304-9e0b5dad8adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31281
5503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.312815503
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2923753820
Short name T2092
Test name
Test status
Simulation time 266049300 ps
CPU time 3.19 seconds
Started Jun 02 02:14:49 PM PDT 24
Finished Jun 02 02:14:52 PM PDT 24
Peak memory 204736 kb
Host smart-38d0e7a3-fabb-49fd-ac19-bfc534f3598d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2923753820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2923753820
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.3498687100
Short name T128
Test name
Test status
Simulation time 10143164390 ps
CPU time 13.93 seconds
Started Jun 02 03:26:02 PM PDT 24
Finished Jun 02 03:26:17 PM PDT 24
Peak memory 205808 kb
Host smart-a0683665-ef9a-4f4e-9158-8f3c9eec3a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34986
87100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.3498687100
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.3577533719
Short name T1270
Test name
Test status
Simulation time 10055030816 ps
CPU time 13.22 seconds
Started Jun 02 03:26:07 PM PDT 24
Finished Jun 02 03:26:21 PM PDT 24
Peak memory 205680 kb
Host smart-9c1bd704-aedf-41bb-ad18-0d6f74e5e31a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35775
33719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.3577533719
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1658172802
Short name T1998
Test name
Test status
Simulation time 10158520238 ps
CPU time 14.19 seconds
Started Jun 02 03:26:24 PM PDT 24
Finished Jun 02 03:26:38 PM PDT 24
Peak memory 205712 kb
Host smart-40ef54fb-5cea-4725-96cb-ee45b05073b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16581
72802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1658172802
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.3241830324
Short name T109
Test name
Test status
Simulation time 10089904502 ps
CPU time 14.85 seconds
Started Jun 02 03:28:02 PM PDT 24
Finished Jun 02 03:28:18 PM PDT 24
Peak memory 205780 kb
Host smart-ea40ef5e-ab89-476a-a581-d140933cf85c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32418
30324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.3241830324
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2813282028
Short name T107
Test name
Test status
Simulation time 10090397909 ps
CPU time 13.44 seconds
Started Jun 02 03:28:12 PM PDT 24
Finished Jun 02 03:28:26 PM PDT 24
Peak memory 205560 kb
Host smart-bf874133-8287-4a38-b2ca-4d398becca35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28132
82028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2813282028
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.4148716400
Short name T1976
Test name
Test status
Simulation time 10129234136 ps
CPU time 14.44 seconds
Started Jun 02 03:28:24 PM PDT 24
Finished Jun 02 03:28:39 PM PDT 24
Peak memory 205868 kb
Host smart-0a89924f-43af-40ce-81f5-bfae95cbf859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41487
16400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.4148716400
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.158668126
Short name T93
Test name
Test status
Simulation time 30836463727 ps
CPU time 60.24 seconds
Started Jun 02 03:28:49 PM PDT 24
Finished Jun 02 03:29:50 PM PDT 24
Peak memory 205656 kb
Host smart-56f8fc5c-51a7-45cc-99e8-77c9cce0b32e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15866
8126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.158668126
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.909422479
Short name T123
Test name
Test status
Simulation time 10087301305 ps
CPU time 13.19 seconds
Started Jun 02 03:29:02 PM PDT 24
Finished Jun 02 03:29:16 PM PDT 24
Peak memory 205860 kb
Host smart-3f6be49e-eae3-497e-854f-d9b86cac1a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90942
2479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.909422479
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2688776207
Short name T126
Test name
Test status
Simulation time 10142607438 ps
CPU time 17.67 seconds
Started Jun 02 03:29:19 PM PDT 24
Finished Jun 02 03:29:37 PM PDT 24
Peak memory 205652 kb
Host smart-7b4e2a29-bb4d-4f07-a143-5b453f8ffb32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26887
76207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2688776207
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.3588351445
Short name T120
Test name
Test status
Simulation time 10155840071 ps
CPU time 14.15 seconds
Started Jun 02 03:29:42 PM PDT 24
Finished Jun 02 03:29:57 PM PDT 24
Peak memory 205344 kb
Host smart-439418f1-336a-4137-b46f-2efd6be2ca11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35883
51445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3588351445
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.958405747
Short name T105
Test name
Test status
Simulation time 10131148011 ps
CPU time 15.28 seconds
Started Jun 02 03:26:49 PM PDT 24
Finished Jun 02 03:27:05 PM PDT 24
Peak memory 205704 kb
Host smart-47060d37-8cd9-4910-a9c8-1a40dd911f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95840
5747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.958405747
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.3922481015
Short name T112
Test name
Test status
Simulation time 10116574594 ps
CPU time 13.66 seconds
Started Jun 02 03:31:15 PM PDT 24
Finished Jun 02 03:31:30 PM PDT 24
Peak memory 205740 kb
Host smart-8ca7df9c-52b4-4729-9bc0-625056d1468d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39224
81015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.3922481015
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.24839623
Short name T78
Test name
Test status
Simulation time 10128370210 ps
CPU time 12.47 seconds
Started Jun 02 03:31:40 PM PDT 24
Finished Jun 02 03:31:54 PM PDT 24
Peak memory 205768 kb
Host smart-ae0d7dbc-b8c4-4970-97a4-ac992e7e15f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24839
623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.24839623
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.4105648656
Short name T119
Test name
Test status
Simulation time 10102575873 ps
CPU time 13.39 seconds
Started Jun 02 03:31:52 PM PDT 24
Finished Jun 02 03:32:06 PM PDT 24
Peak memory 205596 kb
Host smart-099361ce-079d-496f-ad6f-234d8e204e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41056
48656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.4105648656
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.119337031
Short name T251
Test name
Test status
Simulation time 368856607 ps
CPU time 3.73 seconds
Started Jun 02 02:14:33 PM PDT 24
Finished Jun 02 02:14:37 PM PDT 24
Peak memory 204816 kb
Host smart-9adec39a-9eab-4715-9ac6-a876a919a05d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=119337031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.119337031
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3262976814
Short name T2049
Test name
Test status
Simulation time 1193969828 ps
CPU time 4.74 seconds
Started Jun 02 02:14:30 PM PDT 24
Finished Jun 02 02:14:36 PM PDT 24
Peak memory 204684 kb
Host smart-4ae95bcf-5f96-4197-a632-d718c4557c2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3262976814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3262976814
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1135611092
Short name T2084
Test name
Test status
Simulation time 89174456 ps
CPU time 0.93 seconds
Started Jun 02 02:14:33 PM PDT 24
Finished Jun 02 02:14:35 PM PDT 24
Peak memory 204524 kb
Host smart-9ecb30ca-8552-4ce5-af6a-13ff20447c78
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1135611092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1135611092
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.339183946
Short name T2131
Test name
Test status
Simulation time 96197928 ps
CPU time 1.14 seconds
Started Jun 02 02:14:34 PM PDT 24
Finished Jun 02 02:14:35 PM PDT 24
Peak memory 213052 kb
Host smart-413976ec-d863-4873-a428-166245aba967
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339183946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev
_csr_mem_rw_with_rand_reset.339183946
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1662402173
Short name T266
Test name
Test status
Simulation time 109051623 ps
CPU time 1.01 seconds
Started Jun 02 02:14:32 PM PDT 24
Finished Jun 02 02:14:33 PM PDT 24
Peak memory 205016 kb
Host smart-a6c2ec46-0ca8-4cdf-9c61-6f3d6fe28551
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1662402173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1662402173
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.954152550
Short name T271
Test name
Test status
Simulation time 41899548 ps
CPU time 0.69 seconds
Started Jun 02 02:14:30 PM PDT 24
Finished Jun 02 02:14:31 PM PDT 24
Peak memory 204444 kb
Host smart-04d823e0-44d4-4a7b-aa5e-4dc42d42f1d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=954152550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.954152550
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.327316253
Short name T257
Test name
Test status
Simulation time 140041835 ps
CPU time 1.58 seconds
Started Jun 02 02:14:33 PM PDT 24
Finished Jun 02 02:14:35 PM PDT 24
Peak memory 213072 kb
Host smart-db2aeb47-fccc-439b-8c2d-f6c03bc00d60
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=327316253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.327316253
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.4290938574
Short name T2035
Test name
Test status
Simulation time 325979445 ps
CPU time 2.67 seconds
Started Jun 02 02:14:30 PM PDT 24
Finished Jun 02 02:14:33 PM PDT 24
Peak memory 204828 kb
Host smart-b07639a6-96c8-4aef-bd91-795effa4e3fa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4290938574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.4290938574
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2419652317
Short name T2087
Test name
Test status
Simulation time 126109942 ps
CPU time 1.14 seconds
Started Jun 02 02:14:32 PM PDT 24
Finished Jun 02 02:14:34 PM PDT 24
Peak memory 204800 kb
Host smart-0b6415a1-1891-4fd2-b84f-2d925e1eabf1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2419652317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.2419652317
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2288529319
Short name T232
Test name
Test status
Simulation time 185485736 ps
CPU time 1.87 seconds
Started Jun 02 02:14:33 PM PDT 24
Finished Jun 02 02:14:35 PM PDT 24
Peak memory 204864 kb
Host smart-550059a6-09ec-4c74-8079-575e8db26992
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2288529319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2288529319
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.146833405
Short name T2099
Test name
Test status
Simulation time 306147862 ps
CPU time 3.67 seconds
Started Jun 02 02:14:34 PM PDT 24
Finished Jun 02 02:14:38 PM PDT 24
Peak memory 204760 kb
Host smart-fdcdc512-9379-4d0b-96ff-ada0e9e9e72a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=146833405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.146833405
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.4042783023
Short name T256
Test name
Test status
Simulation time 209031235 ps
CPU time 4.26 seconds
Started Jun 02 02:14:36 PM PDT 24
Finished Jun 02 02:14:41 PM PDT 24
Peak memory 204728 kb
Host smart-e1f776d1-4ea4-477d-af34-11a4f26c235a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4042783023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.4042783023
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3234316070
Short name T2048
Test name
Test status
Simulation time 81516996 ps
CPU time 0.92 seconds
Started Jun 02 02:14:41 PM PDT 24
Finished Jun 02 02:14:42 PM PDT 24
Peak memory 204592 kb
Host smart-5be52d7b-fb2d-4e06-ac0b-8a9c234f9608
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3234316070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.3234316070
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3353289971
Short name T222
Test name
Test status
Simulation time 92817801 ps
CPU time 2.77 seconds
Started Jun 02 02:14:36 PM PDT 24
Finished Jun 02 02:14:39 PM PDT 24
Peak memory 216232 kb
Host smart-501811ee-0ce1-4621-a5ad-ef59bb0d673b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353289971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.3353289971
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.281133679
Short name T2057
Test name
Test status
Simulation time 75642763 ps
CPU time 1.05 seconds
Started Jun 02 02:14:35 PM PDT 24
Finished Jun 02 02:14:36 PM PDT 24
Peak memory 204824 kb
Host smart-3bc38bd9-a537-4974-8c8a-3e5db1933b30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=281133679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.281133679
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3037312189
Short name T2067
Test name
Test status
Simulation time 47275242 ps
CPU time 0.77 seconds
Started Jun 02 02:14:30 PM PDT 24
Finished Jun 02 02:14:31 PM PDT 24
Peak memory 204536 kb
Host smart-5298f349-f8df-4708-8587-56353d7c8c34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3037312189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3037312189
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2593005397
Short name T2036
Test name
Test status
Simulation time 58084583 ps
CPU time 1.45 seconds
Started Jun 02 02:14:36 PM PDT 24
Finished Jun 02 02:14:38 PM PDT 24
Peak memory 213052 kb
Host smart-4f07e663-56cd-42e4-bbed-0c5d3ac34008
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2593005397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2593005397
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.506041821
Short name T2045
Test name
Test status
Simulation time 482188960 ps
CPU time 4.49 seconds
Started Jun 02 02:14:31 PM PDT 24
Finished Jun 02 02:14:36 PM PDT 24
Peak memory 204724 kb
Host smart-210c13ad-fa6a-4d9f-884d-1525aeb78568
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=506041821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.506041821
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3300480328
Short name T259
Test name
Test status
Simulation time 222581705 ps
CPU time 1.93 seconds
Started Jun 02 02:14:38 PM PDT 24
Finished Jun 02 02:14:41 PM PDT 24
Peak memory 204764 kb
Host smart-61d85645-b794-4f2e-be9a-9634fb3ac541
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3300480328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.3300480328
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1870970825
Short name T238
Test name
Test status
Simulation time 798616292 ps
CPU time 5.21 seconds
Started Jun 02 02:14:31 PM PDT 24
Finished Jun 02 02:14:37 PM PDT 24
Peak memory 205092 kb
Host smart-9aec7c1c-6d48-4b48-8cc4-fd53b3cdea1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1870970825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1870970825
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1930161584
Short name T227
Test name
Test status
Simulation time 176712996 ps
CPU time 1.59 seconds
Started Jun 02 02:14:50 PM PDT 24
Finished Jun 02 02:14:52 PM PDT 24
Peak memory 214928 kb
Host smart-3cd7cbff-23ad-450b-9f21-c203655bdbcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930161584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.1930161584
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2003648066
Short name T2050
Test name
Test status
Simulation time 41443684 ps
CPU time 0.87 seconds
Started Jun 02 02:14:51 PM PDT 24
Finished Jun 02 02:14:52 PM PDT 24
Peak memory 204572 kb
Host smart-65f5bc2c-2bc9-477d-a25c-0c769291527b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2003648066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2003648066
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2675276136
Short name T2093
Test name
Test status
Simulation time 93222043 ps
CPU time 0.74 seconds
Started Jun 02 02:14:54 PM PDT 24
Finished Jun 02 02:14:55 PM PDT 24
Peak memory 204536 kb
Host smart-81c7c0c9-796b-41c0-a6fb-88949efda003
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2675276136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2675276136
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2292165748
Short name T2061
Test name
Test status
Simulation time 129072621 ps
CPU time 1.2 seconds
Started Jun 02 02:14:54 PM PDT 24
Finished Jun 02 02:14:56 PM PDT 24
Peak memory 204760 kb
Host smart-9a99e56a-e255-47ed-80f5-d333ed9771ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2292165748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2292165748
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2221104226
Short name T229
Test name
Test status
Simulation time 95242221 ps
CPU time 2.05 seconds
Started Jun 02 02:14:50 PM PDT 24
Finished Jun 02 02:14:53 PM PDT 24
Peak memory 204844 kb
Host smart-1478867d-a929-4903-b358-8b99657d82cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2221104226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2221104226
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1332401410
Short name T2051
Test name
Test status
Simulation time 265540674 ps
CPU time 2.1 seconds
Started Jun 02 02:14:51 PM PDT 24
Finished Jun 02 02:14:53 PM PDT 24
Peak memory 212996 kb
Host smart-8d3154ed-afc3-4aba-aa08-676b1e2c0648
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332401410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.1332401410
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.938246454
Short name T203
Test name
Test status
Simulation time 46029472 ps
CPU time 0.82 seconds
Started Jun 02 02:14:54 PM PDT 24
Finished Jun 02 02:14:55 PM PDT 24
Peak memory 204524 kb
Host smart-645bcc7b-605f-4394-a7a6-28e0feed5c9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=938246454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.938246454
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2897881414
Short name T269
Test name
Test status
Simulation time 84201652 ps
CPU time 0.73 seconds
Started Jun 02 02:14:54 PM PDT 24
Finished Jun 02 02:14:55 PM PDT 24
Peak memory 204536 kb
Host smart-d2a86352-67fe-42c7-bfa0-ac5e2ed3401b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2897881414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2897881414
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.694926436
Short name T2043
Test name
Test status
Simulation time 230749342 ps
CPU time 1.8 seconds
Started Jun 02 02:14:50 PM PDT 24
Finished Jun 02 02:14:52 PM PDT 24
Peak memory 204736 kb
Host smart-52ad72e9-d680-493b-ac74-7c93e8561e90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=694926436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.694926436
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2345699413
Short name T233
Test name
Test status
Simulation time 186874851 ps
CPU time 1.86 seconds
Started Jun 02 02:14:51 PM PDT 24
Finished Jun 02 02:14:53 PM PDT 24
Peak memory 213040 kb
Host smart-097c4253-631b-4261-87dc-04580045b879
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345699413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.2345699413
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1072492280
Short name T2064
Test name
Test status
Simulation time 154112890 ps
CPU time 1.12 seconds
Started Jun 02 02:14:51 PM PDT 24
Finished Jun 02 02:14:53 PM PDT 24
Peak memory 204812 kb
Host smart-51947900-2f39-4907-932d-33f27b5c39af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1072492280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1072492280
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3001077049
Short name T2118
Test name
Test status
Simulation time 115301908 ps
CPU time 0.73 seconds
Started Jun 02 02:14:53 PM PDT 24
Finished Jun 02 02:14:54 PM PDT 24
Peak memory 204552 kb
Host smart-00253337-0bda-4a63-8aed-1a7b31be29f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3001077049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.3001077049
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3569465295
Short name T2115
Test name
Test status
Simulation time 280817033 ps
CPU time 2.25 seconds
Started Jun 02 02:14:53 PM PDT 24
Finished Jun 02 02:14:55 PM PDT 24
Peak memory 204816 kb
Host smart-e9919ebd-a37c-4eff-9a9d-ed21d1916021
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3569465295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3569465295
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2419468094
Short name T286
Test name
Test status
Simulation time 514782533 ps
CPU time 4.41 seconds
Started Jun 02 02:14:54 PM PDT 24
Finished Jun 02 02:14:59 PM PDT 24
Peak memory 204720 kb
Host smart-c5b767de-d5b1-4e96-862b-4b6cdd9a4020
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2419468094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2419468094
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1486139830
Short name T2123
Test name
Test status
Simulation time 155754427 ps
CPU time 2.06 seconds
Started Jun 02 02:14:55 PM PDT 24
Finished Jun 02 02:14:58 PM PDT 24
Peak memory 213048 kb
Host smart-1572a99e-4bd3-489e-a709-173d76dbf36e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486139830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1486139830
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1621520610
Short name T2072
Test name
Test status
Simulation time 117561323 ps
CPU time 1.06 seconds
Started Jun 02 02:14:57 PM PDT 24
Finished Jun 02 02:14:58 PM PDT 24
Peak memory 204700 kb
Host smart-4be5c5c9-a26c-4bbe-91d3-9effbb707e4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1621520610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1621520610
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3551230508
Short name T2053
Test name
Test status
Simulation time 159036685 ps
CPU time 1.18 seconds
Started Jun 02 02:14:58 PM PDT 24
Finished Jun 02 02:15:00 PM PDT 24
Peak memory 204812 kb
Host smart-ada6c98b-966f-4d54-95dc-1460e7828018
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3551230508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3551230508
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.367230877
Short name T2058
Test name
Test status
Simulation time 244019390 ps
CPU time 3.02 seconds
Started Jun 02 02:14:54 PM PDT 24
Finished Jun 02 02:14:57 PM PDT 24
Peak memory 204860 kb
Host smart-12e37c0b-539e-4ce6-b915-83e51030a3d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=367230877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.367230877
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4102894550
Short name T2110
Test name
Test status
Simulation time 791018305 ps
CPU time 5.15 seconds
Started Jun 02 02:14:51 PM PDT 24
Finished Jun 02 02:14:56 PM PDT 24
Peak memory 204800 kb
Host smart-fcce3b34-51cf-4515-94c1-ca94758ac8e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4102894550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.4102894550
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.221474148
Short name T2094
Test name
Test status
Simulation time 103842247 ps
CPU time 1.37 seconds
Started Jun 02 02:14:53 PM PDT 24
Finished Jun 02 02:14:55 PM PDT 24
Peak memory 212992 kb
Host smart-b4b091ac-372a-412a-bb10-2cb668592da4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221474148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbde
v_csr_mem_rw_with_rand_reset.221474148
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2751602285
Short name T250
Test name
Test status
Simulation time 41072199 ps
CPU time 0.79 seconds
Started Jun 02 02:14:56 PM PDT 24
Finished Jun 02 02:14:57 PM PDT 24
Peak memory 204592 kb
Host smart-1aa2508c-9be4-4a6f-9d02-8f1d68948b7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2751602285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2751602285
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2042473822
Short name T2037
Test name
Test status
Simulation time 41457841 ps
CPU time 0.77 seconds
Started Jun 02 02:14:57 PM PDT 24
Finished Jun 02 02:14:58 PM PDT 24
Peak memory 204564 kb
Host smart-16a3451a-83c1-41c6-9ec1-eebfa8595585
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2042473822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.2042473822
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1639616347
Short name T2091
Test name
Test status
Simulation time 169891084 ps
CPU time 1.59 seconds
Started Jun 02 02:14:56 PM PDT 24
Finished Jun 02 02:14:58 PM PDT 24
Peak memory 204872 kb
Host smart-0fd3f99e-5904-4824-9f2e-10b01f4f2a7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1639616347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1639616347
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.924045590
Short name T2047
Test name
Test status
Simulation time 120143746 ps
CPU time 1.72 seconds
Started Jun 02 02:14:55 PM PDT 24
Finished Jun 02 02:14:57 PM PDT 24
Peak memory 213060 kb
Host smart-ebd35ab6-9644-4d3e-b621-f693508e4f29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=924045590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.924045590
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3890344274
Short name T287
Test name
Test status
Simulation time 1257540111 ps
CPU time 3.48 seconds
Started Jun 02 02:14:57 PM PDT 24
Finished Jun 02 02:15:01 PM PDT 24
Peak memory 204832 kb
Host smart-858f6ce2-84ea-449a-8bb1-8a577bae80ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3890344274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3890344274
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2644388035
Short name T240
Test name
Test status
Simulation time 177977835 ps
CPU time 2 seconds
Started Jun 02 02:14:57 PM PDT 24
Finished Jun 02 02:14:59 PM PDT 24
Peak memory 213056 kb
Host smart-3561b40d-2df8-4210-b4fe-4c8e0d3b9dad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644388035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.2644388035
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.4205515086
Short name T258
Test name
Test status
Simulation time 56193977 ps
CPU time 0.91 seconds
Started Jun 02 02:14:58 PM PDT 24
Finished Jun 02 02:14:59 PM PDT 24
Peak memory 204564 kb
Host smart-ebaecb7c-72c7-4464-894f-c66294b17640
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4205515086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.4205515086
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.991868901
Short name T2101
Test name
Test status
Simulation time 33464710 ps
CPU time 0.65 seconds
Started Jun 02 02:14:58 PM PDT 24
Finished Jun 02 02:14:59 PM PDT 24
Peak memory 204464 kb
Host smart-1eb284d4-b2b2-42db-8ada-6e487aa35361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=991868901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.991868901
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1891795831
Short name T2071
Test name
Test status
Simulation time 294640625 ps
CPU time 1.64 seconds
Started Jun 02 02:14:58 PM PDT 24
Finished Jun 02 02:15:00 PM PDT 24
Peak memory 204724 kb
Host smart-d73d11dd-80b6-43f4-8f5b-48eca280ab03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1891795831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1891795831
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.776509310
Short name T226
Test name
Test status
Simulation time 68430842 ps
CPU time 1.62 seconds
Started Jun 02 02:14:56 PM PDT 24
Finished Jun 02 02:14:58 PM PDT 24
Peak memory 204836 kb
Host smart-0f215fe1-568b-46b3-9d91-b8671ef8c9e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=776509310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.776509310
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2898240679
Short name T2106
Test name
Test status
Simulation time 410256914 ps
CPU time 3.06 seconds
Started Jun 02 02:14:55 PM PDT 24
Finished Jun 02 02:14:59 PM PDT 24
Peak memory 204832 kb
Host smart-cb414398-00dc-4b79-83c5-2f3ab0c90c18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2898240679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2898240679
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.200086123
Short name T2044
Test name
Test status
Simulation time 122303961 ps
CPU time 1.5 seconds
Started Jun 02 02:15:00 PM PDT 24
Finished Jun 02 02:15:02 PM PDT 24
Peak memory 212940 kb
Host smart-0d6835b4-d516-4316-a400-a48b8c4f9073
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200086123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde
v_csr_mem_rw_with_rand_reset.200086123
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2953437111
Short name T2126
Test name
Test status
Simulation time 87755882 ps
CPU time 1.05 seconds
Started Jun 02 02:14:54 PM PDT 24
Finished Jun 02 02:14:56 PM PDT 24
Peak memory 204780 kb
Host smart-927088ec-72a6-47ab-a36f-e669be972fb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2953437111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2953437111
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1524140328
Short name T267
Test name
Test status
Simulation time 57142900 ps
CPU time 0.7 seconds
Started Jun 02 02:14:58 PM PDT 24
Finished Jun 02 02:14:59 PM PDT 24
Peak memory 204544 kb
Host smart-95387b02-e418-473a-b860-0e5e73a1f4aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1524140328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1524140328
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2743683298
Short name T2059
Test name
Test status
Simulation time 130934328 ps
CPU time 1.56 seconds
Started Jun 02 02:14:59 PM PDT 24
Finished Jun 02 02:15:01 PM PDT 24
Peak memory 204840 kb
Host smart-477e94f8-7094-42f3-b4aa-7532f517a932
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2743683298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.2743683298
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.178922669
Short name T2107
Test name
Test status
Simulation time 240882135 ps
CPU time 2.34 seconds
Started Jun 02 02:14:56 PM PDT 24
Finished Jun 02 02:14:58 PM PDT 24
Peak memory 213008 kb
Host smart-b283e8d9-f3aa-462b-b912-17a631f5b0b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=178922669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.178922669
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3292030601
Short name T219
Test name
Test status
Simulation time 354659846 ps
CPU time 2.56 seconds
Started Jun 02 02:14:55 PM PDT 24
Finished Jun 02 02:14:58 PM PDT 24
Peak memory 204944 kb
Host smart-8a8cef05-db5e-4652-a475-b70bd1c8caa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3292030601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3292030601
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2510280266
Short name T241
Test name
Test status
Simulation time 138538079 ps
CPU time 1.71 seconds
Started Jun 02 02:15:04 PM PDT 24
Finished Jun 02 02:15:06 PM PDT 24
Peak memory 212980 kb
Host smart-d83f906e-2f2f-4d9c-8ccf-f3dff29576d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510280266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.2510280266
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4253676742
Short name T2130
Test name
Test status
Simulation time 42985730 ps
CPU time 0.85 seconds
Started Jun 02 02:15:03 PM PDT 24
Finished Jun 02 02:15:04 PM PDT 24
Peak memory 204576 kb
Host smart-93439417-3796-4d6e-bb04-9bf60aa704bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4253676742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.4253676742
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1434887703
Short name T2116
Test name
Test status
Simulation time 76192981 ps
CPU time 0.7 seconds
Started Jun 02 02:15:03 PM PDT 24
Finished Jun 02 02:15:04 PM PDT 24
Peak memory 204520 kb
Host smart-6e6655de-a153-47f0-bffe-9c61ea46b710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1434887703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1434887703
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.170930388
Short name T2078
Test name
Test status
Simulation time 105824461 ps
CPU time 1.27 seconds
Started Jun 02 02:15:01 PM PDT 24
Finished Jun 02 02:15:03 PM PDT 24
Peak memory 204856 kb
Host smart-0fb960cf-7061-458f-af01-21bf2abff16e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=170930388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.170930388
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.139622480
Short name T2089
Test name
Test status
Simulation time 85345802 ps
CPU time 1.83 seconds
Started Jun 02 02:14:56 PM PDT 24
Finished Jun 02 02:14:58 PM PDT 24
Peak memory 204872 kb
Host smart-4b5af0a8-09b7-4fea-97b5-09bd2df7bc49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=139622480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.139622480
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1073493885
Short name T2104
Test name
Test status
Simulation time 979941862 ps
CPU time 5.39 seconds
Started Jun 02 02:15:04 PM PDT 24
Finished Jun 02 02:15:10 PM PDT 24
Peak memory 204808 kb
Host smart-790b1fcb-d60b-458e-8e6f-ca9020e1590c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1073493885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1073493885
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1250247878
Short name T220
Test name
Test status
Simulation time 264314766 ps
CPU time 1.97 seconds
Started Jun 02 02:15:04 PM PDT 24
Finished Jun 02 02:15:07 PM PDT 24
Peak memory 213028 kb
Host smart-df895771-fdf0-46e8-a3d0-0dc7233b3a44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250247878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.1250247878
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2819979904
Short name T2132
Test name
Test status
Simulation time 72087479 ps
CPU time 0.89 seconds
Started Jun 02 02:15:02 PM PDT 24
Finished Jun 02 02:15:03 PM PDT 24
Peak memory 204488 kb
Host smart-e9b269d4-de04-4305-81e5-2c5ac1f9248e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2819979904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2819979904
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.4255899244
Short name T2069
Test name
Test status
Simulation time 47336515 ps
CPU time 0.76 seconds
Started Jun 02 02:15:03 PM PDT 24
Finished Jun 02 02:15:04 PM PDT 24
Peak memory 204572 kb
Host smart-b0187cbc-e350-4985-bf43-23116f6e9c9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4255899244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.4255899244
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1265295716
Short name T263
Test name
Test status
Simulation time 120147202 ps
CPU time 1.25 seconds
Started Jun 02 02:15:02 PM PDT 24
Finished Jun 02 02:15:04 PM PDT 24
Peak memory 204768 kb
Host smart-aa89c2a7-f2e2-4666-ba76-4b6b234c8a6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1265295716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.1265295716
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.220304425
Short name T221
Test name
Test status
Simulation time 159372363 ps
CPU time 1.68 seconds
Started Jun 02 02:15:04 PM PDT 24
Finished Jun 02 02:15:06 PM PDT 24
Peak memory 204784 kb
Host smart-070c601d-f455-411a-9908-cfc155d2501c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=220304425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.220304425
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.703881739
Short name T2127
Test name
Test status
Simulation time 514783402 ps
CPU time 4.26 seconds
Started Jun 02 02:15:02 PM PDT 24
Finished Jun 02 02:15:07 PM PDT 24
Peak memory 204708 kb
Host smart-7ae3152f-3b09-4c39-a7a0-a946cbf66eea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=703881739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.703881739
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.235689303
Short name T237
Test name
Test status
Simulation time 180210437 ps
CPU time 2.07 seconds
Started Jun 02 02:15:02 PM PDT 24
Finished Jun 02 02:15:04 PM PDT 24
Peak memory 212960 kb
Host smart-363a5cf0-0caa-4873-bb48-bbdb93156bc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235689303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbde
v_csr_mem_rw_with_rand_reset.235689303
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1454855166
Short name T2097
Test name
Test status
Simulation time 59587773 ps
CPU time 0.87 seconds
Started Jun 02 02:15:04 PM PDT 24
Finished Jun 02 02:15:05 PM PDT 24
Peak memory 204628 kb
Host smart-abcd946a-5958-4163-8ea3-11b6df0b5bf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1454855166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1454855166
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1758899483
Short name T2111
Test name
Test status
Simulation time 48190325 ps
CPU time 0.72 seconds
Started Jun 02 02:15:03 PM PDT 24
Finished Jun 02 02:15:04 PM PDT 24
Peak memory 204544 kb
Host smart-ef0fb7ad-044e-4023-84c3-4c57417cd078
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1758899483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.1758899483
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3549674673
Short name T262
Test name
Test status
Simulation time 259764007 ps
CPU time 1.68 seconds
Started Jun 02 02:15:04 PM PDT 24
Finished Jun 02 02:15:06 PM PDT 24
Peak memory 204744 kb
Host smart-9d3692bd-44d3-457d-8ce0-10fa917aa26b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3549674673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.3549674673
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.4236636703
Short name T234
Test name
Test status
Simulation time 85526809 ps
CPU time 1.96 seconds
Started Jun 02 02:15:02 PM PDT 24
Finished Jun 02 02:15:05 PM PDT 24
Peak memory 213068 kb
Host smart-c1eecc2d-40c5-41e0-8f17-e136230c519f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4236636703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.4236636703
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1748272354
Short name T280
Test name
Test status
Simulation time 767490924 ps
CPU time 3.26 seconds
Started Jun 02 02:15:07 PM PDT 24
Finished Jun 02 02:15:10 PM PDT 24
Peak memory 204800 kb
Host smart-81e3e590-163c-4eda-ad2f-4ef2a2a35729
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1748272354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.1748272354
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.4126030567
Short name T248
Test name
Test status
Simulation time 143675469 ps
CPU time 3.21 seconds
Started Jun 02 02:14:34 PM PDT 24
Finished Jun 02 02:14:37 PM PDT 24
Peak memory 204844 kb
Host smart-80f37043-dba7-49cc-a07f-23593c281a45
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4126030567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.4126030567
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3041760530
Short name T255
Test name
Test status
Simulation time 496626496 ps
CPU time 7.21 seconds
Started Jun 02 02:14:36 PM PDT 24
Finished Jun 02 02:14:43 PM PDT 24
Peak memory 204772 kb
Host smart-f4edc76d-57ac-4157-8a0c-0f2e9d3b540e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3041760530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3041760530
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.733730412
Short name T2073
Test name
Test status
Simulation time 222329244 ps
CPU time 1.11 seconds
Started Jun 02 02:14:36 PM PDT 24
Finished Jun 02 02:14:38 PM PDT 24
Peak memory 204676 kb
Host smart-6b58517e-9a23-4d40-bc8d-25276dc89c3b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=733730412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.733730412
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2389175803
Short name T265
Test name
Test status
Simulation time 156847453 ps
CPU time 1.81 seconds
Started Jun 02 02:14:35 PM PDT 24
Finished Jun 02 02:14:37 PM PDT 24
Peak memory 212956 kb
Host smart-c485e68c-8986-4585-afdb-268bc96df168
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389175803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.2389175803
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1915327314
Short name T2038
Test name
Test status
Simulation time 93826830 ps
CPU time 1.15 seconds
Started Jun 02 02:14:37 PM PDT 24
Finished Jun 02 02:14:39 PM PDT 24
Peak memory 204800 kb
Host smart-7f63fcde-735d-4876-be3b-9741dbf6fe15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1915327314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1915327314
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3608683219
Short name T2085
Test name
Test status
Simulation time 52745041 ps
CPU time 0.66 seconds
Started Jun 02 02:14:35 PM PDT 24
Finished Jun 02 02:14:36 PM PDT 24
Peak memory 204532 kb
Host smart-4ef6d5ac-ac07-4ffb-a112-eafe293de3bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3608683219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3608683219
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3217210912
Short name T249
Test name
Test status
Simulation time 114294797 ps
CPU time 1.4 seconds
Started Jun 02 02:14:33 PM PDT 24
Finished Jun 02 02:14:35 PM PDT 24
Peak memory 212968 kb
Host smart-db3feb20-7423-4734-abd9-035255832512
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3217210912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3217210912
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1408256211
Short name T2033
Test name
Test status
Simulation time 732089910 ps
CPU time 4.86 seconds
Started Jun 02 02:14:37 PM PDT 24
Finished Jun 02 02:14:42 PM PDT 24
Peak memory 204808 kb
Host smart-4272d069-ddff-4581-8023-dc8c518c9182
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1408256211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1408256211
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1588767905
Short name T261
Test name
Test status
Simulation time 110000445 ps
CPU time 1.19 seconds
Started Jun 02 02:14:33 PM PDT 24
Finished Jun 02 02:14:35 PM PDT 24
Peak memory 204760 kb
Host smart-a2718213-acdc-40ac-825e-ac6f21bf8a19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1588767905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.1588767905
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1059072554
Short name T2133
Test name
Test status
Simulation time 135962792 ps
CPU time 1.74 seconds
Started Jun 02 02:14:35 PM PDT 24
Finished Jun 02 02:14:37 PM PDT 24
Peak memory 213000 kb
Host smart-fa63a6b3-39da-477e-ae11-3769a986859d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1059072554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1059072554
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.4218613773
Short name T283
Test name
Test status
Simulation time 1184205707 ps
CPU time 5.64 seconds
Started Jun 02 02:14:34 PM PDT 24
Finished Jun 02 02:14:40 PM PDT 24
Peak memory 204748 kb
Host smart-0e723226-5b5d-41e2-bee6-e3efbb4ca97e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4218613773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.4218613773
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1806548997
Short name T2076
Test name
Test status
Simulation time 61613000 ps
CPU time 0.72 seconds
Started Jun 02 02:15:01 PM PDT 24
Finished Jun 02 02:15:02 PM PDT 24
Peak memory 204552 kb
Host smart-4340d9bb-d709-4d7d-93ad-8e5a0dfb05a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1806548997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1806548997
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3556909179
Short name T2108
Test name
Test status
Simulation time 44021913 ps
CPU time 0.68 seconds
Started Jun 02 02:15:03 PM PDT 24
Finished Jun 02 02:15:04 PM PDT 24
Peak memory 204532 kb
Host smart-037c0938-87a4-4e49-9df7-5c9d5945f026
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3556909179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3556909179
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1875882155
Short name T99
Test name
Test status
Simulation time 112725449 ps
CPU time 0.86 seconds
Started Jun 02 02:15:03 PM PDT 24
Finished Jun 02 02:15:04 PM PDT 24
Peak memory 204496 kb
Host smart-2adc731f-6f09-4a92-9261-249dfb849973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1875882155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1875882155
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1594082277
Short name T276
Test name
Test status
Simulation time 83160888 ps
CPU time 0.73 seconds
Started Jun 02 02:15:02 PM PDT 24
Finished Jun 02 02:15:03 PM PDT 24
Peak memory 204516 kb
Host smart-efb49970-025f-4ab8-b927-6a502a47795d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1594082277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1594082277
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2582610421
Short name T2062
Test name
Test status
Simulation time 68259923 ps
CPU time 0.68 seconds
Started Jun 02 02:15:05 PM PDT 24
Finished Jun 02 02:15:07 PM PDT 24
Peak memory 204520 kb
Host smart-1f861cc5-7be4-47f5-911b-b29b8ebc413f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2582610421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2582610421
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2537004948
Short name T204
Test name
Test status
Simulation time 51585693 ps
CPU time 0.7 seconds
Started Jun 02 02:15:02 PM PDT 24
Finished Jun 02 02:15:03 PM PDT 24
Peak memory 204564 kb
Host smart-54e24e21-2b9d-4650-b736-3efe0ed41d40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2537004948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2537004948
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1541478078
Short name T277
Test name
Test status
Simulation time 78716745 ps
CPU time 0.73 seconds
Started Jun 02 02:15:01 PM PDT 24
Finished Jun 02 02:15:02 PM PDT 24
Peak memory 204568 kb
Host smart-77fdf26a-7c85-4a2c-9653-65b363edf5d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1541478078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.1541478078
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3945231490
Short name T2052
Test name
Test status
Simulation time 34992907 ps
CPU time 0.63 seconds
Started Jun 02 02:15:12 PM PDT 24
Finished Jun 02 02:15:13 PM PDT 24
Peak memory 204552 kb
Host smart-eccc82f7-5d48-43e4-99c8-ab3e232a4783
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3945231490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3945231490
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1941298538
Short name T2081
Test name
Test status
Simulation time 42752932 ps
CPU time 0.63 seconds
Started Jun 02 02:15:02 PM PDT 24
Finished Jun 02 02:15:03 PM PDT 24
Peak memory 204476 kb
Host smart-3b1fda83-8619-4953-9938-8e2fde88ed26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1941298538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1941298538
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2943958960
Short name T202
Test name
Test status
Simulation time 289753967 ps
CPU time 3.82 seconds
Started Jun 02 02:14:42 PM PDT 24
Finished Jun 02 02:14:46 PM PDT 24
Peak memory 204676 kb
Host smart-df5c5bea-19ca-470f-8844-675a31543d23
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2943958960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2943958960
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3583917786
Short name T2074
Test name
Test status
Simulation time 666621377 ps
CPU time 8.55 seconds
Started Jun 02 02:14:47 PM PDT 24
Finished Jun 02 02:14:56 PM PDT 24
Peak memory 204804 kb
Host smart-06761160-512f-48d6-a852-31bcbdf58374
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3583917786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3583917786
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2654099660
Short name T253
Test name
Test status
Simulation time 103645318 ps
CPU time 0.94 seconds
Started Jun 02 02:14:47 PM PDT 24
Finished Jun 02 02:14:48 PM PDT 24
Peak memory 204496 kb
Host smart-0bcfd803-3377-465b-b889-5963f24c08ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2654099660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2654099660
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.498098030
Short name T236
Test name
Test status
Simulation time 102275240 ps
CPU time 1.93 seconds
Started Jun 02 02:14:47 PM PDT 24
Finished Jun 02 02:14:49 PM PDT 24
Peak memory 213016 kb
Host smart-509012e7-ae86-44b5-9192-dd6bdb2466e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498098030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev
_csr_mem_rw_with_rand_reset.498098030
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1975193300
Short name T246
Test name
Test status
Simulation time 33425978 ps
CPU time 0.82 seconds
Started Jun 02 02:14:42 PM PDT 24
Finished Jun 02 02:14:44 PM PDT 24
Peak memory 204536 kb
Host smart-786a3535-ca94-43a8-afbf-72813abb896d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1975193300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1975193300
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2114678618
Short name T2079
Test name
Test status
Simulation time 35729214 ps
CPU time 0.65 seconds
Started Jun 02 02:14:36 PM PDT 24
Finished Jun 02 02:14:37 PM PDT 24
Peak memory 204532 kb
Host smart-bc3c8bd0-020c-4241-b012-af1699cfcaec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2114678618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.2114678618
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.864646288
Short name T247
Test name
Test status
Simulation time 76290755 ps
CPU time 2.23 seconds
Started Jun 02 02:14:34 PM PDT 24
Finished Jun 02 02:14:36 PM PDT 24
Peak memory 213032 kb
Host smart-28a8749a-618e-469c-966f-217886dd40e9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=864646288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.864646288
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3396512299
Short name T2034
Test name
Test status
Simulation time 108992149 ps
CPU time 2.46 seconds
Started Jun 02 02:14:39 PM PDT 24
Finished Jun 02 02:14:41 PM PDT 24
Peak memory 204684 kb
Host smart-6d62a976-df46-4819-807d-2b120454efb7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3396512299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3396512299
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1526092770
Short name T2129
Test name
Test status
Simulation time 118024219 ps
CPU time 1.16 seconds
Started Jun 02 02:14:40 PM PDT 24
Finished Jun 02 02:14:42 PM PDT 24
Peak memory 204700 kb
Host smart-6bcda709-c037-44e5-a8e5-fb9f0b26af1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1526092770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.1526092770
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1115770062
Short name T2120
Test name
Test status
Simulation time 224511797 ps
CPU time 3.12 seconds
Started Jun 02 02:14:34 PM PDT 24
Finished Jun 02 02:14:38 PM PDT 24
Peak memory 204824 kb
Host smart-f25ba128-2031-448b-b774-e2fb8a8a4ea8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1115770062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1115770062
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1683996775
Short name T199
Test name
Test status
Simulation time 291806066 ps
CPU time 2.53 seconds
Started Jun 02 02:14:36 PM PDT 24
Finished Jun 02 02:14:38 PM PDT 24
Peak memory 204752 kb
Host smart-b08bac1c-3aac-4418-973c-fec28fa34fd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1683996775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1683996775
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3032150398
Short name T2077
Test name
Test status
Simulation time 57520715 ps
CPU time 0.73 seconds
Started Jun 02 02:15:04 PM PDT 24
Finished Jun 02 02:15:05 PM PDT 24
Peak memory 204528 kb
Host smart-c2715c52-c6d6-4751-a98c-9abef7f172b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3032150398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3032150398
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2146729673
Short name T2055
Test name
Test status
Simulation time 63779720 ps
CPU time 0.7 seconds
Started Jun 02 02:15:09 PM PDT 24
Finished Jun 02 02:15:10 PM PDT 24
Peak memory 204524 kb
Host smart-927c7380-ec3e-4882-96d5-72ba1cfc4ea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2146729673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2146729673
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2301564528
Short name T274
Test name
Test status
Simulation time 64195049 ps
CPU time 0.72 seconds
Started Jun 02 02:15:08 PM PDT 24
Finished Jun 02 02:15:09 PM PDT 24
Peak memory 204556 kb
Host smart-a92b236b-b78f-400e-acf8-38fed6ba8c98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2301564528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2301564528
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1354150006
Short name T2109
Test name
Test status
Simulation time 66812884 ps
CPU time 0.74 seconds
Started Jun 02 02:15:08 PM PDT 24
Finished Jun 02 02:15:09 PM PDT 24
Peak memory 204496 kb
Host smart-50abf58d-f4e9-472c-9f96-6a44ab4f4a83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1354150006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1354150006
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2170085899
Short name T2112
Test name
Test status
Simulation time 32233292 ps
CPU time 0.68 seconds
Started Jun 02 02:15:07 PM PDT 24
Finished Jun 02 02:15:09 PM PDT 24
Peak memory 204484 kb
Host smart-25b33ac6-f719-460d-9c5e-69d34277562f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2170085899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2170085899
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3490606226
Short name T2102
Test name
Test status
Simulation time 78112462 ps
CPU time 0.73 seconds
Started Jun 02 02:15:07 PM PDT 24
Finished Jun 02 02:15:08 PM PDT 24
Peak memory 204544 kb
Host smart-459d326c-bf6d-4c7b-a40f-91aae06a6079
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3490606226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3490606226
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.4023190804
Short name T268
Test name
Test status
Simulation time 36219759 ps
CPU time 0.67 seconds
Started Jun 02 02:15:06 PM PDT 24
Finished Jun 02 02:15:07 PM PDT 24
Peak memory 204480 kb
Host smart-78711215-fcbd-4f6f-b3e1-f8cf84123578
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4023190804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.4023190804
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3398996394
Short name T2117
Test name
Test status
Simulation time 64320259 ps
CPU time 0.7 seconds
Started Jun 02 02:15:09 PM PDT 24
Finished Jun 02 02:15:10 PM PDT 24
Peak memory 204520 kb
Host smart-9a93af2d-c7ac-4cb2-85bf-7c61521910ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3398996394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3398996394
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1333563688
Short name T2063
Test name
Test status
Simulation time 51241551 ps
CPU time 0.69 seconds
Started Jun 02 02:15:06 PM PDT 24
Finished Jun 02 02:15:08 PM PDT 24
Peak memory 204544 kb
Host smart-1b29e523-3237-4a2a-8334-c487551218a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1333563688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1333563688
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3510129478
Short name T254
Test name
Test status
Simulation time 345771087 ps
CPU time 3.59 seconds
Started Jun 02 02:14:47 PM PDT 24
Finished Jun 02 02:14:52 PM PDT 24
Peak memory 204816 kb
Host smart-26b3b748-093d-4900-8bc5-f41dc8dc5e28
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3510129478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3510129478
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1889054710
Short name T2075
Test name
Test status
Simulation time 704697305 ps
CPU time 4.82 seconds
Started Jun 02 02:14:47 PM PDT 24
Finished Jun 02 02:14:52 PM PDT 24
Peak memory 204772 kb
Host smart-271b6205-09b3-4dbf-be74-e32c78b91f85
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1889054710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1889054710
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3541253756
Short name T2095
Test name
Test status
Simulation time 78818715 ps
CPU time 0.95 seconds
Started Jun 02 02:14:42 PM PDT 24
Finished Jun 02 02:14:43 PM PDT 24
Peak memory 204540 kb
Host smart-5de4b79b-984d-4ec4-a0f8-7c4a20f88ee2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3541253756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3541253756
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.877287949
Short name T231
Test name
Test status
Simulation time 81945985 ps
CPU time 1.75 seconds
Started Jun 02 02:14:40 PM PDT 24
Finished Jun 02 02:14:42 PM PDT 24
Peak memory 212988 kb
Host smart-3c932df0-50ab-4fed-ada2-1dc35517ea19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877287949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev
_csr_mem_rw_with_rand_reset.877287949
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1117343491
Short name T2088
Test name
Test status
Simulation time 55542854 ps
CPU time 0.7 seconds
Started Jun 02 02:14:47 PM PDT 24
Finished Jun 02 02:14:48 PM PDT 24
Peak memory 204556 kb
Host smart-ca73cf03-00b8-43eb-befb-22e53b1e2221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1117343491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1117343491
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1792731801
Short name T2103
Test name
Test status
Simulation time 86703724 ps
CPU time 2.3 seconds
Started Jun 02 02:14:41 PM PDT 24
Finished Jun 02 02:14:44 PM PDT 24
Peak memory 213044 kb
Host smart-a4ae4e3a-5069-48cc-af90-81a32bd43a0c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1792731801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1792731801
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3654047377
Short name T2068
Test name
Test status
Simulation time 154269155 ps
CPU time 2.51 seconds
Started Jun 02 02:14:40 PM PDT 24
Finished Jun 02 02:14:43 PM PDT 24
Peak memory 204776 kb
Host smart-11dfeb98-cc54-4243-851c-5e6427c9db1b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3654047377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.3654047377
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3906916882
Short name T2039
Test name
Test status
Simulation time 293730052 ps
CPU time 1.89 seconds
Started Jun 02 02:14:41 PM PDT 24
Finished Jun 02 02:14:44 PM PDT 24
Peak memory 204832 kb
Host smart-d0af2241-1405-41a9-abcc-50a43c67a35e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3906916882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3906916882
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3877684228
Short name T230
Test name
Test status
Simulation time 133023841 ps
CPU time 1.95 seconds
Started Jun 02 02:14:47 PM PDT 24
Finished Jun 02 02:14:50 PM PDT 24
Peak memory 220436 kb
Host smart-5c638660-43ad-46d7-8e2a-e10fb87885fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3877684228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3877684228
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1956643828
Short name T281
Test name
Test status
Simulation time 405698327 ps
CPU time 2.92 seconds
Started Jun 02 02:14:42 PM PDT 24
Finished Jun 02 02:14:45 PM PDT 24
Peak memory 204784 kb
Host smart-75caf04d-2e81-4db0-bfa4-5e24ea53cf44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1956643828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1956643828
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1118759881
Short name T2056
Test name
Test status
Simulation time 39964613 ps
CPU time 0.68 seconds
Started Jun 02 02:15:08 PM PDT 24
Finished Jun 02 02:15:09 PM PDT 24
Peak memory 204548 kb
Host smart-4a01120b-1ea6-4005-a7ca-f2ca54081668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1118759881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.1118759881
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.919759115
Short name T2113
Test name
Test status
Simulation time 34847446 ps
CPU time 0.65 seconds
Started Jun 02 02:15:06 PM PDT 24
Finished Jun 02 02:15:08 PM PDT 24
Peak memory 204536 kb
Host smart-c74ec1f0-181a-4b1e-9296-cf55e84c034b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=919759115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.919759115
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2572976610
Short name T2086
Test name
Test status
Simulation time 97973974 ps
CPU time 0.76 seconds
Started Jun 02 02:15:06 PM PDT 24
Finished Jun 02 02:15:07 PM PDT 24
Peak memory 204500 kb
Host smart-0785bc9d-f5d5-4424-b61e-474adf53b1f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2572976610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2572976610
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.270983347
Short name T2042
Test name
Test status
Simulation time 49146938 ps
CPU time 0.71 seconds
Started Jun 02 02:15:04 PM PDT 24
Finished Jun 02 02:15:06 PM PDT 24
Peak memory 204520 kb
Host smart-2a8bcd29-978a-48fd-88d1-35c5e1aee957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=270983347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.270983347
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.392552693
Short name T205
Test name
Test status
Simulation time 76578983 ps
CPU time 0.74 seconds
Started Jun 02 02:15:05 PM PDT 24
Finished Jun 02 02:15:06 PM PDT 24
Peak memory 204548 kb
Host smart-0f251830-147d-429f-95b1-d8688657ce80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=392552693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.392552693
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.323949268
Short name T2098
Test name
Test status
Simulation time 38092602 ps
CPU time 0.7 seconds
Started Jun 02 02:15:08 PM PDT 24
Finished Jun 02 02:15:09 PM PDT 24
Peak memory 204504 kb
Host smart-41af5823-9a5c-4878-9fe5-0d07a278d517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=323949268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.323949268
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3539159044
Short name T2105
Test name
Test status
Simulation time 70835493 ps
CPU time 0.74 seconds
Started Jun 02 02:15:09 PM PDT 24
Finished Jun 02 02:15:10 PM PDT 24
Peak memory 204520 kb
Host smart-3d533629-2315-4a27-bfbd-fabaa442b6df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3539159044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3539159044
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.335246502
Short name T273
Test name
Test status
Simulation time 39638704 ps
CPU time 0.72 seconds
Started Jun 02 02:15:10 PM PDT 24
Finished Jun 02 02:15:11 PM PDT 24
Peak memory 204508 kb
Host smart-5844af2d-2b89-4878-b479-57466f4ba139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=335246502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.335246502
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.258556678
Short name T224
Test name
Test status
Simulation time 188629083 ps
CPU time 2.13 seconds
Started Jun 02 02:14:43 PM PDT 24
Finished Jun 02 02:14:46 PM PDT 24
Peak memory 213000 kb
Host smart-18736f1c-e925-43d5-8eeb-14f07da93055
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258556678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.258556678
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.874107213
Short name T2065
Test name
Test status
Simulation time 105413288 ps
CPU time 1.16 seconds
Started Jun 02 02:14:47 PM PDT 24
Finished Jun 02 02:14:49 PM PDT 24
Peak memory 204856 kb
Host smart-af1919a1-4a98-4d58-af1a-c34f964948c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=874107213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.874107213
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1851701610
Short name T98
Test name
Test status
Simulation time 37069559 ps
CPU time 0.66 seconds
Started Jun 02 02:14:46 PM PDT 24
Finished Jun 02 02:14:47 PM PDT 24
Peak memory 204528 kb
Host smart-9d95e35d-b2cd-4125-9ebf-e9cd300b4ab1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1851701610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1851701610
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2216978997
Short name T2070
Test name
Test status
Simulation time 162611107 ps
CPU time 1.67 seconds
Started Jun 02 02:14:48 PM PDT 24
Finished Jun 02 02:14:50 PM PDT 24
Peak memory 204716 kb
Host smart-7f2e17ba-5cac-4b85-b503-051cf03d2363
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2216978997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.2216978997
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.4164474811
Short name T2124
Test name
Test status
Simulation time 187306298 ps
CPU time 1.98 seconds
Started Jun 02 02:14:41 PM PDT 24
Finished Jun 02 02:14:43 PM PDT 24
Peak memory 212964 kb
Host smart-99b990ee-c943-46a6-b4f6-36c8ef50efc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4164474811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.4164474811
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3634350481
Short name T284
Test name
Test status
Simulation time 1979328544 ps
CPU time 5.95 seconds
Started Jun 02 02:14:41 PM PDT 24
Finished Jun 02 02:14:48 PM PDT 24
Peak memory 204732 kb
Host smart-93358c80-7e9b-4e09-8262-f461e7aec86a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3634350481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3634350481
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.116314496
Short name T2096
Test name
Test status
Simulation time 81996911 ps
CPU time 1.67 seconds
Started Jun 02 02:14:45 PM PDT 24
Finished Jun 02 02:14:47 PM PDT 24
Peak memory 213028 kb
Host smart-b122ec51-6ff9-433b-b51a-aef5215a4056
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116314496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev
_csr_mem_rw_with_rand_reset.116314496
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4280515686
Short name T2114
Test name
Test status
Simulation time 81892968 ps
CPU time 1.02 seconds
Started Jun 02 02:14:48 PM PDT 24
Finished Jun 02 02:14:50 PM PDT 24
Peak memory 204700 kb
Host smart-ee96758d-5c96-40e7-a466-ff8c58109c4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4280515686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.4280515686
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3394015201
Short name T278
Test name
Test status
Simulation time 31700405 ps
CPU time 0.74 seconds
Started Jun 02 02:14:49 PM PDT 24
Finished Jun 02 02:14:50 PM PDT 24
Peak memory 204496 kb
Host smart-cda4dc5b-d7e0-4c8b-8460-6ba19da5daf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3394015201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.3394015201
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3149816201
Short name T2046
Test name
Test status
Simulation time 66130896 ps
CPU time 1.06 seconds
Started Jun 02 02:14:50 PM PDT 24
Finished Jun 02 02:14:51 PM PDT 24
Peak memory 204828 kb
Host smart-a54b00ef-c926-461f-b96e-da1acc3a0d5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3149816201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3149816201
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2300026433
Short name T2122
Test name
Test status
Simulation time 153604669 ps
CPU time 2.16 seconds
Started Jun 02 02:14:46 PM PDT 24
Finished Jun 02 02:14:48 PM PDT 24
Peak memory 213028 kb
Host smart-a33e4f5d-f479-48fd-923d-829e2aa1da01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2300026433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2300026433
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1807683134
Short name T285
Test name
Test status
Simulation time 1222085993 ps
CPU time 5.81 seconds
Started Jun 02 02:14:51 PM PDT 24
Finished Jun 02 02:14:57 PM PDT 24
Peak memory 204812 kb
Host smart-f6001c19-f63d-44fb-8af4-0c44e2f9f6c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1807683134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.1807683134
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.474270492
Short name T2082
Test name
Test status
Simulation time 88895798 ps
CPU time 1.53 seconds
Started Jun 02 02:14:48 PM PDT 24
Finished Jun 02 02:14:50 PM PDT 24
Peak memory 212964 kb
Host smart-b926ff89-7196-45fe-8356-480f1d9a4c24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474270492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev
_csr_mem_rw_with_rand_reset.474270492
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3756411209
Short name T2040
Test name
Test status
Simulation time 91506443 ps
CPU time 1.03 seconds
Started Jun 02 02:14:48 PM PDT 24
Finished Jun 02 02:14:50 PM PDT 24
Peak memory 204760 kb
Host smart-2a193c89-3b6e-4db4-844f-4bc9a37eee32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3756411209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3756411209
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1858410174
Short name T2125
Test name
Test status
Simulation time 36191093 ps
CPU time 0.75 seconds
Started Jun 02 02:14:49 PM PDT 24
Finished Jun 02 02:14:50 PM PDT 24
Peak memory 204500 kb
Host smart-c8f2db10-3986-4915-a778-c843c27dd458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1858410174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1858410174
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2756742756
Short name T260
Test name
Test status
Simulation time 278631318 ps
CPU time 1.79 seconds
Started Jun 02 02:14:47 PM PDT 24
Finished Jun 02 02:14:49 PM PDT 24
Peak memory 204812 kb
Host smart-3cc03c89-9667-4767-88e8-420012e8f4fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2756742756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2756742756
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2951100677
Short name T2119
Test name
Test status
Simulation time 230436875 ps
CPU time 2.5 seconds
Started Jun 02 02:14:48 PM PDT 24
Finished Jun 02 02:14:51 PM PDT 24
Peak memory 212968 kb
Host smart-1c617bf2-8265-4724-a659-0ca33453ef2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2951100677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2951100677
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2812899523
Short name T2100
Test name
Test status
Simulation time 1288818538 ps
CPU time 5.13 seconds
Started Jun 02 02:14:47 PM PDT 24
Finished Jun 02 02:14:53 PM PDT 24
Peak memory 204740 kb
Host smart-1408ee75-2aaa-4a21-aa65-25e44e032e29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2812899523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.2812899523
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.4222538192
Short name T2060
Test name
Test status
Simulation time 96379122 ps
CPU time 1.22 seconds
Started Jun 02 02:14:47 PM PDT 24
Finished Jun 02 02:14:49 PM PDT 24
Peak memory 215296 kb
Host smart-3b14ff33-0bf3-4806-b864-c05490dc6f5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222538192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.4222538192
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2194244618
Short name T264
Test name
Test status
Simulation time 71223517 ps
CPU time 0.86 seconds
Started Jun 02 02:14:48 PM PDT 24
Finished Jun 02 02:14:49 PM PDT 24
Peak memory 204528 kb
Host smart-79e13cc4-5dad-4bca-9826-53c3aa0e561c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2194244618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2194244618
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1579045869
Short name T206
Test name
Test status
Simulation time 50122110 ps
CPU time 0.69 seconds
Started Jun 02 02:14:45 PM PDT 24
Finished Jun 02 02:14:46 PM PDT 24
Peak memory 204544 kb
Host smart-271a5d6b-a49a-49f2-a74a-765f681f5d4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1579045869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1579045869
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2794354351
Short name T2121
Test name
Test status
Simulation time 133738303 ps
CPU time 1.66 seconds
Started Jun 02 02:14:45 PM PDT 24
Finished Jun 02 02:14:47 PM PDT 24
Peak memory 204772 kb
Host smart-911eb5a3-2a54-4dd8-a45e-dfb85e6c24ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2794354351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.2794354351
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1226926542
Short name T2083
Test name
Test status
Simulation time 171622238 ps
CPU time 2.08 seconds
Started Jun 02 02:14:44 PM PDT 24
Finished Jun 02 02:14:47 PM PDT 24
Peak memory 220688 kb
Host smart-9f4321c1-a052-46c0-a2b8-b89e6be8b523
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1226926542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1226926542
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.4194043563
Short name T200
Test name
Test status
Simulation time 377094835 ps
CPU time 2.6 seconds
Started Jun 02 02:14:45 PM PDT 24
Finished Jun 02 02:14:48 PM PDT 24
Peak memory 204788 kb
Host smart-920a97e4-1182-4398-97b7-81a3df88435d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4194043563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.4194043563
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2676653340
Short name T239
Test name
Test status
Simulation time 67600138 ps
CPU time 1.86 seconds
Started Jun 02 02:14:54 PM PDT 24
Finished Jun 02 02:14:56 PM PDT 24
Peak memory 212992 kb
Host smart-4e753410-19ea-4b46-8224-23a728156506
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676653340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.2676653340
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.696020392
Short name T2080
Test name
Test status
Simulation time 85551336 ps
CPU time 0.87 seconds
Started Jun 02 02:14:51 PM PDT 24
Finished Jun 02 02:14:53 PM PDT 24
Peak memory 204572 kb
Host smart-d25eac4b-ca45-4977-acd7-c8fd295efd7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=696020392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.696020392
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.266974429
Short name T2041
Test name
Test status
Simulation time 44560191 ps
CPU time 0.65 seconds
Started Jun 02 02:14:49 PM PDT 24
Finished Jun 02 02:14:50 PM PDT 24
Peak memory 204460 kb
Host smart-53e34709-ad9a-41a2-a1d5-5f0da285e693
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=266974429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.266974429
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3178652815
Short name T2090
Test name
Test status
Simulation time 236990306 ps
CPU time 1.85 seconds
Started Jun 02 02:14:50 PM PDT 24
Finished Jun 02 02:14:52 PM PDT 24
Peak memory 204788 kb
Host smart-1674d5f2-15d6-46c9-8d7a-c6b43c1149fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3178652815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3178652815
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3977206529
Short name T228
Test name
Test status
Simulation time 127998554 ps
CPU time 1.9 seconds
Started Jun 02 02:14:47 PM PDT 24
Finished Jun 02 02:14:50 PM PDT 24
Peak memory 213000 kb
Host smart-bc89b55c-71a9-4518-b4e9-1ffe119ed28a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3977206529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3977206529
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3796910049
Short name T2128
Test name
Test status
Simulation time 415453975 ps
CPU time 2.98 seconds
Started Jun 02 02:14:48 PM PDT 24
Finished Jun 02 02:14:52 PM PDT 24
Peak memory 204744 kb
Host smart-f059cd96-8b17-4791-86be-7e0daba1d81a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3796910049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3796910049
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.2979873022
Short name T1555
Test name
Test status
Simulation time 10145336036 ps
CPU time 14.34 seconds
Started Jun 02 03:26:16 PM PDT 24
Finished Jun 02 03:26:30 PM PDT 24
Peak memory 205708 kb
Host smart-a1cbb542-2b94-456d-849d-57c5af75a7ee
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2979873022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.2979873022
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.798306225
Short name T1119
Test name
Test status
Simulation time 10068566662 ps
CPU time 13.91 seconds
Started Jun 02 03:26:13 PM PDT 24
Finished Jun 02 03:26:28 PM PDT 24
Peak memory 205684 kb
Host smart-cc93febe-ddb7-410f-8d53-4aed7b94b4af
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=798306225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.798306225
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.661575001
Short name T865
Test name
Test status
Simulation time 10058607321 ps
CPU time 13.37 seconds
Started Jun 02 03:26:12 PM PDT 24
Finished Jun 02 03:26:26 PM PDT 24
Peak memory 205932 kb
Host smart-72382023-66fe-4095-a8e7-eb4b9db3ca7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66157
5001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.661575001
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.3199374684
Short name T1657
Test name
Test status
Simulation time 13666797909 ps
CPU time 21.45 seconds
Started Jun 02 03:25:54 PM PDT 24
Finished Jun 02 03:26:16 PM PDT 24
Peak memory 205652 kb
Host smart-4eb36d20-cfff-402f-bbb8-ada309dfd746
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3199374684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.3199374684
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.42242168
Short name T1133
Test name
Test status
Simulation time 23291306039 ps
CPU time 26.01 seconds
Started Jun 02 03:25:54 PM PDT 24
Finished Jun 02 03:26:20 PM PDT 24
Peak memory 205788 kb
Host smart-0ca7376f-e968-4d09-83d9-af12228fba40
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=42242168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.42242168
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.3790685030
Short name T1073
Test name
Test status
Simulation time 10055725099 ps
CPU time 13.13 seconds
Started Jun 02 03:25:55 PM PDT 24
Finished Jun 02 03:26:09 PM PDT 24
Peak memory 205900 kb
Host smart-9cf97111-9387-44fe-b76d-c7b2f3fd14e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37906
85030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.3790685030
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.769382710
Short name T1877
Test name
Test status
Simulation time 10075270475 ps
CPU time 14.38 seconds
Started Jun 02 03:25:56 PM PDT 24
Finished Jun 02 03:26:11 PM PDT 24
Peak memory 205640 kb
Host smart-e5360965-b9be-4171-a981-96d664f8a310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76938
2710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.769382710
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.3883470476
Short name T79
Test name
Test status
Simulation time 10363185115 ps
CPU time 14.3 seconds
Started Jun 02 03:25:57 PM PDT 24
Finished Jun 02 03:26:12 PM PDT 24
Peak memory 205728 kb
Host smart-26ce648d-ca47-4bf4-a7fd-48c33e9ddaba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38834
70476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.3883470476
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.233910137
Short name T210
Test name
Test status
Simulation time 10047093914 ps
CPU time 14.57 seconds
Started Jun 02 03:25:57 PM PDT 24
Finished Jun 02 03:26:12 PM PDT 24
Peak memory 205692 kb
Host smart-8d69a1b8-d703-44fe-80c0-618861f20088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23391
0137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.233910137
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.1124280405
Short name T89
Test name
Test status
Simulation time 10051922057 ps
CPU time 13.29 seconds
Started Jun 02 03:25:59 PM PDT 24
Finished Jun 02 03:26:13 PM PDT 24
Peak memory 205688 kb
Host smart-4f4ad208-9379-43b5-af87-92655240d2b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11242
80405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1124280405
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.911692521
Short name T1835
Test name
Test status
Simulation time 10891189812 ps
CPU time 15.56 seconds
Started Jun 02 03:25:56 PM PDT 24
Finished Jun 02 03:26:13 PM PDT 24
Peak memory 205768 kb
Host smart-1bf64765-62ad-448b-a26b-96deb7043dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91169
2521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.911692521
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.3831224340
Short name T914
Test name
Test status
Simulation time 10181915600 ps
CPU time 16.64 seconds
Started Jun 02 03:26:00 PM PDT 24
Finished Jun 02 03:26:17 PM PDT 24
Peak memory 205748 kb
Host smart-bbe5b0a5-ca0b-4a34-bbee-c996cd35c44e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38312
24340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.3831224340
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1236241630
Short name T1315
Test name
Test status
Simulation time 10129389906 ps
CPU time 12.98 seconds
Started Jun 02 03:26:13 PM PDT 24
Finished Jun 02 03:26:26 PM PDT 24
Peak memory 205636 kb
Host smart-2f70560c-9273-4c85-ac62-338d4f02d76d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12362
41630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1236241630
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.1558041149
Short name T629
Test name
Test status
Simulation time 10061389395 ps
CPU time 13.67 seconds
Started Jun 02 03:26:14 PM PDT 24
Finished Jun 02 03:26:28 PM PDT 24
Peak memory 205704 kb
Host smart-f941421b-6ad5-4713-a9f5-42d2f17cf386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15580
41149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.1558041149
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2784877137
Short name T1658
Test name
Test status
Simulation time 10142187328 ps
CPU time 12.39 seconds
Started Jun 02 03:26:01 PM PDT 24
Finished Jun 02 03:26:14 PM PDT 24
Peak memory 205704 kb
Host smart-dd97bb41-ae51-4eca-bf17-20cf6ea3d0ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27848
77137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2784877137
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.2273409742
Short name T1640
Test name
Test status
Simulation time 10194939623 ps
CPU time 14.24 seconds
Started Jun 02 03:25:59 PM PDT 24
Finished Jun 02 03:26:13 PM PDT 24
Peak memory 205760 kb
Host smart-82ed3cb3-7574-433a-b67d-fdaa62b87e4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22734
09742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.2273409742
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.3761031578
Short name T1202
Test name
Test status
Simulation time 13240001619 ps
CPU time 15.5 seconds
Started Jun 02 03:25:57 PM PDT 24
Finished Jun 02 03:26:14 PM PDT 24
Peak memory 205716 kb
Host smart-223c80f9-867b-4822-a327-0f9d205ea6ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37610
31578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.3761031578
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2713441299
Short name T731
Test name
Test status
Simulation time 10100927846 ps
CPU time 14.55 seconds
Started Jun 02 03:26:00 PM PDT 24
Finished Jun 02 03:26:15 PM PDT 24
Peak memory 205656 kb
Host smart-7457f95b-4024-44ac-ab62-c3644adea473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27134
41299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2713441299
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.3728660260
Short name T1468
Test name
Test status
Simulation time 23755202175 ps
CPU time 152.23 seconds
Started Jun 02 03:25:57 PM PDT 24
Finished Jun 02 03:28:30 PM PDT 24
Peak memory 205704 kb
Host smart-a4428df1-20d6-4182-9969-c9f9624e41a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37286
60260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.3728660260
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2024593123
Short name T354
Test name
Test status
Simulation time 10056305218 ps
CPU time 13.45 seconds
Started Jun 02 03:25:59 PM PDT 24
Finished Jun 02 03:26:13 PM PDT 24
Peak memory 205768 kb
Host smart-5a1321bc-2a59-428f-a73f-cf9593001212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20245
93123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2024593123
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.60305932
Short name T774
Test name
Test status
Simulation time 10136573004 ps
CPU time 14.52 seconds
Started Jun 02 03:26:06 PM PDT 24
Finished Jun 02 03:26:21 PM PDT 24
Peak memory 205632 kb
Host smart-3bfbeecd-b5a1-4e40-b486-8a876f62ce99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60305
932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.60305932
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.2357974000
Short name T510
Test name
Test status
Simulation time 10065251920 ps
CPU time 14.59 seconds
Started Jun 02 03:26:02 PM PDT 24
Finished Jun 02 03:26:17 PM PDT 24
Peak memory 205652 kb
Host smart-168300de-c8a6-4dd8-9ffa-9e030c313593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23579
74000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.2357974000
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.432214088
Short name T1606
Test name
Test status
Simulation time 10077864407 ps
CPU time 13.07 seconds
Started Jun 02 03:26:03 PM PDT 24
Finished Jun 02 03:26:17 PM PDT 24
Peak memory 205676 kb
Host smart-b76bc2fc-869f-4e1a-9c1f-b92f1508a0cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43221
4088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.432214088
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.1144602108
Short name T1002
Test name
Test status
Simulation time 10093554666 ps
CPU time 13.55 seconds
Started Jun 02 03:26:06 PM PDT 24
Finished Jun 02 03:26:20 PM PDT 24
Peak memory 205692 kb
Host smart-3f33d834-aa4c-4b68-b510-f719b2eee2e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11446
02108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.1144602108
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.771094507
Short name T1058
Test name
Test status
Simulation time 10046379325 ps
CPU time 17.6 seconds
Started Jun 02 03:26:14 PM PDT 24
Finished Jun 02 03:26:32 PM PDT 24
Peak memory 205740 kb
Host smart-8838e7fd-f036-42a8-b6c8-16dce9babfc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77109
4507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.771094507
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.4256394885
Short name T1160
Test name
Test status
Simulation time 29912035797 ps
CPU time 56.76 seconds
Started Jun 02 03:26:05 PM PDT 24
Finished Jun 02 03:27:02 PM PDT 24
Peak memory 205784 kb
Host smart-f5574db5-6ad2-4177-8012-3a0d41697e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42563
94885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.4256394885
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1936941313
Short name T706
Test name
Test status
Simulation time 10042756523 ps
CPU time 15.08 seconds
Started Jun 02 03:26:05 PM PDT 24
Finished Jun 02 03:26:21 PM PDT 24
Peak memory 205832 kb
Host smart-da96bbbc-4d6f-4876-bca7-9c9ac0161e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19369
41313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1936941313
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.2481366997
Short name T1387
Test name
Test status
Simulation time 10105603869 ps
CPU time 14 seconds
Started Jun 02 03:26:02 PM PDT 24
Finished Jun 02 03:26:17 PM PDT 24
Peak memory 205704 kb
Host smart-7044a393-ab17-40a4-9202-d533fad16647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24813
66997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.2481366997
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.895533748
Short name T1683
Test name
Test status
Simulation time 32765057105 ps
CPU time 630.77 seconds
Started Jun 02 03:26:06 PM PDT 24
Finished Jun 02 03:36:38 PM PDT 24
Peak memory 205696 kb
Host smart-ea006f87-8e29-4f78-89f3-6544c4477305
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=895533748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.895533748
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.2751452798
Short name T193
Test name
Test status
Simulation time 18195840068 ps
CPU time 226.99 seconds
Started Jun 02 03:26:02 PM PDT 24
Finished Jun 02 03:29:50 PM PDT 24
Peak memory 205772 kb
Host smart-6cc0346e-80e1-4ae0-8be5-c50b6f5885e5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2751452798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.2751452798
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.2761754945
Short name T339
Test name
Test status
Simulation time 23664842164 ps
CPU time 108.32 seconds
Started Jun 02 03:26:10 PM PDT 24
Finished Jun 02 03:27:59 PM PDT 24
Peak memory 205804 kb
Host smart-cb8a25f0-9d69-46ad-be12-ea1600988604
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2761754945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.2761754945
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.381487093
Short name T1142
Test name
Test status
Simulation time 10090307038 ps
CPU time 13.57 seconds
Started Jun 02 03:26:06 PM PDT 24
Finished Jun 02 03:26:20 PM PDT 24
Peak memory 205636 kb
Host smart-a0f155ce-5e72-4a8d-8de1-5189bf10d563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38148
7093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.381487093
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.2834964978
Short name T1116
Test name
Test status
Simulation time 10065772334 ps
CPU time 13.6 seconds
Started Jun 02 03:26:09 PM PDT 24
Finished Jun 02 03:26:23 PM PDT 24
Peak memory 205704 kb
Host smart-1c076289-a7f4-40a8-9e00-d0a210ff6bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28349
64978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.2834964978
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2269060847
Short name T196
Test name
Test status
Simulation time 298278506 ps
CPU time 1.14 seconds
Started Jun 02 03:26:12 PM PDT 24
Finished Jun 02 03:26:13 PM PDT 24
Peak memory 221736 kb
Host smart-42f24a64-44cd-4815-8fd4-70aeeb996239
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2269060847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2269060847
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.869368663
Short name T1296
Test name
Test status
Simulation time 10050990989 ps
CPU time 14.94 seconds
Started Jun 02 03:26:07 PM PDT 24
Finished Jun 02 03:26:22 PM PDT 24
Peak memory 205680 kb
Host smart-709eff94-b39e-48c4-914c-918c5f723cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86936
8663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.869368663
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1962316593
Short name T1559
Test name
Test status
Simulation time 10187209073 ps
CPU time 14.37 seconds
Started Jun 02 03:25:54 PM PDT 24
Finished Jun 02 03:26:09 PM PDT 24
Peak memory 205804 kb
Host smart-31f2c924-f10d-4af1-b61f-18da75c9f47d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19623
16593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1962316593
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.2122969143
Short name T1687
Test name
Test status
Simulation time 10102881094 ps
CPU time 16.17 seconds
Started Jun 02 03:26:07 PM PDT 24
Finished Jun 02 03:26:24 PM PDT 24
Peak memory 205664 kb
Host smart-171e7a49-5247-4512-a697-77602d21294c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21229
69143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.2122969143
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.1648515108
Short name T1907
Test name
Test status
Simulation time 10085117693 ps
CPU time 13.53 seconds
Started Jun 02 03:26:09 PM PDT 24
Finished Jun 02 03:26:23 PM PDT 24
Peak memory 205792 kb
Host smart-15d6339e-22d0-494e-a7b4-5b626dd77d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16485
15108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.1648515108
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.1824222337
Short name T1601
Test name
Test status
Simulation time 16119944032 ps
CPU time 175.09 seconds
Started Jun 02 03:26:08 PM PDT 24
Finished Jun 02 03:29:03 PM PDT 24
Peak memory 205704 kb
Host smart-7f729f88-e364-48b9-9170-aa338201e7de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18242
22337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.1824222337
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.1944861828
Short name T2015
Test name
Test status
Simulation time 25218928650 ps
CPU time 130.41 seconds
Started Jun 02 03:26:08 PM PDT 24
Finished Jun 02 03:28:19 PM PDT 24
Peak memory 205676 kb
Host smart-9390c79a-238b-4ef7-af5d-22694615565c
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944861828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_
traffic.1944861828
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.1576562727
Short name T1322
Test name
Test status
Simulation time 10180946511 ps
CPU time 13.06 seconds
Started Jun 02 03:26:28 PM PDT 24
Finished Jun 02 03:26:42 PM PDT 24
Peak memory 205664 kb
Host smart-b7ff75cd-8362-43ee-b249-817774d3c353
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1576562727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.1576562727
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.829869393
Short name T18
Test name
Test status
Simulation time 10063414593 ps
CPU time 12.98 seconds
Started Jun 02 03:26:27 PM PDT 24
Finished Jun 02 03:26:41 PM PDT 24
Peak memory 205576 kb
Host smart-14fd17c1-3539-4e43-b4ae-e7714abec1a7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=829869393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.829869393
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.3154105491
Short name T1430
Test name
Test status
Simulation time 10089265024 ps
CPU time 17.23 seconds
Started Jun 02 03:26:28 PM PDT 24
Finished Jun 02 03:26:46 PM PDT 24
Peak memory 205724 kb
Host smart-f75b4816-2b8b-43aa-8a75-9bb7c010d550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31541
05491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.3154105491
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.2818023480
Short name T1441
Test name
Test status
Simulation time 13580163073 ps
CPU time 16.69 seconds
Started Jun 02 03:26:12 PM PDT 24
Finished Jun 02 03:26:29 PM PDT 24
Peak memory 205688 kb
Host smart-6d603070-1bff-446c-885b-5203617bd3f3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2818023480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.2818023480
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.3337131680
Short name T1003
Test name
Test status
Simulation time 23303731312 ps
CPU time 24.01 seconds
Started Jun 02 03:26:12 PM PDT 24
Finished Jun 02 03:26:37 PM PDT 24
Peak memory 205680 kb
Host smart-2d775505-1ccd-4156-9db4-b61aa7b641c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3337131680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.3337131680
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.3312663066
Short name T1186
Test name
Test status
Simulation time 10059158820 ps
CPU time 16.12 seconds
Started Jun 02 03:26:17 PM PDT 24
Finished Jun 02 03:26:34 PM PDT 24
Peak memory 205760 kb
Host smart-4f0dadd2-8abc-480a-a7ea-95a7f8329fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33126
63066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.3312663066
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.141521315
Short name T169
Test name
Test status
Simulation time 10974086079 ps
CPU time 16.06 seconds
Started Jun 02 03:26:18 PM PDT 24
Finished Jun 02 03:26:35 PM PDT 24
Peak memory 205696 kb
Host smart-de07f87f-d956-4ede-b6da-d54cb2842c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14152
1315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.141521315
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.3256345620
Short name T1150
Test name
Test status
Simulation time 10051300126 ps
CPU time 13.74 seconds
Started Jun 02 03:26:21 PM PDT 24
Finished Jun 02 03:26:35 PM PDT 24
Peak memory 205768 kb
Host smart-7b28fb11-a9e3-435b-9568-068c465731ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32563
45620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.3256345620
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.3250944740
Short name T1098
Test name
Test status
Simulation time 10054051065 ps
CPU time 12.48 seconds
Started Jun 02 03:26:17 PM PDT 24
Finished Jun 02 03:26:30 PM PDT 24
Peak memory 205716 kb
Host smart-c70d5569-9f03-4314-9b7e-9871e7712b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32509
44740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3250944740
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.533790817
Short name T1738
Test name
Test status
Simulation time 10634578723 ps
CPU time 14.24 seconds
Started Jun 02 03:26:19 PM PDT 24
Finished Jun 02 03:26:33 PM PDT 24
Peak memory 205716 kb
Host smart-9f32b0f7-c232-4471-828f-6b25d33be72f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53379
0817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.533790817
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1636080824
Short name T923
Test name
Test status
Simulation time 10247598553 ps
CPU time 14.66 seconds
Started Jun 02 03:26:17 PM PDT 24
Finished Jun 02 03:26:33 PM PDT 24
Peak memory 205752 kb
Host smart-61a2bca9-b845-4a62-9c54-eaa4e1202d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16360
80824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1636080824
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.3354105196
Short name T823
Test name
Test status
Simulation time 10077128557 ps
CPU time 12.54 seconds
Started Jun 02 03:26:26 PM PDT 24
Finished Jun 02 03:26:39 PM PDT 24
Peak memory 205752 kb
Host smart-b530e7e3-7397-4651-aa77-30e4d62dcbd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33541
05196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.3354105196
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.41659522
Short name T558
Test name
Test status
Simulation time 10066053406 ps
CPU time 13.51 seconds
Started Jun 02 03:26:27 PM PDT 24
Finished Jun 02 03:26:41 PM PDT 24
Peak memory 205580 kb
Host smart-16eedbbf-43bf-4fbd-8beb-c0af607432e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41659
522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.41659522
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.2797126782
Short name T1327
Test name
Test status
Simulation time 10116761636 ps
CPU time 13.94 seconds
Started Jun 02 03:26:17 PM PDT 24
Finished Jun 02 03:26:31 PM PDT 24
Peak memory 205788 kb
Host smart-8f2e6f51-39c9-4b0c-bace-e88e7da8b26d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27971
26782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.2797126782
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.3884309338
Short name T2032
Test name
Test status
Simulation time 10098769865 ps
CPU time 13.82 seconds
Started Jun 02 03:26:17 PM PDT 24
Finished Jun 02 03:26:32 PM PDT 24
Peak memory 205680 kb
Host smart-9ec9e27c-18d4-4546-af60-bca9fcec9432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38843
09338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.3884309338
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.3743557017
Short name T1817
Test name
Test status
Simulation time 13237628586 ps
CPU time 15.66 seconds
Started Jun 02 03:26:18 PM PDT 24
Finished Jun 02 03:26:35 PM PDT 24
Peak memory 205660 kb
Host smart-fab0a2cf-bb0e-4512-8922-b047aaab6269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37435
57017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.3743557017
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.1580736026
Short name T573
Test name
Test status
Simulation time 10092008440 ps
CPU time 14.51 seconds
Started Jun 02 03:26:18 PM PDT 24
Finished Jun 02 03:26:33 PM PDT 24
Peak memory 205772 kb
Host smart-4a13455e-2ac7-4b5d-a741-17bbcaea4b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15807
36026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.1580736026
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.2567102539
Short name T978
Test name
Test status
Simulation time 22480621371 ps
CPU time 100.49 seconds
Started Jun 02 03:26:22 PM PDT 24
Finished Jun 02 03:28:03 PM PDT 24
Peak memory 205684 kb
Host smart-af3e7568-536a-4abd-8090-32ca26dd1c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25671
02539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.2567102539
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2627112809
Short name T308
Test name
Test status
Simulation time 10057547132 ps
CPU time 16.84 seconds
Started Jun 02 03:26:18 PM PDT 24
Finished Jun 02 03:26:35 PM PDT 24
Peak memory 205792 kb
Host smart-808ad7b2-a100-467f-b443-d4aaf5e69c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26271
12809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2627112809
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.2087244365
Short name T497
Test name
Test status
Simulation time 10091347041 ps
CPU time 18.06 seconds
Started Jun 02 03:26:22 PM PDT 24
Finished Jun 02 03:26:41 PM PDT 24
Peak memory 205620 kb
Host smart-bdc4e227-28dd-46c2-af0d-bf6a6a378924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20872
44365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.2087244365
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.122628981
Short name T1953
Test name
Test status
Simulation time 10122495769 ps
CPU time 16.22 seconds
Started Jun 02 03:26:22 PM PDT 24
Finished Jun 02 03:26:39 PM PDT 24
Peak memory 205764 kb
Host smart-bd857c5c-94ee-49c9-ab6b-ee18cf1cc72a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12262
8981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.122628981
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.2166808204
Short name T962
Test name
Test status
Simulation time 10105268186 ps
CPU time 15.12 seconds
Started Jun 02 03:26:26 PM PDT 24
Finished Jun 02 03:26:42 PM PDT 24
Peak memory 205736 kb
Host smart-46cf5423-d2e1-4a2b-a7da-72017c67ec08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21668
08204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.2166808204
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.3360506518
Short name T1695
Test name
Test status
Simulation time 10078882488 ps
CPU time 13 seconds
Started Jun 02 03:26:26 PM PDT 24
Finished Jun 02 03:26:39 PM PDT 24
Peak memory 205628 kb
Host smart-1def3711-fb60-4fdf-b8c9-0773101301fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33605
06518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.3360506518
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_eop_single_bit_handling.3526710436
Short name T1497
Test name
Test status
Simulation time 10084668775 ps
CPU time 14.1 seconds
Started Jun 02 03:26:27 PM PDT 24
Finished Jun 02 03:26:42 PM PDT 24
Peak memory 205588 kb
Host smart-81d334bd-3947-4497-9268-1cab7e13379b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35267
10436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_eop_single_bit_handling.3526710436
Directory /workspace/1.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.2065153838
Short name T1346
Test name
Test status
Simulation time 10089278295 ps
CPU time 13.91 seconds
Started Jun 02 03:26:28 PM PDT 24
Finished Jun 02 03:26:43 PM PDT 24
Peak memory 205728 kb
Host smart-69920941-872d-4d81-bcbd-ef5680d565e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20651
53838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.2065153838
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.1552476088
Short name T1795
Test name
Test status
Simulation time 27798886449 ps
CPU time 56.13 seconds
Started Jun 02 03:26:31 PM PDT 24
Finished Jun 02 03:27:27 PM PDT 24
Peak memory 205784 kb
Host smart-1634eb73-5cf1-4a98-8107-177d6fcfc83f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15524
76088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.1552476088
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.2789409775
Short name T1940
Test name
Test status
Simulation time 10090778111 ps
CPU time 15.75 seconds
Started Jun 02 03:26:24 PM PDT 24
Finished Jun 02 03:26:41 PM PDT 24
Peak memory 205788 kb
Host smart-5fb9730a-b73f-4f1e-853e-d76791ca0ee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27894
09775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.2789409775
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.2147219278
Short name T781
Test name
Test status
Simulation time 10100527057 ps
CPU time 13.84 seconds
Started Jun 02 03:26:22 PM PDT 24
Finished Jun 02 03:26:36 PM PDT 24
Peak memory 205652 kb
Host smart-3ddbc2bc-ee59-4ad4-ae67-665dacaae6a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21472
19278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.2147219278
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.2337209073
Short name T174
Test name
Test status
Simulation time 41423674694 ps
CPU time 238.5 seconds
Started Jun 02 03:26:22 PM PDT 24
Finished Jun 02 03:30:21 PM PDT 24
Peak memory 205728 kb
Host smart-6fc98a61-c67f-4438-a8bf-7a3b29fe119b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2337209073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2337209073
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.284554399
Short name T1710
Test name
Test status
Simulation time 38141906093 ps
CPU time 192.34 seconds
Started Jun 02 03:26:30 PM PDT 24
Finished Jun 02 03:29:43 PM PDT 24
Peak memory 205844 kb
Host smart-d69aefed-ee27-4003-afcb-37fea8807cb9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=284554399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.284554399
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.1603282887
Short name T1834
Test name
Test status
Simulation time 10067687970 ps
CPU time 16.48 seconds
Started Jun 02 03:26:23 PM PDT 24
Finished Jun 02 03:26:40 PM PDT 24
Peak memory 205624 kb
Host smart-cc816525-d368-4397-9050-c62bb56840ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16032
82887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.1603282887
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.454062131
Short name T1631
Test name
Test status
Simulation time 10048178501 ps
CPU time 13.56 seconds
Started Jun 02 03:26:30 PM PDT 24
Finished Jun 02 03:26:45 PM PDT 24
Peak memory 205692 kb
Host smart-a36b6775-8df6-4d20-999c-aec1640d67bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45406
2131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.454062131
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.106609666
Short name T1564
Test name
Test status
Simulation time 10062608305 ps
CPU time 13.36 seconds
Started Jun 02 03:26:28 PM PDT 24
Finished Jun 02 03:26:42 PM PDT 24
Peak memory 205580 kb
Host smart-2ee35626-535d-49d5-ada9-52ade70ddebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10660
9666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.106609666
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3609883874
Short name T1780
Test name
Test status
Simulation time 10141847001 ps
CPU time 15.23 seconds
Started Jun 02 03:26:14 PM PDT 24
Finished Jun 02 03:26:30 PM PDT 24
Peak memory 205760 kb
Host smart-c029d61e-86b0-4150-8a47-c9d1214ef0e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36098
83874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3609883874
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.3739679669
Short name T1445
Test name
Test status
Simulation time 10089559953 ps
CPU time 12.94 seconds
Started Jun 02 03:26:22 PM PDT 24
Finished Jun 02 03:26:36 PM PDT 24
Peak memory 205624 kb
Host smart-d5bcea34-5db7-4230-8939-966f0432061c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37396
79669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.3739679669
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.2529112111
Short name T1790
Test name
Test status
Simulation time 18584411118 ps
CPU time 244.05 seconds
Started Jun 02 03:26:22 PM PDT 24
Finished Jun 02 03:30:27 PM PDT 24
Peak memory 205684 kb
Host smart-74876e3a-339e-460f-b6d6-a3d178d247fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25291
12111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.2529112111
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.3832480446
Short name T171
Test name
Test status
Simulation time 29991487542 ps
CPU time 136.95 seconds
Started Jun 02 03:26:23 PM PDT 24
Finished Jun 02 03:28:41 PM PDT 24
Peak memory 205780 kb
Host smart-33e161de-64cd-47a6-a31d-bc4509f74a05
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832480446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_
traffic.3832480446
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.4032489385
Short name T828
Test name
Test status
Simulation time 10151585225 ps
CPU time 14.15 seconds
Started Jun 02 03:28:08 PM PDT 24
Finished Jun 02 03:28:23 PM PDT 24
Peak memory 205704 kb
Host smart-e80be1a7-74ff-4afc-92b8-643f50ca1adb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4032489385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.4032489385
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.2728782243
Short name T695
Test name
Test status
Simulation time 10076741012 ps
CPU time 15.62 seconds
Started Jun 02 03:28:09 PM PDT 24
Finished Jun 02 03:28:25 PM PDT 24
Peak memory 205600 kb
Host smart-18a698ed-4689-4f20-bc49-a5027c03f229
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2728782243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.2728782243
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.4115156552
Short name T562
Test name
Test status
Simulation time 10134306791 ps
CPU time 13.36 seconds
Started Jun 02 03:28:12 PM PDT 24
Finished Jun 02 03:28:27 PM PDT 24
Peak memory 205760 kb
Host smart-e976908b-7842-48be-bc1c-bb82bf5fef5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41151
56552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.4115156552
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.57678403
Short name T1589
Test name
Test status
Simulation time 14292623272 ps
CPU time 18.42 seconds
Started Jun 02 03:27:58 PM PDT 24
Finished Jun 02 03:28:17 PM PDT 24
Peak memory 205692 kb
Host smart-6326300e-92fb-4111-8ad1-546a7019acf1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=57678403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.57678403
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.3396559562
Short name T1543
Test name
Test status
Simulation time 23247940628 ps
CPU time 25.26 seconds
Started Jun 02 03:27:58 PM PDT 24
Finished Jun 02 03:28:24 PM PDT 24
Peak memory 205612 kb
Host smart-5d5e6b06-db44-4189-a087-c5e66aeedfba
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3396559562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.3396559562
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.3788625535
Short name T389
Test name
Test status
Simulation time 10056604107 ps
CPU time 14.88 seconds
Started Jun 02 03:27:57 PM PDT 24
Finished Jun 02 03:28:13 PM PDT 24
Peak memory 205672 kb
Host smart-b29c315e-ed9d-443c-baa9-15c5c2a6e460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37886
25535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3788625535
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.636388969
Short name T576
Test name
Test status
Simulation time 10938541584 ps
CPU time 15.25 seconds
Started Jun 02 03:27:57 PM PDT 24
Finished Jun 02 03:28:13 PM PDT 24
Peak memory 205704 kb
Host smart-6ac2f25f-63a0-4903-b0ef-b78d078ac841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63638
8969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.636388969
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.1855367413
Short name T1639
Test name
Test status
Simulation time 10036683657 ps
CPU time 16.52 seconds
Started Jun 02 03:28:05 PM PDT 24
Finished Jun 02 03:28:23 PM PDT 24
Peak memory 205624 kb
Host smart-16cc3c00-6d8e-4c1d-83f5-2bc7ee4abc86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18553
67413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.1855367413
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.447650403
Short name T1334
Test name
Test status
Simulation time 10774455472 ps
CPU time 14.85 seconds
Started Jun 02 03:27:57 PM PDT 24
Finished Jun 02 03:28:13 PM PDT 24
Peak memory 205704 kb
Host smart-001e58b3-c7b1-43ea-bb84-58da2df1bac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44765
0403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.447650403
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.3551983998
Short name T676
Test name
Test status
Simulation time 10073932521 ps
CPU time 14.63 seconds
Started Jun 02 03:28:07 PM PDT 24
Finished Jun 02 03:28:23 PM PDT 24
Peak memory 205500 kb
Host smart-3d67d6ed-68fb-41a8-aef5-713885e2a0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35519
83998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3551983998
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.4107918465
Short name T1178
Test name
Test status
Simulation time 10055063137 ps
CPU time 15.16 seconds
Started Jun 02 03:28:09 PM PDT 24
Finished Jun 02 03:28:25 PM PDT 24
Peak memory 205652 kb
Host smart-e8f759bf-3dfd-46b2-be36-98dbc836db20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41079
18465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.4107918465
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3894802407
Short name T318
Test name
Test status
Simulation time 10123083277 ps
CPU time 15.62 seconds
Started Jun 02 03:28:07 PM PDT 24
Finished Jun 02 03:28:24 PM PDT 24
Peak memory 205632 kb
Host smart-4c0b9073-22c4-4f19-bfcb-4a5973342997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38948
02407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3894802407
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.1143143328
Short name T1188
Test name
Test status
Simulation time 10106939273 ps
CPU time 14.22 seconds
Started Jun 02 03:28:02 PM PDT 24
Finished Jun 02 03:28:17 PM PDT 24
Peak memory 205612 kb
Host smart-08080529-9415-43c5-92bd-5083ce38ab80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11431
43328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.1143143328
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.4132314361
Short name T1376
Test name
Test status
Simulation time 13181749799 ps
CPU time 15.88 seconds
Started Jun 02 03:28:03 PM PDT 24
Finished Jun 02 03:28:19 PM PDT 24
Peak memory 205696 kb
Host smart-6c0dc975-5a7b-4fc2-b0ec-b3c829f04454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41323
14361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.4132314361
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1307019707
Short name T838
Test name
Test status
Simulation time 10107454348 ps
CPU time 13.34 seconds
Started Jun 02 03:28:03 PM PDT 24
Finished Jun 02 03:28:17 PM PDT 24
Peak memory 205688 kb
Host smart-3e25ef9a-5415-4a73-a576-43a6dd01c339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13070
19707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1307019707
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.4074154777
Short name T1042
Test name
Test status
Simulation time 21094300096 ps
CPU time 117.19 seconds
Started Jun 02 03:28:04 PM PDT 24
Finished Jun 02 03:30:02 PM PDT 24
Peak memory 205704 kb
Host smart-57b11d6a-77ed-458f-aa8c-bfcb241729c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40741
54777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.4074154777
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.3137857059
Short name T41
Test name
Test status
Simulation time 10051961220 ps
CPU time 15.54 seconds
Started Jun 02 03:28:02 PM PDT 24
Finished Jun 02 03:28:18 PM PDT 24
Peak memory 205692 kb
Host smart-5917649d-40e0-40e8-a9d9-d4d2867d1bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31378
57059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.3137857059
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.3090532484
Short name T1524
Test name
Test status
Simulation time 10094788128 ps
CPU time 17.02 seconds
Started Jun 02 03:28:05 PM PDT 24
Finished Jun 02 03:28:23 PM PDT 24
Peak memory 205764 kb
Host smart-498d74fe-8e81-40a9-b55c-e0f346349c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30905
32484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.3090532484
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.82585382
Short name T1177
Test name
Test status
Simulation time 10097796583 ps
CPU time 13.72 seconds
Started Jun 02 03:28:01 PM PDT 24
Finished Jun 02 03:28:16 PM PDT 24
Peak memory 205716 kb
Host smart-e56ea3c0-5e75-4825-b136-4243ad126447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82585
382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.82585382
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1423368142
Short name T785
Test name
Test status
Simulation time 10087833992 ps
CPU time 13.24 seconds
Started Jun 02 03:28:02 PM PDT 24
Finished Jun 02 03:28:16 PM PDT 24
Peak memory 205756 kb
Host smart-23477c56-0a1e-496f-a0c4-62e4f812928d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14233
68142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1423368142
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_eop_single_bit_handling.2316709382
Short name T1411
Test name
Test status
Simulation time 10084434971 ps
CPU time 13.65 seconds
Started Jun 02 03:28:08 PM PDT 24
Finished Jun 02 03:28:23 PM PDT 24
Peak memory 205640 kb
Host smart-f1127226-a08a-4769-ae5c-c81f566a0a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23167
09382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_eop_single_bit_handling.2316709382
Directory /workspace/10.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.517484698
Short name T1471
Test name
Test status
Simulation time 10054006940 ps
CPU time 15.26 seconds
Started Jun 02 03:28:08 PM PDT 24
Finished Jun 02 03:28:24 PM PDT 24
Peak memory 205824 kb
Host smart-6bfd0996-5c81-4e02-90ae-c35609a95904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51748
4698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.517484698
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.1785655003
Short name T1615
Test name
Test status
Simulation time 28539300623 ps
CPU time 67.43 seconds
Started Jun 02 03:28:02 PM PDT 24
Finished Jun 02 03:29:11 PM PDT 24
Peak memory 205936 kb
Host smart-d0e18116-040a-4511-9013-f9357948cc1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17856
55003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.1785655003
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.3274815584
Short name T275
Test name
Test status
Simulation time 10092280737 ps
CPU time 13.21 seconds
Started Jun 02 03:28:03 PM PDT 24
Finished Jun 02 03:28:17 PM PDT 24
Peak memory 205688 kb
Host smart-64f8acf6-0894-4441-b697-79bd55c695ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32748
15584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.3274815584
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.946949870
Short name T1462
Test name
Test status
Simulation time 10070731930 ps
CPU time 15.14 seconds
Started Jun 02 03:28:06 PM PDT 24
Finished Jun 02 03:28:22 PM PDT 24
Peak memory 205780 kb
Host smart-912fdb3d-f82b-407b-89ed-d9d95f676242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94694
9870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.946949870
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.3851406079
Short name T907
Test name
Test status
Simulation time 10109119867 ps
CPU time 14.76 seconds
Started Jun 02 03:28:03 PM PDT 24
Finished Jun 02 03:28:19 PM PDT 24
Peak memory 205656 kb
Host smart-09251c83-4c2a-4684-bbe0-b42dd23d8e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38514
06079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.3851406079
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.2379369458
Short name T1158
Test name
Test status
Simulation time 10057623668 ps
CPU time 12.95 seconds
Started Jun 02 03:28:08 PM PDT 24
Finished Jun 02 03:28:22 PM PDT 24
Peak memory 205668 kb
Host smart-e5e62ed1-65f0-419d-9b83-068e570314c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23793
69458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.2379369458
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.1789896953
Short name T1861
Test name
Test status
Simulation time 10074403715 ps
CPU time 13.39 seconds
Started Jun 02 03:28:08 PM PDT 24
Finished Jun 02 03:28:23 PM PDT 24
Peak memory 205736 kb
Host smart-cfa71ec7-a093-4a48-bc43-40386245f95f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17898
96953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.1789896953
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3619958288
Short name T578
Test name
Test status
Simulation time 10090611137 ps
CPU time 16.07 seconds
Started Jun 02 03:28:15 PM PDT 24
Finished Jun 02 03:28:32 PM PDT 24
Peak memory 205704 kb
Host smart-41ca6b86-fcac-4eca-8977-1c5f7942dded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36199
58288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3619958288
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.4054996118
Short name T590
Test name
Test status
Simulation time 10077677094 ps
CPU time 14.35 seconds
Started Jun 02 03:28:09 PM PDT 24
Finished Jun 02 03:28:24 PM PDT 24
Peak memory 205768 kb
Host smart-5d30cb52-9953-43fe-b3a5-46eb57d34aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40549
96118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.4054996118
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.4110174088
Short name T1090
Test name
Test status
Simulation time 10081138121 ps
CPU time 13.12 seconds
Started Jun 02 03:28:06 PM PDT 24
Finished Jun 02 03:28:20 PM PDT 24
Peak memory 205764 kb
Host smart-ce6322d7-5dd8-47f5-93fa-b4220d449cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41101
74088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.4110174088
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.4078554761
Short name T1028
Test name
Test status
Simulation time 19747454950 ps
CPU time 109.18 seconds
Started Jun 02 03:28:15 PM PDT 24
Finished Jun 02 03:30:05 PM PDT 24
Peak memory 205728 kb
Host smart-19d4602b-7a2c-4f49-bc71-b94b872c5002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40785
54761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.4078554761
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.3172016121
Short name T861
Test name
Test status
Simulation time 10180115563 ps
CPU time 14.52 seconds
Started Jun 02 03:28:17 PM PDT 24
Finished Jun 02 03:28:32 PM PDT 24
Peak memory 205600 kb
Host smart-2e3768d8-90c9-4558-9c13-d71b2d191627
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3172016121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.3172016121
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.288703456
Short name T680
Test name
Test status
Simulation time 10071862929 ps
CPU time 13 seconds
Started Jun 02 03:28:21 PM PDT 24
Finished Jun 02 03:28:35 PM PDT 24
Peak memory 205704 kb
Host smart-4039633f-154b-442c-be0d-2583a19910f6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=288703456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.288703456
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.2947067741
Short name T696
Test name
Test status
Simulation time 10117171953 ps
CPU time 16 seconds
Started Jun 02 03:28:19 PM PDT 24
Finished Jun 02 03:28:36 PM PDT 24
Peak memory 205732 kb
Host smart-090708af-eeb8-4fa1-9bb3-294fe6c95e6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29470
67741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.2947067741
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.3196700339
Short name T1493
Test name
Test status
Simulation time 13450505733 ps
CPU time 18.7 seconds
Started Jun 02 03:28:06 PM PDT 24
Finished Jun 02 03:28:26 PM PDT 24
Peak memory 205704 kb
Host smart-c7d9822d-64df-431d-b72d-350c0bb606c2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3196700339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.3196700339
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.3707638756
Short name T1012
Test name
Test status
Simulation time 23261903098 ps
CPU time 27.1 seconds
Started Jun 02 03:28:10 PM PDT 24
Finished Jun 02 03:28:38 PM PDT 24
Peak memory 205656 kb
Host smart-6feeb709-04e4-4183-93d3-d596a620df73
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3707638756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.3707638756
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.1599998613
Short name T920
Test name
Test status
Simulation time 10066689688 ps
CPU time 13.76 seconds
Started Jun 02 03:28:08 PM PDT 24
Finished Jun 02 03:28:23 PM PDT 24
Peak memory 205660 kb
Host smart-eea17901-4ad1-472d-a960-a17c5aae8250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15999
98613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.1599998613
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.4092020655
Short name T1944
Test name
Test status
Simulation time 10883187701 ps
CPU time 16.73 seconds
Started Jun 02 03:28:10 PM PDT 24
Finished Jun 02 03:28:28 PM PDT 24
Peak memory 205692 kb
Host smart-5e01822e-5900-41c6-8b2a-fc8da7f6037b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40920
20655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.4092020655
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.975005141
Short name T66
Test name
Test status
Simulation time 10042333311 ps
CPU time 14.94 seconds
Started Jun 02 03:28:15 PM PDT 24
Finished Jun 02 03:28:31 PM PDT 24
Peak memory 205752 kb
Host smart-7eb9732e-04f4-46eb-bfd0-28810c7020ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97500
5141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.975005141
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.2645542098
Short name T922
Test name
Test status
Simulation time 10075897841 ps
CPU time 13.26 seconds
Started Jun 02 03:28:15 PM PDT 24
Finished Jun 02 03:28:30 PM PDT 24
Peak memory 205680 kb
Host smart-c6aa33ed-3389-48ba-a41e-1df4a5c8546e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26455
42098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2645542098
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.2781453096
Short name T1549
Test name
Test status
Simulation time 10732598698 ps
CPU time 14.61 seconds
Started Jun 02 03:28:07 PM PDT 24
Finished Jun 02 03:28:23 PM PDT 24
Peak memory 205660 kb
Host smart-ac7cd77c-9b5c-423d-99d9-9d02fb4eb56a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27814
53096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.2781453096
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.735586600
Short name T1966
Test name
Test status
Simulation time 10266587069 ps
CPU time 17.83 seconds
Started Jun 02 03:28:10 PM PDT 24
Finished Jun 02 03:28:29 PM PDT 24
Peak memory 205720 kb
Host smart-aca728cd-4346-47cc-a492-ef45697adc1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73558
6600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.735586600
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.142612371
Short name T1808
Test name
Test status
Simulation time 10123203497 ps
CPU time 14.56 seconds
Started Jun 02 03:28:19 PM PDT 24
Finished Jun 02 03:28:34 PM PDT 24
Peak memory 205760 kb
Host smart-6b7e4581-9f63-4afc-8471-bc6aa98e44ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14261
2371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.142612371
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.2010007341
Short name T1661
Test name
Test status
Simulation time 10084798115 ps
CPU time 14.98 seconds
Started Jun 02 03:28:12 PM PDT 24
Finished Jun 02 03:28:29 PM PDT 24
Peak memory 205672 kb
Host smart-4d523b49-2410-4ccb-b1eb-a56b660756d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20100
07341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.2010007341
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.1257334903
Short name T1076
Test name
Test status
Simulation time 10093127015 ps
CPU time 16.83 seconds
Started Jun 02 03:28:13 PM PDT 24
Finished Jun 02 03:28:31 PM PDT 24
Peak memory 205700 kb
Host smart-c45e86f4-0f13-4f85-8904-d8ea9e74dd44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12573
34903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1257334903
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.1993271224
Short name T854
Test name
Test status
Simulation time 10075518351 ps
CPU time 12.62 seconds
Started Jun 02 03:28:13 PM PDT 24
Finished Jun 02 03:28:27 PM PDT 24
Peak memory 205780 kb
Host smart-568f84e5-ad57-4105-a088-d1795ffbca20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19932
71224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.1993271224
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.634940808
Short name T751
Test name
Test status
Simulation time 13175783929 ps
CPU time 16.17 seconds
Started Jun 02 03:28:10 PM PDT 24
Finished Jun 02 03:28:28 PM PDT 24
Peak memory 205668 kb
Host smart-89e58ba8-57a4-432a-9165-6d64a5f4f65e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63494
0808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.634940808
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.2457784843
Short name T830
Test name
Test status
Simulation time 10118484104 ps
CPU time 14.95 seconds
Started Jun 02 03:28:16 PM PDT 24
Finished Jun 02 03:28:32 PM PDT 24
Peak memory 205804 kb
Host smart-48f6c965-e369-4181-a139-f6faece70cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24577
84843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.2457784843
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.4180309099
Short name T1060
Test name
Test status
Simulation time 16425282163 ps
CPU time 77.25 seconds
Started Jun 02 03:28:12 PM PDT 24
Finished Jun 02 03:29:30 PM PDT 24
Peak memory 205688 kb
Host smart-443f84d3-e722-424c-abb1-e46f886e7b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41803
09099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.4180309099
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.1407729575
Short name T1092
Test name
Test status
Simulation time 10087772052 ps
CPU time 17.19 seconds
Started Jun 02 03:28:12 PM PDT 24
Finished Jun 02 03:28:31 PM PDT 24
Peak memory 205736 kb
Host smart-3fdd3469-a033-4da7-9259-2985be5cc4a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14077
29575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.1407729575
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.3475286862
Short name T1866
Test name
Test status
Simulation time 10061047215 ps
CPU time 13.67 seconds
Started Jun 02 03:28:13 PM PDT 24
Finished Jun 02 03:28:28 PM PDT 24
Peak memory 205752 kb
Host smart-c4516b5b-88f3-4c3f-be39-3490261fe45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34752
86862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.3475286862
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1191794428
Short name T1404
Test name
Test status
Simulation time 10044517131 ps
CPU time 13.65 seconds
Started Jun 02 03:28:14 PM PDT 24
Finished Jun 02 03:28:28 PM PDT 24
Peak memory 205704 kb
Host smart-ebc618da-ac72-42c5-9bf6-eb2aa9d53cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11917
94428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1191794428
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1473948668
Short name T476
Test name
Test status
Simulation time 10077753166 ps
CPU time 13.95 seconds
Started Jun 02 03:28:12 PM PDT 24
Finished Jun 02 03:28:27 PM PDT 24
Peak memory 205648 kb
Host smart-e432acc9-6f22-4a09-a5c7-7d8166a47ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14739
48668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1473948668
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_eop_single_bit_handling.2740726311
Short name T1732
Test name
Test status
Simulation time 10054900233 ps
CPU time 15.62 seconds
Started Jun 02 03:28:16 PM PDT 24
Finished Jun 02 03:28:32 PM PDT 24
Peak memory 205660 kb
Host smart-28f9fc88-1312-4ffc-bbc5-b553ba5e8ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27407
26311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_eop_single_bit_handling.2740726311
Directory /workspace/11.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.1657134127
Short name T1887
Test name
Test status
Simulation time 10046718794 ps
CPU time 13.27 seconds
Started Jun 02 03:28:12 PM PDT 24
Finished Jun 02 03:28:27 PM PDT 24
Peak memory 205792 kb
Host smart-36d91d76-6f27-4aa7-b03c-75e46aed7769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16571
34127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.1657134127
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.2261539609
Short name T1598
Test name
Test status
Simulation time 10038149135 ps
CPU time 12.68 seconds
Started Jun 02 03:28:16 PM PDT 24
Finished Jun 02 03:28:30 PM PDT 24
Peak memory 205736 kb
Host smart-aabc2cee-09cc-430d-b08b-1ee9513118c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22615
39609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.2261539609
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.1095847240
Short name T1839
Test name
Test status
Simulation time 21918821221 ps
CPU time 39.8 seconds
Started Jun 02 03:28:16 PM PDT 24
Finished Jun 02 03:28:57 PM PDT 24
Peak memory 205708 kb
Host smart-fdd6c6bc-aa72-4786-ba08-ceeec822c017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10958
47240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.1095847240
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.3305359709
Short name T1673
Test name
Test status
Simulation time 10065675665 ps
CPU time 15.04 seconds
Started Jun 02 03:28:15 PM PDT 24
Finished Jun 02 03:28:31 PM PDT 24
Peak memory 205736 kb
Host smart-1c0005d6-57e4-44d2-bc3b-d3312a93607f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33053
59709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3305359709
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.50818617
Short name T466
Test name
Test status
Simulation time 10176227192 ps
CPU time 13.78 seconds
Started Jun 02 03:28:13 PM PDT 24
Finished Jun 02 03:28:27 PM PDT 24
Peak memory 205748 kb
Host smart-fee950f6-2d56-45d4-af0a-f22ddbd58b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50818
617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.50818617
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.941394518
Short name T1336
Test name
Test status
Simulation time 10059565215 ps
CPU time 12.94 seconds
Started Jun 02 03:28:14 PM PDT 24
Finished Jun 02 03:28:27 PM PDT 24
Peak memory 205724 kb
Host smart-76f67634-4443-4076-a634-af9a741c5d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94139
4518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.941394518
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.2033264517
Short name T390
Test name
Test status
Simulation time 10044924537 ps
CPU time 14.57 seconds
Started Jun 02 03:28:12 PM PDT 24
Finished Jun 02 03:28:28 PM PDT 24
Peak memory 205676 kb
Host smart-560e384a-c053-4456-be2c-371217d36828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20332
64517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.2033264517
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_smoke.3980531050
Short name T1587
Test name
Test status
Simulation time 10127272704 ps
CPU time 12.58 seconds
Started Jun 02 03:28:12 PM PDT 24
Finished Jun 02 03:28:26 PM PDT 24
Peak memory 205792 kb
Host smart-300a3bd0-df92-432c-8b6e-02ca08c09040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39805
31050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.3980531050
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.1138466322
Short name T955
Test name
Test status
Simulation time 10093768543 ps
CPU time 14.73 seconds
Started Jun 02 03:28:14 PM PDT 24
Finished Jun 02 03:28:29 PM PDT 24
Peak memory 205684 kb
Host smart-678faf9c-8b62-47d7-ba39-82bdaf0c08f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11384
66322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.1138466322
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.3778222669
Short name T1200
Test name
Test status
Simulation time 10096918237 ps
CPU time 13.56 seconds
Started Jun 02 03:28:15 PM PDT 24
Finished Jun 02 03:28:29 PM PDT 24
Peak memory 205784 kb
Host smart-73f621ad-3748-4b99-a686-b2a4d068c0ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37782
22669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3778222669
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.149739096
Short name T803
Test name
Test status
Simulation time 23766773330 ps
CPU time 410.74 seconds
Started Jun 02 03:28:14 PM PDT 24
Finished Jun 02 03:35:05 PM PDT 24
Peak memory 205616 kb
Host smart-4552a36e-50a7-4af5-aa45-ac971986e5b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14973
9096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.149739096
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.1295112390
Short name T21
Test name
Test status
Simulation time 10149980508 ps
CPU time 14.22 seconds
Started Jun 02 03:28:31 PM PDT 24
Finished Jun 02 03:28:46 PM PDT 24
Peak memory 205812 kb
Host smart-0354353d-9820-4954-9f2e-73a7819d8e06
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1295112390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.1295112390
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.3903478511
Short name T1510
Test name
Test status
Simulation time 10062895125 ps
CPU time 13.6 seconds
Started Jun 02 03:28:22 PM PDT 24
Finished Jun 02 03:28:37 PM PDT 24
Peak memory 205668 kb
Host smart-dacbe938-d8d9-42ff-9060-f8cd0cc21689
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3903478511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.3903478511
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.1379669026
Short name T209
Test name
Test status
Simulation time 10076428805 ps
CPU time 13.7 seconds
Started Jun 02 03:28:24 PM PDT 24
Finished Jun 02 03:28:39 PM PDT 24
Peak memory 205716 kb
Host smart-40d6fcce-94fe-43a2-8ad0-787a1e4ecdbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13796
69026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.1379669026
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.807864206
Short name T1399
Test name
Test status
Simulation time 14092279131 ps
CPU time 16.82 seconds
Started Jun 02 03:28:17 PM PDT 24
Finished Jun 02 03:28:35 PM PDT 24
Peak memory 205740 kb
Host smart-be90a6d7-a68b-403a-9046-0c2ed65f6706
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=807864206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.807864206
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.3141290438
Short name T1401
Test name
Test status
Simulation time 23249107089 ps
CPU time 25.1 seconds
Started Jun 02 03:28:21 PM PDT 24
Finished Jun 02 03:28:47 PM PDT 24
Peak memory 205796 kb
Host smart-440e771c-b5fc-4629-b6d3-c27c6020c5eb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3141290438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.3141290438
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3882309997
Short name T929
Test name
Test status
Simulation time 10074873885 ps
CPU time 14.73 seconds
Started Jun 02 03:28:18 PM PDT 24
Finished Jun 02 03:28:33 PM PDT 24
Peak memory 205696 kb
Host smart-80b7421a-538c-4976-bb9e-fcb25c3dd8c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38823
09997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3882309997
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.174711908
Short name T805
Test name
Test status
Simulation time 10060005465 ps
CPU time 15.34 seconds
Started Jun 02 03:28:17 PM PDT 24
Finished Jun 02 03:28:33 PM PDT 24
Peak memory 205724 kb
Host smart-04304a22-dc60-4b18-894e-37a2f24b5569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17471
1908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.174711908
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.3177699433
Short name T1231
Test name
Test status
Simulation time 11045305883 ps
CPU time 15.36 seconds
Started Jun 02 03:28:16 PM PDT 24
Finished Jun 02 03:28:32 PM PDT 24
Peak memory 205676 kb
Host smart-e53dffed-5059-4db9-b5cb-edea1d5e3e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31776
99433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.3177699433
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.3984092217
Short name T1971
Test name
Test status
Simulation time 10038602364 ps
CPU time 12.92 seconds
Started Jun 02 03:28:21 PM PDT 24
Finished Jun 02 03:28:35 PM PDT 24
Peak memory 205760 kb
Host smart-ddfe2258-f365-42e1-b580-18594239f603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39840
92217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.3984092217
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.1902841870
Short name T1341
Test name
Test status
Simulation time 10050689451 ps
CPU time 13.67 seconds
Started Jun 02 03:28:19 PM PDT 24
Finished Jun 02 03:28:34 PM PDT 24
Peak memory 205672 kb
Host smart-7bfb9ac2-0760-418e-9a1e-59e57c793fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19028
41870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.1902841870
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.739958105
Short name T1333
Test name
Test status
Simulation time 10712256667 ps
CPU time 16.29 seconds
Started Jun 02 03:28:21 PM PDT 24
Finished Jun 02 03:28:39 PM PDT 24
Peak memory 205600 kb
Host smart-7550587d-6e4d-4503-8b59-d9cf4ef1a4e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73995
8105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.739958105
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.1428837547
Short name T1402
Test name
Test status
Simulation time 10072086523 ps
CPU time 14.81 seconds
Started Jun 02 03:28:21 PM PDT 24
Finished Jun 02 03:28:37 PM PDT 24
Peak memory 205588 kb
Host smart-c62452f8-77a7-466b-8c40-12eddfe2961b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14288
37547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.1428837547
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.337960441
Short name T535
Test name
Test status
Simulation time 10092251005 ps
CPU time 12.33 seconds
Started Jun 02 03:28:31 PM PDT 24
Finished Jun 02 03:28:44 PM PDT 24
Peak memory 205812 kb
Host smart-6d288882-8422-4685-9f27-fa9613897227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33796
0441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.337960441
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.3242406699
Short name T888
Test name
Test status
Simulation time 10055594430 ps
CPU time 13.61 seconds
Started Jun 02 03:28:24 PM PDT 24
Finished Jun 02 03:28:38 PM PDT 24
Peak memory 205592 kb
Host smart-93529e7d-ecca-487d-9ef4-0e9931263396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32424
06699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.3242406699
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.3487488429
Short name T2024
Test name
Test status
Simulation time 10063863083 ps
CPU time 18.4 seconds
Started Jun 02 03:28:18 PM PDT 24
Finished Jun 02 03:28:37 PM PDT 24
Peak memory 205584 kb
Host smart-982630c8-ca3c-43c9-a99d-ef8acd396c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34874
88429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.3487488429
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.3743070255
Short name T821
Test name
Test status
Simulation time 10153924205 ps
CPU time 13.33 seconds
Started Jun 02 03:28:20 PM PDT 24
Finished Jun 02 03:28:34 PM PDT 24
Peak memory 205592 kb
Host smart-53a20a46-8c2c-488e-918c-37554891bfc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37430
70255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.3743070255
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.720134318
Short name T1659
Test name
Test status
Simulation time 13273891065 ps
CPU time 16.59 seconds
Started Jun 02 03:28:21 PM PDT 24
Finished Jun 02 03:28:38 PM PDT 24
Peak memory 205604 kb
Host smart-983e2122-a512-42c6-bd8e-dbebde73dca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72013
4318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.720134318
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1544906505
Short name T1318
Test name
Test status
Simulation time 10099878659 ps
CPU time 16.37 seconds
Started Jun 02 03:28:20 PM PDT 24
Finished Jun 02 03:28:38 PM PDT 24
Peak memory 205804 kb
Host smart-3af34e47-20b9-47a1-8928-46dd8958c548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15449
06505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1544906505
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.1646462231
Short name T1383
Test name
Test status
Simulation time 15042519454 ps
CPU time 64.85 seconds
Started Jun 02 03:28:21 PM PDT 24
Finished Jun 02 03:29:26 PM PDT 24
Peak memory 205716 kb
Host smart-52dfe021-01a1-4903-aa58-201cd29cea06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16464
62231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.1646462231
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.3149992716
Short name T1981
Test name
Test status
Simulation time 10053671398 ps
CPU time 15.06 seconds
Started Jun 02 03:28:21 PM PDT 24
Finished Jun 02 03:28:37 PM PDT 24
Peak memory 205816 kb
Host smart-26c44890-6169-4e16-b2d5-74e76ff85362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31499
92716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.3149992716
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.3904325677
Short name T1196
Test name
Test status
Simulation time 10078168296 ps
CPU time 13.83 seconds
Started Jun 02 03:28:23 PM PDT 24
Finished Jun 02 03:28:38 PM PDT 24
Peak memory 205584 kb
Host smart-94faa53d-5637-4aad-886d-25dea1a79a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39043
25677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.3904325677
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.597963670
Short name T1574
Test name
Test status
Simulation time 10084027846 ps
CPU time 14.97 seconds
Started Jun 02 03:28:22 PM PDT 24
Finished Jun 02 03:28:38 PM PDT 24
Peak memory 205696 kb
Host smart-b96ab774-d70d-45ad-96bb-f43418d4148a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59796
3670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.597963670
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.315319102
Short name T524
Test name
Test status
Simulation time 10076411276 ps
CPU time 15.53 seconds
Started Jun 02 03:28:25 PM PDT 24
Finished Jun 02 03:28:41 PM PDT 24
Peak memory 205760 kb
Host smart-c31093e3-cf5b-44ee-84eb-3457c579e66a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31531
9102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.315319102
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.507477937
Short name T178
Test name
Test status
Simulation time 10104556086 ps
CPU time 15.46 seconds
Started Jun 02 03:28:24 PM PDT 24
Finished Jun 02 03:28:40 PM PDT 24
Peak memory 205704 kb
Host smart-4df44f51-f90e-4c17-a08e-62fd0c4c1a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50747
7937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.507477937
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_eop_single_bit_handling.234919621
Short name T1551
Test name
Test status
Simulation time 10074833264 ps
CPU time 13.85 seconds
Started Jun 02 03:28:22 PM PDT 24
Finished Jun 02 03:28:37 PM PDT 24
Peak memory 205684 kb
Host smart-8f887be7-a1b3-4306-9ae9-41883e08d6f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23491
9621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_eop_single_bit_handling.234919621
Directory /workspace/12.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.2328688093
Short name T1030
Test name
Test status
Simulation time 10040505690 ps
CPU time 13 seconds
Started Jun 02 03:28:22 PM PDT 24
Finished Jun 02 03:28:36 PM PDT 24
Peak memory 205620 kb
Host smart-4567e063-1823-4721-a362-b85a6a18ec9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23286
88093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.2328688093
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.76830475
Short name T623
Test name
Test status
Simulation time 10052148255 ps
CPU time 12.48 seconds
Started Jun 02 03:28:25 PM PDT 24
Finished Jun 02 03:28:38 PM PDT 24
Peak memory 205636 kb
Host smart-9a811ec1-108d-40e8-80db-5e611bc8142e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76830
475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.76830475
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.3989501589
Short name T244
Test name
Test status
Simulation time 28521315242 ps
CPU time 54 seconds
Started Jun 02 03:28:22 PM PDT 24
Finished Jun 02 03:29:16 PM PDT 24
Peak memory 205628 kb
Host smart-0543a7e0-08fa-449a-b915-0e19601b6793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39895
01589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.3989501589
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.2160892876
Short name T1358
Test name
Test status
Simulation time 10089340726 ps
CPU time 13.64 seconds
Started Jun 02 03:28:24 PM PDT 24
Finished Jun 02 03:28:38 PM PDT 24
Peak memory 205628 kb
Host smart-4c4f82c5-b3f4-45ed-b339-b89ca95ca28a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21608
92876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.2160892876
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3316078878
Short name T1250
Test name
Test status
Simulation time 10087635669 ps
CPU time 14.11 seconds
Started Jun 02 03:28:24 PM PDT 24
Finished Jun 02 03:28:39 PM PDT 24
Peak memory 205668 kb
Host smart-063af19b-9140-4e51-aee4-6ce4f5a676e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33160
78878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3316078878
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.4046499740
Short name T769
Test name
Test status
Simulation time 10094013477 ps
CPU time 13.62 seconds
Started Jun 02 03:28:25 PM PDT 24
Finished Jun 02 03:28:39 PM PDT 24
Peak memory 205664 kb
Host smart-ec81a25f-69bb-4615-b1fe-9958c0d7508b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40464
99740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.4046499740
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.1631881164
Short name T60
Test name
Test status
Simulation time 10038448463 ps
CPU time 13.17 seconds
Started Jun 02 03:28:23 PM PDT 24
Finished Jun 02 03:28:37 PM PDT 24
Peak memory 205760 kb
Host smart-f1cbc481-d6c6-49e9-a23f-4b7320e613ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16318
81164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.1631881164
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.3976630755
Short name T1492
Test name
Test status
Simulation time 10079830434 ps
CPU time 13.84 seconds
Started Jun 02 03:28:22 PM PDT 24
Finished Jun 02 03:28:37 PM PDT 24
Peak memory 205748 kb
Host smart-eae48ca3-0cd4-416d-9059-9b278d7cce9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39766
30755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.3976630755
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.163989861
Short name T1828
Test name
Test status
Simulation time 10080304244 ps
CPU time 12.48 seconds
Started Jun 02 03:28:24 PM PDT 24
Finished Jun 02 03:28:37 PM PDT 24
Peak memory 205592 kb
Host smart-9223038b-e0ae-4c76-9b15-d3e2e24506d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16398
9861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.163989861
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.3327096501
Short name T92
Test name
Test status
Simulation time 10183932305 ps
CPU time 12.99 seconds
Started Jun 02 03:28:18 PM PDT 24
Finished Jun 02 03:28:31 PM PDT 24
Peak memory 205712 kb
Host smart-deea3b7d-1280-4646-9a22-0cefb973767d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33270
96501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3327096501
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.1192970900
Short name T73
Test name
Test status
Simulation time 10076589849 ps
CPU time 12.85 seconds
Started Jun 02 03:28:23 PM PDT 24
Finished Jun 02 03:28:36 PM PDT 24
Peak memory 205708 kb
Host smart-5523c7e1-0608-44e3-8404-e6849bb3dedc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11929
70900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.1192970900
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.456200011
Short name T1049
Test name
Test status
Simulation time 10071816734 ps
CPU time 13.29 seconds
Started Jun 02 03:28:30 PM PDT 24
Finished Jun 02 03:28:44 PM PDT 24
Peak memory 205796 kb
Host smart-e9762e21-e6fe-4969-8e44-a2f88e369e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45620
0011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.456200011
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.1369246539
Short name T491
Test name
Test status
Simulation time 21235302694 ps
CPU time 335.27 seconds
Started Jun 02 03:28:22 PM PDT 24
Finished Jun 02 03:33:58 PM PDT 24
Peak memory 205664 kb
Host smart-addaef00-3baa-4405-9e6b-2330c462383c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13692
46539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.1369246539
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.3591124624
Short name T447
Test name
Test status
Simulation time 10158103408 ps
CPU time 14.08 seconds
Started Jun 02 03:28:36 PM PDT 24
Finished Jun 02 03:28:51 PM PDT 24
Peak memory 205732 kb
Host smart-8264a8bc-4a25-4ab6-a8d0-89321f6129bb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3591124624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.3591124624
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.3113450888
Short name T1956
Test name
Test status
Simulation time 10069952263 ps
CPU time 14.61 seconds
Started Jun 02 03:28:35 PM PDT 24
Finished Jun 02 03:28:50 PM PDT 24
Peak memory 205696 kb
Host smart-12f69399-b16a-4cba-936d-157062b989e3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3113450888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.3113450888
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.2536421408
Short name T1588
Test name
Test status
Simulation time 10136299262 ps
CPU time 14.72 seconds
Started Jun 02 03:28:31 PM PDT 24
Finished Jun 02 03:28:46 PM PDT 24
Peak memory 205780 kb
Host smart-bdd10dfb-d703-46fb-aac2-c1575106c353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25364
21408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.2536421408
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.1365485833
Short name T563
Test name
Test status
Simulation time 13461224265 ps
CPU time 15.97 seconds
Started Jun 02 03:28:30 PM PDT 24
Finished Jun 02 03:28:47 PM PDT 24
Peak memory 205808 kb
Host smart-e2f0914c-bf97-48dc-a4d1-c529b5891500
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1365485833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.1365485833
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.3345312877
Short name T1536
Test name
Test status
Simulation time 23218398470 ps
CPU time 30.03 seconds
Started Jun 02 03:28:24 PM PDT 24
Finished Jun 02 03:28:55 PM PDT 24
Peak memory 205612 kb
Host smart-fdef425f-a453-491e-8d6b-7f4445885202
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3345312877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.3345312877
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.4111748549
Short name T1784
Test name
Test status
Simulation time 10081853428 ps
CPU time 14.64 seconds
Started Jun 02 03:28:30 PM PDT 24
Finished Jun 02 03:28:46 PM PDT 24
Peak memory 205800 kb
Host smart-ae65c958-d861-4abe-aa24-a1e02a5cb2b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41117
48549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.4111748549
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.2746664677
Short name T569
Test name
Test status
Simulation time 10408740658 ps
CPU time 14.98 seconds
Started Jun 02 03:28:27 PM PDT 24
Finished Jun 02 03:28:43 PM PDT 24
Peak memory 205696 kb
Host smart-f5504265-4fa2-4fa0-a2d1-0505ce7031aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27466
64677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.2746664677
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.515716077
Short name T1626
Test name
Test status
Simulation time 10056358668 ps
CPU time 14.24 seconds
Started Jun 02 03:28:29 PM PDT 24
Finished Jun 02 03:28:44 PM PDT 24
Peak memory 205752 kb
Host smart-c18426a6-37e6-40d4-a6cf-e1ae8abd6cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51571
6077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.515716077
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.578174086
Short name T429
Test name
Test status
Simulation time 10049984314 ps
CPU time 12.47 seconds
Started Jun 02 03:28:27 PM PDT 24
Finished Jun 02 03:28:41 PM PDT 24
Peak memory 205740 kb
Host smart-d09a8238-166a-46f2-a000-c0b06caa808f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57817
4086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.578174086
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.595761727
Short name T1634
Test name
Test status
Simulation time 10862382875 ps
CPU time 15.29 seconds
Started Jun 02 03:28:26 PM PDT 24
Finished Jun 02 03:28:42 PM PDT 24
Peak memory 205756 kb
Host smart-b6f912d6-11a2-443e-884c-ea78a061dce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59576
1727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.595761727
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.4037257088
Short name T427
Test name
Test status
Simulation time 10083905762 ps
CPU time 15.34 seconds
Started Jun 02 03:28:28 PM PDT 24
Finished Jun 02 03:28:44 PM PDT 24
Peak memory 205588 kb
Host smart-ce460e26-7237-4824-bffd-4cb9d3649b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40372
57088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.4037257088
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.4174831136
Short name T1903
Test name
Test status
Simulation time 10128657182 ps
CPU time 14.77 seconds
Started Jun 02 03:28:33 PM PDT 24
Finished Jun 02 03:28:49 PM PDT 24
Peak memory 205752 kb
Host smart-7bab8edf-4832-4b81-ba7f-81f08e5d3848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41748
31136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.4174831136
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.4047904718
Short name T1294
Test name
Test status
Simulation time 10047782558 ps
CPU time 15.16 seconds
Started Jun 02 03:28:35 PM PDT 24
Finished Jun 02 03:28:50 PM PDT 24
Peak memory 205632 kb
Host smart-c7deba84-3bd5-402e-b049-41f3a26c7ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40479
04718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.4047904718
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1666005342
Short name T1214
Test name
Test status
Simulation time 10097686924 ps
CPU time 15.34 seconds
Started Jun 02 03:28:26 PM PDT 24
Finished Jun 02 03:28:42 PM PDT 24
Peak memory 205676 kb
Host smart-82e98c9b-ddeb-46d1-abfd-347a3e49ba5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16660
05342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1666005342
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.3299272728
Short name T1968
Test name
Test status
Simulation time 10130459874 ps
CPU time 13.66 seconds
Started Jun 02 03:28:25 PM PDT 24
Finished Jun 02 03:28:39 PM PDT 24
Peak memory 205652 kb
Host smart-66f069ca-24c6-4e0d-8cd1-6ef1f970be23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32992
72728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.3299272728
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.3316862579
Short name T506
Test name
Test status
Simulation time 13168621479 ps
CPU time 17.6 seconds
Started Jun 02 03:28:27 PM PDT 24
Finished Jun 02 03:28:45 PM PDT 24
Peak memory 205784 kb
Host smart-e33b2bf7-f58a-4fa1-80e3-765e64964a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33168
62579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.3316862579
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.2305238327
Short name T802
Test name
Test status
Simulation time 10131070462 ps
CPU time 14.3 seconds
Started Jun 02 03:28:30 PM PDT 24
Finished Jun 02 03:28:45 PM PDT 24
Peak memory 205736 kb
Host smart-0e630367-6340-4241-954e-49f23796dd03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23052
38327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.2305238327
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.1189093031
Short name T875
Test name
Test status
Simulation time 22209364127 ps
CPU time 367.93 seconds
Started Jun 02 03:28:27 PM PDT 24
Finished Jun 02 03:34:36 PM PDT 24
Peak memory 205600 kb
Host smart-684aecfe-48d8-42e2-8441-ab7cc0cb42c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11890
93031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.1189093031
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.4068563263
Short name T1080
Test name
Test status
Simulation time 10092978353 ps
CPU time 13.61 seconds
Started Jun 02 03:28:31 PM PDT 24
Finished Jun 02 03:28:46 PM PDT 24
Peak memory 205816 kb
Host smart-eec2c705-39e6-449f-a7dd-03be411d194e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40685
63263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.4068563263
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.876024204
Short name T1171
Test name
Test status
Simulation time 10093487249 ps
CPU time 15.03 seconds
Started Jun 02 03:28:30 PM PDT 24
Finished Jun 02 03:28:46 PM PDT 24
Peak memory 205744 kb
Host smart-ef563578-9d3e-4a84-a8a2-7fe2b90bd0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87602
4204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.876024204
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.3286675542
Short name T398
Test name
Test status
Simulation time 10112937279 ps
CPU time 13.28 seconds
Started Jun 02 03:28:27 PM PDT 24
Finished Jun 02 03:28:41 PM PDT 24
Peak memory 205704 kb
Host smart-1fa36604-d1e0-43b8-9e8c-2ef6690ba600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32866
75542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3286675542
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.3408293794
Short name T1682
Test name
Test status
Simulation time 10075142881 ps
CPU time 13.65 seconds
Started Jun 02 03:28:29 PM PDT 24
Finished Jun 02 03:28:43 PM PDT 24
Peak memory 205760 kb
Host smart-1e8979ef-e93a-4370-b861-df98573d31e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34082
93794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.3408293794
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.2695062835
Short name T1307
Test name
Test status
Simulation time 10057296855 ps
CPU time 17.26 seconds
Started Jun 02 03:28:34 PM PDT 24
Finished Jun 02 03:28:51 PM PDT 24
Peak memory 205760 kb
Host smart-e5920786-8ad2-4347-a922-355528b9aeb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26950
62835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.2695062835
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_eop_single_bit_handling.2859883709
Short name T1316
Test name
Test status
Simulation time 10059270707 ps
CPU time 13.42 seconds
Started Jun 02 03:28:29 PM PDT 24
Finished Jun 02 03:28:43 PM PDT 24
Peak memory 205784 kb
Host smart-5ccbe689-11e7-4e09-9bfa-0c20b65b9080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28598
83709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_eop_single_bit_handling.2859883709
Directory /workspace/13.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1464464624
Short name T50
Test name
Test status
Simulation time 10082058203 ps
CPU time 13.58 seconds
Started Jun 02 03:28:27 PM PDT 24
Finished Jun 02 03:28:42 PM PDT 24
Peak memory 205720 kb
Host smart-dec1a6f0-efb6-4fd0-bbbd-b4b0bd0580fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14644
64624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1464464624
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.3303930745
Short name T1915
Test name
Test status
Simulation time 10026363703 ps
CPU time 13.43 seconds
Started Jun 02 03:28:34 PM PDT 24
Finished Jun 02 03:28:48 PM PDT 24
Peak memory 205756 kb
Host smart-b2f517e5-85da-460c-91ef-ce0b1bc2731c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33039
30745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.3303930745
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1321017881
Short name T1892
Test name
Test status
Simulation time 20327718628 ps
CPU time 36.71 seconds
Started Jun 02 03:28:31 PM PDT 24
Finished Jun 02 03:29:08 PM PDT 24
Peak memory 205604 kb
Host smart-8b079d71-432b-4251-8976-2f5a99a08a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13210
17881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1321017881
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.3103798558
Short name T1745
Test name
Test status
Simulation time 10086077479 ps
CPU time 15.11 seconds
Started Jun 02 03:28:26 PM PDT 24
Finished Jun 02 03:28:42 PM PDT 24
Peak memory 206012 kb
Host smart-4b2b5dbb-5168-45a1-acaa-06b9cea25219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31037
98558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.3103798558
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.4121008663
Short name T1000
Test name
Test status
Simulation time 10072662889 ps
CPU time 13.78 seconds
Started Jun 02 03:28:33 PM PDT 24
Finished Jun 02 03:28:47 PM PDT 24
Peak memory 205760 kb
Host smart-fbccfff0-c3b9-4fa5-bfda-bace6bd776e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41210
08663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.4121008663
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.4288658044
Short name T1451
Test name
Test status
Simulation time 10075573731 ps
CPU time 15.6 seconds
Started Jun 02 03:28:27 PM PDT 24
Finished Jun 02 03:28:44 PM PDT 24
Peak memory 205592 kb
Host smart-3b908c07-6e0c-4e23-90b4-ec6a4a7d086a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42886
58044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.4288658044
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.27119370
Short name T1236
Test name
Test status
Simulation time 10040680064 ps
CPU time 15.42 seconds
Started Jun 02 03:28:28 PM PDT 24
Finished Jun 02 03:28:45 PM PDT 24
Peak memory 205752 kb
Host smart-0b27106a-db2c-4bd1-b916-8ba5505c3968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27119
370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.27119370
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.202220259
Short name T1375
Test name
Test status
Simulation time 10050026146 ps
CPU time 14.63 seconds
Started Jun 02 03:28:34 PM PDT 24
Finished Jun 02 03:28:49 PM PDT 24
Peak memory 205632 kb
Host smart-34568699-092f-487b-a18c-003d36cf3264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20222
0259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.202220259
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.1588226168
Short name T1978
Test name
Test status
Simulation time 10073589023 ps
CPU time 16.11 seconds
Started Jun 02 03:28:26 PM PDT 24
Finished Jun 02 03:28:42 PM PDT 24
Peak memory 205676 kb
Host smart-e7f88bf6-7f98-4843-956f-bf7e3dd2f98d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15882
26168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.1588226168
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.151548617
Short name T1146
Test name
Test status
Simulation time 10096654172 ps
CPU time 13.48 seconds
Started Jun 02 03:28:29 PM PDT 24
Finished Jun 02 03:28:43 PM PDT 24
Peak memory 205696 kb
Host smart-0e0c2d61-ee8f-4712-93dc-660e44c4af53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15154
8617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.151548617
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.1980864001
Short name T819
Test name
Test status
Simulation time 10080540279 ps
CPU time 17.82 seconds
Started Jun 02 03:28:26 PM PDT 24
Finished Jun 02 03:28:44 PM PDT 24
Peak memory 205748 kb
Host smart-364c8fd6-0baa-4692-b86d-5f465a8d3ae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19808
64001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.1980864001
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.2204809344
Short name T1054
Test name
Test status
Simulation time 22059625355 ps
CPU time 125.61 seconds
Started Jun 02 03:28:29 PM PDT 24
Finished Jun 02 03:30:35 PM PDT 24
Peak memory 205764 kb
Host smart-f9c7fe4e-a768-4a6b-be91-9283a079871c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22048
09344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.2204809344
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.302419264
Short name T1910
Test name
Test status
Simulation time 10224503916 ps
CPU time 14.92 seconds
Started Jun 02 03:28:42 PM PDT 24
Finished Jun 02 03:28:57 PM PDT 24
Peak memory 205592 kb
Host smart-71f52ff9-8721-42cf-bb70-8fb969c800f8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=302419264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.302419264
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.2898867152
Short name T603
Test name
Test status
Simulation time 10082730896 ps
CPU time 14.08 seconds
Started Jun 02 03:28:44 PM PDT 24
Finished Jun 02 03:28:59 PM PDT 24
Peak memory 205648 kb
Host smart-43854abb-5c7b-4859-a9d6-d434076208d6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2898867152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.2898867152
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.2749833893
Short name T421
Test name
Test status
Simulation time 10114372149 ps
CPU time 13.3 seconds
Started Jun 02 03:28:49 PM PDT 24
Finished Jun 02 03:29:03 PM PDT 24
Peak memory 205704 kb
Host smart-34e6c8b0-7089-4fe4-802e-f03155b0e091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27498
33893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.2749833893
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.1752026412
Short name T513
Test name
Test status
Simulation time 13563828272 ps
CPU time 17.32 seconds
Started Jun 02 03:28:36 PM PDT 24
Finished Jun 02 03:28:55 PM PDT 24
Peak memory 205728 kb
Host smart-8aa4ab00-e74e-49a7-9435-0d8f83ef42cb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1752026412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.1752026412
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.1233441494
Short name T1166
Test name
Test status
Simulation time 23257463452 ps
CPU time 28.32 seconds
Started Jun 02 03:28:31 PM PDT 24
Finished Jun 02 03:29:00 PM PDT 24
Peak memory 205700 kb
Host smart-6dcbb69f-dedb-434d-803c-97486ea7a45b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1233441494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.1233441494
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.536692276
Short name T1793
Test name
Test status
Simulation time 10073896416 ps
CPU time 13.37 seconds
Started Jun 02 03:28:33 PM PDT 24
Finished Jun 02 03:28:47 PM PDT 24
Peak memory 205748 kb
Host smart-bf319ada-ba61-4d43-ba71-9bda6d1ad04b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53669
2276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.536692276
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.3530668940
Short name T1629
Test name
Test status
Simulation time 10646357552 ps
CPU time 16.4 seconds
Started Jun 02 03:28:32 PM PDT 24
Finished Jun 02 03:28:49 PM PDT 24
Peak memory 205724 kb
Host smart-40381bac-9756-4024-ab3c-17108a07eca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35306
68940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.3530668940
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.3473257444
Short name T65
Test name
Test status
Simulation time 10115899656 ps
CPU time 13.23 seconds
Started Jun 02 03:28:37 PM PDT 24
Finished Jun 02 03:28:52 PM PDT 24
Peak memory 205764 kb
Host smart-dca54bb2-47ec-4ee4-baa1-8bb6e31d6fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34732
57444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.3473257444
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.4067805786
Short name T1349
Test name
Test status
Simulation time 10051066987 ps
CPU time 14.33 seconds
Started Jun 02 03:28:37 PM PDT 24
Finished Jun 02 03:28:52 PM PDT 24
Peak memory 205624 kb
Host smart-307ee184-4b7d-4bbe-ace1-6678113442ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40678
05786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.4067805786
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.4025583586
Short name T1812
Test name
Test status
Simulation time 10727754859 ps
CPU time 14.52 seconds
Started Jun 02 03:28:36 PM PDT 24
Finished Jun 02 03:28:52 PM PDT 24
Peak memory 205628 kb
Host smart-86e91a3a-fe89-4ab6-89f9-31a874867af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40255
83586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.4025583586
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.995369165
Short name T2021
Test name
Test status
Simulation time 10113951437 ps
CPU time 14.02 seconds
Started Jun 02 03:28:38 PM PDT 24
Finished Jun 02 03:28:53 PM PDT 24
Peak memory 205744 kb
Host smart-d7d41c44-0043-44a0-b9de-fb3e70d7e234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99536
9165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.995369165
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.3649502766
Short name T1517
Test name
Test status
Simulation time 10103701424 ps
CPU time 14.03 seconds
Started Jun 02 03:28:45 PM PDT 24
Finished Jun 02 03:28:59 PM PDT 24
Peak memory 205792 kb
Host smart-96d47518-962f-4272-a0df-6d3c8c289cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36495
02766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.3649502766
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.120324825
Short name T1569
Test name
Test status
Simulation time 10111764241 ps
CPU time 12.95 seconds
Started Jun 02 03:28:43 PM PDT 24
Finished Jun 02 03:28:57 PM PDT 24
Peak memory 205680 kb
Host smart-466e6613-63ac-47ea-939e-fd5bc25c4326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12032
4825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.120324825
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2174159523
Short name T1403
Test name
Test status
Simulation time 10077350738 ps
CPU time 13.91 seconds
Started Jun 02 03:28:35 PM PDT 24
Finished Jun 02 03:28:50 PM PDT 24
Peak memory 205768 kb
Host smart-bb6e07bd-c852-4bf7-9a50-ea95ec8d5c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21741
59523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2174159523
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.3728626890
Short name T1422
Test name
Test status
Simulation time 10135799748 ps
CPU time 13.31 seconds
Started Jun 02 03:28:35 PM PDT 24
Finished Jun 02 03:28:50 PM PDT 24
Peak memory 205792 kb
Host smart-aebd630c-3769-4e4a-96a6-3b00959a635b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37286
26890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.3728626890
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.3942471916
Short name T422
Test name
Test status
Simulation time 13219028868 ps
CPU time 19.17 seconds
Started Jun 02 03:28:35 PM PDT 24
Finished Jun 02 03:28:55 PM PDT 24
Peak memory 205864 kb
Host smart-3506d20c-90c3-49e7-bf8e-2fcbbb6edef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39424
71916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.3942471916
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.461264958
Short name T829
Test name
Test status
Simulation time 10131710445 ps
CPU time 15.6 seconds
Started Jun 02 03:28:36 PM PDT 24
Finished Jun 02 03:28:52 PM PDT 24
Peak memory 205752 kb
Host smart-a76b23f8-0ed4-4a68-b13e-d1caf32a9d2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46126
4958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.461264958
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.1594168130
Short name T1571
Test name
Test status
Simulation time 18486659272 ps
CPU time 98.28 seconds
Started Jun 02 03:28:37 PM PDT 24
Finished Jun 02 03:30:16 PM PDT 24
Peak memory 205636 kb
Host smart-776176ab-c031-4923-acf3-c87e69d3ba73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15941
68130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.1594168130
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.2505196416
Short name T739
Test name
Test status
Simulation time 10060711606 ps
CPU time 13.84 seconds
Started Jun 02 03:28:38 PM PDT 24
Finished Jun 02 03:28:53 PM PDT 24
Peak memory 205740 kb
Host smart-5e3fb9e1-a56e-43b5-9d52-90b983838cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25051
96416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.2505196416
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3041435139
Short name T104
Test name
Test status
Simulation time 10113054049 ps
CPU time 13.02 seconds
Started Jun 02 03:28:36 PM PDT 24
Finished Jun 02 03:28:49 PM PDT 24
Peak memory 205708 kb
Host smart-34411c44-4072-4fcf-8dc6-be807db37d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30414
35139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3041435139
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.555267034
Short name T1707
Test name
Test status
Simulation time 10053268620 ps
CPU time 13.78 seconds
Started Jun 02 03:28:36 PM PDT 24
Finished Jun 02 03:28:50 PM PDT 24
Peak memory 205668 kb
Host smart-0bb604fb-4e18-4cc5-b1f5-14721b6c67a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55526
7034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.555267034
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1192092247
Short name T419
Test name
Test status
Simulation time 10074747318 ps
CPU time 13.28 seconds
Started Jun 02 03:28:36 PM PDT 24
Finished Jun 02 03:28:50 PM PDT 24
Peak memory 205656 kb
Host smart-2c8da40a-29b5-492c-9dcf-53e389c17d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11920
92247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1192092247
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.3134336992
Short name T1056
Test name
Test status
Simulation time 10050021417 ps
CPU time 13.83 seconds
Started Jun 02 03:28:36 PM PDT 24
Finished Jun 02 03:28:51 PM PDT 24
Peak memory 205700 kb
Host smart-c6a4e4ed-02ac-4abb-b21e-b77741d18fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31343
36992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.3134336992
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.1032929924
Short name T134
Test name
Test status
Simulation time 10126656023 ps
CPU time 15.3 seconds
Started Jun 02 03:28:38 PM PDT 24
Finished Jun 02 03:28:54 PM PDT 24
Peak memory 205788 kb
Host smart-5bc19edc-ed04-41a6-b7e6-5b06e942be66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10329
29924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.1032929924
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_eop_single_bit_handling.2703764392
Short name T757
Test name
Test status
Simulation time 10090245941 ps
CPU time 16.39 seconds
Started Jun 02 03:28:37 PM PDT 24
Finished Jun 02 03:28:54 PM PDT 24
Peak memory 205616 kb
Host smart-50caeed3-9b78-4ac4-b561-6298653ed7e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27037
64392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_eop_single_bit_handling.2703764392
Directory /workspace/14.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.2035960839
Short name T1110
Test name
Test status
Simulation time 10065645569 ps
CPU time 15.51 seconds
Started Jun 02 03:28:37 PM PDT 24
Finished Jun 02 03:28:54 PM PDT 24
Peak memory 205788 kb
Host smart-cb38dc7d-1d1a-4aee-8135-f987f3e2d43c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20359
60839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.2035960839
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2725707587
Short name T523
Test name
Test status
Simulation time 10035316290 ps
CPU time 13.93 seconds
Started Jun 02 03:28:38 PM PDT 24
Finished Jun 02 03:28:53 PM PDT 24
Peak memory 205712 kb
Host smart-7b5f6f4a-d932-4c28-a929-9fbe4d0f6d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27257
07587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2725707587
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.2519705209
Short name T947
Test name
Test status
Simulation time 16367654813 ps
CPU time 27.03 seconds
Started Jun 02 03:28:39 PM PDT 24
Finished Jun 02 03:29:07 PM PDT 24
Peak memory 205684 kb
Host smart-4cbce788-3619-4c06-ad5f-93c22a720fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25197
05209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.2519705209
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.794134621
Short name T512
Test name
Test status
Simulation time 10072905058 ps
CPU time 13.84 seconds
Started Jun 02 03:28:39 PM PDT 24
Finished Jun 02 03:28:53 PM PDT 24
Peak memory 205656 kb
Host smart-bb4bb2be-31ce-444f-80cd-d0fa79b1ed4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79413
4621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.794134621
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.3655832938
Short name T1894
Test name
Test status
Simulation time 10114768547 ps
CPU time 14.12 seconds
Started Jun 02 03:28:36 PM PDT 24
Finished Jun 02 03:28:51 PM PDT 24
Peak memory 205640 kb
Host smart-de34f924-2f06-41b5-af22-3104d1788fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36558
32938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.3655832938
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.2936656452
Short name T1112
Test name
Test status
Simulation time 10059131803 ps
CPU time 13.79 seconds
Started Jun 02 03:28:40 PM PDT 24
Finished Jun 02 03:28:54 PM PDT 24
Peak memory 205656 kb
Host smart-0139de5f-a2ee-461d-abe5-57e1be204c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29366
56452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.2936656452
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.4254115791
Short name T1293
Test name
Test status
Simulation time 10112768385 ps
CPU time 14.16 seconds
Started Jun 02 03:28:36 PM PDT 24
Finished Jun 02 03:28:52 PM PDT 24
Peak memory 205748 kb
Host smart-0724b98e-d800-4eaa-8a52-8b8cf5bc5659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42541
15791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.4254115791
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.2027307744
Short name T608
Test name
Test status
Simulation time 10044051353 ps
CPU time 13.24 seconds
Started Jun 02 03:28:36 PM PDT 24
Finished Jun 02 03:28:50 PM PDT 24
Peak memory 205760 kb
Host smart-09ca6e63-6fd3-4eb8-aa3d-f0e72975a7a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20273
07744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.2027307744
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.237182721
Short name T546
Test name
Test status
Simulation time 10042700073 ps
CPU time 16.39 seconds
Started Jun 02 03:28:36 PM PDT 24
Finished Jun 02 03:28:54 PM PDT 24
Peak memory 205648 kb
Host smart-bc64cae4-60fc-4f95-964b-a6fc011751e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23718
2721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.237182721
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.3681578379
Short name T1484
Test name
Test status
Simulation time 10109653234 ps
CPU time 15.1 seconds
Started Jun 02 03:28:30 PM PDT 24
Finished Jun 02 03:28:46 PM PDT 24
Peak memory 205684 kb
Host smart-4cd2e7b1-fc4d-43cd-a334-1c935fd68e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36815
78379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.3681578379
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.57087333
Short name T1410
Test name
Test status
Simulation time 10090061632 ps
CPU time 13.54 seconds
Started Jun 02 03:28:38 PM PDT 24
Finished Jun 02 03:28:52 PM PDT 24
Peak memory 205732 kb
Host smart-d95b65c8-1efa-46aa-a10c-35f24ef97678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57087
333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.57087333
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.310577538
Short name T74
Test name
Test status
Simulation time 10084381508 ps
CPU time 14.21 seconds
Started Jun 02 03:28:37 PM PDT 24
Finished Jun 02 03:28:52 PM PDT 24
Peak memory 205640 kb
Host smart-6a8b29cd-4572-44a5-b9f9-6e20737919f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31057
7538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.310577538
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.1858083156
Short name T1495
Test name
Test status
Simulation time 19539178306 ps
CPU time 277.44 seconds
Started Jun 02 03:28:36 PM PDT 24
Finished Jun 02 03:33:14 PM PDT 24
Peak memory 205644 kb
Host smart-4de80d9c-043b-4767-8c24-4ef9dfe0a2f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18580
83156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.1858083156
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.1398533490
Short name T658
Test name
Test status
Simulation time 10156985791 ps
CPU time 14.09 seconds
Started Jun 02 03:28:49 PM PDT 24
Finished Jun 02 03:29:04 PM PDT 24
Peak memory 205696 kb
Host smart-10810508-dd17-4d88-9e4e-0cc5383030d6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1398533490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.1398533490
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.2492204423
Short name T1459
Test name
Test status
Simulation time 10101737411 ps
CPU time 15.56 seconds
Started Jun 02 03:28:51 PM PDT 24
Finished Jun 02 03:29:08 PM PDT 24
Peak memory 205724 kb
Host smart-5a35f7b6-12df-4c93-8c92-5d976b083533
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2492204423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.2492204423
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.3755956042
Short name T777
Test name
Test status
Simulation time 10062174206 ps
CPU time 13.53 seconds
Started Jun 02 03:28:46 PM PDT 24
Finished Jun 02 03:29:00 PM PDT 24
Peak memory 205696 kb
Host smart-b2b3bb87-3259-4d31-a81c-aa5bdd0b24ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37559
56042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.3755956042
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.3307697982
Short name T1031
Test name
Test status
Simulation time 13874717549 ps
CPU time 18.78 seconds
Started Jun 02 03:28:45 PM PDT 24
Finished Jun 02 03:29:04 PM PDT 24
Peak memory 205716 kb
Host smart-939f0d0b-6180-49fd-bd10-ba2de0ad7c78
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3307697982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.3307697982
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.1655027794
Short name T592
Test name
Test status
Simulation time 23396491049 ps
CPU time 24.62 seconds
Started Jun 02 03:28:42 PM PDT 24
Finished Jun 02 03:29:08 PM PDT 24
Peak memory 205668 kb
Host smart-a885e84a-3f27-4c87-b6ea-316a9e5f326d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1655027794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.1655027794
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2080614294
Short name T1191
Test name
Test status
Simulation time 10060824064 ps
CPU time 15.03 seconds
Started Jun 02 03:28:42 PM PDT 24
Finished Jun 02 03:28:57 PM PDT 24
Peak memory 205752 kb
Host smart-f6e3ce35-c3f0-4dae-8c3d-13ec440dd704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20806
14294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2080614294
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.827551388
Short name T711
Test name
Test status
Simulation time 10502802452 ps
CPU time 14.66 seconds
Started Jun 02 03:28:44 PM PDT 24
Finished Jun 02 03:28:59 PM PDT 24
Peak memory 205652 kb
Host smart-adf9f3da-132a-4e5c-b845-2501584c76c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82755
1388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.827551388
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.2711489068
Short name T1304
Test name
Test status
Simulation time 10068140473 ps
CPU time 14.87 seconds
Started Jun 02 03:28:43 PM PDT 24
Finished Jun 02 03:28:59 PM PDT 24
Peak memory 205736 kb
Host smart-acc89062-8ffa-4b18-a21b-a64769e94c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27114
89068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.2711489068
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.3305687012
Short name T1145
Test name
Test status
Simulation time 10057708271 ps
CPU time 15.28 seconds
Started Jun 02 03:28:42 PM PDT 24
Finished Jun 02 03:28:58 PM PDT 24
Peak memory 205708 kb
Host smart-54caa6ca-24b2-486a-b85e-226ff28e6227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33056
87012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.3305687012
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.3129776980
Short name T1513
Test name
Test status
Simulation time 10845062073 ps
CPU time 14.94 seconds
Started Jun 02 03:28:46 PM PDT 24
Finished Jun 02 03:29:01 PM PDT 24
Peak memory 205736 kb
Host smart-2e323bf0-55cf-4d12-b196-1bf8c538d1d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31297
76980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.3129776980
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.1021236115
Short name T1335
Test name
Test status
Simulation time 10264778734 ps
CPU time 15.08 seconds
Started Jun 02 03:28:43 PM PDT 24
Finished Jun 02 03:28:59 PM PDT 24
Peak memory 205668 kb
Host smart-d6261c5d-623c-450c-a334-541dc1646b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10212
36115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.1021236115
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.1777101035
Short name T883
Test name
Test status
Simulation time 10226127390 ps
CPU time 13.85 seconds
Started Jun 02 03:28:49 PM PDT 24
Finished Jun 02 03:29:04 PM PDT 24
Peak memory 205676 kb
Host smart-c83ebeee-2314-4c79-925b-735afe5337af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17771
01035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.1777101035
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.959420014
Short name T1766
Test name
Test status
Simulation time 10048257148 ps
CPU time 12.8 seconds
Started Jun 02 03:28:52 PM PDT 24
Finished Jun 02 03:29:06 PM PDT 24
Peak memory 205620 kb
Host smart-4ac39a6a-f324-4874-a23a-125186370847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95942
0014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.959420014
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2728965606
Short name T327
Test name
Test status
Simulation time 10090892093 ps
CPU time 13.29 seconds
Started Jun 02 03:28:43 PM PDT 24
Finished Jun 02 03:28:58 PM PDT 24
Peak memory 205688 kb
Host smart-26c8af7d-afe5-4044-b6cf-a8268b52ff64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27289
65606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2728965606
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.1129558045
Short name T1415
Test name
Test status
Simulation time 10195388378 ps
CPU time 13.71 seconds
Started Jun 02 03:28:45 PM PDT 24
Finished Jun 02 03:28:59 PM PDT 24
Peak memory 205664 kb
Host smart-5b708190-c82d-4e17-8a45-49204cdb4821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11295
58045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.1129558045
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.2152192445
Short name T326
Test name
Test status
Simulation time 13244723507 ps
CPU time 15.64 seconds
Started Jun 02 03:28:45 PM PDT 24
Finished Jun 02 03:29:01 PM PDT 24
Peak memory 205616 kb
Host smart-2d4f5316-0ad6-431e-8e71-422f5006988c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21521
92445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.2152192445
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.2559746091
Short name T533
Test name
Test status
Simulation time 10099175361 ps
CPU time 13.81 seconds
Started Jun 02 03:28:43 PM PDT 24
Finished Jun 02 03:28:57 PM PDT 24
Peak memory 205748 kb
Host smart-f46e5053-29f7-4399-940b-42f5ec32a985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25597
46091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.2559746091
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.1311219928
Short name T472
Test name
Test status
Simulation time 23977447435 ps
CPU time 149.03 seconds
Started Jun 02 03:28:43 PM PDT 24
Finished Jun 02 03:31:13 PM PDT 24
Peak memory 205612 kb
Host smart-211f99c8-e4da-4ad0-a809-dfd40ba9d1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13112
19928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.1311219928
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.4069960816
Short name T916
Test name
Test status
Simulation time 10054397274 ps
CPU time 14.19 seconds
Started Jun 02 03:28:45 PM PDT 24
Finished Jun 02 03:29:00 PM PDT 24
Peak memory 205756 kb
Host smart-3c80ef83-8ea5-445e-b458-27312bc836c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40699
60816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.4069960816
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.65673032
Short name T23
Test name
Test status
Simulation time 10174049788 ps
CPU time 13.13 seconds
Started Jun 02 03:28:44 PM PDT 24
Finished Jun 02 03:28:58 PM PDT 24
Peak memory 205700 kb
Host smart-646eaf0e-685c-41ff-8bb8-2ffba8055bc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65673
032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.65673032
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.3449759662
Short name T71
Test name
Test status
Simulation time 10054855506 ps
CPU time 13.89 seconds
Started Jun 02 03:28:43 PM PDT 24
Finished Jun 02 03:28:58 PM PDT 24
Peak memory 205720 kb
Host smart-ab8069d0-919d-481c-9a50-3a7e0bdde93f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34497
59662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.3449759662
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.231758366
Short name T1390
Test name
Test status
Simulation time 10074657275 ps
CPU time 12.52 seconds
Started Jun 02 03:28:44 PM PDT 24
Finished Jun 02 03:28:57 PM PDT 24
Peak memory 205748 kb
Host smart-f157b17c-999f-4855-bb7a-f667eabdd7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23175
8366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.231758366
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.2319949922
Short name T1619
Test name
Test status
Simulation time 10082526446 ps
CPU time 12.71 seconds
Started Jun 02 03:28:52 PM PDT 24
Finished Jun 02 03:29:06 PM PDT 24
Peak memory 205716 kb
Host smart-bd3f333a-7353-44d8-90fd-c85adabbe7d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23199
49922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2319949922
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.2498757011
Short name T139
Test name
Test status
Simulation time 10073695338 ps
CPU time 13.6 seconds
Started Jun 02 03:28:48 PM PDT 24
Finished Jun 02 03:29:02 PM PDT 24
Peak memory 205684 kb
Host smart-7268321c-76be-4b5c-a438-777acf66a9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24987
57011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.2498757011
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_eop_single_bit_handling.2438653222
Short name T1678
Test name
Test status
Simulation time 10072759564 ps
CPU time 12.96 seconds
Started Jun 02 03:28:46 PM PDT 24
Finished Jun 02 03:28:59 PM PDT 24
Peak memory 205624 kb
Host smart-46bd334b-e446-41ac-9af8-50c42ef0a6c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24386
53222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_eop_single_bit_handling.2438653222
Directory /workspace/15.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.2164465894
Short name T64
Test name
Test status
Simulation time 10062507260 ps
CPU time 13.92 seconds
Started Jun 02 03:28:46 PM PDT 24
Finished Jun 02 03:29:01 PM PDT 24
Peak memory 205808 kb
Host smart-3df86087-1aea-4f94-9739-594c2dfcc6f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21644
65894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.2164465894
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3127327602
Short name T321
Test name
Test status
Simulation time 10053288481 ps
CPU time 15.17 seconds
Started Jun 02 03:28:48 PM PDT 24
Finished Jun 02 03:29:04 PM PDT 24
Peak memory 205740 kb
Host smart-79d0a994-c4a9-417b-9c0a-334c5370bdb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31273
27602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3127327602
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.515131361
Short name T691
Test name
Test status
Simulation time 25480758073 ps
CPU time 48.69 seconds
Started Jun 02 03:28:47 PM PDT 24
Finished Jun 02 03:29:37 PM PDT 24
Peak memory 205636 kb
Host smart-080ef7a7-1bc5-4b4a-83a2-8e259f988a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51513
1361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.515131361
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.1537974792
Short name T645
Test name
Test status
Simulation time 10131050573 ps
CPU time 13.25 seconds
Started Jun 02 03:28:49 PM PDT 24
Finished Jun 02 03:29:03 PM PDT 24
Peak memory 205728 kb
Host smart-1055e236-00e0-41f3-b93d-71c346a01e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15379
74792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1537974792
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3941255320
Short name T1636
Test name
Test status
Simulation time 10152980325 ps
CPU time 13.49 seconds
Started Jun 02 03:28:51 PM PDT 24
Finished Jun 02 03:29:06 PM PDT 24
Peak memory 205628 kb
Host smart-ae55d820-a7ee-4044-8382-3c4a1f79a4c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39412
55320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3941255320
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.1802473951
Short name T1515
Test name
Test status
Simulation time 10049459466 ps
CPU time 15.06 seconds
Started Jun 02 03:28:47 PM PDT 24
Finished Jun 02 03:29:03 PM PDT 24
Peak memory 205636 kb
Host smart-ef17187d-d9c0-4712-810e-191d1a323c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18024
73951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.1802473951
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.1318046695
Short name T61
Test name
Test status
Simulation time 10089545266 ps
CPU time 13.53 seconds
Started Jun 02 03:28:53 PM PDT 24
Finished Jun 02 03:29:07 PM PDT 24
Peak memory 205736 kb
Host smart-bb52d1c8-e818-433e-81df-265d419ac857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13180
46695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.1318046695
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.783453671
Short name T895
Test name
Test status
Simulation time 10048984174 ps
CPU time 13.31 seconds
Started Jun 02 03:28:48 PM PDT 24
Finished Jun 02 03:29:02 PM PDT 24
Peak memory 205776 kb
Host smart-360af157-5c4f-4430-9a14-721b25e8a0d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78345
3671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.783453671
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2207755216
Short name T361
Test name
Test status
Simulation time 10130210364 ps
CPU time 13.53 seconds
Started Jun 02 03:28:45 PM PDT 24
Finished Jun 02 03:29:00 PM PDT 24
Peak memory 205796 kb
Host smart-3558e9c7-1729-4a82-903c-fc4545c6c590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22077
55216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2207755216
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.266427594
Short name T1586
Test name
Test status
Simulation time 10094049944 ps
CPU time 13.37 seconds
Started Jun 02 03:28:51 PM PDT 24
Finished Jun 02 03:29:05 PM PDT 24
Peak memory 205676 kb
Host smart-7415c7b3-a1b1-43c2-bac5-379302c30f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26642
7594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.266427594
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.1394994187
Short name T406
Test name
Test status
Simulation time 10066525432 ps
CPU time 15.16 seconds
Started Jun 02 03:28:48 PM PDT 24
Finished Jun 02 03:29:04 PM PDT 24
Peak memory 205736 kb
Host smart-1b7281f0-fe62-4f33-b52f-64173e14740d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13949
94187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.1394994187
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.160623166
Short name T449
Test name
Test status
Simulation time 13965255757 ps
CPU time 40.82 seconds
Started Jun 02 03:28:48 PM PDT 24
Finished Jun 02 03:29:30 PM PDT 24
Peak memory 205680 kb
Host smart-91c621a9-f523-494a-be97-34b3661b37b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16062
3166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.160623166
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.3825773156
Short name T540
Test name
Test status
Simulation time 10147102859 ps
CPU time 13.01 seconds
Started Jun 02 03:29:00 PM PDT 24
Finished Jun 02 03:29:13 PM PDT 24
Peak memory 205748 kb
Host smart-aac20f39-3493-4f23-a7e3-b8b85aaf10a3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3825773156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.3825773156
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.3761421190
Short name T745
Test name
Test status
Simulation time 10074646974 ps
CPU time 12.74 seconds
Started Jun 02 03:28:56 PM PDT 24
Finished Jun 02 03:29:09 PM PDT 24
Peak memory 205676 kb
Host smart-ea06ade4-816f-43e4-bda4-6b28b6cbb6bc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3761421190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.3761421190
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.2494900266
Short name T504
Test name
Test status
Simulation time 10075752681 ps
CPU time 13.95 seconds
Started Jun 02 03:28:55 PM PDT 24
Finished Jun 02 03:29:10 PM PDT 24
Peak memory 205732 kb
Host smart-210b0c4a-b30f-4be5-a79f-dc10f40f6aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24949
00266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.2494900266
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.792639905
Short name T928
Test name
Test status
Simulation time 14281387860 ps
CPU time 18.9 seconds
Started Jun 02 03:28:48 PM PDT 24
Finished Jun 02 03:29:07 PM PDT 24
Peak memory 205768 kb
Host smart-64fdaccb-59b1-4e37-a590-d67d6cc8e8e2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=792639905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.792639905
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.3590132136
Short name T528
Test name
Test status
Simulation time 23280421451 ps
CPU time 24.94 seconds
Started Jun 02 03:28:48 PM PDT 24
Finished Jun 02 03:29:14 PM PDT 24
Peak memory 205704 kb
Host smart-00b4fb6f-240a-47bb-b1b5-631450f8dec1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3590132136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.3590132136
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2478473196
Short name T966
Test name
Test status
Simulation time 10077138403 ps
CPU time 12.77 seconds
Started Jun 02 03:28:49 PM PDT 24
Finished Jun 02 03:29:03 PM PDT 24
Peak memory 205708 kb
Host smart-bc1ec5b4-e6f7-4eb9-9451-8e6eda25b3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24784
73196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2478473196
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1131825742
Short name T833
Test name
Test status
Simulation time 11136212051 ps
CPU time 14.67 seconds
Started Jun 02 03:28:48 PM PDT 24
Finished Jun 02 03:29:04 PM PDT 24
Peak memory 205732 kb
Host smart-5dbc2523-de96-41c2-a99d-783353b84b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11318
25742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1131825742
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.3395147705
Short name T1888
Test name
Test status
Simulation time 10043665810 ps
CPU time 13.69 seconds
Started Jun 02 03:28:51 PM PDT 24
Finished Jun 02 03:29:05 PM PDT 24
Peak memory 205676 kb
Host smart-b645efe1-d4e3-40fa-bcd4-61b35b5195fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33951
47705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.3395147705
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1224456828
Short name T1263
Test name
Test status
Simulation time 10043423931 ps
CPU time 14.62 seconds
Started Jun 02 03:28:51 PM PDT 24
Finished Jun 02 03:29:06 PM PDT 24
Peak memory 205660 kb
Host smart-7fe26b52-734c-44fb-b350-2385e27c19f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12244
56828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1224456828
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.2154381002
Short name T722
Test name
Test status
Simulation time 10825741574 ps
CPU time 16.07 seconds
Started Jun 02 03:28:49 PM PDT 24
Finished Jun 02 03:29:06 PM PDT 24
Peak memory 205860 kb
Host smart-a9b6e227-70c4-4aea-a0f1-69a2a1f5a579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21543
81002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.2154381002
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.2118567219
Short name T1830
Test name
Test status
Simulation time 10191548468 ps
CPU time 15.88 seconds
Started Jun 02 03:28:46 PM PDT 24
Finished Jun 02 03:29:03 PM PDT 24
Peak memory 205748 kb
Host smart-888fa116-aa3b-4882-a729-244cc88314d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21185
67219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.2118567219
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.77354847
Short name T82
Test name
Test status
Simulation time 10106550505 ps
CPU time 12.98 seconds
Started Jun 02 03:28:51 PM PDT 24
Finished Jun 02 03:29:05 PM PDT 24
Peak memory 205732 kb
Host smart-489f7969-a54c-45e4-b4e0-31df60ea236b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77354
847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.77354847
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.3937927247
Short name T1034
Test name
Test status
Simulation time 10046342273 ps
CPU time 13.54 seconds
Started Jun 02 03:28:52 PM PDT 24
Finished Jun 02 03:29:07 PM PDT 24
Peak memory 205664 kb
Host smart-0e49949a-e540-4fa2-8880-b15798fefab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39379
27247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3937927247
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.704212917
Short name T708
Test name
Test status
Simulation time 10129095933 ps
CPU time 15.32 seconds
Started Jun 02 03:28:49 PM PDT 24
Finished Jun 02 03:29:05 PM PDT 24
Peak memory 205692 kb
Host smart-4c172f82-dd37-446d-b0c0-6b5cab95b42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70421
2917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.704212917
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.2743889102
Short name T1199
Test name
Test status
Simulation time 10159308537 ps
CPU time 15.5 seconds
Started Jun 02 03:28:53 PM PDT 24
Finished Jun 02 03:29:09 PM PDT 24
Peak memory 205736 kb
Host smart-68436025-751e-4188-991d-c3cfa8efdd94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27438
89102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.2743889102
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.1869749648
Short name T1229
Test name
Test status
Simulation time 13272770853 ps
CPU time 19.28 seconds
Started Jun 02 03:28:48 PM PDT 24
Finished Jun 02 03:29:08 PM PDT 24
Peak memory 205764 kb
Host smart-1a0cb5f4-b8aa-4ef8-8143-9d8f40371dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18697
49648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.1869749648
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.836603854
Short name T1893
Test name
Test status
Simulation time 10086767626 ps
CPU time 17.21 seconds
Started Jun 02 03:28:48 PM PDT 24
Finished Jun 02 03:29:06 PM PDT 24
Peak memory 205864 kb
Host smart-7694acf9-a977-46ad-8c51-6e625f5e8283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83660
3854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.836603854
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.427817770
Short name T1036
Test name
Test status
Simulation time 14939308111 ps
CPU time 60.9 seconds
Started Jun 02 03:28:52 PM PDT 24
Finished Jun 02 03:29:54 PM PDT 24
Peak memory 205664 kb
Host smart-961c8c12-a8c9-464c-b00f-066ee2abe3b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42781
7770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.427817770
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1255628827
Short name T509
Test name
Test status
Simulation time 10068578717 ps
CPU time 15.75 seconds
Started Jun 02 03:28:53 PM PDT 24
Finished Jun 02 03:29:09 PM PDT 24
Peak memory 205712 kb
Host smart-08f43c0d-b594-4376-849d-d608d2a3b5e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12556
28827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1255628827
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.447985952
Short name T1674
Test name
Test status
Simulation time 10116109504 ps
CPU time 16.51 seconds
Started Jun 02 03:28:47 PM PDT 24
Finished Jun 02 03:29:04 PM PDT 24
Peak memory 205732 kb
Host smart-345b8742-90b2-4357-87e9-77ded4898413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44798
5952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.447985952
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.3755631758
Short name T1530
Test name
Test status
Simulation time 10037870886 ps
CPU time 14.77 seconds
Started Jun 02 03:28:49 PM PDT 24
Finished Jun 02 03:29:05 PM PDT 24
Peak memory 205628 kb
Host smart-f098027b-5183-4881-8bfe-2fbd64205f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37556
31758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.3755631758
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3415004654
Short name T911
Test name
Test status
Simulation time 10073467362 ps
CPU time 13.77 seconds
Started Jun 02 03:28:50 PM PDT 24
Finished Jun 02 03:29:05 PM PDT 24
Peak memory 205712 kb
Host smart-ef72397d-face-4b83-bb9d-099d524190b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34150
04654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3415004654
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.1225835759
Short name T568
Test name
Test status
Simulation time 10062513007 ps
CPU time 14.07 seconds
Started Jun 02 03:28:53 PM PDT 24
Finished Jun 02 03:29:08 PM PDT 24
Peak memory 205620 kb
Host smart-2eb001c4-843e-497b-981d-f57e1fe53042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12258
35759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1225835759
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_eop_single_bit_handling.2970333296
Short name T455
Test name
Test status
Simulation time 10060898466 ps
CPU time 15.24 seconds
Started Jun 02 03:28:50 PM PDT 24
Finished Jun 02 03:29:06 PM PDT 24
Peak memory 205640 kb
Host smart-f742f171-c504-431f-8bb8-fce406fcbede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29703
33296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_eop_single_bit_handling.2970333296
Directory /workspace/16.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.4133762231
Short name T792
Test name
Test status
Simulation time 10048212447 ps
CPU time 13.46 seconds
Started Jun 02 03:28:52 PM PDT 24
Finished Jun 02 03:29:06 PM PDT 24
Peak memory 205660 kb
Host smart-6d6e7bae-650b-46be-b516-335623d847bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41337
62231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.4133762231
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.3147750054
Short name T437
Test name
Test status
Simulation time 10036940164 ps
CPU time 13.88 seconds
Started Jun 02 03:28:51 PM PDT 24
Finished Jun 02 03:29:06 PM PDT 24
Peak memory 205660 kb
Host smart-99fb41fd-44f6-43dc-a323-8408cf230b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31477
50054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.3147750054
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.1433715934
Short name T1582
Test name
Test status
Simulation time 10110779458 ps
CPU time 14.86 seconds
Started Jun 02 03:28:55 PM PDT 24
Finished Jun 02 03:29:11 PM PDT 24
Peak memory 205788 kb
Host smart-f3761583-a146-4898-8b33-79d071809246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14337
15934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.1433715934
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.3603722719
Short name T707
Test name
Test status
Simulation time 10154861578 ps
CPU time 13.31 seconds
Started Jun 02 03:28:52 PM PDT 24
Finished Jun 02 03:29:06 PM PDT 24
Peak memory 205784 kb
Host smart-5b995a13-9b54-4372-86d5-28bae8a7c787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36037
22719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.3603722719
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.752022717
Short name T1172
Test name
Test status
Simulation time 10086332136 ps
CPU time 14.59 seconds
Started Jun 02 03:28:50 PM PDT 24
Finished Jun 02 03:29:06 PM PDT 24
Peak memory 205560 kb
Host smart-c892a76c-d90c-4ac8-8c7a-723cb07d166d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75202
2717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.752022717
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.2180122250
Short name T766
Test name
Test status
Simulation time 10043165130 ps
CPU time 12.82 seconds
Started Jun 02 03:28:50 PM PDT 24
Finished Jun 02 03:29:04 PM PDT 24
Peak memory 205644 kb
Host smart-f65a37ce-11b9-49da-927b-efa05c67bd7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21801
22250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.2180122250
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.682201074
Short name T1134
Test name
Test status
Simulation time 10075207775 ps
CPU time 14.87 seconds
Started Jun 02 03:28:52 PM PDT 24
Finished Jun 02 03:29:08 PM PDT 24
Peak memory 205672 kb
Host smart-4aac24d4-cbba-4d59-9920-85948e836d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68220
1074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.682201074
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.3677103613
Short name T1347
Test name
Test status
Simulation time 10048089545 ps
CPU time 14.43 seconds
Started Jun 02 03:28:50 PM PDT 24
Finished Jun 02 03:29:05 PM PDT 24
Peak memory 205648 kb
Host smart-d9fcb473-8468-4b2f-8737-5ac4b823761c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36771
03613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.3677103613
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1414083584
Short name T136
Test name
Test status
Simulation time 10111575654 ps
CPU time 14.93 seconds
Started Jun 02 03:28:50 PM PDT 24
Finished Jun 02 03:29:06 PM PDT 24
Peak memory 205624 kb
Host smart-6b223f8d-2405-4931-a619-b18b7348c672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14140
83584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1414083584
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.4024572527
Short name T639
Test name
Test status
Simulation time 10060435353 ps
CPU time 13.28 seconds
Started Jun 02 03:28:50 PM PDT 24
Finished Jun 02 03:29:04 PM PDT 24
Peak memory 205776 kb
Host smart-b5e2eadf-2b34-46ab-9987-eacb8878a498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40245
72527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.4024572527
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.3132784620
Short name T666
Test name
Test status
Simulation time 10068527678 ps
CPU time 12.94 seconds
Started Jun 02 03:28:51 PM PDT 24
Finished Jun 02 03:29:05 PM PDT 24
Peak memory 205760 kb
Host smart-cff5b15c-8157-427d-88b1-8a50bb095d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31327
84620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.3132784620
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.3043055852
Short name T1466
Test name
Test status
Simulation time 14995233716 ps
CPU time 52.74 seconds
Started Jun 02 03:28:50 PM PDT 24
Finished Jun 02 03:29:43 PM PDT 24
Peak memory 205684 kb
Host smart-e0e00069-56ae-4df5-bb81-2bd43108ce4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30430
55852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.3043055852
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.2344742073
Short name T1942
Test name
Test status
Simulation time 10134314441 ps
CPU time 14.03 seconds
Started Jun 02 03:29:06 PM PDT 24
Finished Jun 02 03:29:20 PM PDT 24
Peak memory 205576 kb
Host smart-acfd1202-cfd1-41d7-a116-172c82ca719b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2344742073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.2344742073
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.278544585
Short name T1841
Test name
Test status
Simulation time 10060437955 ps
CPU time 15.58 seconds
Started Jun 02 03:29:01 PM PDT 24
Finished Jun 02 03:29:17 PM PDT 24
Peak memory 205676 kb
Host smart-462cfa6a-6179-47b3-84c2-b052a44908e8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=278544585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.278544585
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.3165774551
Short name T932
Test name
Test status
Simulation time 10112362782 ps
CPU time 15.79 seconds
Started Jun 02 03:29:14 PM PDT 24
Finished Jun 02 03:29:31 PM PDT 24
Peak memory 205712 kb
Host smart-7736cffa-8f5d-49bc-b08e-040b97e02af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31657
74551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.3165774551
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.3307544336
Short name T1124
Test name
Test status
Simulation time 23222993200 ps
CPU time 29.68 seconds
Started Jun 02 03:28:54 PM PDT 24
Finished Jun 02 03:29:24 PM PDT 24
Peak memory 205728 kb
Host smart-eb981117-6f4c-4b89-bb5a-c71ce60a34f5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3307544336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.3307544336
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3748715013
Short name T1013
Test name
Test status
Simulation time 10046415436 ps
CPU time 15.99 seconds
Started Jun 02 03:28:57 PM PDT 24
Finished Jun 02 03:29:14 PM PDT 24
Peak memory 205700 kb
Host smart-2f906b84-f464-4307-9d6c-cbfeede40cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37487
15013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3748715013
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1395470172
Short name T1130
Test name
Test status
Simulation time 10877583881 ps
CPU time 14.81 seconds
Started Jun 02 03:28:57 PM PDT 24
Finished Jun 02 03:29:13 PM PDT 24
Peak memory 205600 kb
Host smart-6cc23174-1724-49fb-b2ee-c31aaa68d010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13954
70172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1395470172
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.3101728721
Short name T688
Test name
Test status
Simulation time 10034790656 ps
CPU time 15.27 seconds
Started Jun 02 03:29:01 PM PDT 24
Finished Jun 02 03:29:17 PM PDT 24
Peak memory 205660 kb
Host smart-035578d5-e1cf-455a-9718-2e6b0d92fa22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31017
28721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.3101728721
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.35750672
Short name T850
Test name
Test status
Simulation time 10052425110 ps
CPU time 13.32 seconds
Started Jun 02 03:28:56 PM PDT 24
Finished Jun 02 03:29:10 PM PDT 24
Peak memory 205628 kb
Host smart-bcb1fed1-9a43-475a-920c-65069c410de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35750
672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.35750672
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.502738344
Short name T1751
Test name
Test status
Simulation time 10705899836 ps
CPU time 15.57 seconds
Started Jun 02 03:28:57 PM PDT 24
Finished Jun 02 03:29:13 PM PDT 24
Peak memory 205728 kb
Host smart-c7b47d1f-9198-47fc-aec6-b3f0e0fb1e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50273
8344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.502738344
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.4195403788
Short name T1135
Test name
Test status
Simulation time 10128735376 ps
CPU time 14.42 seconds
Started Jun 02 03:28:56 PM PDT 24
Finished Jun 02 03:29:11 PM PDT 24
Peak memory 205588 kb
Host smart-23205246-0561-45a0-91c8-b9df13127b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41954
03788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.4195403788
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.856159341
Short name T1829
Test name
Test status
Simulation time 10113566193 ps
CPU time 14.84 seconds
Started Jun 02 03:29:01 PM PDT 24
Finished Jun 02 03:29:17 PM PDT 24
Peak memory 205572 kb
Host smart-2f995113-093d-4e4c-a16a-1dc9c38af358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85615
9341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.856159341
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3279074804
Short name T1681
Test name
Test status
Simulation time 10041553330 ps
CPU time 13.45 seconds
Started Jun 02 03:29:04 PM PDT 24
Finished Jun 02 03:29:18 PM PDT 24
Peak memory 205684 kb
Host smart-753fe21c-3ae0-40aa-a222-1d72f46ea2ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32790
74804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3279074804
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.2472769835
Short name T737
Test name
Test status
Simulation time 10077729168 ps
CPU time 13.56 seconds
Started Jun 02 03:28:56 PM PDT 24
Finished Jun 02 03:29:10 PM PDT 24
Peak memory 205696 kb
Host smart-3ea931c9-0fad-4af4-9b54-bc81616917d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24727
69835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.2472769835
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.225331729
Short name T1015
Test name
Test status
Simulation time 10087996792 ps
CPU time 13.09 seconds
Started Jun 02 03:28:56 PM PDT 24
Finished Jun 02 03:29:09 PM PDT 24
Peak memory 205624 kb
Host smart-a2c340cd-1c73-4eb9-823b-0f382a3351eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22533
1729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.225331729
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.1103176045
Short name T940
Test name
Test status
Simulation time 13203016297 ps
CPU time 21.15 seconds
Started Jun 02 03:28:56 PM PDT 24
Finished Jun 02 03:29:17 PM PDT 24
Peak memory 205772 kb
Host smart-95203aaf-f680-4412-888d-77fbbe8a62d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11031
76045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.1103176045
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2315154202
Short name T851
Test name
Test status
Simulation time 10103321741 ps
CPU time 14.13 seconds
Started Jun 02 03:29:02 PM PDT 24
Finished Jun 02 03:29:17 PM PDT 24
Peak memory 205648 kb
Host smart-42f59125-33e8-4dd4-9e18-9971727c8f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23151
54202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2315154202
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.3843157808
Short name T413
Test name
Test status
Simulation time 14652431831 ps
CPU time 56.28 seconds
Started Jun 02 03:29:01 PM PDT 24
Finished Jun 02 03:29:58 PM PDT 24
Peak memory 205736 kb
Host smart-38e80ecc-51dc-4c5a-a03f-c183781aae0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38431
57808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.3843157808
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.2307731091
Short name T311
Test name
Test status
Simulation time 10040031697 ps
CPU time 13.68 seconds
Started Jun 02 03:29:02 PM PDT 24
Finished Jun 02 03:29:16 PM PDT 24
Peak memory 205652 kb
Host smart-884e521f-d907-4a7e-9f22-3ed6aa6443a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23077
31091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.2307731091
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.4114703513
Short name T461
Test name
Test status
Simulation time 10113644364 ps
CPU time 14.65 seconds
Started Jun 02 03:28:59 PM PDT 24
Finished Jun 02 03:29:14 PM PDT 24
Peak memory 205736 kb
Host smart-42860e48-6534-42d5-a127-335b79fbc8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41147
03513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.4114703513
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.1964972169
Short name T1051
Test name
Test status
Simulation time 10054416370 ps
CPU time 13.83 seconds
Started Jun 02 03:29:02 PM PDT 24
Finished Jun 02 03:29:17 PM PDT 24
Peak memory 205724 kb
Host smart-61bef8ce-3b4b-45d7-96cd-4cbeff424ab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19649
72169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.1964972169
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.2686162220
Short name T1207
Test name
Test status
Simulation time 10063054983 ps
CPU time 12.76 seconds
Started Jun 02 03:28:59 PM PDT 24
Finished Jun 02 03:29:12 PM PDT 24
Peak memory 205684 kb
Host smart-eff1c91f-80fa-4fde-bd84-e3778ab913b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26861
62220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2686162220
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.2920164670
Short name T133
Test name
Test status
Simulation time 10138788843 ps
CPU time 14.96 seconds
Started Jun 02 03:29:01 PM PDT 24
Finished Jun 02 03:29:17 PM PDT 24
Peak memory 205688 kb
Host smart-593682e3-f0c5-4415-b35e-8e33e0eeecee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29201
64670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.2920164670
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_eop_single_bit_handling.2238014658
Short name T1431
Test name
Test status
Simulation time 10089793882 ps
CPU time 13.21 seconds
Started Jun 02 03:29:01 PM PDT 24
Finished Jun 02 03:29:15 PM PDT 24
Peak memory 205724 kb
Host smart-31bf53c1-a1ac-4447-9cb6-d3338823aabf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22380
14658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_eop_single_bit_handling.2238014658
Directory /workspace/17.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3711848456
Short name T1255
Test name
Test status
Simulation time 10044034628 ps
CPU time 16.26 seconds
Started Jun 02 03:29:01 PM PDT 24
Finished Jun 02 03:29:18 PM PDT 24
Peak memory 205712 kb
Host smart-85f68c7b-7c93-4ff9-b44c-4958baa306f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37118
48456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.3711848456
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.84310892
Short name T350
Test name
Test status
Simulation time 10038783167 ps
CPU time 16.74 seconds
Started Jun 02 03:29:03 PM PDT 24
Finished Jun 02 03:29:20 PM PDT 24
Peak memory 205652 kb
Host smart-08e90dff-111b-42c8-851c-b5b9f1464b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84310
892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.84310892
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3271065432
Short name T1454
Test name
Test status
Simulation time 26380103215 ps
CPU time 48.46 seconds
Started Jun 02 03:29:00 PM PDT 24
Finished Jun 02 03:29:49 PM PDT 24
Peak memory 205592 kb
Host smart-c1abfcb2-5c24-4d0c-abaa-b1ca9b827a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32710
65432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3271065432
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.4181347061
Short name T979
Test name
Test status
Simulation time 10052077858 ps
CPU time 12.83 seconds
Started Jun 02 03:29:01 PM PDT 24
Finished Jun 02 03:29:14 PM PDT 24
Peak memory 205660 kb
Host smart-f63fe3e8-f843-414c-b6cd-1f322eedc238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41813
47061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.4181347061
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.1959951249
Short name T1330
Test name
Test status
Simulation time 10092755102 ps
CPU time 13.56 seconds
Started Jun 02 03:29:01 PM PDT 24
Finished Jun 02 03:29:15 PM PDT 24
Peak memory 205584 kb
Host smart-1528e046-e936-40e5-99da-e3a68f1c36b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19599
51249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.1959951249
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.1647146709
Short name T1769
Test name
Test status
Simulation time 10072438348 ps
CPU time 14.98 seconds
Started Jun 02 03:29:04 PM PDT 24
Finished Jun 02 03:29:20 PM PDT 24
Peak memory 205672 kb
Host smart-1e73082a-f5aa-47d8-892a-14f585e06711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16471
46709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.1647146709
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.348436944
Short name T428
Test name
Test status
Simulation time 10089009090 ps
CPU time 13.84 seconds
Started Jun 02 03:29:02 PM PDT 24
Finished Jun 02 03:29:17 PM PDT 24
Peak memory 205832 kb
Host smart-54151e68-4321-400d-b771-d86fc2499c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34843
6944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.348436944
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.1380023126
Short name T154
Test name
Test status
Simulation time 10047358969 ps
CPU time 15.37 seconds
Started Jun 02 03:29:03 PM PDT 24
Finished Jun 02 03:29:19 PM PDT 24
Peak memory 205664 kb
Host smart-34b445d9-8e79-476d-8c92-cf60a1058e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13800
23126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1380023126
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3812859816
Short name T868
Test name
Test status
Simulation time 10071206674 ps
CPU time 13.83 seconds
Started Jun 02 03:29:00 PM PDT 24
Finished Jun 02 03:29:15 PM PDT 24
Peak memory 205744 kb
Host smart-30cd84bc-e6d6-4224-a1b4-dab49acda0b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38128
59816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3812859816
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2962102228
Short name T1312
Test name
Test status
Simulation time 10153929103 ps
CPU time 14.06 seconds
Started Jun 02 03:28:59 PM PDT 24
Finished Jun 02 03:29:14 PM PDT 24
Peak memory 205728 kb
Host smart-b2809673-e565-483e-ac62-a532001f4221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29621
02228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2962102228
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.1342502930
Short name T763
Test name
Test status
Simulation time 10098401993 ps
CPU time 13.24 seconds
Started Jun 02 03:29:03 PM PDT 24
Finished Jun 02 03:29:17 PM PDT 24
Peak memory 205700 kb
Host smart-36602f92-fe47-48be-94b3-a2e29da33cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13425
02930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.1342502930
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2441607282
Short name T1139
Test name
Test status
Simulation time 10084075469 ps
CPU time 14.13 seconds
Started Jun 02 03:29:03 PM PDT 24
Finished Jun 02 03:29:18 PM PDT 24
Peak memory 205652 kb
Host smart-001d6126-dd0b-45c4-8a30-24ebdeba9d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24416
07282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2441607282
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.3510880223
Short name T473
Test name
Test status
Simulation time 22399836569 ps
CPU time 372.37 seconds
Started Jun 02 03:29:02 PM PDT 24
Finished Jun 02 03:35:15 PM PDT 24
Peak memory 205652 kb
Host smart-7acf7c3d-d2d6-40f8-9948-ae34945dc84d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35108
80223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.3510880223
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.4258303637
Short name T1568
Test name
Test status
Simulation time 10189725054 ps
CPU time 14.05 seconds
Started Jun 02 03:29:13 PM PDT 24
Finished Jun 02 03:29:28 PM PDT 24
Peak memory 205796 kb
Host smart-f642fc74-3729-4c3a-829c-39d29aac4073
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4258303637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.4258303637
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.689778670
Short name T432
Test name
Test status
Simulation time 10076053554 ps
CPU time 13.81 seconds
Started Jun 02 03:29:14 PM PDT 24
Finished Jun 02 03:29:29 PM PDT 24
Peak memory 205704 kb
Host smart-6e410a75-5443-424c-9369-0fc40f6e91d8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=689778670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.689778670
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.1101399642
Short name T684
Test name
Test status
Simulation time 10142392105 ps
CPU time 13.33 seconds
Started Jun 02 03:29:15 PM PDT 24
Finished Jun 02 03:29:29 PM PDT 24
Peak memory 205624 kb
Host smart-5da22d7c-d5fb-418d-944d-7c1913868d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11013
99642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.1101399642
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.933381672
Short name T192
Test name
Test status
Simulation time 13945070997 ps
CPU time 18.8 seconds
Started Jun 02 03:29:08 PM PDT 24
Finished Jun 02 03:29:28 PM PDT 24
Peak memory 205676 kb
Host smart-b5ebe560-e1c2-4707-9d7f-cb603ffa614e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=933381672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.933381672
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.1912388554
Short name T15
Test name
Test status
Simulation time 23345481965 ps
CPU time 27.22 seconds
Started Jun 02 03:29:05 PM PDT 24
Finished Jun 02 03:29:33 PM PDT 24
Peak memory 205676 kb
Host smart-2d489552-6ccf-4a6b-b552-9a6f90eb94cd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1912388554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.1912388554
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2944941321
Short name T1843
Test name
Test status
Simulation time 10081248145 ps
CPU time 13.33 seconds
Started Jun 02 03:29:08 PM PDT 24
Finished Jun 02 03:29:22 PM PDT 24
Peak memory 204840 kb
Host smart-9d281310-12be-44d6-9e6b-9668f8d2b7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29449
41321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2944941321
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.982798776
Short name T1461
Test name
Test status
Simulation time 10413678635 ps
CPU time 13.46 seconds
Started Jun 02 03:29:07 PM PDT 24
Finished Jun 02 03:29:20 PM PDT 24
Peak memory 205764 kb
Host smart-1c66c241-2081-4022-8ed1-5743f27c6b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98279
8776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.982798776
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.3751171952
Short name T366
Test name
Test status
Simulation time 10063804820 ps
CPU time 14.09 seconds
Started Jun 02 03:29:16 PM PDT 24
Finished Jun 02 03:29:31 PM PDT 24
Peak memory 205696 kb
Host smart-fe5ec6e4-740a-4262-8795-943f4052c901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37511
71952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.3751171952
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.1981963641
Short name T784
Test name
Test status
Simulation time 10055109031 ps
CPU time 13.67 seconds
Started Jun 02 03:29:04 PM PDT 24
Finished Jun 02 03:29:18 PM PDT 24
Peak memory 205780 kb
Host smart-6dd62bdb-a491-4067-99a7-e8c6cb6ff418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19819
63641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1981963641
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.2365447417
Short name T1050
Test name
Test status
Simulation time 10865065064 ps
CPU time 15.91 seconds
Started Jun 02 03:29:06 PM PDT 24
Finished Jun 02 03:29:22 PM PDT 24
Peak memory 205684 kb
Host smart-37ab68d1-5337-4fac-8be0-e98ed8a43e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23654
47417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.2365447417
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2105077844
Short name T1770
Test name
Test status
Simulation time 10070521361 ps
CPU time 13.26 seconds
Started Jun 02 03:29:16 PM PDT 24
Finished Jun 02 03:29:30 PM PDT 24
Peak memory 205660 kb
Host smart-22b0a9ac-2dd7-47e1-9268-c4f771ed4002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21050
77844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2105077844
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.3386907034
Short name T83
Test name
Test status
Simulation time 10097649547 ps
CPU time 13.39 seconds
Started Jun 02 03:29:11 PM PDT 24
Finished Jun 02 03:29:26 PM PDT 24
Peak memory 205776 kb
Host smart-617d8618-8bbb-452c-b974-cc5efc9e5a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33869
07034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.3386907034
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.1886652676
Short name T482
Test name
Test status
Simulation time 10047182442 ps
CPU time 14.28 seconds
Started Jun 02 03:29:15 PM PDT 24
Finished Jun 02 03:29:30 PM PDT 24
Peak memory 205760 kb
Host smart-72c53be2-28dc-4db8-843b-8f4a16f95f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18866
52676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1886652676
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.190043763
Short name T1438
Test name
Test status
Simulation time 10059533135 ps
CPU time 13.15 seconds
Started Jun 02 03:29:16 PM PDT 24
Finished Jun 02 03:29:30 PM PDT 24
Peak memory 205680 kb
Host smart-3c185118-360a-4751-811a-7b92ffc114f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19004
3763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.190043763
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.2853730703
Short name T378
Test name
Test status
Simulation time 10107551560 ps
CPU time 16.45 seconds
Started Jun 02 03:29:04 PM PDT 24
Finished Jun 02 03:29:22 PM PDT 24
Peak memory 205732 kb
Host smart-afe61d2f-a133-4386-adf5-baafca8bb477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28537
30703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.2853730703
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.2164998021
Short name T1573
Test name
Test status
Simulation time 13177293697 ps
CPU time 16.15 seconds
Started Jun 02 03:29:14 PM PDT 24
Finished Jun 02 03:29:32 PM PDT 24
Peak memory 205776 kb
Host smart-91c77f36-e6cf-4455-92c0-6215ce0cda41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21649
98021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.2164998021
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.2739447230
Short name T867
Test name
Test status
Simulation time 10099857937 ps
CPU time 13.8 seconds
Started Jun 02 03:29:08 PM PDT 24
Finished Jun 02 03:29:22 PM PDT 24
Peak memory 205680 kb
Host smart-129d7e7b-4383-4198-bcc1-a8dcac661ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27394
47230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.2739447230
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.6923785
Short name T1534
Test name
Test status
Simulation time 23624435030 ps
CPU time 408.01 seconds
Started Jun 02 03:29:06 PM PDT 24
Finished Jun 02 03:35:55 PM PDT 24
Peak memory 205592 kb
Host smart-a14ac4d1-9731-4c9c-a019-4688e662ebeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69237
85 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.6923785
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2090622761
Short name T317
Test name
Test status
Simulation time 10059418424 ps
CPU time 16.14 seconds
Started Jun 02 03:29:08 PM PDT 24
Finished Jun 02 03:29:25 PM PDT 24
Peak memory 205676 kb
Host smart-313060a3-9f04-42e2-a9ad-9c90aca6a133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20906
22761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2090622761
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.1607457503
Short name T124
Test name
Test status
Simulation time 10098122081 ps
CPU time 13.99 seconds
Started Jun 02 03:29:09 PM PDT 24
Finished Jun 02 03:29:23 PM PDT 24
Peak memory 205784 kb
Host smart-7bcbe428-401b-4e7c-84d4-33c8ba4e88a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16074
57503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1607457503
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.805313596
Short name T1064
Test name
Test status
Simulation time 10100706893 ps
CPU time 12.61 seconds
Started Jun 02 03:29:09 PM PDT 24
Finished Jun 02 03:29:22 PM PDT 24
Peak memory 205700 kb
Host smart-b53c2813-286c-4649-9df5-81b9eded20ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80531
3596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.805313596
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1629728402
Short name T945
Test name
Test status
Simulation time 10071339800 ps
CPU time 13.63 seconds
Started Jun 02 03:29:08 PM PDT 24
Finished Jun 02 03:29:22 PM PDT 24
Peak memory 205676 kb
Host smart-ad2d5fd3-683d-4b50-a219-d10887603d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16297
28402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1629728402
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1628650594
Short name T748
Test name
Test status
Simulation time 10099597718 ps
CPU time 12.65 seconds
Started Jun 02 03:29:05 PM PDT 24
Finished Jun 02 03:29:19 PM PDT 24
Peak memory 205648 kb
Host smart-9aee698b-c30f-4108-9965-4700291688da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16286
50594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1628650594
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.61911071
Short name T138
Test name
Test status
Simulation time 10059406210 ps
CPU time 14.45 seconds
Started Jun 02 03:29:13 PM PDT 24
Finished Jun 02 03:29:29 PM PDT 24
Peak memory 205712 kb
Host smart-f8201d10-7ca5-4337-9916-5bc365f9ec9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61911
071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.61911071
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_eop_single_bit_handling.2949988464
Short name T560
Test name
Test status
Simulation time 10052060040 ps
CPU time 15.14 seconds
Started Jun 02 03:29:13 PM PDT 24
Finished Jun 02 03:29:29 PM PDT 24
Peak memory 205640 kb
Host smart-bab2222b-fb9f-4a0b-8b18-6f64fecf6df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29499
88464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_eop_single_bit_handling.2949988464
Directory /workspace/18.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.4169658642
Short name T1832
Test name
Test status
Simulation time 10058577266 ps
CPU time 13.53 seconds
Started Jun 02 03:29:12 PM PDT 24
Finished Jun 02 03:29:26 PM PDT 24
Peak memory 205740 kb
Host smart-639c0fa5-c22e-491f-ad44-891571c71236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41696
58642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.4169658642
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.2159203721
Short name T358
Test name
Test status
Simulation time 10037506191 ps
CPU time 15.88 seconds
Started Jun 02 03:29:14 PM PDT 24
Finished Jun 02 03:29:31 PM PDT 24
Peak memory 205744 kb
Host smart-180ab101-f703-437e-9f16-08fc4d598c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21592
03721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.2159203721
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.2268308834
Short name T245
Test name
Test status
Simulation time 19923538554 ps
CPU time 33.66 seconds
Started Jun 02 03:29:16 PM PDT 24
Finished Jun 02 03:29:51 PM PDT 24
Peak memory 205692 kb
Host smart-1fd290a3-968f-489b-85c5-4557f4b1ed8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22683
08834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.2268308834
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.4213945915
Short name T1756
Test name
Test status
Simulation time 10071292654 ps
CPU time 17.53 seconds
Started Jun 02 03:29:08 PM PDT 24
Finished Jun 02 03:29:26 PM PDT 24
Peak memory 204972 kb
Host smart-07eaaeca-83dc-4f20-8087-4a9e6b50c8d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42139
45915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.4213945915
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.1255176511
Short name T474
Test name
Test status
Simulation time 10173099013 ps
CPU time 15.87 seconds
Started Jun 02 03:29:06 PM PDT 24
Finished Jun 02 03:29:22 PM PDT 24
Peak memory 205664 kb
Host smart-ddd084b2-bd0f-4a22-8799-4498d88d5e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12551
76511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.1255176511
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.2004499127
Short name T536
Test name
Test status
Simulation time 10066217152 ps
CPU time 14.12 seconds
Started Jun 02 03:29:05 PM PDT 24
Finished Jun 02 03:29:20 PM PDT 24
Peak memory 205684 kb
Host smart-cdef547a-a3c0-4c84-bb2c-3fa92460b571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20044
99127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.2004499127
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.3643634522
Short name T457
Test name
Test status
Simulation time 10041622795 ps
CPU time 17.49 seconds
Started Jun 02 03:29:11 PM PDT 24
Finished Jun 02 03:29:29 PM PDT 24
Peak memory 205752 kb
Host smart-dc1352d2-7077-47f2-b5e1-bed242687496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36436
34522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.3643634522
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.3773807482
Short name T1749
Test name
Test status
Simulation time 10067043031 ps
CPU time 16.23 seconds
Started Jun 02 03:29:12 PM PDT 24
Finished Jun 02 03:29:29 PM PDT 24
Peak memory 205688 kb
Host smart-74b4843a-7a42-43c0-bd94-6a201e71be67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37738
07482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3773807482
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1860675347
Short name T424
Test name
Test status
Simulation time 10069890906 ps
CPU time 16.31 seconds
Started Jun 02 03:29:11 PM PDT 24
Finished Jun 02 03:29:29 PM PDT 24
Peak memory 205664 kb
Host smart-ffe20c05-beb7-4e2d-b30b-3e0c3c7ded98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18606
75347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1860675347
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.3602856526
Short name T817
Test name
Test status
Simulation time 10080702980 ps
CPU time 13.39 seconds
Started Jun 02 03:29:11 PM PDT 24
Finished Jun 02 03:29:25 PM PDT 24
Peak memory 205756 kb
Host smart-ad7cc648-f373-40a0-8353-628a05e4dc4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36028
56526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.3602856526
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.3736370170
Short name T724
Test name
Test status
Simulation time 10080414868 ps
CPU time 14 seconds
Started Jun 02 03:29:12 PM PDT 24
Finished Jun 02 03:29:27 PM PDT 24
Peak memory 205672 kb
Host smart-221c0796-1eec-4b8b-8e90-f3a52f9237d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37363
70170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.3736370170
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.1161492319
Short name T931
Test name
Test status
Simulation time 13872672715 ps
CPU time 118.41 seconds
Started Jun 02 03:29:17 PM PDT 24
Finished Jun 02 03:31:16 PM PDT 24
Peak memory 205696 kb
Host smart-7306677e-b703-45ca-87f1-c316e90ff157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11614
92319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.1161492319
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.493087647
Short name T2011
Test name
Test status
Simulation time 10151541027 ps
CPU time 14.16 seconds
Started Jun 02 03:29:19 PM PDT 24
Finished Jun 02 03:29:34 PM PDT 24
Peak memory 205792 kb
Host smart-c41ebf9f-a75f-4b39-b4e5-2828250fd8ed
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=493087647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.493087647
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.1578381040
Short name T1279
Test name
Test status
Simulation time 10140569546 ps
CPU time 16.43 seconds
Started Jun 02 03:29:28 PM PDT 24
Finished Jun 02 03:29:45 PM PDT 24
Peak memory 205788 kb
Host smart-fe86ca8f-e960-4dd1-8deb-7c8934a04326
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1578381040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.1578381040
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.4112524107
Short name T1625
Test name
Test status
Simulation time 10088782118 ps
CPU time 14.35 seconds
Started Jun 02 03:29:27 PM PDT 24
Finished Jun 02 03:29:43 PM PDT 24
Peak memory 205768 kb
Host smart-26b6c2f4-25ab-4879-a6fb-82663510df37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41125
24107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.4112524107
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.1038670345
Short name T770
Test name
Test status
Simulation time 13957944961 ps
CPU time 17.8 seconds
Started Jun 02 03:29:13 PM PDT 24
Finished Jun 02 03:29:32 PM PDT 24
Peak memory 205644 kb
Host smart-8109acd7-1d2e-4ea9-ab18-f63f0197167f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1038670345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.1038670345
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.1653725233
Short name T479
Test name
Test status
Simulation time 23293988657 ps
CPU time 29.46 seconds
Started Jun 02 03:29:14 PM PDT 24
Finished Jun 02 03:29:45 PM PDT 24
Peak memory 205760 kb
Host smart-0a69f8ac-fccc-419d-8147-3ff0976923a3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1653725233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.1653725233
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.222225374
Short name T1655
Test name
Test status
Simulation time 10051311098 ps
CPU time 15.29 seconds
Started Jun 02 03:29:13 PM PDT 24
Finished Jun 02 03:29:30 PM PDT 24
Peak memory 204656 kb
Host smart-9a0e58f6-7fa2-47c4-95a9-8939cf103d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22222
5374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.222225374
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.2788680923
Short name T1744
Test name
Test status
Simulation time 10779948897 ps
CPU time 14.5 seconds
Started Jun 02 03:29:15 PM PDT 24
Finished Jun 02 03:29:30 PM PDT 24
Peak memory 205724 kb
Host smart-7bf9c920-bfed-4cdb-92e7-20cba09e52c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27886
80923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.2788680923
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.1403678896
Short name T49
Test name
Test status
Simulation time 10046447775 ps
CPU time 14.68 seconds
Started Jun 02 03:29:15 PM PDT 24
Finished Jun 02 03:29:31 PM PDT 24
Peak memory 205724 kb
Host smart-38620147-b700-4488-bff9-2e59a178b307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14036
78896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.1403678896
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.2708102124
Short name T749
Test name
Test status
Simulation time 10051910461 ps
CPU time 14.5 seconds
Started Jun 02 03:29:12 PM PDT 24
Finished Jun 02 03:29:28 PM PDT 24
Peak memory 205720 kb
Host smart-f12408d4-2f29-43db-9f3f-3658f0e723a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27081
02124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2708102124
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.3487417158
Short name T1337
Test name
Test status
Simulation time 10664348460 ps
CPU time 16.71 seconds
Started Jun 02 03:29:12 PM PDT 24
Finished Jun 02 03:29:29 PM PDT 24
Peak memory 205716 kb
Host smart-f9d431e5-3b8a-4761-a98c-fc2ce6cdd96c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34874
17158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.3487417158
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.3152894694
Short name T1285
Test name
Test status
Simulation time 10215903135 ps
CPU time 16.01 seconds
Started Jun 02 03:29:13 PM PDT 24
Finished Jun 02 03:29:30 PM PDT 24
Peak memory 204908 kb
Host smart-73797abc-03ed-47df-9d4e-684698452621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31528
94694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.3152894694
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.1002048310
Short name T575
Test name
Test status
Simulation time 10073425813 ps
CPU time 15.85 seconds
Started Jun 02 03:29:18 PM PDT 24
Finished Jun 02 03:29:34 PM PDT 24
Peak memory 205776 kb
Host smart-bdb67078-8aad-4f0a-9dc7-cb41334a129b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10020
48310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.1002048310
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.217116516
Short name T1923
Test name
Test status
Simulation time 10049385965 ps
CPU time 13.38 seconds
Started Jun 02 03:29:17 PM PDT 24
Finished Jun 02 03:29:32 PM PDT 24
Peak memory 205636 kb
Host smart-768551a1-1e94-4415-bda4-7ee6a5d3044b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21711
6516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.217116516
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.1242431985
Short name T705
Test name
Test status
Simulation time 10119920933 ps
CPU time 17.43 seconds
Started Jun 02 03:29:17 PM PDT 24
Finished Jun 02 03:29:36 PM PDT 24
Peak memory 205732 kb
Host smart-29ab8db2-de50-46cc-b63a-d03bf31b8110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12424
31985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.1242431985
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1071348628
Short name T1386
Test name
Test status
Simulation time 10073712377 ps
CPU time 15.89 seconds
Started Jun 02 03:29:16 PM PDT 24
Finished Jun 02 03:29:33 PM PDT 24
Peak memory 205668 kb
Host smart-5147deb0-4653-4347-898c-6794ba89c520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10713
48628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1071348628
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.902931464
Short name T1039
Test name
Test status
Simulation time 13163890923 ps
CPU time 16.42 seconds
Started Jun 02 03:29:16 PM PDT 24
Finished Jun 02 03:29:33 PM PDT 24
Peak memory 205608 kb
Host smart-52efbea2-eaae-417b-abe7-1c7b4582bee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90293
1464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.902931464
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1798279054
Short name T761
Test name
Test status
Simulation time 10095967424 ps
CPU time 13.29 seconds
Started Jun 02 03:29:14 PM PDT 24
Finished Jun 02 03:29:29 PM PDT 24
Peak memory 205772 kb
Host smart-e1d5e7c0-768e-4619-a539-045143ca13ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17982
79054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1798279054
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.2358335510
Short name T425
Test name
Test status
Simulation time 21074941929 ps
CPU time 324.87 seconds
Started Jun 02 03:29:16 PM PDT 24
Finished Jun 02 03:34:42 PM PDT 24
Peak memory 205612 kb
Host smart-17b36fce-6ae6-4a2c-9330-059878e9a8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23583
35510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.2358335510
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.185549449
Short name T559
Test name
Test status
Simulation time 10056074341 ps
CPU time 14.03 seconds
Started Jun 02 03:29:16 PM PDT 24
Finished Jun 02 03:29:31 PM PDT 24
Peak memory 205668 kb
Host smart-fc6b026c-eec3-4534-90fa-1910351adc14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18554
9449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.185549449
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.232324759
Short name T1392
Test name
Test status
Simulation time 10103156101 ps
CPU time 14.07 seconds
Started Jun 02 03:29:16 PM PDT 24
Finished Jun 02 03:29:32 PM PDT 24
Peak memory 205660 kb
Host smart-2c6a83b0-b1dd-4143-9642-065cd32839dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23232
4759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.232324759
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3098049192
Short name T1827
Test name
Test status
Simulation time 10090292587 ps
CPU time 12.95 seconds
Started Jun 02 03:29:19 PM PDT 24
Finished Jun 02 03:29:33 PM PDT 24
Peak memory 205788 kb
Host smart-dfe88774-e67b-46e8-9879-31b155814b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30980
49192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3098049192
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2023210110
Short name T320
Test name
Test status
Simulation time 10081282825 ps
CPU time 12.82 seconds
Started Jun 02 03:29:16 PM PDT 24
Finished Jun 02 03:29:30 PM PDT 24
Peak memory 205596 kb
Host smart-b05762fb-1847-4fbe-8861-508755f528db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20232
10110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2023210110
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.817476682
Short name T1594
Test name
Test status
Simulation time 10060637081 ps
CPU time 15.9 seconds
Started Jun 02 03:29:17 PM PDT 24
Finished Jun 02 03:29:34 PM PDT 24
Peak memory 205708 kb
Host smart-3f32a918-a984-4584-a0fa-7ab7c4238957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81747
6682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.817476682
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_eop_single_bit_handling.3933588343
Short name T944
Test name
Test status
Simulation time 10068177785 ps
CPU time 13.1 seconds
Started Jun 02 03:29:27 PM PDT 24
Finished Jun 02 03:29:42 PM PDT 24
Peak memory 205664 kb
Host smart-9b7c22d5-cf1d-4da4-84a5-70782247f341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39335
88343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_eop_single_bit_handling.3933588343
Directory /workspace/19.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.2815164487
Short name T537
Test name
Test status
Simulation time 10040934187 ps
CPU time 13.44 seconds
Started Jun 02 03:29:18 PM PDT 24
Finished Jun 02 03:29:33 PM PDT 24
Peak memory 205708 kb
Host smart-3f51f1c7-6ea1-477c-89a0-b122d60af3e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28151
64487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.2815164487
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.4080492824
Short name T44
Test name
Test status
Simulation time 10041986036 ps
CPU time 13.56 seconds
Started Jun 02 03:29:16 PM PDT 24
Finished Jun 02 03:29:31 PM PDT 24
Peak memory 205668 kb
Host smart-d929d5f4-07e4-4467-aa71-522546343c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40804
92824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.4080492824
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.2734169384
Short name T1891
Test name
Test status
Simulation time 19913877089 ps
CPU time 37.36 seconds
Started Jun 02 03:29:16 PM PDT 24
Finished Jun 02 03:29:55 PM PDT 24
Peak memory 205628 kb
Host smart-c503a278-bb5a-428d-af1b-ecdc2048782f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27341
69384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.2734169384
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.348665233
Short name T1733
Test name
Test status
Simulation time 10092777317 ps
CPU time 13.59 seconds
Started Jun 02 03:29:20 PM PDT 24
Finished Jun 02 03:29:34 PM PDT 24
Peak memory 205704 kb
Host smart-b865063c-f56a-4700-b2ef-4d7a27f28ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34866
5233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.348665233
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1513873897
Short name T1443
Test name
Test status
Simulation time 10057056001 ps
CPU time 14.53 seconds
Started Jun 02 03:29:18 PM PDT 24
Finished Jun 02 03:29:33 PM PDT 24
Peak memory 205708 kb
Host smart-89c03726-066b-440e-914c-5cc2a267c3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15138
73897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1513873897
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.4181658011
Short name T937
Test name
Test status
Simulation time 10106424132 ps
CPU time 14.73 seconds
Started Jun 02 03:29:18 PM PDT 24
Finished Jun 02 03:29:33 PM PDT 24
Peak memory 205684 kb
Host smart-1082a221-7b35-4a8e-87d7-c5ccdbbe00e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41816
58011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.4181658011
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.1770062656
Short name T1029
Test name
Test status
Simulation time 10082353395 ps
CPU time 14.99 seconds
Started Jun 02 03:29:19 PM PDT 24
Finished Jun 02 03:29:35 PM PDT 24
Peak memory 205732 kb
Host smart-ee4c652f-b1d4-4410-ac0c-0936f087e494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17700
62656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.1770062656
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.1432792716
Short name T2003
Test name
Test status
Simulation time 10061798651 ps
CPU time 13.73 seconds
Started Jun 02 03:29:19 PM PDT 24
Finished Jun 02 03:29:34 PM PDT 24
Peak memory 205704 kb
Host smart-76b1448a-3d36-41bf-b975-8a35df83f562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14327
92716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1432792716
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3660878123
Short name T1904
Test name
Test status
Simulation time 10048500997 ps
CPU time 14.77 seconds
Started Jun 02 03:29:30 PM PDT 24
Finished Jun 02 03:29:46 PM PDT 24
Peak memory 205688 kb
Host smart-0e6459ac-71b4-4663-b9ff-d40bd5608452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36608
78123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3660878123
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.2082325089
Short name T156
Test name
Test status
Simulation time 10106846821 ps
CPU time 14.49 seconds
Started Jun 02 03:29:12 PM PDT 24
Finished Jun 02 03:29:27 PM PDT 24
Peak memory 205712 kb
Host smart-5dc246ed-3d9a-4131-a21a-f6b0551be07b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20823
25089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.2082325089
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.1574835750
Short name T1570
Test name
Test status
Simulation time 10071372070 ps
CPU time 15.06 seconds
Started Jun 02 03:29:17 PM PDT 24
Finished Jun 02 03:29:33 PM PDT 24
Peak memory 205688 kb
Host smart-c08fed81-bc42-4406-8b05-d7c992a87bca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15748
35750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.1574835750
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3897629573
Short name T441
Test name
Test status
Simulation time 10070981546 ps
CPU time 14.09 seconds
Started Jun 02 03:29:17 PM PDT 24
Finished Jun 02 03:29:32 PM PDT 24
Peak memory 205560 kb
Host smart-efc2cf61-3f39-49bc-acb7-e7638b8317f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38976
29573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3897629573
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.1263264440
Short name T1804
Test name
Test status
Simulation time 14429467186 ps
CPU time 60.2 seconds
Started Jun 02 03:29:18 PM PDT 24
Finished Jun 02 03:30:20 PM PDT 24
Peak memory 205732 kb
Host smart-f3c57b30-6f0b-4e67-bfb7-abc2714f138a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12632
64440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.1263264440
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.637882627
Short name T1602
Test name
Test status
Simulation time 10146301514 ps
CPU time 13.47 seconds
Started Jun 02 03:26:42 PM PDT 24
Finished Jun 02 03:26:56 PM PDT 24
Peak memory 205748 kb
Host smart-b6397d68-6d25-4069-8938-4169c1b8da94
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=637882627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.637882627
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.3548037290
Short name T405
Test name
Test status
Simulation time 10056952666 ps
CPU time 14.47 seconds
Started Jun 02 03:26:44 PM PDT 24
Finished Jun 02 03:26:59 PM PDT 24
Peak memory 205584 kb
Host smart-724ddc41-7035-4457-ad16-f972144fdacb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3548037290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.3548037290
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.3346114817
Short name T917
Test name
Test status
Simulation time 10075391791 ps
CPU time 15.36 seconds
Started Jun 02 03:26:45 PM PDT 24
Finished Jun 02 03:27:01 PM PDT 24
Peak memory 205660 kb
Host smart-4a87511e-9f19-4c34-b09c-96a3dc57c119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33461
14817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.3346114817
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.270422787
Short name T492
Test name
Test status
Simulation time 14138628864 ps
CPU time 16.62 seconds
Started Jun 02 03:26:31 PM PDT 24
Finished Jun 02 03:26:48 PM PDT 24
Peak memory 205844 kb
Host smart-ec49f387-ab83-4424-b5a7-304e4791d912
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=270422787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.270422787
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.420444547
Short name T1815
Test name
Test status
Simulation time 10049309464 ps
CPU time 13.05 seconds
Started Jun 02 03:26:32 PM PDT 24
Finished Jun 02 03:26:45 PM PDT 24
Peak memory 205708 kb
Host smart-e4947ff8-404d-43ff-8ba0-f533546cfd63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42044
4547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.420444547
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.2227628901
Short name T57
Test name
Test status
Simulation time 10066916364 ps
CPU time 15.21 seconds
Started Jun 02 03:26:32 PM PDT 24
Finished Jun 02 03:26:48 PM PDT 24
Peak memory 205668 kb
Host smart-83aa26ef-9158-4d57-b6f3-27f8580b7f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22276
28901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.2227628901
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.1203820394
Short name T1363
Test name
Test status
Simulation time 11066415635 ps
CPU time 15.08 seconds
Started Jun 02 03:26:35 PM PDT 24
Finished Jun 02 03:26:51 PM PDT 24
Peak memory 205776 kb
Host smart-4796e612-ff55-4d95-91f7-0e4f99d541ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12038
20394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.1203820394
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.3856715321
Short name T1566
Test name
Test status
Simulation time 10049726563 ps
CPU time 12.66 seconds
Started Jun 02 03:26:32 PM PDT 24
Finished Jun 02 03:26:45 PM PDT 24
Peak memory 205592 kb
Host smart-59539340-20d6-4ac6-8189-08235c78820b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38567
15321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.3856715321
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.1650818218
Short name T342
Test name
Test status
Simulation time 10060293468 ps
CPU time 16.81 seconds
Started Jun 02 03:26:31 PM PDT 24
Finished Jun 02 03:26:48 PM PDT 24
Peak memory 205672 kb
Host smart-89c4ac2a-1f46-4585-9d5a-bab61283165c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16508
18218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.1650818218
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.793754648
Short name T544
Test name
Test status
Simulation time 10744520454 ps
CPU time 17.88 seconds
Started Jun 02 03:26:32 PM PDT 24
Finished Jun 02 03:26:51 PM PDT 24
Peak memory 205676 kb
Host smart-56104a3f-d79a-466f-910a-977e131c2a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79375
4648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.793754648
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2231500751
Short name T1420
Test name
Test status
Simulation time 10072032375 ps
CPU time 13.62 seconds
Started Jun 02 03:26:33 PM PDT 24
Finished Jun 02 03:26:47 PM PDT 24
Peak memory 205620 kb
Host smart-2b1b5c49-0d40-4229-87c6-59ab8e34bd26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22315
00751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2231500751
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.3188621220
Short name T1900
Test name
Test status
Simulation time 10147608846 ps
CPU time 13.26 seconds
Started Jun 02 03:26:44 PM PDT 24
Finished Jun 02 03:26:58 PM PDT 24
Peak memory 205664 kb
Host smart-805aa581-e2a5-4733-af71-d1b99856f4e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31886
21220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.3188621220
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.1673632650
Short name T661
Test name
Test status
Simulation time 10047544735 ps
CPU time 12.37 seconds
Started Jun 02 03:26:45 PM PDT 24
Finished Jun 02 03:26:58 PM PDT 24
Peak memory 205712 kb
Host smart-6281f2a3-88dc-48a3-a0f1-20177917b8a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16736
32650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.1673632650
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.1874795492
Short name T1529
Test name
Test status
Simulation time 10108847436 ps
CPU time 15.59 seconds
Started Jun 02 03:26:33 PM PDT 24
Finished Jun 02 03:26:50 PM PDT 24
Peak memory 205684 kb
Host smart-63b4dea8-6136-4c6d-91ea-d222715c2984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18747
95492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1874795492
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.741194365
Short name T989
Test name
Test status
Simulation time 10101380716 ps
CPU time 13.67 seconds
Started Jun 02 03:26:35 PM PDT 24
Finished Jun 02 03:26:49 PM PDT 24
Peak memory 205624 kb
Host smart-c5c50804-f8c6-4972-bad5-9700a338096b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74119
4365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.741194365
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.767841159
Short name T332
Test name
Test status
Simulation time 13201403206 ps
CPU time 19.45 seconds
Started Jun 02 03:26:33 PM PDT 24
Finished Jun 02 03:26:53 PM PDT 24
Peak memory 205792 kb
Host smart-e8d806ee-c51c-40c4-bd62-7314178d9044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76784
1159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.767841159
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.4191969813
Short name T834
Test name
Test status
Simulation time 10111529639 ps
CPU time 13.97 seconds
Started Jun 02 03:26:31 PM PDT 24
Finished Jun 02 03:26:46 PM PDT 24
Peak memory 205716 kb
Host smart-41aee8f5-9440-4b5b-83ec-7abe3b6150e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41919
69813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.4191969813
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.4027503092
Short name T1563
Test name
Test status
Simulation time 16018350657 ps
CPU time 75.85 seconds
Started Jun 02 03:26:32 PM PDT 24
Finished Jun 02 03:27:48 PM PDT 24
Peak memory 205712 kb
Host smart-614e5b71-db5c-47a6-b001-fc8b748eeaaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40275
03092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.4027503092
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.983922241
Short name T351
Test name
Test status
Simulation time 10039424826 ps
CPU time 12.68 seconds
Started Jun 02 03:26:33 PM PDT 24
Finished Jun 02 03:26:46 PM PDT 24
Peak memory 205668 kb
Host smart-06cc7937-af9b-4f99-b966-9cd7f8526954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98392
2241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.983922241
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.3160108406
Short name T1483
Test name
Test status
Simulation time 10107217068 ps
CPU time 13.95 seconds
Started Jun 02 03:26:38 PM PDT 24
Finished Jun 02 03:26:53 PM PDT 24
Peak memory 205772 kb
Host smart-33be6bb4-e1f0-4187-8b47-55741053d657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31601
08406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3160108406
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.2613849732
Short name T2009
Test name
Test status
Simulation time 10060689264 ps
CPU time 16.54 seconds
Started Jun 02 03:26:38 PM PDT 24
Finished Jun 02 03:26:55 PM PDT 24
Peak memory 205716 kb
Host smart-82779395-d368-4baf-8636-6b9b5694e89b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26138
49732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.2613849732
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.1824599683
Short name T2028
Test name
Test status
Simulation time 10079898965 ps
CPU time 12.73 seconds
Started Jun 02 03:26:38 PM PDT 24
Finished Jun 02 03:26:52 PM PDT 24
Peak memory 205868 kb
Host smart-04e94c1d-3507-4632-9ad1-e82a30df9e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18245
99683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.1824599683
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1496600459
Short name T976
Test name
Test status
Simulation time 10073091980 ps
CPU time 15.9 seconds
Started Jun 02 03:26:38 PM PDT 24
Finished Jun 02 03:26:55 PM PDT 24
Peak memory 205624 kb
Host smart-461befff-1590-4a50-ac1b-3215a6534b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14966
00459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1496600459
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.2581392081
Short name T135
Test name
Test status
Simulation time 10054449784 ps
CPU time 14.27 seconds
Started Jun 02 03:26:43 PM PDT 24
Finished Jun 02 03:26:58 PM PDT 24
Peak memory 205776 kb
Host smart-8f5db81f-1d50-492a-a027-5ebce995e040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25813
92081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.2581392081
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_eop_single_bit_handling.3722811913
Short name T288
Test name
Test status
Simulation time 10050759908 ps
CPU time 13.87 seconds
Started Jun 02 03:26:43 PM PDT 24
Finished Jun 02 03:26:57 PM PDT 24
Peak memory 205676 kb
Host smart-373a55af-0242-4546-84a7-bb947a16d3f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37228
11913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_eop_single_bit_handling.3722811913
Directory /workspace/2.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1928464966
Short name T1603
Test name
Test status
Simulation time 10042520320 ps
CPU time 13.15 seconds
Started Jun 02 03:26:43 PM PDT 24
Finished Jun 02 03:26:56 PM PDT 24
Peak memory 205708 kb
Host smart-85bc4b73-6480-4b76-8655-21df6b6977db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19284
64966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1928464966
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2307166872
Short name T1357
Test name
Test status
Simulation time 10085858889 ps
CPU time 13.08 seconds
Started Jun 02 03:26:46 PM PDT 24
Finished Jun 02 03:26:59 PM PDT 24
Peak memory 205740 kb
Host smart-ab2e6f87-49ed-4ad3-a165-987971c42086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23071
66872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2307166872
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.722974600
Short name T242
Test name
Test status
Simulation time 19258277178 ps
CPU time 33.13 seconds
Started Jun 02 03:26:37 PM PDT 24
Finished Jun 02 03:27:10 PM PDT 24
Peak memory 205688 kb
Host smart-485a9088-a602-4958-9f60-0c7b5ff055f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72297
4600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.722974600
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.3738389034
Short name T1561
Test name
Test status
Simulation time 10054065175 ps
CPU time 14.44 seconds
Started Jun 02 03:26:37 PM PDT 24
Finished Jun 02 03:26:52 PM PDT 24
Peak memory 205708 kb
Host smart-55244cf0-9d2f-47b1-a6e6-0ddd034336b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37383
89034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.3738389034
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.1617862155
Short name T837
Test name
Test status
Simulation time 10101432269 ps
CPU time 14.12 seconds
Started Jun 02 03:26:37 PM PDT 24
Finished Jun 02 03:26:52 PM PDT 24
Peak memory 205692 kb
Host smart-48a39477-3ee4-4504-aab2-3b973cf6b43a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16178
62155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1617862155
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.1953124536
Short name T571
Test name
Test status
Simulation time 14210998678 ps
CPU time 42.81 seconds
Started Jun 02 03:26:37 PM PDT 24
Finished Jun 02 03:27:21 PM PDT 24
Peak memory 205692 kb
Host smart-58c9469e-bad8-45bd-b4e4-db6ef8fa51ff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1953124536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.1953124536
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.2256758079
Short name T1280
Test name
Test status
Simulation time 17866017209 ps
CPU time 53.98 seconds
Started Jun 02 03:26:36 PM PDT 24
Finished Jun 02 03:27:31 PM PDT 24
Peak memory 205660 kb
Host smart-d6da3e96-5ee4-4b2d-88da-dd7b4e1a05b7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2256758079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.2256758079
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.3539021957
Short name T1281
Test name
Test status
Simulation time 10092628723 ps
CPU time 13.13 seconds
Started Jun 02 03:26:36 PM PDT 24
Finished Jun 02 03:26:50 PM PDT 24
Peak memory 205616 kb
Host smart-c9fe41ed-2931-4580-b82e-f7e336e17048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35390
21957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.3539021957
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.555228201
Short name T877
Test name
Test status
Simulation time 10037311804 ps
CPU time 15.52 seconds
Started Jun 02 03:26:39 PM PDT 24
Finished Jun 02 03:26:55 PM PDT 24
Peak memory 205696 kb
Host smart-3aadc2ea-14b1-4c6a-9f73-c6fb68ea721c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55522
8201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.555228201
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1222339904
Short name T198
Test name
Test status
Simulation time 811285219 ps
CPU time 1.66 seconds
Started Jun 02 03:26:57 PM PDT 24
Finished Jun 02 03:26:59 PM PDT 24
Peak memory 222096 kb
Host smart-b4af234c-0833-42b9-8b0a-8be63bf861e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1222339904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1222339904
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.4239384896
Short name T1740
Test name
Test status
Simulation time 10050622884 ps
CPU time 14.43 seconds
Started Jun 02 03:26:46 PM PDT 24
Finished Jun 02 03:27:01 PM PDT 24
Peak memory 205760 kb
Host smart-8487a909-20f9-4b29-9912-07651c5b04fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42393
84896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.4239384896
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3068906114
Short name T1490
Test name
Test status
Simulation time 10058807062 ps
CPU time 12.71 seconds
Started Jun 02 03:26:38 PM PDT 24
Finished Jun 02 03:26:51 PM PDT 24
Peak memory 205740 kb
Host smart-8eef4fdc-819e-455c-85b4-37ca975626f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30689
06114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3068906114
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.219772472
Short name T667
Test name
Test status
Simulation time 10183040745 ps
CPU time 14.64 seconds
Started Jun 02 03:26:29 PM PDT 24
Finished Jun 02 03:26:44 PM PDT 24
Peak memory 205728 kb
Host smart-1def218e-eb1e-4bb8-b3d3-a92a9f0de63d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21977
2472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.219772472
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.2158517128
Short name T346
Test name
Test status
Simulation time 10071206563 ps
CPU time 17.08 seconds
Started Jun 02 03:26:41 PM PDT 24
Finished Jun 02 03:26:58 PM PDT 24
Peak memory 205768 kb
Host smart-96fb2d8c-65f9-4d54-bd1b-cca023f19085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21585
17128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.2158517128
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.2609972133
Short name T1964
Test name
Test status
Simulation time 10100244935 ps
CPU time 13.34 seconds
Started Jun 02 03:26:39 PM PDT 24
Finished Jun 02 03:26:53 PM PDT 24
Peak memory 205744 kb
Host smart-5785561d-c75e-4509-ab3c-8fcb9fbcf485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26099
72133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.2609972133
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.691318290
Short name T825
Test name
Test status
Simulation time 25203146793 ps
CPU time 448.84 seconds
Started Jun 02 03:26:37 PM PDT 24
Finished Jun 02 03:34:07 PM PDT 24
Peak memory 205700 kb
Host smart-09e044dc-5a28-40d1-a98c-493d7c9f462b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69131
8290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.691318290
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.3362405282
Short name T168
Test name
Test status
Simulation time 23778757649 ps
CPU time 144.11 seconds
Started Jun 02 03:26:37 PM PDT 24
Finished Jun 02 03:29:02 PM PDT 24
Peak memory 205708 kb
Host smart-0797dc70-e58b-4634-80de-0b21822ea479
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362405282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_
traffic.3362405282
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.996404312
Short name T1912
Test name
Test status
Simulation time 10163508646 ps
CPU time 12.84 seconds
Started Jun 02 03:29:27 PM PDT 24
Finished Jun 02 03:29:41 PM PDT 24
Peak memory 205784 kb
Host smart-584d1a7f-19ca-44d9-b8ca-cf452cb24a07
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=996404312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.996404312
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.110811137
Short name T2023
Test name
Test status
Simulation time 10059655358 ps
CPU time 12.88 seconds
Started Jun 02 03:29:33 PM PDT 24
Finished Jun 02 03:29:46 PM PDT 24
Peak memory 205760 kb
Host smart-c4f8a10b-d41d-44aa-947c-a924ebdebb74
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=110811137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.110811137
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.2500114339
Short name T341
Test name
Test status
Simulation time 10128514868 ps
CPU time 13.41 seconds
Started Jun 02 03:29:27 PM PDT 24
Finished Jun 02 03:29:42 PM PDT 24
Peak memory 205648 kb
Host smart-6beae9ca-5bc7-4e30-8ab3-d8c62305137b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25001
14339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.2500114339
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.1070284314
Short name T1041
Test name
Test status
Simulation time 13937526525 ps
CPU time 19.18 seconds
Started Jun 02 03:29:22 PM PDT 24
Finished Jun 02 03:29:42 PM PDT 24
Peak memory 205768 kb
Host smart-ac46da7f-b2ae-466f-86c9-7cde5eb25b52
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1070284314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.1070284314
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.2208653137
Short name T1668
Test name
Test status
Simulation time 23211130831 ps
CPU time 25.99 seconds
Started Jun 02 03:29:24 PM PDT 24
Finished Jun 02 03:29:51 PM PDT 24
Peak memory 205700 kb
Host smart-673ddd8e-2e5e-4ed9-9353-ce29683b8109
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2208653137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.2208653137
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.1587124190
Short name T1508
Test name
Test status
Simulation time 10051822458 ps
CPU time 12.46 seconds
Started Jun 02 03:29:22 PM PDT 24
Finished Jun 02 03:29:36 PM PDT 24
Peak memory 205664 kb
Host smart-d2fc3ac1-764a-4dbd-9577-ae6d708b9cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15871
24190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1587124190
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.901992672
Short name T170
Test name
Test status
Simulation time 10669323808 ps
CPU time 13.81 seconds
Started Jun 02 03:29:26 PM PDT 24
Finished Jun 02 03:29:41 PM PDT 24
Peak memory 205696 kb
Host smart-de4a0730-9523-4540-9d2b-1953a7985f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90199
2672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.901992672
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.3294070915
Short name T51
Test name
Test status
Simulation time 10048670131 ps
CPU time 13.23 seconds
Started Jun 02 03:29:26 PM PDT 24
Finished Jun 02 03:29:40 PM PDT 24
Peak memory 205760 kb
Host smart-7d51c816-2e80-4a3a-9a91-d5b612dbd8c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32940
70915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.3294070915
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.1013418456
Short name T1352
Test name
Test status
Simulation time 10071795139 ps
CPU time 14.03 seconds
Started Jun 02 03:29:25 PM PDT 24
Finished Jun 02 03:29:39 PM PDT 24
Peak memory 205680 kb
Host smart-6f5e1ceb-0d65-4e36-bd5d-702fa107dce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10134
18456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1013418456
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.3581907787
Short name T779
Test name
Test status
Simulation time 10943355319 ps
CPU time 14.83 seconds
Started Jun 02 03:29:23 PM PDT 24
Finished Jun 02 03:29:39 PM PDT 24
Peak memory 205756 kb
Host smart-f5c8e8b7-f1bc-4578-82d0-4eda043c1b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35819
07787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.3581907787
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1509227441
Short name T191
Test name
Test status
Simulation time 10069354596 ps
CPU time 13.4 seconds
Started Jun 02 03:29:23 PM PDT 24
Finished Jun 02 03:29:37 PM PDT 24
Peak memory 205768 kb
Host smart-c29dbd98-da6a-4063-b437-0858c1c231fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15092
27441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1509227441
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.2635708926
Short name T1771
Test name
Test status
Simulation time 10105290308 ps
CPU time 13.31 seconds
Started Jun 02 03:29:28 PM PDT 24
Finished Jun 02 03:29:42 PM PDT 24
Peak memory 205700 kb
Host smart-8fb1da08-0e9e-421e-b87c-1a6f3bfa0f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26357
08926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.2635708926
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.1852477610
Short name T910
Test name
Test status
Simulation time 10042584207 ps
CPU time 12.67 seconds
Started Jun 02 03:29:26 PM PDT 24
Finished Jun 02 03:29:39 PM PDT 24
Peak memory 205792 kb
Host smart-32cb846a-21b4-4738-830d-c2a6cf69939a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18524
77610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.1852477610
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.2186058402
Short name T431
Test name
Test status
Simulation time 10061027329 ps
CPU time 14.12 seconds
Started Jun 02 03:29:23 PM PDT 24
Finished Jun 02 03:29:38 PM PDT 24
Peak memory 205652 kb
Host smart-8351d8df-b7e5-4a02-acf1-3769dbd660f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21860
58402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.2186058402
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.3305615346
Short name T793
Test name
Test status
Simulation time 10069850344 ps
CPU time 15.93 seconds
Started Jun 02 03:29:27 PM PDT 24
Finished Jun 02 03:29:43 PM PDT 24
Peak memory 205764 kb
Host smart-7cfbb4b9-2853-41a9-9109-66bffb0b995b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33056
15346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3305615346
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.2737595864
Short name T1249
Test name
Test status
Simulation time 13316334210 ps
CPU time 18.21 seconds
Started Jun 02 03:29:23 PM PDT 24
Finished Jun 02 03:29:42 PM PDT 24
Peak memory 205532 kb
Host smart-67670f3c-a4f8-4f02-8449-3a4d2d09df3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27375
95864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.2737595864
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.469738118
Short name T771
Test name
Test status
Simulation time 10095687925 ps
CPU time 13.15 seconds
Started Jun 02 03:29:22 PM PDT 24
Finished Jun 02 03:29:36 PM PDT 24
Peak memory 205652 kb
Host smart-347f1ba3-7cbd-471a-be88-a0d4c8489f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46973
8118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.469738118
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.3843316432
Short name T791
Test name
Test status
Simulation time 19713095159 ps
CPU time 305.61 seconds
Started Jun 02 03:29:24 PM PDT 24
Finished Jun 02 03:34:30 PM PDT 24
Peak memory 205708 kb
Host smart-21927d25-51fa-4761-b803-3d7a675f8c0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38433
16432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.3843316432
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.2336775938
Short name T1193
Test name
Test status
Simulation time 10065581912 ps
CPU time 14.42 seconds
Started Jun 02 03:29:27 PM PDT 24
Finished Jun 02 03:29:42 PM PDT 24
Peak memory 205816 kb
Host smart-350634bd-dbf2-4636-b26d-c70f6cc74787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23367
75938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.2336775938
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.92583779
Short name T101
Test name
Test status
Simulation time 10078725380 ps
CPU time 12.36 seconds
Started Jun 02 03:29:27 PM PDT 24
Finished Jun 02 03:29:41 PM PDT 24
Peak memory 205700 kb
Host smart-3d3d2ab7-9d41-4090-8881-2662afb20498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92583
779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.92583779
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.523671966
Short name T1256
Test name
Test status
Simulation time 10056496768 ps
CPU time 13.95 seconds
Started Jun 02 03:29:27 PM PDT 24
Finished Jun 02 03:29:42 PM PDT 24
Peak memory 205680 kb
Host smart-9859abea-4ee2-478c-b4db-f34ad958537c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52367
1966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.523671966
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.498454872
Short name T1859
Test name
Test status
Simulation time 10081315248 ps
CPU time 13.59 seconds
Started Jun 02 03:29:26 PM PDT 24
Finished Jun 02 03:29:40 PM PDT 24
Peak memory 205788 kb
Host smart-09d50b16-efb9-46f7-9512-5e6698a81b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49845
4872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.498454872
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.724986608
Short name T1680
Test name
Test status
Simulation time 10092202300 ps
CPU time 13.56 seconds
Started Jun 02 03:29:25 PM PDT 24
Finished Jun 02 03:29:39 PM PDT 24
Peak memory 205500 kb
Host smart-9ebc14df-3edb-4389-b8fd-96b6ed2e8aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72498
6608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.724986608
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.2678189909
Short name T1348
Test name
Test status
Simulation time 10052586157 ps
CPU time 12.9 seconds
Started Jun 02 03:29:26 PM PDT 24
Finished Jun 02 03:29:40 PM PDT 24
Peak memory 205680 kb
Host smart-a0a07ac1-02e6-41a8-880b-361a92de44d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26781
89909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.2678189909
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_eop_single_bit_handling.610649341
Short name T464
Test name
Test status
Simulation time 10108460439 ps
CPU time 13.48 seconds
Started Jun 02 03:29:26 PM PDT 24
Finished Jun 02 03:29:40 PM PDT 24
Peak memory 205648 kb
Host smart-789b7105-d770-48f8-a337-2c0fc0fb5c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61064
9341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_eop_single_bit_handling.610649341
Directory /workspace/20.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.4058907841
Short name T1632
Test name
Test status
Simulation time 10045045465 ps
CPU time 16.91 seconds
Started Jun 02 03:29:27 PM PDT 24
Finished Jun 02 03:29:45 PM PDT 24
Peak memory 205668 kb
Host smart-c192ed48-de90-4ca5-87d1-7eb4e7931c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40589
07841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.4058907841
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2580029842
Short name T42
Test name
Test status
Simulation time 10053210525 ps
CPU time 14.58 seconds
Started Jun 02 03:29:33 PM PDT 24
Finished Jun 02 03:29:48 PM PDT 24
Peak memory 205676 kb
Host smart-d539d3d5-bd02-485a-b0cb-84d4958ceb09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25800
29842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2580029842
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.2615294453
Short name T243
Test name
Test status
Simulation time 15517904085 ps
CPU time 26.5 seconds
Started Jun 02 03:29:21 PM PDT 24
Finished Jun 02 03:29:48 PM PDT 24
Peak memory 205660 kb
Host smart-48ea5c59-f68a-439d-9eee-5d8eaa5aff95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26152
94453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.2615294453
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.2500297398
Short name T1475
Test name
Test status
Simulation time 10126716869 ps
CPU time 14.39 seconds
Started Jun 02 03:29:26 PM PDT 24
Finished Jun 02 03:29:41 PM PDT 24
Peak memory 205712 kb
Host smart-8f227ba0-5c2f-4d35-bcf0-6c1be41798ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25002
97398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2500297398
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.878397787
Short name T1583
Test name
Test status
Simulation time 10094881193 ps
CPU time 13.53 seconds
Started Jun 02 03:29:25 PM PDT 24
Finished Jun 02 03:29:39 PM PDT 24
Peak memory 205436 kb
Host smart-37d0abc5-38d3-40c3-98af-c8e612ab319e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87839
7787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.878397787
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.1709140030
Short name T1955
Test name
Test status
Simulation time 10087009393 ps
CPU time 13.33 seconds
Started Jun 02 03:29:27 PM PDT 24
Finished Jun 02 03:29:41 PM PDT 24
Peak memory 205584 kb
Host smart-fe12085b-fecb-46c5-95dd-64d2a5990748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17091
40030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.1709140030
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.737643078
Short name T1933
Test name
Test status
Simulation time 10045921407 ps
CPU time 15.32 seconds
Started Jun 02 03:29:31 PM PDT 24
Finished Jun 02 03:29:48 PM PDT 24
Peak memory 205784 kb
Host smart-2a1f0e46-492b-43f6-9993-08017d45c49d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73764
3078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.737643078
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1010375503
Short name T912
Test name
Test status
Simulation time 10049306669 ps
CPU time 15.71 seconds
Started Jun 02 03:29:27 PM PDT 24
Finished Jun 02 03:29:44 PM PDT 24
Peak memory 205660 kb
Host smart-adcadcb1-ed4a-4c08-abf4-000563857481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10103
75503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1010375503
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.3450393436
Short name T1721
Test name
Test status
Simulation time 10116856132 ps
CPU time 13.47 seconds
Started Jun 02 03:29:33 PM PDT 24
Finished Jun 02 03:29:47 PM PDT 24
Peak memory 205792 kb
Host smart-600a3f81-4d6a-4b61-afc8-543c48dd1053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34503
93436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.3450393436
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.2834952886
Short name T1897
Test name
Test status
Simulation time 10125870611 ps
CPU time 15.78 seconds
Started Jun 02 03:29:22 PM PDT 24
Finished Jun 02 03:29:38 PM PDT 24
Peak memory 205788 kb
Host smart-2fd46f51-3aeb-44cb-b465-1b858d6bc438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28349
52886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.2834952886
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.948502790
Short name T1768
Test name
Test status
Simulation time 10066349706 ps
CPU time 12.33 seconds
Started Jun 02 03:29:34 PM PDT 24
Finished Jun 02 03:29:47 PM PDT 24
Peak memory 205736 kb
Host smart-b7369643-c19c-4b1d-93fc-ba0202f37e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94850
2790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.948502790
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.3866429045
Short name T960
Test name
Test status
Simulation time 10079704675 ps
CPU time 13.67 seconds
Started Jun 02 03:29:22 PM PDT 24
Finished Jun 02 03:29:36 PM PDT 24
Peak memory 205932 kb
Host smart-a6fbb832-3683-488a-917a-6a4b89ef0306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38664
29045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.3866429045
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.3526830265
Short name T384
Test name
Test status
Simulation time 18060828269 ps
CPU time 236.03 seconds
Started Jun 02 03:29:27 PM PDT 24
Finished Jun 02 03:33:24 PM PDT 24
Peak memory 205664 kb
Host smart-f504f592-7f58-4095-890a-99fc6bd5a4b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35268
30265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.3526830265
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.493388298
Short name T1414
Test name
Test status
Simulation time 10139151132 ps
CPU time 14.18 seconds
Started Jun 02 03:29:37 PM PDT 24
Finished Jun 02 03:29:52 PM PDT 24
Peak memory 205720 kb
Host smart-fcbe4ab7-1fd8-4659-bce3-f2589a7af371
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=493388298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.493388298
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.3434594548
Short name T1308
Test name
Test status
Simulation time 10106408672 ps
CPU time 13.43 seconds
Started Jun 02 03:29:37 PM PDT 24
Finished Jun 02 03:29:51 PM PDT 24
Peak memory 205740 kb
Host smart-b7652eb1-2c46-4a05-8caf-644fe766b58b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3434594548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.3434594548
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.813927974
Short name T400
Test name
Test status
Simulation time 10099106519 ps
CPU time 14.73 seconds
Started Jun 02 03:29:37 PM PDT 24
Finished Jun 02 03:29:52 PM PDT 24
Peak memory 205716 kb
Host smart-888f68bb-22fb-4679-bd41-5b34d1f61452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81392
7974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.813927974
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.2270967791
Short name T999
Test name
Test status
Simulation time 13788182206 ps
CPU time 17.1 seconds
Started Jun 02 03:29:34 PM PDT 24
Finished Jun 02 03:29:51 PM PDT 24
Peak memory 205776 kb
Host smart-46813e3a-1898-4e23-823e-416e7036d97c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2270967791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.2270967791
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.2382480007
Short name T1848
Test name
Test status
Simulation time 23225215239 ps
CPU time 28.57 seconds
Started Jun 02 03:29:31 PM PDT 24
Finished Jun 02 03:30:00 PM PDT 24
Peak memory 205736 kb
Host smart-86567d0f-dafd-48ab-a86f-c7ccef2a5f9f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2382480007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.2382480007
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.1243816768
Short name T1288
Test name
Test status
Simulation time 10054121384 ps
CPU time 16.89 seconds
Started Jun 02 03:29:30 PM PDT 24
Finished Jun 02 03:29:48 PM PDT 24
Peak memory 205748 kb
Host smart-643fc607-9b84-4cb8-a565-38c19fbbaf4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12438
16768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.1243816768
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.570619191
Short name T1607
Test name
Test status
Simulation time 10976192448 ps
CPU time 16.76 seconds
Started Jun 02 03:29:30 PM PDT 24
Finished Jun 02 03:29:48 PM PDT 24
Peak memory 205692 kb
Host smart-3f2c42a4-644d-4ba7-be8e-ee47571f25c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57061
9191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.570619191
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.2416536352
Short name T1227
Test name
Test status
Simulation time 10041877798 ps
CPU time 13.97 seconds
Started Jun 02 03:29:25 PM PDT 24
Finished Jun 02 03:29:39 PM PDT 24
Peak memory 206012 kb
Host smart-bbb3cc61-1216-423c-92ab-528fadc1cec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24165
36352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.2416536352
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.1980263065
Short name T686
Test name
Test status
Simulation time 10086682310 ps
CPU time 14.27 seconds
Started Jun 02 03:29:25 PM PDT 24
Finished Jun 02 03:29:39 PM PDT 24
Peak memory 205688 kb
Host smart-bd34a48e-08d0-46be-bd93-dc73a67f26ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19802
63065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.1980263065
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.2505924567
Short name T375
Test name
Test status
Simulation time 10723013591 ps
CPU time 14.09 seconds
Started Jun 02 03:29:26 PM PDT 24
Finished Jun 02 03:29:41 PM PDT 24
Peak memory 205780 kb
Host smart-96d4e78c-4144-417a-9bed-3666bcf35cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25059
24567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.2505924567
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.909075897
Short name T1487
Test name
Test status
Simulation time 10177194683 ps
CPU time 14.76 seconds
Started Jun 02 03:29:30 PM PDT 24
Finished Jun 02 03:29:46 PM PDT 24
Peak memory 205688 kb
Host smart-cd5cd8c4-d0e6-4720-ab22-52e6c2c751d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90907
5897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.909075897
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.3952686060
Short name T1886
Test name
Test status
Simulation time 10115391637 ps
CPU time 15.35 seconds
Started Jun 02 03:29:37 PM PDT 24
Finished Jun 02 03:29:53 PM PDT 24
Peak memory 205732 kb
Host smart-117c84a8-1aaf-42ab-9a83-0132ba6cbc17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39526
86060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.3952686060
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.1356489101
Short name T1734
Test name
Test status
Simulation time 10036614292 ps
CPU time 13.82 seconds
Started Jun 02 03:29:30 PM PDT 24
Finished Jun 02 03:29:45 PM PDT 24
Peak memory 205672 kb
Host smart-77db8048-1d1c-4bd2-a1dc-c8c1c1842f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13564
89101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.1356489101
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.741847780
Short name T905
Test name
Test status
Simulation time 10135265563 ps
CPU time 13.04 seconds
Started Jun 02 03:29:29 PM PDT 24
Finished Jun 02 03:29:43 PM PDT 24
Peak memory 205808 kb
Host smart-e86f9777-05b0-4912-9aec-fffaf7d2709e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74184
7780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.741847780
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.1275615949
Short name T345
Test name
Test status
Simulation time 10085436017 ps
CPU time 15.22 seconds
Started Jun 02 03:29:31 PM PDT 24
Finished Jun 02 03:29:47 PM PDT 24
Peak memory 205596 kb
Host smart-c7328aac-18a1-4e09-87f7-c7fb43b660c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12756
15949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.1275615949
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.1523145339
Short name T2006
Test name
Test status
Simulation time 13229947089 ps
CPU time 17.39 seconds
Started Jun 02 03:29:31 PM PDT 24
Finished Jun 02 03:29:50 PM PDT 24
Peak memory 205708 kb
Host smart-497a5f54-5eda-45bf-9fac-2efee529410c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15231
45339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.1523145339
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.3957195091
Short name T1948
Test name
Test status
Simulation time 10085454543 ps
CPU time 12.75 seconds
Started Jun 02 03:29:28 PM PDT 24
Finished Jun 02 03:29:42 PM PDT 24
Peak memory 205728 kb
Host smart-5f7eb368-b17a-40f5-88e1-2fc8653b61f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39571
95091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.3957195091
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.4130938792
Short name T1083
Test name
Test status
Simulation time 19638079640 ps
CPU time 277.08 seconds
Started Jun 02 03:29:34 PM PDT 24
Finished Jun 02 03:34:12 PM PDT 24
Peak memory 205660 kb
Host smart-dc552fd0-784a-444b-81f5-c14cf0713bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41309
38792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.4130938792
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3348727323
Short name T887
Test name
Test status
Simulation time 10072090737 ps
CPU time 15.8 seconds
Started Jun 02 03:29:28 PM PDT 24
Finished Jun 02 03:29:45 PM PDT 24
Peak memory 205780 kb
Host smart-750716c7-31d4-4b1d-8c17-ccb59340fa97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33487
27323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3348727323
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.2511680310
Short name T129
Test name
Test status
Simulation time 10111591307 ps
CPU time 15.04 seconds
Started Jun 02 03:29:27 PM PDT 24
Finished Jun 02 03:29:44 PM PDT 24
Peak memory 205716 kb
Host smart-071ab581-0936-4bcc-94d9-063cbc494c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25116
80310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.2511680310
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.4208050471
Short name T502
Test name
Test status
Simulation time 10090604056 ps
CPU time 13.31 seconds
Started Jun 02 03:29:30 PM PDT 24
Finished Jun 02 03:29:45 PM PDT 24
Peak memory 205640 kb
Host smart-7973ada0-0cf1-483e-81a0-46d345ef3c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42080
50471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.4208050471
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2302078175
Short name T583
Test name
Test status
Simulation time 10128343938 ps
CPU time 13.17 seconds
Started Jun 02 03:29:32 PM PDT 24
Finished Jun 02 03:29:46 PM PDT 24
Peak memory 205672 kb
Host smart-dec0268d-b38c-45f3-8bd5-4dca7568a60a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23020
78175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2302078175
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3584593970
Short name T387
Test name
Test status
Simulation time 10085208618 ps
CPU time 13.75 seconds
Started Jun 02 03:29:35 PM PDT 24
Finished Jun 02 03:29:49 PM PDT 24
Peak memory 205636 kb
Host smart-d6f9d3b1-04ef-4b81-a2c9-017f4127056a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35845
93970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3584593970
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.3955235620
Short name T901
Test name
Test status
Simulation time 10076713586 ps
CPU time 15.43 seconds
Started Jun 02 03:29:30 PM PDT 24
Finished Jun 02 03:29:46 PM PDT 24
Peak memory 205676 kb
Host smart-1573bb93-d05c-4a44-aeeb-58d707d82710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39552
35620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.3955235620
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_eop_single_bit_handling.1103223609
Short name T740
Test name
Test status
Simulation time 10094834915 ps
CPU time 12.86 seconds
Started Jun 02 03:29:35 PM PDT 24
Finished Jun 02 03:29:49 PM PDT 24
Peak memory 205608 kb
Host smart-0f29e22a-e0d8-4ed1-81d5-94c9d4e9c874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11032
23609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_eop_single_bit_handling.1103223609
Directory /workspace/21.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1847006843
Short name T585
Test name
Test status
Simulation time 10098411220 ps
CPU time 13.63 seconds
Started Jun 02 03:29:30 PM PDT 24
Finished Jun 02 03:29:45 PM PDT 24
Peak memory 205788 kb
Host smart-8deff768-732b-4924-af0a-0e44f6c169a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18470
06843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1847006843
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2607243356
Short name T1724
Test name
Test status
Simulation time 10039664680 ps
CPU time 15.42 seconds
Started Jun 02 03:29:36 PM PDT 24
Finished Jun 02 03:29:52 PM PDT 24
Peak memory 205700 kb
Host smart-1dabbb35-4534-4ad3-82b2-c3fdae1332dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26072
43356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2607243356
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.3030194451
Short name T176
Test name
Test status
Simulation time 18793786759 ps
CPU time 33.38 seconds
Started Jun 02 03:29:32 PM PDT 24
Finished Jun 02 03:30:06 PM PDT 24
Peak memory 205608 kb
Host smart-80e860fb-93ff-4049-989e-6354ac14a13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30301
94451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.3030194451
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.2004372664
Short name T1485
Test name
Test status
Simulation time 10063527560 ps
CPU time 16.89 seconds
Started Jun 02 03:29:31 PM PDT 24
Finished Jun 02 03:29:49 PM PDT 24
Peak memory 205668 kb
Host smart-07cfbc0c-06ed-4e59-ab8a-b4a6b00f47d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20043
72664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.2004372664
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.936480614
Short name T1610
Test name
Test status
Simulation time 10136040302 ps
CPU time 13.46 seconds
Started Jun 02 03:29:31 PM PDT 24
Finished Jun 02 03:29:46 PM PDT 24
Peak memory 205608 kb
Host smart-4625d364-3ae0-4c56-9fd8-944902124566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93648
0614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.936480614
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.1341121607
Short name T1638
Test name
Test status
Simulation time 10132802440 ps
CPU time 12.83 seconds
Started Jun 02 03:29:36 PM PDT 24
Finished Jun 02 03:29:49 PM PDT 24
Peak memory 205676 kb
Host smart-3f0ee0fc-d3f7-47fc-a0a2-ebe5f3914f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13411
21607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.1341121607
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.2075176315
Short name T794
Test name
Test status
Simulation time 10053106622 ps
CPU time 12.59 seconds
Started Jun 02 03:29:34 PM PDT 24
Finished Jun 02 03:29:47 PM PDT 24
Peak memory 205684 kb
Host smart-7f9fe324-d17f-45c0-9dd7-6d4e76db9d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20751
76315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.2075176315
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.2363042955
Short name T146
Test name
Test status
Simulation time 10066214589 ps
CPU time 15.23 seconds
Started Jun 02 03:29:32 PM PDT 24
Finished Jun 02 03:29:48 PM PDT 24
Peak memory 205712 kb
Host smart-675a8c9e-b7a6-4c27-9143-0d8c8b5ee9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23630
42955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.2363042955
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.2154552826
Short name T1087
Test name
Test status
Simulation time 10050006121 ps
CPU time 12.9 seconds
Started Jun 02 03:29:29 PM PDT 24
Finished Jun 02 03:29:42 PM PDT 24
Peak memory 205760 kb
Host smart-fa7db1e1-6353-4a84-b7be-a2881fc3d1f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21545
52826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.2154552826
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.2857560825
Short name T975
Test name
Test status
Simulation time 10090410475 ps
CPU time 14.73 seconds
Started Jun 02 03:29:30 PM PDT 24
Finished Jun 02 03:29:46 PM PDT 24
Peak memory 205624 kb
Host smart-e6200191-015e-4aae-aa01-fd98c9cc66fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28575
60825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.2857560825
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.2674667905
Short name T1314
Test name
Test status
Simulation time 10080606876 ps
CPU time 14.84 seconds
Started Jun 02 03:29:31 PM PDT 24
Finished Jun 02 03:29:47 PM PDT 24
Peak memory 205732 kb
Host smart-f02e923f-34fa-424f-aca3-1ee874fac9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26746
67905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.2674667905
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.871054879
Short name T687
Test name
Test status
Simulation time 10055142303 ps
CPU time 14.64 seconds
Started Jun 02 03:29:30 PM PDT 24
Finished Jun 02 03:29:45 PM PDT 24
Peak memory 205732 kb
Host smart-b479809b-9e72-45b8-bc2a-c7e6b4437313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87105
4879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.871054879
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.4050099440
Short name T5
Test name
Test status
Simulation time 21931674458 ps
CPU time 121.43 seconds
Started Jun 02 03:29:30 PM PDT 24
Finished Jun 02 03:31:32 PM PDT 24
Peak memory 205680 kb
Host smart-da9fced0-73b9-4adb-a752-e3aa3c135454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40500
99440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.4050099440
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.4142951325
Short name T1449
Test name
Test status
Simulation time 10154879568 ps
CPU time 15.34 seconds
Started Jun 02 03:29:56 PM PDT 24
Finished Jun 02 03:30:12 PM PDT 24
Peak memory 205696 kb
Host smart-a64788e6-07b3-47d7-bee9-35d776d57097
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4142951325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.4142951325
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.4117977359
Short name T328
Test name
Test status
Simulation time 10099862446 ps
CPU time 16.56 seconds
Started Jun 02 03:29:43 PM PDT 24
Finished Jun 02 03:30:00 PM PDT 24
Peak memory 205800 kb
Host smart-64bd07fd-e996-41ae-bf46-c4c8b933417c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4117977359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.4117977359
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.945287501
Short name T297
Test name
Test status
Simulation time 10098349817 ps
CPU time 14.4 seconds
Started Jun 02 03:29:42 PM PDT 24
Finished Jun 02 03:29:57 PM PDT 24
Peak memory 205724 kb
Host smart-8766c464-d76c-46ef-b96f-f76bfd8abdd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94528
7501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.945287501
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.1165460154
Short name T1355
Test name
Test status
Simulation time 13773165598 ps
CPU time 17.8 seconds
Started Jun 02 03:29:38 PM PDT 24
Finished Jun 02 03:29:56 PM PDT 24
Peak memory 205636 kb
Host smart-0dfc2a6b-34fd-43e9-a0d2-f20790e645be
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1165460154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.1165460154
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.1036254431
Short name T1651
Test name
Test status
Simulation time 23268416876 ps
CPU time 30.47 seconds
Started Jun 02 03:29:41 PM PDT 24
Finished Jun 02 03:30:12 PM PDT 24
Peak memory 205708 kb
Host smart-905ef486-607d-400d-95f4-5ee22162cd77
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1036254431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.1036254431
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.727929209
Short name T1922
Test name
Test status
Simulation time 10056531225 ps
CPU time 12.8 seconds
Started Jun 02 03:29:34 PM PDT 24
Finished Jun 02 03:29:47 PM PDT 24
Peak memory 205720 kb
Host smart-019eb5db-cf3e-4da2-bd12-d1dd1b5aa361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72792
9209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.727929209
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.2210625389
Short name T1503
Test name
Test status
Simulation time 10382418560 ps
CPU time 14.56 seconds
Started Jun 02 03:29:35 PM PDT 24
Finished Jun 02 03:29:50 PM PDT 24
Peak memory 205732 kb
Host smart-dc0b7134-b8f7-4326-af72-bca3e1ee60e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22106
25389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.2210625389
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.1490872436
Short name T1407
Test name
Test status
Simulation time 10051783044 ps
CPU time 12.54 seconds
Started Jun 02 03:29:36 PM PDT 24
Finished Jun 02 03:29:49 PM PDT 24
Peak memory 205624 kb
Host smart-b6b21d8a-501c-4ebf-868a-bbc62e3fecbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14908
72436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.1490872436
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.392297006
Short name T1038
Test name
Test status
Simulation time 10065853250 ps
CPU time 13.57 seconds
Started Jun 02 03:29:44 PM PDT 24
Finished Jun 02 03:29:59 PM PDT 24
Peak memory 205776 kb
Host smart-5617fdeb-340a-4aaa-83bc-40288ba16247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39229
7006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.392297006
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.3071592235
Short name T521
Test name
Test status
Simulation time 10877007916 ps
CPU time 14.29 seconds
Started Jun 02 03:29:36 PM PDT 24
Finished Jun 02 03:29:51 PM PDT 24
Peak memory 205720 kb
Host smart-50957d6b-3cfc-4dd3-9952-6426be8fd86a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30715
92235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.3071592235
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.2716661571
Short name T526
Test name
Test status
Simulation time 10232422853 ps
CPU time 16.88 seconds
Started Jun 02 03:29:42 PM PDT 24
Finished Jun 02 03:30:00 PM PDT 24
Peak memory 205712 kb
Host smart-34d2d862-1149-4312-85af-cbebd9317797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27166
61571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.2716661571
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1338137729
Short name T758
Test name
Test status
Simulation time 10095964581 ps
CPU time 13.31 seconds
Started Jun 02 03:29:43 PM PDT 24
Finished Jun 02 03:29:57 PM PDT 24
Peak memory 205756 kb
Host smart-56272dd5-b35b-4b4e-bfcd-05853fafe7c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13381
37729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1338137729
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2404190510
Short name T683
Test name
Test status
Simulation time 10062812797 ps
CPU time 14.88 seconds
Started Jun 02 03:29:43 PM PDT 24
Finished Jun 02 03:29:59 PM PDT 24
Peak memory 205664 kb
Host smart-1720c60b-9845-4c80-a6fe-5b6015f59825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24041
90510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2404190510
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.2412124556
Short name T1052
Test name
Test status
Simulation time 10167283173 ps
CPU time 13.36 seconds
Started Jun 02 03:29:45 PM PDT 24
Finished Jun 02 03:29:59 PM PDT 24
Peak memory 205740 kb
Host smart-a290e229-89f4-45ed-985b-faf6a3f28e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24121
24556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.2412124556
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.3422765204
Short name T1772
Test name
Test status
Simulation time 10186478136 ps
CPU time 16.15 seconds
Started Jun 02 03:29:36 PM PDT 24
Finished Jun 02 03:29:52 PM PDT 24
Peak memory 205608 kb
Host smart-1e3712f3-b287-441d-9970-1591f0e19507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34227
65204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3422765204
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.2096139987
Short name T1533
Test name
Test status
Simulation time 13223632313 ps
CPU time 16.5 seconds
Started Jun 02 03:29:36 PM PDT 24
Finished Jun 02 03:29:53 PM PDT 24
Peak memory 205592 kb
Host smart-6f0cf1fe-5fe3-4b83-88d0-816455444029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20961
39987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.2096139987
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2683726559
Short name T1865
Test name
Test status
Simulation time 10101162996 ps
CPU time 14.12 seconds
Started Jun 02 03:29:38 PM PDT 24
Finished Jun 02 03:29:52 PM PDT 24
Peak memory 205780 kb
Host smart-7de3509d-c99c-4a3b-9455-b04cd2e6278b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26837
26559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2683726559
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.1607533321
Short name T936
Test name
Test status
Simulation time 23335447837 ps
CPU time 110.63 seconds
Started Jun 02 03:29:38 PM PDT 24
Finished Jun 02 03:31:29 PM PDT 24
Peak memory 205648 kb
Host smart-ddfdc4f7-1fbf-4b86-8656-a08864631a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16075
33321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.1607533321
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.699220259
Short name T872
Test name
Test status
Simulation time 10100699238 ps
CPU time 13.52 seconds
Started Jun 02 03:29:40 PM PDT 24
Finished Jun 02 03:29:54 PM PDT 24
Peak memory 205688 kb
Host smart-8415730f-fb80-438d-a637-8d5710f405d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69922
0259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.699220259
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.961274968
Short name T804
Test name
Test status
Simulation time 10066745321 ps
CPU time 13.25 seconds
Started Jun 02 03:29:40 PM PDT 24
Finished Jun 02 03:29:53 PM PDT 24
Peak memory 205748 kb
Host smart-e6d0645b-0f9d-4895-9ca1-e47b1efeb2bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96127
4968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.961274968
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.1441828453
Short name T1712
Test name
Test status
Simulation time 10101154145 ps
CPU time 13.85 seconds
Started Jun 02 03:29:41 PM PDT 24
Finished Jun 02 03:29:55 PM PDT 24
Peak memory 205688 kb
Host smart-8a71e522-f22d-4304-a015-30b2f1eec035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14418
28453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.1441828453
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.428375035
Short name T1867
Test name
Test status
Simulation time 10086169936 ps
CPU time 13.45 seconds
Started Jun 02 03:29:41 PM PDT 24
Finished Jun 02 03:29:56 PM PDT 24
Peak memory 205720 kb
Host smart-dfbadeaf-0707-4fc5-a7dc-686a2e6012ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42837
5035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.428375035
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1615078204
Short name T159
Test name
Test status
Simulation time 10043971907 ps
CPU time 13.05 seconds
Started Jun 02 03:29:43 PM PDT 24
Finished Jun 02 03:29:57 PM PDT 24
Peak memory 205616 kb
Host smart-0d90d5cd-bd59-47db-8b87-234ae9fa351e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16150
78204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1615078204
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_eop_single_bit_handling.702278062
Short name T1989
Test name
Test status
Simulation time 10053372902 ps
CPU time 13.46 seconds
Started Jun 02 03:29:40 PM PDT 24
Finished Jun 02 03:29:54 PM PDT 24
Peak memory 205724 kb
Host smart-d869c21e-de89-4bb9-902a-87db40eaf27c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70227
8062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_eop_single_bit_handling.702278062
Directory /workspace/22.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.4209537950
Short name T1946
Test name
Test status
Simulation time 10055861382 ps
CPU time 13.59 seconds
Started Jun 02 03:29:41 PM PDT 24
Finished Jun 02 03:29:56 PM PDT 24
Peak memory 205752 kb
Host smart-cecb90f0-d1ed-497c-b4d3-03f2dd28e293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42095
37950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.4209537950
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3308137527
Short name T1950
Test name
Test status
Simulation time 10041879198 ps
CPU time 13.97 seconds
Started Jun 02 03:29:43 PM PDT 24
Finished Jun 02 03:29:58 PM PDT 24
Peak memory 205628 kb
Host smart-a2720445-ed07-4ac0-af22-7ad194755dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33081
37527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3308137527
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.2178813396
Short name T565
Test name
Test status
Simulation time 10060660512 ps
CPU time 15.33 seconds
Started Jun 02 03:29:40 PM PDT 24
Finished Jun 02 03:29:55 PM PDT 24
Peak memory 205636 kb
Host smart-7617bf16-a0de-47c8-a3af-e407032f5216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21788
13396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2178813396
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.3963749686
Short name T352
Test name
Test status
Simulation time 10182596777 ps
CPU time 14.62 seconds
Started Jun 02 03:29:40 PM PDT 24
Finished Jun 02 03:29:55 PM PDT 24
Peak memory 205692 kb
Host smart-3184dca1-d580-4c71-a548-0fb446318861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39637
49686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.3963749686
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.1561635145
Short name T1176
Test name
Test status
Simulation time 10085505381 ps
CPU time 13.11 seconds
Started Jun 02 03:29:41 PM PDT 24
Finished Jun 02 03:29:55 PM PDT 24
Peak memory 205636 kb
Host smart-cfce9e6c-08bb-49d5-83f1-c827c4c87f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15616
35145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.1561635145
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.3185309848
Short name T1649
Test name
Test status
Simulation time 10047200010 ps
CPU time 13.87 seconds
Started Jun 02 03:29:39 PM PDT 24
Finished Jun 02 03:29:54 PM PDT 24
Peak memory 205656 kb
Host smart-8d7e1577-ffc8-4239-84f9-0a098071dc8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31853
09848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.3185309848
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.1891604533
Short name T1905
Test name
Test status
Simulation time 10054012681 ps
CPU time 13.64 seconds
Started Jun 02 03:29:42 PM PDT 24
Finished Jun 02 03:29:57 PM PDT 24
Peak memory 205664 kb
Host smart-115a502e-56dd-435a-b7ee-aebaa3d88c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18916
04533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.1891604533
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.3648931934
Short name T1532
Test name
Test status
Simulation time 10093381987 ps
CPU time 15.56 seconds
Started Jun 02 03:29:55 PM PDT 24
Finished Jun 02 03:30:12 PM PDT 24
Peak memory 205736 kb
Host smart-86cb9943-0521-4061-93a2-b63cd705754e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36489
31934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.3648931934
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.3048409079
Short name T1854
Test name
Test status
Simulation time 10104909952 ps
CPU time 13.88 seconds
Started Jun 02 03:29:38 PM PDT 24
Finished Jun 02 03:29:52 PM PDT 24
Peak memory 205588 kb
Host smart-60247ec3-b3a7-4008-865f-c71ec10205d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30484
09079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.3048409079
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.172667160
Short name T362
Test name
Test status
Simulation time 10044640223 ps
CPU time 13.07 seconds
Started Jun 02 03:29:43 PM PDT 24
Finished Jun 02 03:29:57 PM PDT 24
Peak memory 205708 kb
Host smart-8a26d119-233f-44be-acd7-85429d54ea8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17266
7160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.172667160
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2546323994
Short name T845
Test name
Test status
Simulation time 10091437365 ps
CPU time 13.03 seconds
Started Jun 02 03:29:56 PM PDT 24
Finished Jun 02 03:30:10 PM PDT 24
Peak memory 205708 kb
Host smart-7da4bb1a-127d-4cac-b2f5-8f73d79f5045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25463
23994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2546323994
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.2186553593
Short name T4
Test name
Test status
Simulation time 19554706385 ps
CPU time 107.13 seconds
Started Jun 02 03:29:43 PM PDT 24
Finished Jun 02 03:31:31 PM PDT 24
Peak memory 205608 kb
Host smart-81c76ea2-734e-449e-967a-99d62f65a805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21865
53593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.2186553593
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.2922299430
Short name T1958
Test name
Test status
Simulation time 10151068446 ps
CPU time 15.59 seconds
Started Jun 02 03:29:45 PM PDT 24
Finished Jun 02 03:30:01 PM PDT 24
Peak memory 205732 kb
Host smart-fd907a30-2cd6-4cf0-9ab3-e6341b575e9f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2922299430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.2922299430
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.3116523973
Short name T927
Test name
Test status
Simulation time 10107030900 ps
CPU time 14.04 seconds
Started Jun 02 03:29:46 PM PDT 24
Finished Jun 02 03:30:01 PM PDT 24
Peak memory 205772 kb
Host smart-5fc9a79e-8e70-462f-9935-d3d6232412b9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3116523973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.3116523973
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.3192480576
Short name T841
Test name
Test status
Simulation time 10147373782 ps
CPU time 14.48 seconds
Started Jun 02 03:29:47 PM PDT 24
Finished Jun 02 03:30:03 PM PDT 24
Peak memory 205740 kb
Host smart-cc1bb6d7-53f8-46a6-bbb7-3474ae8f2313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31924
80576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.3192480576
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.2625661865
Short name T1560
Test name
Test status
Simulation time 13710601861 ps
CPU time 16.91 seconds
Started Jun 02 03:29:41 PM PDT 24
Finished Jun 02 03:29:59 PM PDT 24
Peak memory 205660 kb
Host smart-b503a890-680b-47fe-be8b-17385d15e5e5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2625661865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.2625661865
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.640403207
Short name T866
Test name
Test status
Simulation time 23228439140 ps
CPU time 24.62 seconds
Started Jun 02 03:29:44 PM PDT 24
Finished Jun 02 03:30:09 PM PDT 24
Peak memory 205776 kb
Host smart-d358b036-90ff-4fbd-9702-eac3ffd9eb1d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=640403207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.640403207
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.225480862
Short name T1165
Test name
Test status
Simulation time 10053821971 ps
CPU time 16.02 seconds
Started Jun 02 03:29:44 PM PDT 24
Finished Jun 02 03:30:01 PM PDT 24
Peak memory 205780 kb
Host smart-b96d6a23-ec4d-4a14-b6e9-3fcb96ba147e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22548
0862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.225480862
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.3380426352
Short name T1216
Test name
Test status
Simulation time 10072178043 ps
CPU time 13.21 seconds
Started Jun 02 03:29:42 PM PDT 24
Finished Jun 02 03:29:56 PM PDT 24
Peak memory 205208 kb
Host smart-c303c35c-a5f0-4457-9b7e-4e9acf31df60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33804
26352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.3380426352
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.2050408821
Short name T1313
Test name
Test status
Simulation time 10459268756 ps
CPU time 13.98 seconds
Started Jun 02 03:29:43 PM PDT 24
Finished Jun 02 03:29:59 PM PDT 24
Peak memory 205700 kb
Host smart-03049a3d-79fb-4df1-b926-cff5f412fbb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20504
08821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.2050408821
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.1422944280
Short name T1831
Test name
Test status
Simulation time 10078044241 ps
CPU time 14.58 seconds
Started Jun 02 03:29:43 PM PDT 24
Finished Jun 02 03:29:59 PM PDT 24
Peak memory 205672 kb
Host smart-11789df6-2e97-4a7c-9ba1-22bbc0f81b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14229
44280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.1422944280
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.246530997
Short name T217
Test name
Test status
Simulation time 10056673544 ps
CPU time 14.05 seconds
Started Jun 02 03:29:43 PM PDT 24
Finished Jun 02 03:29:58 PM PDT 24
Peak memory 205608 kb
Host smart-ed6fd08b-e318-4d0a-a0a4-b3b46f617b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24653
0997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.246530997
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.1474598154
Short name T878
Test name
Test status
Simulation time 10731817184 ps
CPU time 15.12 seconds
Started Jun 02 03:29:41 PM PDT 24
Finished Jun 02 03:29:57 PM PDT 24
Peak memory 205660 kb
Host smart-85ea588a-fae1-461a-9b2c-55b9fd080482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14745
98154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.1474598154
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.4111912612
Short name T1823
Test name
Test status
Simulation time 10168533091 ps
CPU time 17.2 seconds
Started Jun 02 03:29:55 PM PDT 24
Finished Jun 02 03:30:13 PM PDT 24
Peak memory 205704 kb
Host smart-743f6582-903a-4677-badd-f8781ec8946c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41119
12612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.4111912612
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.890721336
Short name T736
Test name
Test status
Simulation time 10127354774 ps
CPU time 13.27 seconds
Started Jun 02 03:29:44 PM PDT 24
Finished Jun 02 03:29:58 PM PDT 24
Peak memory 205756 kb
Host smart-563a3759-b0ee-406d-af98-3a6343fe4e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89072
1336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.890721336
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.2169566057
Short name T1423
Test name
Test status
Simulation time 10108656570 ps
CPU time 13.75 seconds
Started Jun 02 03:29:43 PM PDT 24
Finished Jun 02 03:29:58 PM PDT 24
Peak memory 205688 kb
Host smart-d3ae4561-5a61-4c1e-bb88-d9b1ac9f763b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21695
66057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.2169566057
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.672859207
Short name T1878
Test name
Test status
Simulation time 10072656308 ps
CPU time 14.54 seconds
Started Jun 02 03:29:41 PM PDT 24
Finished Jun 02 03:29:57 PM PDT 24
Peak memory 205624 kb
Host smart-424781ba-e8e2-404e-b8b5-1a47cd0e3036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67285
9207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.672859207
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.3389785409
Short name T1074
Test name
Test status
Simulation time 13198373852 ps
CPU time 18.38 seconds
Started Jun 02 03:29:43 PM PDT 24
Finished Jun 02 03:30:02 PM PDT 24
Peak memory 205712 kb
Host smart-34a0c3c3-a085-48c6-9fdc-4d394ca441da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33897
85409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.3389785409
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.1955608175
Short name T1427
Test name
Test status
Simulation time 10118195236 ps
CPU time 15.36 seconds
Started Jun 02 03:29:41 PM PDT 24
Finished Jun 02 03:29:57 PM PDT 24
Peak memory 205792 kb
Host smart-c83226ea-7589-48b9-81c2-a8658aafeea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19556
08175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.1955608175
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.542181019
Short name T363
Test name
Test status
Simulation time 19135259991 ps
CPU time 102.16 seconds
Started Jun 02 03:29:45 PM PDT 24
Finished Jun 02 03:31:27 PM PDT 24
Peak memory 205712 kb
Host smart-4d410e9b-9a1e-45a4-b9f9-b3c3a7916b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54218
1019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.542181019
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.1413794404
Short name T1862
Test name
Test status
Simulation time 10050038438 ps
CPU time 13.76 seconds
Started Jun 02 03:29:56 PM PDT 24
Finished Jun 02 03:30:11 PM PDT 24
Peak memory 205704 kb
Host smart-389e976e-7bb2-4beb-b79d-d13a79368ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14137
94404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.1413794404
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2998245570
Short name T100
Test name
Test status
Simulation time 10082152703 ps
CPU time 13.33 seconds
Started Jun 02 03:29:43 PM PDT 24
Finished Jun 02 03:29:58 PM PDT 24
Peak memory 205764 kb
Host smart-dbff9a5f-30e1-4b61-a23d-6d306d36a031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29982
45570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2998245570
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.130362471
Short name T1353
Test name
Test status
Simulation time 10084403987 ps
CPU time 13.71 seconds
Started Jun 02 03:29:47 PM PDT 24
Finished Jun 02 03:30:02 PM PDT 24
Peak memory 205684 kb
Host smart-0826bab3-19f7-493b-98d3-2ea7d1fb2faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13036
2471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.130362471
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.1613060466
Short name T712
Test name
Test status
Simulation time 10085688740 ps
CPU time 13.27 seconds
Started Jun 02 03:29:45 PM PDT 24
Finished Jun 02 03:29:59 PM PDT 24
Peak memory 205780 kb
Host smart-5ad167ae-f349-4e2d-b71f-b12772b7520b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16130
60466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.1613060466
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.1389692151
Short name T552
Test name
Test status
Simulation time 10086340640 ps
CPU time 13.34 seconds
Started Jun 02 03:29:56 PM PDT 24
Finished Jun 02 03:30:10 PM PDT 24
Peak memory 205744 kb
Host smart-10b3fe2e-b720-4f5e-a098-a5dd26f589a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13896
92151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1389692151
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.819124502
Short name T132
Test name
Test status
Simulation time 10048606785 ps
CPU time 12.94 seconds
Started Jun 02 03:29:49 PM PDT 24
Finished Jun 02 03:30:02 PM PDT 24
Peak memory 205712 kb
Host smart-427ef702-81a3-4af3-b3ad-52b976fbcb09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81912
4502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.819124502
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_eop_single_bit_handling.3705509993
Short name T1155
Test name
Test status
Simulation time 10106923934 ps
CPU time 14.11 seconds
Started Jun 02 03:29:47 PM PDT 24
Finished Jun 02 03:30:02 PM PDT 24
Peak memory 205708 kb
Host smart-11da960f-6a82-4b83-b2da-49381206ce22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37055
09993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_eop_single_bit_handling.3705509993
Directory /workspace/23.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.2938828136
Short name T213
Test name
Test status
Simulation time 10058594548 ps
CPU time 16.25 seconds
Started Jun 02 03:29:47 PM PDT 24
Finished Jun 02 03:30:04 PM PDT 24
Peak memory 205688 kb
Host smart-25edf0a7-2c8d-4b3c-a038-caea7ebfab52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29388
28136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.2938828136
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.3022825214
Short name T880
Test name
Test status
Simulation time 10045922089 ps
CPU time 15.02 seconds
Started Jun 02 03:29:44 PM PDT 24
Finished Jun 02 03:30:00 PM PDT 24
Peak memory 205720 kb
Host smart-801765bb-f731-42a1-96b3-fc62f96c066a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30228
25214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.3022825214
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.1424686525
Short name T1107
Test name
Test status
Simulation time 23797258695 ps
CPU time 42.78 seconds
Started Jun 02 03:29:43 PM PDT 24
Finished Jun 02 03:30:27 PM PDT 24
Peak memory 205672 kb
Host smart-c40843d4-00ad-4d1d-9656-5c657b57991d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14246
86525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.1424686525
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.1531584837
Short name T371
Test name
Test status
Simulation time 10069496423 ps
CPU time 14.16 seconds
Started Jun 02 03:29:43 PM PDT 24
Finished Jun 02 03:29:58 PM PDT 24
Peak memory 205764 kb
Host smart-f14650b2-7709-41ae-8b0f-fb04dc79b90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15315
84837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.1531584837
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2128470191
Short name T1805
Test name
Test status
Simulation time 10077852433 ps
CPU time 14.63 seconds
Started Jun 02 03:29:44 PM PDT 24
Finished Jun 02 03:30:00 PM PDT 24
Peak memory 205560 kb
Host smart-62628ef8-04fe-415b-9953-6468f539f17b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21284
70191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2128470191
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.3043873738
Short name T1997
Test name
Test status
Simulation time 10052096592 ps
CPU time 13.88 seconds
Started Jun 02 03:29:46 PM PDT 24
Finished Jun 02 03:30:01 PM PDT 24
Peak memory 205556 kb
Host smart-15f71507-3b0f-4937-80b9-42226b0d50a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30438
73738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.3043873738
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2063531481
Short name T370
Test name
Test status
Simulation time 10084161932 ps
CPU time 14.54 seconds
Started Jun 02 03:29:48 PM PDT 24
Finished Jun 02 03:30:03 PM PDT 24
Peak memory 205680 kb
Host smart-d5e16282-3654-48d0-bb3a-9f5d51db2aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20635
31481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2063531481
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.2907289309
Short name T1611
Test name
Test status
Simulation time 10049484780 ps
CPU time 13.78 seconds
Started Jun 02 03:29:45 PM PDT 24
Finished Jun 02 03:30:00 PM PDT 24
Peak memory 205624 kb
Host smart-a06479b2-8ae7-499e-bee2-88db5ab28cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29072
89309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.2907289309
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.1325077426
Short name T1317
Test name
Test status
Simulation time 10054396215 ps
CPU time 14.09 seconds
Started Jun 02 03:29:47 PM PDT 24
Finished Jun 02 03:30:02 PM PDT 24
Peak memory 205776 kb
Host smart-325eb8c4-db29-498c-aced-6f78c53b5f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13250
77426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.1325077426
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.1325445745
Short name T1273
Test name
Test status
Simulation time 10122041677 ps
CPU time 15.74 seconds
Started Jun 02 03:29:42 PM PDT 24
Finished Jun 02 03:29:58 PM PDT 24
Peak memory 205612 kb
Host smart-d4cbcc07-b882-45e1-ae9d-370af1ae1103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13254
45745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.1325445745
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.2613751205
Short name T290
Test name
Test status
Simulation time 10088517612 ps
CPU time 12.77 seconds
Started Jun 02 03:29:45 PM PDT 24
Finished Jun 02 03:29:59 PM PDT 24
Peak memory 205668 kb
Host smart-0c8c7bd9-38c1-4bc6-8e9d-476e8ca88c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26137
51205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.2613751205
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.3319220197
Short name T1082
Test name
Test status
Simulation time 10062368626 ps
CPU time 14.11 seconds
Started Jun 02 03:29:49 PM PDT 24
Finished Jun 02 03:30:04 PM PDT 24
Peak memory 205716 kb
Host smart-cd431cde-498c-44ac-b864-1b58ffa3dae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33192
20197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.3319220197
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.1792546458
Short name T1152
Test name
Test status
Simulation time 21520238828 ps
CPU time 97.08 seconds
Started Jun 02 03:29:46 PM PDT 24
Finished Jun 02 03:31:24 PM PDT 24
Peak memory 205732 kb
Host smart-c8dad52c-c2e8-4c39-8e5a-e75b1eb8bc8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17925
46458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.1792546458
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.3814530249
Short name T1271
Test name
Test status
Simulation time 10165080968 ps
CPU time 13.51 seconds
Started Jun 02 03:29:57 PM PDT 24
Finished Jun 02 03:30:11 PM PDT 24
Peak memory 205772 kb
Host smart-60a62874-e894-4e12-8864-2d6dd9039bee
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3814530249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.3814530249
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.2332146264
Short name T714
Test name
Test status
Simulation time 10059188397 ps
CPU time 13.91 seconds
Started Jun 02 03:29:57 PM PDT 24
Finished Jun 02 03:30:12 PM PDT 24
Peak memory 205632 kb
Host smart-be388892-3a2b-4e3c-9354-3597da228587
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2332146264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.2332146264
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.1842302376
Short name T992
Test name
Test status
Simulation time 10115489649 ps
CPU time 15.83 seconds
Started Jun 02 03:29:58 PM PDT 24
Finished Jun 02 03:30:14 PM PDT 24
Peak memory 205592 kb
Host smart-f0c6bece-dba7-4ce5-8a7f-ba1cded7b63d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18423
02376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.1842302376
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.3826313506
Short name T993
Test name
Test status
Simulation time 14132558990 ps
CPU time 18.25 seconds
Started Jun 02 03:29:51 PM PDT 24
Finished Jun 02 03:30:10 PM PDT 24
Peak memory 205700 kb
Host smart-8fa27433-afc9-4559-bc8b-d076fb687fa5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3826313506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.3826313506
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.695377758
Short name T1360
Test name
Test status
Simulation time 23274569490 ps
CPU time 24.15 seconds
Started Jun 02 03:29:51 PM PDT 24
Finished Jun 02 03:30:16 PM PDT 24
Peak memory 205648 kb
Host smart-7dcb1c8e-2d7b-46be-a75f-c30a2fde43e9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=695377758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.695377758
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.634425116
Short name T1394
Test name
Test status
Simulation time 10111289136 ps
CPU time 16.72 seconds
Started Jun 02 03:29:52 PM PDT 24
Finished Jun 02 03:30:09 PM PDT 24
Peak memory 205764 kb
Host smart-e64938dc-a5e0-4e67-af05-0b63ece9af43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63442
5116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.634425116
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.1227770106
Short name T80
Test name
Test status
Simulation time 10933999510 ps
CPU time 17.93 seconds
Started Jun 02 03:29:51 PM PDT 24
Finished Jun 02 03:30:10 PM PDT 24
Peak memory 205628 kb
Host smart-3b741c33-75fc-4b38-a514-7f1a54e23809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12277
70106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.1227770106
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.1168200432
Short name T1752
Test name
Test status
Simulation time 10041758416 ps
CPU time 15.84 seconds
Started Jun 02 03:29:51 PM PDT 24
Finished Jun 02 03:30:08 PM PDT 24
Peak memory 205592 kb
Host smart-b6fa1d85-3194-4a38-a178-a918be0c1dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11682
00432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.1168200432
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.4241794155
Short name T919
Test name
Test status
Simulation time 10076737513 ps
CPU time 16.24 seconds
Started Jun 02 03:29:51 PM PDT 24
Finished Jun 02 03:30:07 PM PDT 24
Peak memory 205672 kb
Host smart-3e4c7297-da5b-467a-b60c-4ec62d2dbc7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42417
94155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.4241794155
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1178203185
Short name T1393
Test name
Test status
Simulation time 10220157716 ps
CPU time 15.89 seconds
Started Jun 02 03:29:51 PM PDT 24
Finished Jun 02 03:30:07 PM PDT 24
Peak memory 205700 kb
Host smart-1342351d-b4cf-4e97-9867-5ebc9375b9f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11782
03185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1178203185
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.1409300062
Short name T1343
Test name
Test status
Simulation time 10060221229 ps
CPU time 14.07 seconds
Started Jun 02 03:29:55 PM PDT 24
Finished Jun 02 03:30:10 PM PDT 24
Peak memory 205692 kb
Host smart-b22906d7-9153-4372-9281-f956e5262b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14093
00062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.1409300062
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.680306262
Short name T1947
Test name
Test status
Simulation time 10076286680 ps
CPU time 13.13 seconds
Started Jun 02 03:29:57 PM PDT 24
Finished Jun 02 03:30:11 PM PDT 24
Peak memory 205608 kb
Host smart-39a2745b-76f3-4b8f-b972-94af619473f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68030
6262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.680306262
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.407140387
Short name T1957
Test name
Test status
Simulation time 10064603560 ps
CPU time 13.72 seconds
Started Jun 02 03:29:56 PM PDT 24
Finished Jun 02 03:30:10 PM PDT 24
Peak memory 205640 kb
Host smart-44b7c51d-06f7-4b3f-8217-2572103d4d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40714
0387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.407140387
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.2672988992
Short name T668
Test name
Test status
Simulation time 10120919287 ps
CPU time 13.16 seconds
Started Jun 02 03:29:54 PM PDT 24
Finished Jun 02 03:30:08 PM PDT 24
Peak memory 205556 kb
Host smart-0c404365-bc1c-48d6-b5c4-4b0328e088e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26729
88992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.2672988992
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.1425703360
Short name T678
Test name
Test status
Simulation time 13194411081 ps
CPU time 15.55 seconds
Started Jun 02 03:29:55 PM PDT 24
Finished Jun 02 03:30:12 PM PDT 24
Peak memory 205684 kb
Host smart-d3b8667f-4dba-45f5-a4cc-e69c9fa31fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14257
03360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.1425703360
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.204864827
Short name T1342
Test name
Test status
Simulation time 10116515565 ps
CPU time 15.59 seconds
Started Jun 02 03:29:56 PM PDT 24
Finished Jun 02 03:30:13 PM PDT 24
Peak memory 205708 kb
Host smart-e8108164-9699-4cf3-a5fd-618fbecd5f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20486
4827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.204864827
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.3981825901
Short name T1518
Test name
Test status
Simulation time 19980639413 ps
CPU time 93.74 seconds
Started Jun 02 03:29:50 PM PDT 24
Finished Jun 02 03:31:25 PM PDT 24
Peak memory 205676 kb
Host smart-9950c2e3-424b-4c4f-826a-c469ebb2c658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39818
25901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.3981825901
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.1329371649
Short name T316
Test name
Test status
Simulation time 10072816505 ps
CPU time 16.09 seconds
Started Jun 02 03:29:53 PM PDT 24
Finished Jun 02 03:30:10 PM PDT 24
Peak memory 205732 kb
Host smart-7fd0857c-9f28-4c78-a80a-3aef9899dc6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13293
71649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.1329371649
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.3914553686
Short name T1846
Test name
Test status
Simulation time 10151252441 ps
CPU time 14.81 seconds
Started Jun 02 03:29:55 PM PDT 24
Finished Jun 02 03:30:10 PM PDT 24
Peak memory 205836 kb
Host smart-ed546083-d836-4480-9b91-9d9a755ab9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39145
53686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.3914553686
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.2172272426
Short name T70
Test name
Test status
Simulation time 10084169592 ps
CPU time 16.74 seconds
Started Jun 02 03:29:56 PM PDT 24
Finished Jun 02 03:30:14 PM PDT 24
Peak memory 205684 kb
Host smart-08bb167f-a582-4b2c-a06c-f9f00d10301e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21722
72426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.2172272426
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.2498639139
Short name T306
Test name
Test status
Simulation time 10058198656 ps
CPU time 13.41 seconds
Started Jun 02 03:29:54 PM PDT 24
Finished Jun 02 03:30:08 PM PDT 24
Peak memory 205768 kb
Host smart-c8a917b5-4668-4c3f-bddc-5c393002924c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24986
39139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.2498639139
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.1010908516
Short name T1396
Test name
Test status
Simulation time 10070017581 ps
CPU time 14.36 seconds
Started Jun 02 03:29:56 PM PDT 24
Finished Jun 02 03:30:11 PM PDT 24
Peak memory 205700 kb
Host smart-6feeebe7-f09c-4094-a098-ea2cf26a924b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10109
08516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.1010908516
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.1883466285
Short name T1821
Test name
Test status
Simulation time 10085345250 ps
CPU time 14.88 seconds
Started Jun 02 03:29:55 PM PDT 24
Finished Jun 02 03:30:10 PM PDT 24
Peak memory 205760 kb
Host smart-b1473d4d-f3f2-474e-b726-6a4c628823e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18834
66285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.1883466285
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_eop_single_bit_handling.1334041505
Short name T298
Test name
Test status
Simulation time 10056777462 ps
CPU time 13.17 seconds
Started Jun 02 03:29:55 PM PDT 24
Finished Jun 02 03:30:09 PM PDT 24
Peak memory 205688 kb
Host smart-d742dc52-c7fc-4a41-991c-647dc8138b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13340
41505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_eop_single_bit_handling.1334041505
Directory /workspace/24.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.4283497450
Short name T417
Test name
Test status
Simulation time 10048038137 ps
CPU time 15.2 seconds
Started Jun 02 03:29:55 PM PDT 24
Finished Jun 02 03:30:12 PM PDT 24
Peak memory 205804 kb
Host smart-bde6d504-2cc7-4fe0-9da2-19b1f7e29809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42834
97450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.4283497450
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.1879644311
Short name T1881
Test name
Test status
Simulation time 10056881410 ps
CPU time 13.28 seconds
Started Jun 02 03:29:53 PM PDT 24
Finished Jun 02 03:30:07 PM PDT 24
Peak memory 205652 kb
Host smart-b1645712-67da-40f8-8fe2-c6b9d8f5c42f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18796
44311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.1879644311
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.1288587358
Short name T1434
Test name
Test status
Simulation time 18578259689 ps
CPU time 32.35 seconds
Started Jun 02 03:29:54 PM PDT 24
Finished Jun 02 03:30:27 PM PDT 24
Peak memory 205736 kb
Host smart-5a206735-01a1-48c4-9def-75ee8bf8ce6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12885
87358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.1288587358
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1744934577
Short name T671
Test name
Test status
Simulation time 10059010240 ps
CPU time 13.56 seconds
Started Jun 02 03:29:51 PM PDT 24
Finished Jun 02 03:30:05 PM PDT 24
Peak memory 205592 kb
Host smart-6d1f538b-8638-4951-b257-375e90770114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17449
34577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1744934577
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.124473890
Short name T469
Test name
Test status
Simulation time 10078171594 ps
CPU time 13.6 seconds
Started Jun 02 03:29:50 PM PDT 24
Finished Jun 02 03:30:04 PM PDT 24
Peak memory 205800 kb
Host smart-c1dbb069-2774-476c-b42b-7bf7b04460c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12447
3890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.124473890
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.3907965764
Short name T314
Test name
Test status
Simulation time 10059714938 ps
CPU time 13.17 seconds
Started Jun 02 03:29:55 PM PDT 24
Finished Jun 02 03:30:09 PM PDT 24
Peak memory 205628 kb
Host smart-bec75a45-bbf7-4e33-a26f-5a3014cb02cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39079
65764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.3907965764
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.174443092
Short name T1703
Test name
Test status
Simulation time 10043242369 ps
CPU time 13.83 seconds
Started Jun 02 03:29:55 PM PDT 24
Finished Jun 02 03:30:10 PM PDT 24
Peak memory 205668 kb
Host smart-ceda8861-bf66-4836-9fc2-e1553d862b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17444
3092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.174443092
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.303811003
Short name T1149
Test name
Test status
Simulation time 10108374997 ps
CPU time 13.33 seconds
Started Jun 02 03:29:58 PM PDT 24
Finished Jun 02 03:30:12 PM PDT 24
Peak memory 205668 kb
Host smart-24303b6c-25ba-489b-81bc-c0d56514eee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30381
1003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.303811003
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.438725901
Short name T404
Test name
Test status
Simulation time 10065534531 ps
CPU time 14.09 seconds
Started Jun 02 03:29:57 PM PDT 24
Finished Jun 02 03:30:12 PM PDT 24
Peak memory 205704 kb
Host smart-f78b54c0-f181-43a4-af09-25faf0fb1090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43872
5901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.438725901
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.1436905161
Short name T1576
Test name
Test status
Simulation time 10129751988 ps
CPU time 15.27 seconds
Started Jun 02 03:29:52 PM PDT 24
Finished Jun 02 03:30:08 PM PDT 24
Peak memory 205728 kb
Host smart-4056c4ec-2645-4b02-8593-62faa43069b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14369
05161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1436905161
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.2978409296
Short name T2010
Test name
Test status
Simulation time 10119867484 ps
CPU time 13.48 seconds
Started Jun 02 03:29:57 PM PDT 24
Finished Jun 02 03:30:11 PM PDT 24
Peak memory 205700 kb
Host smart-08d4b175-fef5-453c-bc00-bb62f405b4ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29784
09296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.2978409296
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.1004003149
Short name T1902
Test name
Test status
Simulation time 10053011114 ps
CPU time 15.57 seconds
Started Jun 02 03:29:55 PM PDT 24
Finished Jun 02 03:30:11 PM PDT 24
Peak memory 205708 kb
Host smart-e1a19ad5-29c2-464a-b132-719d2060b8fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10040
03149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1004003149
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.3465539760
Short name T1581
Test name
Test status
Simulation time 17657939519 ps
CPU time 83.67 seconds
Started Jun 02 03:29:53 PM PDT 24
Finished Jun 02 03:31:17 PM PDT 24
Peak memory 205608 kb
Host smart-4ab5518e-3741-493a-b84a-2bee04d9d2b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34655
39760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.3465539760
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.432565812
Short name T1595
Test name
Test status
Simulation time 10141841107 ps
CPU time 13.8 seconds
Started Jun 02 03:30:08 PM PDT 24
Finished Jun 02 03:30:23 PM PDT 24
Peak memory 205764 kb
Host smart-0540f4f9-cf16-411e-948a-36621e227c18
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=432565812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.432565812
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.3125029334
Short name T1722
Test name
Test status
Simulation time 10087923658 ps
CPU time 13.53 seconds
Started Jun 02 03:30:11 PM PDT 24
Finished Jun 02 03:30:25 PM PDT 24
Peak memory 205784 kb
Host smart-d73de4d3-39e1-4180-92c2-1cf0aabbe970
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3125029334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.3125029334
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.2294665816
Short name T729
Test name
Test status
Simulation time 10108075152 ps
CPU time 12.91 seconds
Started Jun 02 03:30:05 PM PDT 24
Finished Jun 02 03:30:19 PM PDT 24
Peak memory 205744 kb
Host smart-c9b7f16d-4e9a-4160-bd3a-82a615f716e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22946
65816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.2294665816
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.4215586538
Short name T553
Test name
Test status
Simulation time 13847229749 ps
CPU time 16.67 seconds
Started Jun 02 03:29:57 PM PDT 24
Finished Jun 02 03:30:14 PM PDT 24
Peak memory 205716 kb
Host smart-d159d60e-f453-4b2a-9339-5eaef2e50dc0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4215586538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.4215586538
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.3358849333
Short name T728
Test name
Test status
Simulation time 23262706973 ps
CPU time 31.52 seconds
Started Jun 02 03:30:04 PM PDT 24
Finished Jun 02 03:30:37 PM PDT 24
Peak memory 205740 kb
Host smart-0d51231a-bf13-4bdc-97aa-9e79c3c246f2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3358849333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.3358849333
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.3779637895
Short name T1242
Test name
Test status
Simulation time 10050912224 ps
CPU time 12.64 seconds
Started Jun 02 03:29:56 PM PDT 24
Finished Jun 02 03:30:10 PM PDT 24
Peak memory 205676 kb
Host smart-bfe7bd1f-be32-42d5-925c-06b6f063c9d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37796
37895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.3779637895
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.2914269356
Short name T180
Test name
Test status
Simulation time 11115053818 ps
CPU time 16.87 seconds
Started Jun 02 03:30:01 PM PDT 24
Finished Jun 02 03:30:19 PM PDT 24
Peak memory 205716 kb
Host smart-3261c760-f376-4030-af26-8c31d9a820af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29142
69356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.2914269356
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.1871004330
Short name T1506
Test name
Test status
Simulation time 10088040247 ps
CPU time 15.23 seconds
Started Jun 02 03:30:00 PM PDT 24
Finished Jun 02 03:30:17 PM PDT 24
Peak memory 205708 kb
Host smart-018788a8-4843-4799-a13a-825d61186fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18710
04330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.1871004330
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.618202655
Short name T886
Test name
Test status
Simulation time 10073721655 ps
CPU time 15.27 seconds
Started Jun 02 03:29:58 PM PDT 24
Finished Jun 02 03:30:14 PM PDT 24
Peak memory 205732 kb
Host smart-5a2e5a09-fc1e-4928-98ba-2a8bfba52b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61820
2655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.618202655
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.104783289
Short name T1369
Test name
Test status
Simulation time 10827073755 ps
CPU time 14.22 seconds
Started Jun 02 03:30:00 PM PDT 24
Finished Jun 02 03:30:15 PM PDT 24
Peak memory 205628 kb
Host smart-bf93478e-2c08-4b49-be0f-a5ca892cfd39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10478
3289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.104783289
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.3754781589
Short name T1945
Test name
Test status
Simulation time 10070041698 ps
CPU time 15.77 seconds
Started Jun 02 03:30:04 PM PDT 24
Finished Jun 02 03:30:21 PM PDT 24
Peak memory 205620 kb
Host smart-e6b0cd8d-2fd9-4e7f-b313-d8d9c4745381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37547
81589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.3754781589
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.2222124915
Short name T643
Test name
Test status
Simulation time 10130069722 ps
CPU time 14.97 seconds
Started Jun 02 03:30:05 PM PDT 24
Finished Jun 02 03:30:21 PM PDT 24
Peak memory 205648 kb
Host smart-0e531923-730a-4860-95ac-325e3a80e957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22221
24915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.2222124915
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.2975064585
Short name T1616
Test name
Test status
Simulation time 10037939556 ps
CPU time 13.85 seconds
Started Jun 02 03:30:06 PM PDT 24
Finished Jun 02 03:30:20 PM PDT 24
Peak memory 205732 kb
Host smart-a1971490-907c-4a5a-be76-16d6a806f2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29750
64585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2975064585
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.898806338
Short name T522
Test name
Test status
Simulation time 10073262785 ps
CPU time 14.11 seconds
Started Jun 02 03:30:01 PM PDT 24
Finished Jun 02 03:30:16 PM PDT 24
Peak memory 205728 kb
Host smart-e19c4abc-72f3-4d26-825c-fa778b643fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89880
6338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.898806338
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.4001547550
Short name T1494
Test name
Test status
Simulation time 10100160852 ps
CPU time 13.94 seconds
Started Jun 02 03:30:01 PM PDT 24
Finished Jun 02 03:30:16 PM PDT 24
Peak memory 205860 kb
Host smart-dd44d58e-44bb-47bf-a931-a0b733f312bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40015
47550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.4001547550
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.4127549675
Short name T1787
Test name
Test status
Simulation time 13195814590 ps
CPU time 17.64 seconds
Started Jun 02 03:30:02 PM PDT 24
Finished Jun 02 03:30:21 PM PDT 24
Peak memory 205696 kb
Host smart-59a6cdf3-3489-4463-93a6-c85f998dadf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41275
49675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.4127549675
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.640405691
Short name T1645
Test name
Test status
Simulation time 10103327291 ps
CPU time 13.74 seconds
Started Jun 02 03:29:59 PM PDT 24
Finished Jun 02 03:30:14 PM PDT 24
Peak memory 205764 kb
Host smart-fb8b71ec-49c8-4e34-a4a0-26a5de595389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64040
5691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.640405691
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.1300882738
Short name T1711
Test name
Test status
Simulation time 22609579711 ps
CPU time 366.66 seconds
Started Jun 02 03:30:02 PM PDT 24
Finished Jun 02 03:36:10 PM PDT 24
Peak memory 205656 kb
Host smart-aeaf5846-3b63-4608-b20a-41463bd14593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13008
82738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.1300882738
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2533984503
Short name T1617
Test name
Test status
Simulation time 10078834417 ps
CPU time 14.24 seconds
Started Jun 02 03:30:00 PM PDT 24
Finished Jun 02 03:30:16 PM PDT 24
Peak memory 205664 kb
Host smart-e5529bc7-fc5c-4fe3-930d-d7c2b4b61ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25339
84503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2533984503
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.603569582
Short name T108
Test name
Test status
Simulation time 10109407057 ps
CPU time 13.43 seconds
Started Jun 02 03:29:59 PM PDT 24
Finished Jun 02 03:30:13 PM PDT 24
Peak memory 205724 kb
Host smart-b324b3e3-3f89-4967-98c1-a97e469cb181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60356
9582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.603569582
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.974359677
Short name T813
Test name
Test status
Simulation time 10059314585 ps
CPU time 13.44 seconds
Started Jun 02 03:30:02 PM PDT 24
Finished Jun 02 03:30:17 PM PDT 24
Peak memory 205680 kb
Host smart-043b67b7-d1d2-464e-9ce5-c7a33e99ba0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97435
9677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.974359677
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.1156857208
Short name T1106
Test name
Test status
Simulation time 10069479793 ps
CPU time 12.94 seconds
Started Jun 02 03:30:13 PM PDT 24
Finished Jun 02 03:30:27 PM PDT 24
Peak memory 205616 kb
Host smart-2d68dd10-b882-465b-a8f6-017e85de5169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11568
57208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.1156857208
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.265092363
Short name T1872
Test name
Test status
Simulation time 10085401300 ps
CPU time 14.59 seconds
Started Jun 02 03:30:05 PM PDT 24
Finished Jun 02 03:30:20 PM PDT 24
Peak memory 205584 kb
Host smart-ad67ac0e-6288-4e68-a4e0-15035a415f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26509
2363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.265092363
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.3071701118
Short name T1412
Test name
Test status
Simulation time 10104237305 ps
CPU time 13.19 seconds
Started Jun 02 03:30:03 PM PDT 24
Finished Jun 02 03:30:18 PM PDT 24
Peak memory 205724 kb
Host smart-ee012e15-d54a-4b2e-aae9-60e04aa34d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30717
01118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.3071701118
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_eop_single_bit_handling.4000497067
Short name T759
Test name
Test status
Simulation time 10083904387 ps
CPU time 14.07 seconds
Started Jun 02 03:30:14 PM PDT 24
Finished Jun 02 03:30:29 PM PDT 24
Peak memory 205652 kb
Host smart-c8a5e7a1-6e06-40ad-8f3e-12f486529360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40004
97067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_eop_single_bit_handling.4000497067
Directory /workspace/25.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.666502994
Short name T827
Test name
Test status
Simulation time 10046037421 ps
CPU time 13.95 seconds
Started Jun 02 03:30:14 PM PDT 24
Finished Jun 02 03:30:29 PM PDT 24
Peak memory 205680 kb
Host smart-972d17e1-b3b5-4898-ab1d-6e7365c1c26d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66650
2994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.666502994
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.872449716
Short name T380
Test name
Test status
Simulation time 10040282934 ps
CPU time 14.63 seconds
Started Jun 02 03:30:11 PM PDT 24
Finished Jun 02 03:30:26 PM PDT 24
Peak memory 205732 kb
Host smart-b1dc421d-f94e-465a-a67a-cf38916cd2b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87244
9716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.872449716
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.3438283242
Short name T1984
Test name
Test status
Simulation time 25073872412 ps
CPU time 43.52 seconds
Started Jun 02 03:30:09 PM PDT 24
Finished Jun 02 03:30:53 PM PDT 24
Peak memory 205692 kb
Host smart-9157f5df-4168-4a4a-adfc-58977ab4ce56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34382
83242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.3438283242
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1739949514
Short name T1580
Test name
Test status
Simulation time 10044525210 ps
CPU time 12.69 seconds
Started Jun 02 03:30:14 PM PDT 24
Finished Jun 02 03:30:27 PM PDT 24
Peak memory 205656 kb
Host smart-1a9e2797-6c85-4e3b-bc17-f99916991478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17399
49514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1739949514
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.3823717150
Short name T1896
Test name
Test status
Simulation time 10113697803 ps
CPU time 13.89 seconds
Started Jun 02 03:30:08 PM PDT 24
Finished Jun 02 03:30:23 PM PDT 24
Peak memory 205660 kb
Host smart-80a77991-2d7d-40b5-b0e5-59f2138a12ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38237
17150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3823717150
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.4234878996
Short name T325
Test name
Test status
Simulation time 10057691781 ps
CPU time 14.51 seconds
Started Jun 02 03:30:08 PM PDT 24
Finished Jun 02 03:30:23 PM PDT 24
Peak memory 205672 kb
Host smart-d43963e3-670d-4a98-a9a2-dce379ff8c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42348
78996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.4234878996
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.52036635
Short name T1860
Test name
Test status
Simulation time 10061302422 ps
CPU time 13.61 seconds
Started Jun 02 03:30:08 PM PDT 24
Finished Jun 02 03:30:23 PM PDT 24
Peak memory 205628 kb
Host smart-9e3fc842-44ba-4a57-ae81-b965598fe96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52036
635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.52036635
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.4196087400
Short name T1959
Test name
Test status
Simulation time 10104925425 ps
CPU time 12.85 seconds
Started Jun 02 03:30:13 PM PDT 24
Finished Jun 02 03:30:26 PM PDT 24
Peak memory 205708 kb
Host smart-fa565ef6-8180-4f86-82d1-940e22980c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41960
87400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.4196087400
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3270714543
Short name T518
Test name
Test status
Simulation time 10049739536 ps
CPU time 15.9 seconds
Started Jun 02 03:30:08 PM PDT 24
Finished Jun 02 03:30:25 PM PDT 24
Peak memory 205772 kb
Host smart-c6ab7ba4-fdd1-4d88-a8ee-3eb511bcec9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32707
14543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3270714543
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2316315347
Short name T147
Test name
Test status
Simulation time 10095861474 ps
CPU time 13.41 seconds
Started Jun 02 03:29:55 PM PDT 24
Finished Jun 02 03:30:09 PM PDT 24
Peak memory 205636 kb
Host smart-5fb96ad4-09a4-4126-adb1-4a62511733d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23163
15347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2316315347
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.1976423763
Short name T801
Test name
Test status
Simulation time 10076169233 ps
CPU time 14.65 seconds
Started Jun 02 03:30:04 PM PDT 24
Finished Jun 02 03:30:20 PM PDT 24
Peak memory 205648 kb
Host smart-94083b49-34da-4abc-bd72-590318d55dab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19764
23763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.1976423763
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.1345129380
Short name T1983
Test name
Test status
Simulation time 10079490744 ps
CPU time 14.24 seconds
Started Jun 02 03:30:13 PM PDT 24
Finished Jun 02 03:30:28 PM PDT 24
Peak memory 205640 kb
Host smart-548a5389-2680-487f-be46-9dfc39fd9d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13451
29380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.1345129380
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.3245479050
Short name T1185
Test name
Test status
Simulation time 21353453245 ps
CPU time 124.92 seconds
Started Jun 02 03:30:04 PM PDT 24
Finished Jun 02 03:32:10 PM PDT 24
Peak memory 205692 kb
Host smart-a0d72bf9-eecb-4462-9f38-a5fc1f246f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32454
79050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.3245479050
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.3412220446
Short name T974
Test name
Test status
Simulation time 10160219081 ps
CPU time 13.89 seconds
Started Jun 02 03:30:10 PM PDT 24
Finished Jun 02 03:30:24 PM PDT 24
Peak memory 206028 kb
Host smart-481761d0-1122-4017-8226-695d88631f16
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3412220446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.3412220446
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.1025780571
Short name T1094
Test name
Test status
Simulation time 10082791739 ps
CPU time 14.81 seconds
Started Jun 02 03:30:10 PM PDT 24
Finished Jun 02 03:30:26 PM PDT 24
Peak memory 205608 kb
Host smart-a2dd9c4e-e6a2-420a-b400-4c3a1a283104
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1025780571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.1025780571
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.3389203524
Short name T909
Test name
Test status
Simulation time 10126497152 ps
CPU time 13.51 seconds
Started Jun 02 03:30:09 PM PDT 24
Finished Jun 02 03:30:24 PM PDT 24
Peak memory 205580 kb
Host smart-a8689963-2c78-4dd5-b476-9bb2fce86195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33892
03524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.3389203524
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.1244836816
Short name T545
Test name
Test status
Simulation time 13788376197 ps
CPU time 20.14 seconds
Started Jun 02 03:30:08 PM PDT 24
Finished Jun 02 03:30:29 PM PDT 24
Peak memory 205748 kb
Host smart-02e76f01-f5b9-4306-b572-4b4163fc2e29
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1244836816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.1244836816
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.439065791
Short name T1539
Test name
Test status
Simulation time 23252561399 ps
CPU time 25.65 seconds
Started Jun 02 03:30:07 PM PDT 24
Finished Jun 02 03:30:33 PM PDT 24
Peak memory 205776 kb
Host smart-27a4a0da-48fd-44d7-b117-46c0dd2f16be
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=439065791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.439065791
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.527386518
Short name T632
Test name
Test status
Simulation time 10073077455 ps
CPU time 13.91 seconds
Started Jun 02 03:30:05 PM PDT 24
Finished Jun 02 03:30:20 PM PDT 24
Peak memory 205740 kb
Host smart-bdf8109a-d981-4e6e-9189-fa5c69685941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52738
6518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.527386518
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.2065214673
Short name T1500
Test name
Test status
Simulation time 10051000095 ps
CPU time 14.73 seconds
Started Jun 02 03:30:08 PM PDT 24
Finished Jun 02 03:30:23 PM PDT 24
Peak memory 205652 kb
Host smart-464fcd68-6eda-46d5-9c0b-b7b5629bb9ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20652
14673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.2065214673
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.163833307
Short name T1208
Test name
Test status
Simulation time 10331647339 ps
CPU time 13.64 seconds
Started Jun 02 03:30:07 PM PDT 24
Finished Jun 02 03:30:21 PM PDT 24
Peak memory 205764 kb
Host smart-8f6d3f0b-8532-4b73-a0cc-2aac874a4a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16383
3307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.163833307
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.786608441
Short name T1970
Test name
Test status
Simulation time 10066536942 ps
CPU time 12.71 seconds
Started Jun 02 03:30:03 PM PDT 24
Finished Jun 02 03:30:17 PM PDT 24
Peak memory 205736 kb
Host smart-ea3490a2-2980-4d14-9945-1b55c3901838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78660
8441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.786608441
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.4281222657
Short name T983
Test name
Test status
Simulation time 10090542741 ps
CPU time 13.18 seconds
Started Jun 02 03:30:08 PM PDT 24
Finished Jun 02 03:30:22 PM PDT 24
Peak memory 205672 kb
Host smart-de46df5c-676e-4eff-8ca1-e6d23c421b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42812
22657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.4281222657
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.3921460115
Short name T296
Test name
Test status
Simulation time 10854464704 ps
CPU time 14.45 seconds
Started Jun 02 03:30:07 PM PDT 24
Finished Jun 02 03:30:22 PM PDT 24
Peak memory 205756 kb
Host smart-88e8c607-1a35-4ccd-b043-98a465f1999d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39214
60115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.3921460115
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.764766995
Short name T566
Test name
Test status
Simulation time 10171872936 ps
CPU time 15.42 seconds
Started Jun 02 03:30:04 PM PDT 24
Finished Jun 02 03:30:21 PM PDT 24
Peak memory 205776 kb
Host smart-dfb17e31-0e44-4b0b-bf6d-ca8af31d9816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76476
6995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.764766995
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.2990644675
Short name T893
Test name
Test status
Simulation time 10141818345 ps
CPU time 15.06 seconds
Started Jun 02 03:30:13 PM PDT 24
Finished Jun 02 03:30:29 PM PDT 24
Peak memory 205744 kb
Host smart-bbeb9de1-7e4c-4c83-bbfa-d2eb29811236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29906
44675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.2990644675
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.3286147672
Short name T368
Test name
Test status
Simulation time 10060362877 ps
CPU time 13.66 seconds
Started Jun 02 03:30:08 PM PDT 24
Finished Jun 02 03:30:22 PM PDT 24
Peak memory 205724 kb
Host smart-3ed82348-f26f-4ff5-add3-74287567f98c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32861
47672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.3286147672
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.2850108093
Short name T634
Test name
Test status
Simulation time 10117546899 ps
CPU time 13.06 seconds
Started Jun 02 03:30:07 PM PDT 24
Finished Jun 02 03:30:20 PM PDT 24
Peak memory 205788 kb
Host smart-3d426cbe-10c4-4b48-bf44-c26eac922f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28501
08093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2850108093
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.1474925162
Short name T1578
Test name
Test status
Simulation time 10054952037 ps
CPU time 13.27 seconds
Started Jun 02 03:30:11 PM PDT 24
Finished Jun 02 03:30:25 PM PDT 24
Peak memory 205696 kb
Host smart-2f6836f6-7e04-4129-8856-581373029e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14749
25162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.1474925162
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.1181482908
Short name T1672
Test name
Test status
Simulation time 13204782223 ps
CPU time 20.33 seconds
Started Jun 02 03:30:14 PM PDT 24
Finished Jun 02 03:30:35 PM PDT 24
Peak memory 205628 kb
Host smart-71490629-21cf-4f5b-b765-e7bd50139e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11814
82908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.1181482908
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.2231662605
Short name T1748
Test name
Test status
Simulation time 10184627325 ps
CPU time 12.57 seconds
Started Jun 02 03:30:04 PM PDT 24
Finished Jun 02 03:30:18 PM PDT 24
Peak memory 205820 kb
Host smart-aea33712-1ada-4503-8d07-f7dc11e2f34b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22316
62605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.2231662605
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.4033330304
Short name T463
Test name
Test status
Simulation time 20421410365 ps
CPU time 114.84 seconds
Started Jun 02 03:30:09 PM PDT 24
Finished Jun 02 03:32:05 PM PDT 24
Peak memory 205724 kb
Host smart-eaf081aa-57a4-4901-8333-dca5acc99ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40333
30304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.4033330304
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1481552035
Short name T1417
Test name
Test status
Simulation time 10053331186 ps
CPU time 12.39 seconds
Started Jun 02 03:30:08 PM PDT 24
Finished Jun 02 03:30:21 PM PDT 24
Peak memory 205744 kb
Host smart-3c67bfce-cf7d-4640-bd33-f7fc20bfa7e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14815
52035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1481552035
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2787228977
Short name T1168
Test name
Test status
Simulation time 10124009618 ps
CPU time 14.4 seconds
Started Jun 02 03:30:14 PM PDT 24
Finished Jun 02 03:30:29 PM PDT 24
Peak memory 205580 kb
Host smart-efdbb6a0-a755-4fd1-9ee3-8ab189cd30bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27872
28977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2787228977
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.3985827119
Short name T1433
Test name
Test status
Simulation time 10082719095 ps
CPU time 14.67 seconds
Started Jun 02 03:30:09 PM PDT 24
Finished Jun 02 03:30:24 PM PDT 24
Peak memory 205684 kb
Host smart-734a7aab-1cbc-4401-b220-23cf01fb6d37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39858
27119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.3985827119
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.3520162931
Short name T1554
Test name
Test status
Simulation time 10071444997 ps
CPU time 14.47 seconds
Started Jun 02 03:30:10 PM PDT 24
Finished Jun 02 03:30:25 PM PDT 24
Peak memory 205664 kb
Host smart-3e99968f-6165-4706-9578-b1828a48e73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35201
62931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.3520162931
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.2956647237
Short name T1309
Test name
Test status
Simulation time 10083005354 ps
CPU time 16.58 seconds
Started Jun 02 03:30:13 PM PDT 24
Finished Jun 02 03:30:30 PM PDT 24
Peak memory 205708 kb
Host smart-fc455beb-ae42-472f-94b4-754747e7aa86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29566
47237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.2956647237
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.1554219671
Short name T165
Test name
Test status
Simulation time 10062867092 ps
CPU time 13.24 seconds
Started Jun 02 03:30:10 PM PDT 24
Finished Jun 02 03:30:24 PM PDT 24
Peak memory 205604 kb
Host smart-026ddf94-038e-4c7c-ab11-0c2987ad04f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15542
19671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.1554219671
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_eop_single_bit_handling.1055465559
Short name T1370
Test name
Test status
Simulation time 10066627223 ps
CPU time 13.88 seconds
Started Jun 02 03:30:09 PM PDT 24
Finished Jun 02 03:30:24 PM PDT 24
Peak memory 205696 kb
Host smart-fd364fb6-f446-4545-adff-7c177e1d4d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10554
65559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_eop_single_bit_handling.1055465559
Directory /workspace/26.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.279795806
Short name T1633
Test name
Test status
Simulation time 10046435561 ps
CPU time 13.89 seconds
Started Jun 02 03:30:13 PM PDT 24
Finished Jun 02 03:30:28 PM PDT 24
Peak memory 205572 kb
Host smart-bf53c5af-657d-42df-a208-473ac411606e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27979
5806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.279795806
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1417093493
Short name T365
Test name
Test status
Simulation time 10040060702 ps
CPU time 14.46 seconds
Started Jun 02 03:30:11 PM PDT 24
Finished Jun 02 03:30:27 PM PDT 24
Peak memory 205652 kb
Host smart-31504ded-864d-4b66-9bae-409ee75c2e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14170
93493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1417093493
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.3720736213
Short name T1405
Test name
Test status
Simulation time 10055935520 ps
CPU time 13.41 seconds
Started Jun 02 03:30:11 PM PDT 24
Finished Jun 02 03:30:26 PM PDT 24
Peak memory 205644 kb
Host smart-366bf236-a827-44e0-8a5d-904fcaa0644d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37207
36213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.3720736213
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1499368993
Short name T443
Test name
Test status
Simulation time 10101816795 ps
CPU time 15.14 seconds
Started Jun 02 03:30:10 PM PDT 24
Finished Jun 02 03:30:26 PM PDT 24
Peak memory 205696 kb
Host smart-ad5894c4-1e13-4961-8515-f3a1572763f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14993
68993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1499368993
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.3813154452
Short name T330
Test name
Test status
Simulation time 10119022443 ps
CPU time 13.25 seconds
Started Jun 02 03:30:12 PM PDT 24
Finished Jun 02 03:30:27 PM PDT 24
Peak memory 205680 kb
Host smart-198bd33b-9710-4ddd-9cef-d187459de342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38131
54452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.3813154452
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1147157970
Short name T1874
Test name
Test status
Simulation time 10036191706 ps
CPU time 12.68 seconds
Started Jun 02 03:30:11 PM PDT 24
Finished Jun 02 03:30:25 PM PDT 24
Peak memory 205700 kb
Host smart-97274d89-72c9-41e6-a03b-cde2596edc8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11471
57970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1147157970
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.1884095369
Short name T1535
Test name
Test status
Simulation time 10054495618 ps
CPU time 13.52 seconds
Started Jun 02 03:30:09 PM PDT 24
Finished Jun 02 03:30:23 PM PDT 24
Peak memory 205720 kb
Host smart-9b1202f5-cd74-42f4-bfc3-9ebc530e8a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18840
95369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.1884095369
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2528584738
Short name T662
Test name
Test status
Simulation time 10050590197 ps
CPU time 16.51 seconds
Started Jun 02 03:30:13 PM PDT 24
Finished Jun 02 03:30:30 PM PDT 24
Peak memory 205772 kb
Host smart-e2de0445-ba50-4215-8f70-143932e7a133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25285
84738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2528584738
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.1997221130
Short name T1523
Test name
Test status
Simulation time 10148009713 ps
CPU time 13.45 seconds
Started Jun 02 03:30:11 PM PDT 24
Finished Jun 02 03:30:26 PM PDT 24
Peak memory 205696 kb
Host smart-f7a66127-b174-4d86-8078-6c07ebd660af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19972
21130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1997221130
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.2560720424
Short name T1220
Test name
Test status
Simulation time 10104732829 ps
CPU time 12.97 seconds
Started Jun 02 03:30:11 PM PDT 24
Finished Jun 02 03:30:26 PM PDT 24
Peak memory 205744 kb
Host smart-9fc96050-9688-42bf-ad7a-d0092f10de10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25607
20424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.2560720424
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.2797672962
Short name T775
Test name
Test status
Simulation time 10067151639 ps
CPU time 15.09 seconds
Started Jun 02 03:30:13 PM PDT 24
Finished Jun 02 03:30:29 PM PDT 24
Peak memory 205612 kb
Host smart-5ef1483e-63a4-4ac3-9bd8-c6ab11e0b307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27976
72962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2797672962
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.1417844668
Short name T508
Test name
Test status
Simulation time 17161792431 ps
CPU time 216.54 seconds
Started Jun 02 03:30:11 PM PDT 24
Finished Jun 02 03:33:49 PM PDT 24
Peak memory 205676 kb
Host smart-f0cfed42-1ab4-4644-9b12-728f3de4d2cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14178
44668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.1417844668
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.2086812987
Short name T836
Test name
Test status
Simulation time 10138963967 ps
CPU time 12.97 seconds
Started Jun 02 03:30:22 PM PDT 24
Finished Jun 02 03:30:36 PM PDT 24
Peak memory 205800 kb
Host smart-45ececf2-20c4-4271-87bd-17edf41701d8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2086812987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.2086812987
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.1807841764
Short name T1079
Test name
Test status
Simulation time 10051142407 ps
CPU time 13.96 seconds
Started Jun 02 03:30:18 PM PDT 24
Finished Jun 02 03:30:33 PM PDT 24
Peak memory 205712 kb
Host smart-1198b131-9378-4a7d-869b-7bda19fadb8c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1807841764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.1807841764
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.2378886096
Short name T426
Test name
Test status
Simulation time 10078292404 ps
CPU time 14.62 seconds
Started Jun 02 03:30:22 PM PDT 24
Finished Jun 02 03:30:37 PM PDT 24
Peak memory 205676 kb
Host smart-458cd7bc-faa5-417d-b652-e92e4c9a27a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23788
86096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.2378886096
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.2973246884
Short name T1212
Test name
Test status
Simulation time 13598171908 ps
CPU time 17.26 seconds
Started Jun 02 03:30:17 PM PDT 24
Finished Jun 02 03:30:35 PM PDT 24
Peak memory 205672 kb
Host smart-32855199-44fb-4214-ae14-cc183c06fc9c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2973246884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.2973246884
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.3655769114
Short name T1723
Test name
Test status
Simulation time 23304387260 ps
CPU time 28.46 seconds
Started Jun 02 03:30:15 PM PDT 24
Finished Jun 02 03:30:44 PM PDT 24
Peak memory 205756 kb
Host smart-3259db8d-5d69-45e7-ae77-3d5da72b4d81
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3655769114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.3655769114
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.1664304623
Short name T1391
Test name
Test status
Simulation time 10071682520 ps
CPU time 13.34 seconds
Started Jun 02 03:30:14 PM PDT 24
Finished Jun 02 03:30:28 PM PDT 24
Peak memory 206016 kb
Host smart-d5f5e8af-32de-4972-b109-62ebff95b697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16643
04623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.1664304623
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.1400156910
Short name T2030
Test name
Test status
Simulation time 10440270443 ps
CPU time 14.65 seconds
Started Jun 02 03:30:15 PM PDT 24
Finished Jun 02 03:30:31 PM PDT 24
Peak memory 205636 kb
Host smart-f25984a5-da72-4c60-a448-a5092ea25971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14001
56910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.1400156910
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.1081127751
Short name T1266
Test name
Test status
Simulation time 10044138557 ps
CPU time 14.61 seconds
Started Jun 02 03:30:12 PM PDT 24
Finished Jun 02 03:30:28 PM PDT 24
Peak memory 205632 kb
Host smart-7cd98422-985a-4ab7-b877-70c41eebab88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10811
27751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.1081127751
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.3161015337
Short name T1820
Test name
Test status
Simulation time 10070578568 ps
CPU time 16.35 seconds
Started Jun 02 03:30:14 PM PDT 24
Finished Jun 02 03:30:31 PM PDT 24
Peak memory 205684 kb
Host smart-2c45f615-b9de-485a-8179-181f968483e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31610
15337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.3161015337
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.1650523270
Short name T1068
Test name
Test status
Simulation time 10906262601 ps
CPU time 14.7 seconds
Started Jun 02 03:30:13 PM PDT 24
Finished Jun 02 03:30:28 PM PDT 24
Peak memory 205612 kb
Host smart-87ec1cca-9489-479c-b577-c7d238a52924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16505
23270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.1650523270
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.911860884
Short name T1654
Test name
Test status
Simulation time 10195981922 ps
CPU time 16.29 seconds
Started Jun 02 03:30:16 PM PDT 24
Finished Jun 02 03:30:33 PM PDT 24
Peak memory 205684 kb
Host smart-a6f7b5c6-ffef-44f7-8c8e-a30ca04b3bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91186
0884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.911860884
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.1352741850
Short name T589
Test name
Test status
Simulation time 10070583994 ps
CPU time 13.4 seconds
Started Jun 02 03:30:19 PM PDT 24
Finished Jun 02 03:30:34 PM PDT 24
Peak memory 205976 kb
Host smart-af1c0f70-5e0f-4137-8c57-528cab266413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13527
41850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.1352741850
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.1460246259
Short name T410
Test name
Test status
Simulation time 10050186267 ps
CPU time 15.38 seconds
Started Jun 02 03:30:19 PM PDT 24
Finished Jun 02 03:30:35 PM PDT 24
Peak memory 205852 kb
Host smart-65ade84c-db49-4a75-9f9d-10fba939bb42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14602
46259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.1460246259
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.1225484165
Short name T1747
Test name
Test status
Simulation time 10075072794 ps
CPU time 14.25 seconds
Started Jun 02 03:30:16 PM PDT 24
Finished Jun 02 03:30:31 PM PDT 24
Peak memory 205684 kb
Host smart-a0509c9d-c7e3-49ea-9c7f-0dd06b37936a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12254
84165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.1225484165
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.2165580756
Short name T918
Test name
Test status
Simulation time 10118553196 ps
CPU time 13.02 seconds
Started Jun 02 03:30:15 PM PDT 24
Finished Jun 02 03:30:29 PM PDT 24
Peak memory 205788 kb
Host smart-a9e3fbde-1c4b-453a-ac62-30cdac900ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21655
80756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.2165580756
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.4199575334
Short name T1806
Test name
Test status
Simulation time 13238278741 ps
CPU time 17.82 seconds
Started Jun 02 03:30:14 PM PDT 24
Finished Jun 02 03:30:32 PM PDT 24
Peak memory 205636 kb
Host smart-221fdaa7-c414-49fa-aa94-7df7d9e358f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41995
75334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.4199575334
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.3758488216
Short name T654
Test name
Test status
Simulation time 10083433366 ps
CPU time 13.97 seconds
Started Jun 02 03:30:15 PM PDT 24
Finished Jun 02 03:30:29 PM PDT 24
Peak memory 205656 kb
Host smart-c38f9dba-fa20-4d19-b2fd-e054973371fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37584
88216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.3758488216
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.4226047516
Short name T1840
Test name
Test status
Simulation time 17187783440 ps
CPU time 66.21 seconds
Started Jun 02 03:30:16 PM PDT 24
Finished Jun 02 03:31:23 PM PDT 24
Peak memory 205676 kb
Host smart-6d455e15-34d7-430c-bae9-e15f3bbb3f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42260
47516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.4226047516
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.3496316000
Short name T1901
Test name
Test status
Simulation time 10102425283 ps
CPU time 12.92 seconds
Started Jun 02 03:30:18 PM PDT 24
Finished Jun 02 03:30:32 PM PDT 24
Peak memory 205652 kb
Host smart-bffd1f3b-6068-43af-a121-c301fdda6af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34963
16000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.3496316000
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.174547738
Short name T1476
Test name
Test status
Simulation time 10111531199 ps
CPU time 14.76 seconds
Started Jun 02 03:30:18 PM PDT 24
Finished Jun 02 03:30:33 PM PDT 24
Peak memory 205560 kb
Host smart-e3c65e99-44b4-45f8-a5b2-497bc84fbe06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17454
7738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.174547738
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.3810154171
Short name T692
Test name
Test status
Simulation time 10052434826 ps
CPU time 13.38 seconds
Started Jun 02 03:30:16 PM PDT 24
Finished Jun 02 03:30:30 PM PDT 24
Peak memory 205684 kb
Host smart-a1ec38e2-7c9e-44fe-a9a1-dcf884e842f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38101
54171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.3810154171
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.3564425997
Short name T1010
Test name
Test status
Simulation time 10066972145 ps
CPU time 14.54 seconds
Started Jun 02 03:30:16 PM PDT 24
Finished Jun 02 03:30:31 PM PDT 24
Peak memory 205704 kb
Host smart-a5d1c2b5-b007-496c-8367-81b895adb7f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35644
25997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.3564425997
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.4210753385
Short name T1525
Test name
Test status
Simulation time 10114572140 ps
CPU time 13.36 seconds
Started Jun 02 03:30:14 PM PDT 24
Finished Jun 02 03:30:28 PM PDT 24
Peak memory 205720 kb
Host smart-c62a4f9f-f55e-487d-9af0-078a0d7f323f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42107
53385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.4210753385
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.1637158430
Short name T148
Test name
Test status
Simulation time 10099801320 ps
CPU time 12.87 seconds
Started Jun 02 03:30:21 PM PDT 24
Finished Jun 02 03:30:34 PM PDT 24
Peak memory 205672 kb
Host smart-f1525ba2-73e2-4bcc-86cb-6760dc314b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16371
58430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.1637158430
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_eop_single_bit_handling.3989963608
Short name T1385
Test name
Test status
Simulation time 10074805319 ps
CPU time 13.44 seconds
Started Jun 02 03:30:25 PM PDT 24
Finished Jun 02 03:30:40 PM PDT 24
Peak memory 205680 kb
Host smart-7e1f78e0-e075-48bc-914e-1b6c1a1da851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39899
63608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_eop_single_bit_handling.3989963608
Directory /workspace/27.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.1475216561
Short name T1608
Test name
Test status
Simulation time 10042379553 ps
CPU time 12.98 seconds
Started Jun 02 03:30:20 PM PDT 24
Finished Jun 02 03:30:34 PM PDT 24
Peak memory 205760 kb
Host smart-22748332-2691-4040-be30-706f12e8575c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14752
16561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.1475216561
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.2779355604
Short name T904
Test name
Test status
Simulation time 10101754292 ps
CPU time 13.15 seconds
Started Jun 02 03:30:19 PM PDT 24
Finished Jun 02 03:30:33 PM PDT 24
Peak memory 205752 kb
Host smart-4b10e76b-01a0-45a1-8e28-a4f53e72e704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27793
55604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.2779355604
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2967890640
Short name T619
Test name
Test status
Simulation time 21250903608 ps
CPU time 37.91 seconds
Started Jun 02 03:30:15 PM PDT 24
Finished Jun 02 03:30:53 PM PDT 24
Peak memory 205616 kb
Host smart-eb9cfc33-2cdf-41f7-bb3a-a11272fd1d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29678
90640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2967890640
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3695538097
Short name T611
Test name
Test status
Simulation time 10150424794 ps
CPU time 16.11 seconds
Started Jun 02 03:30:16 PM PDT 24
Finished Jun 02 03:30:33 PM PDT 24
Peak memory 205760 kb
Host smart-b1ccdd95-c454-4ba3-a01e-0ebdd0fbe260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36955
38097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3695538097
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.524757546
Short name T614
Test name
Test status
Simulation time 10064734521 ps
CPU time 14.39 seconds
Started Jun 02 03:30:15 PM PDT 24
Finished Jun 02 03:30:30 PM PDT 24
Peak memory 205728 kb
Host smart-8d37c1e6-571a-4bfd-ba99-366214967367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52475
7546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.524757546
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.3645653564
Short name T765
Test name
Test status
Simulation time 10099415478 ps
CPU time 14.29 seconds
Started Jun 02 03:30:17 PM PDT 24
Finished Jun 02 03:30:32 PM PDT 24
Peak memory 205732 kb
Host smart-c32534d2-c770-49cb-a643-7e882e07a509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36456
53564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.3645653564
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.316837650
Short name T1305
Test name
Test status
Simulation time 10048746004 ps
CPU time 14.56 seconds
Started Jun 02 03:30:16 PM PDT 24
Finished Jun 02 03:30:31 PM PDT 24
Peak memory 205656 kb
Host smart-83374402-2634-442f-b8c3-3bf8eb0d73eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31683
7650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.316837650
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.642064818
Short name T485
Test name
Test status
Simulation time 10067167305 ps
CPU time 14.37 seconds
Started Jun 02 03:30:19 PM PDT 24
Finished Jun 02 03:30:34 PM PDT 24
Peak memory 205708 kb
Host smart-7edc022b-c1ec-481f-960f-d7c39a5c4d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64206
4818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.642064818
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.242657954
Short name T1642
Test name
Test status
Simulation time 10048140298 ps
CPU time 13.89 seconds
Started Jun 02 03:30:18 PM PDT 24
Finished Jun 02 03:30:32 PM PDT 24
Peak memory 205668 kb
Host smart-63bcf79b-0f3f-4913-b998-bff7d200e306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24265
7954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.242657954
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.849388887
Short name T1450
Test name
Test status
Simulation time 10110026512 ps
CPU time 15.76 seconds
Started Jun 02 03:30:23 PM PDT 24
Finished Jun 02 03:30:40 PM PDT 24
Peak memory 205712 kb
Host smart-e18ac723-72cc-4950-9042-97e9e0fbffa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84938
8887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.849388887
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.1127580834
Short name T930
Test name
Test status
Simulation time 10060544938 ps
CPU time 12.95 seconds
Started Jun 02 03:30:18 PM PDT 24
Finished Jun 02 03:30:31 PM PDT 24
Peak memory 205656 kb
Host smart-82cc3d82-97e6-45f6-91c0-90f06421bccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11275
80834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1127580834
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.317624646
Short name T1364
Test name
Test status
Simulation time 19459007824 ps
CPU time 103.15 seconds
Started Jun 02 03:30:23 PM PDT 24
Finished Jun 02 03:32:07 PM PDT 24
Peak memory 205644 kb
Host smart-c1941241-9a19-467a-aadb-41397a83c60d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31762
4646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.317624646
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.61593091
Short name T1764
Test name
Test status
Simulation time 10154525076 ps
CPU time 13.02 seconds
Started Jun 02 03:30:32 PM PDT 24
Finished Jun 02 03:30:46 PM PDT 24
Peak memory 205696 kb
Host smart-73390161-9356-4d85-b9d2-48d395ae6439
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=61593091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.61593091
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.3729309026
Short name T1096
Test name
Test status
Simulation time 10060922944 ps
CPU time 13.39 seconds
Started Jun 02 03:30:31 PM PDT 24
Finished Jun 02 03:30:45 PM PDT 24
Peak memory 205684 kb
Host smart-da9c0407-5977-41bc-b4c3-978afc778392
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3729309026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.3729309026
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.1180702790
Short name T689
Test name
Test status
Simulation time 10067670335 ps
CPU time 16.97 seconds
Started Jun 02 03:30:25 PM PDT 24
Finished Jun 02 03:30:43 PM PDT 24
Peak memory 205676 kb
Host smart-cb04afd2-4628-423b-b837-89eea8617faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11807
02790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.1180702790
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.1764198078
Short name T1519
Test name
Test status
Simulation time 13607889848 ps
CPU time 17.02 seconds
Started Jun 02 03:30:24 PM PDT 24
Finished Jun 02 03:30:42 PM PDT 24
Peak memory 205700 kb
Host smart-d01417c5-b0e4-463b-b733-d1965f2046a0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1764198078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.1764198078
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.1704758036
Short name T1005
Test name
Test status
Simulation time 23259658615 ps
CPU time 33.36 seconds
Started Jun 02 03:30:22 PM PDT 24
Finished Jun 02 03:30:57 PM PDT 24
Peak memory 205756 kb
Host smart-7bf3b180-aa2e-4599-aaa8-f098c5e73df9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1704758036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.1704758036
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.2674911515
Short name T913
Test name
Test status
Simulation time 10117195274 ps
CPU time 14.32 seconds
Started Jun 02 03:30:19 PM PDT 24
Finished Jun 02 03:30:34 PM PDT 24
Peak memory 205704 kb
Host smart-91a01d75-ff5f-4936-9611-8649fa38f4c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26749
11515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.2674911515
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.2927903683
Short name T547
Test name
Test status
Simulation time 10047806257 ps
CPU time 12.43 seconds
Started Jun 02 03:30:21 PM PDT 24
Finished Jun 02 03:30:34 PM PDT 24
Peak memory 205668 kb
Host smart-a006c564-3f10-4f1c-926f-c7bdbc4f60b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29279
03683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.2927903683
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.2193644423
Short name T53
Test name
Test status
Simulation time 10159667497 ps
CPU time 13.1 seconds
Started Jun 02 03:30:20 PM PDT 24
Finished Jun 02 03:30:34 PM PDT 24
Peak memory 205716 kb
Host smart-142fc819-4a5a-417b-b994-2e28b81689ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21936
44423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.2193644423
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.3680861462
Short name T602
Test name
Test status
Simulation time 10050648611 ps
CPU time 15.74 seconds
Started Jun 02 03:30:23 PM PDT 24
Finished Jun 02 03:30:40 PM PDT 24
Peak memory 205652 kb
Host smart-9eac915b-8093-49fa-947a-50c6fd3dd02f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36808
61462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.3680861462
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.3792681222
Short name T1991
Test name
Test status
Simulation time 10052167489 ps
CPU time 13.43 seconds
Started Jun 02 03:30:21 PM PDT 24
Finished Jun 02 03:30:35 PM PDT 24
Peak memory 205672 kb
Host smart-4f550cc2-724b-4373-ad57-c0ffa25a0026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37926
81222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3792681222
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.2279036060
Short name T1728
Test name
Test status
Simulation time 10840991080 ps
CPU time 15.13 seconds
Started Jun 02 03:30:19 PM PDT 24
Finished Jun 02 03:30:35 PM PDT 24
Peak memory 205664 kb
Host smart-c11a7a34-208f-4a7d-acc5-5897cc27a7d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22790
36060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.2279036060
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.17857543
Short name T847
Test name
Test status
Simulation time 10135774190 ps
CPU time 14.49 seconds
Started Jun 02 03:30:17 PM PDT 24
Finished Jun 02 03:30:33 PM PDT 24
Peak memory 205744 kb
Host smart-13bb9657-1562-4414-adc0-e95312b2e931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17857
543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.17857543
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.3943587849
Short name T620
Test name
Test status
Simulation time 10166000127 ps
CPU time 13.61 seconds
Started Jun 02 03:30:24 PM PDT 24
Finished Jun 02 03:30:38 PM PDT 24
Peak memory 206004 kb
Host smart-bb1cb0bb-2c4c-4cf2-9da4-2a22a1d3c89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39435
87849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.3943587849
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.228328472
Short name T721
Test name
Test status
Simulation time 10045654600 ps
CPU time 16.08 seconds
Started Jun 02 03:30:29 PM PDT 24
Finished Jun 02 03:30:45 PM PDT 24
Peak memory 205800 kb
Host smart-11c8c366-6f43-4e3d-8396-0500a8e61327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22832
8472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.228328472
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.363104048
Short name T433
Test name
Test status
Simulation time 10137228397 ps
CPU time 14.28 seconds
Started Jun 02 03:30:22 PM PDT 24
Finished Jun 02 03:30:37 PM PDT 24
Peak memory 205712 kb
Host smart-fac9a2cf-551f-409c-873c-47d0b9f4d3ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36310
4048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.363104048
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.1609321455
Short name T471
Test name
Test status
Simulation time 10128653658 ps
CPU time 13.8 seconds
Started Jun 02 03:30:22 PM PDT 24
Finished Jun 02 03:30:37 PM PDT 24
Peak memory 205584 kb
Host smart-26275c0b-b16f-46f7-8f5a-c6cf8406b7fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16093
21455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.1609321455
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.3417189680
Short name T1779
Test name
Test status
Simulation time 13188558390 ps
CPU time 16.33 seconds
Started Jun 02 03:30:17 PM PDT 24
Finished Jun 02 03:30:34 PM PDT 24
Peak memory 205704 kb
Host smart-14440719-195a-4f1a-bfd9-c98a935ed114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34171
89680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.3417189680
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1924317517
Short name T814
Test name
Test status
Simulation time 10108847194 ps
CPU time 14.01 seconds
Started Jun 02 03:30:24 PM PDT 24
Finished Jun 02 03:30:39 PM PDT 24
Peak memory 205788 kb
Host smart-29feea50-ea2c-40bf-b09e-d57c32f2fd6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19243
17517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1924317517
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.447614253
Short name T1198
Test name
Test status
Simulation time 17079031830 ps
CPU time 61.16 seconds
Started Jun 02 03:30:21 PM PDT 24
Finished Jun 02 03:31:23 PM PDT 24
Peak memory 205676 kb
Host smart-c33f4fc9-2b55-4842-9d5a-588f07b5d0f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44761
4253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.447614253
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1663673633
Short name T971
Test name
Test status
Simulation time 10051791661 ps
CPU time 14.13 seconds
Started Jun 02 03:30:23 PM PDT 24
Finished Jun 02 03:30:38 PM PDT 24
Peak memory 205816 kb
Host smart-96ecd103-b99c-4043-9380-cad03dc1bd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16636
73633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1663673633
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.3200779726
Short name T102
Test name
Test status
Simulation time 10116155090 ps
CPU time 13.24 seconds
Started Jun 02 03:30:22 PM PDT 24
Finished Jun 02 03:30:36 PM PDT 24
Peak memory 205672 kb
Host smart-302d94fa-f424-489f-90f4-3a53a4b13c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32007
79726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.3200779726
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.2316893396
Short name T1531
Test name
Test status
Simulation time 10051909849 ps
CPU time 14.91 seconds
Started Jun 02 03:30:20 PM PDT 24
Finished Jun 02 03:30:35 PM PDT 24
Peak memory 205748 kb
Host smart-7ee51d3a-6cde-4bf8-9df1-669bca09638c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23168
93396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.2316893396
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3076834618
Short name T1885
Test name
Test status
Simulation time 10067268618 ps
CPU time 13.86 seconds
Started Jun 02 03:30:18 PM PDT 24
Finished Jun 02 03:30:33 PM PDT 24
Peak memory 205672 kb
Host smart-cbddf5de-e7d6-49fe-bd05-d08998e0e265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30768
34618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3076834618
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2581448541
Short name T1156
Test name
Test status
Simulation time 10067013189 ps
CPU time 16.34 seconds
Started Jun 02 03:30:27 PM PDT 24
Finished Jun 02 03:30:44 PM PDT 24
Peak memory 205652 kb
Host smart-b0cecb35-ebe3-49d6-b3ac-76e61f075ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25814
48541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2581448541
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.792405995
Short name T1627
Test name
Test status
Simulation time 10047570765 ps
CPU time 13.6 seconds
Started Jun 02 03:30:30 PM PDT 24
Finished Jun 02 03:30:44 PM PDT 24
Peak memory 205932 kb
Host smart-87c45312-ce00-4c63-8197-ab88ac1dd6b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79240
5995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.792405995
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_eop_single_bit_handling.2274547744
Short name T580
Test name
Test status
Simulation time 10086388747 ps
CPU time 14.98 seconds
Started Jun 02 03:30:30 PM PDT 24
Finished Jun 02 03:30:45 PM PDT 24
Peak memory 205636 kb
Host smart-bd858696-1e3b-46d8-907e-bef4fd486a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22745
47744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_eop_single_bit_handling.2274547744
Directory /workspace/28.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.2211154257
Short name T1783
Test name
Test status
Simulation time 10040333139 ps
CPU time 12.87 seconds
Started Jun 02 03:30:21 PM PDT 24
Finished Jun 02 03:30:35 PM PDT 24
Peak memory 205656 kb
Host smart-fbe90366-2a93-46e7-be6b-1f5d63ec3f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22111
54257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.2211154257
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2307355255
Short name T1440
Test name
Test status
Simulation time 10054599564 ps
CPU time 15.13 seconds
Started Jun 02 03:30:26 PM PDT 24
Finished Jun 02 03:30:42 PM PDT 24
Peak memory 205736 kb
Host smart-07bcaabc-a6b8-456a-b69a-4676fd77f604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23073
55255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2307355255
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.2598377546
Short name T160
Test name
Test status
Simulation time 22102261166 ps
CPU time 37.47 seconds
Started Jun 02 03:30:22 PM PDT 24
Finished Jun 02 03:31:01 PM PDT 24
Peak memory 205632 kb
Host smart-e476d745-269c-4e4c-b55b-7becf9c9eea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25983
77546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.2598377546
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.3336790141
Short name T1362
Test name
Test status
Simulation time 10062039334 ps
CPU time 15.64 seconds
Started Jun 02 03:30:22 PM PDT 24
Finished Jun 02 03:30:39 PM PDT 24
Peak memory 205716 kb
Host smart-aba993d6-c265-4a79-98bd-3124be5b5387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33367
90141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.3336790141
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2102480288
Short name T1447
Test name
Test status
Simulation time 10139049122 ps
CPU time 15.24 seconds
Started Jun 02 03:30:25 PM PDT 24
Finished Jun 02 03:30:42 PM PDT 24
Peak memory 205644 kb
Host smart-415f89d3-315d-4e57-8575-90d481243f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21024
80288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2102480288
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.1443438591
Short name T1498
Test name
Test status
Simulation time 10093349323 ps
CPU time 14.48 seconds
Started Jun 02 03:30:28 PM PDT 24
Finished Jun 02 03:30:43 PM PDT 24
Peak memory 205720 kb
Host smart-5da85fb0-2445-4392-8e27-be7a4d8cb25c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14434
38591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.1443438591
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.1061914713
Short name T391
Test name
Test status
Simulation time 10053820494 ps
CPU time 17.18 seconds
Started Jun 02 03:30:26 PM PDT 24
Finished Jun 02 03:30:44 PM PDT 24
Peak memory 205672 kb
Host smart-2ca4352c-f775-4056-b862-8484f3b64611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10619
14713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.1061914713
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2239527131
Short name T1302
Test name
Test status
Simulation time 10080356956 ps
CPU time 13.01 seconds
Started Jun 02 03:30:35 PM PDT 24
Finished Jun 02 03:30:49 PM PDT 24
Peak memory 205640 kb
Host smart-606d081e-67d0-4a74-92a7-eddfda0b7d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22395
27131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2239527131
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.2483510110
Short name T453
Test name
Test status
Simulation time 10098736370 ps
CPU time 14.01 seconds
Started Jun 02 03:30:25 PM PDT 24
Finished Jun 02 03:30:40 PM PDT 24
Peak memory 205648 kb
Host smart-a27b7a84-88b4-423e-9920-b1f06a605298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24835
10110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.2483510110
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.880371689
Short name T879
Test name
Test status
Simulation time 10135629944 ps
CPU time 13.78 seconds
Started Jun 02 03:30:25 PM PDT 24
Finished Jun 02 03:30:40 PM PDT 24
Peak memory 205680 kb
Host smart-d7a7825f-f306-4482-ae4b-d51a802bc563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88037
1689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.880371689
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.3005214
Short name T1499
Test name
Test status
Simulation time 10063532832 ps
CPU time 13.93 seconds
Started Jun 02 03:30:33 PM PDT 24
Finished Jun 02 03:30:48 PM PDT 24
Peak memory 205676 kb
Host smart-db6afb47-d290-44c8-980d-ceffa062f068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30052
14 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.3005214
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.4292224199
Short name T1473
Test name
Test status
Simulation time 10059499224 ps
CPU time 14.66 seconds
Started Jun 02 03:30:24 PM PDT 24
Finished Jun 02 03:30:40 PM PDT 24
Peak memory 205740 kb
Host smart-704d8f13-bb5d-436c-bb93-6031ee3652fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42922
24199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.4292224199
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.2335237293
Short name T1303
Test name
Test status
Simulation time 24458605559 ps
CPU time 433.19 seconds
Started Jun 02 03:30:23 PM PDT 24
Finished Jun 02 03:37:38 PM PDT 24
Peak memory 205664 kb
Host smart-a01bdf37-06c9-400f-b08c-19286dd7bdf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23352
37293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.2335237293
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.76130610
Short name T515
Test name
Test status
Simulation time 10163097905 ps
CPU time 16.85 seconds
Started Jun 02 03:30:39 PM PDT 24
Finished Jun 02 03:30:58 PM PDT 24
Peak memory 205616 kb
Host smart-ec614453-0538-4e93-a479-77ad0e7e4d8c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=76130610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.76130610
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.1532099283
Short name T1128
Test name
Test status
Simulation time 10090781335 ps
CPU time 15.58 seconds
Started Jun 02 03:30:36 PM PDT 24
Finished Jun 02 03:30:52 PM PDT 24
Peak memory 205764 kb
Host smart-6062e874-bf98-4267-8243-3a3eea63dcfa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1532099283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.1532099283
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.2114848719
Short name T946
Test name
Test status
Simulation time 10091598521 ps
CPU time 13.44 seconds
Started Jun 02 03:30:39 PM PDT 24
Finished Jun 02 03:30:55 PM PDT 24
Peak memory 205688 kb
Host smart-183a1b85-4be7-4aae-9cc3-7ea2186e1d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21148
48719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.2114848719
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.2258660997
Short name T517
Test name
Test status
Simulation time 13990262703 ps
CPU time 21.04 seconds
Started Jun 02 03:30:25 PM PDT 24
Finished Jun 02 03:30:47 PM PDT 24
Peak memory 205688 kb
Host smart-91020263-cb9e-48a8-9345-f43018f5bdb3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2258660997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.2258660997
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.1159240779
Short name T651
Test name
Test status
Simulation time 23232933864 ps
CPU time 29.13 seconds
Started Jun 02 03:30:23 PM PDT 24
Finished Jun 02 03:30:53 PM PDT 24
Peak memory 205704 kb
Host smart-ecd036c0-48ed-4f4e-9c23-407ed620bf9f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1159240779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.1159240779
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.447712427
Short name T1599
Test name
Test status
Simulation time 10075561327 ps
CPU time 13.81 seconds
Started Jun 02 03:30:23 PM PDT 24
Finished Jun 02 03:30:38 PM PDT 24
Peak memory 205748 kb
Host smart-debea15b-3f55-47b5-a126-5c123657d795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44771
2427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.447712427
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.3073082370
Short name T59
Test name
Test status
Simulation time 10116748436 ps
CPU time 16.77 seconds
Started Jun 02 03:30:25 PM PDT 24
Finished Jun 02 03:30:43 PM PDT 24
Peak memory 205692 kb
Host smart-63adce28-0f51-4ee8-b31e-dd07693762c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30730
82370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.3073082370
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.1562379104
Short name T1234
Test name
Test status
Simulation time 10785265408 ps
CPU time 16.66 seconds
Started Jun 02 03:30:27 PM PDT 24
Finished Jun 02 03:30:44 PM PDT 24
Peak memory 205660 kb
Host smart-09115b0b-7907-4526-8be8-384c1af299f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15623
79104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.1562379104
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.3549178799
Short name T1205
Test name
Test status
Simulation time 10045357545 ps
CPU time 13.04 seconds
Started Jun 02 03:30:33 PM PDT 24
Finished Jun 02 03:30:47 PM PDT 24
Peak memory 205676 kb
Host smart-e0d545f2-0c17-4043-a98f-5884987de495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35491
78799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.3549178799
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.1762816762
Short name T1382
Test name
Test status
Simulation time 10063899254 ps
CPU time 13.02 seconds
Started Jun 02 03:30:31 PM PDT 24
Finished Jun 02 03:30:44 PM PDT 24
Peak memory 205612 kb
Host smart-c63d7df8-073c-48d1-9025-2c46156b2681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17628
16762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.1762816762
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.4081897483
Short name T460
Test name
Test status
Simulation time 10702177329 ps
CPU time 13.72 seconds
Started Jun 02 03:30:33 PM PDT 24
Finished Jun 02 03:30:47 PM PDT 24
Peak memory 205656 kb
Host smart-400b6a4b-f317-4371-bd5c-d0d2234b316a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40818
97483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.4081897483
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.3695529318
Short name T1040
Test name
Test status
Simulation time 10215680547 ps
CPU time 14.95 seconds
Started Jun 02 03:30:27 PM PDT 24
Finished Jun 02 03:30:42 PM PDT 24
Peak memory 205660 kb
Host smart-fbc20095-484e-4a60-9da8-a96a33e5ec39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36955
29318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3695529318
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.1976652916
Short name T988
Test name
Test status
Simulation time 10130100762 ps
CPU time 15.12 seconds
Started Jun 02 03:30:32 PM PDT 24
Finished Jun 02 03:30:48 PM PDT 24
Peak memory 205656 kb
Host smart-71dedddf-451d-4138-b69a-bfbf399f40e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19766
52916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1976652916
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.40562042
Short name T1237
Test name
Test status
Simulation time 10040959351 ps
CPU time 13.13 seconds
Started Jun 02 03:30:39 PM PDT 24
Finished Jun 02 03:30:54 PM PDT 24
Peak memory 205628 kb
Host smart-ae7622cd-8a32-4580-995b-497ec975a5dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40562
042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.40562042
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.1428227205
Short name T418
Test name
Test status
Simulation time 10085887985 ps
CPU time 13.6 seconds
Started Jun 02 03:30:29 PM PDT 24
Finished Jun 02 03:30:43 PM PDT 24
Peak memory 205676 kb
Host smart-ab615768-b6ca-43db-976e-acd504a2a00a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14282
27205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.1428227205
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.3850994199
Short name T516
Test name
Test status
Simulation time 10150388883 ps
CPU time 14.37 seconds
Started Jun 02 03:30:36 PM PDT 24
Finished Jun 02 03:30:52 PM PDT 24
Peak memory 205444 kb
Host smart-c5b471f4-1b77-4025-8a9c-fc7e3e572c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38509
94199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.3850994199
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.1098376426
Short name T364
Test name
Test status
Simulation time 13170094420 ps
CPU time 19.65 seconds
Started Jun 02 03:30:33 PM PDT 24
Finished Jun 02 03:30:53 PM PDT 24
Peak memory 205792 kb
Host smart-9a0f76a3-14b3-441b-994f-cbcca9ae4641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10983
76426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.1098376426
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3192580246
Short name T990
Test name
Test status
Simulation time 10122896484 ps
CPU time 13.15 seconds
Started Jun 02 03:30:34 PM PDT 24
Finished Jun 02 03:30:48 PM PDT 24
Peak memory 205772 kb
Host smart-b901338b-b08d-47e9-8db3-70183ae2684e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31925
80246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3192580246
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.2776539297
Short name T1818
Test name
Test status
Simulation time 13954076215 ps
CPU time 39.97 seconds
Started Jun 02 03:30:33 PM PDT 24
Finished Jun 02 03:31:14 PM PDT 24
Peak memory 205652 kb
Host smart-74c31ad9-8ee2-4777-b043-8c89a90b5bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27765
39297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.2776539297
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.1926578207
Short name T1825
Test name
Test status
Simulation time 10080728139 ps
CPU time 13 seconds
Started Jun 02 03:30:35 PM PDT 24
Finished Jun 02 03:30:49 PM PDT 24
Peak memory 205648 kb
Host smart-4bf3f101-25b8-4f9c-b817-ca973fa1680b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19265
78207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.1926578207
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.1563691935
Short name T130
Test name
Test status
Simulation time 10218232442 ps
CPU time 14.99 seconds
Started Jun 02 03:30:32 PM PDT 24
Finished Jun 02 03:30:48 PM PDT 24
Peak memory 205760 kb
Host smart-e17e62d9-61e8-4118-9a04-0cb82acefa97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15636
91935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1563691935
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.1427083501
Short name T1243
Test name
Test status
Simulation time 10084582791 ps
CPU time 13.13 seconds
Started Jun 02 03:30:27 PM PDT 24
Finished Jun 02 03:30:41 PM PDT 24
Peak memory 205756 kb
Host smart-a594173c-a485-4bc7-90f0-95da907a75c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14270
83501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.1427083501
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2032226367
Short name T598
Test name
Test status
Simulation time 10046638697 ps
CPU time 16.81 seconds
Started Jun 02 03:30:34 PM PDT 24
Finished Jun 02 03:30:52 PM PDT 24
Peak memory 205780 kb
Host smart-6753de50-4713-4bf9-99e3-d6eddb823fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20322
26367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2032226367
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.2320436541
Short name T2013
Test name
Test status
Simulation time 10060136882 ps
CPU time 15.08 seconds
Started Jun 02 03:30:31 PM PDT 24
Finished Jun 02 03:30:47 PM PDT 24
Peak memory 205768 kb
Host smart-4a5e2612-bbe8-441e-a777-2f3cfdf4e4d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23204
36541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.2320436541
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.3198394509
Short name T1509
Test name
Test status
Simulation time 10092902475 ps
CPU time 13.04 seconds
Started Jun 02 03:30:30 PM PDT 24
Finished Jun 02 03:30:44 PM PDT 24
Peak memory 205556 kb
Host smart-5f9dc43b-64d9-4968-b809-7a090f68a8ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31983
94509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.3198394509
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_eop_single_bit_handling.879206334
Short name T941
Test name
Test status
Simulation time 10086514089 ps
CPU time 12.95 seconds
Started Jun 02 03:30:33 PM PDT 24
Finished Jun 02 03:30:47 PM PDT 24
Peak memory 205596 kb
Host smart-a2639737-164b-4e42-a49f-54ab995da2d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87920
6334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_eop_single_bit_handling.879206334
Directory /workspace/29.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.1280598334
Short name T194
Test name
Test status
Simulation time 10038049609 ps
CPU time 15.7 seconds
Started Jun 02 03:30:32 PM PDT 24
Finished Jun 02 03:30:48 PM PDT 24
Peak memory 205584 kb
Host smart-186dbc90-e09b-4ad8-a5dc-1c843d094078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12805
98334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.1280598334
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.1695465990
Short name T587
Test name
Test status
Simulation time 10077657989 ps
CPU time 16.48 seconds
Started Jun 02 03:30:32 PM PDT 24
Finished Jun 02 03:30:49 PM PDT 24
Peak memory 205748 kb
Host smart-57cf93e7-6171-4eb7-b0f8-9406728b08b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16954
65990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.1695465990
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2535501312
Short name T235
Test name
Test status
Simulation time 17416886384 ps
CPU time 35.05 seconds
Started Jun 02 03:30:27 PM PDT 24
Finished Jun 02 03:31:03 PM PDT 24
Peak memory 205664 kb
Host smart-c98656c0-8326-44b5-9be1-c0e3a867c8bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25355
01312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2535501312
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.724086408
Short name T468
Test name
Test status
Simulation time 10063330308 ps
CPU time 13.52 seconds
Started Jun 02 03:30:30 PM PDT 24
Finished Jun 02 03:30:44 PM PDT 24
Peak memory 205620 kb
Host smart-7787264b-ebb2-487f-a1d8-a91c4a929495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72408
6408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.724086408
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.3568076530
Short name T1117
Test name
Test status
Simulation time 10099092911 ps
CPU time 13.37 seconds
Started Jun 02 03:30:36 PM PDT 24
Finished Jun 02 03:30:51 PM PDT 24
Peak memory 205564 kb
Host smart-9afb2b3b-495c-4639-ac8b-e68f9067a50f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35680
76530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.3568076530
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.366291764
Short name T1810
Test name
Test status
Simulation time 10094822564 ps
CPU time 13.37 seconds
Started Jun 02 03:30:33 PM PDT 24
Finished Jun 02 03:30:48 PM PDT 24
Peak memory 205644 kb
Host smart-451b7af9-6214-4cd6-ae3e-39255443f345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36629
1764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.366291764
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.3331366243
Short name T1359
Test name
Test status
Simulation time 10048768358 ps
CPU time 13.41 seconds
Started Jun 02 03:30:33 PM PDT 24
Finished Jun 02 03:30:48 PM PDT 24
Peak memory 205560 kb
Host smart-eee841f9-aaea-4866-90ca-e2152a77aa76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33313
66243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.3331366243
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.3829292436
Short name T1527
Test name
Test status
Simulation time 10086824691 ps
CPU time 14.67 seconds
Started Jun 02 03:30:30 PM PDT 24
Finished Jun 02 03:30:45 PM PDT 24
Peak memory 205640 kb
Host smart-ceaca34f-9cde-4de1-b7ff-9b8875a09fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38292
92436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.3829292436
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3475858927
Short name T1132
Test name
Test status
Simulation time 10056516102 ps
CPU time 15.42 seconds
Started Jun 02 03:30:35 PM PDT 24
Finished Jun 02 03:30:51 PM PDT 24
Peak memory 205732 kb
Host smart-1f0ab0bb-0d51-4d02-94e5-77f70bfea5ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34758
58927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3475858927
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.379403074
Short name T618
Test name
Test status
Simulation time 10120289942 ps
CPU time 15.84 seconds
Started Jun 02 03:30:30 PM PDT 24
Finished Jun 02 03:30:46 PM PDT 24
Peak memory 205732 kb
Host smart-9465295d-0635-4b8d-8e9b-66109cc5aa70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37940
3074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.379403074
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.1900123017
Short name T1455
Test name
Test status
Simulation time 10065514311 ps
CPU time 16.05 seconds
Started Jun 02 03:30:34 PM PDT 24
Finished Jun 02 03:30:51 PM PDT 24
Peak memory 205660 kb
Host smart-3acea78b-5d27-468f-b9be-5d9726b399f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19001
23017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.1900123017
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.2887065596
Short name T1701
Test name
Test status
Simulation time 10052729227 ps
CPU time 13.12 seconds
Started Jun 02 03:30:36 PM PDT 24
Finished Jun 02 03:30:50 PM PDT 24
Peak memory 205636 kb
Host smart-c93010c1-0ab6-4752-abb7-7fc42b8426fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28870
65596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2887065596
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.2101073482
Short name T1550
Test name
Test status
Simulation time 23113021114 ps
CPU time 103.37 seconds
Started Jun 02 03:30:35 PM PDT 24
Finished Jun 02 03:32:19 PM PDT 24
Peak memory 205700 kb
Host smart-395ff9d9-21e0-4634-ac9c-253c6a417c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21010
73482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.2101073482
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.1032029089
Short name T465
Test name
Test status
Simulation time 10147023528 ps
CPU time 13.92 seconds
Started Jun 02 03:26:52 PM PDT 24
Finished Jun 02 03:27:06 PM PDT 24
Peak memory 205668 kb
Host smart-d006e6a1-db8d-4595-94d6-4b8728a2b9bf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1032029089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.1032029089
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.3827397292
Short name T488
Test name
Test status
Simulation time 10076283061 ps
CPU time 14.41 seconds
Started Jun 02 03:26:53 PM PDT 24
Finished Jun 02 03:27:08 PM PDT 24
Peak memory 205668 kb
Host smart-d988029c-2d80-430e-897b-5bcc9abb4545
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3827397292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.3827397292
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.3956286417
Short name T894
Test name
Test status
Simulation time 10090488198 ps
CPU time 13.25 seconds
Started Jun 02 03:26:52 PM PDT 24
Finished Jun 02 03:27:06 PM PDT 24
Peak memory 205736 kb
Host smart-c3d59b91-6607-44f0-a30b-817b945f0266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39562
86417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.3956286417
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.3035890951
Short name T826
Test name
Test status
Simulation time 14163135434 ps
CPU time 17.06 seconds
Started Jun 02 03:26:48 PM PDT 24
Finished Jun 02 03:27:05 PM PDT 24
Peak memory 205760 kb
Host smart-a59ce83c-9867-4b33-8754-310428f380be
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3035890951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.3035890951
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.1246095752
Short name T555
Test name
Test status
Simulation time 23277236753 ps
CPU time 24.86 seconds
Started Jun 02 03:26:46 PM PDT 24
Finished Jun 02 03:27:11 PM PDT 24
Peak memory 205696 kb
Host smart-8aa4dc57-2479-4b0f-b78f-851f79b7a716
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1246095752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.1246095752
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.2300637188
Short name T1590
Test name
Test status
Simulation time 10059044967 ps
CPU time 13.5 seconds
Started Jun 02 03:26:46 PM PDT 24
Finished Jun 02 03:27:00 PM PDT 24
Peak memory 205644 kb
Host smart-38aa9fc8-e2bd-4e1c-92e5-3afad556737b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23006
37188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.2300637188
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.1497888605
Short name T185
Test name
Test status
Simulation time 11113418716 ps
CPU time 17.22 seconds
Started Jun 02 03:26:47 PM PDT 24
Finished Jun 02 03:27:05 PM PDT 24
Peak memory 205700 kb
Host smart-6dbe0da4-234d-40cc-902e-3562179ecb3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14978
88605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.1497888605
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.2311770221
Short name T48
Test name
Test status
Simulation time 10039927365 ps
CPU time 13.23 seconds
Started Jun 02 03:26:49 PM PDT 24
Finished Jun 02 03:27:03 PM PDT 24
Peak memory 205684 kb
Host smart-1c48ffbf-d335-49c5-a2d8-1f0e78234fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23117
70221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.2311770221
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.3119621752
Short name T1836
Test name
Test status
Simulation time 10040611894 ps
CPU time 13.85 seconds
Started Jun 02 03:26:47 PM PDT 24
Finished Jun 02 03:27:01 PM PDT 24
Peak memory 205564 kb
Host smart-729a459c-45cb-46f4-8956-1de338d99aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31196
21752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.3119621752
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.2729097197
Short name T1963
Test name
Test status
Simulation time 10721886838 ps
CPU time 16.98 seconds
Started Jun 02 03:26:57 PM PDT 24
Finished Jun 02 03:27:14 PM PDT 24
Peak memory 205636 kb
Host smart-682c367e-a560-44e1-8d2b-01f5260634e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27290
97197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.2729097197
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.260159410
Short name T1504
Test name
Test status
Simulation time 10205807501 ps
CPU time 17.82 seconds
Started Jun 02 03:26:49 PM PDT 24
Finished Jun 02 03:27:07 PM PDT 24
Peak memory 205824 kb
Host smart-e1794749-5238-4ffe-9c17-f88013eec54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26015
9410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.260159410
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1497683438
Short name T334
Test name
Test status
Simulation time 10116088601 ps
CPU time 14.63 seconds
Started Jun 02 03:26:51 PM PDT 24
Finished Jun 02 03:27:06 PM PDT 24
Peak memory 205716 kb
Host smart-e7a1081c-5830-424f-8e8c-83e9c75c5c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14976
83438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1497683438
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.1555723408
Short name T1977
Test name
Test status
Simulation time 10054004162 ps
CPU time 15.38 seconds
Started Jun 02 03:26:54 PM PDT 24
Finished Jun 02 03:27:10 PM PDT 24
Peak memory 205692 kb
Host smart-381dd525-2435-4a37-b832-f06274cb8127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15557
23408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.1555723408
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.2369981011
Short name T403
Test name
Test status
Simulation time 10098979684 ps
CPU time 15 seconds
Started Jun 02 03:26:48 PM PDT 24
Finished Jun 02 03:27:04 PM PDT 24
Peak memory 205676 kb
Host smart-01f5178d-24bb-427b-af5b-658f52bd2c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23699
81011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.2369981011
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.3945807827
Short name T675
Test name
Test status
Simulation time 10172913052 ps
CPU time 14.1 seconds
Started Jun 02 03:26:50 PM PDT 24
Finished Jun 02 03:27:05 PM PDT 24
Peak memory 205704 kb
Host smart-14a2bb09-27ad-4df6-aef9-92b88462841b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39458
07827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.3945807827
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.2095655279
Short name T1719
Test name
Test status
Simulation time 13275613778 ps
CPU time 19.94 seconds
Started Jun 02 03:26:49 PM PDT 24
Finished Jun 02 03:27:09 PM PDT 24
Peak memory 205876 kb
Host smart-23079b3e-2d5a-4dfd-9780-98f1bbc6aadf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20956
55279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2095655279
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1520498614
Short name T753
Test name
Test status
Simulation time 10143872583 ps
CPU time 15.06 seconds
Started Jun 02 03:26:54 PM PDT 24
Finished Jun 02 03:27:09 PM PDT 24
Peak memory 205652 kb
Host smart-7948113f-c6ae-45b7-821d-78b6de2d64c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15204
98614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1520498614
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.1067867962
Short name T1331
Test name
Test status
Simulation time 19320365292 ps
CPU time 82.14 seconds
Started Jun 02 03:26:49 PM PDT 24
Finished Jun 02 03:28:12 PM PDT 24
Peak memory 205720 kb
Host smart-8b7764af-14ec-43e3-960c-7aa3ea353258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10678
67962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.1067867962
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2403082155
Short name T1521
Test name
Test status
Simulation time 10042442432 ps
CPU time 13.33 seconds
Started Jun 02 03:26:50 PM PDT 24
Finished Jun 02 03:27:04 PM PDT 24
Peak memory 205696 kb
Host smart-d55b1dd8-1b60-4f55-8934-cf5ae0a7c978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24030
82155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2403082155
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.885719506
Short name T1437
Test name
Test status
Simulation time 10066012514 ps
CPU time 13.29 seconds
Started Jun 02 03:26:49 PM PDT 24
Finished Jun 02 03:27:03 PM PDT 24
Peak memory 205788 kb
Host smart-a83f5e08-05d6-4d98-b9ac-1e443d912f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88571
9506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.885719506
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.28127462
Short name T1788
Test name
Test status
Simulation time 10090671878 ps
CPU time 14.47 seconds
Started Jun 02 03:26:47 PM PDT 24
Finished Jun 02 03:27:02 PM PDT 24
Peak memory 205680 kb
Host smart-e13cb4af-49cb-4657-afd5-f8bfa249839a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28127
462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.28127462
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.2053722359
Short name T690
Test name
Test status
Simulation time 10048030190 ps
CPU time 14.57 seconds
Started Jun 02 03:26:57 PM PDT 24
Finished Jun 02 03:27:12 PM PDT 24
Peak memory 205596 kb
Host smart-86f96b1f-f9c5-4c52-bdde-a9f048f08742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20537
22359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.2053722359
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.707754440
Short name T131
Test name
Test status
Simulation time 10063569796 ps
CPU time 15.21 seconds
Started Jun 02 03:26:51 PM PDT 24
Finished Jun 02 03:27:06 PM PDT 24
Peak memory 205776 kb
Host smart-38054088-8eb1-4df8-a675-ab7d4b44179f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70775
4440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.707754440
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_eop_single_bit_handling.2183021744
Short name T1996
Test name
Test status
Simulation time 10069438593 ps
CPU time 14.25 seconds
Started Jun 02 03:26:53 PM PDT 24
Finished Jun 02 03:27:07 PM PDT 24
Peak memory 205616 kb
Host smart-537ef4da-b8f7-426d-9ff1-b52a06631abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21830
21744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_eop_single_bit_handling.2183021744
Directory /workspace/3.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2318503576
Short name T1809
Test name
Test status
Simulation time 10075800102 ps
CPU time 15.45 seconds
Started Jun 02 03:26:51 PM PDT 24
Finished Jun 02 03:27:07 PM PDT 24
Peak memory 205744 kb
Host smart-e295012d-6419-4098-bc1e-bae7cc3b3710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23185
03576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2318503576
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1673645639
Short name T876
Test name
Test status
Simulation time 10039738291 ps
CPU time 14.45 seconds
Started Jun 02 03:26:52 PM PDT 24
Finished Jun 02 03:27:07 PM PDT 24
Peak memory 205708 kb
Host smart-ed849b83-35cf-449e-8828-365c4adde452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16736
45639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1673645639
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.245590271
Short name T1914
Test name
Test status
Simulation time 10068479861 ps
CPU time 14.74 seconds
Started Jun 02 03:26:49 PM PDT 24
Finished Jun 02 03:27:04 PM PDT 24
Peak memory 205792 kb
Host smart-1c2c9f49-ef05-4171-aec0-5dbab7b3ea2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24559
0271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.245590271
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2399112020
Short name T870
Test name
Test status
Simulation time 10128982981 ps
CPU time 14.04 seconds
Started Jun 02 03:26:47 PM PDT 24
Finished Jun 02 03:27:02 PM PDT 24
Peak memory 205716 kb
Host smart-1c21cb0b-7c5a-473e-b89a-2abe88237174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23991
12020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2399112020
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.2890685598
Short name T1700
Test name
Test status
Simulation time 27851651905 ps
CPU time 508.31 seconds
Started Jun 02 03:26:51 PM PDT 24
Finished Jun 02 03:35:20 PM PDT 24
Peak memory 205748 kb
Host smart-3ce655fa-c870-40ac-b87b-e3e4273c63a1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2890685598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.2890685598
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.732834036
Short name T1725
Test name
Test status
Simulation time 29143318232 ps
CPU time 139.58 seconds
Started Jun 02 03:26:56 PM PDT 24
Finished Jun 02 03:29:17 PM PDT 24
Peak memory 205740 kb
Host smart-13b20af4-fbe5-4d68-8d50-04673686068e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=732834036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.732834036
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.3057351704
Short name T1091
Test name
Test status
Simulation time 40837726954 ps
CPU time 796.05 seconds
Started Jun 02 03:26:52 PM PDT 24
Finished Jun 02 03:40:12 PM PDT 24
Peak memory 205792 kb
Host smart-9a194cf3-9308-40bf-a500-ba8d7480d943
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3057351704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.3057351704
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.3009744490
Short name T1046
Test name
Test status
Simulation time 10098956424 ps
CPU time 15.25 seconds
Started Jun 02 03:26:51 PM PDT 24
Finished Jun 02 03:27:07 PM PDT 24
Peak memory 205668 kb
Host smart-5b9bf857-b863-43ec-aba5-8c5469199aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30097
44490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.3009744490
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.2666603346
Short name T924
Test name
Test status
Simulation time 10057053779 ps
CPU time 16.71 seconds
Started Jun 02 03:26:50 PM PDT 24
Finished Jun 02 03:27:07 PM PDT 24
Peak memory 205628 kb
Host smart-cc486e96-5c29-4009-8502-c470329862a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26666
03346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.2666603346
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.1823163298
Short name T197
Test name
Test status
Simulation time 744096015 ps
CPU time 1.74 seconds
Started Jun 02 03:26:59 PM PDT 24
Finished Jun 02 03:27:01 PM PDT 24
Peak memory 222828 kb
Host smart-196794e3-a891-44ab-a639-71c41d5c11b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1823163298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1823163298
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.3164523854
Short name T1679
Test name
Test status
Simulation time 10064186300 ps
CPU time 16.7 seconds
Started Jun 02 03:26:52 PM PDT 24
Finished Jun 02 03:27:10 PM PDT 24
Peak memory 205728 kb
Host smart-97fe6f6c-5a99-4b2c-882b-eb121d6e8967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31645
23854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.3164523854
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.3923974061
Short name T2031
Test name
Test status
Simulation time 10064164235 ps
CPU time 14.72 seconds
Started Jun 02 03:26:50 PM PDT 24
Finished Jun 02 03:27:06 PM PDT 24
Peak memory 205760 kb
Host smart-d3356a64-de31-4530-9bca-cff825500d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39239
74061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.3923974061
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1934268300
Short name T682
Test name
Test status
Simulation time 10142014041 ps
CPU time 16.53 seconds
Started Jun 02 03:26:47 PM PDT 24
Finished Jun 02 03:27:04 PM PDT 24
Peak memory 205728 kb
Host smart-5c9ea52f-7d17-449b-92e4-60c806189897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19342
68300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1934268300
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.3772495651
Short name T897
Test name
Test status
Simulation time 10058019276 ps
CPU time 16.02 seconds
Started Jun 02 03:26:53 PM PDT 24
Finished Jun 02 03:27:10 PM PDT 24
Peak memory 205780 kb
Host smart-0f3d2b22-c921-46ca-a9fb-79b209d60dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37724
95651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.3772495651
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.3125204786
Short name T300
Test name
Test status
Simulation time 10095425697 ps
CPU time 13.31 seconds
Started Jun 02 03:26:48 PM PDT 24
Finished Jun 02 03:27:02 PM PDT 24
Peak memory 205768 kb
Host smart-fe1d56d1-6707-41a3-a4c5-2dc3e4ce61d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31252
04786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.3125204786
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.4214077544
Short name T333
Test name
Test status
Simulation time 22684226073 ps
CPU time 100.52 seconds
Started Jun 02 03:26:57 PM PDT 24
Finished Jun 02 03:28:38 PM PDT 24
Peak memory 205596 kb
Host smart-8e27dcb5-ab12-4d8c-88b4-32a4824db9b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42140
77544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.4214077544
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.285695027
Short name T493
Test name
Test status
Simulation time 19148866656 ps
CPU time 98.38 seconds
Started Jun 02 03:26:48 PM PDT 24
Finished Jun 02 03:28:27 PM PDT 24
Peak memory 205792 kb
Host smart-5c7d8254-f377-4bd3-a713-9c951ed7a38c
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285695027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bu
s_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_t
raffic.285695027
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.2926669594
Short name T1278
Test name
Test status
Simulation time 10209730483 ps
CPU time 13.29 seconds
Started Jun 02 03:30:46 PM PDT 24
Finished Jun 02 03:31:01 PM PDT 24
Peak memory 205784 kb
Host smart-16233e71-3617-4abf-8406-97d2f03e5705
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2926669594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.2926669594
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.2128574016
Short name T1123
Test name
Test status
Simulation time 10094343478 ps
CPU time 15.57 seconds
Started Jun 02 03:30:36 PM PDT 24
Finished Jun 02 03:30:53 PM PDT 24
Peak memory 205752 kb
Host smart-e416dd7b-86f9-4913-b095-f2e8218aefd3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2128574016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.2128574016
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.2052228434
Short name T394
Test name
Test status
Simulation time 10154491070 ps
CPU time 16.3 seconds
Started Jun 02 03:30:46 PM PDT 24
Finished Jun 02 03:31:04 PM PDT 24
Peak memory 205652 kb
Host smart-11b014a2-e392-45e1-a25c-eb74bf49f8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20522
28434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.2052228434
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.2023722664
Short name T1516
Test name
Test status
Simulation time 13389565664 ps
CPU time 21.04 seconds
Started Jun 02 03:30:37 PM PDT 24
Finished Jun 02 03:30:59 PM PDT 24
Peak memory 205636 kb
Host smart-34038dcc-5ea3-496a-9e1f-0f4292baf7f9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2023722664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.2023722664
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.730000183
Short name T8
Test name
Test status
Simulation time 23348977333 ps
CPU time 32.04 seconds
Started Jun 02 03:30:39 PM PDT 24
Finished Jun 02 03:31:13 PM PDT 24
Peak memory 205696 kb
Host smart-29c55d80-7033-4560-badc-5614603160a3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=730000183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.730000183
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.3968788475
Short name T1026
Test name
Test status
Simulation time 10068912547 ps
CPU time 13.16 seconds
Started Jun 02 03:30:32 PM PDT 24
Finished Jun 02 03:30:46 PM PDT 24
Peak memory 205668 kb
Host smart-4d6ea431-6f76-4ef1-8078-2b793e1c7d73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39687
88475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.3968788475
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.2028075640
Short name T1987
Test name
Test status
Simulation time 10392061995 ps
CPU time 14.33 seconds
Started Jun 02 03:30:38 PM PDT 24
Finished Jun 02 03:30:53 PM PDT 24
Peak memory 205796 kb
Host smart-93bc1237-048e-4b4c-9284-1365182b49d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20280
75640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.2028075640
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.1555351177
Short name T1268
Test name
Test status
Simulation time 10038775045 ps
CPU time 13.68 seconds
Started Jun 02 03:30:33 PM PDT 24
Finished Jun 02 03:30:48 PM PDT 24
Peak memory 205744 kb
Host smart-8b4b5e63-fe77-447f-933b-0151cf46114c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15553
51177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.1555351177
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.3916241959
Short name T1884
Test name
Test status
Simulation time 10062158620 ps
CPU time 14.09 seconds
Started Jun 02 03:30:31 PM PDT 24
Finished Jun 02 03:30:45 PM PDT 24
Peak memory 205768 kb
Host smart-757b6a7d-d88a-43eb-b02b-3df6af7607f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39162
41959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.3916241959
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.1438763496
Short name T582
Test name
Test status
Simulation time 10820103294 ps
CPU time 15.47 seconds
Started Jun 02 03:30:39 PM PDT 24
Finished Jun 02 03:30:57 PM PDT 24
Peak memory 205596 kb
Host smart-dc105982-a253-432f-be94-57591147486b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14387
63496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.1438763496
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.4272660067
Short name T903
Test name
Test status
Simulation time 10199419249 ps
CPU time 15.83 seconds
Started Jun 02 03:30:38 PM PDT 24
Finished Jun 02 03:30:55 PM PDT 24
Peak memory 205668 kb
Host smart-f27b1953-4d0c-4ff0-9872-27e1d68be7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42726
60067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.4272660067
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.1768258189
Short name T959
Test name
Test status
Simulation time 10190076255 ps
CPU time 13.05 seconds
Started Jun 02 03:30:36 PM PDT 24
Finished Jun 02 03:30:51 PM PDT 24
Peak memory 205788 kb
Host smart-6c82dd67-2949-4e4c-83c4-2970ecf44f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17682
58189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.1768258189
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.138414009
Short name T1167
Test name
Test status
Simulation time 10041978365 ps
CPU time 14.31 seconds
Started Jun 02 03:30:39 PM PDT 24
Finished Jun 02 03:30:55 PM PDT 24
Peak memory 205600 kb
Host smart-5c094c24-51b9-4ef0-94b0-c93c39aebaf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13841
4009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.138414009
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1744139639
Short name T1898
Test name
Test status
Simulation time 10111622248 ps
CPU time 16.05 seconds
Started Jun 02 03:30:37 PM PDT 24
Finished Jun 02 03:30:54 PM PDT 24
Peak memory 205676 kb
Host smart-fd7b6422-9007-4cf2-8480-aba521f0c643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17441
39639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1744139639
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.2476581484
Short name T1099
Test name
Test status
Simulation time 10145159501 ps
CPU time 13.42 seconds
Started Jun 02 03:30:39 PM PDT 24
Finished Jun 02 03:30:54 PM PDT 24
Peak memory 205624 kb
Host smart-ff0cc9f2-e662-4624-a4ce-33dd23b1e65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24765
81484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.2476581484
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.2677500505
Short name T1108
Test name
Test status
Simulation time 13213216314 ps
CPU time 16.75 seconds
Started Jun 02 03:30:33 PM PDT 24
Finished Jun 02 03:30:51 PM PDT 24
Peak memory 205680 kb
Host smart-f56776c3-80ef-4015-ae7a-435ef2bce957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26775
00505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.2677500505
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.24421767
Short name T1930
Test name
Test status
Simulation time 10100971295 ps
CPU time 12.9 seconds
Started Jun 02 03:30:39 PM PDT 24
Finished Jun 02 03:30:53 PM PDT 24
Peak memory 205624 kb
Host smart-649390ed-59ee-427e-8f3e-1d8802c04d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24421
767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.24421767
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.3280636168
Short name T1604
Test name
Test status
Simulation time 18263817579 ps
CPU time 74.01 seconds
Started Jun 02 03:30:35 PM PDT 24
Finished Jun 02 03:31:50 PM PDT 24
Peak memory 205640 kb
Host smart-e376719a-2979-4cfa-9a37-a1580f6b8667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32806
36168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.3280636168
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.3169425651
Short name T622
Test name
Test status
Simulation time 10039836607 ps
CPU time 13.32 seconds
Started Jun 02 03:30:39 PM PDT 24
Finished Jun 02 03:30:54 PM PDT 24
Peak memory 205644 kb
Host smart-a93b81e8-20e5-4202-9ed4-99b61bc3d289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31694
25651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.3169425651
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2547866578
Short name T115
Test name
Test status
Simulation time 10133519536 ps
CPU time 14.17 seconds
Started Jun 02 03:30:39 PM PDT 24
Finished Jun 02 03:30:55 PM PDT 24
Peak memory 205684 kb
Host smart-8064f036-9204-497d-8cc2-db3607dad6b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25478
66578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2547866578
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3452390457
Short name T1282
Test name
Test status
Simulation time 10057204108 ps
CPU time 13.05 seconds
Started Jun 02 03:30:39 PM PDT 24
Finished Jun 02 03:30:54 PM PDT 24
Peak memory 205672 kb
Host smart-72de118f-cc7c-4ebd-8eca-75986f784d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34523
90457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3452390457
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.493036932
Short name T1044
Test name
Test status
Simulation time 10072557773 ps
CPU time 12.69 seconds
Started Jun 02 03:30:39 PM PDT 24
Finished Jun 02 03:30:54 PM PDT 24
Peak memory 205716 kb
Host smart-967379d2-815a-4246-b1ae-04fafe89de3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49303
6932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.493036932
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.3003598720
Short name T1849
Test name
Test status
Simulation time 10073473056 ps
CPU time 12.69 seconds
Started Jun 02 03:30:39 PM PDT 24
Finished Jun 02 03:30:53 PM PDT 24
Peak memory 205716 kb
Host smart-834008d1-8a33-422e-be25-904bf3360b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30035
98720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3003598720
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.2496138911
Short name T852
Test name
Test status
Simulation time 10118457214 ps
CPU time 16.38 seconds
Started Jun 02 03:30:39 PM PDT 24
Finished Jun 02 03:30:57 PM PDT 24
Peak memory 205636 kb
Host smart-9c6f8079-d05e-4d77-95cf-ba57f570f2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24961
38911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.2496138911
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_eop_single_bit_handling.3074420510
Short name T949
Test name
Test status
Simulation time 10078928430 ps
CPU time 13.37 seconds
Started Jun 02 03:30:39 PM PDT 24
Finished Jun 02 03:30:54 PM PDT 24
Peak memory 205660 kb
Host smart-dba97d90-87c6-44a5-a828-80427dc21a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30744
20510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_eop_single_bit_handling.3074420510
Directory /workspace/30.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.2443144967
Short name T857
Test name
Test status
Simulation time 10065742577 ps
CPU time 12.98 seconds
Started Jun 02 03:30:39 PM PDT 24
Finished Jun 02 03:30:54 PM PDT 24
Peak memory 205708 kb
Host smart-6cbd7ce3-5535-442d-a824-6da6eb4b53b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24431
44967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.2443144967
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1057352763
Short name T27
Test name
Test status
Simulation time 10065485099 ps
CPU time 13.91 seconds
Started Jun 02 03:30:39 PM PDT 24
Finished Jun 02 03:30:54 PM PDT 24
Peak memory 205660 kb
Host smart-0d05f45b-177e-4e06-aa8a-3d6a535af081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10573
52763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1057352763
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.1117817483
Short name T1882
Test name
Test status
Simulation time 31427588217 ps
CPU time 59.05 seconds
Started Jun 02 03:30:37 PM PDT 24
Finished Jun 02 03:31:37 PM PDT 24
Peak memory 205656 kb
Host smart-90c54aa3-eda8-47fe-86eb-e7e334b38801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11178
17483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.1117817483
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1274881754
Short name T408
Test name
Test status
Simulation time 10116512981 ps
CPU time 16 seconds
Started Jun 02 03:30:39 PM PDT 24
Finished Jun 02 03:30:57 PM PDT 24
Peak memory 205564 kb
Host smart-30749802-dbcf-48d6-8275-7e7bcd5e01af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12748
81754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1274881754
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.82662238
Short name T985
Test name
Test status
Simulation time 10089115384 ps
CPU time 12.21 seconds
Started Jun 02 03:30:32 PM PDT 24
Finished Jun 02 03:30:45 PM PDT 24
Peak memory 205792 kb
Host smart-264d9952-2043-4bcd-901f-e89c101796da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82662
238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.82662238
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.1867620290
Short name T624
Test name
Test status
Simulation time 10080230345 ps
CPU time 13.45 seconds
Started Jun 02 03:30:33 PM PDT 24
Finished Jun 02 03:30:47 PM PDT 24
Peak memory 205688 kb
Host smart-2fb2764e-a462-4a5e-821c-e64fdcc8d86c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18676
20290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.1867620290
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.2797805340
Short name T1926
Test name
Test status
Simulation time 10084252354 ps
CPU time 13.06 seconds
Started Jun 02 03:30:36 PM PDT 24
Finished Jun 02 03:30:50 PM PDT 24
Peak memory 205680 kb
Host smart-d6618b44-0ef3-4796-8ddd-037f6fafe071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27978
05340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.2797805340
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.4078449662
Short name T1807
Test name
Test status
Simulation time 10066352120 ps
CPU time 15.12 seconds
Started Jun 02 03:30:36 PM PDT 24
Finished Jun 02 03:30:52 PM PDT 24
Peak memory 205764 kb
Host smart-1320f9d6-1b0f-4fa0-8fab-878f99981689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40784
49662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.4078449662
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.407202879
Short name T698
Test name
Test status
Simulation time 10101550551 ps
CPU time 14.67 seconds
Started Jun 02 03:30:38 PM PDT 24
Finished Jun 02 03:30:54 PM PDT 24
Peak memory 205776 kb
Host smart-2fa4876a-e5de-4eeb-afc1-f5a110595e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40720
2879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.407202879
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.194097536
Short name T1264
Test name
Test status
Simulation time 10123351353 ps
CPU time 15.14 seconds
Started Jun 02 03:30:43 PM PDT 24
Finished Jun 02 03:31:00 PM PDT 24
Peak memory 205712 kb
Host smart-103b79c2-b20d-4f7b-96bd-7ca26d131a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19409
7536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.194097536
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.2033627348
Short name T496
Test name
Test status
Simulation time 10095007196 ps
CPU time 13.09 seconds
Started Jun 02 03:30:45 PM PDT 24
Finished Jun 02 03:30:59 PM PDT 24
Peak memory 205788 kb
Host smart-f40ff2e5-7917-487b-8ad5-19a853ffcf72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20336
27348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.2033627348
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.2710662586
Short name T1952
Test name
Test status
Simulation time 10078010503 ps
CPU time 15.64 seconds
Started Jun 02 03:30:39 PM PDT 24
Finished Jun 02 03:30:55 PM PDT 24
Peak memory 205472 kb
Host smart-53918cdc-4ed9-467d-b031-ce8f9500c1b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27106
62586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.2710662586
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.634824364
Short name T1361
Test name
Test status
Simulation time 20839849129 ps
CPU time 89.21 seconds
Started Jun 02 03:30:37 PM PDT 24
Finished Jun 02 03:32:07 PM PDT 24
Peak memory 205644 kb
Host smart-2ab699fd-4983-4d0b-a1dc-65f605869604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63482
4364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.634824364
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.97835682
Short name T579
Test name
Test status
Simulation time 10133665467 ps
CPU time 15.11 seconds
Started Jun 02 03:30:49 PM PDT 24
Finished Jun 02 03:31:05 PM PDT 24
Peak memory 205704 kb
Host smart-02838cca-f534-42ad-aea8-25827dc276d7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=97835682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.97835682
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.3360510720
Short name T935
Test name
Test status
Simulation time 10077469486 ps
CPU time 12.98 seconds
Started Jun 02 03:30:46 PM PDT 24
Finished Jun 02 03:31:00 PM PDT 24
Peak memory 205736 kb
Host smart-fab6ec2e-feff-46fe-bcf2-0a6965f3fd13
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3360510720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.3360510720
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.4099614016
Short name T1254
Test name
Test status
Simulation time 10102583254 ps
CPU time 16.59 seconds
Started Jun 02 03:30:46 PM PDT 24
Finished Jun 02 03:31:04 PM PDT 24
Peak memory 205700 kb
Host smart-6b082e02-98bc-42c7-a6fe-603de0c6cc6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40996
14016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.4099614016
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.2437230169
Short name T10
Test name
Test status
Simulation time 14140047651 ps
CPU time 21.42 seconds
Started Jun 02 03:30:39 PM PDT 24
Finished Jun 02 03:31:01 PM PDT 24
Peak memory 205588 kb
Host smart-17f79f6a-e666-4385-a514-01f8e832e8f1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2437230169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.2437230169
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.1463082617
Short name T699
Test name
Test status
Simulation time 23310246588 ps
CPU time 27.17 seconds
Started Jun 02 03:30:35 PM PDT 24
Finished Jun 02 03:31:03 PM PDT 24
Peak memory 205680 kb
Host smart-148c9899-ccfa-41a5-86ae-b9ecba904955
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1463082617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.1463082617
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.3648378548
Short name T1663
Test name
Test status
Simulation time 10051833786 ps
CPU time 13.29 seconds
Started Jun 02 03:30:37 PM PDT 24
Finished Jun 02 03:30:51 PM PDT 24
Peak memory 205700 kb
Host smart-96b27fe1-7a8e-48ce-a455-fd11e05b4321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36483
78548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.3648378548
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.2652928724
Short name T1127
Test name
Test status
Simulation time 11295759701 ps
CPU time 16.01 seconds
Started Jun 02 03:30:36 PM PDT 24
Finished Jun 02 03:30:53 PM PDT 24
Peak memory 205644 kb
Host smart-89264ad3-a027-4c66-ada3-422168dbab5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26529
28724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.2652928724
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.3554097897
Short name T1277
Test name
Test status
Simulation time 10040570673 ps
CPU time 13.68 seconds
Started Jun 02 03:30:42 PM PDT 24
Finished Jun 02 03:30:56 PM PDT 24
Peak memory 205704 kb
Host smart-ba343ddf-68d5-4db5-b319-2cc701fca862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35540
97897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.3554097897
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.1470280138
Short name T640
Test name
Test status
Simulation time 10056134150 ps
CPU time 13.33 seconds
Started Jun 02 03:30:36 PM PDT 24
Finished Jun 02 03:30:51 PM PDT 24
Peak memory 205612 kb
Host smart-f0c895ba-5928-478b-8375-9cd1cd5cec20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14702
80138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.1470280138
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.779857478
Short name T29
Test name
Test status
Simulation time 10682294794 ps
CPU time 14.91 seconds
Started Jun 02 03:30:46 PM PDT 24
Finished Jun 02 03:31:02 PM PDT 24
Peak memory 205692 kb
Host smart-a1049b61-6158-4b1d-b1da-92c1581b8a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77985
7478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.779857478
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.620784291
Short name T1677
Test name
Test status
Simulation time 10252888776 ps
CPU time 14.64 seconds
Started Jun 02 03:30:40 PM PDT 24
Finished Jun 02 03:30:56 PM PDT 24
Peak memory 205720 kb
Host smart-f420a539-9ab1-4f8c-8e4d-d4aea376dfb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62078
4291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.620784291
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.3998005571
Short name T859
Test name
Test status
Simulation time 10053448031 ps
CPU time 13.47 seconds
Started Jun 02 03:30:48 PM PDT 24
Finished Jun 02 03:31:03 PM PDT 24
Peak memory 205732 kb
Host smart-2e0c2286-3dbd-4ae7-b78f-da8c54c8567c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39980
05571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.3998005571
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.1570119370
Short name T86
Test name
Test status
Simulation time 10070065807 ps
CPU time 14.43 seconds
Started Jun 02 03:30:53 PM PDT 24
Finished Jun 02 03:31:09 PM PDT 24
Peak memory 205680 kb
Host smart-179a3d96-5e1f-4d0e-ae0e-b75b9442909d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15701
19370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.1570119370
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.369487706
Short name T1781
Test name
Test status
Simulation time 10115898129 ps
CPU time 13.24 seconds
Started Jun 02 03:30:46 PM PDT 24
Finished Jun 02 03:31:01 PM PDT 24
Peak memory 205704 kb
Host smart-5fc9e7b5-9a85-491e-85d7-2d1485d4e07b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36948
7706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.369487706
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.3937159058
Short name T1248
Test name
Test status
Simulation time 10122457637 ps
CPU time 12.94 seconds
Started Jun 02 03:30:42 PM PDT 24
Finished Jun 02 03:30:57 PM PDT 24
Peak memory 205716 kb
Host smart-0fbe1981-bf08-4c58-831b-7e52f3f633d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39371
59058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.3937159058
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.2517131080
Short name T2019
Test name
Test status
Simulation time 13188021631 ps
CPU time 16.18 seconds
Started Jun 02 03:30:42 PM PDT 24
Finished Jun 02 03:31:00 PM PDT 24
Peak memory 205624 kb
Host smart-808391e2-7261-49a5-b40d-88a71086755d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25171
31080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2517131080
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.2544667158
Short name T704
Test name
Test status
Simulation time 10085663877 ps
CPU time 13.12 seconds
Started Jun 02 03:30:43 PM PDT 24
Finished Jun 02 03:30:58 PM PDT 24
Peak memory 205584 kb
Host smart-b9403366-17e8-4a0b-8dc8-228c3c45c072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25446
67158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.2544667158
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.4227295085
Short name T1300
Test name
Test status
Simulation time 24403737776 ps
CPU time 455.35 seconds
Started Jun 02 03:30:42 PM PDT 24
Finished Jun 02 03:38:19 PM PDT 24
Peak memory 205704 kb
Host smart-80f14f76-6234-4e74-aa7c-8a2492f83197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42272
95085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.4227295085
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.156084718
Short name T503
Test name
Test status
Simulation time 10052184788 ps
CPU time 14.13 seconds
Started Jun 02 03:30:43 PM PDT 24
Finished Jun 02 03:30:59 PM PDT 24
Peak memory 205716 kb
Host smart-3d86d0b5-d58a-4dfa-9e69-2a094b62ba64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15608
4718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.156084718
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.3354717010
Short name T1692
Test name
Test status
Simulation time 10095424130 ps
CPU time 12.41 seconds
Started Jun 02 03:30:44 PM PDT 24
Finished Jun 02 03:30:58 PM PDT 24
Peak memory 205708 kb
Host smart-69bc99d6-3cc3-46d1-9adf-115b5dec9ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33547
17010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.3354717010
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.1186564603
Short name T612
Test name
Test status
Simulation time 10089336240 ps
CPU time 13.24 seconds
Started Jun 02 03:30:45 PM PDT 24
Finished Jun 02 03:30:59 PM PDT 24
Peak memory 205688 kb
Host smart-9d054efd-78de-46a1-8afb-fe736e23c10d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11865
64603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.1186564603
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1128198278
Short name T1190
Test name
Test status
Simulation time 10068736072 ps
CPU time 14.54 seconds
Started Jun 02 03:30:46 PM PDT 24
Finished Jun 02 03:31:02 PM PDT 24
Peak memory 205656 kb
Host smart-86c37cf5-1ef2-413c-a8ee-ad59e1febf4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11281
98278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1128198278
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.3235615935
Short name T534
Test name
Test status
Simulation time 10110359435 ps
CPU time 13.63 seconds
Started Jun 02 03:30:47 PM PDT 24
Finished Jun 02 03:31:01 PM PDT 24
Peak memory 205764 kb
Host smart-f2e340d6-3617-41da-9fab-24e7f5d8d146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32356
15935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.3235615935
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.364177590
Short name T1973
Test name
Test status
Simulation time 10070922345 ps
CPU time 13.98 seconds
Started Jun 02 03:30:48 PM PDT 24
Finished Jun 02 03:31:03 PM PDT 24
Peak memory 205628 kb
Host smart-824249ab-fdfe-4e34-b077-c22bb581eaba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36417
7590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.364177590
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_eop_single_bit_handling.4145764242
Short name T313
Test name
Test status
Simulation time 10058884162 ps
CPU time 12.77 seconds
Started Jun 02 03:30:53 PM PDT 24
Finished Jun 02 03:31:07 PM PDT 24
Peak memory 205640 kb
Host smart-51cb95e5-9bbb-42ed-aeb7-ccb00ffdb7b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41457
64242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_eop_single_bit_handling.4145764242
Directory /workspace/31.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.2538274558
Short name T885
Test name
Test status
Simulation time 10110980118 ps
CPU time 16.12 seconds
Started Jun 02 03:30:48 PM PDT 24
Finished Jun 02 03:31:05 PM PDT 24
Peak memory 205580 kb
Host smart-209c2f7a-b81b-44f2-9f9c-15c4f20104b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25382
74558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.2538274558
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.127831588
Short name T184
Test name
Test status
Simulation time 20345584381 ps
CPU time 39.48 seconds
Started Jun 02 03:30:44 PM PDT 24
Finished Jun 02 03:31:25 PM PDT 24
Peak memory 205656 kb
Host smart-fe925b34-6c27-4671-b503-25b33cfe3cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12783
1588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.127831588
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.984720770
Short name T1718
Test name
Test status
Simulation time 10130479685 ps
CPU time 15.33 seconds
Started Jun 02 03:30:42 PM PDT 24
Finished Jun 02 03:30:59 PM PDT 24
Peak memory 205764 kb
Host smart-c0a59f5b-e81c-4815-897e-c68f4f7dc356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98472
0770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.984720770
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2034534652
Short name T489
Test name
Test status
Simulation time 10144137260 ps
CPU time 13.51 seconds
Started Jun 02 03:30:42 PM PDT 24
Finished Jun 02 03:30:57 PM PDT 24
Peak memory 205704 kb
Host smart-a6c99cbb-02b7-40ff-8348-9a03ea23584f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20345
34652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2034534652
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.2812632040
Short name T1379
Test name
Test status
Simulation time 10123392448 ps
CPU time 14.86 seconds
Started Jun 02 03:30:40 PM PDT 24
Finished Jun 02 03:30:56 PM PDT 24
Peak memory 205652 kb
Host smart-a6f8b49e-1fdc-4a42-a810-745d6e0c088c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28126
32040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.2812632040
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.3243926372
Short name T481
Test name
Test status
Simulation time 10070658348 ps
CPU time 12.8 seconds
Started Jun 02 03:30:41 PM PDT 24
Finished Jun 02 03:30:55 PM PDT 24
Peak memory 205616 kb
Host smart-e2919773-8026-455d-b8ed-3bfdc1efd44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32439
26372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.3243926372
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.952767351
Short name T438
Test name
Test status
Simulation time 10085869564 ps
CPU time 14.39 seconds
Started Jun 02 03:30:52 PM PDT 24
Finished Jun 02 03:31:07 PM PDT 24
Peak memory 205756 kb
Host smart-aa35f09f-ff34-431c-aa76-083026db6996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95276
7351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.952767351
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.577784105
Short name T1526
Test name
Test status
Simulation time 10066940550 ps
CPU time 13.65 seconds
Started Jun 02 03:30:57 PM PDT 24
Finished Jun 02 03:31:11 PM PDT 24
Peak memory 205660 kb
Host smart-e89dad73-ec87-4b75-b5d2-c1f6258a1728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57778
4105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.577784105
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.1364824390
Short name T1232
Test name
Test status
Simulation time 10132323768 ps
CPU time 15.23 seconds
Started Jun 02 03:30:37 PM PDT 24
Finished Jun 02 03:30:54 PM PDT 24
Peak memory 205768 kb
Host smart-03eabd5c-0594-4ded-8f89-3d6bc75e15ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13648
24390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.1364824390
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.2004025854
Short name T630
Test name
Test status
Simulation time 10113379677 ps
CPU time 15.54 seconds
Started Jun 02 03:30:48 PM PDT 24
Finished Jun 02 03:31:04 PM PDT 24
Peak memory 205644 kb
Host smart-7b2caf13-d3fd-41fb-a566-49495bc2ba0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20040
25854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.2004025854
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.3892016177
Short name T952
Test name
Test status
Simulation time 10116794258 ps
CPU time 15.49 seconds
Started Jun 02 03:30:43 PM PDT 24
Finished Jun 02 03:31:00 PM PDT 24
Peak memory 205664 kb
Host smart-5065c210-61a7-4f1e-8f85-930a8053ba40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38920
16177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.3892016177
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.3755628247
Short name T664
Test name
Test status
Simulation time 20280018840 ps
CPU time 110.67 seconds
Started Jun 02 03:30:41 PM PDT 24
Finished Jun 02 03:32:33 PM PDT 24
Peak memory 205696 kb
Host smart-0a7c9af4-e190-4b4e-9e61-9aabfc6ee48a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37556
28247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.3755628247
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.3729878688
Short name T409
Test name
Test status
Simulation time 10145016772 ps
CPU time 15.99 seconds
Started Jun 02 03:30:59 PM PDT 24
Finished Jun 02 03:31:16 PM PDT 24
Peak memory 205804 kb
Host smart-5c404b8e-7719-4352-a2a1-de9e3d431329
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3729878688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.3729878688
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.613123654
Short name T1541
Test name
Test status
Simulation time 10119905081 ps
CPU time 15.58 seconds
Started Jun 02 03:30:53 PM PDT 24
Finished Jun 02 03:31:10 PM PDT 24
Peak memory 205656 kb
Host smart-44fa95ae-533a-4dc8-a493-85d860c45f08
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=613123654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.613123654
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.4254758239
Short name T1975
Test name
Test status
Simulation time 10101744337 ps
CPU time 14 seconds
Started Jun 02 03:30:53 PM PDT 24
Finished Jun 02 03:31:09 PM PDT 24
Peak memory 205668 kb
Host smart-4dbbcb90-885d-43e2-bde5-25cf44391c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42547
58239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.4254758239
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.2629960994
Short name T1081
Test name
Test status
Simulation time 14036747249 ps
CPU time 18.11 seconds
Started Jun 02 03:30:57 PM PDT 24
Finished Jun 02 03:31:16 PM PDT 24
Peak memory 205680 kb
Host smart-b3693d91-702d-433f-ab0a-432c9b4440d8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2629960994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.2629960994
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3310064740
Short name T1109
Test name
Test status
Simulation time 23255221016 ps
CPU time 24.3 seconds
Started Jun 02 03:30:49 PM PDT 24
Finished Jun 02 03:31:14 PM PDT 24
Peak memory 205740 kb
Host smart-0841621a-affc-46f7-ac9e-f44bb678eb33
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3310064740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3310064740
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.122994012
Short name T385
Test name
Test status
Simulation time 10066536635 ps
CPU time 13.13 seconds
Started Jun 02 03:30:47 PM PDT 24
Finished Jun 02 03:31:02 PM PDT 24
Peak memory 205764 kb
Host smart-3cb05caf-6fb3-48a1-b739-e98d74c06cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12299
4012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.122994012
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.3225222080
Short name T776
Test name
Test status
Simulation time 10046902156 ps
CPU time 16.77 seconds
Started Jun 02 03:30:53 PM PDT 24
Finished Jun 02 03:31:11 PM PDT 24
Peak memory 205740 kb
Host smart-7416d60f-8d9a-4e7d-b18f-3da641ff2906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32252
22080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.3225222080
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.358229432
Short name T1439
Test name
Test status
Simulation time 10964479874 ps
CPU time 15.93 seconds
Started Jun 02 03:30:48 PM PDT 24
Finished Jun 02 03:31:05 PM PDT 24
Peak memory 205416 kb
Host smart-9d855c52-51c9-4aac-ae17-f0ba349b3937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35822
9432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.358229432
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.1196367562
Short name T1446
Test name
Test status
Simulation time 10060873649 ps
CPU time 15.78 seconds
Started Jun 02 03:30:45 PM PDT 24
Finished Jun 02 03:31:02 PM PDT 24
Peak memory 205760 kb
Host smart-5fa0aef9-2ab2-4ab0-8a3e-803223394d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11963
67562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.1196367562
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2089978471
Short name T376
Test name
Test status
Simulation time 10055547393 ps
CPU time 13.09 seconds
Started Jun 02 03:30:51 PM PDT 24
Finished Jun 02 03:31:05 PM PDT 24
Peak memory 205752 kb
Host smart-4d4ba4ff-7802-417d-9cfc-78c91c4be719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20899
78471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2089978471
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.3386884028
Short name T1129
Test name
Test status
Simulation time 10901917654 ps
CPU time 14.94 seconds
Started Jun 02 03:30:47 PM PDT 24
Finished Jun 02 03:31:04 PM PDT 24
Peak memory 205768 kb
Host smart-4f1eeef2-2d78-4cf1-b135-64289b7a35f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33868
84028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.3386884028
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3901147410
Short name T1852
Test name
Test status
Simulation time 10092504579 ps
CPU time 15.95 seconds
Started Jun 02 03:30:46 PM PDT 24
Finished Jun 02 03:31:03 PM PDT 24
Peak memory 205652 kb
Host smart-5493411c-b334-4714-9464-222616819ccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39011
47410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3901147410
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.3750575232
Short name T1726
Test name
Test status
Simulation time 10100454342 ps
CPU time 13.76 seconds
Started Jun 02 03:30:56 PM PDT 24
Finished Jun 02 03:31:10 PM PDT 24
Peak memory 205660 kb
Host smart-7b3e63f0-7818-4f20-ace4-32fc88f8fcb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37505
75232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.3750575232
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3314848221
Short name T1773
Test name
Test status
Simulation time 10058444928 ps
CPU time 14.26 seconds
Started Jun 02 03:30:56 PM PDT 24
Finished Jun 02 03:31:11 PM PDT 24
Peak memory 205584 kb
Host smart-9812ce2e-b21b-4f34-8f4e-da8c7878b14b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33148
48221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3314848221
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.826886334
Short name T1791
Test name
Test status
Simulation time 10052298176 ps
CPU time 14.1 seconds
Started Jun 02 03:30:51 PM PDT 24
Finished Jun 02 03:31:06 PM PDT 24
Peak memory 205784 kb
Host smart-07d108e1-45ca-4180-a2b6-45a14faaceac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82688
6334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.826886334
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.2918025776
Short name T411
Test name
Test status
Simulation time 10143329480 ps
CPU time 15.39 seconds
Started Jun 02 03:30:48 PM PDT 24
Finished Jun 02 03:31:05 PM PDT 24
Peak memory 205512 kb
Host smart-b6338279-71c4-4819-a056-c79eb6bfa2ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29180
25776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.2918025776
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.1700420571
Short name T1935
Test name
Test status
Simulation time 13175448790 ps
CPU time 17.01 seconds
Started Jun 02 03:30:48 PM PDT 24
Finished Jun 02 03:31:06 PM PDT 24
Peak memory 205708 kb
Host smart-26a097ea-285c-4198-950a-d75def794761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17004
20571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.1700420571
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.2608216339
Short name T1071
Test name
Test status
Simulation time 10107906855 ps
CPU time 14.22 seconds
Started Jun 02 03:30:49 PM PDT 24
Finished Jun 02 03:31:04 PM PDT 24
Peak memory 205608 kb
Host smart-4a20edb3-4a8f-4043-a7be-ddd306a6d89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26082
16339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2608216339
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.722437821
Short name T1553
Test name
Test status
Simulation time 15151561497 ps
CPU time 161.46 seconds
Started Jun 02 03:30:48 PM PDT 24
Finished Jun 02 03:33:31 PM PDT 24
Peak memory 205596 kb
Host smart-0f68a826-6f33-40a7-87c2-cbe08e59499f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72243
7821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.722437821
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.275734051
Short name T33
Test name
Test status
Simulation time 10091370326 ps
CPU time 14.89 seconds
Started Jun 02 03:30:45 PM PDT 24
Finished Jun 02 03:31:02 PM PDT 24
Peak memory 205788 kb
Host smart-59dd3905-dd15-45ba-b291-46da45b035b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27573
4051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.275734051
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1981659773
Short name T110
Test name
Test status
Simulation time 10092502100 ps
CPU time 14.23 seconds
Started Jun 02 03:30:55 PM PDT 24
Finished Jun 02 03:31:09 PM PDT 24
Peak memory 205660 kb
Host smart-10060832-970a-41b0-93e3-e304c2b27613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19816
59773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1981659773
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.2023090447
Short name T1520
Test name
Test status
Simulation time 10134270548 ps
CPU time 13.45 seconds
Started Jun 02 03:30:47 PM PDT 24
Finished Jun 02 03:31:01 PM PDT 24
Peak memory 205980 kb
Host smart-f79659d3-d7f0-47bf-9b05-380ac7f84520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20230
90447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.2023090447
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.184058389
Short name T452
Test name
Test status
Simulation time 10096301517 ps
CPU time 13.93 seconds
Started Jun 02 03:30:53 PM PDT 24
Finished Jun 02 03:31:08 PM PDT 24
Peak memory 205692 kb
Host smart-c4446903-f138-4689-af66-82c167bc6ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18405
8389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.184058389
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.1308657796
Short name T495
Test name
Test status
Simulation time 10131993315 ps
CPU time 13.27 seconds
Started Jun 02 03:30:51 PM PDT 24
Finished Jun 02 03:31:05 PM PDT 24
Peak memory 205656 kb
Host smart-62679d95-4120-425b-9619-01ff493aea05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13086
57796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.1308657796
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_eop_single_bit_handling.2519566848
Short name T347
Test name
Test status
Simulation time 10100157097 ps
CPU time 14.92 seconds
Started Jun 02 03:31:00 PM PDT 24
Finished Jun 02 03:31:15 PM PDT 24
Peak memory 205696 kb
Host smart-8dc23c34-3f5f-4c75-a0ca-1a765b947a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25195
66848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_eop_single_bit_handling.2519566848
Directory /workspace/32.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.2249793071
Short name T1646
Test name
Test status
Simulation time 10038912149 ps
CPU time 15.66 seconds
Started Jun 02 03:30:51 PM PDT 24
Finished Jun 02 03:31:08 PM PDT 24
Peak memory 205612 kb
Host smart-75d261a5-be6b-48d5-b06b-ee1ce0a6ec1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22497
93071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.2249793071
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.3119458982
Short name T430
Test name
Test status
Simulation time 10030029732 ps
CPU time 14.27 seconds
Started Jun 02 03:30:55 PM PDT 24
Finished Jun 02 03:31:10 PM PDT 24
Peak memory 205696 kb
Host smart-58c86c5a-9d7b-43c0-b1dc-504d0f17b39a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31194
58982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.3119458982
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.3789101815
Short name T1572
Test name
Test status
Simulation time 22453143083 ps
CPU time 38.8 seconds
Started Jun 02 03:30:47 PM PDT 24
Finished Jun 02 03:31:27 PM PDT 24
Peak memory 205644 kb
Host smart-43922f0a-f909-4680-b3ad-57ce4f9f6d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37891
01815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.3789101815
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.490327821
Short name T416
Test name
Test status
Simulation time 10111553414 ps
CPU time 13.54 seconds
Started Jun 02 03:30:52 PM PDT 24
Finished Jun 02 03:31:06 PM PDT 24
Peak memory 205708 kb
Host smart-20b432f5-a6ad-4164-b57b-bb897047f2fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49032
7821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.490327821
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3234161216
Short name T717
Test name
Test status
Simulation time 10126497510 ps
CPU time 16.42 seconds
Started Jun 02 03:30:55 PM PDT 24
Finished Jun 02 03:31:12 PM PDT 24
Peak memory 205780 kb
Host smart-daa85c1a-9340-4c7f-86fa-293968c103c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32341
61216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3234161216
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.2250881872
Short name T381
Test name
Test status
Simulation time 10095583368 ps
CPU time 14.26 seconds
Started Jun 02 03:30:53 PM PDT 24
Finished Jun 02 03:31:09 PM PDT 24
Peak memory 205392 kb
Host smart-6e933344-b187-46b2-969c-9f490461d916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22508
81872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.2250881872
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.2525143887
Short name T442
Test name
Test status
Simulation time 10050280850 ps
CPU time 13.1 seconds
Started Jun 02 03:30:54 PM PDT 24
Finished Jun 02 03:31:08 PM PDT 24
Peak memory 205704 kb
Host smart-c10fa8cc-b449-4ed8-b93b-1baefdfe4242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25251
43887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.2525143887
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.2690285458
Short name T1247
Test name
Test status
Simulation time 10068979763 ps
CPU time 14.47 seconds
Started Jun 02 03:30:53 PM PDT 24
Finished Jun 02 03:31:09 PM PDT 24
Peak memory 205732 kb
Host smart-3e1f0979-642d-426c-a691-7e269efbd9a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26902
85458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.2690285458
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2941867621
Short name T312
Test name
Test status
Simulation time 10048227293 ps
CPU time 13.81 seconds
Started Jun 02 03:30:53 PM PDT 24
Finished Jun 02 03:31:08 PM PDT 24
Peak memory 205712 kb
Host smart-e0f690c7-ad79-4928-ad96-5a677c358fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29418
67621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2941867621
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2001604291
Short name T2017
Test name
Test status
Simulation time 10139520342 ps
CPU time 17.16 seconds
Started Jun 02 03:30:48 PM PDT 24
Finished Jun 02 03:31:06 PM PDT 24
Peak memory 205732 kb
Host smart-fd23c74c-d6b3-413d-827d-cafeb30c1893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20016
04291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2001604291
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.2639503517
Short name T900
Test name
Test status
Simulation time 10061160219 ps
CPU time 14.06 seconds
Started Jun 02 03:30:54 PM PDT 24
Finished Jun 02 03:31:09 PM PDT 24
Peak memory 205712 kb
Host smart-59cd8ed1-8cbb-4454-a8c1-c2e231b8dcde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26395
03517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.2639503517
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.3130449201
Short name T1017
Test name
Test status
Simulation time 10091793167 ps
CPU time 14.73 seconds
Started Jun 02 03:30:52 PM PDT 24
Finished Jun 02 03:31:08 PM PDT 24
Peak memory 205860 kb
Host smart-361670f8-2d3d-46fd-8fd6-8198325f38b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31304
49201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.3130449201
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.1837804177
Short name T397
Test name
Test status
Simulation time 18589243232 ps
CPU time 96.95 seconds
Started Jun 02 03:30:51 PM PDT 24
Finished Jun 02 03:32:28 PM PDT 24
Peak memory 205696 kb
Host smart-6c8f215c-a63b-4279-9e90-9de1290cebea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18378
04177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.1837804177
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.3061082786
Short name T1287
Test name
Test status
Simulation time 10157409326 ps
CPU time 13.76 seconds
Started Jun 02 03:31:04 PM PDT 24
Finished Jun 02 03:31:19 PM PDT 24
Peak memory 205748 kb
Host smart-17992558-d40c-4baa-bdbf-b9ae285c39a6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3061082786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.3061082786
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.1202160129
Short name T1618
Test name
Test status
Simulation time 10057099241 ps
CPU time 13.27 seconds
Started Jun 02 03:31:01 PM PDT 24
Finished Jun 02 03:31:15 PM PDT 24
Peak memory 205656 kb
Host smart-d43db611-9790-46a2-b490-53fd8f58175c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1202160129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.1202160129
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.24149772
Short name T1716
Test name
Test status
Simulation time 10079721923 ps
CPU time 13.93 seconds
Started Jun 02 03:31:03 PM PDT 24
Finished Jun 02 03:31:18 PM PDT 24
Peak memory 205772 kb
Host smart-9d7880ef-8d1d-4109-8f90-bfed4517d3cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24149
772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.24149772
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.800328570
Short name T1180
Test name
Test status
Simulation time 13320665020 ps
CPU time 18.21 seconds
Started Jun 02 03:30:53 PM PDT 24
Finished Jun 02 03:31:12 PM PDT 24
Peak memory 205788 kb
Host smart-94159551-69d1-4283-b638-2b3680343f0f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=800328570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.800328570
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.3344963079
Short name T1089
Test name
Test status
Simulation time 23267016316 ps
CPU time 32.98 seconds
Started Jun 02 03:30:53 PM PDT 24
Finished Jun 02 03:31:27 PM PDT 24
Peak memory 205484 kb
Host smart-28a7f8d2-6136-4ae7-94fe-c2102920e210
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3344963079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.3344963079
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.4052408404
Short name T1421
Test name
Test status
Simulation time 10103953284 ps
CPU time 14.12 seconds
Started Jun 02 03:30:57 PM PDT 24
Finished Jun 02 03:31:11 PM PDT 24
Peak memory 205780 kb
Host smart-61f4a58d-1ec6-4c93-a20f-b4c56e782031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40524
08404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.4052408404
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.1121098783
Short name T498
Test name
Test status
Simulation time 10042019707 ps
CPU time 14.08 seconds
Started Jun 02 03:30:59 PM PDT 24
Finished Jun 02 03:31:13 PM PDT 24
Peak memory 205664 kb
Host smart-13936042-acf3-4e80-a2c0-25436637497b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11210
98783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.1121098783
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.2074746870
Short name T1472
Test name
Test status
Simulation time 10669455843 ps
CPU time 14.38 seconds
Started Jun 02 03:30:57 PM PDT 24
Finished Jun 02 03:31:12 PM PDT 24
Peak memory 205912 kb
Host smart-3e11363d-2a2e-401f-b97c-9bfd106214f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20747
46870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.2074746870
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2705280893
Short name T1456
Test name
Test status
Simulation time 10041638497 ps
CPU time 14.05 seconds
Started Jun 02 03:30:59 PM PDT 24
Finished Jun 02 03:31:14 PM PDT 24
Peak memory 205620 kb
Host smart-f1a74295-6157-46c2-a22b-5be913f2a906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27052
80893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2705280893
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.3090035652
Short name T1585
Test name
Test status
Simulation time 10077309862 ps
CPU time 15.41 seconds
Started Jun 02 03:30:56 PM PDT 24
Finished Jun 02 03:31:12 PM PDT 24
Peak memory 205736 kb
Host smart-f825f06f-fbe3-4f5c-9a5b-005214042ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30900
35652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.3090035652
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.1962654239
Short name T1183
Test name
Test status
Simulation time 10782410372 ps
CPU time 14.01 seconds
Started Jun 02 03:30:54 PM PDT 24
Finished Jun 02 03:31:09 PM PDT 24
Peak memory 205768 kb
Host smart-c93ca77d-8e5a-44cd-9b4b-9227d1a440d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19626
54239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.1962654239
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1609981288
Short name T581
Test name
Test status
Simulation time 10165712577 ps
CPU time 16 seconds
Started Jun 02 03:30:59 PM PDT 24
Finished Jun 02 03:31:16 PM PDT 24
Peak memory 205676 kb
Host smart-b52b8380-8c44-4035-8bf5-4a35a74ff62e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16099
81288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1609981288
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.2190370912
Short name T564
Test name
Test status
Simulation time 10075817375 ps
CPU time 14 seconds
Started Jun 02 03:31:05 PM PDT 24
Finished Jun 02 03:31:20 PM PDT 24
Peak memory 205760 kb
Host smart-54c9a9ff-8d3e-407f-b7fa-7038b3e321fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21903
70912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2190370912
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2843417436
Short name T85
Test name
Test status
Simulation time 10038823944 ps
CPU time 13.58 seconds
Started Jun 02 03:31:01 PM PDT 24
Finished Jun 02 03:31:16 PM PDT 24
Peak memory 205644 kb
Host smart-4a130e0a-a226-4fe3-8f64-145229d79df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28434
17436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2843417436
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.1979803804
Short name T797
Test name
Test status
Simulation time 10137333862 ps
CPU time 17.09 seconds
Started Jun 02 03:30:58 PM PDT 24
Finished Jun 02 03:31:15 PM PDT 24
Peak memory 205764 kb
Host smart-92da8368-4d4b-437e-a369-935cf28d11e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19798
03804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1979803804
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.1104297783
Short name T511
Test name
Test status
Simulation time 10111181855 ps
CPU time 14.32 seconds
Started Jun 02 03:30:59 PM PDT 24
Finished Jun 02 03:31:14 PM PDT 24
Peak memory 205628 kb
Host smart-4e8a8e4d-42bf-4ade-be7b-a52dfcf73f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11042
97783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.1104297783
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.1269199671
Short name T1542
Test name
Test status
Simulation time 13226798632 ps
CPU time 15.9 seconds
Started Jun 02 03:30:55 PM PDT 24
Finished Jun 02 03:31:12 PM PDT 24
Peak memory 205728 kb
Host smart-5b3c1f2b-44e8-411e-82b5-240e836231bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12691
99671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.1269199671
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1171877815
Short name T542
Test name
Test status
Simulation time 10092545760 ps
CPU time 13.84 seconds
Started Jun 02 03:30:54 PM PDT 24
Finished Jun 02 03:31:09 PM PDT 24
Peak memory 205772 kb
Host smart-47648e6a-02c4-44a7-83f6-85ae81a7cb6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11718
77815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1171877815
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.4152577141
Short name T1652
Test name
Test status
Simulation time 20528967526 ps
CPU time 114.54 seconds
Started Jun 02 03:30:55 PM PDT 24
Finished Jun 02 03:32:50 PM PDT 24
Peak memory 205704 kb
Host smart-1c7fb5f7-f408-4bc2-80ac-49aa22d53f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41525
77141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.4152577141
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.3678499654
Short name T1332
Test name
Test status
Simulation time 10079143254 ps
CPU time 14.52 seconds
Started Jun 02 03:30:56 PM PDT 24
Finished Jun 02 03:31:11 PM PDT 24
Peak memory 205780 kb
Host smart-7be5bb48-e6f6-4003-b7db-7e2eae643fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36784
99654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.3678499654
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.1075554727
Short name T116
Test name
Test status
Simulation time 10124105278 ps
CPU time 12.86 seconds
Started Jun 02 03:30:58 PM PDT 24
Finished Jun 02 03:31:12 PM PDT 24
Peak memory 205780 kb
Host smart-e8aead5c-571d-4542-9dfb-5542665656ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10755
54727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.1075554727
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.626597204
Short name T1086
Test name
Test status
Simulation time 10150344713 ps
CPU time 13.1 seconds
Started Jun 02 03:30:57 PM PDT 24
Finished Jun 02 03:31:10 PM PDT 24
Peak memory 205668 kb
Host smart-ec906626-c906-433d-820c-e1b6579619f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62659
7204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.626597204
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3522250404
Short name T1556
Test name
Test status
Simulation time 10084392748 ps
CPU time 15.52 seconds
Started Jun 02 03:30:59 PM PDT 24
Finished Jun 02 03:31:15 PM PDT 24
Peak memory 205740 kb
Host smart-d8dffd34-e971-44bc-bb9f-bec2b507a831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35222
50404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3522250404
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.3106911334
Short name T839
Test name
Test status
Simulation time 10075641729 ps
CPU time 13.14 seconds
Started Jun 02 03:31:01 PM PDT 24
Finished Jun 02 03:31:16 PM PDT 24
Peak memory 205464 kb
Host smart-df832321-7f5c-418d-aae2-8ad50bd9b3e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31069
11334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.3106911334
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.1797518868
Short name T187
Test name
Test status
Simulation time 10075207811 ps
CPU time 14.41 seconds
Started Jun 02 03:31:03 PM PDT 24
Finished Jun 02 03:31:18 PM PDT 24
Peak memory 205760 kb
Host smart-dcf0f3f7-4eb1-44eb-b2fa-9bbfea0959d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17975
18868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.1797518868
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_eop_single_bit_handling.1720368319
Short name T1999
Test name
Test status
Simulation time 10048236023 ps
CPU time 15.99 seconds
Started Jun 02 03:31:03 PM PDT 24
Finished Jun 02 03:31:20 PM PDT 24
Peak memory 205972 kb
Host smart-6fb2611a-e489-4ca9-8370-f3b225878934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17203
68319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_eop_single_bit_handling.1720368319
Directory /workspace/33.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.2842589281
Short name T1297
Test name
Test status
Simulation time 10044439148 ps
CPU time 15.63 seconds
Started Jun 02 03:30:55 PM PDT 24
Finished Jun 02 03:31:11 PM PDT 24
Peak memory 205636 kb
Host smart-51dd5730-b3f8-4a0e-95fd-5c9d9ce581c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28425
89281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.2842589281
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.4279880418
Short name T1920
Test name
Test status
Simulation time 10064757207 ps
CPU time 15.24 seconds
Started Jun 02 03:31:05 PM PDT 24
Finished Jun 02 03:31:21 PM PDT 24
Peak memory 205648 kb
Host smart-8ecb7d8b-0dd1-4bbf-92d4-15ca237754d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42798
80418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.4279880418
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.420278701
Short name T1311
Test name
Test status
Simulation time 23527634553 ps
CPU time 41.26 seconds
Started Jun 02 03:30:54 PM PDT 24
Finished Jun 02 03:31:36 PM PDT 24
Peak memory 205632 kb
Host smart-db1fb86c-c7d6-47df-8077-f61b4fc5d1c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42027
8701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.420278701
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.3812522121
Short name T697
Test name
Test status
Simulation time 10076629675 ps
CPU time 13.4 seconds
Started Jun 02 03:30:57 PM PDT 24
Finished Jun 02 03:31:11 PM PDT 24
Peak memory 205672 kb
Host smart-a2b20092-f5dd-4912-853f-af674872223f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38125
22121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.3812522121
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3394761521
Short name T1729
Test name
Test status
Simulation time 10145848513 ps
CPU time 15.6 seconds
Started Jun 02 03:30:55 PM PDT 24
Finished Jun 02 03:31:11 PM PDT 24
Peak memory 205656 kb
Host smart-1578bcef-5cf5-4196-aa9a-98889bb07fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33947
61521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3394761521
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.3859939096
Short name T798
Test name
Test status
Simulation time 10108317418 ps
CPU time 13.54 seconds
Started Jun 02 03:31:01 PM PDT 24
Finished Jun 02 03:31:16 PM PDT 24
Peak memory 205416 kb
Host smart-07fbeef7-c428-4cf3-b701-c0db7f689098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38599
39096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.3859939096
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1177278797
Short name T1066
Test name
Test status
Simulation time 10048184828 ps
CPU time 16.46 seconds
Started Jun 02 03:30:56 PM PDT 24
Finished Jun 02 03:31:13 PM PDT 24
Peak memory 205752 kb
Host smart-385aa1b8-ab35-4899-b455-ad97bde6bfb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11772
78797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1177278797
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.3554264830
Short name T1558
Test name
Test status
Simulation time 10099354777 ps
CPU time 13.08 seconds
Started Jun 02 03:31:00 PM PDT 24
Finished Jun 02 03:31:14 PM PDT 24
Peak memory 205720 kb
Host smart-c5953e81-3dc5-4caf-935f-336f9acb7ac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35542
64830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.3554264830
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.4001361805
Short name T483
Test name
Test status
Simulation time 10061571920 ps
CPU time 13.34 seconds
Started Jun 02 03:30:59 PM PDT 24
Finished Jun 02 03:31:13 PM PDT 24
Peak memory 205676 kb
Host smart-df4f7cab-0d60-4051-a9d2-d20be7e4ac8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40013
61805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.4001361805
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2483805605
Short name T1197
Test name
Test status
Simulation time 10197606684 ps
CPU time 15.21 seconds
Started Jun 02 03:30:55 PM PDT 24
Finished Jun 02 03:31:11 PM PDT 24
Peak memory 205680 kb
Host smart-fb8fe8f5-3791-46b6-9b8e-18f3e4a868ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24838
05605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2483805605
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.478901730
Short name T1435
Test name
Test status
Simulation time 10083054619 ps
CPU time 13.67 seconds
Started Jun 02 03:31:02 PM PDT 24
Finished Jun 02 03:31:17 PM PDT 24
Peak memory 205628 kb
Host smart-355df1e8-01d8-4fa2-be6d-15b5ce391419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47890
1730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.478901730
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.1199603369
Short name T1104
Test name
Test status
Simulation time 10097285341 ps
CPU time 13.81 seconds
Started Jun 02 03:30:59 PM PDT 24
Finished Jun 02 03:31:14 PM PDT 24
Peak memory 205652 kb
Host smart-8a8bf57c-56ed-4327-8187-73dc351a6dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11996
03369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.1199603369
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.3044827258
Short name T1761
Test name
Test status
Simulation time 19189686841 ps
CPU time 98.51 seconds
Started Jun 02 03:30:54 PM PDT 24
Finished Jun 02 03:32:33 PM PDT 24
Peak memory 205688 kb
Host smart-0ae9b5a8-25c2-4cd9-8e6c-6aa09bf6e09a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30448
27258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.3044827258
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.401505771
Short name T1072
Test name
Test status
Simulation time 10140519686 ps
CPU time 13.13 seconds
Started Jun 02 03:31:16 PM PDT 24
Finished Jun 02 03:31:30 PM PDT 24
Peak memory 205344 kb
Host smart-5955db3e-0f6c-4ea7-a91e-df820a6b64bf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=401505771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.401505771
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.1321046489
Short name T561
Test name
Test status
Simulation time 10068646820 ps
CPU time 16.68 seconds
Started Jun 02 03:31:04 PM PDT 24
Finished Jun 02 03:31:21 PM PDT 24
Peak memory 205668 kb
Host smart-96c1969b-36be-4d11-881f-ba343fca3b40
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1321046489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.1321046489
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.3725589107
Short name T1464
Test name
Test status
Simulation time 10135733461 ps
CPU time 13.87 seconds
Started Jun 02 03:31:05 PM PDT 24
Finished Jun 02 03:31:20 PM PDT 24
Peak memory 205620 kb
Host smart-86dff00a-3daa-433d-93c9-83fafbd4ff78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37255
89107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.3725589107
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.2071832706
Short name T1741
Test name
Test status
Simulation time 14273663869 ps
CPU time 18.25 seconds
Started Jun 02 03:31:07 PM PDT 24
Finished Jun 02 03:31:26 PM PDT 24
Peak memory 205780 kb
Host smart-bdf06f62-317c-4b45-90a6-1bf35891a9db
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2071832706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.2071832706
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.405057725
Short name T13
Test name
Test status
Simulation time 23272529719 ps
CPU time 28.34 seconds
Started Jun 02 03:31:05 PM PDT 24
Finished Jun 02 03:31:34 PM PDT 24
Peak memory 205712 kb
Host smart-ca6d335d-d076-4779-af41-3a528a93d5c8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=405057725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.405057725
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.566288621
Short name T1767
Test name
Test status
Simulation time 10056900033 ps
CPU time 15.12 seconds
Started Jun 02 03:31:08 PM PDT 24
Finished Jun 02 03:31:24 PM PDT 24
Peak memory 205784 kb
Host smart-6539ceaa-92c8-44a1-8695-fee44b89cd8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56628
8621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.566288621
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.542960869
Short name T1906
Test name
Test status
Simulation time 10134131989 ps
CPU time 12.39 seconds
Started Jun 02 03:31:04 PM PDT 24
Finished Jun 02 03:31:17 PM PDT 24
Peak memory 205748 kb
Host smart-d60d98cf-600f-451c-903e-4a7964bd3b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54296
0869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.542960869
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.3978205600
Short name T1289
Test name
Test status
Simulation time 10043637427 ps
CPU time 12.38 seconds
Started Jun 02 03:31:04 PM PDT 24
Finished Jun 02 03:31:17 PM PDT 24
Peak memory 205708 kb
Host smart-1e0a2b88-b21c-4205-a625-82a8e41d5086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39782
05600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.3978205600
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.2588269319
Short name T1937
Test name
Test status
Simulation time 10060340418 ps
CPU time 12.46 seconds
Started Jun 02 03:31:01 PM PDT 24
Finished Jun 02 03:31:14 PM PDT 24
Peak memory 205680 kb
Host smart-a934030a-d853-4b50-ad04-dd5b063f0587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25882
69319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.2588269319
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.3562211322
Short name T860
Test name
Test status
Simulation time 10809598939 ps
CPU time 15.13 seconds
Started Jun 02 03:31:08 PM PDT 24
Finished Jun 02 03:31:24 PM PDT 24
Peak memory 205708 kb
Host smart-85a4090a-8bd9-4e1c-9bda-2b03321861dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35622
11322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.3562211322
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.1960596984
Short name T190
Test name
Test status
Simulation time 10237317018 ps
CPU time 15.55 seconds
Started Jun 02 03:31:01 PM PDT 24
Finished Jun 02 03:31:17 PM PDT 24
Peak memory 205744 kb
Host smart-3f2d11a2-9828-44b7-ad08-132c1f02a05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19605
96984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.1960596984
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.520758742
Short name T1004
Test name
Test status
Simulation time 10114029399 ps
CPU time 14.79 seconds
Started Jun 02 03:31:06 PM PDT 24
Finished Jun 02 03:31:21 PM PDT 24
Peak memory 205780 kb
Host smart-49413661-d8ed-4593-8aad-7fb5a656ed93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52075
8742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.520758742
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.1462224551
Short name T650
Test name
Test status
Simulation time 10070852010 ps
CPU time 12.79 seconds
Started Jun 02 03:31:16 PM PDT 24
Finished Jun 02 03:31:30 PM PDT 24
Peak memory 205480 kb
Host smart-d1db7a48-d99e-4c04-995f-6ac3af5fa781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14622
24551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.1462224551
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2360465887
Short name T1122
Test name
Test status
Simulation time 10162210448 ps
CPU time 13.15 seconds
Started Jun 02 03:31:04 PM PDT 24
Finished Jun 02 03:31:17 PM PDT 24
Peak memory 205764 kb
Host smart-8e07bae1-bb54-4a95-8bbe-b9d7c4d3b018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23604
65887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2360465887
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.4150359769
Short name T807
Test name
Test status
Simulation time 10105167845 ps
CPU time 14.61 seconds
Started Jun 02 03:31:03 PM PDT 24
Finished Jun 02 03:31:18 PM PDT 24
Peak memory 205696 kb
Host smart-edb2bdc6-676c-454f-9f3a-d044805d26d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41503
59769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.4150359769
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.1003338684
Short name T1022
Test name
Test status
Simulation time 13244565897 ps
CPU time 18.29 seconds
Started Jun 02 03:31:03 PM PDT 24
Finished Jun 02 03:31:22 PM PDT 24
Peak memory 205696 kb
Host smart-0a0ae3bc-a81d-4801-8865-9628c79c2a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10033
38684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.1003338684
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2941807054
Short name T713
Test name
Test status
Simulation time 10114202870 ps
CPU time 14.52 seconds
Started Jun 02 03:31:06 PM PDT 24
Finished Jun 02 03:31:22 PM PDT 24
Peak memory 205652 kb
Host smart-9067d2fe-9771-43dd-9a8d-1d2719652e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29418
07054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2941807054
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.774908712
Short name T1204
Test name
Test status
Simulation time 20139155380 ps
CPU time 84.54 seconds
Started Jun 02 03:31:12 PM PDT 24
Finished Jun 02 03:32:37 PM PDT 24
Peak memory 205712 kb
Host smart-3433b4cd-f235-491e-b927-d9921fed512f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77490
8712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.774908712
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.1747937459
Short name T505
Test name
Test status
Simulation time 10055197430 ps
CPU time 12.56 seconds
Started Jun 02 03:31:06 PM PDT 24
Finished Jun 02 03:31:19 PM PDT 24
Peak memory 205696 kb
Host smart-4a253c70-5d33-43d7-903e-5caf291a4e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17479
37459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.1747937459
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.539513260
Short name T1943
Test name
Test status
Simulation time 10072745389 ps
CPU time 13.73 seconds
Started Jun 02 03:31:03 PM PDT 24
Finished Jun 02 03:31:18 PM PDT 24
Peak memory 205612 kb
Host smart-a9c40e80-968e-4164-a649-75b4333d6930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53951
3260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.539513260
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.3576750504
Short name T1100
Test name
Test status
Simulation time 10125280715 ps
CPU time 13.17 seconds
Started Jun 02 03:31:07 PM PDT 24
Finished Jun 02 03:31:21 PM PDT 24
Peak memory 205704 kb
Host smart-37be381d-22d3-4471-85f5-51f4ce96770a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35767
50504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3576750504
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.4154513509
Short name T1063
Test name
Test status
Simulation time 10065120972 ps
CPU time 13.42 seconds
Started Jun 02 03:31:04 PM PDT 24
Finished Jun 02 03:31:18 PM PDT 24
Peak memory 205692 kb
Host smart-d08f3120-4d44-40ed-baef-1d0a9a5e53cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41545
13509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.4154513509
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.4280526190
Short name T181
Test name
Test status
Simulation time 10069378251 ps
CPU time 12.86 seconds
Started Jun 02 03:31:16 PM PDT 24
Finished Jun 02 03:31:30 PM PDT 24
Peak memory 205640 kb
Host smart-8032df01-3056-4e39-96ba-eb7d431de780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42805
26190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.4280526190
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_eop_single_bit_handling.1905601837
Short name T1694
Test name
Test status
Simulation time 10132900775 ps
CPU time 13.04 seconds
Started Jun 02 03:31:06 PM PDT 24
Finished Jun 02 03:31:20 PM PDT 24
Peak memory 205724 kb
Host smart-53de6f9f-73d0-473f-8aa9-bedd193fc7e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19056
01837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_eop_single_bit_handling.1905601837
Directory /workspace/34.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.3857339542
Short name T574
Test name
Test status
Simulation time 10075430979 ps
CPU time 13.73 seconds
Started Jun 02 03:31:06 PM PDT 24
Finished Jun 02 03:31:21 PM PDT 24
Peak memory 205704 kb
Host smart-e7690eea-82ed-426c-b060-d5e4cdae232a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38573
39542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.3857339542
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.2693172245
Short name T45
Test name
Test status
Simulation time 10052452879 ps
CPU time 15.54 seconds
Started Jun 02 03:31:05 PM PDT 24
Finished Jun 02 03:31:22 PM PDT 24
Peak memory 205776 kb
Host smart-c570082e-52f6-477e-8484-4b0c900da2ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26931
72245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.2693172245
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.2301463826
Short name T1624
Test name
Test status
Simulation time 19111124107 ps
CPU time 33.57 seconds
Started Jun 02 03:31:04 PM PDT 24
Finished Jun 02 03:31:39 PM PDT 24
Peak memory 205676 kb
Host smart-e16f21d3-371d-4726-abe0-b4f32048a77a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23014
63826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.2301463826
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.740290360
Short name T1671
Test name
Test status
Simulation time 10107463245 ps
CPU time 13.09 seconds
Started Jun 02 03:31:08 PM PDT 24
Finished Jun 02 03:31:22 PM PDT 24
Peak memory 205716 kb
Host smart-5cbcb6ab-2869-4838-9ae8-953d8c706e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74029
0360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.740290360
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.3180791411
Short name T727
Test name
Test status
Simulation time 10098325137 ps
CPU time 14.67 seconds
Started Jun 02 03:31:19 PM PDT 24
Finished Jun 02 03:31:34 PM PDT 24
Peak memory 205660 kb
Host smart-80f30a77-7409-418e-9439-11974990f272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31807
91411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.3180791411
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.2661738763
Short name T1698
Test name
Test status
Simulation time 10098608347 ps
CPU time 15.49 seconds
Started Jun 02 03:31:08 PM PDT 24
Finished Jun 02 03:31:24 PM PDT 24
Peak memory 205952 kb
Host smart-d20a429c-657d-49a1-a235-5f2df0ea2a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26617
38763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.2661738763
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.1229803493
Short name T2004
Test name
Test status
Simulation time 10089908324 ps
CPU time 13.13 seconds
Started Jun 02 03:31:16 PM PDT 24
Finished Jun 02 03:31:30 PM PDT 24
Peak memory 205492 kb
Host smart-0e822129-38e9-41ac-bf7c-02ee90ad19f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12298
03493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.1229803493
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.3372550580
Short name T157
Test name
Test status
Simulation time 10121945427 ps
CPU time 14.72 seconds
Started Jun 02 03:31:07 PM PDT 24
Finished Jun 02 03:31:23 PM PDT 24
Peak memory 205740 kb
Host smart-3b18230f-55b9-40e6-9c17-bf0b94e28f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33725
50580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.3372550580
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.2985405258
Short name T557
Test name
Test status
Simulation time 10050402858 ps
CPU time 14.29 seconds
Started Jun 02 03:31:05 PM PDT 24
Finished Jun 02 03:31:20 PM PDT 24
Peak memory 205860 kb
Host smart-3d942542-98ed-4891-9c47-7e743a6acf7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29854
05258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.2985405258
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2962841054
Short name T150
Test name
Test status
Simulation time 10142009602 ps
CPU time 15.22 seconds
Started Jun 02 03:31:06 PM PDT 24
Finished Jun 02 03:31:22 PM PDT 24
Peak memory 205756 kb
Host smart-b92bd81f-bb53-43bd-8255-137bcde700e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29628
41054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2962841054
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.942045680
Short name T1381
Test name
Test status
Simulation time 10062377116 ps
CPU time 14.26 seconds
Started Jun 02 03:31:07 PM PDT 24
Finished Jun 02 03:31:22 PM PDT 24
Peak memory 205696 kb
Host smart-598368f2-d1e9-4c9b-b903-2e50ba11bb17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94204
5680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.942045680
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.1416212635
Short name T1584
Test name
Test status
Simulation time 10070544136 ps
CPU time 15.88 seconds
Started Jun 02 03:31:16 PM PDT 24
Finished Jun 02 03:31:33 PM PDT 24
Peak memory 205600 kb
Host smart-b2940d3e-c906-4ad9-ad91-e57f9f0c59af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14162
12635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1416212635
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.1897112953
Short name T305
Test name
Test status
Simulation time 21814900944 ps
CPU time 122.64 seconds
Started Jun 02 03:31:05 PM PDT 24
Finished Jun 02 03:33:09 PM PDT 24
Peak memory 205608 kb
Host smart-bda8d75b-c034-4236-86a1-e0fe26200c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18971
12953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.1897112953
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.3289401754
Short name T726
Test name
Test status
Simulation time 10141700712 ps
CPU time 13.89 seconds
Started Jun 02 03:31:13 PM PDT 24
Finished Jun 02 03:31:28 PM PDT 24
Peak memory 205692 kb
Host smart-79351086-85da-4a58-a9f5-9ba605229424
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3289401754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.3289401754
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.3640178480
Short name T1960
Test name
Test status
Simulation time 10053470461 ps
CPU time 13.22 seconds
Started Jun 02 03:31:18 PM PDT 24
Finished Jun 02 03:31:32 PM PDT 24
Peak memory 205696 kb
Host smart-28d181fe-b2dd-4f63-8673-7065aac5cf10
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3640178480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.3640178480
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.3272017762
Short name T1597
Test name
Test status
Simulation time 10081553512 ps
CPU time 13.66 seconds
Started Jun 02 03:31:16 PM PDT 24
Finished Jun 02 03:31:30 PM PDT 24
Peak memory 205624 kb
Host smart-ff9e0071-4d4e-4750-864b-77c78047203b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32720
17762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.3272017762
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.3159458983
Short name T1045
Test name
Test status
Simulation time 14275477819 ps
CPU time 17.1 seconds
Started Jun 02 03:31:16 PM PDT 24
Finished Jun 02 03:31:34 PM PDT 24
Peak memory 205644 kb
Host smart-aafdeab5-d6a7-42af-96de-fb7cc6614413
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3159458983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.3159458983
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.3542144325
Short name T486
Test name
Test status
Simulation time 23271683364 ps
CPU time 28.2 seconds
Started Jun 02 03:31:07 PM PDT 24
Finished Jun 02 03:31:36 PM PDT 24
Peak memory 205704 kb
Host smart-9865f3d3-6eac-46bc-be3b-b453e92f5131
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3542144325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.3542144325
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.3799483150
Short name T1444
Test name
Test status
Simulation time 10040047163 ps
CPU time 14.82 seconds
Started Jun 02 03:31:06 PM PDT 24
Finished Jun 02 03:31:22 PM PDT 24
Peak memory 205720 kb
Host smart-f908c580-6933-49d7-a0f2-41926812590d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37994
83150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.3799483150
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.3681946297
Short name T55
Test name
Test status
Simulation time 10038561845 ps
CPU time 14.9 seconds
Started Jun 02 03:31:16 PM PDT 24
Finished Jun 02 03:31:32 PM PDT 24
Peak memory 205628 kb
Host smart-35e99eff-3221-4dac-9227-1d1083175544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36819
46297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.3681946297
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.1664859643
Short name T527
Test name
Test status
Simulation time 11030825222 ps
CPU time 15.92 seconds
Started Jun 02 03:31:05 PM PDT 24
Finished Jun 02 03:31:22 PM PDT 24
Peak memory 205688 kb
Host smart-ae2ef74b-4408-475b-92a6-25c7bdaa2287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16648
59643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.1664859643
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.622125590
Short name T1413
Test name
Test status
Simulation time 10040273368 ps
CPU time 14.18 seconds
Started Jun 02 03:31:15 PM PDT 24
Finished Jun 02 03:31:30 PM PDT 24
Peak memory 205780 kb
Host smart-532b1775-85c7-45bd-8dc8-bb4488208ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62212
5590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.622125590
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.3145953147
Short name T1328
Test name
Test status
Simulation time 10040243748 ps
CPU time 14.17 seconds
Started Jun 02 03:31:16 PM PDT 24
Finished Jun 02 03:31:32 PM PDT 24
Peak memory 205608 kb
Host smart-9deabff4-faab-4edd-862d-16fcb914ac3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31459
53147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.3145953147
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.864565669
Short name T1395
Test name
Test status
Simulation time 10730984844 ps
CPU time 13.89 seconds
Started Jun 02 03:31:07 PM PDT 24
Finished Jun 02 03:31:21 PM PDT 24
Peak memory 205672 kb
Host smart-8b743b88-18b0-461f-92bb-52d3a08feead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86456
5669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.864565669
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1655980346
Short name T1021
Test name
Test status
Simulation time 10137292651 ps
CPU time 15.16 seconds
Started Jun 02 03:31:10 PM PDT 24
Finished Jun 02 03:31:26 PM PDT 24
Peak memory 205660 kb
Host smart-022168f2-dfd9-44a8-9778-64381f071446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16559
80346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1655980346
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.3863298825
Short name T331
Test name
Test status
Simulation time 10090243346 ps
CPU time 14.92 seconds
Started Jun 02 03:31:13 PM PDT 24
Finished Jun 02 03:31:28 PM PDT 24
Peak memory 205756 kb
Host smart-3a190207-50ab-4f82-9c50-ca49149092b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38632
98825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.3863298825
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.3102176918
Short name T1736
Test name
Test status
Simulation time 10050629142 ps
CPU time 14.15 seconds
Started Jun 02 03:31:19 PM PDT 24
Finished Jun 02 03:31:34 PM PDT 24
Peak memory 205732 kb
Host smart-74ce8cf6-b08d-4da4-b4b9-e34d9dbfc18e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31021
76918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.3102176918
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3420071971
Short name T1545
Test name
Test status
Simulation time 10129945610 ps
CPU time 12.99 seconds
Started Jun 02 03:31:16 PM PDT 24
Finished Jun 02 03:31:30 PM PDT 24
Peak memory 205296 kb
Host smart-282feb59-3ba6-4e18-9f5b-36e6a33e768d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34200
71971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3420071971
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.699617292
Short name T1325
Test name
Test status
Simulation time 10128777495 ps
CPU time 14.07 seconds
Started Jun 02 03:31:16 PM PDT 24
Finished Jun 02 03:31:31 PM PDT 24
Peak memory 205740 kb
Host smart-9137f2cb-c68c-4b88-b1b8-566862dfe368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69961
7292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.699617292
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.3225827835
Short name T1032
Test name
Test status
Simulation time 13270948214 ps
CPU time 16.53 seconds
Started Jun 02 03:31:09 PM PDT 24
Finished Jun 02 03:31:26 PM PDT 24
Peak memory 205732 kb
Host smart-f93f0304-7bff-4b4e-bd83-d45ab79b9d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32258
27835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.3225827835
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.1054361911
Short name T1662
Test name
Test status
Simulation time 10125855323 ps
CPU time 13.76 seconds
Started Jun 02 03:31:05 PM PDT 24
Finished Jun 02 03:31:20 PM PDT 24
Peak memory 205768 kb
Host smart-35a5a7f0-efc3-4db4-b42b-68bb89030e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10543
61911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.1054361911
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.3124536844
Short name T450
Test name
Test status
Simulation time 19942238365 ps
CPU time 303.72 seconds
Started Jun 02 03:31:11 PM PDT 24
Finished Jun 02 03:36:15 PM PDT 24
Peak memory 205684 kb
Host smart-ce64843e-c9bf-4d63-b858-233d639e0446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31245
36844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.3124536844
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.3328521791
Short name T1371
Test name
Test status
Simulation time 10098536092 ps
CPU time 14.42 seconds
Started Jun 02 03:31:11 PM PDT 24
Finished Jun 02 03:31:26 PM PDT 24
Peak memory 205636 kb
Host smart-7322f227-22fb-4843-8c69-4db26316b29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33285
21791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.3328521791
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2471515490
Short name T1863
Test name
Test status
Simulation time 10096782721 ps
CPU time 13.64 seconds
Started Jun 02 03:31:13 PM PDT 24
Finished Jun 02 03:31:27 PM PDT 24
Peak memory 205672 kb
Host smart-508c6d97-d074-4604-9d48-96999c24ba2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24715
15490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2471515490
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.1625272604
Short name T1306
Test name
Test status
Simulation time 10092963270 ps
CPU time 13.08 seconds
Started Jun 02 03:31:15 PM PDT 24
Finished Jun 02 03:31:29 PM PDT 24
Peak memory 205708 kb
Host smart-c3f30dd9-2bd1-479c-b43d-9bd078091860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16252
72604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.1625272604
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.2773586716
Short name T1979
Test name
Test status
Simulation time 10063157564 ps
CPU time 13.79 seconds
Started Jun 02 03:31:12 PM PDT 24
Finished Jun 02 03:31:26 PM PDT 24
Peak memory 205704 kb
Host smart-4a335a49-75d9-4378-82c1-f9597a0ccf8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27735
86716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.2773586716
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3344275805
Short name T1691
Test name
Test status
Simulation time 10091496549 ps
CPU time 14.07 seconds
Started Jun 02 03:31:13 PM PDT 24
Finished Jun 02 03:31:27 PM PDT 24
Peak memory 205608 kb
Host smart-02caddb4-a116-460d-93c0-fe531b862687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33442
75805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3344275805
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.2915160138
Short name T142
Test name
Test status
Simulation time 10053615525 ps
CPU time 14.53 seconds
Started Jun 02 03:31:11 PM PDT 24
Finished Jun 02 03:31:26 PM PDT 24
Peak memory 205760 kb
Host smart-2ae5e2ad-fed6-4da8-ae04-bab08af301ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29151
60138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.2915160138
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_eop_single_bit_handling.352933477
Short name T1257
Test name
Test status
Simulation time 10083094969 ps
CPU time 12.95 seconds
Started Jun 02 03:31:15 PM PDT 24
Finished Jun 02 03:31:29 PM PDT 24
Peak memory 205672 kb
Host smart-48c7224b-e68f-49a4-8eb4-33ec66b38025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35293
3477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_eop_single_bit_handling.352933477
Directory /workspace/35.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.1037701537
Short name T633
Test name
Test status
Simulation time 10042816834 ps
CPU time 13.29 seconds
Started Jun 02 03:31:12 PM PDT 24
Finished Jun 02 03:31:26 PM PDT 24
Peak memory 205720 kb
Host smart-0bbdb021-e883-4d7b-b21c-f727b18df93e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10377
01537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.1037701537
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.4229831675
Short name T1261
Test name
Test status
Simulation time 10084834574 ps
CPU time 13.19 seconds
Started Jun 02 03:31:11 PM PDT 24
Finished Jun 02 03:31:25 PM PDT 24
Peak memory 205584 kb
Host smart-4dd536d6-f8e1-420a-91bf-6c40a7d00ef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42298
31675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.4229831675
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1944916752
Short name T1141
Test name
Test status
Simulation time 24019853415 ps
CPU time 43.86 seconds
Started Jun 02 03:31:10 PM PDT 24
Finished Jun 02 03:31:54 PM PDT 24
Peak memory 205624 kb
Host smart-80f1d483-e299-43c8-bae3-d7023a2b660c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19449
16752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1944916752
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.1793556399
Short name T1221
Test name
Test status
Simulation time 10084350099 ps
CPU time 14.38 seconds
Started Jun 02 03:31:11 PM PDT 24
Finished Jun 02 03:31:26 PM PDT 24
Peak memory 205668 kb
Host smart-abda72f4-b771-4913-af57-110bcfebe089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17935
56399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.1793556399
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.572717887
Short name T1350
Test name
Test status
Simulation time 10150191129 ps
CPU time 15.97 seconds
Started Jun 02 03:31:14 PM PDT 24
Finished Jun 02 03:31:31 PM PDT 24
Peak memory 205756 kb
Host smart-1d1a367b-4001-4efd-bbda-e91ad4035729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57271
7887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.572717887
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.3895067563
Short name T40
Test name
Test status
Simulation time 10071902397 ps
CPU time 13.76 seconds
Started Jun 02 03:31:11 PM PDT 24
Finished Jun 02 03:31:25 PM PDT 24
Peak memory 205712 kb
Host smart-412b9f0f-0c0f-421a-88dd-550173e0edbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38950
67563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.3895067563
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.2254766975
Short name T723
Test name
Test status
Simulation time 10120214373 ps
CPU time 12.95 seconds
Started Jun 02 03:31:20 PM PDT 24
Finished Jun 02 03:31:34 PM PDT 24
Peak memory 205736 kb
Host smart-0dc8af54-1807-4d64-a858-c6ab2c0a23f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22547
66975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.2254766975
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.459557994
Short name T1217
Test name
Test status
Simulation time 10047447917 ps
CPU time 13.15 seconds
Started Jun 02 03:31:15 PM PDT 24
Finished Jun 02 03:31:29 PM PDT 24
Peak memory 205640 kb
Host smart-7be5f6e4-8142-4ffb-aa8a-48d15a02beda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45955
7994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.459557994
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.851398784
Short name T1211
Test name
Test status
Simulation time 10056451085 ps
CPU time 12.91 seconds
Started Jun 02 03:31:10 PM PDT 24
Finished Jun 02 03:31:24 PM PDT 24
Peak memory 205644 kb
Host smart-979b4eb1-300f-4c68-9a46-94910f619364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85139
8784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.851398784
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.2346786116
Short name T149
Test name
Test status
Simulation time 10142345816 ps
CPU time 12.96 seconds
Started Jun 02 03:31:19 PM PDT 24
Finished Jun 02 03:31:33 PM PDT 24
Peak memory 205588 kb
Host smart-0c847fa0-8f8e-4434-a698-4cd0d6a83f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23467
86116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2346786116
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3198461864
Short name T1782
Test name
Test status
Simulation time 10111098316 ps
CPU time 12.88 seconds
Started Jun 02 03:31:19 PM PDT 24
Finished Jun 02 03:31:32 PM PDT 24
Peak memory 205688 kb
Host smart-63c459fc-e701-446d-95c3-40457a7b6796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31984
61864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3198461864
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.486239762
Short name T414
Test name
Test status
Simulation time 10093130339 ps
CPU time 14.95 seconds
Started Jun 02 03:31:12 PM PDT 24
Finished Jun 02 03:31:28 PM PDT 24
Peak memory 205760 kb
Host smart-b6572cbe-abe1-4249-bc93-9c6885cfbdb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48623
9762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.486239762
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.3198365047
Short name T440
Test name
Test status
Simulation time 22666625315 ps
CPU time 352.81 seconds
Started Jun 02 03:31:13 PM PDT 24
Finished Jun 02 03:37:07 PM PDT 24
Peak memory 205632 kb
Host smart-6d7c93ae-ab3a-4eca-965f-527fef63f279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31983
65047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.3198365047
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.1180350192
Short name T1985
Test name
Test status
Simulation time 10144983358 ps
CPU time 13.29 seconds
Started Jun 02 03:31:27 PM PDT 24
Finished Jun 02 03:31:41 PM PDT 24
Peak memory 205756 kb
Host smart-67162412-649f-49b9-bb5f-14001386b983
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1180350192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.1180350192
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.539708988
Short name T1789
Test name
Test status
Simulation time 10056334076 ps
CPU time 13.82 seconds
Started Jun 02 03:31:32 PM PDT 24
Finished Jun 02 03:31:47 PM PDT 24
Peak memory 205740 kb
Host smart-4aaccd27-5b2a-449b-a75d-f04a299d0e95
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=539708988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.539708988
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.393670257
Short name T1260
Test name
Test status
Simulation time 10092203160 ps
CPU time 13.72 seconds
Started Jun 02 03:31:21 PM PDT 24
Finished Jun 02 03:31:35 PM PDT 24
Peak memory 205780 kb
Host smart-a38e79df-dcaf-4d63-a090-0bebe85bbbba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39367
0257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.393670257
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.2925396942
Short name T554
Test name
Test status
Simulation time 14088748625 ps
CPU time 16.66 seconds
Started Jun 02 03:31:18 PM PDT 24
Finished Jun 02 03:31:35 PM PDT 24
Peak memory 205768 kb
Host smart-4b37c691-57db-4ea2-9f8e-e59785fc9674
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2925396942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.2925396942
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.3480043508
Short name T652
Test name
Test status
Simulation time 23282265907 ps
CPU time 24.87 seconds
Started Jun 02 03:31:20 PM PDT 24
Finished Jun 02 03:31:45 PM PDT 24
Peak memory 205772 kb
Host smart-4e5a10ce-433e-4d2f-822c-a7b533addd3e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3480043508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.3480043508
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.819685774
Short name T653
Test name
Test status
Simulation time 10057533552 ps
CPU time 15.61 seconds
Started Jun 02 03:31:18 PM PDT 24
Finished Jun 02 03:31:34 PM PDT 24
Peak memory 205760 kb
Host smart-7a4a4f48-3c3b-499d-82cf-8b2bf558de1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81968
5774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.819685774
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.670106108
Short name T1019
Test name
Test status
Simulation time 11277816102 ps
CPU time 16.17 seconds
Started Jun 02 03:31:16 PM PDT 24
Finished Jun 02 03:31:33 PM PDT 24
Peak memory 205636 kb
Host smart-97e24143-5ff2-4abc-8472-a1276995fa9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67010
6108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.670106108
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.2247868727
Short name T1416
Test name
Test status
Simulation time 10070832493 ps
CPU time 14.51 seconds
Started Jun 02 03:31:15 PM PDT 24
Finished Jun 02 03:31:30 PM PDT 24
Peak memory 205636 kb
Host smart-78b70997-ed2a-45ac-aeed-2701fd7d3704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22478
68727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.2247868727
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.326173004
Short name T1876
Test name
Test status
Simulation time 10054156896 ps
CPU time 14.49 seconds
Started Jun 02 03:31:15 PM PDT 24
Finished Jun 02 03:31:30 PM PDT 24
Peak memory 205700 kb
Host smart-5fb882e3-1da7-4403-bd44-34610a7dfaf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32617
3004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.326173004
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.3657496416
Short name T1373
Test name
Test status
Simulation time 10755553894 ps
CPU time 14.56 seconds
Started Jun 02 03:31:17 PM PDT 24
Finished Jun 02 03:31:32 PM PDT 24
Peak memory 205708 kb
Host smart-adfebd48-109d-4970-b229-5cf42172764e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36574
96416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.3657496416
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1317298662
Short name T1995
Test name
Test status
Simulation time 10097657436 ps
CPU time 13.96 seconds
Started Jun 02 03:31:22 PM PDT 24
Finished Jun 02 03:31:37 PM PDT 24
Peak memory 205676 kb
Host smart-cff49d18-4bb3-472e-a35b-0f679828f674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13172
98662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1317298662
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.1857594712
Short name T1161
Test name
Test status
Simulation time 10099138658 ps
CPU time 15.18 seconds
Started Jun 02 03:31:22 PM PDT 24
Finished Jun 02 03:31:38 PM PDT 24
Peak memory 205640 kb
Host smart-df911d75-7bde-4737-a36d-803c9ade47fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18575
94712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.1857594712
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.1311599892
Short name T1613
Test name
Test status
Simulation time 10078226140 ps
CPU time 12.82 seconds
Started Jun 02 03:31:27 PM PDT 24
Finished Jun 02 03:31:41 PM PDT 24
Peak memory 205628 kb
Host smart-62a8c85f-56a1-489b-be0f-bbc863d5203f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13115
99892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.1311599892
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.4023552769
Short name T1689
Test name
Test status
Simulation time 10094565260 ps
CPU time 13.41 seconds
Started Jun 02 03:31:14 PM PDT 24
Finished Jun 02 03:31:28 PM PDT 24
Peak memory 205736 kb
Host smart-1759a453-a129-4efa-a09b-b4e73b7d3475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40235
52769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.4023552769
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.7119751
Short name T787
Test name
Test status
Simulation time 10122794883 ps
CPU time 14.81 seconds
Started Jun 02 03:31:15 PM PDT 24
Finished Jun 02 03:31:30 PM PDT 24
Peak memory 205780 kb
Host smart-df742380-50ec-4ccf-b3b5-2ee47ffc6ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71197
51 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.7119751
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.2805336337
Short name T434
Test name
Test status
Simulation time 13207033824 ps
CPU time 15.24 seconds
Started Jun 02 03:31:19 PM PDT 24
Finished Jun 02 03:31:35 PM PDT 24
Peak memory 205868 kb
Host smart-166476d5-75c7-4fd5-89c2-70e46f967b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28053
36337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.2805336337
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1915163501
Short name T1182
Test name
Test status
Simulation time 10100890537 ps
CPU time 15.24 seconds
Started Jun 02 03:31:17 PM PDT 24
Finished Jun 02 03:31:33 PM PDT 24
Peak memory 205808 kb
Host smart-22832ee1-36b7-45a9-afe6-4a3f60ec4cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19151
63501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1915163501
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.1694606697
Short name T1826
Test name
Test status
Simulation time 22903852527 ps
CPU time 133.63 seconds
Started Jun 02 03:31:17 PM PDT 24
Finished Jun 02 03:33:32 PM PDT 24
Peak memory 205688 kb
Host smart-eb9c3a25-60e5-41f5-a7a8-7ed4449c1532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16946
06697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.1694606697
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.19306638
Short name T1295
Test name
Test status
Simulation time 10036288906 ps
CPU time 15.37 seconds
Started Jun 02 03:31:20 PM PDT 24
Finished Jun 02 03:31:36 PM PDT 24
Peak memory 205620 kb
Host smart-f33bb4e6-3e91-40fd-b6fe-20cf24fdcacc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19306
638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.19306638
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.584091914
Short name T1477
Test name
Test status
Simulation time 10133301752 ps
CPU time 15.15 seconds
Started Jun 02 03:31:20 PM PDT 24
Finished Jun 02 03:31:36 PM PDT 24
Peak memory 205688 kb
Host smart-ded0b648-ffb3-4a75-bdbf-128fd160a6ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58409
1914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.584091914
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.550366630
Short name T750
Test name
Test status
Simulation time 10117613683 ps
CPU time 14.15 seconds
Started Jun 02 03:31:16 PM PDT 24
Finished Jun 02 03:31:31 PM PDT 24
Peak memory 205928 kb
Host smart-4a2471dc-af0c-4254-a611-ee8722ed51e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55036
6630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.550366630
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.2885119667
Short name T1120
Test name
Test status
Simulation time 10060340700 ps
CPU time 14.06 seconds
Started Jun 02 03:31:25 PM PDT 24
Finished Jun 02 03:31:40 PM PDT 24
Peak memory 205760 kb
Host smart-4b0a310c-35c8-4d8a-b233-616df5af0986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28851
19667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.2885119667
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.401210684
Short name T694
Test name
Test status
Simulation time 10074857694 ps
CPU time 12.44 seconds
Started Jun 02 03:31:23 PM PDT 24
Finished Jun 02 03:31:36 PM PDT 24
Peak memory 205704 kb
Host smart-fe34e6a2-fcfe-4dc9-ab0c-788db678eb0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40121
0684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.401210684
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.550035911
Short name T548
Test name
Test status
Simulation time 10054001847 ps
CPU time 12.07 seconds
Started Jun 02 03:31:21 PM PDT 24
Finished Jun 02 03:31:34 PM PDT 24
Peak memory 205600 kb
Host smart-23859690-e52c-4228-b770-e5eec2401c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55003
5911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.550035911
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_eop_single_bit_handling.1917755688
Short name T600
Test name
Test status
Simulation time 10157900205 ps
CPU time 13.39 seconds
Started Jun 02 03:31:22 PM PDT 24
Finished Jun 02 03:31:36 PM PDT 24
Peak memory 205704 kb
Host smart-72bc50b6-a8dd-49e8-9199-ba4053dbe854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19177
55688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_eop_single_bit_handling.1917755688
Directory /workspace/36.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.1375352526
Short name T214
Test name
Test status
Simulation time 10058372723 ps
CPU time 13.11 seconds
Started Jun 02 03:31:24 PM PDT 24
Finished Jun 02 03:31:38 PM PDT 24
Peak memory 205728 kb
Host smart-0f2b8148-d209-4246-9276-3faaf1f65933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13753
52526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.1375352526
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.3007248181
Short name T2008
Test name
Test status
Simulation time 10051287432 ps
CPU time 13.91 seconds
Started Jun 02 03:31:22 PM PDT 24
Finished Jun 02 03:31:37 PM PDT 24
Peak memory 205976 kb
Host smart-a6e9881b-b691-4bd2-a221-14dc3a1e5296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30072
48181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.3007248181
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3121317558
Short name T1974
Test name
Test status
Simulation time 18466532048 ps
CPU time 32.56 seconds
Started Jun 02 03:31:27 PM PDT 24
Finished Jun 02 03:32:01 PM PDT 24
Peak memory 205660 kb
Host smart-c8355187-5c7d-4db5-9ec4-4e88a4ffbac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31213
17558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3121317558
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.4263796747
Short name T647
Test name
Test status
Simulation time 10073244650 ps
CPU time 13.98 seconds
Started Jun 02 03:31:29 PM PDT 24
Finished Jun 02 03:31:43 PM PDT 24
Peak memory 205652 kb
Host smart-d30ddabe-6e3c-4785-98df-e268285e5db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42637
96747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.4263796747
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.2809299437
Short name T402
Test name
Test status
Simulation time 10164203141 ps
CPU time 14 seconds
Started Jun 02 03:31:21 PM PDT 24
Finished Jun 02 03:31:36 PM PDT 24
Peak memory 205768 kb
Host smart-10f962f3-00f0-4b8b-8030-0f9457920480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28092
99437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.2809299437
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.1336116357
Short name T423
Test name
Test status
Simulation time 10059512060 ps
CPU time 14.45 seconds
Started Jun 02 03:31:22 PM PDT 24
Finished Jun 02 03:31:37 PM PDT 24
Peak memory 205604 kb
Host smart-5cc97833-c8e0-4ac6-9922-f8008c2bd67f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13361
16357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.1336116357
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.3884837031
Short name T435
Test name
Test status
Simulation time 10033374524 ps
CPU time 13.7 seconds
Started Jun 02 03:31:20 PM PDT 24
Finished Jun 02 03:31:34 PM PDT 24
Peak memory 205740 kb
Host smart-c3e7f332-9a39-4eba-962a-971f4790c728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38848
37031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.3884837031
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.2572537762
Short name T1705
Test name
Test status
Simulation time 10087897060 ps
CPU time 14.42 seconds
Started Jun 02 03:31:20 PM PDT 24
Finished Jun 02 03:31:35 PM PDT 24
Peak memory 205660 kb
Host smart-13a90488-1685-4af0-b83a-5a165eb1ce57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25725
37762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.2572537762
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3524568661
Short name T39
Test name
Test status
Simulation time 10045800198 ps
CPU time 12.56 seconds
Started Jun 02 03:31:21 PM PDT 24
Finished Jun 02 03:31:35 PM PDT 24
Peak memory 205660 kb
Host smart-42dad324-a246-4f93-8b3c-c4b7e2907c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35245
68661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3524568661
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.1414846988
Short name T1824
Test name
Test status
Simulation time 10126897844 ps
CPU time 16.24 seconds
Started Jun 02 03:31:12 PM PDT 24
Finished Jun 02 03:31:29 PM PDT 24
Peak memory 205612 kb
Host smart-3ea42aee-ce92-4d10-8d44-5cc39499f2b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14148
46988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.1414846988
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.2847868082
Short name T367
Test name
Test status
Simulation time 10088774895 ps
CPU time 14.7 seconds
Started Jun 02 03:31:21 PM PDT 24
Finished Jun 02 03:31:36 PM PDT 24
Peak memory 205688 kb
Host smart-5ad4d1a3-6965-4687-adaf-fa2eec54efd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28478
68082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.2847868082
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.2649454973
Short name T1591
Test name
Test status
Simulation time 10057944952 ps
CPU time 16.34 seconds
Started Jun 02 03:31:23 PM PDT 24
Finished Jun 02 03:31:40 PM PDT 24
Peak memory 205664 kb
Host smart-63c6e4ac-2fec-4426-9687-3f3dda38446b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26494
54973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.2649454973
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.716502060
Short name T1291
Test name
Test status
Simulation time 23693556199 ps
CPU time 389.67 seconds
Started Jun 02 03:31:20 PM PDT 24
Finished Jun 02 03:37:50 PM PDT 24
Peak memory 205616 kb
Host smart-c4a463d0-c47d-4897-83c4-8ca0ee4cad24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71650
2060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.716502060
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.2535204708
Short name T1715
Test name
Test status
Simulation time 10149037312 ps
CPU time 14.88 seconds
Started Jun 02 03:31:28 PM PDT 24
Finished Jun 02 03:31:44 PM PDT 24
Peak memory 205620 kb
Host smart-b26aeb99-5dfb-421c-a536-789499646a64
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2535204708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.2535204708
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.421268885
Short name T1225
Test name
Test status
Simulation time 10053395315 ps
CPU time 13.44 seconds
Started Jun 02 03:31:30 PM PDT 24
Finished Jun 02 03:31:44 PM PDT 24
Peak memory 205624 kb
Host smart-5585fdaf-d9fc-4acb-80c0-7b84d8c2b386
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=421268885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.421268885
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.1648582515
Short name T973
Test name
Test status
Simulation time 10100230080 ps
CPU time 15.32 seconds
Started Jun 02 03:31:31 PM PDT 24
Finished Jun 02 03:31:47 PM PDT 24
Peak memory 205648 kb
Host smart-ae990296-7d96-4a22-b01d-1f846b326a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16485
82515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.1648582515
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.3682320741
Short name T1623
Test name
Test status
Simulation time 13739049195 ps
CPU time 16.34 seconds
Started Jun 02 03:31:24 PM PDT 24
Finished Jun 02 03:31:40 PM PDT 24
Peak memory 205800 kb
Host smart-1a67252b-3b59-4934-ae9f-38288f1467c3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3682320741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.3682320741
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.2139318819
Short name T9
Test name
Test status
Simulation time 23270388748 ps
CPU time 24.78 seconds
Started Jun 02 03:31:22 PM PDT 24
Finished Jun 02 03:31:48 PM PDT 24
Peak memory 205680 kb
Host smart-6ed5c1b4-d04e-4c78-8e03-3535f2fd5d66
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2139318819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.2139318819
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.1894388714
Short name T1351
Test name
Test status
Simulation time 10055983617 ps
CPU time 14.14 seconds
Started Jun 02 03:31:32 PM PDT 24
Finished Jun 02 03:31:47 PM PDT 24
Peak memory 205676 kb
Host smart-086d603d-0567-48f8-bd61-ae795859ca4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18943
88714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.1894388714
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.3754316613
Short name T1890
Test name
Test status
Simulation time 10234232742 ps
CPU time 14.51 seconds
Started Jun 02 03:31:30 PM PDT 24
Finished Jun 02 03:31:45 PM PDT 24
Peak memory 205684 kb
Host smart-69e3033d-e49d-4e9d-ba27-a37dd31f63e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37543
16613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.3754316613
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.1424186939
Short name T735
Test name
Test status
Simulation time 10079649073 ps
CPU time 13.04 seconds
Started Jun 02 03:31:26 PM PDT 24
Finished Jun 02 03:31:40 PM PDT 24
Peak memory 205688 kb
Host smart-f1628bac-d337-48f3-8b13-02470eb3333d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14241
86939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.1424186939
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.1339423235
Short name T1931
Test name
Test status
Simulation time 10052313686 ps
CPU time 12.55 seconds
Started Jun 02 03:31:31 PM PDT 24
Finished Jun 02 03:31:45 PM PDT 24
Peak memory 205604 kb
Host smart-b4324b09-e9f2-456b-9bea-034c0ac3e0ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13394
23235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.1339423235
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.3988270358
Short name T1078
Test name
Test status
Simulation time 10755955280 ps
CPU time 15.74 seconds
Started Jun 02 03:31:26 PM PDT 24
Finished Jun 02 03:31:42 PM PDT 24
Peak memory 205712 kb
Host smart-d0b4602f-948d-4ea3-8abe-52436a454eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39882
70358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.3988270358
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3846829198
Short name T998
Test name
Test status
Simulation time 10240779331 ps
CPU time 17.86 seconds
Started Jun 02 03:31:26 PM PDT 24
Finished Jun 02 03:31:45 PM PDT 24
Peak memory 205748 kb
Host smart-560b390a-40d1-45cd-99d2-60d1b2f7d65c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38468
29198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3846829198
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.1656732426
Short name T1201
Test name
Test status
Simulation time 10114107307 ps
CPU time 13.65 seconds
Started Jun 02 03:31:31 PM PDT 24
Finished Jun 02 03:31:46 PM PDT 24
Peak memory 205756 kb
Host smart-1cf665c0-a9ed-45a6-904f-b5de2fb3b8e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16567
32426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.1656732426
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.1165692907
Short name T1169
Test name
Test status
Simulation time 10064793142 ps
CPU time 12.99 seconds
Started Jun 02 03:31:45 PM PDT 24
Finished Jun 02 03:31:59 PM PDT 24
Peak memory 205776 kb
Host smart-ebace92e-5133-44a2-823a-822d7b36c07d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11656
92907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.1165692907
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3358795925
Short name T1994
Test name
Test status
Simulation time 10058717196 ps
CPU time 13.19 seconds
Started Jun 02 03:31:28 PM PDT 24
Finished Jun 02 03:31:42 PM PDT 24
Peak memory 205624 kb
Host smart-6d80bab2-8ee9-4878-bf97-70905b9d0a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33587
95925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3358795925
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.3807275441
Short name T1419
Test name
Test status
Simulation time 10110980093 ps
CPU time 13.21 seconds
Started Jun 02 03:31:27 PM PDT 24
Finished Jun 02 03:31:41 PM PDT 24
Peak memory 205720 kb
Host smart-514e5fd1-cb16-40ff-a687-3d674f25de0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38072
75441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.3807275441
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.799560030
Short name T820
Test name
Test status
Simulation time 13304571382 ps
CPU time 17.45 seconds
Started Jun 02 03:31:25 PM PDT 24
Finished Jun 02 03:31:43 PM PDT 24
Peak memory 206012 kb
Host smart-74b1b83c-8f22-485b-bcdb-4dec9a7d49d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79956
0030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.799560030
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.2334935673
Short name T1103
Test name
Test status
Simulation time 10141629071 ps
CPU time 15.06 seconds
Started Jun 02 03:31:24 PM PDT 24
Finished Jun 02 03:31:39 PM PDT 24
Peak memory 205724 kb
Host smart-6ac3c7b9-b7d1-4a8f-8885-571256c1c356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23349
35673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.2334935673
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.1548328755
Short name T657
Test name
Test status
Simulation time 24992460105 ps
CPU time 161.58 seconds
Started Jun 02 03:31:27 PM PDT 24
Finished Jun 02 03:34:10 PM PDT 24
Peak memory 205584 kb
Host smart-7df2120b-26bc-44a7-b7ff-2617fb9fedb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15483
28755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.1548328755
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.3133581819
Short name T1131
Test name
Test status
Simulation time 10068757365 ps
CPU time 14.84 seconds
Started Jun 02 03:31:26 PM PDT 24
Finished Jun 02 03:31:42 PM PDT 24
Peak memory 205748 kb
Host smart-ee039a9f-802c-4e5f-adc3-3d458a0391d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31335
81819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.3133581819
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.202823021
Short name T125
Test name
Test status
Simulation time 10062459195 ps
CPU time 14.73 seconds
Started Jun 02 03:31:26 PM PDT 24
Finished Jun 02 03:31:42 PM PDT 24
Peak memory 205784 kb
Host smart-026384e8-3bdd-414d-8b79-a0d105f27b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20282
3021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.202823021
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.1360703163
Short name T926
Test name
Test status
Simulation time 10042975567 ps
CPU time 14.63 seconds
Started Jun 02 03:31:30 PM PDT 24
Finished Jun 02 03:31:46 PM PDT 24
Peak memory 205784 kb
Host smart-023cd8f3-5cb3-4730-be73-ae5140c773f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13607
03163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.1360703163
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.3600585834
Short name T556
Test name
Test status
Simulation time 10079930836 ps
CPU time 12.8 seconds
Started Jun 02 03:31:31 PM PDT 24
Finished Jun 02 03:31:45 PM PDT 24
Peak memory 205708 kb
Host smart-61958207-f1c4-40cb-85ae-c10a9c22da65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36005
85834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3600585834
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2418901508
Short name T738
Test name
Test status
Simulation time 10087634697 ps
CPU time 14.13 seconds
Started Jun 02 03:31:25 PM PDT 24
Finished Jun 02 03:31:39 PM PDT 24
Peak memory 205748 kb
Host smart-d2f23f8f-343b-4953-97ea-3e656d7cca4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24189
01508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2418901508
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.2407185957
Short name T151
Test name
Test status
Simulation time 10066240525 ps
CPU time 13.38 seconds
Started Jun 02 03:31:29 PM PDT 24
Finished Jun 02 03:31:43 PM PDT 24
Peak memory 205744 kb
Host smart-98b947f8-9a87-44b7-9d86-d99e4d1c5e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24071
85957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.2407185957
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_eop_single_bit_handling.739324885
Short name T1480
Test name
Test status
Simulation time 10065834647 ps
CPU time 13.58 seconds
Started Jun 02 03:31:27 PM PDT 24
Finished Jun 02 03:31:42 PM PDT 24
Peak memory 205596 kb
Host smart-aeab5258-4b68-4064-b7f2-570c35119b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73932
4885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_eop_single_bit_handling.739324885
Directory /workspace/37.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3972220840
Short name T1706
Test name
Test status
Simulation time 10052263593 ps
CPU time 13.56 seconds
Started Jun 02 03:31:45 PM PDT 24
Finished Jun 02 03:31:59 PM PDT 24
Peak memory 205768 kb
Host smart-6181a8a6-e8ce-4794-b83b-dd91ea48de44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39722
20840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3972220840
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.993484884
Short name T752
Test name
Test status
Simulation time 10035626218 ps
CPU time 13.32 seconds
Started Jun 02 03:31:30 PM PDT 24
Finished Jun 02 03:31:44 PM PDT 24
Peak memory 205608 kb
Host smart-f780f563-97c6-4a5a-b96c-0af10a6bf22f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99348
4884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.993484884
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.985238244
Short name T718
Test name
Test status
Simulation time 23358907284 ps
CPU time 42.85 seconds
Started Jun 02 03:31:27 PM PDT 24
Finished Jun 02 03:32:11 PM PDT 24
Peak memory 205680 kb
Host smart-374b8cfb-bbe9-44ae-8ed9-acfaede0b904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98523
8244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.985238244
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.2982756788
Short name T898
Test name
Test status
Simulation time 10107576584 ps
CPU time 13.72 seconds
Started Jun 02 03:31:27 PM PDT 24
Finished Jun 02 03:31:42 PM PDT 24
Peak memory 205592 kb
Host smart-dece8f90-0281-4106-9d53-712e354221fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29827
56788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2982756788
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.3211600180
Short name T1868
Test name
Test status
Simulation time 10076031561 ps
CPU time 12.58 seconds
Started Jun 02 03:31:44 PM PDT 24
Finished Jun 02 03:31:57 PM PDT 24
Peak memory 205696 kb
Host smart-8d9f5482-6747-47c8-9354-f463814a4c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32116
00180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.3211600180
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.2790655681
Short name T470
Test name
Test status
Simulation time 10069872385 ps
CPU time 13.65 seconds
Started Jun 02 03:31:24 PM PDT 24
Finished Jun 02 03:31:38 PM PDT 24
Peak memory 205692 kb
Host smart-1483c68a-8ee1-469c-a716-ad2d1a6ea701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27906
55681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.2790655681
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.69357111
Short name T374
Test name
Test status
Simulation time 10040676432 ps
CPU time 13.93 seconds
Started Jun 02 03:31:27 PM PDT 24
Finished Jun 02 03:31:42 PM PDT 24
Peak memory 205792 kb
Host smart-f10169e1-9663-4d54-9379-2c825520b5c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69357
111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.69357111
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.1052185963
Short name T1765
Test name
Test status
Simulation time 10048642866 ps
CPU time 14.97 seconds
Started Jun 02 03:31:26 PM PDT 24
Finished Jun 02 03:31:42 PM PDT 24
Peak memory 205672 kb
Host smart-142b8056-2ba4-46f2-9d45-b61a027d6331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10521
85963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.1052185963
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.1089045995
Short name T1895
Test name
Test status
Simulation time 10056238247 ps
CPU time 15.02 seconds
Started Jun 02 03:31:27 PM PDT 24
Finished Jun 02 03:31:44 PM PDT 24
Peak memory 205588 kb
Host smart-734bb64e-0e3f-47b7-911b-97ef3a782768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10890
45995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.1089045995
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.3113592954
Short name T741
Test name
Test status
Simulation time 10110603689 ps
CPU time 16.06 seconds
Started Jun 02 03:31:25 PM PDT 24
Finished Jun 02 03:31:42 PM PDT 24
Peak memory 205660 kb
Host smart-245c7328-9c2d-41da-9c39-d5a41b68f2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31135
92954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3113592954
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.3313815932
Short name T655
Test name
Test status
Simulation time 10041566603 ps
CPU time 13.49 seconds
Started Jun 02 03:31:27 PM PDT 24
Finished Jun 02 03:31:41 PM PDT 24
Peak memory 205640 kb
Host smart-fa7646d9-5132-4866-ac52-6fbc8cf2ae8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33138
15932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.3313815932
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.2500309323
Short name T1194
Test name
Test status
Simulation time 10085441512 ps
CPU time 14.97 seconds
Started Jun 02 03:31:27 PM PDT 24
Finished Jun 02 03:31:43 PM PDT 24
Peak memory 205560 kb
Host smart-300580ec-a90e-4042-80f5-f514fd63e134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25003
09323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.2500309323
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.2226468861
Short name T1253
Test name
Test status
Simulation time 24511950610 ps
CPU time 146.22 seconds
Started Jun 02 03:31:28 PM PDT 24
Finished Jun 02 03:33:55 PM PDT 24
Peak memory 205720 kb
Host smart-0c0d8e5f-9aa7-4dfb-99e0-9576376cefa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22264
68861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.2226468861
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.1275834624
Short name T1175
Test name
Test status
Simulation time 10140169377 ps
CPU time 15.9 seconds
Started Jun 02 03:31:35 PM PDT 24
Finished Jun 02 03:31:51 PM PDT 24
Peak memory 205772 kb
Host smart-0ef03cb3-a6af-4d5a-8206-510ecf5edd6a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1275834624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.1275834624
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.2801918070
Short name T292
Test name
Test status
Simulation time 10069785208 ps
CPU time 13.65 seconds
Started Jun 02 03:31:37 PM PDT 24
Finished Jun 02 03:31:51 PM PDT 24
Peak memory 205688 kb
Host smart-4fbed984-d796-48e2-84e2-c883925a8ef6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2801918070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.2801918070
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.2957282378
Short name T1921
Test name
Test status
Simulation time 10070381648 ps
CPU time 14.61 seconds
Started Jun 02 03:31:37 PM PDT 24
Finished Jun 02 03:31:52 PM PDT 24
Peak memory 205744 kb
Host smart-6c54467e-59d2-49ff-87fc-1c156f0be73d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29572
82378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.2957282378
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.828831055
Short name T681
Test name
Test status
Simulation time 14249920070 ps
CPU time 18.49 seconds
Started Jun 02 03:31:30 PM PDT 24
Finished Jun 02 03:31:50 PM PDT 24
Peak memory 205712 kb
Host smart-8f5412e2-7401-4d70-98a5-1ea111a47ee9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=828831055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.828831055
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.1770599976
Short name T1147
Test name
Test status
Simulation time 23244072124 ps
CPU time 26.9 seconds
Started Jun 02 03:31:32 PM PDT 24
Finished Jun 02 03:32:00 PM PDT 24
Peak memory 205708 kb
Host smart-9194d0d7-2c82-4514-98d6-7525fd101710
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1770599976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.1770599976
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.1651895158
Short name T1842
Test name
Test status
Simulation time 10068166111 ps
CPU time 13.16 seconds
Started Jun 02 03:31:31 PM PDT 24
Finished Jun 02 03:31:45 PM PDT 24
Peak memory 205764 kb
Host smart-3e6c3b13-102b-4912-af27-8d9ffc2b3ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16518
95158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.1651895158
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.961317514
Short name T551
Test name
Test status
Simulation time 10280700181 ps
CPU time 14.54 seconds
Started Jun 02 03:31:32 PM PDT 24
Finished Jun 02 03:31:47 PM PDT 24
Peak memory 205724 kb
Host smart-1a375d06-6f69-477b-8725-a740b48dd597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96131
7514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.961317514
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_enable.91081650
Short name T617
Test name
Test status
Simulation time 10051192424 ps
CPU time 13.67 seconds
Started Jun 02 03:31:30 PM PDT 24
Finished Jun 02 03:31:44 PM PDT 24
Peak memory 205672 kb
Host smart-b4969eee-d2f3-4fe1-84a9-c4327a073940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91081
650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.91081650
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.3844540717
Short name T1667
Test name
Test status
Simulation time 10931500120 ps
CPU time 14.97 seconds
Started Jun 02 03:31:31 PM PDT 24
Finished Jun 02 03:31:47 PM PDT 24
Peak memory 205780 kb
Host smart-4da745c0-47f7-47f7-be4e-5515c8671fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38445
40717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.3844540717
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.3825604245
Short name T415
Test name
Test status
Simulation time 10211428246 ps
CPU time 14.82 seconds
Started Jun 02 03:31:31 PM PDT 24
Finished Jun 02 03:31:47 PM PDT 24
Peak memory 205756 kb
Host smart-b9375da4-5d0b-4d07-a2bf-c447325f63e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38256
04245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.3825604245
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2770226246
Short name T1065
Test name
Test status
Simulation time 10089243706 ps
CPU time 12.7 seconds
Started Jun 02 03:31:39 PM PDT 24
Finished Jun 02 03:31:52 PM PDT 24
Peak memory 205700 kb
Host smart-8ac4b4c8-8ceb-4155-9c33-229cb4c63329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27702
26246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2770226246
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.605331379
Short name T1274
Test name
Test status
Simulation time 10057436200 ps
CPU time 12.8 seconds
Started Jun 02 03:31:35 PM PDT 24
Finished Jun 02 03:31:48 PM PDT 24
Peak memory 205652 kb
Host smart-360a2a76-fc8d-4988-9bff-232822e02a0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60533
1379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.605331379
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.753223951
Short name T356
Test name
Test status
Simulation time 10092659291 ps
CPU time 15.47 seconds
Started Jun 02 03:31:32 PM PDT 24
Finished Jun 02 03:31:49 PM PDT 24
Peak memory 205728 kb
Host smart-092b1d82-d71b-403b-963e-4b52647741f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75322
3951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.753223951
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.2020489719
Short name T991
Test name
Test status
Simulation time 10140491934 ps
CPU time 13.89 seconds
Started Jun 02 03:31:29 PM PDT 24
Finished Jun 02 03:31:43 PM PDT 24
Peak memory 205772 kb
Host smart-5b8d1567-4073-44eb-bd73-a26f18137797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20204
89719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.2020489719
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.2280152064
Short name T844
Test name
Test status
Simulation time 13235183900 ps
CPU time 16.46 seconds
Started Jun 02 03:31:43 PM PDT 24
Finished Jun 02 03:32:00 PM PDT 24
Peak memory 205664 kb
Host smart-81028ea3-33da-42a1-b6ac-890f6d2135ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22801
52064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.2280152064
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1758324683
Short name T211
Test name
Test status
Simulation time 10116644406 ps
CPU time 15.06 seconds
Started Jun 02 03:31:32 PM PDT 24
Finished Jun 02 03:31:48 PM PDT 24
Peak memory 205728 kb
Host smart-8988d1dc-0845-4493-8736-fd1ec276567b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17583
24683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1758324683
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.1929669693
Short name T1084
Test name
Test status
Simulation time 22185133784 ps
CPU time 350.35 seconds
Started Jun 02 03:31:33 PM PDT 24
Finished Jun 02 03:37:24 PM PDT 24
Peak memory 205596 kb
Host smart-ebf7b472-2b89-4b81-b42a-f45e1f3b277e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19296
69693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.1929669693
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.1204783545
Short name T1053
Test name
Test status
Simulation time 10097368961 ps
CPU time 12.29 seconds
Started Jun 02 03:31:40 PM PDT 24
Finished Jun 02 03:31:53 PM PDT 24
Peak memory 205740 kb
Host smart-854a9a11-d5b3-416a-9d5d-b32f60c54b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12047
83545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1204783545
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.3385933174
Short name T127
Test name
Test status
Simulation time 10105250372 ps
CPU time 12.81 seconds
Started Jun 02 03:31:39 PM PDT 24
Finished Jun 02 03:31:52 PM PDT 24
Peak memory 205764 kb
Host smart-d886d759-2091-4354-8e12-acd4940b6508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33859
33174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3385933174
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.2281654668
Short name T795
Test name
Test status
Simulation time 10083261164 ps
CPU time 14.84 seconds
Started Jun 02 03:31:31 PM PDT 24
Finished Jun 02 03:31:47 PM PDT 24
Peak memory 205664 kb
Host smart-c938dac0-6282-41c2-98b3-01de5aa7c912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22816
54668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.2281654668
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.3600631728
Short name T420
Test name
Test status
Simulation time 10053808531 ps
CPU time 13.18 seconds
Started Jun 02 03:31:43 PM PDT 24
Finished Jun 02 03:31:57 PM PDT 24
Peak memory 205692 kb
Host smart-3453a600-6af0-4bb1-9dbd-bea05ff09e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36006
31728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3600631728
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.2782226465
Short name T1562
Test name
Test status
Simulation time 10088196821 ps
CPU time 13.75 seconds
Started Jun 02 03:31:31 PM PDT 24
Finished Jun 02 03:31:45 PM PDT 24
Peak memory 205736 kb
Host smart-ca448245-cf3d-455b-a743-e6577f420fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27822
26465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.2782226465
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.3120047278
Short name T20
Test name
Test status
Simulation time 10096343515 ps
CPU time 12.7 seconds
Started Jun 02 03:31:38 PM PDT 24
Finished Jun 02 03:31:51 PM PDT 24
Peak memory 205788 kb
Host smart-406c489b-919d-4793-92ac-86ac87a41f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31200
47278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.3120047278
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_eop_single_bit_handling.3238628889
Short name T1457
Test name
Test status
Simulation time 10105412929 ps
CPU time 13.64 seconds
Started Jun 02 03:31:33 PM PDT 24
Finished Jun 02 03:31:47 PM PDT 24
Peak memory 205708 kb
Host smart-9d48e0fc-c1c3-40ab-888b-e7e1c03b296f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32386
28889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_eop_single_bit_handling.3238628889
Directory /workspace/38.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3015844905
Short name T862
Test name
Test status
Simulation time 10039089811 ps
CPU time 14.96 seconds
Started Jun 02 03:31:31 PM PDT 24
Finished Jun 02 03:31:47 PM PDT 24
Peak memory 205756 kb
Host smart-e1c2858c-8ba1-4d1d-a6fa-ba50faed31bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30158
44905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3015844905
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1547100162
Short name T2014
Test name
Test status
Simulation time 10073004247 ps
CPU time 15.47 seconds
Started Jun 02 03:31:38 PM PDT 24
Finished Jun 02 03:31:54 PM PDT 24
Peak memory 205780 kb
Host smart-3dc388cf-a663-4403-b599-d4a6df4006a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15471
00162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1547100162
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1838431935
Short name T1240
Test name
Test status
Simulation time 17907228544 ps
CPU time 34.03 seconds
Started Jun 02 03:31:43 PM PDT 24
Finished Jun 02 03:32:18 PM PDT 24
Peak memory 205688 kb
Host smart-9efb6a01-44cf-4e0b-8a63-24e45afa63ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18384
31935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1838431935
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.3737527930
Short name T344
Test name
Test status
Simulation time 10090217458 ps
CPU time 14.58 seconds
Started Jun 02 03:31:30 PM PDT 24
Finished Jun 02 03:31:45 PM PDT 24
Peak memory 205640 kb
Host smart-67b2a63d-6122-444b-a3e9-60d54b734d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37375
27930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3737527930
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.217768500
Short name T884
Test name
Test status
Simulation time 10181551614 ps
CPU time 13.76 seconds
Started Jun 02 03:31:31 PM PDT 24
Finished Jun 02 03:31:45 PM PDT 24
Peak memory 205672 kb
Host smart-fb25e08a-a699-41b6-a756-855af35542b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21776
8500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.217768500
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.484115342
Short name T1062
Test name
Test status
Simulation time 10078764472 ps
CPU time 13.59 seconds
Started Jun 02 03:31:39 PM PDT 24
Finished Jun 02 03:31:53 PM PDT 24
Peak memory 205684 kb
Host smart-942bef69-8fba-4ce0-aa3e-be662dfb486f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48411
5342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.484115342
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.2588356001
Short name T953
Test name
Test status
Simulation time 10062258637 ps
CPU time 12.99 seconds
Started Jun 02 03:31:33 PM PDT 24
Finished Jun 02 03:31:46 PM PDT 24
Peak memory 205676 kb
Host smart-6d4aec08-74ea-487e-9d00-c5805add7527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25883
56001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.2588356001
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.2641394188
Short name T1272
Test name
Test status
Simulation time 10055248074 ps
CPU time 13.48 seconds
Started Jun 02 03:31:40 PM PDT 24
Finished Jun 02 03:31:54 PM PDT 24
Peak memory 205764 kb
Host smart-49e76fa2-facf-4824-ad6a-0ab800f7cb03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26413
94188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.2641394188
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.3405031317
Short name T1575
Test name
Test status
Simulation time 10084083712 ps
CPU time 14.65 seconds
Started Jun 02 03:31:33 PM PDT 24
Finished Jun 02 03:31:48 PM PDT 24
Peak memory 205556 kb
Host smart-7aada7c5-3d51-426b-965b-4fb7c16ce2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34050
31317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.3405031317
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.4062141949
Short name T1612
Test name
Test status
Simulation time 10119421987 ps
CPU time 14.11 seconds
Started Jun 02 03:31:31 PM PDT 24
Finished Jun 02 03:31:46 PM PDT 24
Peak memory 205752 kb
Host smart-7bf910c9-2320-43c1-95e3-888467c19327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40621
41949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.4062141949
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2633566704
Short name T586
Test name
Test status
Simulation time 10078577249 ps
CPU time 13.55 seconds
Started Jun 02 03:31:45 PM PDT 24
Finished Jun 02 03:31:59 PM PDT 24
Peak memory 205780 kb
Host smart-b2783477-6018-4143-b63f-32970de8b745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26335
66704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2633566704
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.3780810780
Short name T507
Test name
Test status
Simulation time 10109302790 ps
CPU time 13.97 seconds
Started Jun 02 03:31:33 PM PDT 24
Finished Jun 02 03:31:48 PM PDT 24
Peak memory 205672 kb
Host smart-0caba269-bf77-43c4-b9ce-070977410b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37808
10780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.3780810780
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.1264822955
Short name T616
Test name
Test status
Simulation time 24111256708 ps
CPU time 109.41 seconds
Started Jun 02 03:31:31 PM PDT 24
Finished Jun 02 03:33:21 PM PDT 24
Peak memory 205660 kb
Host smart-f92581f9-929a-4f06-9370-67c301d70a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12648
22955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.1264822955
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.1604130572
Short name T1033
Test name
Test status
Simulation time 10137970546 ps
CPU time 14.39 seconds
Started Jun 02 03:31:42 PM PDT 24
Finished Jun 02 03:31:57 PM PDT 24
Peak memory 205748 kb
Host smart-463590f6-5b87-4992-ad0d-2dc07f5bfb08
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1604130572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.1604130572
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.4099737310
Short name T388
Test name
Test status
Simulation time 10070977142 ps
CPU time 14.08 seconds
Started Jun 02 03:31:38 PM PDT 24
Finished Jun 02 03:31:52 PM PDT 24
Peak memory 205740 kb
Host smart-4be5a441-87c3-40b3-9251-49a0aaea6cde
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4099737310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.4099737310
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.3911423690
Short name T1241
Test name
Test status
Simulation time 10100527965 ps
CPU time 13.79 seconds
Started Jun 02 03:31:40 PM PDT 24
Finished Jun 02 03:31:55 PM PDT 24
Peak memory 205700 kb
Host smart-0e928879-5de9-4dbd-b38a-561acc04471b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39114
23690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.3911423690
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.2801522329
Short name T12
Test name
Test status
Simulation time 13743563107 ps
CPU time 20.75 seconds
Started Jun 02 03:31:34 PM PDT 24
Finished Jun 02 03:31:55 PM PDT 24
Peak memory 205784 kb
Host smart-5c3324e0-f200-4827-afc6-f54d611bad59
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2801522329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.2801522329
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.784515720
Short name T1164
Test name
Test status
Simulation time 23286182012 ps
CPU time 26.02 seconds
Started Jun 02 03:31:39 PM PDT 24
Finished Jun 02 03:32:06 PM PDT 24
Peak memory 205680 kb
Host smart-611f589c-d3c1-4119-b0a3-a44f4e8598fb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=784515720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.784515720
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.21632425
Short name T302
Test name
Test status
Simulation time 10062489983 ps
CPU time 14.18 seconds
Started Jun 02 03:31:35 PM PDT 24
Finished Jun 02 03:31:50 PM PDT 24
Peak memory 205716 kb
Host smart-0b8888e0-09e8-4145-9f26-85e309eaabf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21632
425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.21632425
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.563669184
Short name T392
Test name
Test status
Simulation time 10046181113 ps
CPU time 14.29 seconds
Started Jun 02 03:31:40 PM PDT 24
Finished Jun 02 03:31:55 PM PDT 24
Peak memory 205560 kb
Host smart-9d0c41c9-7873-4615-bc6b-82de06967ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56366
9184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.563669184
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.1670626840
Short name T637
Test name
Test status
Simulation time 10057114522 ps
CPU time 16.44 seconds
Started Jun 02 03:31:38 PM PDT 24
Finished Jun 02 03:31:55 PM PDT 24
Peak memory 205588 kb
Host smart-8a33ddf5-8d52-4cc2-b2ea-c2ab1c376d50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16706
26840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.1670626840
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.3615758071
Short name T299
Test name
Test status
Simulation time 10711197849 ps
CPU time 16.38 seconds
Started Jun 02 03:31:41 PM PDT 24
Finished Jun 02 03:31:58 PM PDT 24
Peak memory 205704 kb
Host smart-00a62ee3-0c11-4613-adf1-e405e56a00a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36157
58071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.3615758071
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3846890576
Short name T659
Test name
Test status
Simulation time 10339569245 ps
CPU time 16.95 seconds
Started Jun 02 03:31:35 PM PDT 24
Finished Jun 02 03:31:53 PM PDT 24
Peak memory 205708 kb
Host smart-e2583022-4f35-4ab1-a132-943635ceb34a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38468
90576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3846890576
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.3114097644
Short name T1873
Test name
Test status
Simulation time 10104218597 ps
CPU time 13.49 seconds
Started Jun 02 03:31:39 PM PDT 24
Finished Jun 02 03:31:54 PM PDT 24
Peak memory 205660 kb
Host smart-52afaace-7d07-4675-a552-badf5d6abc69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31140
97644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.3114097644
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2773299462
Short name T1785
Test name
Test status
Simulation time 10053373292 ps
CPU time 12.92 seconds
Started Jun 02 03:31:42 PM PDT 24
Finished Jun 02 03:31:56 PM PDT 24
Peak memory 205720 kb
Host smart-24a478fe-6aa3-434c-92fb-ec00ec1b45d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27732
99462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2773299462
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3550549389
Short name T1195
Test name
Test status
Simulation time 10144099210 ps
CPU time 14.39 seconds
Started Jun 02 03:31:34 PM PDT 24
Finished Jun 02 03:31:49 PM PDT 24
Peak memory 205684 kb
Host smart-43bed72e-22d4-4d5f-8234-ef647354d1ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35505
49389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3550549389
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.2475888678
Short name T32
Test name
Test status
Simulation time 10155353061 ps
CPU time 14.01 seconds
Started Jun 02 03:31:34 PM PDT 24
Finished Jun 02 03:31:49 PM PDT 24
Peak memory 205612 kb
Host smart-924cfa40-0d9a-4d4f-8419-2742158b15a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24758
88678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.2475888678
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.2593937098
Short name T638
Test name
Test status
Simulation time 13187039300 ps
CPU time 20.85 seconds
Started Jun 02 03:31:34 PM PDT 24
Finished Jun 02 03:31:56 PM PDT 24
Peak memory 205724 kb
Host smart-820e8757-ae43-47e5-9771-85a7e22cca73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25939
37098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.2593937098
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.3841877536
Short name T980
Test name
Test status
Simulation time 10115786927 ps
CPU time 13.11 seconds
Started Jun 02 03:31:41 PM PDT 24
Finished Jun 02 03:31:56 PM PDT 24
Peak memory 205660 kb
Host smart-1464fa8a-6487-4c42-8cb3-561f73414766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38418
77536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.3841877536
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.1725804930
Short name T1252
Test name
Test status
Simulation time 14934643682 ps
CPU time 53.11 seconds
Started Jun 02 03:31:38 PM PDT 24
Finished Jun 02 03:32:32 PM PDT 24
Peak memory 205952 kb
Host smart-1f8b5ead-b0c8-43c5-bd53-17b69b437b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17258
04930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.1725804930
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.847824981
Short name T2000
Test name
Test status
Simulation time 10051433859 ps
CPU time 16.18 seconds
Started Jun 02 03:31:37 PM PDT 24
Finished Jun 02 03:31:54 PM PDT 24
Peak memory 205652 kb
Host smart-ac01f361-a3da-4ef8-ba8b-a5fdb4b31f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84782
4981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.847824981
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.398601214
Short name T121
Test name
Test status
Simulation time 10086588286 ps
CPU time 14.28 seconds
Started Jun 02 03:31:41 PM PDT 24
Finished Jun 02 03:31:56 PM PDT 24
Peak memory 205672 kb
Host smart-20345730-8aa2-4c28-88a8-fe22ee091e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39860
1214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.398601214
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.3699374340
Short name T448
Test name
Test status
Simulation time 10074525549 ps
CPU time 13.12 seconds
Started Jun 02 03:31:42 PM PDT 24
Finished Jun 02 03:31:56 PM PDT 24
Peak memory 205688 kb
Host smart-bc22563d-5bd6-4f36-8c53-d025846d413c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36993
74340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.3699374340
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.4170773152
Short name T1465
Test name
Test status
Simulation time 10060983781 ps
CPU time 15.64 seconds
Started Jun 02 03:31:37 PM PDT 24
Finished Jun 02 03:31:54 PM PDT 24
Peak memory 205636 kb
Host smart-dd2c19cc-dda5-4f63-8a02-c0c11b05283c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41707
73152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.4170773152
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3913030337
Short name T72
Test name
Test status
Simulation time 10042598186 ps
CPU time 14.51 seconds
Started Jun 02 03:31:41 PM PDT 24
Finished Jun 02 03:31:56 PM PDT 24
Peak memory 205664 kb
Host smart-f25b0621-9a8a-4a21-a513-0e82187c81d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39130
30337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3913030337
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.2773995724
Short name T1290
Test name
Test status
Simulation time 10069406483 ps
CPU time 14.57 seconds
Started Jun 02 03:31:37 PM PDT 24
Finished Jun 02 03:31:52 PM PDT 24
Peak memory 205752 kb
Host smart-d3a33a91-a026-4137-9f22-6e25b2cccc4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27739
95724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.2773995724
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_eop_single_bit_handling.2416886107
Short name T1961
Test name
Test status
Simulation time 10068615631 ps
CPU time 14.7 seconds
Started Jun 02 03:31:44 PM PDT 24
Finished Jun 02 03:31:59 PM PDT 24
Peak memory 205648 kb
Host smart-70232f08-835c-41b7-a4f8-b6fe14c28e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24168
86107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_eop_single_bit_handling.2416886107
Directory /workspace/39.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2139738737
Short name T215
Test name
Test status
Simulation time 10056994886 ps
CPU time 13.39 seconds
Started Jun 02 03:31:40 PM PDT 24
Finished Jun 02 03:31:54 PM PDT 24
Peak memory 205756 kb
Host smart-6762c00e-c1ad-4c97-8893-778f14fbd6af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21397
38737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.2139738737
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.4113083270
Short name T1666
Test name
Test status
Simulation time 10036987857 ps
CPU time 13.91 seconds
Started Jun 02 03:31:41 PM PDT 24
Finished Jun 02 03:31:56 PM PDT 24
Peak memory 205660 kb
Host smart-06aeb896-b0df-4ee6-a178-61bd9c39cd24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41130
83270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.4113083270
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.4269204868
Short name T94
Test name
Test status
Simulation time 25923889229 ps
CPU time 49.16 seconds
Started Jun 02 03:31:40 PM PDT 24
Finished Jun 02 03:32:30 PM PDT 24
Peak memory 205704 kb
Host smart-16b4ac1a-ca23-494f-a0f8-2423c9ac9321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42692
04868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.4269204868
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.2512979727
Short name T921
Test name
Test status
Simulation time 10114332714 ps
CPU time 13.53 seconds
Started Jun 02 03:31:39 PM PDT 24
Finished Jun 02 03:31:54 PM PDT 24
Peak memory 205752 kb
Host smart-8d8248e4-33fa-4c56-bf1d-cb7a24175198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25129
79727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2512979727
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.616417671
Short name T1269
Test name
Test status
Simulation time 10072586633 ps
CPU time 13.2 seconds
Started Jun 02 03:31:42 PM PDT 24
Finished Jun 02 03:31:56 PM PDT 24
Peak memory 205648 kb
Host smart-634351e9-3fa9-4f10-867c-f9f6f537732c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61641
7671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.616417671
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.1486832213
Short name T31
Test name
Test status
Simulation time 10069142787 ps
CPU time 15.03 seconds
Started Jun 02 03:31:40 PM PDT 24
Finished Jun 02 03:31:55 PM PDT 24
Peak memory 205796 kb
Host smart-4314b417-f90e-4116-aef2-671a579addb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14868
32213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.1486832213
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.1564739582
Short name T1924
Test name
Test status
Simulation time 10115441644 ps
CPU time 15.33 seconds
Started Jun 02 03:31:40 PM PDT 24
Finished Jun 02 03:31:57 PM PDT 24
Peak memory 205732 kb
Host smart-7125e442-9571-43f3-8f07-340092390f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15647
39582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.1564739582
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.3415501277
Short name T1244
Test name
Test status
Simulation time 10066914086 ps
CPU time 13.65 seconds
Started Jun 02 03:31:41 PM PDT 24
Finished Jun 02 03:31:55 PM PDT 24
Peak memory 205704 kb
Host smart-7358b219-8e0e-4d67-a4ff-e0c706432816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34155
01277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3415501277
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.315196594
Short name T1899
Test name
Test status
Simulation time 10075816357 ps
CPU time 14.7 seconds
Started Jun 02 03:31:42 PM PDT 24
Finished Jun 02 03:31:58 PM PDT 24
Peak memory 205564 kb
Host smart-0380ca17-7fab-4690-98e7-2da82cca9820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31519
6594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.315196594
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.443184619
Short name T762
Test name
Test status
Simulation time 10095910912 ps
CPU time 16.2 seconds
Started Jun 02 03:31:35 PM PDT 24
Finished Jun 02 03:31:52 PM PDT 24
Peak memory 205612 kb
Host smart-91777812-fcb4-4e7f-a563-fa1f09456374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44318
4619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.443184619
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.191591102
Short name T1592
Test name
Test status
Simulation time 10074203213 ps
CPU time 13.5 seconds
Started Jun 02 03:31:47 PM PDT 24
Finished Jun 02 03:32:01 PM PDT 24
Peak memory 205760 kb
Host smart-8a0ec0fb-4025-48ae-8a4a-2dd48828420e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19159
1102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.191591102
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.535827644
Short name T386
Test name
Test status
Simulation time 10089768382 ps
CPU time 16.35 seconds
Started Jun 02 03:31:42 PM PDT 24
Finished Jun 02 03:31:59 PM PDT 24
Peak memory 205688 kb
Host smart-e6055306-e2d4-4052-938a-7c41640b85bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53582
7644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.535827644
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.3794722690
Short name T572
Test name
Test status
Simulation time 15423062337 ps
CPU time 64.02 seconds
Started Jun 02 03:31:39 PM PDT 24
Finished Jun 02 03:32:44 PM PDT 24
Peak memory 205660 kb
Host smart-7403abc1-3576-45a0-84dd-95ef4ea96dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37947
22690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.3794722690
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.2756186922
Short name T1552
Test name
Test status
Simulation time 10143786770 ps
CPU time 13.48 seconds
Started Jun 02 03:27:07 PM PDT 24
Finished Jun 02 03:27:21 PM PDT 24
Peak memory 205552 kb
Host smart-75dfbdab-4b85-4e2d-94ac-bded561e3643
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2756186922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.2756186922
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.1684998420
Short name T669
Test name
Test status
Simulation time 10057641668 ps
CPU time 14.25 seconds
Started Jun 02 03:27:14 PM PDT 24
Finished Jun 02 03:27:28 PM PDT 24
Peak memory 205708 kb
Host smart-96c71d81-b0ef-4ff9-885b-94cdbcb834e8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1684998420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.1684998420
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.2310026417
Short name T1113
Test name
Test status
Simulation time 10100522743 ps
CPU time 12.82 seconds
Started Jun 02 03:27:07 PM PDT 24
Finished Jun 02 03:27:21 PM PDT 24
Peak memory 205564 kb
Host smart-dfb8e556-f28a-4203-8018-aa954fd874cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23100
26417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.2310026417
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.946390216
Short name T1742
Test name
Test status
Simulation time 13850005549 ps
CPU time 17.6 seconds
Started Jun 02 03:26:59 PM PDT 24
Finished Jun 02 03:27:17 PM PDT 24
Peak memory 205736 kb
Host smart-b968d998-71b5-41a7-ac7b-2e1c754e6905
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=946390216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.946390216
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.319623853
Short name T1908
Test name
Test status
Simulation time 23286321780 ps
CPU time 26.36 seconds
Started Jun 02 03:26:59 PM PDT 24
Finished Jun 02 03:27:26 PM PDT 24
Peak memory 205792 kb
Host smart-503dbf32-eb55-4802-b396-cd46b4cd83f8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=319623853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.319623853
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.1211670134
Short name T1596
Test name
Test status
Simulation time 10056743492 ps
CPU time 13.2 seconds
Started Jun 02 03:27:00 PM PDT 24
Finished Jun 02 03:27:14 PM PDT 24
Peak memory 205792 kb
Host smart-dd248ee9-78a3-4df1-84b4-32b15d11059d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12116
70134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.1211670134
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.353843707
Short name T1697
Test name
Test status
Simulation time 10037405129 ps
CPU time 14.73 seconds
Started Jun 02 03:26:56 PM PDT 24
Finished Jun 02 03:27:12 PM PDT 24
Peak memory 205556 kb
Host smart-a5e99899-dcd7-47ae-a5fe-96158615fd9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35384
3707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.353843707
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.4286565383
Short name T1936
Test name
Test status
Simulation time 10691849129 ps
CPU time 13.65 seconds
Started Jun 02 03:27:03 PM PDT 24
Finished Jun 02 03:27:17 PM PDT 24
Peak memory 205720 kb
Host smart-a423343d-c783-4dd6-a1b5-d510ddc24ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42865
65383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.4286565383
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.1257154615
Short name T764
Test name
Test status
Simulation time 10042580322 ps
CPU time 14.15 seconds
Started Jun 02 03:26:57 PM PDT 24
Finished Jun 02 03:27:11 PM PDT 24
Peak memory 205664 kb
Host smart-40850273-3eea-4cba-9956-0eef80de413e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12571
54615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.1257154615
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.803472889
Short name T641
Test name
Test status
Simulation time 10085284256 ps
CPU time 14.12 seconds
Started Jun 02 03:26:57 PM PDT 24
Finished Jun 02 03:27:11 PM PDT 24
Peak memory 205660 kb
Host smart-37f9df43-33f6-4bf0-ac4e-2f3795a939f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80347
2889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.803472889
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.2671814075
Short name T788
Test name
Test status
Simulation time 10798427147 ps
CPU time 16.46 seconds
Started Jun 02 03:26:58 PM PDT 24
Finished Jun 02 03:27:15 PM PDT 24
Peak memory 205760 kb
Host smart-caef414c-b300-4ee8-8bf5-32a5aba47caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26718
14075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.2671814075
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1052007896
Short name T702
Test name
Test status
Simulation time 10150522448 ps
CPU time 16.78 seconds
Started Jun 02 03:26:58 PM PDT 24
Finished Jun 02 03:27:16 PM PDT 24
Peak memory 205700 kb
Host smart-7c9e87ea-c2f0-448b-b42d-7bf4bdcc893e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10520
07896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1052007896
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1613111142
Short name T1023
Test name
Test status
Simulation time 10118084957 ps
CPU time 14.32 seconds
Started Jun 02 03:27:06 PM PDT 24
Finished Jun 02 03:27:22 PM PDT 24
Peak memory 205896 kb
Host smart-a5efe8f0-ebea-46db-88d2-cc85e9df48a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16131
11142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1613111142
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.3750370414
Short name T1452
Test name
Test status
Simulation time 10042111687 ps
CPU time 13.51 seconds
Started Jun 02 03:27:06 PM PDT 24
Finished Jun 02 03:27:21 PM PDT 24
Peak memory 205680 kb
Host smart-d113e515-712a-470e-9274-cbd16a5feb7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37503
70414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3750370414
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.2042400971
Short name T487
Test name
Test status
Simulation time 10127745491 ps
CPU time 13.22 seconds
Started Jun 02 03:26:58 PM PDT 24
Finished Jun 02 03:27:12 PM PDT 24
Peak memory 205800 kb
Host smart-6b26f4b0-5bc3-47bc-9a9c-3c734b4bed56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20424
00971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.2042400971
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.1796363105
Short name T951
Test name
Test status
Simulation time 10154894745 ps
CPU time 13.97 seconds
Started Jun 02 03:26:56 PM PDT 24
Finished Jun 02 03:27:11 PM PDT 24
Peak memory 205676 kb
Host smart-12b776a0-58a9-4139-a108-529648e4929b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17963
63105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.1796363105
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.2410152432
Short name T1656
Test name
Test status
Simulation time 13210861448 ps
CPU time 16.8 seconds
Started Jun 02 03:26:55 PM PDT 24
Finished Jun 02 03:27:13 PM PDT 24
Peak memory 205620 kb
Host smart-1c52667b-84c9-4df6-a3bf-6d87fe94ae7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24101
52432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.2410152432
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.3600988969
Short name T995
Test name
Test status
Simulation time 10142832788 ps
CPU time 13.46 seconds
Started Jun 02 03:26:58 PM PDT 24
Finished Jun 02 03:27:12 PM PDT 24
Peak memory 205752 kb
Host smart-3c585c25-78cd-40db-8a6d-84b50d00c1d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36009
88969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.3600988969
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.4110777157
Short name T1323
Test name
Test status
Simulation time 24073430777 ps
CPU time 151.06 seconds
Started Jun 02 03:27:03 PM PDT 24
Finished Jun 02 03:29:34 PM PDT 24
Peak memory 205648 kb
Host smart-b9a0282d-b874-4b2d-805c-d78dcabae000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41107
77157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.4110777157
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.2968407455
Short name T808
Test name
Test status
Simulation time 10037333404 ps
CPU time 13.76 seconds
Started Jun 02 03:26:59 PM PDT 24
Finished Jun 02 03:27:14 PM PDT 24
Peak memory 205688 kb
Host smart-d2402d43-6876-49b3-9e34-3dd02ca5e9ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29684
07455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.2968407455
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.772406628
Short name T117
Test name
Test status
Simulation time 10092783764 ps
CPU time 12.9 seconds
Started Jun 02 03:27:00 PM PDT 24
Finished Jun 02 03:27:14 PM PDT 24
Peak memory 205704 kb
Host smart-6ddcee94-27d8-4260-95f1-d7413b06ef07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77240
6628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.772406628
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.1090974426
Short name T531
Test name
Test status
Simulation time 10102029946 ps
CPU time 14.39 seconds
Started Jun 02 03:27:02 PM PDT 24
Finished Jun 02 03:27:17 PM PDT 24
Peak memory 205760 kb
Host smart-4e05dd97-a7f5-4e87-904f-30627b003eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10909
74426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.1090974426
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.3303853309
Short name T1408
Test name
Test status
Simulation time 10079197021 ps
CPU time 12.37 seconds
Started Jun 02 03:27:01 PM PDT 24
Finished Jun 02 03:27:15 PM PDT 24
Peak memory 205792 kb
Host smart-0d158d9f-82a7-4f58-8359-fbe9541068df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33038
53309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.3303853309
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.337052128
Short name T1093
Test name
Test status
Simulation time 10074416381 ps
CPU time 13.11 seconds
Started Jun 02 03:27:00 PM PDT 24
Finished Jun 02 03:27:14 PM PDT 24
Peak memory 205676 kb
Host smart-da17b0d7-0209-4b7a-88ea-bb61b8dd9529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33705
2128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.337052128
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1345262376
Short name T155
Test name
Test status
Simulation time 10051235835 ps
CPU time 13.69 seconds
Started Jun 02 03:27:12 PM PDT 24
Finished Jun 02 03:27:26 PM PDT 24
Peak memory 205768 kb
Host smart-34d98ed7-315f-4273-85e9-9942e3ad4a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13452
62376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1345262376
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_eop_single_bit_handling.4247709717
Short name T1436
Test name
Test status
Simulation time 10074920178 ps
CPU time 14.89 seconds
Started Jun 02 03:27:01 PM PDT 24
Finished Jun 02 03:27:17 PM PDT 24
Peak memory 205588 kb
Host smart-d60bc0ed-f45e-4547-a088-040f2e286b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42477
09717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_eop_single_bit_handling.4247709717
Directory /workspace/4.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.820177943
Short name T1675
Test name
Test status
Simulation time 10048938125 ps
CPU time 12.81 seconds
Started Jun 02 03:27:03 PM PDT 24
Finished Jun 02 03:27:17 PM PDT 24
Peak memory 205728 kb
Host smart-8e6b4cf5-a8b7-4ed3-8aaf-293ea8ca1fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82017
7943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.820177943
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3732935135
Short name T984
Test name
Test status
Simulation time 10058912357 ps
CPU time 13.81 seconds
Started Jun 02 03:27:06 PM PDT 24
Finished Jun 02 03:27:21 PM PDT 24
Peak memory 205776 kb
Host smart-c55b356a-a6c3-4b97-92c7-d6de37bdcaf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37329
35135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3732935135
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3327184039
Short name T95
Test name
Test status
Simulation time 32718152046 ps
CPU time 62.85 seconds
Started Jun 02 03:27:02 PM PDT 24
Finished Jun 02 03:28:06 PM PDT 24
Peak memory 205664 kb
Host smart-21581ce8-2acd-4bb1-912b-74711d00724f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33271
84039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3327184039
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3108152961
Short name T446
Test name
Test status
Simulation time 10065169258 ps
CPU time 13.42 seconds
Started Jun 02 03:27:01 PM PDT 24
Finished Jun 02 03:27:16 PM PDT 24
Peak memory 205768 kb
Host smart-a2f8c951-44a1-41b5-9ae5-0f2b286b9f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31081
52961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3108152961
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2151364483
Short name T934
Test name
Test status
Simulation time 10093848624 ps
CPU time 14.71 seconds
Started Jun 02 03:27:01 PM PDT 24
Finished Jun 02 03:27:16 PM PDT 24
Peak memory 205744 kb
Host smart-303b45ab-3070-486f-853e-6315cd8f91aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21513
64483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2151364483
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.4208111562
Short name T163
Test name
Test status
Simulation time 41660757402 ps
CPU time 239.35 seconds
Started Jun 02 03:27:05 PM PDT 24
Finished Jun 02 03:31:06 PM PDT 24
Peak memory 205768 kb
Host smart-facdb428-536d-40c7-93e4-792bb589137f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4208111562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.4208111562
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.1111414490
Short name T1275
Test name
Test status
Simulation time 14794060661 ps
CPU time 117.52 seconds
Started Jun 02 03:27:04 PM PDT 24
Finished Jun 02 03:29:02 PM PDT 24
Peak memory 205648 kb
Host smart-70d63a78-3ce3-4016-a4b3-fb05151c2d74
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1111414490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.1111414490
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.3961635717
Short name T968
Test name
Test status
Simulation time 36939995070 ps
CPU time 190.98 seconds
Started Jun 02 03:27:04 PM PDT 24
Finished Jun 02 03:30:16 PM PDT 24
Peak memory 205780 kb
Host smart-d1aa07db-a6b1-4c3a-9178-3cfb507c8ef5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3961635717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.3961635717
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.121391561
Short name T1609
Test name
Test status
Simulation time 10065089099 ps
CPU time 15.17 seconds
Started Jun 02 03:27:03 PM PDT 24
Finished Jun 02 03:27:18 PM PDT 24
Peak memory 205716 kb
Host smart-09d135af-64dd-469a-a700-9a3353331e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12139
1561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.121391561
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.456592729
Short name T439
Test name
Test status
Simulation time 10061470424 ps
CPU time 13.76 seconds
Started Jun 02 03:27:01 PM PDT 24
Finished Jun 02 03:27:16 PM PDT 24
Peak memory 205680 kb
Host smart-d592e6cc-77b1-452c-8eac-6f822bfaf5a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45659
2729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.456592729
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.1212610322
Short name T208
Test name
Test status
Simulation time 770282727 ps
CPU time 1.58 seconds
Started Jun 02 03:27:08 PM PDT 24
Finished Jun 02 03:27:10 PM PDT 24
Peak memory 221688 kb
Host smart-557a24b5-6bf0-40a4-b45f-269496a6c233
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1212610322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.1212610322
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.1796051560
Short name T144
Test name
Test status
Simulation time 10053053154 ps
CPU time 12.56 seconds
Started Jun 02 03:27:01 PM PDT 24
Finished Jun 02 03:27:15 PM PDT 24
Peak memory 205684 kb
Host smart-93616952-2813-41e3-a63e-64135aa916f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17960
51560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.1796051560
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2809843170
Short name T1670
Test name
Test status
Simulation time 10047062463 ps
CPU time 16.38 seconds
Started Jun 02 03:27:02 PM PDT 24
Finished Jun 02 03:27:19 PM PDT 24
Peak memory 205668 kb
Host smart-50ab89dd-b5e6-4e32-9378-cf88dbb8fefc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28098
43170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2809843170
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.2492978508
Short name T818
Test name
Test status
Simulation time 10174051623 ps
CPU time 13.36 seconds
Started Jun 02 03:26:58 PM PDT 24
Finished Jun 02 03:27:12 PM PDT 24
Peak memory 205772 kb
Host smart-8e9e971f-cb15-474b-8c2c-b5ab82dee805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24929
78508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2492978508
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.2761723961
Short name T395
Test name
Test status
Simulation time 10042746710 ps
CPU time 15.95 seconds
Started Jun 02 03:27:03 PM PDT 24
Finished Jun 02 03:27:19 PM PDT 24
Peak memory 205736 kb
Host smart-c49778e3-bdb6-43cc-b046-dbe3d7533d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27617
23961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.2761723961
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.3304896769
Short name T767
Test name
Test status
Simulation time 10078199669 ps
CPU time 16.55 seconds
Started Jun 02 03:27:02 PM PDT 24
Finished Jun 02 03:27:19 PM PDT 24
Peak memory 205744 kb
Host smart-8573765d-f4da-494c-98d2-ad09d287ef16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33048
96769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.3304896769
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.229381473
Short name T772
Test name
Test status
Simulation time 13980290013 ps
CPU time 49.12 seconds
Started Jun 02 03:27:00 PM PDT 24
Finished Jun 02 03:27:50 PM PDT 24
Peak memory 205704 kb
Host smart-3e5a2d58-e39a-43f8-9cf3-e4bcb8bd7aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22938
1473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.229381473
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.4158420432
Short name T1537
Test name
Test status
Simulation time 41890462562 ps
CPU time 977.07 seconds
Started Jun 02 03:27:01 PM PDT 24
Finished Jun 02 03:43:30 PM PDT 24
Peak memory 205796 kb
Host smart-23b43031-3e4b-42cb-8a97-6a6d315d7482
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158420432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_
traffic.4158420432
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.3098318564
Short name T519
Test name
Test status
Simulation time 10137241324 ps
CPU time 14.44 seconds
Started Jun 02 03:31:50 PM PDT 24
Finished Jun 02 03:32:05 PM PDT 24
Peak memory 205672 kb
Host smart-063b6571-9196-4106-b613-c2d6c8e72663
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3098318564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.3098318564
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.3907677743
Short name T628
Test name
Test status
Simulation time 10067085011 ps
CPU time 13.31 seconds
Started Jun 02 03:31:50 PM PDT 24
Finished Jun 02 03:32:04 PM PDT 24
Peak memory 205752 kb
Host smart-cb4cc204-df44-499c-8291-9448dc0a04ce
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3907677743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.3907677743
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.3015029749
Short name T670
Test name
Test status
Simulation time 10146849887 ps
CPU time 13.79 seconds
Started Jun 02 03:31:49 PM PDT 24
Finished Jun 02 03:32:03 PM PDT 24
Peak memory 205668 kb
Host smart-5fdb6289-beac-4694-b3bf-16f67450c5d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30150
29749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.3015029749
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.3582475911
Short name T1488
Test name
Test status
Simulation time 13299559735 ps
CPU time 17.58 seconds
Started Jun 02 03:31:42 PM PDT 24
Finished Jun 02 03:32:01 PM PDT 24
Peak memory 205608 kb
Host smart-bc8575cb-9b7b-45bc-865c-e10784bce5ff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3582475911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.3582475911
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.418851502
Short name T1802
Test name
Test status
Simulation time 23344800411 ps
CPU time 30.41 seconds
Started Jun 02 03:31:56 PM PDT 24
Finished Jun 02 03:32:27 PM PDT 24
Peak memory 205768 kb
Host smart-522c97ed-6e6d-4909-8b9f-6df7b70fd2a1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=418851502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.418851502
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.3483925135
Short name T994
Test name
Test status
Simulation time 10088914477 ps
CPU time 13.2 seconds
Started Jun 02 03:31:44 PM PDT 24
Finished Jun 02 03:31:58 PM PDT 24
Peak memory 205724 kb
Host smart-db8dcb09-c646-4a4b-b7af-c53ef12d68fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34839
25135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.3483925135
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2160002401
Short name T606
Test name
Test status
Simulation time 10760612879 ps
CPU time 15.65 seconds
Started Jun 02 03:31:45 PM PDT 24
Finished Jun 02 03:32:02 PM PDT 24
Peak memory 205652 kb
Host smart-33786e96-d611-4605-9000-fb80fb198ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21600
02401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2160002401
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.1137953520
Short name T599
Test name
Test status
Simulation time 10073530322 ps
CPU time 16.1 seconds
Started Jun 02 03:31:43 PM PDT 24
Finished Jun 02 03:32:00 PM PDT 24
Peak memory 205640 kb
Host smart-5490f207-a165-4e42-b2e1-479ae1bd1a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11379
53520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.1137953520
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.2560838978
Short name T1372
Test name
Test status
Simulation time 10142565372 ps
CPU time 12.97 seconds
Started Jun 02 03:31:47 PM PDT 24
Finished Jun 02 03:32:01 PM PDT 24
Peak memory 205688 kb
Host smart-1d0963de-6eb8-43f0-bc77-651d72b1fa9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25608
38978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.2560838978
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.5491381
Short name T1251
Test name
Test status
Simulation time 10739929100 ps
CPU time 14.65 seconds
Started Jun 02 03:31:43 PM PDT 24
Finished Jun 02 03:31:58 PM PDT 24
Peak memory 205748 kb
Host smart-8afb4e6d-341e-4c48-82e8-69905d90f883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54913
81 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.5491381
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2103381157
Short name T1801
Test name
Test status
Simulation time 10072119827 ps
CPU time 14.13 seconds
Started Jun 02 03:31:45 PM PDT 24
Finished Jun 02 03:32:00 PM PDT 24
Peak memory 205656 kb
Host smart-8fd16b62-37ff-48d2-be00-23d95fa663f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21033
81157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2103381157
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.1893567394
Short name T1048
Test name
Test status
Simulation time 10142438842 ps
CPU time 14.64 seconds
Started Jun 02 03:31:58 PM PDT 24
Finished Jun 02 03:32:14 PM PDT 24
Peak memory 205612 kb
Host smart-bf01970e-15a4-4871-bc05-5c50220fd529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18935
67394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.1893567394
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.3309959267
Short name T382
Test name
Test status
Simulation time 10043337046 ps
CPU time 12.79 seconds
Started Jun 02 03:31:50 PM PDT 24
Finished Jun 02 03:32:04 PM PDT 24
Peak memory 205716 kb
Host smart-35c49b30-90e8-4384-a5ae-37d0ec883ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33099
59267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.3309959267
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.799918361
Short name T1870
Test name
Test status
Simulation time 10132585468 ps
CPU time 14.18 seconds
Started Jun 02 03:31:45 PM PDT 24
Finished Jun 02 03:32:00 PM PDT 24
Peak memory 205828 kb
Host smart-fb66e5af-09e0-43ae-bfbf-dabf093b4548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79991
8361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.799918361
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.1184594432
Short name T685
Test name
Test status
Simulation time 10075267639 ps
CPU time 13.18 seconds
Started Jun 02 03:31:47 PM PDT 24
Finished Jun 02 03:32:00 PM PDT 24
Peak memory 205732 kb
Host smart-ae374e13-fc41-441c-8f14-a758fefab37b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11845
94432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.1184594432
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.4010677472
Short name T1693
Test name
Test status
Simulation time 13269326297 ps
CPU time 17.46 seconds
Started Jun 02 03:31:50 PM PDT 24
Finished Jun 02 03:32:08 PM PDT 24
Peak memory 205756 kb
Host smart-5a9694e0-3896-4aa2-bccc-706d229af5d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40106
77472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.4010677472
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.1779330967
Short name T1669
Test name
Test status
Simulation time 10098814341 ps
CPU time 13.92 seconds
Started Jun 02 03:31:42 PM PDT 24
Finished Jun 02 03:31:57 PM PDT 24
Peak memory 205700 kb
Host smart-88b6ef7e-6e2c-4c60-9d2f-79bac07c6334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17793
30967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1779330967
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.549397420
Short name T786
Test name
Test status
Simulation time 24132547318 ps
CPU time 145.45 seconds
Started Jun 02 03:31:45 PM PDT 24
Finished Jun 02 03:34:12 PM PDT 24
Peak memory 205712 kb
Host smart-d29e1702-22aa-4b12-905d-7a4c2260af5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54939
7420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.549397420
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.1339303767
Short name T349
Test name
Test status
Simulation time 10058380285 ps
CPU time 13.33 seconds
Started Jun 02 03:31:47 PM PDT 24
Finished Jun 02 03:32:01 PM PDT 24
Peak memory 205676 kb
Host smart-1196860c-cb77-46de-bba3-28a4436b75e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13393
03767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.1339303767
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.2732197517
Short name T1600
Test name
Test status
Simulation time 10141292259 ps
CPU time 14 seconds
Started Jun 02 03:31:45 PM PDT 24
Finished Jun 02 03:32:00 PM PDT 24
Peak memory 205772 kb
Host smart-79fc01d3-f7c9-496f-8242-93739994dc42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27321
97517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.2732197517
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.3264963482
Short name T1704
Test name
Test status
Simulation time 10076085753 ps
CPU time 14.94 seconds
Started Jun 02 03:31:44 PM PDT 24
Finished Jun 02 03:32:00 PM PDT 24
Peak memory 205756 kb
Host smart-3f1993d8-daac-4354-84c0-b764d344dd47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32649
63482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.3264963482
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.1929211173
Short name T1962
Test name
Test status
Simulation time 10057471600 ps
CPU time 13.87 seconds
Started Jun 02 03:31:44 PM PDT 24
Finished Jun 02 03:31:59 PM PDT 24
Peak memory 205792 kb
Host smart-eb890dfe-ddd8-4878-9f2e-1c768e9a22d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19292
11173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1929211173
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.365944074
Short name T1163
Test name
Test status
Simulation time 10071779952 ps
CPU time 13.59 seconds
Started Jun 02 03:31:43 PM PDT 24
Finished Jun 02 03:31:57 PM PDT 24
Peak memory 205692 kb
Host smart-5f2ce84a-7372-411b-9b15-a05f673ec974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36594
4074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.365944074
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.3179623897
Short name T703
Test name
Test status
Simulation time 10065097715 ps
CPU time 12.91 seconds
Started Jun 02 03:31:54 PM PDT 24
Finished Jun 02 03:32:08 PM PDT 24
Peak memory 205772 kb
Host smart-5e75ad80-8fee-43a8-ab76-60c677306d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31796
23897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.3179623897
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_eop_single_bit_handling.3054986359
Short name T1059
Test name
Test status
Simulation time 10090516988 ps
CPU time 13.86 seconds
Started Jun 02 03:31:49 PM PDT 24
Finished Jun 02 03:32:03 PM PDT 24
Peak memory 205664 kb
Host smart-778992c2-3da1-4347-a5bc-1f2d9cb40b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30549
86359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_eop_single_bit_handling.3054986359
Directory /workspace/40.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2798229496
Short name T1811
Test name
Test status
Simulation time 10062813547 ps
CPU time 15.6 seconds
Started Jun 02 03:31:53 PM PDT 24
Finished Jun 02 03:32:09 PM PDT 24
Peak memory 205616 kb
Host smart-48f8599b-30e5-4c05-a530-8d19c236c29d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27982
29496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2798229496
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.2061048316
Short name T43
Test name
Test status
Simulation time 10080550200 ps
CPU time 14.42 seconds
Started Jun 02 03:31:49 PM PDT 24
Finished Jun 02 03:32:04 PM PDT 24
Peak memory 205828 kb
Host smart-bc1b19a4-ac90-46df-90fb-a16cae931d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20610
48316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.2061048316
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.3955841002
Short name T1228
Test name
Test status
Simulation time 19999194252 ps
CPU time 40.58 seconds
Started Jun 02 03:31:49 PM PDT 24
Finished Jun 02 03:32:30 PM PDT 24
Peak memory 205708 kb
Host smart-830691a6-1ede-41e2-b571-e83ca674249c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39558
41002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.3955841002
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.1799831299
Short name T849
Test name
Test status
Simulation time 10090319394 ps
CPU time 15.09 seconds
Started Jun 02 03:31:56 PM PDT 24
Finished Jun 02 03:32:12 PM PDT 24
Peak memory 205740 kb
Host smart-03ed2a88-6db8-41c6-90f1-b8a8caee9cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17998
31299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.1799831299
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.3517010007
Short name T815
Test name
Test status
Simulation time 10111082764 ps
CPU time 12.91 seconds
Started Jun 02 03:31:46 PM PDT 24
Finished Jun 02 03:31:59 PM PDT 24
Peak memory 205696 kb
Host smart-decf4ba7-cafe-4756-9e68-8019bd3941b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35170
10007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.3517010007
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.2993382040
Short name T1889
Test name
Test status
Simulation time 10122376693 ps
CPU time 13.96 seconds
Started Jun 02 03:31:46 PM PDT 24
Finished Jun 02 03:32:00 PM PDT 24
Peak memory 205652 kb
Host smart-b1af52df-675e-4ac6-b5f4-82c1bea02aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29933
82040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.2993382040
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.3716083074
Short name T338
Test name
Test status
Simulation time 10043312513 ps
CPU time 12.96 seconds
Started Jun 02 03:31:46 PM PDT 24
Finished Jun 02 03:32:00 PM PDT 24
Peak memory 205760 kb
Host smart-8b0c5d16-f3af-4f89-bddc-f293318e3472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37160
83074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.3716083074
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.1014602663
Short name T1750
Test name
Test status
Simulation time 10073616506 ps
CPU time 13.72 seconds
Started Jun 02 03:31:52 PM PDT 24
Finished Jun 02 03:32:06 PM PDT 24
Peak memory 205708 kb
Host smart-0dd2419f-ef65-4055-8f39-00c04983eaf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10146
02663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.1014602663
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.2528053374
Short name T1354
Test name
Test status
Simulation time 10056322494 ps
CPU time 14.47 seconds
Started Jun 02 03:31:51 PM PDT 24
Finished Jun 02 03:32:06 PM PDT 24
Peak memory 205776 kb
Host smart-da626e6c-e8d1-4e55-abcc-d1ece3f663bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25280
53374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.2528053374
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2924306159
Short name T2025
Test name
Test status
Simulation time 10146930550 ps
CPU time 15.57 seconds
Started Jun 02 03:31:43 PM PDT 24
Finished Jun 02 03:32:00 PM PDT 24
Peak memory 205732 kb
Host smart-d4215db0-c114-40e6-a583-cbe32f876e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29243
06159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2924306159
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.3516566576
Short name T1426
Test name
Test status
Simulation time 10062356442 ps
CPU time 12.78 seconds
Started Jun 02 03:31:59 PM PDT 24
Finished Jun 02 03:32:12 PM PDT 24
Peak memory 205756 kb
Host smart-ed9ff04b-b1f9-4a22-9912-51ed1d0d9522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35165
66576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.3516566576
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.830310303
Short name T520
Test name
Test status
Simulation time 10066778790 ps
CPU time 14.57 seconds
Started Jun 02 03:31:44 PM PDT 24
Finished Jun 02 03:31:59 PM PDT 24
Peak memory 205556 kb
Host smart-20919d1d-6a5a-4df5-bbf4-c7a16fca754d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83031
0303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.830310303
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.3542699287
Short name T625
Test name
Test status
Simulation time 17546186539 ps
CPU time 84.78 seconds
Started Jun 02 03:31:54 PM PDT 24
Finished Jun 02 03:33:20 PM PDT 24
Peak memory 205712 kb
Host smart-e35d4e37-9eba-4151-be3a-a70b182f36ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35426
99287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.3542699287
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.1014863990
Short name T1822
Test name
Test status
Simulation time 10144548316 ps
CPU time 15.77 seconds
Started Jun 02 03:31:54 PM PDT 24
Finished Jun 02 03:32:10 PM PDT 24
Peak memory 205640 kb
Host smart-0dabda0d-ab39-42e2-9d75-9bd178aac558
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1014863990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.1014863990
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.1627903641
Short name T34
Test name
Test status
Simulation time 10049649785 ps
CPU time 16.06 seconds
Started Jun 02 03:31:55 PM PDT 24
Finished Jun 02 03:32:12 PM PDT 24
Peak memory 205576 kb
Host smart-eb5f560a-ffde-4d79-99a8-dfd96313ed55
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1627903641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.1627903641
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.3955893560
Short name T1799
Test name
Test status
Simulation time 10129356136 ps
CPU time 13.69 seconds
Started Jun 02 03:31:53 PM PDT 24
Finished Jun 02 03:32:08 PM PDT 24
Peak memory 205760 kb
Host smart-6460e11f-10a4-4968-a2b2-51221b63af7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39558
93560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.3955893560
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.121466505
Short name T216
Test name
Test status
Simulation time 13481222248 ps
CPU time 18.16 seconds
Started Jun 02 03:31:56 PM PDT 24
Finished Jun 02 03:32:15 PM PDT 24
Peak memory 205704 kb
Host smart-78980cfd-9ec3-43ad-abfe-3fa028e0959f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=121466505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.121466505
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.1379598753
Short name T672
Test name
Test status
Simulation time 23271918782 ps
CPU time 26.49 seconds
Started Jun 02 03:31:54 PM PDT 24
Finished Jun 02 03:32:21 PM PDT 24
Peak memory 205380 kb
Host smart-231b62c2-7423-4ff7-a61b-2dea7b2faf69
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1379598753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.1379598753
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.4057529500
Short name T1803
Test name
Test status
Simulation time 10061120300 ps
CPU time 16.01 seconds
Started Jun 02 03:31:54 PM PDT 24
Finished Jun 02 03:32:11 PM PDT 24
Peak memory 205576 kb
Host smart-924571dd-9aee-485c-8d5b-acd1d71e403b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40575
29500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.4057529500
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.3448105753
Short name T1397
Test name
Test status
Simulation time 10163736080 ps
CPU time 12.9 seconds
Started Jun 02 03:31:58 PM PDT 24
Finished Jun 02 03:32:12 PM PDT 24
Peak memory 205648 kb
Host smart-748287fb-0f0e-407d-b37f-fa3c39a95ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34481
05753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.3448105753
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.3321797000
Short name T1276
Test name
Test status
Simulation time 10083875956 ps
CPU time 14.53 seconds
Started Jun 02 03:31:52 PM PDT 24
Finished Jun 02 03:32:07 PM PDT 24
Peak memory 205640 kb
Host smart-b8154ee1-b050-4c89-8fa1-57e78a40d835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33217
97000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.3321797000
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.479850971
Short name T701
Test name
Test status
Simulation time 10064691515 ps
CPU time 13.69 seconds
Started Jun 02 03:31:51 PM PDT 24
Finished Jun 02 03:32:05 PM PDT 24
Peak memory 205708 kb
Host smart-c08b2a8e-65e7-4387-b015-c3e1dd339483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47985
0971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.479850971
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.4067603385
Short name T604
Test name
Test status
Simulation time 11060406663 ps
CPU time 15.61 seconds
Started Jun 02 03:31:51 PM PDT 24
Finished Jun 02 03:32:07 PM PDT 24
Peak memory 205772 kb
Host smart-dce89cf3-47de-4c89-939b-ca8e6a6530e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40676
03385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.4067603385
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.2592504474
Short name T1467
Test name
Test status
Simulation time 10061925231 ps
CPU time 14.27 seconds
Started Jun 02 03:31:55 PM PDT 24
Finished Jun 02 03:32:10 PM PDT 24
Peak memory 205656 kb
Host smart-8c743297-cadb-4728-90ae-c1f8351730a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25925
04474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.2592504474
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.3473973712
Short name T733
Test name
Test status
Simulation time 10108091809 ps
CPU time 12.98 seconds
Started Jun 02 03:31:54 PM PDT 24
Finished Jun 02 03:32:07 PM PDT 24
Peak memory 205584 kb
Host smart-1a37c51a-4ae5-4629-901f-e7e6a2e679b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34739
73712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.3473973712
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2528636496
Short name T1814
Test name
Test status
Simulation time 10063076028 ps
CPU time 13.88 seconds
Started Jun 02 03:32:02 PM PDT 24
Finished Jun 02 03:32:17 PM PDT 24
Peak memory 205696 kb
Host smart-d8a63e26-add3-4dd3-8d33-f2e9eab06fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25286
36496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2528636496
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.2957235152
Short name T343
Test name
Test status
Simulation time 10101007305 ps
CPU time 13.56 seconds
Started Jun 02 03:31:51 PM PDT 24
Finished Jun 02 03:32:06 PM PDT 24
Peak memory 205764 kb
Host smart-d2b68d1d-233e-4751-a292-ab851966fe65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29572
35152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.2957235152
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.909237221
Short name T1546
Test name
Test status
Simulation time 10123421526 ps
CPU time 13.52 seconds
Started Jun 02 03:31:49 PM PDT 24
Finished Jun 02 03:32:03 PM PDT 24
Peak memory 205680 kb
Host smart-32d706b9-2c46-4bcc-8d2b-88685edfe48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90923
7221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.909237221
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.1229768397
Short name T309
Test name
Test status
Simulation time 13169932008 ps
CPU time 17.26 seconds
Started Jun 02 03:31:51 PM PDT 24
Finished Jun 02 03:32:09 PM PDT 24
Peak memory 205672 kb
Host smart-75144668-171b-4dbd-a94f-ef7fe3c9ac55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12297
68397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.1229768397
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.2997744627
Short name T799
Test name
Test status
Simulation time 10079086802 ps
CPU time 13.24 seconds
Started Jun 02 03:31:53 PM PDT 24
Finished Jun 02 03:32:07 PM PDT 24
Peak memory 205644 kb
Host smart-a49ec143-4bac-430d-bb67-e03baea0ead6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29977
44627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.2997744627
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.2926113971
Short name T1990
Test name
Test status
Simulation time 24830134465 ps
CPU time 121.92 seconds
Started Jun 02 03:31:48 PM PDT 24
Finished Jun 02 03:33:50 PM PDT 24
Peak memory 205696 kb
Host smart-73824835-e396-463e-839f-f022e64609b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29261
13971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.2926113971
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.3162043674
Short name T319
Test name
Test status
Simulation time 10076519208 ps
CPU time 14.81 seconds
Started Jun 02 03:31:56 PM PDT 24
Finished Jun 02 03:32:11 PM PDT 24
Peak memory 205764 kb
Host smart-774932ab-e57b-4c02-adc8-aa90e7dbffd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31620
43674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.3162043674
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.3204006041
Short name T1993
Test name
Test status
Simulation time 10080674854 ps
CPU time 13.38 seconds
Started Jun 02 03:31:50 PM PDT 24
Finished Jun 02 03:32:05 PM PDT 24
Peak memory 205700 kb
Host smart-e38f351a-62aa-4163-977a-8a5839714a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32040
06041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.3204006041
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.2823768648
Short name T1730
Test name
Test status
Simulation time 10105135089 ps
CPU time 13.8 seconds
Started Jun 02 03:31:56 PM PDT 24
Finished Jun 02 03:32:10 PM PDT 24
Peak memory 205668 kb
Host smart-68961e50-4d2d-4e26-8b00-5f44548b0b55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28237
68648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2823768648
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.4230968506
Short name T621
Test name
Test status
Simulation time 10045398254 ps
CPU time 13.61 seconds
Started Jun 02 03:31:58 PM PDT 24
Finished Jun 02 03:32:13 PM PDT 24
Peak memory 205616 kb
Host smart-0de319bd-49bb-4b66-b7d7-8d51b0abf72a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42309
68506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.4230968506
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3839485334
Short name T1929
Test name
Test status
Simulation time 10056523381 ps
CPU time 13.08 seconds
Started Jun 02 03:31:56 PM PDT 24
Finished Jun 02 03:32:10 PM PDT 24
Peak memory 205644 kb
Host smart-9d2a251b-e502-4bbd-8caf-35b6fa1174e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38394
85334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3839485334
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_eop_single_bit_handling.3759030291
Short name T1992
Test name
Test status
Simulation time 10058981900 ps
CPU time 14.31 seconds
Started Jun 02 03:31:56 PM PDT 24
Finished Jun 02 03:32:10 PM PDT 24
Peak memory 205640 kb
Host smart-c0c8ed35-16f8-457a-bde1-3edce50b31d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37590
30291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_eop_single_bit_handling.3759030291
Directory /workspace/41.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.2382936955
Short name T529
Test name
Test status
Simulation time 10047958541 ps
CPU time 13.86 seconds
Started Jun 02 03:31:55 PM PDT 24
Finished Jun 02 03:32:09 PM PDT 24
Peak memory 205688 kb
Host smart-2ca38bbb-fcf5-48fd-9046-113feb614b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23829
36955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.2382936955
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2729513070
Short name T1324
Test name
Test status
Simulation time 10087979022 ps
CPU time 14.37 seconds
Started Jun 02 03:31:55 PM PDT 24
Finished Jun 02 03:32:10 PM PDT 24
Peak memory 205660 kb
Host smart-e8c2fa1d-f291-4a8e-9761-f28723b764de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27295
13070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2729513070
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3335413011
Short name T1218
Test name
Test status
Simulation time 18134879596 ps
CPU time 32.28 seconds
Started Jun 02 03:31:50 PM PDT 24
Finished Jun 02 03:32:23 PM PDT 24
Peak memory 205660 kb
Host smart-5bd4c786-ec6e-4fed-bcb3-32ec09d45404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33354
13011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3335413011
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1594884610
Short name T812
Test name
Test status
Simulation time 10062945743 ps
CPU time 13.38 seconds
Started Jun 02 03:31:53 PM PDT 24
Finished Jun 02 03:32:07 PM PDT 24
Peak memory 205788 kb
Host smart-7f3fff7b-36a6-476a-aadd-84d7174df00f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15948
84610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1594884610
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3630524830
Short name T1774
Test name
Test status
Simulation time 10127688835 ps
CPU time 13.97 seconds
Started Jun 02 03:31:52 PM PDT 24
Finished Jun 02 03:32:07 PM PDT 24
Peak memory 205732 kb
Host smart-69191a5b-2a13-4a7a-a25b-873e71b14fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36305
24830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3630524830
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.2188216954
Short name T615
Test name
Test status
Simulation time 10070067420 ps
CPU time 16.28 seconds
Started Jun 02 03:31:57 PM PDT 24
Finished Jun 02 03:32:14 PM PDT 24
Peak memory 205720 kb
Host smart-2ff6b5dc-f692-4bbe-86f3-efe16fb1dfcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21882
16954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.2188216954
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.2016888571
Short name T407
Test name
Test status
Simulation time 10097960756 ps
CPU time 15.75 seconds
Started Jun 02 03:31:52 PM PDT 24
Finished Jun 02 03:32:09 PM PDT 24
Peak memory 205600 kb
Host smart-8c817140-c0a3-423e-bd91-887e3616972f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20168
88571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.2016888571
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.1143958466
Short name T1206
Test name
Test status
Simulation time 10053275297 ps
CPU time 13.68 seconds
Started Jun 02 03:31:54 PM PDT 24
Finished Jun 02 03:32:08 PM PDT 24
Peak memory 205672 kb
Host smart-70b54ffe-3d8d-4da9-bab4-3598319d3cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11439
58466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.1143958466
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3891178576
Short name T609
Test name
Test status
Simulation time 10053800226 ps
CPU time 14.14 seconds
Started Jun 02 03:31:52 PM PDT 24
Finished Jun 02 03:32:07 PM PDT 24
Peak memory 206008 kb
Host smart-03d4d098-cf5d-4f61-bee1-0c5dc38a71a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38911
78576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3891178576
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.650697285
Short name T663
Test name
Test status
Simulation time 10130458682 ps
CPU time 14.07 seconds
Started Jun 02 03:31:52 PM PDT 24
Finished Jun 02 03:32:07 PM PDT 24
Peak memory 205728 kb
Host smart-84ef8fb7-3be8-43d9-bbea-454c688e674c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65069
7285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.650697285
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2439763404
Short name T396
Test name
Test status
Simulation time 10070148633 ps
CPU time 13.79 seconds
Started Jun 02 03:31:58 PM PDT 24
Finished Jun 02 03:32:13 PM PDT 24
Peak memory 205716 kb
Host smart-036d2186-fd1f-4c0c-9853-7928276af5ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24397
63404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2439763404
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.1251827829
Short name T1713
Test name
Test status
Simulation time 10072347790 ps
CPU time 13.33 seconds
Started Jun 02 03:31:52 PM PDT 24
Finished Jun 02 03:32:06 PM PDT 24
Peak memory 205752 kb
Host smart-7a4b19f6-492d-4f96-ad4a-a5fda0c4cd2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12518
27829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.1251827829
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.993890380
Short name T324
Test name
Test status
Simulation time 23080748071 ps
CPU time 402.38 seconds
Started Jun 02 03:31:53 PM PDT 24
Finished Jun 02 03:38:36 PM PDT 24
Peak memory 205704 kb
Host smart-b4d1e176-7444-4b64-bfab-99e0d6bef33a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99389
0380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.993890380
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.2116223229
Short name T1507
Test name
Test status
Simulation time 10186392437 ps
CPU time 13.95 seconds
Started Jun 02 03:32:00 PM PDT 24
Finished Jun 02 03:32:15 PM PDT 24
Peak memory 205700 kb
Host smart-62f54ab3-51b8-4cf3-a89b-8c0643aa9225
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2116223229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.2116223229
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.1953609269
Short name T1969
Test name
Test status
Simulation time 10072695450 ps
CPU time 13.14 seconds
Started Jun 02 03:32:01 PM PDT 24
Finished Jun 02 03:32:15 PM PDT 24
Peak memory 205756 kb
Host smart-09ac9dac-cef2-4020-a66e-acce71c41fc3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1953609269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.1953609269
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.2402975163
Short name T755
Test name
Test status
Simulation time 10146824477 ps
CPU time 13.02 seconds
Started Jun 02 03:32:12 PM PDT 24
Finished Jun 02 03:32:26 PM PDT 24
Peak memory 205632 kb
Host smart-ffc8f7d1-a8a0-4be1-8851-761c80b332a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24029
75163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.2402975163
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.4101081012
Short name T1709
Test name
Test status
Simulation time 14133456635 ps
CPU time 18.24 seconds
Started Jun 02 03:31:55 PM PDT 24
Finished Jun 02 03:32:14 PM PDT 24
Peak memory 205808 kb
Host smart-3fa5ec40-5c3d-4611-ae6d-0176ebce0180
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4101081012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.4101081012
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.3231591067
Short name T1853
Test name
Test status
Simulation time 23371612914 ps
CPU time 26.88 seconds
Started Jun 02 03:31:53 PM PDT 24
Finished Jun 02 03:32:20 PM PDT 24
Peak memory 205760 kb
Host smart-4ac60123-6289-4903-8db8-7bbb8c77d68f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3231591067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3231591067
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2387410315
Short name T636
Test name
Test status
Simulation time 10079205599 ps
CPU time 14.65 seconds
Started Jun 02 03:31:55 PM PDT 24
Finished Jun 02 03:32:10 PM PDT 24
Peak memory 205764 kb
Host smart-1f23d968-a694-4331-8a37-45b141fa28f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23874
10315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2387410315
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.2826137534
Short name T1496
Test name
Test status
Simulation time 10842798812 ps
CPU time 16 seconds
Started Jun 02 03:31:53 PM PDT 24
Finished Jun 02 03:32:10 PM PDT 24
Peak memory 205748 kb
Host smart-1ea03d19-ae96-40e8-b8b9-7069f9a788c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28261
37534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.2826137534
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.3112408158
Short name T1284
Test name
Test status
Simulation time 10071310699 ps
CPU time 14.56 seconds
Started Jun 02 03:32:03 PM PDT 24
Finished Jun 02 03:32:19 PM PDT 24
Peak memory 205700 kb
Host smart-e394e1dc-7d60-4198-b896-5da026be18fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31124
08158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.3112408158
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.1539814151
Short name T1001
Test name
Test status
Simulation time 10075667413 ps
CPU time 15.37 seconds
Started Jun 02 03:32:03 PM PDT 24
Finished Jun 02 03:32:20 PM PDT 24
Peak memory 205708 kb
Host smart-a6719d10-c595-4270-9bde-c7a1195ed283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15398
14151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1539814151
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.760131474
Short name T1778
Test name
Test status
Simulation time 10825603575 ps
CPU time 14.9 seconds
Started Jun 02 03:31:54 PM PDT 24
Finished Jun 02 03:32:09 PM PDT 24
Peak memory 205788 kb
Host smart-e4ed7d5b-2d61-4866-bef9-86f26421ddab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76013
1474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.760131474
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3270919728
Short name T1077
Test name
Test status
Simulation time 10217422090 ps
CPU time 15.99 seconds
Started Jun 02 03:32:00 PM PDT 24
Finished Jun 02 03:32:17 PM PDT 24
Peak memory 205744 kb
Host smart-47693dfb-d4d5-414b-b8aa-0dc7ed6bc5b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32709
19728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3270919728
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.521234879
Short name T1819
Test name
Test status
Simulation time 10102122139 ps
CPU time 13.71 seconds
Started Jun 02 03:32:02 PM PDT 24
Finished Jun 02 03:32:16 PM PDT 24
Peak memory 205764 kb
Host smart-161e788e-06e1-44a9-9144-1046136b9298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52123
4879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.521234879
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.2004385211
Short name T1125
Test name
Test status
Simulation time 10040676741 ps
CPU time 14.69 seconds
Started Jun 02 03:32:00 PM PDT 24
Finished Jun 02 03:32:15 PM PDT 24
Peak memory 205732 kb
Host smart-24330086-d1fe-43dd-b491-10b7c3d89b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20043
85211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2004385211
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.342965284
Short name T1647
Test name
Test status
Simulation time 10133985337 ps
CPU time 13.29 seconds
Started Jun 02 03:32:03 PM PDT 24
Finished Jun 02 03:32:17 PM PDT 24
Peak memory 205684 kb
Host smart-511d75e9-7b06-4508-8506-7a1b0e171820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34296
5284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.342965284
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.2194283988
Short name T1800
Test name
Test status
Simulation time 10114385371 ps
CPU time 14 seconds
Started Jun 02 03:32:00 PM PDT 24
Finished Jun 02 03:32:14 PM PDT 24
Peak memory 205932 kb
Host smart-fd639fc9-8c43-48cb-aefc-687e70bd3f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21942
83988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.2194283988
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1111098229
Short name T1972
Test name
Test status
Simulation time 13217544340 ps
CPU time 15.99 seconds
Started Jun 02 03:32:03 PM PDT 24
Finished Jun 02 03:32:20 PM PDT 24
Peak memory 205452 kb
Host smart-d2b695a5-b743-496b-8bb9-5f2f0372e2d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11110
98229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1111098229
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.432393806
Short name T1759
Test name
Test status
Simulation time 10121402023 ps
CPU time 13.99 seconds
Started Jun 02 03:31:59 PM PDT 24
Finished Jun 02 03:32:13 PM PDT 24
Peak memory 205640 kb
Host smart-82d18c25-f20c-461c-91cb-4c2a36161302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43239
3806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.432393806
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.2888823473
Short name T383
Test name
Test status
Simulation time 16996512674 ps
CPU time 79.27 seconds
Started Jun 02 03:31:58 PM PDT 24
Finished Jun 02 03:33:18 PM PDT 24
Peak memory 205656 kb
Host smart-5501568d-7483-4c72-b988-bc32ce698f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28888
23473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.2888823473
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.2514190804
Short name T908
Test name
Test status
Simulation time 10061100571 ps
CPU time 13.27 seconds
Started Jun 02 03:31:59 PM PDT 24
Finished Jun 02 03:32:13 PM PDT 24
Peak memory 205608 kb
Host smart-9d121dcd-01cd-439c-bc22-155f1fa7f7f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25141
90804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.2514190804
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3081539885
Short name T118
Test name
Test status
Simulation time 10130415307 ps
CPU time 16.01 seconds
Started Jun 02 03:31:59 PM PDT 24
Finished Jun 02 03:32:16 PM PDT 24
Peak memory 205720 kb
Host smart-d2d52a51-9016-4362-805d-dd1fe80894d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30815
39885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3081539885
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.4278024767
Short name T543
Test name
Test status
Simulation time 10063458479 ps
CPU time 12.9 seconds
Started Jun 02 03:32:04 PM PDT 24
Finished Jun 02 03:32:18 PM PDT 24
Peak memory 205784 kb
Host smart-bc0f69c4-8184-4e8d-9371-3572c5e28c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42780
24767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.4278024767
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3592046998
Short name T1458
Test name
Test status
Simulation time 10086036804 ps
CPU time 15.45 seconds
Started Jun 02 03:32:01 PM PDT 24
Finished Jun 02 03:32:17 PM PDT 24
Peak memory 205740 kb
Host smart-5ded3148-4eeb-476a-b4c5-e215bc45efd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35920
46998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3592046998
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.297461114
Short name T782
Test name
Test status
Simulation time 10076574872 ps
CPU time 13.29 seconds
Started Jun 02 03:32:00 PM PDT 24
Finished Jun 02 03:32:14 PM PDT 24
Peak memory 205780 kb
Host smart-4356e500-de51-4c75-b1ce-dfefb3bd8dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29746
1114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.297461114
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.1856853473
Short name T183
Test name
Test status
Simulation time 10075633014 ps
CPU time 13.72 seconds
Started Jun 02 03:31:59 PM PDT 24
Finished Jun 02 03:32:14 PM PDT 24
Peak memory 205700 kb
Host smart-fcd0ca6a-aa44-4cc1-bb1f-e3a388b2e3b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18568
53473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.1856853473
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_eop_single_bit_handling.1448810028
Short name T939
Test name
Test status
Simulation time 10095176498 ps
CPU time 14.82 seconds
Started Jun 02 03:32:02 PM PDT 24
Finished Jun 02 03:32:17 PM PDT 24
Peak memory 205692 kb
Host smart-c7bb0dda-31fb-45c6-8a08-0a584a20eaad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14488
10028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_eop_single_bit_handling.1448810028
Directory /workspace/42.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.422072326
Short name T1909
Test name
Test status
Simulation time 10098101682 ps
CPU time 16.72 seconds
Started Jun 02 03:32:01 PM PDT 24
Finished Jun 02 03:32:18 PM PDT 24
Peak memory 205664 kb
Host smart-8a03f1de-dfac-40c0-b25d-268e6d2798f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42207
2326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.422072326
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.884530283
Short name T1245
Test name
Test status
Simulation time 10080460245 ps
CPU time 15.91 seconds
Started Jun 02 03:32:03 PM PDT 24
Finished Jun 02 03:32:20 PM PDT 24
Peak memory 205500 kb
Host smart-4cc7c5b9-7012-47ca-9e88-8785f00096a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88453
0283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.884530283
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.3278998336
Short name T809
Test name
Test status
Simulation time 26770290667 ps
CPU time 53.9 seconds
Started Jun 02 03:32:01 PM PDT 24
Finished Jun 02 03:32:56 PM PDT 24
Peak memory 205660 kb
Host smart-9de2db24-0651-4809-bf28-18fe9b1af79f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32789
98336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3278998336
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.1626439692
Short name T549
Test name
Test status
Simulation time 10106477977 ps
CPU time 13.75 seconds
Started Jun 02 03:32:05 PM PDT 24
Finished Jun 02 03:32:20 PM PDT 24
Peak memory 205628 kb
Host smart-a3d4ef19-3e95-4206-bd17-5cdd99378708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16264
39692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.1626439692
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.1661795308
Short name T303
Test name
Test status
Simulation time 10104450252 ps
CPU time 17.2 seconds
Started Jun 02 03:32:04 PM PDT 24
Finished Jun 02 03:32:22 PM PDT 24
Peak memory 205724 kb
Host smart-b1fa4a67-521b-4a4a-b6d7-40ebc398f74a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16617
95308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.1661795308
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.2247355157
Short name T1925
Test name
Test status
Simulation time 10081737706 ps
CPU time 14.94 seconds
Started Jun 02 03:32:03 PM PDT 24
Finished Jun 02 03:32:19 PM PDT 24
Peak memory 205692 kb
Host smart-53578ca9-8995-43b4-bed5-6b39ffb11f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22473
55157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.2247355157
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.3183670113
Short name T1233
Test name
Test status
Simulation time 10079480836 ps
CPU time 14.05 seconds
Started Jun 02 03:31:59 PM PDT 24
Finished Jun 02 03:32:14 PM PDT 24
Peak memory 205592 kb
Host smart-aa35118c-4529-48c5-a5a6-491a0e9c7762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31836
70113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.3183670113
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.3506663403
Short name T152
Test name
Test status
Simulation time 10078771166 ps
CPU time 15.08 seconds
Started Jun 02 03:32:01 PM PDT 24
Finished Jun 02 03:32:16 PM PDT 24
Peak memory 205668 kb
Host smart-57e915ae-cf94-4d0a-b555-0478efa830a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35066
63403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.3506663403
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.1414465788
Short name T1235
Test name
Test status
Simulation time 10040634401 ps
CPU time 14.94 seconds
Started Jun 02 03:31:57 PM PDT 24
Finished Jun 02 03:32:13 PM PDT 24
Peak memory 205676 kb
Host smart-83fe7f89-0f44-4880-92f2-fc6b77fa37dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14144
65788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.1414465788
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.3434662745
Short name T1879
Test name
Test status
Simulation time 10128849958 ps
CPU time 13.97 seconds
Started Jun 02 03:31:51 PM PDT 24
Finished Jun 02 03:32:06 PM PDT 24
Peak memory 205716 kb
Host smart-e28aab25-9121-48a5-8cd7-e5bc8cd74702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34346
62745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3434662745
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.3272034694
Short name T359
Test name
Test status
Simulation time 10081838033 ps
CPU time 15.09 seconds
Started Jun 02 03:32:03 PM PDT 24
Finished Jun 02 03:32:20 PM PDT 24
Peak memory 205760 kb
Host smart-8a765a73-3f44-4adc-a680-ebc44fd00e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32720
34694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.3272034694
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.277820837
Short name T1939
Test name
Test status
Simulation time 10075320871 ps
CPU time 13.82 seconds
Started Jun 02 03:32:03 PM PDT 24
Finished Jun 02 03:32:18 PM PDT 24
Peak memory 205652 kb
Host smart-6aed12b7-01b3-45f5-a537-e584cdd730d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27782
0837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.277820837
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.1702006121
Short name T445
Test name
Test status
Simulation time 16310589447 ps
CPU time 76.2 seconds
Started Jun 02 03:32:11 PM PDT 24
Finished Jun 02 03:33:28 PM PDT 24
Peak memory 205656 kb
Host smart-f85a1279-74c7-40fb-9c20-b7b9d4a7c1b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17020
06121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.1702006121
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.1723318234
Short name T1111
Test name
Test status
Simulation time 10140175587 ps
CPU time 13.1 seconds
Started Jun 02 03:32:12 PM PDT 24
Finished Jun 02 03:32:26 PM PDT 24
Peak memory 205696 kb
Host smart-7809e72a-22a0-45ee-8b4b-cf520189e480
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1723318234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.1723318234
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.1974893409
Short name T773
Test name
Test status
Simulation time 10070469510 ps
CPU time 15.48 seconds
Started Jun 02 03:32:11 PM PDT 24
Finished Jun 02 03:32:28 PM PDT 24
Peak memory 205600 kb
Host smart-0dd08375-3113-468d-b66f-1731056e5e91
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1974893409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.1974893409
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.3504040706
Short name T2026
Test name
Test status
Simulation time 10127183001 ps
CPU time 15.89 seconds
Started Jun 02 03:32:17 PM PDT 24
Finished Jun 02 03:32:34 PM PDT 24
Peak memory 205656 kb
Host smart-49497fa9-da66-4cf9-b0c1-52f444ac095b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35040
40706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.3504040706
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.120404522
Short name T605
Test name
Test status
Simulation time 13534854159 ps
CPU time 16.9 seconds
Started Jun 02 03:32:06 PM PDT 24
Finished Jun 02 03:32:24 PM PDT 24
Peak memory 205712 kb
Host smart-05008fd5-6de4-44f2-88d7-3242ffbc88d7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=120404522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.120404522
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.673944298
Short name T874
Test name
Test status
Simulation time 23276292935 ps
CPU time 25.65 seconds
Started Jun 02 03:32:03 PM PDT 24
Finished Jun 02 03:32:29 PM PDT 24
Peak memory 205712 kb
Host smart-a1195596-d6a9-4357-8435-4d869c6dfa57
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=673944298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.673944298
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.2113168309
Short name T1238
Test name
Test status
Simulation time 10063747465 ps
CPU time 12.8 seconds
Started Jun 02 03:32:05 PM PDT 24
Finished Jun 02 03:32:19 PM PDT 24
Peak memory 205688 kb
Host smart-8965deeb-1a4a-4e55-86a4-81c5679a093b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21131
68309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2113168309
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.1804022642
Short name T693
Test name
Test status
Simulation time 11242499996 ps
CPU time 17.93 seconds
Started Jun 02 03:32:19 PM PDT 24
Finished Jun 02 03:32:38 PM PDT 24
Peak memory 205696 kb
Host smart-1e2002a0-e36e-4c6e-9853-55c4742d8315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18040
22642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.1804022642
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.3439233158
Short name T1622
Test name
Test status
Simulation time 10061907569 ps
CPU time 13.88 seconds
Started Jun 02 03:32:11 PM PDT 24
Finished Jun 02 03:32:25 PM PDT 24
Peak memory 205636 kb
Host smart-09578a35-7ba6-4718-a51c-41c5a4d600a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34392
33158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.3439233158
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.1449125482
Short name T1224
Test name
Test status
Simulation time 10062341898 ps
CPU time 13.67 seconds
Started Jun 02 03:32:04 PM PDT 24
Finished Jun 02 03:32:18 PM PDT 24
Peak memory 205996 kb
Host smart-1466feb9-3dc6-4f68-819f-ab1d87a0e9da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14491
25482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1449125482
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.3853627918
Short name T1735
Test name
Test status
Simulation time 10707842512 ps
CPU time 14.09 seconds
Started Jun 02 03:32:04 PM PDT 24
Finished Jun 02 03:32:19 PM PDT 24
Peak memory 205560 kb
Host smart-ea2f815c-a986-4f11-be8b-a6726aa5f35a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38536
27918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.3853627918
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.3809210460
Short name T1380
Test name
Test status
Simulation time 10100557631 ps
CPU time 16.02 seconds
Started Jun 02 03:32:15 PM PDT 24
Finished Jun 02 03:32:32 PM PDT 24
Peak memory 205772 kb
Host smart-41818461-6ff7-43d9-b5f0-37d0def89e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38092
10460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.3809210460
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.1199163638
Short name T1298
Test name
Test status
Simulation time 10041173688 ps
CPU time 12.94 seconds
Started Jun 02 03:32:09 PM PDT 24
Finished Jun 02 03:32:23 PM PDT 24
Peak memory 205684 kb
Host smart-881713d7-d820-408e-8863-beb88d5945f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11991
63638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.1199163638
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1005403373
Short name T1754
Test name
Test status
Simulation time 10167220597 ps
CPU time 14.31 seconds
Started Jun 02 03:32:06 PM PDT 24
Finished Jun 02 03:32:21 PM PDT 24
Peak memory 205672 kb
Host smart-2382b18e-7b01-4396-a56b-74ca93266bc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10054
03373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1005403373
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.1136124154
Short name T1540
Test name
Test status
Simulation time 10117850791 ps
CPU time 13.75 seconds
Started Jun 02 03:32:05 PM PDT 24
Finished Jun 02 03:32:20 PM PDT 24
Peak memory 205572 kb
Host smart-8918c008-775b-4dad-aa8e-045dc518f5eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11361
24154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.1136124154
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.3078712477
Short name T1690
Test name
Test status
Simulation time 13172689232 ps
CPU time 16.27 seconds
Started Jun 02 03:32:06 PM PDT 24
Finished Jun 02 03:32:23 PM PDT 24
Peak memory 205784 kb
Host smart-6c9875a7-6ca9-4a87-991d-847a07f68e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30787
12477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.3078712477
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.1974221747
Short name T1140
Test name
Test status
Simulation time 10089794733 ps
CPU time 15.41 seconds
Started Jun 02 03:32:13 PM PDT 24
Finished Jun 02 03:32:29 PM PDT 24
Peak memory 205708 kb
Host smart-9d5d1c47-327f-43a0-afbb-d74e794b5fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19742
21747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.1974221747
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.2369588366
Short name T315
Test name
Test status
Simulation time 21499869567 ps
CPU time 97.54 seconds
Started Jun 02 03:32:05 PM PDT 24
Finished Jun 02 03:33:44 PM PDT 24
Peak memory 205640 kb
Host smart-f5acc7cf-7f30-4bf5-a184-5d90604a8f28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23695
88366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.2369588366
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1924282462
Short name T2002
Test name
Test status
Simulation time 10096929314 ps
CPU time 15.5 seconds
Started Jun 02 03:32:12 PM PDT 24
Finished Jun 02 03:32:29 PM PDT 24
Peak memory 205628 kb
Host smart-0403ceda-7534-4c84-84ea-017ca05a4f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19242
82462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1924282462
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.3269998618
Short name T111
Test name
Test status
Simulation time 10153684752 ps
CPU time 17.5 seconds
Started Jun 02 03:32:12 PM PDT 24
Finished Jun 02 03:32:30 PM PDT 24
Peak memory 205792 kb
Host smart-0bdcb10c-810c-481d-a71e-cfaa9bbd5ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32699
98618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.3269998618
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.276349960
Short name T890
Test name
Test status
Simulation time 10065214601 ps
CPU time 13.09 seconds
Started Jun 02 03:32:12 PM PDT 24
Finished Jun 02 03:32:26 PM PDT 24
Peak memory 205680 kb
Host smart-27f0cb69-609e-4cf9-83c6-164f85317a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27634
9960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.276349960
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.1220761046
Short name T304
Test name
Test status
Simulation time 10066944088 ps
CPU time 12.96 seconds
Started Jun 02 03:32:09 PM PDT 24
Finished Jun 02 03:32:23 PM PDT 24
Peak memory 205772 kb
Host smart-b4edf801-40a1-4210-80bd-837a8d77210f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12207
61046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.1220761046
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3272712210
Short name T1605
Test name
Test status
Simulation time 10055928456 ps
CPU time 13.62 seconds
Started Jun 02 03:32:07 PM PDT 24
Finished Jun 02 03:32:21 PM PDT 24
Peak memory 205736 kb
Host smart-c195515c-033d-41ec-ad1d-6c3a3c37cb9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32727
12210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3272712210
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.3756615578
Short name T954
Test name
Test status
Simulation time 10059924159 ps
CPU time 13.64 seconds
Started Jun 02 03:32:13 PM PDT 24
Finished Jun 02 03:32:27 PM PDT 24
Peak memory 205680 kb
Host smart-c8c6888f-89d7-4907-94c4-eba350410b10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37566
15578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.3756615578
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_eop_single_bit_handling.2099150228
Short name T665
Test name
Test status
Simulation time 10133757252 ps
CPU time 12.84 seconds
Started Jun 02 03:32:11 PM PDT 24
Finished Jun 02 03:32:25 PM PDT 24
Peak memory 205596 kb
Host smart-904b3fef-4618-4d46-b83c-f28675a9edf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20991
50228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_eop_single_bit_handling.2099150228
Directory /workspace/43.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.99454818
Short name T950
Test name
Test status
Simulation time 10043268130 ps
CPU time 13.87 seconds
Started Jun 02 03:32:07 PM PDT 24
Finished Jun 02 03:32:22 PM PDT 24
Peak memory 205700 kb
Host smart-8c62a1b9-f113-4246-a917-cb4fe2ff233d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99454
818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.99454818
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.386223466
Short name T1418
Test name
Test status
Simulation time 10034399995 ps
CPU time 14.42 seconds
Started Jun 02 03:32:20 PM PDT 24
Finished Jun 02 03:32:35 PM PDT 24
Peak memory 205748 kb
Host smart-2f361341-b5bd-4ff0-98fb-4de88e3bd316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38622
3466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.386223466
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.549167424
Short name T760
Test name
Test status
Simulation time 20998729093 ps
CPU time 36.03 seconds
Started Jun 02 03:32:03 PM PDT 24
Finished Jun 02 03:32:40 PM PDT 24
Peak memory 205648 kb
Host smart-670ebb63-1afd-49d7-982d-9da823d319b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54916
7424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.549167424
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.4195891824
Short name T743
Test name
Test status
Simulation time 10065774439 ps
CPU time 13.25 seconds
Started Jun 02 03:32:02 PM PDT 24
Finished Jun 02 03:32:17 PM PDT 24
Peak memory 205704 kb
Host smart-d8484ed6-3511-4059-8766-d84a9483e39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41958
91824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.4195891824
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3067666617
Short name T1760
Test name
Test status
Simulation time 10127665109 ps
CPU time 14.88 seconds
Started Jun 02 03:32:05 PM PDT 24
Finished Jun 02 03:32:20 PM PDT 24
Peak memory 205736 kb
Host smart-c66b0624-c4a6-403b-9131-68e4d4c092a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30676
66617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3067666617
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.3446424997
Short name T1917
Test name
Test status
Simulation time 10092273305 ps
CPU time 13.51 seconds
Started Jun 02 03:32:11 PM PDT 24
Finished Jun 02 03:32:26 PM PDT 24
Peak memory 205656 kb
Host smart-9281b269-34b3-45a6-bea8-4f84f9a8fc76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34464
24997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.3446424997
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.1514397820
Short name T1858
Test name
Test status
Simulation time 10041276030 ps
CPU time 15.07 seconds
Started Jun 02 03:32:03 PM PDT 24
Finished Jun 02 03:32:19 PM PDT 24
Peak memory 205596 kb
Host smart-b0f24500-6b9e-4ede-a6d7-67745bd1ae94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15143
97820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.1514397820
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.2044977960
Short name T725
Test name
Test status
Simulation time 10095244213 ps
CPU time 13.72 seconds
Started Jun 02 03:32:13 PM PDT 24
Finished Jun 02 03:32:28 PM PDT 24
Peak memory 205780 kb
Host smart-bc5f3e43-e711-472a-987b-a482844e68c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20449
77960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.2044977960
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3041836124
Short name T480
Test name
Test status
Simulation time 10062386398 ps
CPU time 16.44 seconds
Started Jun 02 03:32:05 PM PDT 24
Finished Jun 02 03:32:22 PM PDT 24
Peak memory 205756 kb
Host smart-4b439e36-ada5-403c-adbf-8bdfb7e6c372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30418
36124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3041836124
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.963196700
Short name T1954
Test name
Test status
Simulation time 10118611695 ps
CPU time 13.96 seconds
Started Jun 02 03:32:13 PM PDT 24
Finished Jun 02 03:32:28 PM PDT 24
Peak memory 205776 kb
Host smart-d0b86615-0f3b-40dc-ae6d-938f5b09787e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96319
6700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.963196700
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.305133571
Short name T642
Test name
Test status
Simulation time 10059425071 ps
CPU time 13.75 seconds
Started Jun 02 03:32:07 PM PDT 24
Finished Jun 02 03:32:21 PM PDT 24
Peak memory 205684 kb
Host smart-4df0d887-f5c3-4200-ad7b-01ae2d95a2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30513
3571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.305133571
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.2521620812
Short name T1159
Test name
Test status
Simulation time 10070918803 ps
CPU time 14.07 seconds
Started Jun 02 03:32:03 PM PDT 24
Finished Jun 02 03:32:18 PM PDT 24
Peak memory 205676 kb
Host smart-3dda1e0e-a86c-4653-aaa3-1b4a90693f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25216
20812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2521620812
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.918890583
Short name T412
Test name
Test status
Simulation time 20069411617 ps
CPU time 311.1 seconds
Started Jun 02 03:32:05 PM PDT 24
Finished Jun 02 03:37:18 PM PDT 24
Peak memory 205632 kb
Host smart-84098384-6a1e-4d0f-b7c6-1599b89e47ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91889
0583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.918890583
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.4091525472
Short name T1009
Test name
Test status
Simulation time 10137116414 ps
CPU time 13.11 seconds
Started Jun 02 03:32:18 PM PDT 24
Finished Jun 02 03:32:32 PM PDT 24
Peak memory 205724 kb
Host smart-70470e59-6165-4085-8ba5-dbfa4168f1f3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4091525472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.4091525472
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.2549004633
Short name T635
Test name
Test status
Simulation time 10056937094 ps
CPU time 12.73 seconds
Started Jun 02 03:32:15 PM PDT 24
Finished Jun 02 03:32:29 PM PDT 24
Peak memory 205612 kb
Host smart-0e103347-74fa-4bec-96fe-70bf0f4be6ee
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2549004633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.2549004633
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.479851075
Short name T1676
Test name
Test status
Simulation time 10156585446 ps
CPU time 13.38 seconds
Started Jun 02 03:32:18 PM PDT 24
Finished Jun 02 03:32:32 PM PDT 24
Peak memory 205708 kb
Host smart-e10a82b1-9a91-45a0-aeba-2b297d169a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47985
1075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.479851075
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.3760166184
Short name T1460
Test name
Test status
Simulation time 13441070006 ps
CPU time 18.51 seconds
Started Jun 02 03:32:19 PM PDT 24
Finished Jun 02 03:32:39 PM PDT 24
Peak memory 205648 kb
Host smart-45268bfe-7111-425f-b371-571a2fda18e2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3760166184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.3760166184
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.898192541
Short name T1982
Test name
Test status
Simulation time 23287297911 ps
CPU time 25.98 seconds
Started Jun 02 03:32:15 PM PDT 24
Finished Jun 02 03:32:41 PM PDT 24
Peak memory 205816 kb
Host smart-603c5e00-13ea-4e85-8de8-f89c116c8310
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=898192541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.898192541
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.2762873143
Short name T1986
Test name
Test status
Simulation time 10051833516 ps
CPU time 14 seconds
Started Jun 02 03:32:09 PM PDT 24
Finished Jun 02 03:32:24 PM PDT 24
Peak memory 205672 kb
Host smart-cb7f912a-a39d-43a7-a7b0-53254c36c7b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27628
73143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.2762873143
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.1428101150
Short name T177
Test name
Test status
Simulation time 10658326168 ps
CPU time 18.01 seconds
Started Jun 02 03:32:18 PM PDT 24
Finished Jun 02 03:32:37 PM PDT 24
Peak memory 205724 kb
Host smart-d8097abc-5e21-462d-8cf1-692a893547b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14281
01150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.1428101150
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.905705506
Short name T1429
Test name
Test status
Simulation time 10060945424 ps
CPU time 13.48 seconds
Started Jun 02 03:32:20 PM PDT 24
Finished Jun 02 03:32:34 PM PDT 24
Peak memory 205752 kb
Host smart-d1b26f34-fc6d-4964-a0b4-55cbfdb91cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90570
5506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.905705506
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.2592773585
Short name T1432
Test name
Test status
Simulation time 10056931932 ps
CPU time 12.98 seconds
Started Jun 02 03:32:12 PM PDT 24
Finished Jun 02 03:32:26 PM PDT 24
Peak memory 205656 kb
Host smart-33b2ef22-f205-4766-8ad5-65e0a99d9b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25927
73585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.2592773585
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.1325788138
Short name T1105
Test name
Test status
Simulation time 10642208561 ps
CPU time 16.38 seconds
Started Jun 02 03:32:14 PM PDT 24
Finished Jun 02 03:32:31 PM PDT 24
Peak memory 205700 kb
Host smart-07f67ab8-465f-46ab-86d2-4b3418f14e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13257
88138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.1325788138
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.3616743146
Short name T715
Test name
Test status
Simulation time 10180005707 ps
CPU time 15.73 seconds
Started Jun 02 03:32:11 PM PDT 24
Finished Jun 02 03:32:28 PM PDT 24
Peak memory 205660 kb
Host smart-4931cd8e-473e-4387-b528-e4149b27b300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36167
43146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.3616743146
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.2074970521
Short name T1479
Test name
Test status
Simulation time 10107629075 ps
CPU time 13.14 seconds
Started Jun 02 03:32:13 PM PDT 24
Finished Jun 02 03:32:27 PM PDT 24
Peak memory 205604 kb
Host smart-108d89da-f91b-491e-9e9f-a0a43600ac0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20749
70521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.2074970521
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.3943241329
Short name T467
Test name
Test status
Simulation time 10118853354 ps
CPU time 12.74 seconds
Started Jun 02 03:32:17 PM PDT 24
Finished Jun 02 03:32:30 PM PDT 24
Peak memory 205760 kb
Host smart-a92ebafc-2914-4f04-97ee-4b9e691345ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39432
41329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.3943241329
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3295766489
Short name T1223
Test name
Test status
Simulation time 10131268151 ps
CPU time 13.49 seconds
Started Jun 02 03:32:09 PM PDT 24
Finished Jun 02 03:32:23 PM PDT 24
Peak memory 205764 kb
Host smart-24cbf05e-d37e-4f18-be2f-f7ccb7a1ff32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32957
66489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3295766489
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.2209583916
Short name T81
Test name
Test status
Simulation time 10124409640 ps
CPU time 13.24 seconds
Started Jun 02 03:32:12 PM PDT 24
Finished Jun 02 03:32:26 PM PDT 24
Peak memory 205704 kb
Host smart-099d3c65-5bc9-42ad-af99-d82fbfdf7c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22095
83916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.2209583916
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.2651754815
Short name T613
Test name
Test status
Simulation time 13189015970 ps
CPU time 19.27 seconds
Started Jun 02 03:32:11 PM PDT 24
Finished Jun 02 03:32:31 PM PDT 24
Peak memory 205640 kb
Host smart-89179e54-6dba-44f4-a414-5c72dc9d5be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26517
54815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.2651754815
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.2595361918
Short name T677
Test name
Test status
Simulation time 10093903052 ps
CPU time 13.36 seconds
Started Jun 02 03:32:13 PM PDT 24
Finished Jun 02 03:32:27 PM PDT 24
Peak memory 205736 kb
Host smart-9cc3bfbe-89de-47a5-bfa4-79cc39190f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25953
61918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.2595361918
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.2110599960
Short name T891
Test name
Test status
Simulation time 17510387268 ps
CPU time 71.02 seconds
Started Jun 02 03:32:12 PM PDT 24
Finished Jun 02 03:33:24 PM PDT 24
Peak memory 205692 kb
Host smart-c74067ab-36bf-4b10-88f2-96882a2f6290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21105
99960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.2110599960
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.127110331
Short name T373
Test name
Test status
Simulation time 10061537015 ps
CPU time 15.31 seconds
Started Jun 02 03:32:12 PM PDT 24
Finished Jun 02 03:32:34 PM PDT 24
Peak memory 205604 kb
Host smart-c1cf88eb-f1d5-4eef-ae86-a03914bebc58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12711
0331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.127110331
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.152456475
Short name T113
Test name
Test status
Simulation time 10112062881 ps
CPU time 15.45 seconds
Started Jun 02 03:32:09 PM PDT 24
Finished Jun 02 03:32:25 PM PDT 24
Peak memory 205668 kb
Host smart-6cecb769-e649-447c-bc7e-1961fbda5bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15245
6475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.152456475
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.3210039616
Short name T1209
Test name
Test status
Simulation time 10076462866 ps
CPU time 12.99 seconds
Started Jun 02 03:32:16 PM PDT 24
Finished Jun 02 03:32:29 PM PDT 24
Peak memory 205688 kb
Host smart-975ca1ac-01cf-4286-8b88-9dd54909b376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32100
39616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.3210039616
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.882163679
Short name T593
Test name
Test status
Simulation time 10111304662 ps
CPU time 13.58 seconds
Started Jun 02 03:32:19 PM PDT 24
Finished Jun 02 03:32:33 PM PDT 24
Peak memory 205780 kb
Host smart-216d287a-b765-4e7a-9cd6-e843fe74e643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88216
3679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.882163679
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.1527053848
Short name T1777
Test name
Test status
Simulation time 10062296582 ps
CPU time 13.12 seconds
Started Jun 02 03:32:12 PM PDT 24
Finished Jun 02 03:32:26 PM PDT 24
Peak memory 205764 kb
Host smart-0c41eab0-d295-40eb-be99-2b944e5e933d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15270
53848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.1527053848
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.3880985030
Short name T90
Test name
Test status
Simulation time 10057901101 ps
CPU time 12.9 seconds
Started Jun 02 03:32:17 PM PDT 24
Finished Jun 02 03:32:30 PM PDT 24
Peak memory 205936 kb
Host smart-9aa2a2ea-9b96-4460-80e0-ae6ad872ae25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38809
85030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.3880985030
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_eop_single_bit_handling.2833961909
Short name T1020
Test name
Test status
Simulation time 10073660079 ps
CPU time 13.3 seconds
Started Jun 02 03:32:12 PM PDT 24
Finished Jun 02 03:32:27 PM PDT 24
Peak memory 205640 kb
Host smart-ca578269-9659-4b02-a98a-671bda23b53c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28339
61909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_eop_single_bit_handling.2833961909
Directory /workspace/44.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3230441973
Short name T67
Test name
Test status
Simulation time 10081362998 ps
CPU time 14.14 seconds
Started Jun 02 03:32:17 PM PDT 24
Finished Jun 02 03:32:32 PM PDT 24
Peak memory 205732 kb
Host smart-854b60f3-9383-46d5-b3b8-2cae9fb43617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32304
41973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3230441973
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.195403787
Short name T679
Test name
Test status
Simulation time 10056948462 ps
CPU time 14.98 seconds
Started Jun 02 03:32:14 PM PDT 24
Finished Jun 02 03:32:30 PM PDT 24
Peak memory 205664 kb
Host smart-ddb8bd55-2864-426c-b8c2-166958f594c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19540
3787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.195403787
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2526401428
Short name T783
Test name
Test status
Simulation time 32619796447 ps
CPU time 60.56 seconds
Started Jun 02 03:32:15 PM PDT 24
Finished Jun 02 03:33:17 PM PDT 24
Peak memory 205652 kb
Host smart-f2b8e185-2712-469c-9f6f-9440a65bd62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25264
01428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2526401428
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.1211748927
Short name T379
Test name
Test status
Simulation time 10058539636 ps
CPU time 16.72 seconds
Started Jun 02 03:32:12 PM PDT 24
Finished Jun 02 03:32:30 PM PDT 24
Peak memory 205760 kb
Host smart-54e8c20d-2e0d-4b29-aaff-1b44ebffdea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12117
48927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.1211748927
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1615975980
Short name T902
Test name
Test status
Simulation time 10072891003 ps
CPU time 13.53 seconds
Started Jun 02 03:32:17 PM PDT 24
Finished Jun 02 03:32:32 PM PDT 24
Peak memory 205628 kb
Host smart-9a6d0075-9437-4c66-8fe0-e745c7163741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16159
75980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1615975980
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.2811409504
Short name T1731
Test name
Test status
Simulation time 10074724286 ps
CPU time 15.82 seconds
Started Jun 02 03:32:15 PM PDT 24
Finished Jun 02 03:32:32 PM PDT 24
Peak memory 205648 kb
Host smart-4d81f340-187d-4a68-9df0-8a4ec1611226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28114
09504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.2811409504
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.799003179
Short name T1428
Test name
Test status
Simulation time 10116058127 ps
CPU time 13.13 seconds
Started Jun 02 03:32:17 PM PDT 24
Finished Jun 02 03:32:31 PM PDT 24
Peak memory 205716 kb
Host smart-57510aeb-7560-43af-b805-e1cb34cccae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79900
3179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.799003179
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.2234840089
Short name T816
Test name
Test status
Simulation time 10083809273 ps
CPU time 15.45 seconds
Started Jun 02 03:32:17 PM PDT 24
Finished Jun 02 03:32:33 PM PDT 24
Peak memory 205980 kb
Host smart-7d16d9e6-4035-43dd-aad5-10f819d2c919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22348
40089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2234840089
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3269570148
Short name T1688
Test name
Test status
Simulation time 10057111687 ps
CPU time 13.76 seconds
Started Jun 02 03:32:15 PM PDT 24
Finished Jun 02 03:32:30 PM PDT 24
Peak memory 205748 kb
Host smart-25027a2e-e8bc-4780-9c75-0b3c264b7c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32695
70148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3269570148
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.3511996280
Short name T756
Test name
Test status
Simulation time 10142113930 ps
CPU time 15.15 seconds
Started Jun 02 03:32:07 PM PDT 24
Finished Jun 02 03:32:23 PM PDT 24
Peak memory 205640 kb
Host smart-4bd3754c-d737-4354-9773-be3d2587f8f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35119
96280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.3511996280
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2381736963
Short name T1548
Test name
Test status
Simulation time 10122305480 ps
CPU time 13.36 seconds
Started Jun 02 03:32:13 PM PDT 24
Finished Jun 02 03:32:27 PM PDT 24
Peak memory 205724 kb
Host smart-ca6e7387-298e-43da-89f8-c3d25edded51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23817
36963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2381736963
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.178641075
Short name T810
Test name
Test status
Simulation time 10077313355 ps
CPU time 13.67 seconds
Started Jun 02 03:32:15 PM PDT 24
Finished Jun 02 03:32:29 PM PDT 24
Peak memory 205672 kb
Host smart-af03ec1f-25d7-4212-8c8a-752fde11db64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17864
1075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.178641075
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.2847097904
Short name T1813
Test name
Test status
Simulation time 20378377257 ps
CPU time 310.72 seconds
Started Jun 02 03:32:21 PM PDT 24
Finished Jun 02 03:37:33 PM PDT 24
Peak memory 205616 kb
Host smart-8bce02df-d760-4c34-9f2d-411fd90ff5ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28470
97904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.2847097904
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.3182255548
Short name T591
Test name
Test status
Simulation time 10156989900 ps
CPU time 14.31 seconds
Started Jun 02 03:32:24 PM PDT 24
Finished Jun 02 03:32:39 PM PDT 24
Peak memory 205564 kb
Host smart-35faa6c0-c526-41aa-9015-0337121cc44d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3182255548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.3182255548
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.2793342184
Short name T796
Test name
Test status
Simulation time 10057662171 ps
CPU time 15.75 seconds
Started Jun 02 03:32:31 PM PDT 24
Finished Jun 02 03:32:48 PM PDT 24
Peak memory 205752 kb
Host smart-64a2993a-9284-4130-a5be-4a9a3f3c818b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2793342184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.2793342184
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.2077642068
Short name T1374
Test name
Test status
Simulation time 10135969733 ps
CPU time 13.69 seconds
Started Jun 02 03:32:29 PM PDT 24
Finished Jun 02 03:32:44 PM PDT 24
Peak memory 205760 kb
Host smart-48926ff2-9b30-41c8-b745-5c6ade012228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20776
42068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.2077642068
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.174365132
Short name T1775
Test name
Test status
Simulation time 13457157379 ps
CPU time 16.09 seconds
Started Jun 02 03:32:25 PM PDT 24
Finished Jun 02 03:32:42 PM PDT 24
Peak memory 205708 kb
Host smart-cdca0dce-fd5f-487d-8496-2a2f9d870c1d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=174365132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.174365132
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.1722882013
Short name T768
Test name
Test status
Simulation time 23215889175 ps
CPU time 26.99 seconds
Started Jun 02 03:32:33 PM PDT 24
Finished Jun 02 03:33:01 PM PDT 24
Peak memory 205732 kb
Host smart-57b18163-1764-41c0-8450-7bfb69f528d2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1722882013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.1722882013
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.3610434686
Short name T1720
Test name
Test status
Simulation time 10046769175 ps
CPU time 13.81 seconds
Started Jun 02 03:32:17 PM PDT 24
Finished Jun 02 03:32:32 PM PDT 24
Peak memory 205592 kb
Host smart-7fc97d4e-9cb4-414f-a826-3100b8b4ffce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36104
34686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3610434686
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.2927695713
Short name T167
Test name
Test status
Simulation time 10758601059 ps
CPU time 14.85 seconds
Started Jun 02 03:32:23 PM PDT 24
Finished Jun 02 03:32:39 PM PDT 24
Peak memory 205696 kb
Host smart-0da0c5fd-0dc1-4a0e-af2e-adcdd6aadbc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29276
95713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.2927695713
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.3880138214
Short name T1144
Test name
Test status
Simulation time 10051398189 ps
CPU time 13.13 seconds
Started Jun 02 03:32:17 PM PDT 24
Finished Jun 02 03:32:32 PM PDT 24
Peak memory 205624 kb
Host smart-b0e682dd-6d80-4d06-bd09-28534681d073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38801
38214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.3880138214
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.3374875124
Short name T832
Test name
Test status
Simulation time 10047024963 ps
CPU time 12.71 seconds
Started Jun 02 03:32:30 PM PDT 24
Finished Jun 02 03:32:44 PM PDT 24
Peak memory 205696 kb
Host smart-9ecbf516-c602-4bbc-bb30-2f8aa549a3e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33748
75124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.3374875124
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.3557014330
Short name T660
Test name
Test status
Simulation time 10802561117 ps
CPU time 13.68 seconds
Started Jun 02 03:32:20 PM PDT 24
Finished Jun 02 03:32:35 PM PDT 24
Peak memory 205788 kb
Host smart-069079e0-ebb2-4d07-b496-507d4eecc524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35570
14330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.3557014330
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.3210509819
Short name T1356
Test name
Test status
Simulation time 10231545150 ps
CPU time 17.21 seconds
Started Jun 02 03:32:18 PM PDT 24
Finished Jun 02 03:32:36 PM PDT 24
Peak memory 205732 kb
Host smart-39ee91c9-14f7-444a-b5cd-dd7c77cd5c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32105
09819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.3210509819
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.3377679303
Short name T1310
Test name
Test status
Simulation time 10065826133 ps
CPU time 13.43 seconds
Started Jun 02 03:32:29 PM PDT 24
Finished Jun 02 03:32:43 PM PDT 24
Peak memory 205756 kb
Host smart-3859dbda-5df7-49ca-9f73-d6a1a627611d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33776
79303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.3377679303
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1232182439
Short name T1061
Test name
Test status
Simulation time 10055013030 ps
CPU time 13.89 seconds
Started Jun 02 03:32:26 PM PDT 24
Finished Jun 02 03:32:40 PM PDT 24
Peak memory 205680 kb
Host smart-df1edda1-330e-43ce-aae4-c115b2b66fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12321
82439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1232182439
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.234749188
Short name T1184
Test name
Test status
Simulation time 10116443932 ps
CPU time 13.18 seconds
Started Jun 02 03:32:25 PM PDT 24
Finished Jun 02 03:32:39 PM PDT 24
Peak memory 205600 kb
Host smart-7d18108e-a8c4-41cb-852d-26a037784b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23474
9188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.234749188
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.969891006
Short name T709
Test name
Test status
Simulation time 10120494027 ps
CPU time 13.57 seconds
Started Jun 02 03:32:20 PM PDT 24
Finished Jun 02 03:32:35 PM PDT 24
Peak memory 205584 kb
Host smart-096a9c63-7387-4608-b36c-fba5866ec8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96989
1006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.969891006
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.4191461136
Short name T47
Test name
Test status
Simulation time 13201783866 ps
CPU time 18.13 seconds
Started Jun 02 03:32:18 PM PDT 24
Finished Jun 02 03:32:37 PM PDT 24
Peak memory 205864 kb
Host smart-4b019f43-4d22-4792-ba0a-b400f67c1945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41914
61136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.4191461136
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.437882174
Short name T1851
Test name
Test status
Simulation time 10114540887 ps
CPU time 12.93 seconds
Started Jun 02 03:32:17 PM PDT 24
Finished Jun 02 03:32:31 PM PDT 24
Peak memory 205612 kb
Host smart-3d865f46-74b2-4009-9574-74f16332cb5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43788
2174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.437882174
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.3991654642
Short name T747
Test name
Test status
Simulation time 23292855066 ps
CPU time 101.48 seconds
Started Jun 02 03:32:23 PM PDT 24
Finished Jun 02 03:34:04 PM PDT 24
Peak memory 205708 kb
Host smart-339be599-a3e0-4554-9da3-73c943468796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39916
54642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.3991654642
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2481386112
Short name T864
Test name
Test status
Simulation time 10044394385 ps
CPU time 12.99 seconds
Started Jun 02 03:32:19 PM PDT 24
Finished Jun 02 03:32:33 PM PDT 24
Peak memory 205644 kb
Host smart-fc01123d-8408-4e18-bbfc-ecf1cc22f057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24813
86112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2481386112
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.1208253164
Short name T1762
Test name
Test status
Simulation time 10076803136 ps
CPU time 14.6 seconds
Started Jun 02 03:32:19 PM PDT 24
Finished Jun 02 03:32:34 PM PDT 24
Peak memory 205760 kb
Host smart-51e5f95f-10f3-4f30-b18a-ce9c7b8edd96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12082
53164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.1208253164
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.1200342146
Short name T323
Test name
Test status
Simulation time 10077138769 ps
CPU time 16.23 seconds
Started Jun 02 03:32:23 PM PDT 24
Finished Jun 02 03:32:39 PM PDT 24
Peak memory 205752 kb
Host smart-9ef13d8c-aee1-4ffd-9962-2e3d7e0171d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12003
42146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.1200342146
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.2622276869
Short name T1727
Test name
Test status
Simulation time 10052400548 ps
CPU time 13.03 seconds
Started Jun 02 03:32:19 PM PDT 24
Finished Jun 02 03:32:33 PM PDT 24
Peak memory 205768 kb
Host smart-ae1571d9-c240-404b-a7b1-b0bbf04bc3fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26222
76869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.2622276869
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.1754460887
Short name T1628
Test name
Test status
Simulation time 10049770632 ps
CPU time 13.74 seconds
Started Jun 02 03:32:27 PM PDT 24
Finished Jun 02 03:32:42 PM PDT 24
Peak memory 205768 kb
Host smart-738410c1-ecc4-4037-8596-796e372fecc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17544
60887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1754460887
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.3072907245
Short name T158
Test name
Test status
Simulation time 10054005540 ps
CPU time 15.21 seconds
Started Jun 02 03:32:24 PM PDT 24
Finished Jun 02 03:32:39 PM PDT 24
Peak memory 205772 kb
Host smart-346d1a23-b31b-446c-a5d1-7eab7a8e7544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30729
07245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.3072907245
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_eop_single_bit_handling.2931391294
Short name T1283
Test name
Test status
Simulation time 10083960262 ps
CPU time 15.52 seconds
Started Jun 02 03:32:24 PM PDT 24
Finished Jun 02 03:32:40 PM PDT 24
Peak memory 205588 kb
Host smart-6bc19601-7146-4441-85c5-92da191c7c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29313
91294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_eop_single_bit_handling.2931391294
Directory /workspace/45.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.2732955204
Short name T855
Test name
Test status
Simulation time 10047569405 ps
CPU time 14.52 seconds
Started Jun 02 03:32:24 PM PDT 24
Finished Jun 02 03:32:39 PM PDT 24
Peak memory 205652 kb
Host smart-716de7c8-27d3-4945-b1c1-c81e445aad2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27329
55204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.2732955204
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.937092659
Short name T1153
Test name
Test status
Simulation time 10048364586 ps
CPU time 15.38 seconds
Started Jun 02 03:32:23 PM PDT 24
Finished Jun 02 03:32:39 PM PDT 24
Peak memory 205656 kb
Host smart-fec176fc-5d84-440b-80f8-5e58edb1c711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93709
2659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.937092659
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.3301152955
Short name T161
Test name
Test status
Simulation time 31684117714 ps
CPU time 57.48 seconds
Started Jun 02 03:32:20 PM PDT 24
Finished Jun 02 03:33:19 PM PDT 24
Peak memory 205696 kb
Host smart-011481b6-73ee-4f30-89cf-f52051e12d4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33011
52955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.3301152955
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.2280588499
Short name T1389
Test name
Test status
Simulation time 10083608575 ps
CPU time 14.08 seconds
Started Jun 02 03:32:17 PM PDT 24
Finished Jun 02 03:32:32 PM PDT 24
Peak memory 205752 kb
Host smart-fd3ce4ae-f2d2-4943-9da6-6ad59388be52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22805
88499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.2280588499
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.2869628390
Short name T1648
Test name
Test status
Simulation time 10107337057 ps
CPU time 14.36 seconds
Started Jun 02 03:32:27 PM PDT 24
Finished Jun 02 03:32:43 PM PDT 24
Peak memory 205792 kb
Host smart-f28e545e-9f23-4d2f-afdf-2a79f136b586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28696
28390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.2869628390
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.2566707773
Short name T972
Test name
Test status
Simulation time 10105181210 ps
CPU time 13.33 seconds
Started Jun 02 03:32:17 PM PDT 24
Finished Jun 02 03:32:31 PM PDT 24
Peak memory 205668 kb
Host smart-6c0aa1ac-7956-49d6-ae57-1be945a55ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25667
07773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.2566707773
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.2484498997
Short name T459
Test name
Test status
Simulation time 10109536048 ps
CPU time 12.97 seconds
Started Jun 02 03:32:21 PM PDT 24
Finished Jun 02 03:32:35 PM PDT 24
Peak memory 205736 kb
Host smart-4ed54147-e47c-4367-bc9a-1455c0b305be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24844
98997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.2484498997
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3219017693
Short name T137
Test name
Test status
Simulation time 10053856510 ps
CPU time 13.97 seconds
Started Jun 02 03:32:24 PM PDT 24
Finished Jun 02 03:32:39 PM PDT 24
Peak memory 205732 kb
Host smart-88205695-ceb2-4e13-b7b0-aa33922b2ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32190
17693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3219017693
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.4239228407
Short name T69
Test name
Test status
Simulation time 10072470822 ps
CPU time 13.25 seconds
Started Jun 02 03:32:20 PM PDT 24
Finished Jun 02 03:32:34 PM PDT 24
Peak memory 205760 kb
Host smart-5b4d35d3-07bd-4ec2-8f8a-904ddb87a1e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42392
28407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.4239228407
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.24270794
Short name T800
Test name
Test status
Simulation time 10128600921 ps
CPU time 14.24 seconds
Started Jun 02 03:32:25 PM PDT 24
Finished Jun 02 03:32:40 PM PDT 24
Peak memory 205728 kb
Host smart-3014c940-293a-4867-a0bc-ad6b717bbf57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24270
794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.24270794
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.992785415
Short name T75
Test name
Test status
Simulation time 10083610883 ps
CPU time 13.78 seconds
Started Jun 02 03:32:32 PM PDT 24
Finished Jun 02 03:32:47 PM PDT 24
Peak memory 205632 kb
Host smart-b5c3b984-9cf2-4bfb-ac00-0ce3d6b9c41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99278
5415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.992785415
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.3344329133
Short name T746
Test name
Test status
Simulation time 10073539777 ps
CPU time 12.99 seconds
Started Jun 02 03:32:29 PM PDT 24
Finished Jun 02 03:32:43 PM PDT 24
Peak memory 205740 kb
Host smart-a2b75015-44e8-49ff-baaf-17ee6b428e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33443
29133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.3344329133
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.1441934339
Short name T1088
Test name
Test status
Simulation time 15005285202 ps
CPU time 154.15 seconds
Started Jun 02 03:32:17 PM PDT 24
Finished Jun 02 03:34:52 PM PDT 24
Peak memory 205592 kb
Host smart-79475594-c573-4b26-a1d3-d34ddc8f869f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14419
34339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.1441934339
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.165492568
Short name T444
Test name
Test status
Simulation time 10189741719 ps
CPU time 13.03 seconds
Started Jun 02 03:32:29 PM PDT 24
Finished Jun 02 03:32:43 PM PDT 24
Peak memory 205756 kb
Host smart-f4cd9049-8a59-4696-85fc-abfaee41988b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=165492568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.165492568
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.2200443807
Short name T291
Test name
Test status
Simulation time 10053721115 ps
CPU time 14.91 seconds
Started Jun 02 03:32:32 PM PDT 24
Finished Jun 02 03:32:48 PM PDT 24
Peak memory 205688 kb
Host smart-1617309c-b20d-4059-a165-6d0d9a080b2a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2200443807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.2200443807
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.1732272010
Short name T1162
Test name
Test status
Simulation time 10099062553 ps
CPU time 13.79 seconds
Started Jun 02 03:32:30 PM PDT 24
Finished Jun 02 03:32:45 PM PDT 24
Peak memory 205728 kb
Host smart-62592727-f6bf-4114-adfd-09c01c164dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17322
72010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.1732272010
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.2442342370
Short name T982
Test name
Test status
Simulation time 13368018936 ps
CPU time 16.7 seconds
Started Jun 02 03:32:28 PM PDT 24
Finished Jun 02 03:32:45 PM PDT 24
Peak memory 205692 kb
Host smart-34cb8b04-03e5-4380-afba-4e8c0830d6ca
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2442342370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.2442342370
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.2037265860
Short name T1482
Test name
Test status
Simulation time 23290352580 ps
CPU time 26.62 seconds
Started Jun 02 03:32:24 PM PDT 24
Finished Jun 02 03:32:52 PM PDT 24
Peak memory 205868 kb
Host smart-8aba907d-03c1-4b6a-8fb5-044c1161f241
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2037265860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.2037265860
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.517629401
Short name T1321
Test name
Test status
Simulation time 10051724889 ps
CPU time 14.89 seconds
Started Jun 02 03:32:32 PM PDT 24
Finished Jun 02 03:32:48 PM PDT 24
Peak memory 205560 kb
Host smart-43b4b401-0796-4202-836f-df168227c0b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51762
9401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.517629401
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.2512742828
Short name T76
Test name
Test status
Simulation time 11242267731 ps
CPU time 15.09 seconds
Started Jun 02 03:32:31 PM PDT 24
Finished Jun 02 03:32:47 PM PDT 24
Peak memory 205748 kb
Host smart-3790bbfd-b864-4750-a965-9ad932995444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25127
42828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.2512742828
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.2599081719
Short name T1593
Test name
Test status
Simulation time 10082908258 ps
CPU time 14.19 seconds
Started Jun 02 03:32:26 PM PDT 24
Finished Jun 02 03:32:41 PM PDT 24
Peak memory 205652 kb
Host smart-18f298d4-0405-4e6c-8bba-72934a7dc081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25990
81719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.2599081719
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.3926874852
Short name T744
Test name
Test status
Simulation time 10052474072 ps
CPU time 12.78 seconds
Started Jun 02 03:32:25 PM PDT 24
Finished Jun 02 03:32:38 PM PDT 24
Peak memory 205672 kb
Host smart-573be5f1-2a36-430c-a2b4-6de8b21561de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39268
74852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3926874852
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.3208943934
Short name T871
Test name
Test status
Simulation time 10917980979 ps
CPU time 16.02 seconds
Started Jun 02 03:32:26 PM PDT 24
Finished Jun 02 03:32:43 PM PDT 24
Peak memory 205684 kb
Host smart-9143874e-9671-4233-a2b7-1abff0580010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32089
43934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.3208943934
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.1262792774
Short name T1246
Test name
Test status
Simulation time 10077569412 ps
CPU time 15.62 seconds
Started Jun 02 03:32:29 PM PDT 24
Finished Jun 02 03:32:46 PM PDT 24
Peak memory 205588 kb
Host smart-f63c1eb7-c0ac-4c3f-803f-9845d38b1904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12627
92774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.1262792774
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.381719436
Short name T1763
Test name
Test status
Simulation time 10107721158 ps
CPU time 13.7 seconds
Started Jun 02 03:32:36 PM PDT 24
Finished Jun 02 03:32:50 PM PDT 24
Peak memory 205600 kb
Host smart-59959720-f7e4-437b-bd20-467b2e28159a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38171
9436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.381719436
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3352396612
Short name T1409
Test name
Test status
Simulation time 10065246555 ps
CPU time 12.85 seconds
Started Jun 02 03:32:40 PM PDT 24
Finished Jun 02 03:32:53 PM PDT 24
Peak memory 205396 kb
Host smart-fc6fa9b1-98ee-446d-9e08-e88cf7d204db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33523
96612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3352396612
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.4269016416
Short name T1181
Test name
Test status
Simulation time 10089863538 ps
CPU time 15.22 seconds
Started Jun 02 03:32:30 PM PDT 24
Finished Jun 02 03:32:46 PM PDT 24
Peak memory 205660 kb
Host smart-f21a1c0a-703e-4ee0-8d82-9b1eefd1bf34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42690
16416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.4269016416
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.2437364620
Short name T2016
Test name
Test status
Simulation time 10100513289 ps
CPU time 14.86 seconds
Started Jun 02 03:32:27 PM PDT 24
Finished Jun 02 03:32:43 PM PDT 24
Peak memory 205704 kb
Host smart-ed5d5667-7a53-4dfb-8583-a0dc9a2182c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24373
64620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.2437364620
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.3579500623
Short name T212
Test name
Test status
Simulation time 13255990551 ps
CPU time 16.48 seconds
Started Jun 02 03:32:31 PM PDT 24
Finished Jun 02 03:32:48 PM PDT 24
Peak memory 205632 kb
Host smart-2972e539-393c-46dc-b54a-c0b5e36d93ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35795
00623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.3579500623
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.315786840
Short name T1292
Test name
Test status
Simulation time 10095859008 ps
CPU time 12.85 seconds
Started Jun 02 03:32:28 PM PDT 24
Finished Jun 02 03:32:41 PM PDT 24
Peak memory 205644 kb
Host smart-0aba216c-9335-424a-aa69-1fa4dcf4dc1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31578
6840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.315786840
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.4038714662
Short name T329
Test name
Test status
Simulation time 14733274310 ps
CPU time 146.14 seconds
Started Jun 02 03:32:32 PM PDT 24
Finished Jun 02 03:34:59 PM PDT 24
Peak memory 205608 kb
Host smart-b7cf5801-360d-47ae-bfe9-2f2b7ffe70b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40387
14662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.4038714662
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.54082387
Short name T1069
Test name
Test status
Simulation time 10063415090 ps
CPU time 13.51 seconds
Started Jun 02 03:32:30 PM PDT 24
Finished Jun 02 03:32:44 PM PDT 24
Peak memory 205648 kb
Host smart-8a14a01f-c70e-443b-9ab8-d1a05d42deab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54082
387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.54082387
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.174663196
Short name T103
Test name
Test status
Simulation time 10099969214 ps
CPU time 12.73 seconds
Started Jun 02 03:32:26 PM PDT 24
Finished Jun 02 03:32:40 PM PDT 24
Peak memory 205760 kb
Host smart-00c0f91e-69af-4cf6-b5b4-fe5c8e211f74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17466
3196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.174663196
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.3798540981
Short name T824
Test name
Test status
Simulation time 10130533931 ps
CPU time 13.37 seconds
Started Jun 02 03:32:31 PM PDT 24
Finished Jun 02 03:32:46 PM PDT 24
Peak memory 205788 kb
Host smart-a0067f46-c6f4-41e8-a9af-410a3b46f35b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37985
40981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.3798540981
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.3479245271
Short name T451
Test name
Test status
Simulation time 10102879238 ps
CPU time 14.54 seconds
Started Jun 02 03:32:33 PM PDT 24
Finished Jun 02 03:32:48 PM PDT 24
Peak memory 205800 kb
Host smart-3ac8392c-9bfc-4116-964f-85a5599c312b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34792
45271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.3479245271
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2261260605
Short name T1448
Test name
Test status
Simulation time 10053446212 ps
CPU time 13.86 seconds
Started Jun 02 03:32:32 PM PDT 24
Finished Jun 02 03:32:47 PM PDT 24
Peak memory 205612 kb
Host smart-0a43a90f-71d9-4023-97b2-63233c70d2a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22612
60605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2261260605
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.3939018757
Short name T780
Test name
Test status
Simulation time 10063636982 ps
CPU time 13.26 seconds
Started Jun 02 03:32:51 PM PDT 24
Finished Jun 02 03:33:05 PM PDT 24
Peak memory 205684 kb
Host smart-b088f154-0671-4542-93d0-7d52cc2f99f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39390
18757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.3939018757
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_eop_single_bit_handling.278262275
Short name T822
Test name
Test status
Simulation time 10062062055 ps
CPU time 14.93 seconds
Started Jun 02 03:32:33 PM PDT 24
Finished Jun 02 03:32:49 PM PDT 24
Peak memory 205656 kb
Host smart-9cd75217-80bb-45ad-b950-d237460e9eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27826
2275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_eop_single_bit_handling.278262275
Directory /workspace/46.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3146880197
Short name T195
Test name
Test status
Simulation time 10045765428 ps
CPU time 15.12 seconds
Started Jun 02 03:32:33 PM PDT 24
Finished Jun 02 03:32:49 PM PDT 24
Peak memory 205760 kb
Host smart-5f1cc157-82b1-487b-ba20-73336daf028e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31468
80197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3146880197
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.2668203151
Short name T789
Test name
Test status
Simulation time 10037832495 ps
CPU time 13.83 seconds
Started Jun 02 03:32:33 PM PDT 24
Finished Jun 02 03:32:47 PM PDT 24
Peak memory 205700 kb
Host smart-15f034f1-5ddb-4de6-b3d4-ba6d550b08cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26682
03151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.2668203151
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.2545369835
Short name T24
Test name
Test status
Simulation time 24314840644 ps
CPU time 46.2 seconds
Started Jun 02 03:32:27 PM PDT 24
Finished Jun 02 03:33:14 PM PDT 24
Peak memory 205624 kb
Host smart-0a77332f-a582-4c11-aaf9-896d5d9ad854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25453
69835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.2545369835
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.3778121599
Short name T294
Test name
Test status
Simulation time 10089148723 ps
CPU time 13.23 seconds
Started Jun 02 03:32:29 PM PDT 24
Finished Jun 02 03:32:43 PM PDT 24
Peak memory 205672 kb
Host smart-bab3523e-e9b4-45c0-bbd2-9eac84b49b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37781
21599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3778121599
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.754389635
Short name T19
Test name
Test status
Simulation time 10111394462 ps
CPU time 13.56 seconds
Started Jun 02 03:32:30 PM PDT 24
Finished Jun 02 03:32:44 PM PDT 24
Peak memory 205780 kb
Host smart-64f16076-d9df-4a0a-bc16-21984e4fbbdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75438
9635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.754389635
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.3273201618
Short name T577
Test name
Test status
Simulation time 10079071717 ps
CPU time 13.83 seconds
Started Jun 02 03:32:32 PM PDT 24
Finished Jun 02 03:32:47 PM PDT 24
Peak memory 205724 kb
Host smart-2f0ee31c-38a5-4e4a-b8bb-5b0c91fb0a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32732
01618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.3273201618
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.3920421195
Short name T1916
Test name
Test status
Simulation time 10042094398 ps
CPU time 13.7 seconds
Started Jun 02 03:32:36 PM PDT 24
Finished Jun 02 03:32:51 PM PDT 24
Peak memory 205612 kb
Host smart-01a0a15f-0867-4b81-9e97-27f2cea6650c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39204
21195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.3920421195
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.453120402
Short name T1453
Test name
Test status
Simulation time 10102663002 ps
CPU time 13.09 seconds
Started Jun 02 03:32:33 PM PDT 24
Finished Jun 02 03:32:47 PM PDT 24
Peak memory 205596 kb
Host smart-85c99a14-bda5-43bf-8178-700435c02b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45312
0402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.453120402
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.3076205996
Short name T1024
Test name
Test status
Simulation time 10045090045 ps
CPU time 14.73 seconds
Started Jun 02 03:32:32 PM PDT 24
Finished Jun 02 03:32:48 PM PDT 24
Peak memory 205588 kb
Host smart-cb218169-c43c-400e-849d-6884caefedb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30762
05996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.3076205996
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.1981426871
Short name T1685
Test name
Test status
Simulation time 10105621156 ps
CPU time 13.04 seconds
Started Jun 02 03:32:27 PM PDT 24
Finished Jun 02 03:32:41 PM PDT 24
Peak memory 205656 kb
Host smart-4d97ddc1-211b-4b2a-b487-e24e770d3934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19814
26871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.1981426871
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.2774551021
Short name T570
Test name
Test status
Simulation time 10099721405 ps
CPU time 12.96 seconds
Started Jun 02 03:32:32 PM PDT 24
Finished Jun 02 03:32:46 PM PDT 24
Peak memory 205620 kb
Host smart-93927823-a6c9-4d84-8d69-881f71fbbacf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27745
51021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.2774551021
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2251054102
Short name T732
Test name
Test status
Simulation time 10052752025 ps
CPU time 13.52 seconds
Started Jun 02 03:32:30 PM PDT 24
Finished Jun 02 03:32:45 PM PDT 24
Peak memory 205632 kb
Host smart-777d23de-5e4a-47b2-81c9-f5a8b7ba3a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22510
54102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2251054102
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.2137305912
Short name T858
Test name
Test status
Simulation time 17120623090 ps
CPU time 204 seconds
Started Jun 02 03:32:31 PM PDT 24
Finished Jun 02 03:35:56 PM PDT 24
Peak memory 205684 kb
Host smart-d137093c-eb3c-4c50-aeca-e824f497fbf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21373
05912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.2137305912
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.1881055068
Short name T348
Test name
Test status
Simulation time 10151377879 ps
CPU time 13.19 seconds
Started Jun 02 03:32:38 PM PDT 24
Finished Jun 02 03:32:52 PM PDT 24
Peak memory 205680 kb
Host smart-9d4f6f47-e5fa-4786-acc7-68c3edde4e1b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1881055068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.1881055068
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.611150055
Short name T1338
Test name
Test status
Simulation time 10073937063 ps
CPU time 14.24 seconds
Started Jun 02 03:32:37 PM PDT 24
Finished Jun 02 03:32:52 PM PDT 24
Peak memory 205704 kb
Host smart-5c7acecc-e198-4414-996f-54d2089f835a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=611150055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.611150055
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.3596328427
Short name T1816
Test name
Test status
Simulation time 10110628683 ps
CPU time 14.38 seconds
Started Jun 02 03:32:44 PM PDT 24
Finished Jun 02 03:32:59 PM PDT 24
Peak memory 205728 kb
Host smart-4e044a14-7d51-4238-b3ad-4d3c9c8ca73c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35963
28427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.3596328427
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.965039463
Short name T458
Test name
Test status
Simulation time 13882096764 ps
CPU time 17.72 seconds
Started Jun 02 03:32:43 PM PDT 24
Finished Jun 02 03:33:02 PM PDT 24
Peak memory 205680 kb
Host smart-51729d69-f51c-41ca-a389-f2228f5231b0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=965039463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.965039463
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.2685573017
Short name T986
Test name
Test status
Simulation time 23230996727 ps
CPU time 24.89 seconds
Started Jun 02 03:32:32 PM PDT 24
Finished Jun 02 03:32:58 PM PDT 24
Peak memory 205752 kb
Host smart-a6a5d9ff-44b5-48a4-b778-7cacca7f51cc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2685573017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.2685573017
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.149802570
Short name T1967
Test name
Test status
Simulation time 10058541316 ps
CPU time 14.48 seconds
Started Jun 02 03:32:36 PM PDT 24
Finished Jun 02 03:32:51 PM PDT 24
Peak memory 205692 kb
Host smart-919b725e-491f-458b-b9c8-8be7d9451872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14980
2570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.149802570
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.2641434213
Short name T607
Test name
Test status
Simulation time 10108331993 ps
CPU time 15.64 seconds
Started Jun 02 03:32:30 PM PDT 24
Finished Jun 02 03:32:47 PM PDT 24
Peak memory 205712 kb
Host smart-6b62e3a9-2940-486c-a602-fb2d791fdf82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26414
34213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.2641434213
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.1340108210
Short name T166
Test name
Test status
Simulation time 11124035963 ps
CPU time 16.26 seconds
Started Jun 02 03:32:31 PM PDT 24
Finished Jun 02 03:32:48 PM PDT 24
Peak memory 205708 kb
Host smart-2ed2d7d0-d50d-49fa-9afe-c2dce5efb8d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13401
08210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.1340108210
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.2749861055
Short name T719
Test name
Test status
Simulation time 10070420155 ps
CPU time 13.16 seconds
Started Jun 02 03:32:31 PM PDT 24
Finished Jun 02 03:32:45 PM PDT 24
Peak memory 205640 kb
Host smart-b86dfe1c-0a56-4acd-b3bf-1fa6ff2e218a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27498
61055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.2749861055
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.2440633533
Short name T357
Test name
Test status
Simulation time 10078362617 ps
CPU time 13.36 seconds
Started Jun 02 03:32:30 PM PDT 24
Finished Jun 02 03:32:44 PM PDT 24
Peak memory 205700 kb
Host smart-660c85bb-a076-4c5c-9d70-9b939fa90897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24406
33533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2440633533
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.2274255019
Short name T648
Test name
Test status
Simulation time 10769546781 ps
CPU time 16.34 seconds
Started Jun 02 03:32:35 PM PDT 24
Finished Jun 02 03:32:52 PM PDT 24
Peak memory 205240 kb
Host smart-7636fe50-a125-4886-a683-d8d6987fac1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22742
55019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.2274255019
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3863342459
Short name T1880
Test name
Test status
Simulation time 10101198728 ps
CPU time 14.7 seconds
Started Jun 02 03:32:40 PM PDT 24
Finished Jun 02 03:32:56 PM PDT 24
Peak memory 205896 kb
Host smart-877dc080-69ba-4902-a5d4-e5748f1fc21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38633
42459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3863342459
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.1070588202
Short name T840
Test name
Test status
Simulation time 10103447452 ps
CPU time 15.87 seconds
Started Jun 02 03:32:43 PM PDT 24
Finished Jun 02 03:33:00 PM PDT 24
Peak memory 205760 kb
Host smart-e7797826-e320-43e4-a6e8-a1d6fb530de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10705
88202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.1070588202
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.752110197
Short name T550
Test name
Test status
Simulation time 10054308487 ps
CPU time 16.3 seconds
Started Jun 02 03:32:43 PM PDT 24
Finished Jun 02 03:33:00 PM PDT 24
Peak memory 205776 kb
Host smart-6238c05e-32b5-47db-ac08-d4dc8530ff5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75211
0197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.752110197
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.13778266
Short name T353
Test name
Test status
Simulation time 10127291280 ps
CPU time 14.64 seconds
Started Jun 02 03:32:31 PM PDT 24
Finished Jun 02 03:32:46 PM PDT 24
Peak memory 205728 kb
Host smart-08c7d7c3-7ba6-4faa-9838-843efe5bb390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13778
266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.13778266
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.355145368
Short name T1365
Test name
Test status
Simulation time 10096171162 ps
CPU time 14.85 seconds
Started Jun 02 03:32:40 PM PDT 24
Finished Jun 02 03:32:55 PM PDT 24
Peak memory 205824 kb
Host smart-1c03db72-ffe7-46a3-a447-d9dda7a8d864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35514
5368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.355145368
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.2803306979
Short name T25
Test name
Test status
Simulation time 13180263357 ps
CPU time 15.22 seconds
Started Jun 02 03:32:36 PM PDT 24
Finished Jun 02 03:32:52 PM PDT 24
Peak memory 205652 kb
Host smart-4bdfd955-1703-44b4-8092-9db5941ab088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28033
06979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.2803306979
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.3940049746
Short name T1095
Test name
Test status
Simulation time 10116968928 ps
CPU time 14.12 seconds
Started Jun 02 03:32:38 PM PDT 24
Finished Jun 02 03:32:53 PM PDT 24
Peak memory 205728 kb
Host smart-533af582-2c6c-419d-a564-a59f435a53e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39400
49746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.3940049746
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.3370861985
Short name T1097
Test name
Test status
Simulation time 20022588175 ps
CPU time 109.4 seconds
Started Jun 02 03:32:37 PM PDT 24
Finished Jun 02 03:34:27 PM PDT 24
Peak memory 205740 kb
Host smart-9516f455-c203-4dd4-9104-6cb24ae73987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33708
61985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.3370861985
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.948105387
Short name T1057
Test name
Test status
Simulation time 10071062216 ps
CPU time 14.21 seconds
Started Jun 02 03:32:30 PM PDT 24
Finished Jun 02 03:32:45 PM PDT 24
Peak memory 205720 kb
Host smart-9326f089-3c13-4220-ace6-c90d13c66006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94810
5387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.948105387
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.40103883
Short name T1258
Test name
Test status
Simulation time 10130861189 ps
CPU time 13.45 seconds
Started Jun 02 03:32:31 PM PDT 24
Finished Jun 02 03:32:45 PM PDT 24
Peak memory 205688 kb
Host smart-e8439a7c-2f41-4667-b6fa-1cd241641362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40103
883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.40103883
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.2903651280
Short name T484
Test name
Test status
Simulation time 10087766879 ps
CPU time 13.31 seconds
Started Jun 02 03:32:35 PM PDT 24
Finished Jun 02 03:32:48 PM PDT 24
Peak memory 205732 kb
Host smart-38944137-3f62-40ba-92a2-b9790502b728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29036
51280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.2903651280
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.262487563
Short name T631
Test name
Test status
Simulation time 10080503014 ps
CPU time 12.86 seconds
Started Jun 02 03:32:37 PM PDT 24
Finished Jun 02 03:32:51 PM PDT 24
Peak memory 205796 kb
Host smart-8e19c472-40a1-41e8-8d4d-fa101fafb3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26248
7563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.262487563
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.867776673
Short name T1151
Test name
Test status
Simulation time 10131655010 ps
CPU time 13.34 seconds
Started Jun 02 03:32:37 PM PDT 24
Finished Jun 02 03:32:51 PM PDT 24
Peak memory 205716 kb
Host smart-1c29ee72-09a0-487b-958d-d6aec9fbc8de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86777
6673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.867776673
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.604322238
Short name T143
Test name
Test status
Simulation time 10058776678 ps
CPU time 13.06 seconds
Started Jun 02 03:32:38 PM PDT 24
Finished Jun 02 03:32:52 PM PDT 24
Peak memory 205716 kb
Host smart-f91589cb-588d-4336-a4dc-05cce14231c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60432
2238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.604322238
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_eop_single_bit_handling.3894717869
Short name T1505
Test name
Test status
Simulation time 10075351720 ps
CPU time 15.11 seconds
Started Jun 02 03:32:38 PM PDT 24
Finished Jun 02 03:32:54 PM PDT 24
Peak memory 205700 kb
Host smart-0ab341f0-2f9c-4bce-8443-deb4f54a0695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38947
17869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_eop_single_bit_handling.3894717869
Directory /workspace/47.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.4235273900
Short name T1377
Test name
Test status
Simulation time 10057990066 ps
CPU time 13.1 seconds
Started Jun 02 03:32:46 PM PDT 24
Finished Jun 02 03:32:59 PM PDT 24
Peak memory 205720 kb
Host smart-26919cba-7269-48b5-8fa8-9ea187294f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42352
73900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.4235273900
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.1637819560
Short name T1686
Test name
Test status
Simulation time 10045977173 ps
CPU time 14.09 seconds
Started Jun 02 03:32:45 PM PDT 24
Finished Jun 02 03:33:00 PM PDT 24
Peak memory 205732 kb
Host smart-8bd457f8-24b1-440d-bab4-e82259616993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16378
19560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.1637819560
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2714975335
Short name T1481
Test name
Test status
Simulation time 17446719382 ps
CPU time 27.81 seconds
Started Jun 02 03:32:35 PM PDT 24
Finished Jun 02 03:33:03 PM PDT 24
Peak memory 205268 kb
Host smart-27d70abb-fed2-4649-acda-3e5520140d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27149
75335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2714975335
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.2887019495
Short name T1776
Test name
Test status
Simulation time 10085889271 ps
CPU time 14.24 seconds
Started Jun 02 03:32:40 PM PDT 24
Finished Jun 02 03:32:55 PM PDT 24
Peak memory 205452 kb
Host smart-de974581-54e5-4a30-9d13-24a6977dbf86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28870
19495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2887019495
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.374906301
Short name T1753
Test name
Test status
Simulation time 10106660157 ps
CPU time 16.58 seconds
Started Jun 02 03:32:32 PM PDT 24
Finished Jun 02 03:32:50 PM PDT 24
Peak memory 205796 kb
Host smart-29b941c6-fd45-45bb-9a6f-4896d792389a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37490
6301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.374906301
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.2929549423
Short name T1286
Test name
Test status
Simulation time 10068363582 ps
CPU time 14.96 seconds
Started Jun 02 03:32:32 PM PDT 24
Finished Jun 02 03:32:48 PM PDT 24
Peak memory 205612 kb
Host smart-ad8cbc3d-71ca-44bd-9b69-184f9b3b7f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29295
49423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.2929549423
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.3377508468
Short name T610
Test name
Test status
Simulation time 10047131458 ps
CPU time 14.37 seconds
Started Jun 02 03:32:38 PM PDT 24
Finished Jun 02 03:32:53 PM PDT 24
Peak memory 205632 kb
Host smart-b6c1bb67-9ce1-4662-b82e-d68c0f6ce8e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33775
08468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.3377508468
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.580293251
Short name T1366
Test name
Test status
Simulation time 10115125736 ps
CPU time 15.27 seconds
Started Jun 02 03:32:39 PM PDT 24
Finished Jun 02 03:32:54 PM PDT 24
Peak memory 205760 kb
Host smart-e3302ab7-fd2a-46c1-8074-9c2d565913c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58029
3251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.580293251
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2488277574
Short name T1210
Test name
Test status
Simulation time 10045397979 ps
CPU time 14.39 seconds
Started Jun 02 03:32:39 PM PDT 24
Finished Jun 02 03:32:54 PM PDT 24
Peak memory 205792 kb
Host smart-df0ce6fd-c853-435a-b017-e2dbd4f2e1d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24882
77574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2488277574
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.1713934864
Short name T3
Test name
Test status
Simulation time 10138147376 ps
CPU time 15.81 seconds
Started Jun 02 03:32:40 PM PDT 24
Finished Jun 02 03:32:56 PM PDT 24
Peak memory 205772 kb
Host smart-ba143353-4444-4dba-9915-518fa2c1a871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17139
34864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1713934864
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.4246287452
Short name T1869
Test name
Test status
Simulation time 10106876348 ps
CPU time 14.1 seconds
Started Jun 02 03:32:36 PM PDT 24
Finished Jun 02 03:32:51 PM PDT 24
Peak memory 205736 kb
Host smart-4bb37c54-b3af-421b-9659-298413d635c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42462
87452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.4246287452
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2905501619
Short name T1226
Test name
Test status
Simulation time 10059499042 ps
CPU time 13.15 seconds
Started Jun 02 03:32:35 PM PDT 24
Finished Jun 02 03:32:48 PM PDT 24
Peak memory 205760 kb
Host smart-a223a468-deaf-423b-9067-7664fa78c48a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29055
01619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2905501619
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.1937584312
Short name T1367
Test name
Test status
Simulation time 21101313169 ps
CPU time 355.3 seconds
Started Jun 02 03:32:46 PM PDT 24
Finished Jun 02 03:38:41 PM PDT 24
Peak memory 205692 kb
Host smart-c6133cdb-f9c0-4e96-a502-5947cbfe2226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19375
84312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.1937584312
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.1273382551
Short name T1927
Test name
Test status
Simulation time 10158754609 ps
CPU time 14.91 seconds
Started Jun 02 03:32:41 PM PDT 24
Finished Jun 02 03:32:56 PM PDT 24
Peak memory 205660 kb
Host smart-39ef377e-f665-438a-96e6-fc820584eb27
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1273382551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.1273382551
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.2475327194
Short name T1425
Test name
Test status
Simulation time 10095326948 ps
CPU time 13.66 seconds
Started Jun 02 03:32:42 PM PDT 24
Finished Jun 02 03:32:57 PM PDT 24
Peak memory 205788 kb
Host smart-cc73e2d7-4d21-41ba-9d3e-b63d2dd93b8d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2475327194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.2475327194
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.1505314272
Short name T1215
Test name
Test status
Simulation time 10096244041 ps
CPU time 13.18 seconds
Started Jun 02 03:32:48 PM PDT 24
Finished Jun 02 03:33:02 PM PDT 24
Peak memory 205760 kb
Host smart-7cf5ea4d-316c-481a-b5c7-89b95799350f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15053
14272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.1505314272
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.3677081208
Short name T1883
Test name
Test status
Simulation time 13575498610 ps
CPU time 17.95 seconds
Started Jun 02 03:32:45 PM PDT 24
Finished Jun 02 03:33:03 PM PDT 24
Peak memory 205644 kb
Host smart-ff9c7d2d-3d3d-45e5-a751-b142bd1e1157
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3677081208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.3677081208
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.906348534
Short name T499
Test name
Test status
Simulation time 23242742607 ps
CPU time 24.85 seconds
Started Jun 02 03:32:39 PM PDT 24
Finished Jun 02 03:33:04 PM PDT 24
Peak memory 205704 kb
Host smart-ac0796c5-4aa6-4bf5-9442-cca929bb5450
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=906348534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.906348534
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.3012096499
Short name T1758
Test name
Test status
Simulation time 10092321627 ps
CPU time 12.73 seconds
Started Jun 02 03:32:38 PM PDT 24
Finished Jun 02 03:32:51 PM PDT 24
Peak memory 205708 kb
Host smart-b2ac5487-4a23-499a-a297-558dde122e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30120
96499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.3012096499
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.2639159755
Short name T1014
Test name
Test status
Simulation time 10980871534 ps
CPU time 14.64 seconds
Started Jun 02 03:32:38 PM PDT 24
Finished Jun 02 03:32:54 PM PDT 24
Peak memory 205740 kb
Host smart-1ed22fec-d489-4d1b-873c-1cdbc0d7e3d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26391
59755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.2639159755
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.911943269
Short name T1230
Test name
Test status
Simulation time 10065605189 ps
CPU time 15.74 seconds
Started Jun 02 03:32:33 PM PDT 24
Finished Jun 02 03:32:49 PM PDT 24
Peak memory 205584 kb
Host smart-40f5ae65-2140-4f9a-be70-fc5113b37b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91194
3269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.911943269
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.343566628
Short name T1406
Test name
Test status
Simulation time 10044833554 ps
CPU time 12.39 seconds
Started Jun 02 03:32:38 PM PDT 24
Finished Jun 02 03:32:51 PM PDT 24
Peak memory 205680 kb
Host smart-772288e2-5437-43ad-befb-e1841c256833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34356
6628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.343566628
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.4279915642
Short name T915
Test name
Test status
Simulation time 10789430314 ps
CPU time 15.61 seconds
Started Jun 02 03:32:38 PM PDT 24
Finished Jun 02 03:32:54 PM PDT 24
Peak memory 205736 kb
Host smart-0a5669ba-e74c-4cb5-803b-49a10085a569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42799
15642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.4279915642
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.958464541
Short name T925
Test name
Test status
Simulation time 10089339633 ps
CPU time 15 seconds
Started Jun 02 03:32:39 PM PDT 24
Finished Jun 02 03:32:55 PM PDT 24
Peak memory 205692 kb
Host smart-d86b2ad9-36ea-4294-bd16-0b4c17f67c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95846
4541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.958464541
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.198090083
Short name T462
Test name
Test status
Simulation time 10058625339 ps
CPU time 15.1 seconds
Started Jun 02 03:32:44 PM PDT 24
Finished Jun 02 03:33:00 PM PDT 24
Peak memory 205700 kb
Host smart-5dcafd5c-80fb-4c13-a0d3-ed835a1c0720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19809
0083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.198090083
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.3293349690
Short name T1512
Test name
Test status
Simulation time 10043065920 ps
CPU time 12.34 seconds
Started Jun 02 03:32:44 PM PDT 24
Finished Jun 02 03:32:57 PM PDT 24
Peak memory 205716 kb
Host smart-34535932-47bf-43ed-b73d-dbc3a930fca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32933
49690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.3293349690
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.2219146202
Short name T293
Test name
Test status
Simulation time 10105786598 ps
CPU time 13.15 seconds
Started Jun 02 03:32:36 PM PDT 24
Finished Jun 02 03:32:49 PM PDT 24
Peak memory 205828 kb
Host smart-e9188084-b4c8-4ea4-9f15-40977596997e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22191
46202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.2219146202
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.197090155
Short name T1085
Test name
Test status
Simulation time 10096646174 ps
CPU time 12.75 seconds
Started Jun 02 03:32:36 PM PDT 24
Finished Jun 02 03:32:49 PM PDT 24
Peak memory 205656 kb
Host smart-4ccc03e0-341f-4520-b825-3df094fd34b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19709
0155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.197090155
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.37284820
Short name T36
Test name
Test status
Simulation time 13218841753 ps
CPU time 17.6 seconds
Started Jun 02 03:32:45 PM PDT 24
Finished Jun 02 03:33:03 PM PDT 24
Peak memory 205712 kb
Host smart-4d0f8a37-d431-4ac3-ab6d-e89bae43db1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37284
820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.37284820
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.255798163
Short name T340
Test name
Test status
Simulation time 10119903138 ps
CPU time 15.33 seconds
Started Jun 02 03:32:41 PM PDT 24
Finished Jun 02 03:32:56 PM PDT 24
Peak memory 205688 kb
Host smart-76f207ad-68fd-40cf-80ae-58d31a520376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25579
8163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.255798163
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.2132391844
Short name T1918
Test name
Test status
Simulation time 21351256223 ps
CPU time 91.12 seconds
Started Jun 02 03:32:33 PM PDT 24
Finished Jun 02 03:34:05 PM PDT 24
Peak memory 205672 kb
Host smart-c221b06b-1313-42c5-a97d-84ffbb69cf33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21323
91844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.2132391844
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2356931730
Short name T399
Test name
Test status
Simulation time 10048343057 ps
CPU time 12.55 seconds
Started Jun 02 03:32:39 PM PDT 24
Finished Jun 02 03:32:52 PM PDT 24
Peak memory 205660 kb
Host smart-7b2d54a2-a52b-4186-a126-84ac55f1e83e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23569
31730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2356931730
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.3016577166
Short name T114
Test name
Test status
Simulation time 10101107069 ps
CPU time 14.58 seconds
Started Jun 02 03:32:49 PM PDT 24
Finished Jun 02 03:33:04 PM PDT 24
Peak memory 205736 kb
Host smart-dfad1cd3-3d92-4a96-a93c-7cc3f573d0bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30165
77166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.3016577166
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.1825668556
Short name T1794
Test name
Test status
Simulation time 10066420550 ps
CPU time 12.79 seconds
Started Jun 02 03:32:48 PM PDT 24
Finished Jun 02 03:33:02 PM PDT 24
Peak memory 205676 kb
Host smart-834340d6-961b-4d13-a424-391963dd8940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18256
68556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.1825668556
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.1012771160
Short name T1006
Test name
Test status
Simulation time 10091605971 ps
CPU time 14.29 seconds
Started Jun 02 03:32:45 PM PDT 24
Finished Jun 02 03:33:00 PM PDT 24
Peak memory 205768 kb
Host smart-1dc21849-7a73-4449-8acd-3c708b127b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10127
71160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.1012771160
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.584904902
Short name T700
Test name
Test status
Simulation time 10070806829 ps
CPU time 14.33 seconds
Started Jun 02 03:32:42 PM PDT 24
Finished Jun 02 03:32:57 PM PDT 24
Peak memory 205680 kb
Host smart-8b6463e3-171e-4ca5-8aab-8305d9b24561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58490
4902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.584904902
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.289166917
Short name T1514
Test name
Test status
Simulation time 10079112829 ps
CPU time 13.17 seconds
Started Jun 02 03:32:49 PM PDT 24
Finished Jun 02 03:33:03 PM PDT 24
Peak memory 205740 kb
Host smart-fbd445be-7cfe-49c8-bd1e-469869bab9b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28916
6917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.289166917
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_eop_single_bit_handling.2531508026
Short name T490
Test name
Test status
Simulation time 10087703528 ps
CPU time 12.49 seconds
Started Jun 02 03:32:46 PM PDT 24
Finished Jun 02 03:32:59 PM PDT 24
Peak memory 205648 kb
Host smart-f841203d-c938-4936-b62b-20eb583a1296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25315
08026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_eop_single_bit_handling.2531508026
Directory /workspace/48.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.3976671543
Short name T716
Test name
Test status
Simulation time 10057507690 ps
CPU time 13.68 seconds
Started Jun 02 03:32:48 PM PDT 24
Finished Jun 02 03:33:02 PM PDT 24
Peak memory 205740 kb
Host smart-61cba225-0201-4406-8363-ccf8961c4819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39766
71543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.3976671543
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.2581031039
Short name T1329
Test name
Test status
Simulation time 10034584068 ps
CPU time 14.35 seconds
Started Jun 02 03:32:48 PM PDT 24
Finished Jun 02 03:33:03 PM PDT 24
Peak memory 205660 kb
Host smart-83918a5f-6c7d-43e4-a067-aff4215eeb41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25810
31039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.2581031039
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1778555424
Short name T1075
Test name
Test status
Simulation time 22002723286 ps
CPU time 37.47 seconds
Started Jun 02 03:32:51 PM PDT 24
Finished Jun 02 03:33:29 PM PDT 24
Peak memory 205616 kb
Host smart-ea2455fd-3132-4e0f-b6f5-8fc93e6a77f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17785
55424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1778555424
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.3307369507
Short name T1027
Test name
Test status
Simulation time 10076878766 ps
CPU time 13.41 seconds
Started Jun 02 03:32:48 PM PDT 24
Finished Jun 02 03:33:02 PM PDT 24
Peak memory 205760 kb
Host smart-bfa965f9-c3a5-4588-9951-763c0a70ffa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33073
69507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3307369507
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.436333394
Short name T1965
Test name
Test status
Simulation time 10085883164 ps
CPU time 14.12 seconds
Started Jun 02 03:32:46 PM PDT 24
Finished Jun 02 03:33:01 PM PDT 24
Peak memory 205796 kb
Host smart-54c42db7-5c64-4790-9547-b16e7c2579bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43633
3394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.436333394
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.2891134003
Short name T532
Test name
Test status
Simulation time 10100119700 ps
CPU time 14.6 seconds
Started Jun 02 03:32:52 PM PDT 24
Finished Jun 02 03:33:07 PM PDT 24
Peak memory 205688 kb
Host smart-5b9b9716-0677-45fd-8743-e2203e739560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28911
34003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.2891134003
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.3747931181
Short name T1980
Test name
Test status
Simulation time 10082201398 ps
CPU time 14.25 seconds
Started Jun 02 03:32:49 PM PDT 24
Finished Jun 02 03:33:04 PM PDT 24
Peak memory 205704 kb
Host smart-3ead1b98-9698-404f-acfd-cea29a3b9e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37479
31181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.3747931181
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.1231083499
Short name T1522
Test name
Test status
Simulation time 10055607909 ps
CPU time 17.22 seconds
Started Jun 02 03:32:42 PM PDT 24
Finished Jun 02 03:33:00 PM PDT 24
Peak memory 205760 kb
Host smart-406792d3-917e-480f-a754-b28dbe3c4eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12310
83499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.1231083499
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.1807262283
Short name T734
Test name
Test status
Simulation time 10045460209 ps
CPU time 14.01 seconds
Started Jun 02 03:32:47 PM PDT 24
Finished Jun 02 03:33:02 PM PDT 24
Peak memory 205664 kb
Host smart-52591aa6-930e-4e2a-8e7f-14f3c2456dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18072
62283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1807262283
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1301076491
Short name T91
Test name
Test status
Simulation time 10108687578 ps
CPU time 14.38 seconds
Started Jun 02 03:32:42 PM PDT 24
Finished Jun 02 03:32:57 PM PDT 24
Peak memory 205772 kb
Host smart-bd3fcefe-bfe1-44f4-b03b-ca4e57ef4806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13010
76491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1301076491
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.3682496218
Short name T956
Test name
Test status
Simulation time 10040973252 ps
CPU time 12.83 seconds
Started Jun 02 03:32:44 PM PDT 24
Finished Jun 02 03:32:58 PM PDT 24
Peak memory 205692 kb
Host smart-e9f6972d-e0aa-4991-aec6-4f6241513666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36824
96218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.3682496218
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.298970643
Short name T673
Test name
Test status
Simulation time 10066259712 ps
CPU time 13.45 seconds
Started Jun 02 03:32:48 PM PDT 24
Finished Jun 02 03:33:02 PM PDT 24
Peak memory 205680 kb
Host smart-41b71a5c-8753-4634-b9ab-ae3817fbc42e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29897
0643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.298970643
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.2207079068
Short name T846
Test name
Test status
Simulation time 21120559540 ps
CPU time 89.82 seconds
Started Jun 02 03:32:44 PM PDT 24
Finished Jun 02 03:34:15 PM PDT 24
Peak memory 205668 kb
Host smart-758415b0-043a-4845-a897-e915e2906a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22070
79068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.2207079068
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.3188352324
Short name T1469
Test name
Test status
Simulation time 10139338165 ps
CPU time 13.71 seconds
Started Jun 02 03:32:50 PM PDT 24
Finished Jun 02 03:33:04 PM PDT 24
Peak memory 205576 kb
Host smart-0a03a31a-7b27-48c4-8744-1eaf45ec3c41
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3188352324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.3188352324
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.2833856157
Short name T401
Test name
Test status
Simulation time 10109537693 ps
CPU time 14.5 seconds
Started Jun 02 03:32:54 PM PDT 24
Finished Jun 02 03:33:09 PM PDT 24
Peak memory 205804 kb
Host smart-8fa40275-8955-4a20-a916-3239f06d4d48
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2833856157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.2833856157
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.2804478282
Short name T965
Test name
Test status
Simulation time 10088107767 ps
CPU time 12.62 seconds
Started Jun 02 03:32:50 PM PDT 24
Finished Jun 02 03:33:04 PM PDT 24
Peak memory 205612 kb
Host smart-d4f7d296-b589-4dde-8f83-8fc21fb4ab2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28044
78282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.2804478282
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.475118934
Short name T16
Test name
Test status
Simulation time 14382596753 ps
CPU time 17.98 seconds
Started Jun 02 03:32:43 PM PDT 24
Finished Jun 02 03:33:01 PM PDT 24
Peak memory 205772 kb
Host smart-6fdd260f-fd83-4bb1-9be4-c9f209e4b7ec
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=475118934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.475118934
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.2478174955
Short name T1845
Test name
Test status
Simulation time 23356077030 ps
CPU time 25.79 seconds
Started Jun 02 03:32:44 PM PDT 24
Finished Jun 02 03:33:11 PM PDT 24
Peak memory 205768 kb
Host smart-129e6b37-19eb-4050-ab6f-9f02f14b68fe
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2478174955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.2478174955
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.1448972597
Short name T964
Test name
Test status
Simulation time 10087740412 ps
CPU time 14.92 seconds
Started Jun 02 03:32:50 PM PDT 24
Finished Jun 02 03:33:06 PM PDT 24
Peak memory 205668 kb
Host smart-864c22b3-79ce-4925-b5aa-6b5fcc1d2681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14489
72597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.1448972597
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.814493323
Short name T1621
Test name
Test status
Simulation time 10199565468 ps
CPU time 13.81 seconds
Started Jun 02 03:32:48 PM PDT 24
Finished Jun 02 03:33:02 PM PDT 24
Peak memory 205696 kb
Host smart-6f3a2422-63f3-4d08-b73f-79485b6f4607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81449
3323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.814493323
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.1147339376
Short name T649
Test name
Test status
Simulation time 10040108765 ps
CPU time 13.88 seconds
Started Jun 02 03:32:49 PM PDT 24
Finished Jun 02 03:33:04 PM PDT 24
Peak memory 205748 kb
Host smart-209eac8c-5c02-4633-813c-80fe3bbd20f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11473
39376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.1147339376
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.1818914037
Short name T627
Test name
Test status
Simulation time 10053467628 ps
CPU time 12.41 seconds
Started Jun 02 03:32:49 PM PDT 24
Finished Jun 02 03:33:02 PM PDT 24
Peak memory 205596 kb
Host smart-5e607cc3-dd32-4e28-8e7e-d54b4f07bf29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18189
14037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.1818914037
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.936867551
Short name T538
Test name
Test status
Simulation time 10741991081 ps
CPU time 17.43 seconds
Started Jun 02 03:32:55 PM PDT 24
Finished Jun 02 03:33:12 PM PDT 24
Peak memory 205632 kb
Host smart-030d7517-96c2-4738-94ea-095d2a79e009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93686
7551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.936867551
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.2831163093
Short name T848
Test name
Test status
Simulation time 10203982295 ps
CPU time 15.15 seconds
Started Jun 02 03:32:47 PM PDT 24
Finished Jun 02 03:33:03 PM PDT 24
Peak memory 205732 kb
Host smart-0f47eefa-7ed6-43a1-a225-d5831ade739f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28311
63093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.2831163093
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.755638384
Short name T1501
Test name
Test status
Simulation time 10158699898 ps
CPU time 16.59 seconds
Started Jun 02 03:32:51 PM PDT 24
Finished Jun 02 03:33:09 PM PDT 24
Peak memory 205768 kb
Host smart-dc896fda-82bd-4bb6-adf7-5cc92794f868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75563
8384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.755638384
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.3276330966
Short name T933
Test name
Test status
Simulation time 10048478936 ps
CPU time 14.08 seconds
Started Jun 02 03:32:49 PM PDT 24
Finished Jun 02 03:33:04 PM PDT 24
Peak memory 205656 kb
Host smart-a3d81679-f41a-426b-8c6b-1aebe55335e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32763
30966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.3276330966
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.2056510190
Short name T644
Test name
Test status
Simulation time 10132929905 ps
CPU time 13.9 seconds
Started Jun 02 03:32:49 PM PDT 24
Finished Jun 02 03:33:04 PM PDT 24
Peak memory 205640 kb
Host smart-704227fb-1833-4294-ae87-c4ff48841413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20565
10190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.2056510190
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.1033704891
Short name T1174
Test name
Test status
Simulation time 10118747167 ps
CPU time 13.98 seconds
Started Jun 02 03:32:55 PM PDT 24
Finished Jun 02 03:33:10 PM PDT 24
Peak memory 205704 kb
Host smart-194cc248-de17-452b-a458-ac1acd57cf6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10337
04891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.1033704891
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.142391856
Short name T1187
Test name
Test status
Simulation time 13219294977 ps
CPU time 17.74 seconds
Started Jun 02 03:33:01 PM PDT 24
Finished Jun 02 03:33:19 PM PDT 24
Peak memory 205776 kb
Host smart-95221e54-f5ba-43ef-a8c0-fc434a467041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14239
1856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.142391856
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2064687992
Short name T906
Test name
Test status
Simulation time 10107062532 ps
CPU time 13.11 seconds
Started Jun 02 03:32:47 PM PDT 24
Finished Jun 02 03:33:01 PM PDT 24
Peak memory 205680 kb
Host smart-fc12e82b-8559-4bdc-b626-3b45e5e98dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20646
87992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2064687992
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.1516729392
Short name T1213
Test name
Test status
Simulation time 23947716204 ps
CPU time 150.18 seconds
Started Jun 02 03:32:55 PM PDT 24
Finished Jun 02 03:35:26 PM PDT 24
Peak memory 205648 kb
Host smart-00ace096-3d4c-4908-9854-30758e2507f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15167
29392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.1516729392
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1443598863
Short name T1913
Test name
Test status
Simulation time 10052971056 ps
CPU time 18.09 seconds
Started Jun 02 03:32:49 PM PDT 24
Finished Jun 02 03:33:08 PM PDT 24
Peak memory 205756 kb
Host smart-abf4f33a-ae39-4839-bd07-891cd471fac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14435
98863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1443598863
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.284049601
Short name T96
Test name
Test status
Simulation time 10101014530 ps
CPU time 13.31 seconds
Started Jun 02 03:32:57 PM PDT 24
Finished Jun 02 03:33:10 PM PDT 24
Peak memory 205720 kb
Host smart-27e6141c-b6bb-4bfa-8926-e99aa4d5c237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28404
9601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.284049601
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.781449516
Short name T1154
Test name
Test status
Simulation time 10091894224 ps
CPU time 13.18 seconds
Started Jun 02 03:32:49 PM PDT 24
Finished Jun 02 03:33:03 PM PDT 24
Peak memory 205744 kb
Host smart-5833b067-cd71-42d5-8fd0-4262d42d86ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78144
9516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.781449516
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1388409632
Short name T899
Test name
Test status
Simulation time 10078191551 ps
CPU time 13.47 seconds
Started Jun 02 03:32:50 PM PDT 24
Finished Jun 02 03:33:05 PM PDT 24
Peak memory 205764 kb
Host smart-6e00c13b-03bf-4d90-a30f-3fbf106902bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13884
09632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1388409632
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.3010657806
Short name T1934
Test name
Test status
Simulation time 10045602485 ps
CPU time 13.64 seconds
Started Jun 02 03:32:46 PM PDT 24
Finished Jun 02 03:33:01 PM PDT 24
Peak memory 205592 kb
Host smart-c00e3165-528d-4de3-9c81-86ed67af9dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30106
57806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.3010657806
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.2775668884
Short name T172
Test name
Test status
Simulation time 10074986608 ps
CPU time 12.91 seconds
Started Jun 02 03:32:52 PM PDT 24
Finished Jun 02 03:33:05 PM PDT 24
Peak memory 205660 kb
Host smart-741409c4-8088-4a48-97bc-30fd7e90d5db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27756
68884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.2775668884
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_eop_single_bit_handling.107092130
Short name T2029
Test name
Test status
Simulation time 10069803409 ps
CPU time 15.92 seconds
Started Jun 02 03:32:52 PM PDT 24
Finished Jun 02 03:33:09 PM PDT 24
Peak memory 205624 kb
Host smart-e20b0150-1c0c-4276-8a90-be345312fd4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10709
2130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_eop_single_bit_handling.107092130
Directory /workspace/49.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.1197842677
Short name T1557
Test name
Test status
Simulation time 10055843921 ps
CPU time 13.28 seconds
Started Jun 02 03:32:57 PM PDT 24
Finished Jun 02 03:33:10 PM PDT 24
Peak memory 205712 kb
Host smart-adc24b3a-623e-474b-99b2-af9c206d5042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11978
42677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.1197842677
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1109289918
Short name T1856
Test name
Test status
Simulation time 10064343406 ps
CPU time 13.48 seconds
Started Jun 02 03:32:50 PM PDT 24
Finished Jun 02 03:33:04 PM PDT 24
Peak memory 205828 kb
Host smart-3ef0d5c4-8def-4513-96ba-37474f1b4e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11092
89918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1109289918
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.1205218464
Short name T1400
Test name
Test status
Simulation time 16303101352 ps
CPU time 30.31 seconds
Started Jun 02 03:32:48 PM PDT 24
Finished Jun 02 03:33:19 PM PDT 24
Peak memory 205720 kb
Host smart-d5fb196b-671b-43fb-8138-a2dfd9cfb7e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12052
18464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.1205218464
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3146943325
Short name T842
Test name
Test status
Simulation time 10071890573 ps
CPU time 16.53 seconds
Started Jun 02 03:32:51 PM PDT 24
Finished Jun 02 03:33:08 PM PDT 24
Peak memory 205696 kb
Host smart-5e47e686-852c-47f3-843c-ae818132530f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31469
43325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3146943325
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.517241404
Short name T943
Test name
Test status
Simulation time 10196051458 ps
CPU time 13.79 seconds
Started Jun 02 03:32:49 PM PDT 24
Finished Jun 02 03:33:04 PM PDT 24
Peak memory 205796 kb
Host smart-c4719f95-c248-469f-9f7b-758510e8bc1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51724
1404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.517241404
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.2544103988
Short name T1378
Test name
Test status
Simulation time 10066327315 ps
CPU time 13.15 seconds
Started Jun 02 03:32:54 PM PDT 24
Finished Jun 02 03:33:07 PM PDT 24
Peak memory 205728 kb
Host smart-1cf531ae-0366-4c1a-976d-f14d59f9617e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25441
03988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.2544103988
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.1335666462
Short name T1368
Test name
Test status
Simulation time 10047958676 ps
CPU time 13.85 seconds
Started Jun 02 03:32:52 PM PDT 24
Finished Jun 02 03:33:06 PM PDT 24
Peak memory 205732 kb
Host smart-6cfd9c8d-2d51-4114-8a6f-dcefae90b4a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13356
66462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.1335666462
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.3217473930
Short name T1189
Test name
Test status
Simulation time 10077928640 ps
CPU time 15.31 seconds
Started Jun 02 03:32:50 PM PDT 24
Finished Jun 02 03:33:07 PM PDT 24
Peak memory 205760 kb
Host smart-34c9ceac-2e5b-405b-a2f5-a11df448b7f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32174
73930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.3217473930
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.4151789647
Short name T1614
Test name
Test status
Simulation time 10139655906 ps
CPU time 13.93 seconds
Started Jun 02 03:32:56 PM PDT 24
Finished Jun 02 03:33:10 PM PDT 24
Peak memory 205852 kb
Host smart-e1ceaabd-0d55-436e-9b9f-f4975bad15a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41517
89647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.4151789647
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.4120893989
Short name T1911
Test name
Test status
Simulation time 10082894743 ps
CPU time 14.36 seconds
Started Jun 02 03:32:50 PM PDT 24
Finished Jun 02 03:33:06 PM PDT 24
Peak memory 205784 kb
Host smart-51d52430-909b-4dc0-81d5-4335fe40848f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41208
93989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.4120893989
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.2388130268
Short name T1203
Test name
Test status
Simulation time 10060311205 ps
CPU time 15.64 seconds
Started Jun 02 03:32:50 PM PDT 24
Finished Jun 02 03:33:07 PM PDT 24
Peak memory 205684 kb
Host smart-7b216663-0fd7-448f-ac7b-4f6f89f0f24e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23881
30268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.2388130268
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.1619440667
Short name T494
Test name
Test status
Simulation time 23035198825 ps
CPU time 145.93 seconds
Started Jun 02 03:32:47 PM PDT 24
Finished Jun 02 03:35:14 PM PDT 24
Peak memory 205724 kb
Host smart-3109c533-2d8c-49aa-befe-37698c558172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16194
40667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.1619440667
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.2599751199
Short name T1470
Test name
Test status
Simulation time 10143930892 ps
CPU time 12.83 seconds
Started Jun 02 03:27:17 PM PDT 24
Finished Jun 02 03:27:31 PM PDT 24
Peak memory 205784 kb
Host smart-c22da5f2-f3f9-41ce-8043-97d325fda67b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2599751199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.2599751199
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.3397969884
Short name T1170
Test name
Test status
Simulation time 10087902393 ps
CPU time 12.86 seconds
Started Jun 02 03:27:19 PM PDT 24
Finished Jun 02 03:27:33 PM PDT 24
Peak memory 205704 kb
Host smart-d1f8d12f-84b8-4e31-b895-42c92e8accd7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3397969884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.3397969884
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.290925399
Short name T37
Test name
Test status
Simulation time 10086131913 ps
CPU time 13.15 seconds
Started Jun 02 03:27:17 PM PDT 24
Finished Jun 02 03:27:31 PM PDT 24
Peak memory 205696 kb
Host smart-6536a01e-7cf8-4ee9-ab2c-7e7aefbcef80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29092
5399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.290925399
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.3601008833
Short name T856
Test name
Test status
Simulation time 14030812534 ps
CPU time 17.38 seconds
Started Jun 02 03:27:13 PM PDT 24
Finished Jun 02 03:27:32 PM PDT 24
Peak memory 205632 kb
Host smart-8ecd6cb4-3305-43e6-b978-e4cb6a168d65
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3601008833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.3601008833
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.1334795425
Short name T1660
Test name
Test status
Simulation time 23302034418 ps
CPU time 29.91 seconds
Started Jun 02 03:27:09 PM PDT 24
Finished Jun 02 03:27:40 PM PDT 24
Peak memory 205712 kb
Host smart-f6f383aa-7f11-40aa-b994-0c324d0a46fb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1334795425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.1334795425
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.2535568382
Short name T1143
Test name
Test status
Simulation time 10055670262 ps
CPU time 14.19 seconds
Started Jun 02 03:27:08 PM PDT 24
Finished Jun 02 03:27:23 PM PDT 24
Peak memory 205760 kb
Host smart-a59b484d-33bb-4a09-8d97-38e60bc80194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25355
68382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2535568382
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.4249894606
Short name T179
Test name
Test status
Simulation time 10799712065 ps
CPU time 15.12 seconds
Started Jun 02 03:27:06 PM PDT 24
Finished Jun 02 03:27:22 PM PDT 24
Peak memory 205656 kb
Host smart-8d05c004-a5c9-4c59-9efa-b2a7bd80e7b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42498
94606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.4249894606
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.2024390017
Short name T1702
Test name
Test status
Simulation time 10043332975 ps
CPU time 13.95 seconds
Started Jun 02 03:27:10 PM PDT 24
Finished Jun 02 03:27:24 PM PDT 24
Peak memory 205784 kb
Host smart-824ae080-de55-4175-a1f2-3ca2fbd939cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20243
90017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.2024390017
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.3938554039
Short name T958
Test name
Test status
Simulation time 10128377928 ps
CPU time 15.23 seconds
Started Jun 02 03:27:05 PM PDT 24
Finished Jun 02 03:27:22 PM PDT 24
Peak memory 205748 kb
Host smart-963952e1-b885-49d6-9f6c-87ec248e36fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39385
54039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.3938554039
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.1484273330
Short name T525
Test name
Test status
Simulation time 10828670606 ps
CPU time 15.16 seconds
Started Jun 02 03:27:06 PM PDT 24
Finished Jun 02 03:27:23 PM PDT 24
Peak memory 205672 kb
Host smart-efe45da5-9ddc-4710-b306-8c40237caebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14842
73330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.1484273330
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.2414727906
Short name T942
Test name
Test status
Simulation time 10078561317 ps
CPU time 14.74 seconds
Started Jun 02 03:27:08 PM PDT 24
Finished Jun 02 03:27:23 PM PDT 24
Peak memory 205636 kb
Host smart-5eb785d0-a529-4f15-a17f-cc0cd2817dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24147
27906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.2414727906
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.392436539
Short name T1070
Test name
Test status
Simulation time 10109972041 ps
CPU time 13.44 seconds
Started Jun 02 03:27:20 PM PDT 24
Finished Jun 02 03:27:35 PM PDT 24
Peak memory 205720 kb
Host smart-6056557a-2d73-4a69-86e5-c1d46ccb9a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39243
6539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.392436539
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.2374251684
Short name T595
Test name
Test status
Simulation time 10039919668 ps
CPU time 13.82 seconds
Started Jun 02 03:27:18 PM PDT 24
Finished Jun 02 03:27:34 PM PDT 24
Peak memory 205632 kb
Host smart-f5de14af-a193-4f1d-a8ef-04aa81a6b037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23742
51684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.2374251684
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.2068218701
Short name T500
Test name
Test status
Simulation time 10133970333 ps
CPU time 14.06 seconds
Started Jun 02 03:27:13 PM PDT 24
Finished Jun 02 03:27:28 PM PDT 24
Peak memory 205696 kb
Host smart-ff4e2deb-f006-4287-bb9a-3c2e3c6f1961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20682
18701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.2068218701
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.3903738497
Short name T831
Test name
Test status
Simulation time 10129176397 ps
CPU time 12.76 seconds
Started Jun 02 03:27:13 PM PDT 24
Finished Jun 02 03:27:26 PM PDT 24
Peak memory 205664 kb
Host smart-6f8266d7-ce70-4f45-9d72-e6737178c2cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39037
38497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.3903738497
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.174012952
Short name T310
Test name
Test status
Simulation time 13216276424 ps
CPU time 15.72 seconds
Started Jun 02 03:27:12 PM PDT 24
Finished Jun 02 03:27:29 PM PDT 24
Peak memory 205684 kb
Host smart-135371f9-de8f-499c-9087-d42957030e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17401
2952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.174012952
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3395137355
Short name T1037
Test name
Test status
Simulation time 10084148883 ps
CPU time 17.5 seconds
Started Jun 02 03:27:14 PM PDT 24
Finished Jun 02 03:27:32 PM PDT 24
Peak memory 205748 kb
Host smart-e8041630-e23b-4397-a91c-4192fe82fd7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33951
37355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3395137355
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.4268214666
Short name T970
Test name
Test status
Simulation time 18623675784 ps
CPU time 91.86 seconds
Started Jun 02 03:27:11 PM PDT 24
Finished Jun 02 03:28:44 PM PDT 24
Peak memory 205660 kb
Host smart-5e1a6381-9439-469f-a0e9-44ebadddd8f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42682
14666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.4268214666
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1650818799
Short name T336
Test name
Test status
Simulation time 10048599128 ps
CPU time 16.12 seconds
Started Jun 02 03:27:12 PM PDT 24
Finished Jun 02 03:27:29 PM PDT 24
Peak memory 205708 kb
Host smart-345544b4-2977-40ea-913a-877975ad330e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16508
18799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1650818799
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.3292841016
Short name T1424
Test name
Test status
Simulation time 10101117840 ps
CPU time 17.14 seconds
Started Jun 02 03:27:11 PM PDT 24
Finished Jun 02 03:27:28 PM PDT 24
Peak memory 205664 kb
Host smart-9cb0e6e9-f923-4681-9a9b-f0ef089b6e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32928
41016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.3292841016
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.2480293341
Short name T742
Test name
Test status
Simulation time 10072333416 ps
CPU time 14.48 seconds
Started Jun 02 03:27:15 PM PDT 24
Finished Jun 02 03:27:30 PM PDT 24
Peak memory 205680 kb
Host smart-b134803c-25d5-4ef9-a0ff-bb37e056391c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24802
93341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.2480293341
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.2054143474
Short name T1388
Test name
Test status
Simulation time 10070946391 ps
CPU time 13.96 seconds
Started Jun 02 03:27:11 PM PDT 24
Finished Jun 02 03:27:25 PM PDT 24
Peak memory 205764 kb
Host smart-fcebf54f-5e34-416b-868e-82ace10e2664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20541
43474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2054143474
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.3739553131
Short name T948
Test name
Test status
Simulation time 10094776906 ps
CPU time 13.85 seconds
Started Jun 02 03:27:11 PM PDT 24
Finished Jun 02 03:27:26 PM PDT 24
Peak memory 205688 kb
Host smart-a3a3da74-c6dc-4e25-92dd-32d4e6b79ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37395
53131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.3739553131
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.4049215145
Short name T1855
Test name
Test status
Simulation time 10046320406 ps
CPU time 12.93 seconds
Started Jun 02 03:27:18 PM PDT 24
Finished Jun 02 03:27:32 PM PDT 24
Peak memory 205756 kb
Host smart-b9c4971a-ade0-4a21-b020-d73f9e3f3896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40492
15145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.4049215145
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_eop_single_bit_handling.1791707612
Short name T322
Test name
Test status
Simulation time 10084221720 ps
CPU time 13.78 seconds
Started Jun 02 03:27:16 PM PDT 24
Finished Jun 02 03:27:31 PM PDT 24
Peak memory 205692 kb
Host smart-da8e9f4f-40ab-4dfb-9a88-894303633439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17917
07612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_eop_single_bit_handling.1791707612
Directory /workspace/5.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.2738966704
Short name T1384
Test name
Test status
Simulation time 10079675933 ps
CPU time 13.51 seconds
Started Jun 02 03:27:16 PM PDT 24
Finished Jun 02 03:27:31 PM PDT 24
Peak memory 205692 kb
Host smart-e78da417-c121-4300-b1dc-3314366d5ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27389
66704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.2738966704
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.759030852
Short name T46
Test name
Test status
Simulation time 10103184260 ps
CPU time 16.16 seconds
Started Jun 02 03:27:18 PM PDT 24
Finished Jun 02 03:27:36 PM PDT 24
Peak memory 205556 kb
Host smart-5897e7d4-777e-4ea1-ad4d-311e7871648d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75903
0852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.759030852
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.4163085716
Short name T1219
Test name
Test status
Simulation time 28196845481 ps
CPU time 54.29 seconds
Started Jun 02 03:27:13 PM PDT 24
Finished Jun 02 03:28:08 PM PDT 24
Peak memory 205716 kb
Host smart-20e911fb-e28f-4084-b568-728a470f64fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41630
85716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.4163085716
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.3330829268
Short name T790
Test name
Test status
Simulation time 10094186346 ps
CPU time 13.71 seconds
Started Jun 02 03:27:15 PM PDT 24
Finished Jun 02 03:27:30 PM PDT 24
Peak memory 205772 kb
Host smart-c05b7aa1-4276-4fac-a9d9-d47c52a26ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33308
29268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3330829268
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.4001053665
Short name T567
Test name
Test status
Simulation time 10132195854 ps
CPU time 14.35 seconds
Started Jun 02 03:27:10 PM PDT 24
Finished Jun 02 03:27:25 PM PDT 24
Peak memory 205696 kb
Host smart-d1096819-1b1a-44e5-9ad6-c9651633bf0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40010
53665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.4001053665
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.2815144978
Short name T454
Test name
Test status
Simulation time 31420341093 ps
CPU time 139.34 seconds
Started Jun 02 03:27:11 PM PDT 24
Finished Jun 02 03:29:32 PM PDT 24
Peak memory 205752 kb
Host smart-b6eba7e8-93c4-4687-852e-98a9fed8194f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2815144978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.2815144978
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.3827415124
Short name T1699
Test name
Test status
Simulation time 26926279720 ps
CPU time 492.81 seconds
Started Jun 02 03:27:13 PM PDT 24
Finished Jun 02 03:35:27 PM PDT 24
Peak memory 205792 kb
Host smart-5b66f473-f58b-47ca-b790-f95937920a39
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3827415124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.3827415124
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.1793075195
Short name T1025
Test name
Test status
Simulation time 34895840941 ps
CPU time 179.61 seconds
Started Jun 02 03:27:12 PM PDT 24
Finished Jun 02 03:30:13 PM PDT 24
Peak memory 205760 kb
Host smart-183ed17f-a466-435a-bce6-955170b6cc3e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1793075195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.1793075195
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.2468831368
Short name T1875
Test name
Test status
Simulation time 10066248647 ps
CPU time 13.63 seconds
Started Jun 02 03:27:11 PM PDT 24
Finished Jun 02 03:27:25 PM PDT 24
Peak memory 205624 kb
Host smart-c4e702d4-914f-4214-8e58-021ea63c0bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24688
31368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.2468831368
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.2420214541
Short name T2007
Test name
Test status
Simulation time 10051434000 ps
CPU time 13.2 seconds
Started Jun 02 03:27:21 PM PDT 24
Finished Jun 02 03:27:35 PM PDT 24
Peak memory 205608 kb
Host smart-aaaa08a3-5eef-46a3-aec3-58e78fbbffe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24202
14541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.2420214541
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.1146966042
Short name T1326
Test name
Test status
Simulation time 10060461902 ps
CPU time 16.43 seconds
Started Jun 02 03:27:18 PM PDT 24
Finished Jun 02 03:27:36 PM PDT 24
Peak memory 205732 kb
Host smart-242e3b7d-e542-499c-8345-3bdad7c43a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11469
66042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.1146966042
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.765994455
Short name T1538
Test name
Test status
Simulation time 10049496137 ps
CPU time 13.45 seconds
Started Jun 02 03:27:19 PM PDT 24
Finished Jun 02 03:27:33 PM PDT 24
Peak memory 205636 kb
Host smart-2de37755-9f70-483c-bf20-138abe8f394a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76599
4455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.765994455
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2861756462
Short name T1665
Test name
Test status
Simulation time 10110457956 ps
CPU time 14.72 seconds
Started Jun 02 03:27:06 PM PDT 24
Finished Jun 02 03:27:22 PM PDT 24
Peak memory 205780 kb
Host smart-c72b65e3-88c9-4057-a2f8-093648bde9b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28617
56462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2861756462
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.3807862448
Short name T1016
Test name
Test status
Simulation time 10080598058 ps
CPU time 12.7 seconds
Started Jun 02 03:27:17 PM PDT 24
Finished Jun 02 03:27:31 PM PDT 24
Peak memory 205740 kb
Host smart-b57ea2d9-5838-4f51-9401-08638ba4c6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38078
62448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.3807862448
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.557437841
Short name T1179
Test name
Test status
Simulation time 10071177849 ps
CPU time 14.15 seconds
Started Jun 02 03:27:18 PM PDT 24
Finished Jun 02 03:27:34 PM PDT 24
Peak memory 205784 kb
Host smart-e6ff1812-b21b-4530-a4aa-1c21c66be94f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55743
7841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.557437841
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.1424292800
Short name T1528
Test name
Test status
Simulation time 22963573642 ps
CPU time 132.08 seconds
Started Jun 02 03:27:18 PM PDT 24
Finished Jun 02 03:29:32 PM PDT 24
Peak memory 205680 kb
Host smart-86a46512-4bfc-47f1-a064-5bc79920804d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14242
92800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.1424292800
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.2046227209
Short name T436
Test name
Test status
Simulation time 10148314960 ps
CPU time 13.31 seconds
Started Jun 02 03:27:25 PM PDT 24
Finished Jun 02 03:27:39 PM PDT 24
Peak memory 205584 kb
Host smart-cac4520b-068b-4ec3-9986-e2835eefefa1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2046227209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.2046227209
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.1250754819
Short name T289
Test name
Test status
Simulation time 10058615874 ps
CPU time 12.87 seconds
Started Jun 02 03:27:29 PM PDT 24
Finished Jun 02 03:27:42 PM PDT 24
Peak memory 205764 kb
Host smart-6d788f94-d913-4583-86cd-5d6ee74a2aa6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1250754819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.1250754819
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.2332172945
Short name T1344
Test name
Test status
Simulation time 10165780114 ps
CPU time 14.82 seconds
Started Jun 02 03:27:29 PM PDT 24
Finished Jun 02 03:27:45 PM PDT 24
Peak memory 205676 kb
Host smart-9b0a93db-4718-4832-9882-ade9f152fea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23321
72945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.2332172945
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.1063283504
Short name T1259
Test name
Test status
Simulation time 13378246506 ps
CPU time 16.74 seconds
Started Jun 02 03:27:17 PM PDT 24
Finished Jun 02 03:27:35 PM PDT 24
Peak memory 205728 kb
Host smart-9e708650-fd02-4888-b764-53e8ae9d6485
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1063283504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.1063283504
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.1567296997
Short name T1951
Test name
Test status
Simulation time 23272498605 ps
CPU time 27.73 seconds
Started Jun 02 03:27:17 PM PDT 24
Finished Jun 02 03:27:46 PM PDT 24
Peak memory 205784 kb
Host smart-845f1482-d567-4b6e-bfd3-04e6b02f5727
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1567296997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.1567296997
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.443485907
Short name T987
Test name
Test status
Simulation time 10064840342 ps
CPU time 12.82 seconds
Started Jun 02 03:27:19 PM PDT 24
Finished Jun 02 03:27:33 PM PDT 24
Peak memory 205700 kb
Host smart-82482de4-b4ab-4c2a-9f58-a86ced7e6d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44348
5907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.443485907
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.4257540662
Short name T1544
Test name
Test status
Simulation time 10470250142 ps
CPU time 14.47 seconds
Started Jun 02 03:27:19 PM PDT 24
Finished Jun 02 03:27:35 PM PDT 24
Peak memory 205680 kb
Host smart-6d81d586-44ff-4163-b78c-8afa40579c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42575
40662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.4257540662
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.2057495703
Short name T2018
Test name
Test status
Simulation time 10077584769 ps
CPU time 13.43 seconds
Started Jun 02 03:27:22 PM PDT 24
Finished Jun 02 03:27:37 PM PDT 24
Peak memory 205716 kb
Host smart-272f74c5-002e-4a55-a9f5-5fcefa0b9ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20574
95703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2057495703
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.3565617185
Short name T1708
Test name
Test status
Simulation time 10052411511 ps
CPU time 14.08 seconds
Started Jun 02 03:27:18 PM PDT 24
Finished Jun 02 03:27:33 PM PDT 24
Peak memory 205644 kb
Host smart-df06e6e4-d8e9-4a74-b6b9-ae25511b50b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35656
17185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3565617185
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.1352891588
Short name T1011
Test name
Test status
Simulation time 10817951268 ps
CPU time 15.38 seconds
Started Jun 02 03:27:17 PM PDT 24
Finished Jun 02 03:27:33 PM PDT 24
Peak memory 205736 kb
Host smart-a72f1055-9fca-4ed8-b82b-71f780099c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13528
91588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.1352891588
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1387672084
Short name T1833
Test name
Test status
Simulation time 10063614808 ps
CPU time 19.4 seconds
Started Jun 02 03:27:21 PM PDT 24
Finished Jun 02 03:27:42 PM PDT 24
Peak memory 205660 kb
Host smart-42482cc8-97bf-4e4f-a7d2-6bb6d4a8d4e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13876
72084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1387672084
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.3755465231
Short name T656
Test name
Test status
Simulation time 10157225369 ps
CPU time 14.15 seconds
Started Jun 02 03:27:30 PM PDT 24
Finished Jun 02 03:27:45 PM PDT 24
Peak memory 205740 kb
Host smart-3690df39-6b22-4a30-a4a6-41db30a36567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37554
65231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.3755465231
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.1732386718
Short name T1664
Test name
Test status
Simulation time 10072077884 ps
CPU time 16.3 seconds
Started Jun 02 03:27:27 PM PDT 24
Finished Jun 02 03:27:45 PM PDT 24
Peak memory 205776 kb
Host smart-094f3f35-4811-478f-82dd-5b0c3a0719fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17323
86718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.1732386718
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.3398651481
Short name T1797
Test name
Test status
Simulation time 10059043580 ps
CPU time 14.47 seconds
Started Jun 02 03:27:24 PM PDT 24
Finished Jun 02 03:27:40 PM PDT 24
Peak memory 205656 kb
Host smart-f3614ee9-6378-4bd5-8c29-4a3e2120ff8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33986
51481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.3398651481
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.2722817751
Short name T1442
Test name
Test status
Simulation time 10129838667 ps
CPU time 14.66 seconds
Started Jun 02 03:27:21 PM PDT 24
Finished Jun 02 03:27:37 PM PDT 24
Peak memory 205780 kb
Host smart-a7a075d1-ef47-4c60-b019-57f5247ba444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27228
17751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.2722817751
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.3528545191
Short name T1798
Test name
Test status
Simulation time 13190000755 ps
CPU time 16.93 seconds
Started Jun 02 03:27:23 PM PDT 24
Finished Jun 02 03:27:40 PM PDT 24
Peak memory 205744 kb
Host smart-1987ffd4-3204-4494-90b3-cac5e91de055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35285
45191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.3528545191
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.3342490466
Short name T1938
Test name
Test status
Simulation time 10111206569 ps
CPU time 13.23 seconds
Started Jun 02 03:27:22 PM PDT 24
Finished Jun 02 03:27:37 PM PDT 24
Peak memory 205660 kb
Host smart-c5668543-6fd8-4c85-ad5c-1c4acea12aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33424
90466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.3342490466
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.3148189621
Short name T1047
Test name
Test status
Simulation time 20904888181 ps
CPU time 325.75 seconds
Started Jun 02 03:27:22 PM PDT 24
Finished Jun 02 03:32:49 PM PDT 24
Peak memory 205660 kb
Host smart-0e7c2393-ccda-4ce3-9450-9cebbf87eabd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31481
89621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.3148189621
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.4201025057
Short name T337
Test name
Test status
Simulation time 10050653651 ps
CPU time 15.62 seconds
Started Jun 02 03:27:23 PM PDT 24
Finished Jun 02 03:27:40 PM PDT 24
Peak memory 205700 kb
Host smart-a3f7b701-1af2-4b6f-8cd4-d99eab04d0af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42010
25057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.4201025057
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3059252228
Short name T122
Test name
Test status
Simulation time 10097140778 ps
CPU time 14.71 seconds
Started Jun 02 03:27:26 PM PDT 24
Finished Jun 02 03:27:42 PM PDT 24
Peak memory 205772 kb
Host smart-00ac0c18-1808-4772-aadc-f77d33d0a2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30592
52228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3059252228
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.3628219837
Short name T1786
Test name
Test status
Simulation time 10074753746 ps
CPU time 14.63 seconds
Started Jun 02 03:27:21 PM PDT 24
Finished Jun 02 03:27:37 PM PDT 24
Peak memory 205696 kb
Host smart-1f3c9913-47e9-46cb-9268-2dc1f1111318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36282
19837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.3628219837
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.182050317
Short name T1138
Test name
Test status
Simulation time 10082699654 ps
CPU time 12.91 seconds
Started Jun 02 03:27:23 PM PDT 24
Finished Jun 02 03:27:36 PM PDT 24
Peak memory 205616 kb
Host smart-053fbea6-7ec4-41cb-b610-40865f40f64e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18205
0317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.182050317
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1326700027
Short name T967
Test name
Test status
Simulation time 10060456221 ps
CPU time 13.63 seconds
Started Jun 02 03:27:24 PM PDT 24
Finished Jun 02 03:27:38 PM PDT 24
Peak memory 205736 kb
Host smart-f6c135a2-3a9c-4ea9-9921-3fa43f6c5c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13267
00027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1326700027
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.4053056078
Short name T140
Test name
Test status
Simulation time 10054310800 ps
CPU time 13.1 seconds
Started Jun 02 03:27:28 PM PDT 24
Finished Jun 02 03:27:42 PM PDT 24
Peak memory 205788 kb
Host smart-39f5ec0f-16d3-4aec-bb01-aa938d372fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40530
56078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.4053056078
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_eop_single_bit_handling.1898501410
Short name T1345
Test name
Test status
Simulation time 10112599090 ps
CPU time 13.2 seconds
Started Jun 02 03:27:30 PM PDT 24
Finished Jun 02 03:27:44 PM PDT 24
Peak memory 205648 kb
Host smart-2dcb2e58-0ab1-40e3-9114-017c39c40d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18985
01410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_eop_single_bit_handling.1898501410
Directory /workspace/6.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.3414923275
Short name T1949
Test name
Test status
Simulation time 10065484712 ps
CPU time 14.4 seconds
Started Jun 02 03:27:29 PM PDT 24
Finished Jun 02 03:27:44 PM PDT 24
Peak memory 205736 kb
Host smart-8361fea7-3e96-4585-a13c-0aad115f3528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34149
23275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.3414923275
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.3479095534
Short name T1644
Test name
Test status
Simulation time 10064886137 ps
CPU time 12.62 seconds
Started Jun 02 03:27:27 PM PDT 24
Finished Jun 02 03:27:41 PM PDT 24
Peak memory 205744 kb
Host smart-1f4391f8-538a-4325-a41d-85779642cffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34790
95534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.3479095534
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1576256621
Short name T1696
Test name
Test status
Simulation time 21431910035 ps
CPU time 37.42 seconds
Started Jun 02 03:27:26 PM PDT 24
Finished Jun 02 03:28:04 PM PDT 24
Peak memory 205696 kb
Host smart-052d79c5-677d-485f-a4ce-5322f088d53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15762
56621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1576256621
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.4069370500
Short name T1844
Test name
Test status
Simulation time 10051868579 ps
CPU time 13.43 seconds
Started Jun 02 03:27:24 PM PDT 24
Finished Jun 02 03:27:38 PM PDT 24
Peak memory 205628 kb
Host smart-f8020001-0bac-4f17-ad4c-d76a35e22f0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40693
70500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.4069370500
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.1180366454
Short name T1035
Test name
Test status
Simulation time 10188080340 ps
CPU time 14.33 seconds
Started Jun 02 03:27:21 PM PDT 24
Finished Jun 02 03:27:37 PM PDT 24
Peak memory 205660 kb
Host smart-a152a956-707c-4091-a6ac-4661eb12d108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11803
66454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1180366454
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.3663952240
Short name T1547
Test name
Test status
Simulation time 30879357856 ps
CPU time 182.89 seconds
Started Jun 02 03:27:22 PM PDT 24
Finished Jun 02 03:30:26 PM PDT 24
Peak memory 205736 kb
Host smart-d70eb712-0409-4d92-a2cd-9c380291c03d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3663952240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.3663952240
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.2118469710
Short name T1398
Test name
Test status
Simulation time 27279419938 ps
CPU time 112.11 seconds
Started Jun 02 03:27:22 PM PDT 24
Finished Jun 02 03:29:16 PM PDT 24
Peak memory 205724 kb
Host smart-0410ebe6-5d98-4bcd-8bbb-dd15b147634d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2118469710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.2118469710
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.3344564857
Short name T1486
Test name
Test status
Simulation time 10050648309 ps
CPU time 14.18 seconds
Started Jun 02 03:27:24 PM PDT 24
Finished Jun 02 03:27:39 PM PDT 24
Peak memory 205624 kb
Host smart-9898b4f7-2674-4883-9d1b-27788c8be98d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33445
64857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.3344564857
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.1006644963
Short name T896
Test name
Test status
Simulation time 10051719317 ps
CPU time 12.97 seconds
Started Jun 02 03:27:28 PM PDT 24
Finished Jun 02 03:27:42 PM PDT 24
Peak memory 205748 kb
Host smart-1bf01878-90eb-4f9b-bad6-78e7645f6930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10066
44963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.1006644963
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.3280446003
Short name T1932
Test name
Test status
Simulation time 10075402769 ps
CPU time 12.5 seconds
Started Jun 02 03:27:26 PM PDT 24
Finished Jun 02 03:27:39 PM PDT 24
Peak memory 205704 kb
Host smart-a1831738-e27d-4b29-9117-f1fe40e99944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32804
46003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.3280446003
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.2862415104
Short name T541
Test name
Test status
Simulation time 10084846545 ps
CPU time 13.25 seconds
Started Jun 02 03:27:30 PM PDT 24
Finished Jun 02 03:27:45 PM PDT 24
Peak memory 205752 kb
Host smart-dcf3669e-71f4-45f4-aca4-663e55382428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28624
15104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.2862415104
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1593325594
Short name T1478
Test name
Test status
Simulation time 10091118976 ps
CPU time 15.57 seconds
Started Jun 02 03:27:19 PM PDT 24
Finished Jun 02 03:27:36 PM PDT 24
Peak memory 205700 kb
Host smart-e2721a9a-7a81-4bb8-8e3f-579a952e1d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15933
25594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1593325594
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.3971525514
Short name T456
Test name
Test status
Simulation time 10053544725 ps
CPU time 12.86 seconds
Started Jun 02 03:27:28 PM PDT 24
Finished Jun 02 03:27:41 PM PDT 24
Peak memory 205780 kb
Host smart-fc0713b8-bdb7-4ce6-be20-b3de2ddadb49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39715
25514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.3971525514
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.3187746301
Short name T996
Test name
Test status
Simulation time 10074577620 ps
CPU time 13.39 seconds
Started Jun 02 03:27:28 PM PDT 24
Finished Jun 02 03:27:42 PM PDT 24
Peak memory 205636 kb
Host smart-7d2bdea7-c58f-48f2-8add-b0ad63cd8462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31877
46301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.3187746301
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.327021745
Short name T1714
Test name
Test status
Simulation time 23677799278 ps
CPU time 146.03 seconds
Started Jun 02 03:27:30 PM PDT 24
Finished Jun 02 03:29:58 PM PDT 24
Peak memory 205708 kb
Host smart-b3b8bb6d-6cd6-41ef-98d8-93ef629c8cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32702
1745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.327021745
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.3747710463
Short name T1620
Test name
Test status
Simulation time 10144011729 ps
CPU time 13.76 seconds
Started Jun 02 03:27:51 PM PDT 24
Finished Jun 02 03:28:06 PM PDT 24
Peak memory 205464 kb
Host smart-7a924fa4-87e5-4ffe-a9a0-c7ee3c7d72d8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3747710463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.3747710463
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.3615571136
Short name T811
Test name
Test status
Simulation time 10051470815 ps
CPU time 12.93 seconds
Started Jun 02 03:27:47 PM PDT 24
Finished Jun 02 03:28:01 PM PDT 24
Peak memory 205652 kb
Host smart-5dc6b183-7b1c-417c-bdac-6b4774feb4c8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3615571136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.3615571136
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.3764924770
Short name T2022
Test name
Test status
Simulation time 10118489485 ps
CPU time 13.46 seconds
Started Jun 02 03:27:43 PM PDT 24
Finished Jun 02 03:27:57 PM PDT 24
Peak memory 205716 kb
Host smart-5832786d-e135-44f9-a437-574bef26b073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37649
24770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.3764924770
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.2901591913
Short name T1102
Test name
Test status
Simulation time 14086139312 ps
CPU time 18.06 seconds
Started Jun 02 03:27:32 PM PDT 24
Finished Jun 02 03:27:52 PM PDT 24
Peak memory 205664 kb
Host smart-c5cc9149-a15d-494d-9329-e82165a669e4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2901591913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.2901591913
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.1314090253
Short name T1988
Test name
Test status
Simulation time 23329528502 ps
CPU time 24.16 seconds
Started Jun 02 03:27:34 PM PDT 24
Finished Jun 02 03:28:00 PM PDT 24
Peak memory 205668 kb
Host smart-43df3e03-7e56-4ea9-bfb6-66bc98422511
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1314090253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.1314090253
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.341018555
Short name T1491
Test name
Test status
Simulation time 10075858122 ps
CPU time 13.01 seconds
Started Jun 02 03:27:33 PM PDT 24
Finished Jun 02 03:27:47 PM PDT 24
Peak memory 205664 kb
Host smart-dae60e4f-dc9c-4758-991c-012acc643a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34101
8555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.341018555
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.2693100575
Short name T1008
Test name
Test status
Simulation time 10051775133 ps
CPU time 13.84 seconds
Started Jun 02 03:27:32 PM PDT 24
Finished Jun 02 03:27:47 PM PDT 24
Peak memory 205676 kb
Host smart-177c26cc-40ad-4c3f-8a38-d99dd2588c25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26931
00575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.2693100575
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.683591850
Short name T1755
Test name
Test status
Simulation time 10667652050 ps
CPU time 15.11 seconds
Started Jun 02 03:27:32 PM PDT 24
Finished Jun 02 03:27:48 PM PDT 24
Peak memory 205596 kb
Host smart-6e7bbc2b-1ff5-49b1-bc09-dd6d77b500d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68359
1850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.683591850
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.3867171107
Short name T1637
Test name
Test status
Simulation time 10036708688 ps
CPU time 14.04 seconds
Started Jun 02 03:27:34 PM PDT 24
Finished Jun 02 03:27:49 PM PDT 24
Peak memory 205584 kb
Host smart-b82b54cb-723e-49f8-a6ff-42ae1f681933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38671
71107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.3867171107
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.771264423
Short name T1919
Test name
Test status
Simulation time 10049948542 ps
CPU time 14.38 seconds
Started Jun 02 03:27:34 PM PDT 24
Finished Jun 02 03:27:50 PM PDT 24
Peak memory 205780 kb
Host smart-9114713d-4a0a-4116-a6be-5c4a0151bbeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77126
4423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.771264423
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.3530367936
Short name T626
Test name
Test status
Simulation time 10777158891 ps
CPU time 15.15 seconds
Started Jun 02 03:27:35 PM PDT 24
Finished Jun 02 03:27:51 PM PDT 24
Peak memory 205792 kb
Host smart-b45e537f-9154-4694-aa12-cff9ab64841a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35303
67936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.3530367936
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.901411435
Short name T1267
Test name
Test status
Simulation time 10197919713 ps
CPU time 15.62 seconds
Started Jun 02 03:27:31 PM PDT 24
Finished Jun 02 03:27:48 PM PDT 24
Peak memory 205680 kb
Host smart-9bb35cb2-2e58-417e-b40c-9d40a17272c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90141
1435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.901411435
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.3288249123
Short name T1737
Test name
Test status
Simulation time 10105547122 ps
CPU time 15.75 seconds
Started Jun 02 03:27:43 PM PDT 24
Finished Jun 02 03:27:59 PM PDT 24
Peak memory 205704 kb
Host smart-ea2e5ea7-056c-4301-a010-8e9b901ce582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32882
49123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.3288249123
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3041048636
Short name T1489
Test name
Test status
Simulation time 10042880467 ps
CPU time 13.82 seconds
Started Jun 02 03:27:47 PM PDT 24
Finished Jun 02 03:28:02 PM PDT 24
Peak memory 205764 kb
Host smart-e12f686c-8b3d-4cc7-bca9-68de34123274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30410
48636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3041048636
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3837749761
Short name T1319
Test name
Test status
Simulation time 10152694017 ps
CPU time 12.86 seconds
Started Jun 02 03:27:34 PM PDT 24
Finished Jun 02 03:27:48 PM PDT 24
Peak memory 205728 kb
Host smart-7fefdce3-e759-481a-8b56-530a14e23b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38377
49761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3837749761
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.3590622204
Short name T2020
Test name
Test status
Simulation time 10100456367 ps
CPU time 12.53 seconds
Started Jun 02 03:27:32 PM PDT 24
Finished Jun 02 03:27:46 PM PDT 24
Peak memory 205584 kb
Host smart-060193eb-d8a8-4bf2-9740-7cdadc064304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35906
22204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.3590622204
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.1313791060
Short name T1511
Test name
Test status
Simulation time 13255884261 ps
CPU time 17.26 seconds
Started Jun 02 03:27:32 PM PDT 24
Finished Jun 02 03:27:50 PM PDT 24
Peak memory 205736 kb
Host smart-ceb840f9-2fed-45ff-a734-312df277f24f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13137
91060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.1313791060
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.4098261618
Short name T1746
Test name
Test status
Simulation time 10096813397 ps
CPU time 14.77 seconds
Started Jun 02 03:27:32 PM PDT 24
Finished Jun 02 03:27:48 PM PDT 24
Peak memory 205736 kb
Host smart-6f8dcc43-5d57-4239-ad91-e2bcc590ab1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40982
61618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.4098261618
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.4032238331
Short name T1173
Test name
Test status
Simulation time 15169715699 ps
CPU time 151.37 seconds
Started Jun 02 03:27:34 PM PDT 24
Finished Jun 02 03:30:07 PM PDT 24
Peak memory 205648 kb
Host smart-52f4f9e2-f7f5-4776-9017-f2fcb079e16b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40322
38331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.4032238331
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.1158928336
Short name T863
Test name
Test status
Simulation time 10054229186 ps
CPU time 15.92 seconds
Started Jun 02 03:27:32 PM PDT 24
Finished Jun 02 03:27:50 PM PDT 24
Peak memory 205660 kb
Host smart-d524fb61-ffad-4975-b52c-f60cd0252e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11589
28336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.1158928336
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.1634160182
Short name T1630
Test name
Test status
Simulation time 10091228612 ps
CPU time 13.08 seconds
Started Jun 02 03:27:32 PM PDT 24
Finished Jun 02 03:27:46 PM PDT 24
Peak memory 205744 kb
Host smart-77bdbeff-cb97-4e12-b545-382d8645cc64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16341
60182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1634160182
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.2868392382
Short name T1653
Test name
Test status
Simulation time 10094574339 ps
CPU time 12.9 seconds
Started Jun 02 03:27:32 PM PDT 24
Finished Jun 02 03:27:47 PM PDT 24
Peak memory 205816 kb
Host smart-bbaa82f2-5cd9-4817-9f4e-a4aa510ea80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28683
92382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.2868392382
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.3371286747
Short name T1567
Test name
Test status
Simulation time 10066241921 ps
CPU time 16.39 seconds
Started Jun 02 03:27:38 PM PDT 24
Finished Jun 02 03:27:55 PM PDT 24
Peak memory 205812 kb
Host smart-5a8e6de1-e693-4d8e-9760-1147f0ed7f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33712
86747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.3371286747
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.2181418421
Short name T369
Test name
Test status
Simulation time 10114635236 ps
CPU time 12.61 seconds
Started Jun 02 03:27:36 PM PDT 24
Finished Jun 02 03:27:50 PM PDT 24
Peak memory 205792 kb
Host smart-2bac250c-68b2-4198-9e8e-e8ead07d2186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21814
18421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.2181418421
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.2377484517
Short name T1850
Test name
Test status
Simulation time 10103868330 ps
CPU time 14 seconds
Started Jun 02 03:27:43 PM PDT 24
Finished Jun 02 03:27:58 PM PDT 24
Peak memory 205672 kb
Host smart-531daca8-0d7f-4678-867f-2406210e4cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23774
84517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.2377484517
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_eop_single_bit_handling.3807159836
Short name T596
Test name
Test status
Simulation time 10075733681 ps
CPU time 13.09 seconds
Started Jun 02 03:27:37 PM PDT 24
Finished Jun 02 03:27:51 PM PDT 24
Peak memory 205620 kb
Host smart-ef090c6d-5d25-48d4-80a4-dc3538c1bf0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38071
59836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_eop_single_bit_handling.3807159836
Directory /workspace/7.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.1905069858
Short name T889
Test name
Test status
Simulation time 10062432310 ps
CPU time 13.86 seconds
Started Jun 02 03:27:37 PM PDT 24
Finished Jun 02 03:27:51 PM PDT 24
Peak memory 205756 kb
Host smart-c1f4812e-7e9c-4321-8dff-0550e87d1214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19050
69858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.1905069858
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2683964152
Short name T393
Test name
Test status
Simulation time 10103096557 ps
CPU time 13.53 seconds
Started Jun 02 03:27:43 PM PDT 24
Finished Jun 02 03:27:57 PM PDT 24
Peak memory 205760 kb
Host smart-43ebeb7e-292e-4348-afc2-34e831d698c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26839
64152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2683964152
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.3187802367
Short name T938
Test name
Test status
Simulation time 10048251201 ps
CPU time 13.42 seconds
Started Jun 02 03:27:37 PM PDT 24
Finished Jun 02 03:27:51 PM PDT 24
Peak memory 205700 kb
Host smart-2332758d-272c-45e3-9313-4aac8dadd3f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31878
02367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.3187802367
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.1557598345
Short name T730
Test name
Test status
Simulation time 10179512356 ps
CPU time 13.39 seconds
Started Jun 02 03:27:39 PM PDT 24
Finished Jun 02 03:27:53 PM PDT 24
Peak memory 205764 kb
Host smart-32b032f2-c427-4f89-a193-b3abdf2b5f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15575
98345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1557598345
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.2612269065
Short name T164
Test name
Test status
Simulation time 37217970122 ps
CPU time 189.27 seconds
Started Jun 02 03:27:39 PM PDT 24
Finished Jun 02 03:30:49 PM PDT 24
Peak memory 205756 kb
Host smart-c7f39771-0978-4ecf-a1e0-692a3668f939
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2612269065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.2612269065
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.1613456191
Short name T1301
Test name
Test status
Simulation time 27595590475 ps
CPU time 111.46 seconds
Started Jun 02 03:27:36 PM PDT 24
Finished Jun 02 03:29:29 PM PDT 24
Peak memory 205776 kb
Host smart-3f39d8fe-04cf-426d-bd74-9c6e71fe1814
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1613456191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.1613456191
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.3210010431
Short name T977
Test name
Test status
Simulation time 10114704790 ps
CPU time 14.6 seconds
Started Jun 02 03:27:36 PM PDT 24
Finished Jun 02 03:27:52 PM PDT 24
Peak memory 205660 kb
Host smart-f565ecb5-a2fb-4045-88ea-626f0b6f9595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32100
10431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.3210010431
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.2422055530
Short name T588
Test name
Test status
Simulation time 10106804351 ps
CPU time 13.79 seconds
Started Jun 02 03:27:38 PM PDT 24
Finished Jun 02 03:27:52 PM PDT 24
Peak memory 205596 kb
Host smart-834a29a6-c445-46bd-ab48-253c05099c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24220
55530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.2422055530
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.3657616206
Short name T17
Test name
Test status
Simulation time 10060968959 ps
CPU time 13.56 seconds
Started Jun 02 03:27:39 PM PDT 24
Finished Jun 02 03:27:53 PM PDT 24
Peak memory 205740 kb
Host smart-93e0838f-b05c-4d0b-9c1f-34cfb64dc41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36576
16206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.3657616206
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3872940500
Short name T1928
Test name
Test status
Simulation time 10058913225 ps
CPU time 13.81 seconds
Started Jun 02 03:27:38 PM PDT 24
Finished Jun 02 03:27:53 PM PDT 24
Peak memory 205732 kb
Host smart-5c8514d4-b622-4686-a1fb-7750354ac9ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38729
40500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3872940500
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.1428695347
Short name T1067
Test name
Test status
Simulation time 10164905931 ps
CPU time 13.32 seconds
Started Jun 02 03:27:31 PM PDT 24
Finished Jun 02 03:27:45 PM PDT 24
Peak memory 205780 kb
Host smart-8c816c45-f56a-4c50-b194-b09862732cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14286
95347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1428695347
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.1364164307
Short name T1643
Test name
Test status
Simulation time 10085381046 ps
CPU time 15.65 seconds
Started Jun 02 03:27:37 PM PDT 24
Finished Jun 02 03:27:53 PM PDT 24
Peak memory 205628 kb
Host smart-88473096-0bb1-4dc6-8e71-f8a8c247c96f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13641
64307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1364164307
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.49630816
Short name T360
Test name
Test status
Simulation time 10088868573 ps
CPU time 14.55 seconds
Started Jun 02 03:27:37 PM PDT 24
Finished Jun 02 03:27:52 PM PDT 24
Peak memory 205752 kb
Host smart-51ad45d8-3b4a-44e5-b66c-38c574ada764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49630
816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.49630816
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.3637582735
Short name T2012
Test name
Test status
Simulation time 13995353118 ps
CPU time 124.01 seconds
Started Jun 02 03:27:36 PM PDT 24
Finished Jun 02 03:29:41 PM PDT 24
Peak memory 205684 kb
Host smart-8b97a07d-fb99-4d3b-b433-f7c7ef07d699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36375
82735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.3637582735
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.2750454723
Short name T1792
Test name
Test status
Simulation time 10138232225 ps
CPU time 13.87 seconds
Started Jun 02 03:27:47 PM PDT 24
Finished Jun 02 03:28:01 PM PDT 24
Peak memory 205660 kb
Host smart-3b5c514e-f385-42ee-adcf-7f26ba0aae75
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2750454723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.2750454723
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.345410651
Short name T372
Test name
Test status
Simulation time 10093307291 ps
CPU time 15.01 seconds
Started Jun 02 03:27:47 PM PDT 24
Finished Jun 02 03:28:03 PM PDT 24
Peak memory 205772 kb
Host smart-e03d8c0c-f230-45e3-907f-dd65de3dd505
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=345410651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.345410651
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.2234274874
Short name T835
Test name
Test status
Simulation time 10073603449 ps
CPU time 13.27 seconds
Started Jun 02 03:27:52 PM PDT 24
Finished Jun 02 03:28:06 PM PDT 24
Peak memory 205780 kb
Host smart-a9181f62-c5f6-498d-aad6-bf6faee64e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22342
74874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.2234274874
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.2064346621
Short name T2027
Test name
Test status
Simulation time 14170528516 ps
CPU time 17.57 seconds
Started Jun 02 03:27:51 PM PDT 24
Finished Jun 02 03:28:09 PM PDT 24
Peak memory 205664 kb
Host smart-07a9db7a-191e-4115-b3d7-01bfc024a736
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2064346621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.2064346621
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.258914944
Short name T14
Test name
Test status
Simulation time 23194493354 ps
CPU time 26.04 seconds
Started Jun 02 03:27:42 PM PDT 24
Finished Jun 02 03:28:09 PM PDT 24
Peak memory 205772 kb
Host smart-1312c256-69de-4e03-a832-05338d1f7a27
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=258914944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.258914944
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1757832906
Short name T1148
Test name
Test status
Simulation time 10097722618 ps
CPU time 15.97 seconds
Started Jun 02 03:27:41 PM PDT 24
Finished Jun 02 03:27:57 PM PDT 24
Peak memory 205748 kb
Host smart-7e988372-ebba-4a8f-b478-224132171324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17578
32906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1757832906
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.2010986381
Short name T963
Test name
Test status
Simulation time 10103524731 ps
CPU time 12.86 seconds
Started Jun 02 03:27:44 PM PDT 24
Finished Jun 02 03:27:57 PM PDT 24
Peak memory 205668 kb
Host smart-b6456ec3-e69a-4081-a8fe-04cfd25cfe8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20109
86381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.2010986381
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.2083615652
Short name T477
Test name
Test status
Simulation time 10048262724 ps
CPU time 14.54 seconds
Started Jun 02 03:27:44 PM PDT 24
Finished Jun 02 03:27:59 PM PDT 24
Peak memory 205764 kb
Host smart-3785bdf8-4342-4a5c-8c27-50b092b29167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20836
15652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.2083615652
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.3071597474
Short name T530
Test name
Test status
Simulation time 10073387941 ps
CPU time 15.09 seconds
Started Jun 02 03:27:44 PM PDT 24
Finished Jun 02 03:28:00 PM PDT 24
Peak memory 205744 kb
Host smart-e0ee6aed-8144-4099-90ce-10bc2140c22f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30715
97474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3071597474
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.1424184790
Short name T754
Test name
Test status
Simulation time 10790873080 ps
CPU time 15.07 seconds
Started Jun 02 03:27:44 PM PDT 24
Finished Jun 02 03:28:00 PM PDT 24
Peak memory 205624 kb
Host smart-5afb5b97-f4e5-4ef1-b03f-2920fd0690d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14241
84790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.1424184790
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.915454439
Short name T882
Test name
Test status
Simulation time 10104097631 ps
CPU time 13.63 seconds
Started Jun 02 03:27:45 PM PDT 24
Finished Jun 02 03:28:00 PM PDT 24
Peak memory 205756 kb
Host smart-46593c3f-5090-4137-9229-09e6430199a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91545
4439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.915454439
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.3843067629
Short name T873
Test name
Test status
Simulation time 10150906231 ps
CPU time 13.65 seconds
Started Jun 02 03:27:51 PM PDT 24
Finished Jun 02 03:28:06 PM PDT 24
Peak memory 205768 kb
Host smart-527492ae-cc0b-4620-b754-c9948de5d1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38430
67629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.3843067629
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1902178276
Short name T1121
Test name
Test status
Simulation time 10044888891 ps
CPU time 13.75 seconds
Started Jun 02 03:27:47 PM PDT 24
Finished Jun 02 03:28:02 PM PDT 24
Peak memory 205724 kb
Host smart-505a8aba-8c61-4897-853c-693ff5b0a834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19021
78276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1902178276
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3471416028
Short name T1320
Test name
Test status
Simulation time 10093042339 ps
CPU time 13.03 seconds
Started Jun 02 03:27:41 PM PDT 24
Finished Jun 02 03:27:55 PM PDT 24
Peak memory 205660 kb
Host smart-cab9e4eb-72dd-4f36-86d1-908a18a87661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34714
16028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3471416028
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.2690487827
Short name T1577
Test name
Test status
Simulation time 10097293804 ps
CPU time 12.8 seconds
Started Jun 02 03:27:44 PM PDT 24
Finished Jun 02 03:27:58 PM PDT 24
Peak memory 205764 kb
Host smart-91b04211-f7d1-4207-8c68-e5fac64f8d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26904
87827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.2690487827
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.2646052595
Short name T301
Test name
Test status
Simulation time 13234136189 ps
CPU time 16.77 seconds
Started Jun 02 03:27:41 PM PDT 24
Finished Jun 02 03:27:59 PM PDT 24
Peak memory 205688 kb
Host smart-fb484a58-efe1-4af5-b293-8557ca5d3ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26460
52595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.2646052595
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.1793322481
Short name T1838
Test name
Test status
Simulation time 10169673917 ps
CPU time 15.53 seconds
Started Jun 02 03:27:45 PM PDT 24
Finished Jun 02 03:28:01 PM PDT 24
Peak memory 205660 kb
Host smart-30e2de9d-f924-44ba-8c24-0a29d40e382e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17933
22481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.1793322481
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.924222486
Short name T997
Test name
Test status
Simulation time 24388361648 ps
CPU time 426.19 seconds
Started Jun 02 03:27:51 PM PDT 24
Finished Jun 02 03:34:58 PM PDT 24
Peak memory 205700 kb
Host smart-ed96f8c3-a3fc-41d4-ad57-6a2463b20b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92422
2486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.924222486
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.3367701344
Short name T710
Test name
Test status
Simulation time 10054105503 ps
CPU time 16.02 seconds
Started Jun 02 03:27:51 PM PDT 24
Finished Jun 02 03:28:08 PM PDT 24
Peak memory 205476 kb
Host smart-efa4c178-6ade-4d16-a1a1-d7f4e02ae9e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33677
01344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3367701344
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.4148764660
Short name T1871
Test name
Test status
Simulation time 10072325209 ps
CPU time 13.69 seconds
Started Jun 02 03:27:45 PM PDT 24
Finished Jun 02 03:27:59 PM PDT 24
Peak memory 205680 kb
Host smart-ca99cfdb-72da-4018-8080-3a25b3dd9a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41487
64660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.4148764660
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.3879198966
Short name T1650
Test name
Test status
Simulation time 10094786091 ps
CPU time 15.79 seconds
Started Jun 02 03:27:44 PM PDT 24
Finished Jun 02 03:28:00 PM PDT 24
Peak memory 205684 kb
Host smart-af4fa0cc-639d-4631-a89d-4ae50bbe72bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38791
98966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.3879198966
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.3778167719
Short name T1502
Test name
Test status
Simulation time 10072006776 ps
CPU time 16.23 seconds
Started Jun 02 03:27:43 PM PDT 24
Finished Jun 02 03:28:00 PM PDT 24
Peak memory 205652 kb
Host smart-714cda33-30b2-4645-99b2-6cb780faf0b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37781
67719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.3778167719
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1677357222
Short name T514
Test name
Test status
Simulation time 10080451987 ps
CPU time 13.95 seconds
Started Jun 02 03:27:45 PM PDT 24
Finished Jun 02 03:27:59 PM PDT 24
Peak memory 205724 kb
Host smart-0c4cd514-5ed5-4510-8b50-362e05f3b640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16773
57222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1677357222
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.2380243949
Short name T1299
Test name
Test status
Simulation time 10056442408 ps
CPU time 14.3 seconds
Started Jun 02 03:27:47 PM PDT 24
Finished Jun 02 03:28:02 PM PDT 24
Peak memory 205752 kb
Host smart-dec6d4c8-a420-4940-8f96-779441780284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23802
43949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.2380243949
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_eop_single_bit_handling.3794034192
Short name T806
Test name
Test status
Simulation time 10066436893 ps
CPU time 13.39 seconds
Started Jun 02 03:27:49 PM PDT 24
Finished Jun 02 03:28:04 PM PDT 24
Peak memory 205668 kb
Host smart-478cec4d-8877-4fd1-91e4-db89c789faa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37940
34192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_eop_single_bit_handling.3794034192
Directory /workspace/8.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.2356988744
Short name T1137
Test name
Test status
Simulation time 10054076045 ps
CPU time 13.31 seconds
Started Jun 02 03:27:52 PM PDT 24
Finished Jun 02 03:28:07 PM PDT 24
Peak memory 205748 kb
Host smart-e4ef3ec5-5e4c-4fcb-85ba-7602c17a6e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23569
88744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.2356988744
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3950122535
Short name T1222
Test name
Test status
Simulation time 10036685686 ps
CPU time 13.54 seconds
Started Jun 02 03:27:49 PM PDT 24
Finished Jun 02 03:28:04 PM PDT 24
Peak memory 205664 kb
Host smart-96156e24-ae68-46bc-b491-02bb0d49be4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39501
22535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3950122535
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.1184472953
Short name T1265
Test name
Test status
Simulation time 18780832491 ps
CPU time 34.6 seconds
Started Jun 02 03:27:42 PM PDT 24
Finished Jun 02 03:28:18 PM PDT 24
Peak memory 205652 kb
Host smart-e35b1395-7c54-4c53-b4d8-5729ec6e7fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11844
72953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.1184472953
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.1731973468
Short name T961
Test name
Test status
Simulation time 10053711204 ps
CPU time 14.3 seconds
Started Jun 02 03:27:48 PM PDT 24
Finished Jun 02 03:28:03 PM PDT 24
Peak memory 205768 kb
Host smart-1f689b03-8271-4b74-8942-3595a35d4376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17319
73468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.1731973468
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.2287071772
Short name T1136
Test name
Test status
Simulation time 10074362409 ps
CPU time 13.06 seconds
Started Jun 02 03:27:48 PM PDT 24
Finished Jun 02 03:28:02 PM PDT 24
Peak memory 205768 kb
Host smart-b012819c-8ade-411f-8e91-540a6c67fba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22870
71772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.2287071772
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.249792280
Short name T584
Test name
Test status
Simulation time 24257016277 ps
CPU time 303.03 seconds
Started Jun 02 03:27:49 PM PDT 24
Finished Jun 02 03:32:53 PM PDT 24
Peak memory 205776 kb
Host smart-781355a8-6ff7-4797-8d31-f819180326b1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=249792280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.249792280
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.3920682058
Short name T335
Test name
Test status
Simulation time 34919699701 ps
CPU time 229.21 seconds
Started Jun 02 03:27:48 PM PDT 24
Finished Jun 02 03:31:38 PM PDT 24
Peak memory 205700 kb
Host smart-fcbf259c-55e1-473c-bb5d-a06aca1bd1bf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3920682058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.3920682058
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.364707606
Short name T478
Test name
Test status
Simulation time 30890466084 ps
CPU time 494.32 seconds
Started Jun 02 03:27:49 PM PDT 24
Finished Jun 02 03:36:07 PM PDT 24
Peak memory 205792 kb
Host smart-5de7e035-a566-4ff7-9c06-93db04c62f0e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=364707606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.364707606
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.2691806659
Short name T1739
Test name
Test status
Simulation time 10054135724 ps
CPU time 16.83 seconds
Started Jun 02 03:27:52 PM PDT 24
Finished Jun 02 03:28:10 PM PDT 24
Peak memory 205672 kb
Host smart-7f8e2cdf-1aae-47da-8777-b959c898603b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26918
06659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.2691806659
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.1883642010
Short name T1115
Test name
Test status
Simulation time 10030298958 ps
CPU time 17.21 seconds
Started Jun 02 03:27:47 PM PDT 24
Finished Jun 02 03:28:04 PM PDT 24
Peak memory 205736 kb
Host smart-937b665f-3324-4641-8d7d-2306d78cc2f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18836
42010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.1883642010
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.496176384
Short name T981
Test name
Test status
Simulation time 10062422414 ps
CPU time 12.83 seconds
Started Jun 02 03:27:49 PM PDT 24
Finished Jun 02 03:28:03 PM PDT 24
Peak memory 205684 kb
Host smart-5f3fc564-edd7-4e5c-b03f-9c35f0f9fb95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49617
6384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.496176384
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.10181397
Short name T377
Test name
Test status
Simulation time 10057325726 ps
CPU time 12.93 seconds
Started Jun 02 03:27:46 PM PDT 24
Finished Jun 02 03:27:59 PM PDT 24
Peak memory 205744 kb
Host smart-762a89ad-e6eb-45f3-b82b-172c120f76c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10181
397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.10181397
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.4134225266
Short name T2001
Test name
Test status
Simulation time 10107244630 ps
CPU time 15.93 seconds
Started Jun 02 03:27:42 PM PDT 24
Finished Jun 02 03:27:59 PM PDT 24
Peak memory 205852 kb
Host smart-3d5a8afa-8799-428f-9f4e-59be1849a4d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41342
25266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.4134225266
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.1078202345
Short name T1837
Test name
Test status
Simulation time 10086080526 ps
CPU time 15.97 seconds
Started Jun 02 03:27:52 PM PDT 24
Finished Jun 02 03:28:09 PM PDT 24
Peak memory 205748 kb
Host smart-2949ab73-5620-4873-8b08-09671ab7e67b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10782
02345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.1078202345
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.4021295326
Short name T601
Test name
Test status
Simulation time 10061921499 ps
CPU time 14.63 seconds
Started Jun 02 03:27:50 PM PDT 24
Finished Jun 02 03:28:05 PM PDT 24
Peak memory 205628 kb
Host smart-d71ebaeb-b83e-47b1-96ec-f21069798248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40212
95326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.4021295326
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.3107734588
Short name T853
Test name
Test status
Simulation time 18246696450 ps
CPU time 233.26 seconds
Started Jun 02 03:27:49 PM PDT 24
Finished Jun 02 03:31:44 PM PDT 24
Peak memory 205640 kb
Host smart-53931f22-ef7c-4995-901b-98529b22af8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31077
34588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.3107734588
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.877525657
Short name T1757
Test name
Test status
Simulation time 10141708565 ps
CPU time 16.93 seconds
Started Jun 02 03:27:59 PM PDT 24
Finished Jun 02 03:28:17 PM PDT 24
Peak memory 205680 kb
Host smart-cbc3eeac-82de-4d44-98b3-db47b236af56
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=877525657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.877525657
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.3704953353
Short name T1463
Test name
Test status
Simulation time 10063497449 ps
CPU time 14.55 seconds
Started Jun 02 03:27:57 PM PDT 24
Finished Jun 02 03:28:13 PM PDT 24
Peak memory 205672 kb
Host smart-a20f6082-d6ab-4623-b35b-82c3d166ea01
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3704953353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.3704953353
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.2276387184
Short name T1101
Test name
Test status
Simulation time 10104967349 ps
CPU time 13.13 seconds
Started Jun 02 03:27:57 PM PDT 24
Finished Jun 02 03:28:10 PM PDT 24
Peak memory 205664 kb
Host smart-f248cbad-fba2-40e3-9b48-655781230683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22763
87184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.2276387184
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.2979207996
Short name T969
Test name
Test status
Simulation time 13894776622 ps
CPU time 17.47 seconds
Started Jun 02 03:27:52 PM PDT 24
Finished Jun 02 03:28:10 PM PDT 24
Peak memory 205696 kb
Host smart-89583a02-e8a8-407f-8b29-84e4c3ca6158
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2979207996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.2979207996
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.4279138205
Short name T778
Test name
Test status
Simulation time 23325032970 ps
CPU time 33.03 seconds
Started Jun 02 03:27:48 PM PDT 24
Finished Jun 02 03:28:22 PM PDT 24
Peak memory 205768 kb
Host smart-5350fabe-87a8-49db-82e9-7d8ba23c78f4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4279138205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.4279138205
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2153829888
Short name T1262
Test name
Test status
Simulation time 10056521106 ps
CPU time 16.06 seconds
Started Jun 02 03:27:49 PM PDT 24
Finished Jun 02 03:28:06 PM PDT 24
Peak memory 205632 kb
Host smart-8177e686-80bf-49d4-85f4-dbc6a31b1e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21538
29888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2153829888
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.3637726797
Short name T1007
Test name
Test status
Simulation time 10561318486 ps
CPU time 15.2 seconds
Started Jun 02 03:27:51 PM PDT 24
Finished Jun 02 03:28:08 PM PDT 24
Peak memory 205764 kb
Host smart-b5f8cb71-b665-45d6-9ece-58e16ecb61bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36377
26797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.3637726797
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.3557440186
Short name T892
Test name
Test status
Simulation time 10079898974 ps
CPU time 13.66 seconds
Started Jun 02 03:27:53 PM PDT 24
Finished Jun 02 03:28:08 PM PDT 24
Peak memory 205740 kb
Host smart-12265cf7-686b-4a36-be7a-06e8171cdc74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35574
40186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.3557440186
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.4134594024
Short name T355
Test name
Test status
Simulation time 10049371535 ps
CPU time 16.28 seconds
Started Jun 02 03:27:53 PM PDT 24
Finished Jun 02 03:28:11 PM PDT 24
Peak memory 205652 kb
Host smart-724c5e1e-e29d-4c47-8192-be72c1aa9261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41345
94024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.4134594024
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.1158222952
Short name T674
Test name
Test status
Simulation time 10768262395 ps
CPU time 15.22 seconds
Started Jun 02 03:27:53 PM PDT 24
Finished Jun 02 03:28:09 PM PDT 24
Peak memory 205720 kb
Host smart-5124b8d0-6829-43ab-99b0-397932be9472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11582
22952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.1158222952
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1937703106
Short name T1118
Test name
Test status
Simulation time 10101254330 ps
CPU time 14.27 seconds
Started Jun 02 03:27:52 PM PDT 24
Finished Jun 02 03:28:07 PM PDT 24
Peak memory 205696 kb
Host smart-e7221062-f2f6-4a79-b700-005aecf18c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19377
03106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1937703106
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.1328143345
Short name T1941
Test name
Test status
Simulation time 10104702791 ps
CPU time 13.25 seconds
Started Jun 02 03:27:57 PM PDT 24
Finished Jun 02 03:28:11 PM PDT 24
Peak memory 205700 kb
Host smart-014c93f9-5b0c-480f-b17e-507d5679626e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13281
43345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.1328143345
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.1027576815
Short name T1114
Test name
Test status
Simulation time 10042143337 ps
CPU time 13.83 seconds
Started Jun 02 03:27:57 PM PDT 24
Finished Jun 02 03:28:12 PM PDT 24
Peak memory 205776 kb
Host smart-71f2a1a2-1588-454a-ba92-5274212f2f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10275
76815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1027576815
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.4012814370
Short name T1641
Test name
Test status
Simulation time 10075319397 ps
CPU time 13.77 seconds
Started Jun 02 03:27:51 PM PDT 24
Finished Jun 02 03:28:06 PM PDT 24
Peak memory 205688 kb
Host smart-508afd96-8aa5-484c-a696-135a26578201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40128
14370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.4012814370
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.4078252530
Short name T594
Test name
Test status
Simulation time 10085184598 ps
CPU time 15.15 seconds
Started Jun 02 03:27:52 PM PDT 24
Finished Jun 02 03:28:08 PM PDT 24
Peak memory 205784 kb
Host smart-cbef9105-fcce-4b8f-9ea3-a47cb26d46e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40782
52530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.4078252530
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.881651623
Short name T646
Test name
Test status
Simulation time 13196315815 ps
CPU time 15.79 seconds
Started Jun 02 03:27:54 PM PDT 24
Finished Jun 02 03:28:11 PM PDT 24
Peak memory 205768 kb
Host smart-801c73d1-9d75-4e68-9a46-278beefcd115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88165
1623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.881651623
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1375984413
Short name T307
Test name
Test status
Simulation time 10093235129 ps
CPU time 14.78 seconds
Started Jun 02 03:27:52 PM PDT 24
Finished Jun 02 03:28:08 PM PDT 24
Peak memory 205704 kb
Host smart-95a0e6e1-faaa-4f25-a7d8-304ddd661fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13759
84413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1375984413
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.2922813078
Short name T1126
Test name
Test status
Simulation time 23607193863 ps
CPU time 149.35 seconds
Started Jun 02 03:27:53 PM PDT 24
Finished Jun 02 03:30:24 PM PDT 24
Peak memory 205616 kb
Host smart-c6ce2507-2ced-48c4-813e-c6925de99ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29228
13078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.2922813078
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.640407559
Short name T1635
Test name
Test status
Simulation time 10041899776 ps
CPU time 14.63 seconds
Started Jun 02 03:27:56 PM PDT 24
Finished Jun 02 03:28:11 PM PDT 24
Peak memory 205660 kb
Host smart-6b7b0580-c6b4-445f-9fa6-89e6baaf2fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64040
7559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.640407559
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.2300068267
Short name T106
Test name
Test status
Simulation time 10087539553 ps
CPU time 13.45 seconds
Started Jun 02 03:27:53 PM PDT 24
Finished Jun 02 03:28:08 PM PDT 24
Peak memory 205748 kb
Host smart-61a8b800-160c-4eb5-96e7-1e4382a37390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23000
68267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.2300068267
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.4031294990
Short name T1857
Test name
Test status
Simulation time 10059274741 ps
CPU time 16.47 seconds
Started Jun 02 03:27:56 PM PDT 24
Finished Jun 02 03:28:13 PM PDT 24
Peak memory 205740 kb
Host smart-a21085f6-5efc-4eb1-a3ec-5fff8ff994bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40312
94990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.4031294990
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2849284575
Short name T1192
Test name
Test status
Simulation time 10103049735 ps
CPU time 12.57 seconds
Started Jun 02 03:27:52 PM PDT 24
Finished Jun 02 03:28:05 PM PDT 24
Peak memory 205656 kb
Host smart-7f6425f1-96a9-43fe-b778-bd539dc67dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28492
84575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2849284575
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.498485312
Short name T1796
Test name
Test status
Simulation time 10060909122 ps
CPU time 13.27 seconds
Started Jun 02 03:27:54 PM PDT 24
Finished Jun 02 03:28:08 PM PDT 24
Peak memory 205760 kb
Host smart-03a4b9cd-d7de-464e-98bf-e68035cd843b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49848
5312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.498485312
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.2167729444
Short name T1565
Test name
Test status
Simulation time 10060292903 ps
CPU time 12.98 seconds
Started Jun 02 03:27:56 PM PDT 24
Finished Jun 02 03:28:10 PM PDT 24
Peak memory 205728 kb
Host smart-81410ac5-9bce-4c11-8332-e783a278dff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21677
29444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.2167729444
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_eop_single_bit_handling.282491799
Short name T1
Test name
Test status
Simulation time 10058082812 ps
CPU time 13.68 seconds
Started Jun 02 03:27:56 PM PDT 24
Finished Jun 02 03:28:10 PM PDT 24
Peak memory 205656 kb
Host smart-9a036400-c778-4568-9bdd-95be29436c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28249
1799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_eop_single_bit_handling.282491799
Directory /workspace/9.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.3653264873
Short name T1339
Test name
Test status
Simulation time 10065080499 ps
CPU time 12.92 seconds
Started Jun 02 03:27:59 PM PDT 24
Finished Jun 02 03:28:12 PM PDT 24
Peak memory 205660 kb
Host smart-5f1047fe-be68-45c5-9b18-2f3fc7db63eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36532
64873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3653264873
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.4222879438
Short name T1743
Test name
Test status
Simulation time 10055657049 ps
CPU time 14.74 seconds
Started Jun 02 03:27:58 PM PDT 24
Finished Jun 02 03:28:14 PM PDT 24
Peak memory 205552 kb
Host smart-8b701e5d-d6d4-4c43-b7b4-19ea51333567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42228
79438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.4222879438
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.333909082
Short name T1018
Test name
Test status
Simulation time 18542587077 ps
CPU time 33.27 seconds
Started Jun 02 03:27:54 PM PDT 24
Finished Jun 02 03:28:28 PM PDT 24
Peak memory 205624 kb
Host smart-e1705b76-c95d-4099-9a56-9a78a137446b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33390
9082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.333909082
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.641187371
Short name T2005
Test name
Test status
Simulation time 10105727923 ps
CPU time 15.62 seconds
Started Jun 02 03:27:55 PM PDT 24
Finished Jun 02 03:28:12 PM PDT 24
Peak memory 205764 kb
Host smart-11d47832-8bec-4f84-8929-d5c0f3df36ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64118
7371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.641187371
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.282585931
Short name T720
Test name
Test status
Simulation time 10115853660 ps
CPU time 14.14 seconds
Started Jun 02 03:27:55 PM PDT 24
Finished Jun 02 03:28:10 PM PDT 24
Peak memory 205760 kb
Host smart-bb541d98-ffff-404b-8179-de9828687964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28258
5931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.282585931
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.388473257
Short name T1684
Test name
Test status
Simulation time 15728725918 ps
CPU time 50.34 seconds
Started Jun 02 03:27:53 PM PDT 24
Finished Jun 02 03:28:45 PM PDT 24
Peak memory 205636 kb
Host smart-2150bedc-26e8-4073-a68e-75534548be69
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=388473257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.388473257
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.247960616
Short name T597
Test name
Test status
Simulation time 28233425305 ps
CPU time 183.47 seconds
Started Jun 02 03:27:54 PM PDT 24
Finished Jun 02 03:30:59 PM PDT 24
Peak memory 205732 kb
Host smart-4fd99874-7cbc-438c-b3b2-fe1287748544
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=247960616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.247960616
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.516708345
Short name T1157
Test name
Test status
Simulation time 29572613341 ps
CPU time 174.99 seconds
Started Jun 02 03:27:53 PM PDT 24
Finished Jun 02 03:30:50 PM PDT 24
Peak memory 205728 kb
Host smart-5d93ed12-dc8f-4e9f-8365-9868670da7f5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=516708345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.516708345
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.1559186379
Short name T475
Test name
Test status
Simulation time 10058629558 ps
CPU time 13.72 seconds
Started Jun 02 03:27:51 PM PDT 24
Finished Jun 02 03:28:06 PM PDT 24
Peak memory 205656 kb
Host smart-1ffd856c-5826-4a88-9bf2-fdfdcd4fcfc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15591
86379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.1559186379
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.4019161920
Short name T1847
Test name
Test status
Simulation time 10041832097 ps
CPU time 14.17 seconds
Started Jun 02 03:27:55 PM PDT 24
Finished Jun 02 03:28:10 PM PDT 24
Peak memory 205716 kb
Host smart-0ee0cb1e-20b1-46e4-ad1d-b2e4293bb55a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40191
61920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.4019161920
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.2758633777
Short name T1239
Test name
Test status
Simulation time 10093636756 ps
CPU time 13.2 seconds
Started Jun 02 03:27:58 PM PDT 24
Finished Jun 02 03:28:12 PM PDT 24
Peak memory 205560 kb
Host smart-ced97a4a-3f91-4739-b01b-af868e212f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27586
33777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.2758633777
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.249281580
Short name T843
Test name
Test status
Simulation time 10122731374 ps
CPU time 14.17 seconds
Started Jun 02 03:27:53 PM PDT 24
Finished Jun 02 03:28:08 PM PDT 24
Peak memory 205640 kb
Host smart-ba7b9a56-525c-40d1-a96c-2274de8d5e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24928
1580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.249281580
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.1387484818
Short name T539
Test name
Test status
Simulation time 10171808753 ps
CPU time 15.95 seconds
Started Jun 02 03:27:47 PM PDT 24
Finished Jun 02 03:28:04 PM PDT 24
Peak memory 205728 kb
Host smart-60e50bc1-4f9e-4974-8fbb-0da61d74fc1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13874
84818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1387484818
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.3383354973
Short name T1474
Test name
Test status
Simulation time 10075964405 ps
CPU time 15.76 seconds
Started Jun 02 03:27:55 PM PDT 24
Finished Jun 02 03:28:11 PM PDT 24
Peak memory 205708 kb
Host smart-b922b293-ca29-44fe-86a4-f1a6966b4a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33833
54973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.3383354973
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.671882148
Short name T1043
Test name
Test status
Simulation time 10131860544 ps
CPU time 16.89 seconds
Started Jun 02 03:27:54 PM PDT 24
Finished Jun 02 03:28:12 PM PDT 24
Peak memory 205676 kb
Host smart-b6251a0a-c2b0-4add-a945-79948213d061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67188
2148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.671882148
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.356267664
Short name T501
Test name
Test status
Simulation time 19155445752 ps
CPU time 74.52 seconds
Started Jun 02 03:27:54 PM PDT 24
Finished Jun 02 03:29:10 PM PDT 24
Peak memory 205640 kb
Host smart-aa2c0b3f-d62d-443b-a87c-734218e17f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35626
7664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.356267664
Directory /workspace/9.usbdev_streaming_out/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%