Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	118616	1		T1	3		T2	5		T3	4
all_values[1]	118616	1		T1	3		T2	5		T3	4
all_values[2]	118616	1		T1	3		T2	5		T3	4
all_values[3]	118616	1		T1	3		T2	5		T3	4
all_values[4]	118616	1		T1	3		T2	5		T3	4
all_values[5]	118616	1		T1	3		T2	5		T3	4
all_values[6]	118616	1		T1	3		T2	5		T3	4
all_values[7]	118616	1		T1	3		T2	5		T3	4
all_values[8]	118616	1		T1	3		T2	5		T3	4
all_values[9]	118616	1		T1	3		T2	5		T3	4
all_values[10]	118616	1		T1	3		T2	5		T3	4
all_values[11]	118616	1		T1	3		T2	5		T3	4
all_values[12]	118616	1		T1	3		T2	5		T3	4
all_values[13]	118616	1		T1	3		T2	5		T3	4
all_values[14]	118616	1		T1	3		T2	5		T3	4
all_values[15]	118616	1		T1	3		T2	5		T3	4
all_values[16]	118616	1		T1	3		T2	5		T3	4
all_values[17]	118616	1		T1	3		T2	5		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2129061	1		T1	54		T2	90		T3	68
auto[1]	6027	1		T3	4		T7	4		T48	4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2130347	1		T1	54		T2	90		T3	72
auto[1]	4741	1		T91	77		T92	72		T93	122

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	117631	1		T1	3		T2	5		T3	4
all_values[0]	auto[0]	auto[1]	128	1		T91	3		T92	1		T191	1
all_values[0]	auto[1]	auto[0]	735	1		T48	4		T50	4		T51	3
all_values[0]	auto[1]	auto[1]	122	1		T91	2		T92	3		T93	4
all_values[1]	auto[0]	auto[0]	116026	1		T1	3		T2	5		T25	2
all_values[1]	auto[0]	auto[1]	136	1		T91	4		T92	5		T93	3
all_values[1]	auto[1]	auto[0]	2323	1		T3	4		T7	4		T34	38
all_values[1]	auto[1]	auto[1]	131	1		T91	1		T93	5		T190	3
all_values[2]	auto[0]	auto[0]	118221	1		T1	3		T2	5		T3	4
all_values[2]	auto[0]	auto[1]	147	1		T92	5		T93	2		T190	5
all_values[2]	auto[1]	auto[0]	115	1		T44	2		T45	2		T46	2
all_values[2]	auto[1]	auto[1]	133	1		T91	4		T93	6		T192	5
all_values[3]	auto[0]	auto[0]	118327	1		T1	3		T2	5		T3	4
all_values[3]	auto[0]	auto[1]	126	1		T91	3		T92	1		T93	2
all_values[3]	auto[1]	auto[0]	25	1		T190	1		T272	1		T273	1
all_values[3]	auto[1]	auto[1]	138	1		T92	4		T93	6		T191	3
all_values[4]	auto[0]	auto[0]	118327	1		T1	3		T2	5		T3	4
all_values[4]	auto[0]	auto[1]	127	1		T91	4		T92	4		T93	2
all_values[4]	auto[1]	auto[0]	22	1		T92	1		T93	1		T190	2
all_values[4]	auto[1]	auto[1]	140	1		T91	1		T93	4		T191	1
all_values[5]	auto[0]	auto[0]	118321	1		T1	3		T2	5		T3	4
all_values[5]	auto[0]	auto[1]	137	1		T91	5		T92	3		T93	4
all_values[5]	auto[1]	auto[0]	25	1		T93	1		T190	1		T192	1
all_values[5]	auto[1]	auto[1]	133	1		T92	1		T191	2		T192	3
all_values[6]	auto[0]	auto[0]	118333	1		T1	3		T2	5		T3	4
all_values[6]	auto[0]	auto[1]	112	1		T92	2		T93	3		T192	3
all_values[6]	auto[1]	auto[0]	19	1		T91	1		T274	2		T275	2
all_values[6]	auto[1]	auto[1]	152	1		T91	3		T92	3		T93	5
all_values[7]	auto[0]	auto[0]	118336	1		T1	3		T2	5		T3	4
all_values[7]	auto[0]	auto[1]	105	1		T91	3		T92	4		T93	5
all_values[7]	auto[1]	auto[0]	31	1		T91	2		T92	1		T93	1
all_values[7]	auto[1]	auto[1]	144	1		T93	1		T190	1		T191	3
all_values[8]	auto[0]	auto[0]	118326	1		T1	3		T2	5		T3	4
all_values[8]	auto[0]	auto[1]	127	1		T91	3		T93	6		T191	4
all_values[8]	auto[1]	auto[0]	35	1		T92	4		T272	3		T273	5
all_values[8]	auto[1]	auto[1]	128	1		T91	2		T93	2		T190	5
all_values[9]	auto[0]	auto[0]	118322	1		T1	3		T2	5		T3	4
all_values[9]	auto[0]	auto[1]	119	1		T93	2		T190	4		T191	4
all_values[9]	auto[1]	auto[0]	19	1		T93	1		T192	1		T270	1
all_values[9]	auto[1]	auto[1]	156	1		T91	4		T92	4		T93	5
all_values[10]	auto[0]	auto[0]	118319	1		T1	3		T2	5		T3	4
all_values[10]	auto[0]	auto[1]	127	1		T92	1		T93	4		T190	3
all_values[10]	auto[1]	auto[0]	12	1		T93	1		T191	1		T192	1
all_values[10]	auto[1]	auto[1]	158	1		T91	3		T92	3		T93	1
all_values[11]	auto[0]	auto[0]	118228	1		T1	3		T2	5		T3	4
all_values[11]	auto[0]	auto[1]	141	1		T91	3		T93	3		T190	5
all_values[11]	auto[1]	auto[0]	120	1		T49	2		T60	2		T61	2
all_values[11]	auto[1]	auto[1]	127	1		T91	2		T92	5		T93	5
all_values[12]	auto[0]	auto[0]	118331	1		T1	3		T2	5		T3	4
all_values[12]	auto[0]	auto[1]	133	1		T93	5		T191	4		T270	2
all_values[12]	auto[1]	auto[0]	32	1		T91	1		T92	4		T276	2
all_values[12]	auto[1]	auto[1]	120	1		T91	3		T93	2		T190	5
all_values[13]	auto[0]	auto[0]	118327	1		T1	3		T2	5		T3	4
all_values[13]	auto[0]	auto[1]	135	1		T91	2		T92	4		T93	5
all_values[13]	auto[1]	auto[0]	37	1		T190	4		T271	1		T272	1
all_values[13]	auto[1]	auto[1]	117	1		T91	3		T92	1		T93	3
all_values[14]	auto[0]	auto[0]	118333	1		T1	3		T2	5		T3	4
all_values[14]	auto[0]	auto[1]	139	1		T91	2		T92	5		T93	6
all_values[14]	auto[1]	auto[0]	23	1		T191	1		T192	1		T271	1
all_values[14]	auto[1]	auto[1]	121	1		T91	3		T93	1		T190	3
all_values[15]	auto[0]	auto[0]	118325	1		T1	3		T2	5		T3	4
all_values[15]	auto[0]	auto[1]	144	1		T91	4		T92	4		T93	3
all_values[15]	auto[1]	auto[0]	23	1		T91	1		T93	1		T192	8
all_values[15]	auto[1]	auto[1]	124	1		T93	4		T190	5		T191	1
all_values[16]	auto[0]	auto[0]	118336	1		T1	3		T2	5		T3	4
all_values[16]	auto[0]	auto[1]	147	1		T91	4		T92	1		T93	3
all_values[16]	auto[1]	auto[0]	23	1		T93	1		T190	1		T271	1
all_values[16]	auto[1]	auto[1]	110	1		T91	1		T92	3		T93	2
all_values[17]	auto[0]	auto[0]	118328	1		T1	3		T2	5		T3	4
all_values[17]	auto[0]	auto[1]	134	1		T91	4		T92	5		T93	6
all_values[17]	auto[1]	auto[0]	31	1		T192	1		T270	2		T271	1
all_values[17]	auto[1]	auto[1]	123	1		T91	1		T93	2		T190	5