Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	118616	1		T1	3		T2	5		T3	4
all_pins[1]	118616	1		T1	3		T2	5		T3	4
all_pins[2]	118616	1		T1	3		T2	5		T3	4
all_pins[3]	118616	1		T1	3		T2	5		T3	4
all_pins[4]	118616	1		T1	3		T2	5		T3	4
all_pins[5]	118616	1		T1	3		T2	5		T3	4
all_pins[6]	118616	1		T1	3		T2	5		T3	4
all_pins[7]	118616	1		T1	3		T2	5		T3	4
all_pins[8]	118616	1		T1	3		T2	5		T3	4
all_pins[9]	118616	1		T1	3		T2	5		T3	4
all_pins[10]	118616	1		T1	3		T2	5		T3	4
all_pins[11]	118616	1		T1	3		T2	5		T3	4
all_pins[12]	118616	1		T1	3		T2	5		T3	4
all_pins[13]	118616	1		T1	3		T2	5		T3	4
all_pins[14]	118616	1		T1	3		T2	5		T3	4
all_pins[15]	118616	1		T1	3		T2	5		T3	4
all_pins[16]	118616	1		T1	3		T2	5		T3	4
all_pins[17]	118616	1		T1	3		T2	5		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2132521	1		T1	54		T2	90		T3	71
values[0x1]	2567	1		T3	1		T7	1		T48	1
transitions[0x0=>0x1]	2273	1		T3	1		T7	1		T48	1
transitions[0x1=>0x0]	2286	1		T3	1		T7	1		T48	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	118466	1		T1	3		T2	5		T3	4
all_pins[0]	values[0x1]	150	1		T48	1		T50	1		T201	1
all_pins[0]	transitions[0x0=>0x1]	141	1		T48	1		T50	1		T201	1
all_pins[0]	transitions[0x1=>0x0]	1278	1		T3	1		T7	1		T34	24
all_pins[1]	values[0x0]	117329	1		T1	3		T2	5		T3	3
all_pins[1]	values[0x1]	1287	1		T3	1		T7	1		T34	24
all_pins[1]	transitions[0x0=>0x1]	1270	1		T3	1		T7	1		T34	24
all_pins[1]	transitions[0x1=>0x0]	102	1		T44	1		T45	1		T46	1
all_pins[2]	values[0x0]	118497	1		T1	3		T2	5		T3	4
all_pins[2]	values[0x1]	119	1		T44	1		T45	1		T46	1
all_pins[2]	transitions[0x0=>0x1]	105	1		T44	1		T45	1		T46	1
all_pins[2]	transitions[0x1=>0x0]	61	1		T92	1		T93	4		T191	2
all_pins[3]	values[0x0]	118541	1		T1	3		T2	5		T3	4
all_pins[3]	values[0x1]	75	1		T92	1		T93	5		T191	2
all_pins[3]	transitions[0x0=>0x1]	57	1		T92	1		T93	5		T191	2
all_pins[3]	transitions[0x1=>0x0]	45	1		T91	1		T191	1		T192	1
all_pins[4]	values[0x0]	118553	1		T1	3		T2	5		T3	4
all_pins[4]	values[0x1]	63	1		T91	1		T191	1		T192	1
all_pins[4]	transitions[0x0=>0x1]	42	1		T91	1		T192	1		T270	1
all_pins[4]	transitions[0x1=>0x0]	47	1		T92	1		T191	1		T192	1
all_pins[5]	values[0x0]	118548	1		T1	3		T2	5		T3	4
all_pins[5]	values[0x1]	68	1		T92	1		T191	2		T192	1
all_pins[5]	transitions[0x0=>0x1]	49	1		T92	1		T191	1		T270	2
all_pins[5]	transitions[0x1=>0x0]	57	1		T91	2		T93	3		T190	3
all_pins[6]	values[0x0]	118540	1		T1	3		T2	5		T3	4
all_pins[6]	values[0x1]	76	1		T91	2		T93	3		T190	3
all_pins[6]	transitions[0x0=>0x1]	61	1		T91	2		T93	3		T190	2
all_pins[6]	transitions[0x1=>0x0]	38	1		T93	1		T191	1		T272	2
all_pins[7]	values[0x0]	118563	1		T1	3		T2	5		T3	4
all_pins[7]	values[0x1]	53	1		T93	1		T190	1		T191	1
all_pins[7]	transitions[0x0=>0x1]	40	1		T191	1		T192	1		T272	2
all_pins[7]	transitions[0x1=>0x0]	39	1		T91	2		T190	1		T270	3
all_pins[8]	values[0x0]	118564	1		T1	3		T2	5		T3	4
all_pins[8]	values[0x1]	52	1		T91	2		T93	1		T190	2
all_pins[8]	transitions[0x0=>0x1]	38	1		T91	1		T93	1		T190	1
all_pins[8]	transitions[0x1=>0x0]	63	1		T91	2		T92	3		T93	4
all_pins[9]	values[0x0]	118539	1		T1	3		T2	5		T3	4
all_pins[9]	values[0x1]	77	1		T91	3		T92	3		T93	4
all_pins[9]	transitions[0x0=>0x1]	45	1		T91	1		T92	3		T93	4
all_pins[9]	transitions[0x1=>0x0]	46	1		T93	1		T270	3		T271	3
all_pins[10]	values[0x0]	118538	1		T1	3		T2	5		T3	4
all_pins[10]	values[0x1]	78	1		T91	2		T93	1		T270	3
all_pins[10]	transitions[0x0=>0x1]	57	1		T91	2		T93	1		T270	2
all_pins[10]	transitions[0x1=>0x0]	92	1		T49	1		T60	1		T61	1
all_pins[11]	values[0x0]	118503	1		T1	3		T2	5		T3	4
all_pins[11]	values[0x1]	113	1		T49	1		T60	1		T61	1
all_pins[11]	transitions[0x0=>0x1]	100	1		T49	1		T60	1		T61	1
all_pins[11]	transitions[0x1=>0x0]	55	1		T91	2		T190	2		T192	2
all_pins[12]	values[0x0]	118548	1		T1	3		T2	5		T3	4
all_pins[12]	values[0x1]	68	1		T91	2		T190	2		T192	2
all_pins[12]	transitions[0x0=>0x1]	49	1		T190	2		T192	2		T270	2
all_pins[12]	transitions[0x1=>0x0]	50	1		T93	3		T192	1		T270	3
all_pins[13]	values[0x0]	118547	1		T1	3		T2	5		T3	4
all_pins[13]	values[0x1]	69	1		T91	2		T93	3		T192	1
all_pins[13]	transitions[0x0=>0x1]	51	1		T93	3		T192	1		T270	1
all_pins[13]	transitions[0x1=>0x0]	38	1		T270	1		T271	1		T272	2
all_pins[14]	values[0x0]	118560	1		T1	3		T2	5		T3	4
all_pins[14]	values[0x1]	56	1		T91	2		T270	3		T271	1
all_pins[14]	transitions[0x0=>0x1]	48	1		T91	2		T270	2		T271	1
all_pins[14]	transitions[0x1=>0x0]	51	1		T93	3		T190	4		T270	1
all_pins[15]	values[0x0]	118557	1		T1	3		T2	5		T3	4
all_pins[15]	values[0x1]	59	1		T93	3		T190	4		T270	2
all_pins[15]	transitions[0x0=>0x1]	50	1		T93	3		T190	3		T270	1
all_pins[15]	transitions[0x1=>0x0]	47	1		T91	1		T92	2		T93	2
all_pins[16]	values[0x0]	118560	1		T1	3		T2	5		T3	4
all_pins[16]	values[0x1]	56	1		T91	1		T92	2		T93	2
all_pins[16]	transitions[0x0=>0x1]	43	1		T92	2		T93	2		T191	1
all_pins[16]	transitions[0x1=>0x0]	35	1		T93	1		T190	2		T191	1
all_pins[17]	values[0x0]	118568	1		T1	3		T2	5		T3	4
all_pins[17]	values[0x1]	48	1		T91	1		T93	1		T190	3
all_pins[17]	transitions[0x0=>0x1]	27	1		T93	1		T190	2		T191	1
all_pins[17]	transitions[0x1=>0x0]	142	1		T48	1		T50	1		T201	1