Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	266	1		T91	4		T92	4		T93	7
all_values[1]	266	1		T91	4		T92	4		T93	7
all_values[2]	266	1		T91	4		T92	4		T93	7
all_values[3]	266	1		T91	4		T92	4		T93	7
all_values[4]	266	1		T91	4		T92	4		T93	7
all_values[5]	266	1		T91	4		T92	4		T93	7
all_values[6]	266	1		T91	4		T92	4		T93	7
all_values[7]	266	1		T91	4		T92	4		T93	7
all_values[8]	266	1		T91	4		T92	4		T93	7
all_values[9]	266	1		T91	4		T92	4		T93	7
all_values[10]	266	1		T91	4		T92	4		T93	7
all_values[11]	266	1		T91	4		T92	4		T93	7
all_values[12]	266	1		T91	4		T92	4		T93	7
all_values[13]	266	1		T91	4		T92	4		T93	7
all_values[14]	266	1		T91	4		T92	4		T93	7
all_values[15]	266	1		T91	4		T92	4		T93	7
all_values[16]	266	1		T91	4		T92	4		T93	7
all_values[17]	266	1		T91	4		T92	4		T93	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2614	1		T91	41		T92	49		T93	79
auto[1]	2174	1		T91	31		T92	23		T93	47

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	883	1		T91	13		T92	16		T93	22
auto[1]	3905	1		T91	59		T92	56		T93	104

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2862	1		T91	44		T92	42		T93	79
auto[1]	1926	1		T91	28		T92	30		T93	47

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	33	1		T92	1		T93	3		T190	2
all_values[0]	auto[0]	auto[0]	auto[1]	59	1		T91	1		T192	3		T270	2
all_values[0]	auto[0]	auto[1]	auto[0]	27	1		T93	1		T190	2		T192	1
all_values[0]	auto[0]	auto[1]	auto[1]	50	1		T91	1		T92	1		T93	2
all_values[0]	auto[1]	auto[0]	auto[1]	48	1		T92	1		T191	1		T192	2
all_values[0]	auto[1]	auto[1]	auto[1]	49	1		T91	2		T92	1		T93	1
all_values[1]	auto[0]	auto[0]	auto[0]	21	1		T190	1		T191	1		T192	2
all_values[1]	auto[0]	auto[0]	auto[1]	55	1		T91	2		T92	1		T93	2
all_values[1]	auto[0]	auto[1]	auto[0]	25	1		T190	1		T272	1		T276	2
all_values[1]	auto[0]	auto[1]	auto[1]	44	1		T93	2		T190	1		T191	1
all_values[1]	auto[1]	auto[0]	auto[1]	65	1		T91	1		T92	3		T93	2
all_values[1]	auto[1]	auto[1]	auto[1]	56	1		T91	1		T93	1		T190	1
all_values[2]	auto[0]	auto[0]	auto[0]	26	1		T91	1		T191	2		T272	1
all_values[2]	auto[0]	auto[0]	auto[1]	55	1		T92	2		T93	2		T190	1
all_values[2]	auto[0]	auto[1]	auto[0]	9	1		T191	2		T270	2		T277	2
all_values[2]	auto[0]	auto[1]	auto[1]	60	1		T91	2		T93	2		T192	3
all_values[2]	auto[1]	auto[0]	auto[1]	67	1		T91	1		T92	2		T93	3
all_values[2]	auto[1]	auto[1]	auto[1]	49	1		T192	1		T270	1		T271	2
all_values[3]	auto[0]	auto[0]	auto[0]	31	1		T91	2		T190	1		T191	1
all_values[3]	auto[0]	auto[0]	auto[1]	48	1		T91	1		T190	1		T192	1
all_values[3]	auto[0]	auto[1]	auto[0]	16	1		T272	1		T273	1		T278	3
all_values[3]	auto[0]	auto[1]	auto[1]	56	1		T92	1		T93	3		T191	1
all_values[3]	auto[1]	auto[0]	auto[1]	59	1		T91	1		T92	2		T93	2
all_values[3]	auto[1]	auto[1]	auto[1]	56	1		T92	1		T93	2		T270	3
all_values[4]	auto[0]	auto[0]	auto[0]	29	1		T92	1		T93	1		T190	3
all_values[4]	auto[0]	auto[0]	auto[1]	54	1		T91	1		T92	1		T93	2
all_values[4]	auto[0]	auto[1]	auto[0]	17	1		T93	1		T190	1		T275	1
all_values[4]	auto[0]	auto[1]	auto[1]	63	1		T91	1		T93	1		T192	1
all_values[4]	auto[1]	auto[0]	auto[1]	56	1		T91	1		T92	2		T191	2
all_values[4]	auto[1]	auto[1]	auto[1]	47	1		T91	1		T93	2		T191	1
all_values[5]	auto[0]	auto[0]	auto[0]	31	1		T92	1		T93	4		T190	1
all_values[5]	auto[0]	auto[0]	auto[1]	59	1		T91	3		T92	2		T93	1
all_values[5]	auto[0]	auto[1]	auto[0]	14	1		T276	1		T275	1		T277	1
all_values[5]	auto[0]	auto[1]	auto[1]	54	1		T191	2		T192	2		T270	2
all_values[5]	auto[1]	auto[0]	auto[1]	57	1		T91	1		T93	2		T190	1
all_values[5]	auto[1]	auto[1]	auto[1]	51	1		T92	1		T192	1		T270	2
all_values[6]	auto[0]	auto[0]	auto[0]	29	1		T190	1		T271	1		T276	1
all_values[6]	auto[0]	auto[0]	auto[1]	49	1		T92	1		T93	1		T192	1
all_values[6]	auto[0]	auto[1]	auto[0]	19	1		T91	2		T274	1		T275	2
all_values[6]	auto[0]	auto[1]	auto[1]	62	1		T91	1		T92	1		T93	1
all_values[6]	auto[1]	auto[0]	auto[1]	54	1		T91	1		T92	1		T93	2
all_values[6]	auto[1]	auto[1]	auto[1]	53	1		T92	1		T93	3		T190	1
all_values[7]	auto[0]	auto[0]	auto[0]	44	1		T92	1		T93	1		T191	1
all_values[7]	auto[0]	auto[0]	auto[1]	48	1		T91	1		T92	2		T93	2
all_values[7]	auto[0]	auto[1]	auto[0]	17	1		T91	2		T93	1		T191	1
all_values[7]	auto[0]	auto[1]	auto[1]	59	1		T191	1		T192	3		T271	1
all_values[7]	auto[1]	auto[0]	auto[1]	45	1		T92	1		T93	2		T190	2
all_values[7]	auto[1]	auto[1]	auto[1]	53	1		T91	1		T93	1		T190	1
all_values[8]	auto[0]	auto[0]	auto[0]	31	1		T92	1		T191	1		T273	1
all_values[8]	auto[0]	auto[0]	auto[1]	57	1		T91	1		T93	3		T191	2
all_values[8]	auto[0]	auto[1]	auto[0]	24	1		T92	3		T272	3		T273	3
all_values[8]	auto[0]	auto[1]	auto[1]	53	1		T91	1		T93	1		T190	2
all_values[8]	auto[1]	auto[0]	auto[1]	53	1		T93	2		T190	1		T191	1
all_values[8]	auto[1]	auto[1]	auto[1]	48	1		T91	2		T93	1		T190	1
all_values[9]	auto[0]	auto[0]	auto[0]	29	1		T91	1		T92	1		T93	1
all_values[9]	auto[0]	auto[0]	auto[1]	51	1		T93	1		T190	1		T191	2
all_values[9]	auto[0]	auto[1]	auto[0]	12	1		T192	2		T270	2		T274	1
all_values[9]	auto[0]	auto[1]	auto[1]	67	1		T91	2		T92	2		T93	2
all_values[9]	auto[1]	auto[0]	auto[1]	51	1		T91	1		T93	1		T190	3
all_values[9]	auto[1]	auto[1]	auto[1]	56	1		T92	1		T93	2		T191	1
all_values[10]	auto[0]	auto[0]	auto[0]	23	1		T91	2		T92	1		T93	3
all_values[10]	auto[0]	auto[0]	auto[1]	48	1		T93	3		T190	1		T192	1
all_values[10]	auto[0]	auto[1]	auto[0]	8	1		T191	1		T192	1		T275	1
all_values[10]	auto[0]	auto[1]	auto[1]	65	1		T91	1		T92	2		T191	1
all_values[10]	auto[1]	auto[0]	auto[1]	70	1		T91	1		T92	1		T93	1
all_values[10]	auto[1]	auto[1]	auto[1]	52	1		T192	1		T270	4		T271	1
all_values[11]	auto[0]	auto[0]	auto[0]	32	1		T273	1		T274	1		T277	2
all_values[11]	auto[0]	auto[0]	auto[1]	53	1		T91	1		T93	2		T190	2
all_values[11]	auto[0]	auto[1]	auto[0]	13	1		T192	1		T273	1		T278	1
all_values[11]	auto[0]	auto[1]	auto[1]	65	1		T92	3		T93	4		T191	3
all_values[11]	auto[1]	auto[0]	auto[1]	57	1		T92	1		T93	1		T190	2
all_values[11]	auto[1]	auto[1]	auto[1]	46	1		T91	3		T192	1		T270	2
all_values[12]	auto[0]	auto[0]	auto[0]	34	1		T91	2		T92	2		T93	1
all_values[12]	auto[0]	auto[0]	auto[1]	58	1		T93	2		T191	1		T270	1
all_values[12]	auto[0]	auto[1]	auto[0]	24	1		T92	2		T276	2		T275	1
all_values[12]	auto[0]	auto[1]	auto[1]	47	1		T91	1		T93	1		T190	3
all_values[12]	auto[1]	auto[0]	auto[1]	61	1		T93	2		T190	1		T191	2
all_values[12]	auto[1]	auto[1]	auto[1]	42	1		T91	1		T93	1		T192	1
all_values[13]	auto[0]	auto[0]	auto[0]	32	1		T190	1		T191	2		T270	3
all_values[13]	auto[0]	auto[0]	auto[1]	52	1		T91	1		T92	1		T93	4
all_values[13]	auto[0]	auto[1]	auto[0]	26	1		T190	3		T272	1		T276	1
all_values[13]	auto[0]	auto[1]	auto[1]	51	1		T91	1		T92	1		T93	2
all_values[13]	auto[1]	auto[0]	auto[1]	68	1		T91	2		T92	2		T93	1
all_values[13]	auto[1]	auto[1]	auto[1]	37	1		T192	1		T270	1		T272	3
all_values[14]	auto[0]	auto[0]	auto[0]	36	1		T93	1		T191	3		T271	2
all_values[14]	auto[0]	auto[0]	auto[1]	53	1		T91	1		T92	1		T93	3
all_values[14]	auto[0]	auto[1]	auto[0]	16	1		T191	1		T192	1		T271	2
all_values[14]	auto[0]	auto[1]	auto[1]	60	1		T91	1		T93	1		T190	2
all_values[14]	auto[1]	auto[0]	auto[1]	64	1		T91	2		T92	3		T93	2
all_values[14]	auto[1]	auto[1]	auto[1]	37	1		T192	1		T270	3		T272	1
all_values[15]	auto[0]	auto[0]	auto[0]	29	1		T92	1		T93	1		T191	1
all_values[15]	auto[0]	auto[0]	auto[1]	67	1		T91	2		T92	1		T93	1
all_values[15]	auto[0]	auto[1]	auto[0]	16	1		T91	1		T192	7		T279	1
all_values[15]	auto[0]	auto[1]	auto[1]	42	1		T93	2		T190	1		T191	1
all_values[15]	auto[1]	auto[0]	auto[1]	73	1		T92	2		T93	3		T190	1
all_values[15]	auto[1]	auto[1]	auto[1]	39	1		T91	1		T190	2		T270	2
all_values[16]	auto[0]	auto[0]	auto[0]	38	1		T92	1		T93	3		T190	1
all_values[16]	auto[0]	auto[0]	auto[1]	67	1		T91	2		T93	1		T191	1
all_values[16]	auto[0]	auto[1]	auto[0]	17	1		T272	3		T276	3		T277	1
all_values[16]	auto[0]	auto[1]	auto[1]	43	1		T92	2		T190	2		T270	3
all_values[16]	auto[1]	auto[0]	auto[1]	60	1		T91	1		T92	1		T191	2
all_values[16]	auto[1]	auto[1]	auto[1]	41	1		T91	1		T93	3		T190	1
all_values[17]	auto[0]	auto[0]	auto[0]	33	1		T270	2		T271	1		T273	1
all_values[17]	auto[0]	auto[0]	auto[1]	50	1		T91	1		T92	1		T93	2
all_values[17]	auto[0]	auto[1]	auto[0]	22	1		T192	1		T270	1		T272	2
all_values[17]	auto[0]	auto[1]	auto[1]	55	1		T91	1		T93	1		T190	1
all_values[17]	auto[1]	auto[0]	auto[1]	62	1		T91	2		T92	3		T93	2
all_values[17]	auto[1]	auto[1]	auto[1]	44	1		T93	2		T190	2		T192	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal