Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.40 97.48 92.21 97.86 68.75 95.77 98.17 96.58


Total test records in report: 2135
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T218 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1255033489 Jun 05 05:18:52 PM PDT 24 Jun 05 05:18:55 PM PDT 24 179817120 ps
T213 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.524563356 Jun 05 05:18:46 PM PDT 24 Jun 05 05:18:49 PM PDT 24 186253460 ps
T2040 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1148969623 Jun 05 05:19:11 PM PDT 24 Jun 05 05:19:15 PM PDT 24 152936603 ps
T2041 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3826243689 Jun 05 05:19:09 PM PDT 24 Jun 05 05:19:12 PM PDT 24 214499397 ps
T273 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3388113716 Jun 05 05:19:09 PM PDT 24 Jun 05 05:19:11 PM PDT 24 56594124 ps
T274 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1057085061 Jun 05 05:19:17 PM PDT 24 Jun 05 05:19:18 PM PDT 24 42004360 ps
T275 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3219199678 Jun 05 05:18:26 PM PDT 24 Jun 05 05:18:27 PM PDT 24 46719314 ps
T2042 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2182534577 Jun 05 05:18:28 PM PDT 24 Jun 05 05:18:30 PM PDT 24 76857464 ps
T264 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1090428950 Jun 05 05:18:45 PM PDT 24 Jun 05 05:18:47 PM PDT 24 66398728 ps
T277 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1885162745 Jun 05 05:18:36 PM PDT 24 Jun 05 05:18:37 PM PDT 24 38764551 ps
T2043 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.307019955 Jun 05 05:18:53 PM PDT 24 Jun 05 05:18:55 PM PDT 24 43092676 ps
T2044 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2989019728 Jun 05 05:18:40 PM PDT 24 Jun 05 05:18:43 PM PDT 24 49441032 ps
T278 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2862284386 Jun 05 05:19:09 PM PDT 24 Jun 05 05:19:10 PM PDT 24 72265148 ps
T279 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3908634039 Jun 05 05:19:13 PM PDT 24 Jun 05 05:19:14 PM PDT 24 32971003 ps
T243 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.4094771682 Jun 05 05:18:33 PM PDT 24 Jun 05 05:18:34 PM PDT 24 84506392 ps
T265 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.681948742 Jun 05 05:18:22 PM PDT 24 Jun 05 05:18:24 PM PDT 24 152466810 ps
T240 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2755706109 Jun 05 05:18:29 PM PDT 24 Jun 05 05:18:33 PM PDT 24 301839621 ps
T266 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2930740135 Jun 05 05:18:29 PM PDT 24 Jun 05 05:18:31 PM PDT 24 117736142 ps
T241 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1071203653 Jun 05 05:18:22 PM PDT 24 Jun 05 05:18:26 PM PDT 24 287986502 ps
T267 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.770858703 Jun 05 05:18:29 PM PDT 24 Jun 05 05:18:31 PM PDT 24 110792432 ps
T2045 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2089479309 Jun 05 05:18:51 PM PDT 24 Jun 05 05:18:52 PM PDT 24 92241498 ps
T2046 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1960476284 Jun 05 05:18:28 PM PDT 24 Jun 05 05:18:31 PM PDT 24 82434719 ps
T217 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2322418936 Jun 05 05:18:43 PM PDT 24 Jun 05 05:18:47 PM PDT 24 105776690 ps
T2047 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2166466057 Jun 05 05:18:39 PM PDT 24 Jun 05 05:18:41 PM PDT 24 73694921 ps
T283 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3917998140 Jun 05 05:18:54 PM PDT 24 Jun 05 05:18:57 PM PDT 24 395423081 ps
T2048 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1268559843 Jun 05 05:19:08 PM PDT 24 Jun 05 05:19:09 PM PDT 24 62978532 ps
T2049 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2612019946 Jun 05 05:19:10 PM PDT 24 Jun 05 05:19:11 PM PDT 24 68754348 ps
T289 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.4028661913 Jun 05 05:19:12 PM PDT 24 Jun 05 05:19:19 PM PDT 24 1483611975 ps
T2050 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2653545693 Jun 05 05:18:43 PM PDT 24 Jun 05 05:18:46 PM PDT 24 205380762 ps
T212 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.33538148 Jun 05 05:18:53 PM PDT 24 Jun 05 05:18:56 PM PDT 24 238687329 ps
T215 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2472032949 Jun 05 05:18:45 PM PDT 24 Jun 05 05:18:49 PM PDT 24 153920461 ps
T2051 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.190581767 Jun 05 05:19:18 PM PDT 24 Jun 05 05:19:21 PM PDT 24 87247670 ps
T2052 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1668144731 Jun 05 05:19:18 PM PDT 24 Jun 05 05:19:21 PM PDT 24 58498253 ps
T268 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2800306999 Jun 05 05:19:10 PM PDT 24 Jun 05 05:19:12 PM PDT 24 93499115 ps
T2053 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.4080092692 Jun 05 05:18:39 PM PDT 24 Jun 05 05:18:41 PM PDT 24 101921722 ps
T2054 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3137788529 Jun 05 05:18:21 PM PDT 24 Jun 05 05:18:24 PM PDT 24 134176362 ps
T2055 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1026968396 Jun 05 05:19:10 PM PDT 24 Jun 05 05:19:12 PM PDT 24 71961884 ps
T2056 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1700685946 Jun 05 05:19:09 PM PDT 24 Jun 05 05:19:10 PM PDT 24 36295406 ps
T2057 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.4191000677 Jun 05 05:18:24 PM PDT 24 Jun 05 05:18:26 PM PDT 24 37248819 ps
T2058 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2037653497 Jun 05 05:18:52 PM PDT 24 Jun 05 05:18:55 PM PDT 24 217271644 ps
T219 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3480027096 Jun 05 05:18:45 PM PDT 24 Jun 05 05:18:48 PM PDT 24 60429939 ps
T242 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1345947682 Jun 05 05:18:29 PM PDT 24 Jun 05 05:18:32 PM PDT 24 124287675 ps
T2059 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1819041011 Jun 05 05:19:18 PM PDT 24 Jun 05 05:19:20 PM PDT 24 42462411 ps
T2060 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3203934737 Jun 05 05:18:41 PM PDT 24 Jun 05 05:18:44 PM PDT 24 169846303 ps
T269 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1401578240 Jun 05 05:19:00 PM PDT 24 Jun 05 05:19:01 PM PDT 24 189849394 ps
T2061 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.222034377 Jun 05 05:18:29 PM PDT 24 Jun 05 05:18:33 PM PDT 24 732031438 ps
T249 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2265127734 Jun 05 05:18:52 PM PDT 24 Jun 05 05:18:54 PM PDT 24 50580266 ps
T2062 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1511075336 Jun 05 05:19:07 PM PDT 24 Jun 05 05:19:09 PM PDT 24 179511781 ps
T2063 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2262380100 Jun 05 05:19:10 PM PDT 24 Jun 05 05:19:14 PM PDT 24 265441372 ps
T2064 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3912436874 Jun 05 05:19:17 PM PDT 24 Jun 05 05:19:19 PM PDT 24 40910096 ps
T2065 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2985542700 Jun 05 05:18:30 PM PDT 24 Jun 05 05:18:32 PM PDT 24 102493543 ps
T281 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2932368856 Jun 05 05:18:47 PM PDT 24 Jun 05 05:18:53 PM PDT 24 781486194 ps
T2066 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.4235155044 Jun 05 05:19:17 PM PDT 24 Jun 05 05:19:18 PM PDT 24 35594844 ps
T2067 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2408068373 Jun 05 05:19:10 PM PDT 24 Jun 05 05:19:13 PM PDT 24 74399643 ps
T2068 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.4113044957 Jun 05 05:18:39 PM PDT 24 Jun 05 05:18:42 PM PDT 24 75711736 ps
T2069 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.701809668 Jun 05 05:19:17 PM PDT 24 Jun 05 05:19:19 PM PDT 24 90841805 ps
T2070 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.4123449883 Jun 05 05:18:29 PM PDT 24 Jun 05 05:18:31 PM PDT 24 107244403 ps
T2071 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.4095395853 Jun 05 05:18:30 PM PDT 24 Jun 05 05:18:32 PM PDT 24 64076610 ps
T2072 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1374839082 Jun 05 05:19:17 PM PDT 24 Jun 05 05:19:20 PM PDT 24 57670643 ps
T287 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3106286119 Jun 05 05:19:11 PM PDT 24 Jun 05 05:19:17 PM PDT 24 756928662 ps
T2073 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.606725176 Jun 05 05:19:09 PM PDT 24 Jun 05 05:19:10 PM PDT 24 49207366 ps
T2074 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2599287383 Jun 05 05:19:00 PM PDT 24 Jun 05 05:19:01 PM PDT 24 44182867 ps
T2075 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3799547100 Jun 05 05:19:10 PM PDT 24 Jun 05 05:19:12 PM PDT 24 44356086 ps
T244 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.477515909 Jun 05 05:18:24 PM PDT 24 Jun 05 05:18:26 PM PDT 24 81548896 ps
T2076 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.875499504 Jun 05 05:18:39 PM PDT 24 Jun 05 05:18:41 PM PDT 24 67648838 ps
T2077 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1277010737 Jun 05 05:18:51 PM PDT 24 Jun 05 05:18:53 PM PDT 24 124042640 ps
T250 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.958833650 Jun 05 05:18:49 PM PDT 24 Jun 05 05:18:50 PM PDT 24 131330211 ps
T245 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4254941997 Jun 05 05:18:29 PM PDT 24 Jun 05 05:18:32 PM PDT 24 202157565 ps
T2078 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2575197997 Jun 05 05:18:39 PM PDT 24 Jun 05 05:18:43 PM PDT 24 199804035 ps
T2079 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1327745995 Jun 05 05:18:24 PM PDT 24 Jun 05 05:18:28 PM PDT 24 769105034 ps
T2080 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2874649410 Jun 05 05:19:11 PM PDT 24 Jun 05 05:19:14 PM PDT 24 185151574 ps
T2081 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.4136691584 Jun 05 05:19:13 PM PDT 24 Jun 05 05:19:15 PM PDT 24 91214187 ps
T2082 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.490688267 Jun 05 05:19:08 PM PDT 24 Jun 05 05:19:10 PM PDT 24 42249102 ps
T2083 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.695189080 Jun 05 05:18:43 PM PDT 24 Jun 05 05:18:45 PM PDT 24 100194364 ps
T2084 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1406084323 Jun 05 05:19:04 PM PDT 24 Jun 05 05:19:07 PM PDT 24 72936089 ps
T246 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2197931754 Jun 05 05:18:31 PM PDT 24 Jun 05 05:18:34 PM PDT 24 237687997 ps
T2085 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2554014014 Jun 05 05:18:29 PM PDT 24 Jun 05 05:18:30 PM PDT 24 44289179 ps
T2086 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3459584203 Jun 05 05:19:01 PM PDT 24 Jun 05 05:19:03 PM PDT 24 114030522 ps
T2087 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1486316598 Jun 05 05:18:23 PM PDT 24 Jun 05 05:18:28 PM PDT 24 861056822 ps
T288 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1780838541 Jun 05 05:18:52 PM PDT 24 Jun 05 05:18:55 PM PDT 24 642739539 ps
T2088 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2122149367 Jun 05 05:19:14 PM PDT 24 Jun 05 05:19:16 PM PDT 24 34802095 ps
T2089 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3399282950 Jun 05 05:19:08 PM PDT 24 Jun 05 05:19:09 PM PDT 24 31570536 ps
T2090 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.831923524 Jun 05 05:19:17 PM PDT 24 Jun 05 05:19:18 PM PDT 24 69408028 ps
T2091 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2678902282 Jun 05 05:19:10 PM PDT 24 Jun 05 05:19:12 PM PDT 24 50563192 ps
T2092 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1465835849 Jun 05 05:18:43 PM PDT 24 Jun 05 05:18:46 PM PDT 24 175881102 ps
T2093 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1997602365 Jun 05 05:18:51 PM PDT 24 Jun 05 05:18:53 PM PDT 24 62450579 ps
T2094 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3537546161 Jun 05 05:18:28 PM PDT 24 Jun 05 05:18:31 PM PDT 24 274341568 ps
T284 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2274236264 Jun 05 05:18:59 PM PDT 24 Jun 05 05:19:02 PM PDT 24 324702963 ps
T2095 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1328712149 Jun 05 05:18:25 PM PDT 24 Jun 05 05:18:27 PM PDT 24 147493696 ps
T2096 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.353454508 Jun 05 05:19:08 PM PDT 24 Jun 05 05:19:10 PM PDT 24 111419039 ps
T2097 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.387772451 Jun 05 05:18:23 PM PDT 24 Jun 05 05:18:27 PM PDT 24 419688057 ps
T285 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1734899664 Jun 05 05:18:37 PM PDT 24 Jun 05 05:18:42 PM PDT 24 644604518 ps
T2098 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2064194205 Jun 05 05:18:28 PM PDT 24 Jun 05 05:18:30 PM PDT 24 83603415 ps
T2099 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3019329720 Jun 05 05:18:37 PM PDT 24 Jun 05 05:18:39 PM PDT 24 148766799 ps
T2100 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1998928109 Jun 05 05:18:59 PM PDT 24 Jun 05 05:19:03 PM PDT 24 107526310 ps
T2101 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2984104794 Jun 05 05:19:01 PM PDT 24 Jun 05 05:19:04 PM PDT 24 169543153 ps
T2102 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.183829951 Jun 05 05:18:26 PM PDT 24 Jun 05 05:18:29 PM PDT 24 222110778 ps
T2103 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3055535019 Jun 05 05:18:31 PM PDT 24 Jun 05 05:18:36 PM PDT 24 343403843 ps
T2104 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.332831189 Jun 05 05:18:39 PM PDT 24 Jun 05 05:18:44 PM PDT 24 1029188876 ps
T282 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.4124827814 Jun 05 05:19:00 PM PDT 24 Jun 05 05:19:06 PM PDT 24 866365661 ps
T2105 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3608492549 Jun 05 05:18:37 PM PDT 24 Jun 05 05:18:39 PM PDT 24 85290554 ps
T2106 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2099546861 Jun 05 05:18:38 PM PDT 24 Jun 05 05:18:40 PM PDT 24 109991901 ps
T2107 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2381534782 Jun 05 05:19:10 PM PDT 24 Jun 05 05:19:16 PM PDT 24 886800760 ps
T2108 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3927244113 Jun 05 05:19:00 PM PDT 24 Jun 05 05:19:01 PM PDT 24 41639915 ps
T2109 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.307502563 Jun 05 05:18:46 PM PDT 24 Jun 05 05:18:48 PM PDT 24 52135351 ps
T2110 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2251352495 Jun 05 05:19:10 PM PDT 24 Jun 05 05:19:11 PM PDT 24 35383536 ps
T2111 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3664838965 Jun 05 05:18:46 PM PDT 24 Jun 05 05:18:51 PM PDT 24 731581623 ps
T2112 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.4077698981 Jun 05 05:18:51 PM PDT 24 Jun 05 05:18:52 PM PDT 24 96688376 ps
T2113 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.4254700691 Jun 05 05:18:29 PM PDT 24 Jun 05 05:18:31 PM PDT 24 57028694 ps
T2114 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.8503015 Jun 05 05:18:46 PM PDT 24 Jun 05 05:18:53 PM PDT 24 1659460063 ps
T2115 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.529530902 Jun 05 05:18:31 PM PDT 24 Jun 05 05:18:34 PM PDT 24 206586481 ps
T2116 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.662033023 Jun 05 05:18:47 PM PDT 24 Jun 05 05:18:49 PM PDT 24 68698335 ps
T2117 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2938742881 Jun 05 05:18:47 PM PDT 24 Jun 05 05:18:54 PM PDT 24 1779562586 ps
T2118 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.4105279154 Jun 05 05:18:53 PM PDT 24 Jun 05 05:18:55 PM PDT 24 126233615 ps
T2119 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1968984902 Jun 05 05:19:09 PM PDT 24 Jun 05 05:19:11 PM PDT 24 52211181 ps
T2120 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.731226014 Jun 05 05:19:02 PM PDT 24 Jun 05 05:19:04 PM PDT 24 215125135 ps
T2121 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3057363750 Jun 05 05:19:11 PM PDT 24 Jun 05 05:19:15 PM PDT 24 94344489 ps
T247 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4020166913 Jun 05 05:18:30 PM PDT 24 Jun 05 05:18:32 PM PDT 24 57007948 ps
T2122 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3458809455 Jun 05 05:18:37 PM PDT 24 Jun 05 05:18:39 PM PDT 24 247267040 ps
T2123 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3013197996 Jun 05 05:18:50 PM PDT 24 Jun 05 05:18:53 PM PDT 24 184856535 ps
T2124 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.689172732 Jun 05 05:18:20 PM PDT 24 Jun 05 05:18:23 PM PDT 24 200700222 ps
T290 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1938754162 Jun 05 05:19:10 PM PDT 24 Jun 05 05:19:17 PM PDT 24 1771152563 ps
T2125 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2217502478 Jun 05 05:19:10 PM PDT 24 Jun 05 05:19:12 PM PDT 24 46926571 ps
T248 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2964285618 Jun 05 05:18:22 PM PDT 24 Jun 05 05:18:24 PM PDT 24 123047799 ps
T2126 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3301748892 Jun 05 05:19:10 PM PDT 24 Jun 05 05:19:12 PM PDT 24 33687716 ps
T2127 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.888934180 Jun 05 05:18:38 PM PDT 24 Jun 05 05:18:41 PM PDT 24 104637316 ps
T2128 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3973273893 Jun 05 05:18:45 PM PDT 24 Jun 05 05:18:48 PM PDT 24 109233579 ps
T2129 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1188733152 Jun 05 05:18:39 PM PDT 24 Jun 05 05:18:42 PM PDT 24 47953779 ps
T2130 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2270494943 Jun 05 05:19:17 PM PDT 24 Jun 05 05:19:18 PM PDT 24 56846873 ps
T286 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3567327795 Jun 05 05:18:40 PM PDT 24 Jun 05 05:18:44 PM PDT 24 407401403 ps
T2131 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1313678092 Jun 05 05:18:29 PM PDT 24 Jun 05 05:18:31 PM PDT 24 347322902 ps
T2132 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.4259502611 Jun 05 05:18:53 PM PDT 24 Jun 05 05:18:54 PM PDT 24 70031457 ps
T2133 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.424578317 Jun 05 05:18:29 PM PDT 24 Jun 05 05:18:31 PM PDT 24 119146616 ps
T2134 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1056981801 Jun 05 05:19:10 PM PDT 24 Jun 05 05:19:14 PM PDT 24 131871140 ps
T2135 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3711493721 Jun 05 05:19:17 PM PDT 24 Jun 05 05:19:19 PM PDT 24 59784583 ps

Test location /workspace/coverage/default/47.usbdev_link_suspend.2009248248
Short name T3
Test name
Test status
Simulation time 13161128203 ps
CPU time 18.32 seconds
Started Jun 05 05:49:30 PM PDT 24
Finished Jun 05 05:49:49 PM PDT 24
Peak memory 205764 kb
Host smart-dd7799c6-1934-4a4e-8b71-5e7c21501386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20092
48248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.2009248248
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.4191128998
Short name T270
Test name
Test status
Simulation time 47775132 ps
CPU time 0.69 seconds
Started Jun 05 05:18:53 PM PDT 24
Finished Jun 05 05:18:54 PM PDT 24
Peak memory 204584 kb
Host smart-1f6e66b0-cea3-460d-a920-69fdd999a041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4191128998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.4191128998
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.3596257330
Short name T34
Test name
Test status
Simulation time 10766333245 ps
CPU time 13.57 seconds
Started Jun 05 05:47:23 PM PDT 24
Finished Jun 05 05:47:37 PM PDT 24
Peak memory 205660 kb
Host smart-b34ee91a-245f-4bfd-b0ae-f1192260f7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35962
57330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.3596257330
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.454715015
Short name T186
Test name
Test status
Simulation time 283300442 ps
CPU time 2.61 seconds
Started Jun 05 05:18:39 PM PDT 24
Finished Jun 05 05:18:44 PM PDT 24
Peak memory 204848 kb
Host smart-45283210-ce75-4cf4-bd36-1d5b6fd2d359
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=454715015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.454715015
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.78381484
Short name T13
Test name
Test status
Simulation time 23411239614 ps
CPU time 26.03 seconds
Started Jun 05 05:45:26 PM PDT 24
Finished Jun 05 05:45:53 PM PDT 24
Peak memory 205740 kb
Host smart-a2eff8d2-0135-4893-9f52-f3c29e5c603c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=78381484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.78381484
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2051170610
Short name T51
Test name
Test status
Simulation time 10120222176 ps
CPU time 13.33 seconds
Started Jun 05 05:47:31 PM PDT 24
Finished Jun 05 05:47:45 PM PDT 24
Peak memory 205712 kb
Host smart-f15b9e01-7401-4712-850d-f66d8b5606e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20511
70610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2051170610
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1885162745
Short name T277
Test name
Test status
Simulation time 38764551 ps
CPU time 0.68 seconds
Started Jun 05 05:18:36 PM PDT 24
Finished Jun 05 05:18:37 PM PDT 24
Peak memory 204548 kb
Host smart-1e9d46e5-f4b7-4b36-984e-ecff75576475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1885162745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1885162745
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.971159127
Short name T1
Test name
Test status
Simulation time 10067811931 ps
CPU time 13.69 seconds
Started Jun 05 05:48:06 PM PDT 24
Finished Jun 05 05:48:21 PM PDT 24
Peak memory 205660 kb
Host smart-b7d008c7-3cde-4901-abf3-f9393efd526b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97115
9127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.971159127
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.773877160
Short name T46
Test name
Test status
Simulation time 10104717524 ps
CPU time 14.25 seconds
Started Jun 05 05:44:08 PM PDT 24
Finished Jun 05 05:44:23 PM PDT 24
Peak memory 205732 kb
Host smart-82cafbd2-45ec-4df8-aef8-04d9f24f316a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77387
7160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.773877160
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.452588376
Short name T33
Test name
Test status
Simulation time 10063764990 ps
CPU time 13.42 seconds
Started Jun 05 05:45:36 PM PDT 24
Finished Jun 05 05:45:50 PM PDT 24
Peak memory 205760 kb
Host smart-33252e40-a0fe-4e0a-9ea6-5e37d0879415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45258
8376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.452588376
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3322809941
Short name T263
Test name
Test status
Simulation time 209153744 ps
CPU time 1.86 seconds
Started Jun 05 05:19:10 PM PDT 24
Finished Jun 05 05:19:14 PM PDT 24
Peak memory 213060 kb
Host smart-f7fcc165-b4f5-4212-b407-01d9ba322132
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322809941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.3322809941
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.2126498848
Short name T89
Test name
Test status
Simulation time 10097465367 ps
CPU time 15.22 seconds
Started Jun 05 05:46:50 PM PDT 24
Finished Jun 05 05:47:06 PM PDT 24
Peak memory 205636 kb
Host smart-a63a4873-cf0f-4296-86bb-1d27eefead5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21264
98848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.2126498848
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.418094571
Short name T460
Test name
Test status
Simulation time 14197268620 ps
CPU time 17.36 seconds
Started Jun 05 05:46:06 PM PDT 24
Finished Jun 05 05:46:24 PM PDT 24
Peak memory 205780 kb
Host smart-8288d9cb-de35-4033-9962-8c74afeb8404
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=418094571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.418094571
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.2425890042
Short name T182
Test name
Test status
Simulation time 975877257 ps
CPU time 1.88 seconds
Started Jun 05 05:44:37 PM PDT 24
Finished Jun 05 05:44:39 PM PDT 24
Peak memory 223068 kb
Host smart-754f7d22-8554-416e-8887-3a1aef2cb3d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2425890042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2425890042
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.2493217188
Short name T26
Test name
Test status
Simulation time 10031465750 ps
CPU time 13.86 seconds
Started Jun 05 05:47:58 PM PDT 24
Finished Jun 05 05:48:13 PM PDT 24
Peak memory 205760 kb
Host smart-e2edab65-9eaf-4eba-abbc-5cfa54405701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24932
17188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.2493217188
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.401907048
Short name T464
Test name
Test status
Simulation time 10056108575 ps
CPU time 13.76 seconds
Started Jun 05 05:46:47 PM PDT 24
Finished Jun 05 05:47:02 PM PDT 24
Peak memory 205948 kb
Host smart-20eb0075-e35a-4c96-9108-341af76fff3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40190
7048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.401907048
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.2989292464
Short name T63
Test name
Test status
Simulation time 11382377591 ps
CPU time 16.7 seconds
Started Jun 05 05:48:23 PM PDT 24
Finished Jun 05 05:48:41 PM PDT 24
Peak memory 205692 kb
Host smart-b2f957cd-5db2-449b-9105-9e00c4276262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29892
92464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.2989292464
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.2582152880
Short name T4
Test name
Test status
Simulation time 24282801821 ps
CPU time 406.45 seconds
Started Jun 05 05:47:16 PM PDT 24
Finished Jun 05 05:54:03 PM PDT 24
Peak memory 205656 kb
Host smart-51259055-1bb5-47f2-a324-ab7a9c00516f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25821
52880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.2582152880
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.1337647504
Short name T55
Test name
Test status
Simulation time 10142319043 ps
CPU time 13.97 seconds
Started Jun 05 05:48:04 PM PDT 24
Finished Jun 05 05:48:18 PM PDT 24
Peak memory 205680 kb
Host smart-66b18ec8-80a5-4a1a-9fad-62d7cc24adad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13376
47504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.1337647504
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3388113716
Short name T273
Test name
Test status
Simulation time 56594124 ps
CPU time 0.68 seconds
Started Jun 05 05:19:09 PM PDT 24
Finished Jun 05 05:19:11 PM PDT 24
Peak memory 204588 kb
Host smart-e7a86c3f-2c17-4ffb-b8ef-0fc71c848660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3388113716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3388113716
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3166893664
Short name T233
Test name
Test status
Simulation time 43668607 ps
CPU time 0.95 seconds
Started Jun 05 05:18:38 PM PDT 24
Finished Jun 05 05:18:41 PM PDT 24
Peak memory 204800 kb
Host smart-9e89ccec-bad3-44d1-83dc-f810a2919ee0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3166893664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3166893664
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.1258109644
Short name T454
Test name
Test status
Simulation time 10190986665 ps
CPU time 14.71 seconds
Started Jun 05 05:45:55 PM PDT 24
Finished Jun 05 05:46:11 PM PDT 24
Peak memory 205744 kb
Host smart-61fb0294-64c5-4f7a-9ad5-275ac1e66392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12581
09644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1258109644
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.1989262427
Short name T49
Test name
Test status
Simulation time 10059534287 ps
CPU time 15.14 seconds
Started Jun 05 05:44:07 PM PDT 24
Finished Jun 05 05:44:23 PM PDT 24
Peak memory 205764 kb
Host smart-9bde64fe-c899-45c3-ac50-b3140dfe93ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19892
62427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.1989262427
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1552461790
Short name T206
Test name
Test status
Simulation time 98060748 ps
CPU time 3.28 seconds
Started Jun 05 05:18:52 PM PDT 24
Finished Jun 05 05:18:55 PM PDT 24
Peak memory 220432 kb
Host smart-f1078ffb-3efd-44cf-8109-b1819e0f2aeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1552461790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1552461790
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.3302228657
Short name T157
Test name
Test status
Simulation time 31235314796 ps
CPU time 142.65 seconds
Started Jun 05 05:44:59 PM PDT 24
Finished Jun 05 05:47:23 PM PDT 24
Peak memory 205752 kb
Host smart-dda0af7b-cd77-4c5a-9956-00d82421856c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3302228657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.3302228657
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.3880447288
Short name T201
Test name
Test status
Simulation time 10077383049 ps
CPU time 13.74 seconds
Started Jun 05 05:49:48 PM PDT 24
Finished Jun 05 05:50:02 PM PDT 24
Peak memory 205752 kb
Host smart-db831b32-be21-4b8d-8796-27b481693b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38804
47288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.3880447288
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2932368856
Short name T281
Test name
Test status
Simulation time 781486194 ps
CPU time 5.43 seconds
Started Jun 05 05:18:47 PM PDT 24
Finished Jun 05 05:18:53 PM PDT 24
Peak memory 204864 kb
Host smart-48c01a22-1490-4711-b1e8-bba334830697
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2932368856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2932368856
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.307019955
Short name T2043
Test name
Test status
Simulation time 43092676 ps
CPU time 0.72 seconds
Started Jun 05 05:18:53 PM PDT 24
Finished Jun 05 05:18:55 PM PDT 24
Peak memory 204552 kb
Host smart-33a870e8-9cd8-4c94-a49d-0cbd367807a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=307019955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.307019955
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.651297892
Short name T192
Test name
Test status
Simulation time 30486848 ps
CPU time 0.72 seconds
Started Jun 05 05:19:17 PM PDT 24
Finished Jun 05 05:19:19 PM PDT 24
Peak memory 204572 kb
Host smart-9bdc1f5d-bc8f-469d-b0e6-03cc7d908406
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=651297892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.651297892
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.2523753672
Short name T200
Test name
Test status
Simulation time 5107201051 ps
CPU time 127.24 seconds
Started Jun 05 05:44:03 PM PDT 24
Finished Jun 05 05:46:11 PM PDT 24
Peak memory 205504 kb
Host smart-82b78a44-cfda-4c23-b854-ed3c4b9e8fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25237
53672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.2523753672
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.705070750
Short name T209
Test name
Test status
Simulation time 1180694389 ps
CPU time 3.6 seconds
Started Jun 05 05:18:20 PM PDT 24
Finished Jun 05 05:18:25 PM PDT 24
Peak memory 204788 kb
Host smart-e05a0392-f272-4b55-8554-2c1809e2214a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=705070750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.705070750
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2274236264
Short name T284
Test name
Test status
Simulation time 324702963 ps
CPU time 2.5 seconds
Started Jun 05 05:18:59 PM PDT 24
Finished Jun 05 05:19:02 PM PDT 24
Peak memory 204796 kb
Host smart-2c8e06f8-fc7e-4f81-99ad-b459b5ed1bea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2274236264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2274236264
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3106286119
Short name T287
Test name
Test status
Simulation time 756928662 ps
CPU time 4.8 seconds
Started Jun 05 05:19:11 PM PDT 24
Finished Jun 05 05:19:17 PM PDT 24
Peak memory 204808 kb
Host smart-d383f74a-f363-405f-b965-1ce05f54a306
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3106286119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3106286119
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.183829951
Short name T2102
Test name
Test status
Simulation time 222110778 ps
CPU time 2.91 seconds
Started Jun 05 05:18:26 PM PDT 24
Finished Jun 05 05:18:29 PM PDT 24
Peak memory 220464 kb
Host smart-ef6f54bf-c894-4ff9-be42-865f26b1f043
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=183829951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.183829951
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.2772448216
Short name T1373
Test name
Test status
Simulation time 30037975577 ps
CPU time 196.86 seconds
Started Jun 05 05:44:28 PM PDT 24
Finished Jun 05 05:47:46 PM PDT 24
Peak memory 205796 kb
Host smart-a46bf8d5-6c4e-4d68-be1d-05cb853e067d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2772448216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2772448216
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.96957498
Short name T73
Test name
Test status
Simulation time 10078123589 ps
CPU time 14.09 seconds
Started Jun 05 05:50:00 PM PDT 24
Finished Jun 05 05:50:15 PM PDT 24
Peak memory 205756 kb
Host smart-2b9a7ac4-a58d-42b9-b366-ce315604feec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96957
498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.96957498
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.427013247
Short name T876
Test name
Test status
Simulation time 10097758913 ps
CPU time 13.27 seconds
Started Jun 05 05:44:21 PM PDT 24
Finished Jun 05 05:44:35 PM PDT 24
Peak memory 205680 kb
Host smart-921f8532-8642-4945-bfcb-32749ce734ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42701
3247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.427013247
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.2635775398
Short name T145
Test name
Test status
Simulation time 10047388330 ps
CPU time 14.71 seconds
Started Jun 05 05:47:56 PM PDT 24
Finished Jun 05 05:48:11 PM PDT 24
Peak memory 205688 kb
Host smart-3521b43d-3565-44e5-8acc-68575f9a24e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26357
75398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.2635775398
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.1843648405
Short name T35
Test name
Test status
Simulation time 11101928513 ps
CPU time 18.11 seconds
Started Jun 05 05:49:20 PM PDT 24
Finished Jun 05 05:49:38 PM PDT 24
Peak memory 205596 kb
Host smart-b75d6c96-fe72-4209-a4a4-92d702b538c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18436
48405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.1843648405
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.1554069540
Short name T180
Test name
Test status
Simulation time 23307610412 ps
CPU time 24.76 seconds
Started Jun 05 05:45:57 PM PDT 24
Finished Jun 05 05:46:22 PM PDT 24
Peak memory 205668 kb
Host smart-7a398317-bd3b-4f06-a7f3-64d2aa141ac0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1554069540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.1554069540
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.2156357830
Short name T127
Test name
Test status
Simulation time 10064723371 ps
CPU time 12.85 seconds
Started Jun 05 05:45:52 PM PDT 24
Finished Jun 05 05:46:06 PM PDT 24
Peak memory 205728 kb
Host smart-f57f9e32-78c7-4764-95f6-d1959118b7a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21563
57830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.2156357830
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3065104241
Short name T195
Test name
Test status
Simulation time 10065149187 ps
CPU time 14.25 seconds
Started Jun 05 05:45:37 PM PDT 24
Finished Jun 05 05:45:52 PM PDT 24
Peak memory 205900 kb
Host smart-1b61f9b0-2638-41b7-8fd4-8de0b3a5744e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30651
04241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3065104241
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.1430068921
Short name T1243
Test name
Test status
Simulation time 10055889292 ps
CPU time 12.84 seconds
Started Jun 05 05:44:12 PM PDT 24
Finished Jun 05 05:44:25 PM PDT 24
Peak memory 205672 kb
Host smart-d7e00b2d-8762-480c-b0e0-8b49b48e8865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14300
68921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.1430068921
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.3150829117
Short name T966
Test name
Test status
Simulation time 10051560562 ps
CPU time 13.64 seconds
Started Jun 05 05:44:09 PM PDT 24
Finished Jun 05 05:44:23 PM PDT 24
Peak memory 205788 kb
Host smart-513ee80c-3376-4072-a3c3-998d6979767c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31508
29117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.3150829117
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1445126747
Short name T124
Test name
Test status
Simulation time 10146331408 ps
CPU time 13.08 seconds
Started Jun 05 05:44:02 PM PDT 24
Finished Jun 05 05:44:16 PM PDT 24
Peak memory 205772 kb
Host smart-afcc1e29-57f1-4e13-a18c-7bedb3a98c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14451
26747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1445126747
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.2540371303
Short name T141
Test name
Test status
Simulation time 10057146728 ps
CPU time 15.1 seconds
Started Jun 05 05:44:15 PM PDT 24
Finished Jun 05 05:44:31 PM PDT 24
Peak memory 205648 kb
Host smart-0a8e29ee-fdb1-45a9-8646-d252b3a5b324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25403
71303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2540371303
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1883914766
Short name T176
Test name
Test status
Simulation time 10072475343 ps
CPU time 15.55 seconds
Started Jun 05 05:45:34 PM PDT 24
Finished Jun 05 05:45:50 PM PDT 24
Peak memory 205796 kb
Host smart-ebd22280-34de-447f-b7d8-cd8203c317c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18839
14766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1883914766
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.4263012996
Short name T1242
Test name
Test status
Simulation time 10068363599 ps
CPU time 16.1 seconds
Started Jun 05 05:45:26 PM PDT 24
Finished Jun 05 05:45:42 PM PDT 24
Peak memory 205732 kb
Host smart-72003468-d55f-42d6-939c-0328f4cf388b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42630
12996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.4263012996
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.386064958
Short name T147
Test name
Test status
Simulation time 10069336818 ps
CPU time 15.68 seconds
Started Jun 05 05:45:38 PM PDT 24
Finished Jun 05 05:45:55 PM PDT 24
Peak memory 205668 kb
Host smart-2d5b7438-f2e1-4770-b0f1-543e2283f581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38606
4958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.386064958
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.3041474079
Short name T160
Test name
Test status
Simulation time 31687795476 ps
CPU time 58.78 seconds
Started Jun 05 05:45:36 PM PDT 24
Finished Jun 05 05:46:35 PM PDT 24
Peak memory 205712 kb
Host smart-dba09254-56e8-4986-ad7d-63c5f9927779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30414
74079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.3041474079
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.687596044
Short name T377
Test name
Test status
Simulation time 10059662898 ps
CPU time 12.64 seconds
Started Jun 05 05:45:43 PM PDT 24
Finished Jun 05 05:45:57 PM PDT 24
Peak memory 205676 kb
Host smart-e5c23daf-37ce-40c3-97ba-fa77822cb84f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68759
6044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.687596044
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.3062028238
Short name T142
Test name
Test status
Simulation time 10049031455 ps
CPU time 13.85 seconds
Started Jun 05 05:46:17 PM PDT 24
Finished Jun 05 05:46:32 PM PDT 24
Peak memory 205680 kb
Host smart-dc8a060d-f63c-4f8c-9d91-32a3c9cda7f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30620
28238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.3062028238
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.37506685
Short name T165
Test name
Test status
Simulation time 32085721642 ps
CPU time 613.68 seconds
Started Jun 05 05:44:42 PM PDT 24
Finished Jun 05 05:54:56 PM PDT 24
Peak memory 205768 kb
Host smart-e4ca1537-5d4b-4b05-8e0c-f547d3c8982d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=37506685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.37506685
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2472032949
Short name T215
Test name
Test status
Simulation time 153920461 ps
CPU time 2.04 seconds
Started Jun 05 05:18:45 PM PDT 24
Finished Jun 05 05:18:49 PM PDT 24
Peak memory 220388 kb
Host smart-36a36084-5d09-4ede-a59d-a0a359420037
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2472032949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2472032949
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.987105362
Short name T116
Test name
Test status
Simulation time 10131018176 ps
CPU time 12.9 seconds
Started Jun 05 05:44:01 PM PDT 24
Finished Jun 05 05:44:15 PM PDT 24
Peak memory 205684 kb
Host smart-fad0fd22-b1ac-40e4-9303-3bf60fff08f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98710
5362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.987105362
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.3637649574
Short name T1895
Test name
Test status
Simulation time 23480381310 ps
CPU time 47.01 seconds
Started Jun 05 05:44:03 PM PDT 24
Finished Jun 05 05:44:51 PM PDT 24
Peak memory 205688 kb
Host smart-2165639d-7ddd-4586-a5a2-c3a1537605ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36376
49574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.3637649574
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.768293133
Short name T1683
Test name
Test status
Simulation time 10094369999 ps
CPU time 13.49 seconds
Started Jun 05 05:44:21 PM PDT 24
Finished Jun 05 05:44:35 PM PDT 24
Peak memory 205772 kb
Host smart-64bce656-2c1e-498a-af28-b65059a76c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76829
3133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.768293133
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.3668208234
Short name T118
Test name
Test status
Simulation time 10104652334 ps
CPU time 13.17 seconds
Started Jun 05 05:45:23 PM PDT 24
Finished Jun 05 05:45:37 PM PDT 24
Peak memory 205692 kb
Host smart-2f690ce4-4e36-4bed-89b7-4b00417e1a96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36682
08234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.3668208234
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.3240657159
Short name T761
Test name
Test status
Simulation time 10950155239 ps
CPU time 15.16 seconds
Started Jun 05 05:45:29 PM PDT 24
Finished Jun 05 05:45:45 PM PDT 24
Peak memory 205704 kb
Host smart-a1539aec-7291-48e0-9712-537f82de5b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32406
57159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.3240657159
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3191398957
Short name T117
Test name
Test status
Simulation time 10091197527 ps
CPU time 13.94 seconds
Started Jun 05 05:45:38 PM PDT 24
Finished Jun 05 05:45:53 PM PDT 24
Peak memory 205768 kb
Host smart-35a13c39-849c-4ce0-b076-e9e71979024d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31913
98957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3191398957
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.4169413967
Short name T107
Test name
Test status
Simulation time 10111891930 ps
CPU time 15.2 seconds
Started Jun 05 05:46:08 PM PDT 24
Finished Jun 05 05:46:24 PM PDT 24
Peak memory 205680 kb
Host smart-4fb29198-44ae-411a-b4eb-172b75358f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41694
13967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.4169413967
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.2589745767
Short name T112
Test name
Test status
Simulation time 10108835589 ps
CPU time 13.26 seconds
Started Jun 05 05:46:04 PM PDT 24
Finished Jun 05 05:46:18 PM PDT 24
Peak memory 205684 kb
Host smart-36dc6751-ac71-4c52-8c88-7fb3105f8491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25897
45767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.2589745767
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.1435466228
Short name T110
Test name
Test status
Simulation time 10109646708 ps
CPU time 15.85 seconds
Started Jun 05 05:46:14 PM PDT 24
Finished Jun 05 05:46:31 PM PDT 24
Peak memory 205736 kb
Host smart-180a6717-396a-4020-aa5d-1432676dabf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14354
66228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.1435466228
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.586566871
Short name T1064
Test name
Test status
Simulation time 10123360864 ps
CPU time 13.05 seconds
Started Jun 05 05:46:17 PM PDT 24
Finished Jun 05 05:46:31 PM PDT 24
Peak memory 205652 kb
Host smart-1c72fbc3-6c8e-4d46-8df1-2efc6e0578d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58656
6871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.586566871
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.4011220072
Short name T90
Test name
Test status
Simulation time 10070995840 ps
CPU time 13.45 seconds
Started Jun 05 05:46:43 PM PDT 24
Finished Jun 05 05:46:57 PM PDT 24
Peak memory 205772 kb
Host smart-995594f7-c81d-4bbf-87c7-faecc42f156f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40112
20072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.4011220072
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3708251753
Short name T106
Test name
Test status
Simulation time 10125651613 ps
CPU time 13.73 seconds
Started Jun 05 05:47:39 PM PDT 24
Finished Jun 05 05:47:53 PM PDT 24
Peak memory 205688 kb
Host smart-f33a69d8-b673-4989-9398-205e3d0ed253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37082
51753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3708251753
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.4094484903
Short name T1527
Test name
Test status
Simulation time 10079365458 ps
CPU time 14.27 seconds
Started Jun 05 05:47:50 PM PDT 24
Finished Jun 05 05:48:05 PM PDT 24
Peak memory 205684 kb
Host smart-3c2d7150-ea87-45cb-922e-2bd82fbce056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40944
84903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.4094484903
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1071203653
Short name T241
Test name
Test status
Simulation time 287986502 ps
CPU time 3.34 seconds
Started Jun 05 05:18:22 PM PDT 24
Finished Jun 05 05:18:26 PM PDT 24
Peak memory 204804 kb
Host smart-e5383cfe-bcfc-4da4-a080-51a9b06e1a79
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1071203653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1071203653
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1486316598
Short name T2087
Test name
Test status
Simulation time 861056822 ps
CPU time 5 seconds
Started Jun 05 05:18:23 PM PDT 24
Finished Jun 05 05:18:28 PM PDT 24
Peak memory 204796 kb
Host smart-da959c8b-9438-4066-8441-7e97e8fc876e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1486316598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1486316598
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.689172732
Short name T2124
Test name
Test status
Simulation time 200700222 ps
CPU time 1.09 seconds
Started Jun 05 05:18:20 PM PDT 24
Finished Jun 05 05:18:23 PM PDT 24
Peak memory 204596 kb
Host smart-121f75e2-5300-42dc-8cbd-0933293c712e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=689172732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.689172732
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1328712149
Short name T2095
Test name
Test status
Simulation time 147493696 ps
CPU time 1.58 seconds
Started Jun 05 05:18:25 PM PDT 24
Finished Jun 05 05:18:27 PM PDT 24
Peak memory 213060 kb
Host smart-de278ee3-c064-4e39-856e-e070ca649fd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328712149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.1328712149
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3324889873
Short name T234
Test name
Test status
Simulation time 50388268 ps
CPU time 0.84 seconds
Started Jun 05 05:18:23 PM PDT 24
Finished Jun 05 05:18:25 PM PDT 24
Peak memory 204636 kb
Host smart-8d71961e-a815-438f-8af0-ce06e3ece668
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3324889873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3324889873
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3219199678
Short name T275
Test name
Test status
Simulation time 46719314 ps
CPU time 0.67 seconds
Started Jun 05 05:18:26 PM PDT 24
Finished Jun 05 05:18:27 PM PDT 24
Peak memory 204508 kb
Host smart-ba94dcfe-54c3-41fa-951d-fbaaddfcde50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3219199678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3219199678
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.477515909
Short name T244
Test name
Test status
Simulation time 81548896 ps
CPU time 1.38 seconds
Started Jun 05 05:18:24 PM PDT 24
Finished Jun 05 05:18:26 PM PDT 24
Peak memory 213036 kb
Host smart-05a3b75f-5ab4-4b7e-8c49-6ddf2ab0f733
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=477515909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.477515909
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3137788529
Short name T2054
Test name
Test status
Simulation time 134176362 ps
CPU time 2.43 seconds
Started Jun 05 05:18:21 PM PDT 24
Finished Jun 05 05:18:24 PM PDT 24
Peak memory 204800 kb
Host smart-c0b6988b-3cee-4fb1-8f27-34131c08e327
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3137788529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3137788529
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.681948742
Short name T265
Test name
Test status
Simulation time 152466810 ps
CPU time 1.24 seconds
Started Jun 05 05:18:22 PM PDT 24
Finished Jun 05 05:18:24 PM PDT 24
Peak memory 204812 kb
Host smart-52917d85-1b86-4660-ade3-8a97f8aacc33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=681948742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.681948742
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1327745995
Short name T2079
Test name
Test status
Simulation time 769105034 ps
CPU time 3.78 seconds
Started Jun 05 05:18:24 PM PDT 24
Finished Jun 05 05:18:28 PM PDT 24
Peak memory 204824 kb
Host smart-baabd1ad-1a8a-44b0-8e88-d7366b3269d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1327745995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.1327745995
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1960476284
Short name T2046
Test name
Test status
Simulation time 82434719 ps
CPU time 2.04 seconds
Started Jun 05 05:18:28 PM PDT 24
Finished Jun 05 05:18:31 PM PDT 24
Peak memory 204844 kb
Host smart-431e1ad4-04e7-4324-9a01-ca1d60e1d716
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1960476284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1960476284
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1066387128
Short name T2037
Test name
Test status
Simulation time 1384739973 ps
CPU time 9.42 seconds
Started Jun 05 05:18:33 PM PDT 24
Finished Jun 05 05:18:43 PM PDT 24
Peak memory 204800 kb
Host smart-812f27e5-c3d7-4cb9-a550-f53abdfc70f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1066387128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1066387128
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2964285618
Short name T248
Test name
Test status
Simulation time 123047799 ps
CPU time 0.98 seconds
Started Jun 05 05:18:22 PM PDT 24
Finished Jun 05 05:18:24 PM PDT 24
Peak memory 204604 kb
Host smart-dcd0c141-3e11-4aa1-851c-d330e8b4e9a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2964285618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2964285618
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2930740135
Short name T266
Test name
Test status
Simulation time 117736142 ps
CPU time 1.29 seconds
Started Jun 05 05:18:29 PM PDT 24
Finished Jun 05 05:18:31 PM PDT 24
Peak memory 213104 kb
Host smart-98afda86-71bb-4c06-bde9-777df4facd36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930740135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2930740135
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4020166913
Short name T247
Test name
Test status
Simulation time 57007948 ps
CPU time 0.94 seconds
Started Jun 05 05:18:30 PM PDT 24
Finished Jun 05 05:18:32 PM PDT 24
Peak memory 204768 kb
Host smart-43750496-5b18-46e8-a60c-598d621b60cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4020166913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.4020166913
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.4191000677
Short name T2057
Test name
Test status
Simulation time 37248819 ps
CPU time 0.67 seconds
Started Jun 05 05:18:24 PM PDT 24
Finished Jun 05 05:18:26 PM PDT 24
Peak memory 204540 kb
Host smart-8d97b628-652a-446a-adce-ddc031fea995
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4191000677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.4191000677
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1661350661
Short name T235
Test name
Test status
Simulation time 201876352 ps
CPU time 2.38 seconds
Started Jun 05 05:18:21 PM PDT 24
Finished Jun 05 05:18:24 PM PDT 24
Peak memory 212972 kb
Host smart-521bc140-a393-4c23-a1e3-838575467832
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1661350661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1661350661
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.387772451
Short name T2097
Test name
Test status
Simulation time 419688057 ps
CPU time 2.78 seconds
Started Jun 05 05:18:23 PM PDT 24
Finished Jun 05 05:18:27 PM PDT 24
Peak memory 204832 kb
Host smart-591160c5-e043-4f7d-b27f-484711ca3473
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=387772451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.387772451
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1313678092
Short name T2131
Test name
Test status
Simulation time 347322902 ps
CPU time 2.02 seconds
Started Jun 05 05:18:29 PM PDT 24
Finished Jun 05 05:18:31 PM PDT 24
Peak memory 204784 kb
Host smart-0879116b-0e04-463d-8c8b-0b0114a9b2f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1313678092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.1313678092
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.476821630
Short name T216
Test name
Test status
Simulation time 128791475 ps
CPU time 1.67 seconds
Started Jun 05 05:18:20 PM PDT 24
Finished Jun 05 05:18:22 PM PDT 24
Peak memory 213004 kb
Host smart-0495696a-e4c4-4539-9a80-3d70b9d04f19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=476821630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.476821630
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3973273893
Short name T2128
Test name
Test status
Simulation time 109233579 ps
CPU time 1.42 seconds
Started Jun 05 05:18:45 PM PDT 24
Finished Jun 05 05:18:48 PM PDT 24
Peak memory 214700 kb
Host smart-2f33d21a-caf7-40da-9140-b066fc23d370
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973273893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.3973273893
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1997602365
Short name T2093
Test name
Test status
Simulation time 62450579 ps
CPU time 0.82 seconds
Started Jun 05 05:18:51 PM PDT 24
Finished Jun 05 05:18:53 PM PDT 24
Peak memory 204624 kb
Host smart-cfbcab91-a991-465b-8f04-b817b228f41f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1997602365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.1997602365
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.4205488587
Short name T253
Test name
Test status
Simulation time 189461392 ps
CPU time 1.55 seconds
Started Jun 05 05:18:52 PM PDT 24
Finished Jun 05 05:18:54 PM PDT 24
Peak memory 204720 kb
Host smart-17a4d78e-f9c6-48b4-b9ab-f35cc0ccad72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4205488587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.4205488587
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.4105279154
Short name T2118
Test name
Test status
Simulation time 126233615 ps
CPU time 1.43 seconds
Started Jun 05 05:18:53 PM PDT 24
Finished Jun 05 05:18:55 PM PDT 24
Peak memory 215036 kb
Host smart-444995a8-eeab-4601-8cc8-aa04c4c33ac6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105279154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.4105279154
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.4077698981
Short name T2112
Test name
Test status
Simulation time 96688376 ps
CPU time 0.87 seconds
Started Jun 05 05:18:51 PM PDT 24
Finished Jun 05 05:18:52 PM PDT 24
Peak memory 204592 kb
Host smart-ce66dc85-27d9-478d-98d6-b208229606fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4077698981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.4077698981
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.4259502611
Short name T2132
Test name
Test status
Simulation time 70031457 ps
CPU time 0.73 seconds
Started Jun 05 05:18:53 PM PDT 24
Finished Jun 05 05:18:54 PM PDT 24
Peak memory 204600 kb
Host smart-06d1c2ee-8d5a-4759-beb4-977d8a114370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4259502611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.4259502611
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3013197996
Short name T2123
Test name
Test status
Simulation time 184856535 ps
CPU time 1.84 seconds
Started Jun 05 05:18:50 PM PDT 24
Finished Jun 05 05:18:53 PM PDT 24
Peak memory 204852 kb
Host smart-43ed815e-2b7d-43c8-b792-61c563d9c93b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3013197996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3013197996
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3480027096
Short name T219
Test name
Test status
Simulation time 60429939 ps
CPU time 1.55 seconds
Started Jun 05 05:18:45 PM PDT 24
Finished Jun 05 05:18:48 PM PDT 24
Peak memory 204876 kb
Host smart-7a1428a3-2d73-44d2-bd77-e47d084d184a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3480027096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3480027096
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.4165794791
Short name T187
Test name
Test status
Simulation time 791464166 ps
CPU time 5.21 seconds
Started Jun 05 05:18:44 PM PDT 24
Finished Jun 05 05:18:51 PM PDT 24
Peak memory 204828 kb
Host smart-64011802-8331-47a0-87f1-214c805c4a72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4165794791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.4165794791
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3837673081
Short name T185
Test name
Test status
Simulation time 103222864 ps
CPU time 1.78 seconds
Started Jun 05 05:18:52 PM PDT 24
Finished Jun 05 05:18:54 PM PDT 24
Peak memory 213092 kb
Host smart-b5dca8e3-2183-4889-9930-d3ff29458be2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837673081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.3837673081
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2265127734
Short name T249
Test name
Test status
Simulation time 50580266 ps
CPU time 1 seconds
Started Jun 05 05:18:52 PM PDT 24
Finished Jun 05 05:18:54 PM PDT 24
Peak memory 204884 kb
Host smart-4ce6911c-931f-4cbd-8147-7243bdad9209
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2265127734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2265127734
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2089479309
Short name T2045
Test name
Test status
Simulation time 92241498 ps
CPU time 1.15 seconds
Started Jun 05 05:18:51 PM PDT 24
Finished Jun 05 05:18:52 PM PDT 24
Peak memory 204828 kb
Host smart-cf25eefb-cbe9-4ce2-b364-09a22f9c01c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2089479309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.2089479309
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1780838541
Short name T288
Test name
Test status
Simulation time 642739539 ps
CPU time 2.91 seconds
Started Jun 05 05:18:52 PM PDT 24
Finished Jun 05 05:18:55 PM PDT 24
Peak memory 204828 kb
Host smart-3a722231-d1f4-44e5-af85-3adb2f03c74f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1780838541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1780838541
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1406084323
Short name T2084
Test name
Test status
Simulation time 72936089 ps
CPU time 1.75 seconds
Started Jun 05 05:19:04 PM PDT 24
Finished Jun 05 05:19:07 PM PDT 24
Peak memory 213012 kb
Host smart-ec90a07d-c3dd-49db-8b02-9ed203310f59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406084323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1406084323
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1871810178
Short name T252
Test name
Test status
Simulation time 78487130 ps
CPU time 0.95 seconds
Started Jun 05 05:18:54 PM PDT 24
Finished Jun 05 05:18:56 PM PDT 24
Peak memory 204624 kb
Host smart-21a33fe2-109d-4cac-a0e4-bb211c58e0bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1871810178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1871810178
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3806506833
Short name T271
Test name
Test status
Simulation time 86931225 ps
CPU time 0.76 seconds
Started Jun 05 05:18:54 PM PDT 24
Finished Jun 05 05:18:55 PM PDT 24
Peak memory 204512 kb
Host smart-23b73e7c-f329-4217-9bbd-b70f47bdba7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3806506833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3806506833
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1277010737
Short name T2077
Test name
Test status
Simulation time 124042640 ps
CPU time 1.19 seconds
Started Jun 05 05:18:51 PM PDT 24
Finished Jun 05 05:18:53 PM PDT 24
Peak memory 204872 kb
Host smart-35db3726-debf-4140-8550-41dce54dbae2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1277010737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1277010737
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.33538148
Short name T212
Test name
Test status
Simulation time 238687329 ps
CPU time 2.43 seconds
Started Jun 05 05:18:53 PM PDT 24
Finished Jun 05 05:18:56 PM PDT 24
Peak memory 204896 kb
Host smart-d0f76682-96c7-4ff2-a3f1-a7b817fe647e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=33538148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.33538148
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3917998140
Short name T283
Test name
Test status
Simulation time 395423081 ps
CPU time 3.01 seconds
Started Jun 05 05:18:54 PM PDT 24
Finished Jun 05 05:18:57 PM PDT 24
Peak memory 204788 kb
Host smart-b2d119ca-5897-4919-aca5-8db5127f2d6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3917998140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3917998140
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1401578240
Short name T269
Test name
Test status
Simulation time 189849394 ps
CPU time 1.27 seconds
Started Jun 05 05:19:00 PM PDT 24
Finished Jun 05 05:19:01 PM PDT 24
Peak memory 214604 kb
Host smart-e5f9c214-c60a-418e-9123-c198d10ce6a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401578240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.1401578240
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1981908904
Short name T237
Test name
Test status
Simulation time 61972913 ps
CPU time 0.89 seconds
Started Jun 05 05:19:01 PM PDT 24
Finished Jun 05 05:19:03 PM PDT 24
Peak memory 204628 kb
Host smart-572f40a4-542d-4ccc-9f0c-b82eafe50c7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1981908904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1981908904
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3927244113
Short name T2108
Test name
Test status
Simulation time 41639915 ps
CPU time 0.7 seconds
Started Jun 05 05:19:00 PM PDT 24
Finished Jun 05 05:19:01 PM PDT 24
Peak memory 204592 kb
Host smart-3e545b90-e16f-4780-9293-f7ce0b942882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3927244113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3927244113
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.731226014
Short name T2120
Test name
Test status
Simulation time 215125135 ps
CPU time 1.88 seconds
Started Jun 05 05:19:02 PM PDT 24
Finished Jun 05 05:19:04 PM PDT 24
Peak memory 204792 kb
Host smart-685a127d-74e9-4b50-88c2-9e7c9291122b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=731226014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.731226014
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1998928109
Short name T2100
Test name
Test status
Simulation time 107526310 ps
CPU time 2.71 seconds
Started Jun 05 05:18:59 PM PDT 24
Finished Jun 05 05:19:03 PM PDT 24
Peak memory 220436 kb
Host smart-0955699d-80ac-40bc-b6a9-e75673aa566d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1998928109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.1998928109
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.4124827814
Short name T282
Test name
Test status
Simulation time 866365661 ps
CPU time 5.39 seconds
Started Jun 05 05:19:00 PM PDT 24
Finished Jun 05 05:19:06 PM PDT 24
Peak memory 204884 kb
Host smart-520542fa-af84-49cb-b03c-78b4941fedf4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4124827814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.4124827814
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2701599701
Short name T220
Test name
Test status
Simulation time 96148164 ps
CPU time 1.84 seconds
Started Jun 05 05:19:12 PM PDT 24
Finished Jun 05 05:19:15 PM PDT 24
Peak memory 213068 kb
Host smart-0c4c65fa-cc42-4ed8-9bb9-e39faeddffb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701599701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.2701599701
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3459584203
Short name T2086
Test name
Test status
Simulation time 114030522 ps
CPU time 1.16 seconds
Started Jun 05 05:19:01 PM PDT 24
Finished Jun 05 05:19:03 PM PDT 24
Peak memory 204868 kb
Host smart-15d44361-5e0e-47a1-baed-627cce3ff292
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3459584203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3459584203
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2599287383
Short name T2074
Test name
Test status
Simulation time 44182867 ps
CPU time 0.71 seconds
Started Jun 05 05:19:00 PM PDT 24
Finished Jun 05 05:19:01 PM PDT 24
Peak memory 204548 kb
Host smart-e92aca09-fabb-40d2-a94f-8c890f1bb4a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2599287383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2599287383
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1511075336
Short name T2062
Test name
Test status
Simulation time 179511781 ps
CPU time 1.76 seconds
Started Jun 05 05:19:07 PM PDT 24
Finished Jun 05 05:19:09 PM PDT 24
Peak memory 204872 kb
Host smart-41314d44-b30a-44ca-8fde-37651537ef21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1511075336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1511075336
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2984104794
Short name T2101
Test name
Test status
Simulation time 169543153 ps
CPU time 2.34 seconds
Started Jun 05 05:19:01 PM PDT 24
Finished Jun 05 05:19:04 PM PDT 24
Peak memory 205100 kb
Host smart-c46f869d-7db8-4d18-85de-89ada78148f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2984104794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2984104794
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1231788776
Short name T214
Test name
Test status
Simulation time 120268984 ps
CPU time 2.33 seconds
Started Jun 05 05:19:11 PM PDT 24
Finished Jun 05 05:19:15 PM PDT 24
Peak memory 213092 kb
Host smart-6a30c4ce-853f-4d24-99c8-0ddcb48484a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231788776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.1231788776
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3799547100
Short name T2075
Test name
Test status
Simulation time 44356086 ps
CPU time 1 seconds
Started Jun 05 05:19:10 PM PDT 24
Finished Jun 05 05:19:12 PM PDT 24
Peak memory 204256 kb
Host smart-298fc66a-01d1-41f1-a7f3-c429e2a5a132
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3799547100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3799547100
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2217502478
Short name T2125
Test name
Test status
Simulation time 46926571 ps
CPU time 0.68 seconds
Started Jun 05 05:19:10 PM PDT 24
Finished Jun 05 05:19:12 PM PDT 24
Peak memory 204072 kb
Host smart-a6df0a14-59c7-40d6-908c-a94dba212281
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2217502478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2217502478
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2202928414
Short name T188
Test name
Test status
Simulation time 146915930 ps
CPU time 1.45 seconds
Started Jun 05 05:19:08 PM PDT 24
Finished Jun 05 05:19:10 PM PDT 24
Peak memory 204780 kb
Host smart-e7079694-5c93-4e2c-944f-c179dfbdef58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2202928414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.2202928414
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1056981801
Short name T2134
Test name
Test status
Simulation time 131871140 ps
CPU time 2.86 seconds
Started Jun 05 05:19:10 PM PDT 24
Finished Jun 05 05:19:14 PM PDT 24
Peak memory 204844 kb
Host smart-1c150dfe-5cb1-490c-8c19-6747db97b539
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1056981801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1056981801
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2381534782
Short name T2107
Test name
Test status
Simulation time 886800760 ps
CPU time 4.7 seconds
Started Jun 05 05:19:10 PM PDT 24
Finished Jun 05 05:19:16 PM PDT 24
Peak memory 204808 kb
Host smart-728251db-6111-44ed-9957-b855a4cdd6f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2381534782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.2381534782
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.353454508
Short name T2096
Test name
Test status
Simulation time 111419039 ps
CPU time 0.88 seconds
Started Jun 05 05:19:08 PM PDT 24
Finished Jun 05 05:19:10 PM PDT 24
Peak memory 204504 kb
Host smart-0b125a55-6892-4e36-a0d0-270f6ae5f26a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=353454508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.353454508
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2134271636
Short name T91
Test name
Test status
Simulation time 123507124 ps
CPU time 0.76 seconds
Started Jun 05 05:19:08 PM PDT 24
Finished Jun 05 05:19:09 PM PDT 24
Peak memory 204576 kb
Host smart-7c9671ff-5cff-4e22-a08a-baefc7171f55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2134271636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2134271636
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1148969623
Short name T2040
Test name
Test status
Simulation time 152936603 ps
CPU time 1.91 seconds
Started Jun 05 05:19:11 PM PDT 24
Finished Jun 05 05:19:15 PM PDT 24
Peak memory 204800 kb
Host smart-dbe96278-5b51-478f-9d93-17907ba3576d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1148969623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1148969623
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2262380100
Short name T2063
Test name
Test status
Simulation time 265441372 ps
CPU time 2.81 seconds
Started Jun 05 05:19:10 PM PDT 24
Finished Jun 05 05:19:14 PM PDT 24
Peak memory 220616 kb
Host smart-2de846d1-70c1-4f04-9eb3-6b14e701518d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2262380100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2262380100
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.4136691584
Short name T2081
Test name
Test status
Simulation time 91214187 ps
CPU time 1.41 seconds
Started Jun 05 05:19:13 PM PDT 24
Finished Jun 05 05:19:15 PM PDT 24
Peak memory 213064 kb
Host smart-fc5088a3-7f5f-4555-afe4-6b8119f2e5f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136691584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.4136691584
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2800306999
Short name T268
Test name
Test status
Simulation time 93499115 ps
CPU time 0.92 seconds
Started Jun 05 05:19:10 PM PDT 24
Finished Jun 05 05:19:12 PM PDT 24
Peak memory 204524 kb
Host smart-40a44c65-38d3-4bb9-9a71-9da82dd3b102
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2800306999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2800306999
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3399282950
Short name T2089
Test name
Test status
Simulation time 31570536 ps
CPU time 0.65 seconds
Started Jun 05 05:19:08 PM PDT 24
Finished Jun 05 05:19:09 PM PDT 24
Peak memory 204588 kb
Host smart-3bb3f075-ef99-4c7a-a218-6e53f86d4d52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3399282950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3399282950
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2874649410
Short name T2080
Test name
Test status
Simulation time 185151574 ps
CPU time 1.57 seconds
Started Jun 05 05:19:11 PM PDT 24
Finished Jun 05 05:19:14 PM PDT 24
Peak memory 204772 kb
Host smart-d152ffba-7177-4d45-bb86-9a98538381ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2874649410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2874649410
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3057363750
Short name T2121
Test name
Test status
Simulation time 94344489 ps
CPU time 2.26 seconds
Started Jun 05 05:19:11 PM PDT 24
Finished Jun 05 05:19:15 PM PDT 24
Peak memory 204892 kb
Host smart-bdbf44c2-1afd-4654-8eef-72d9a115866c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3057363750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3057363750
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1938754162
Short name T290
Test name
Test status
Simulation time 1771152563 ps
CPU time 5.93 seconds
Started Jun 05 05:19:10 PM PDT 24
Finished Jun 05 05:19:17 PM PDT 24
Peak memory 204804 kb
Host smart-5f230810-0b10-4d3d-b14b-a82d041cdad3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1938754162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1938754162
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3826243689
Short name T2041
Test name
Test status
Simulation time 214499397 ps
CPU time 2.34 seconds
Started Jun 05 05:19:09 PM PDT 24
Finished Jun 05 05:19:12 PM PDT 24
Peak memory 213084 kb
Host smart-13c2156e-f4bc-4c04-afa5-47a847c5beaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826243689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.3826243689
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3442130875
Short name T236
Test name
Test status
Simulation time 88220205 ps
CPU time 1 seconds
Started Jun 05 05:19:09 PM PDT 24
Finished Jun 05 05:19:11 PM PDT 24
Peak memory 204796 kb
Host smart-72ce4bb7-c303-4d3f-b525-6f813443c124
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3442130875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3442130875
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1700685946
Short name T2056
Test name
Test status
Simulation time 36295406 ps
CPU time 0.72 seconds
Started Jun 05 05:19:09 PM PDT 24
Finished Jun 05 05:19:10 PM PDT 24
Peak memory 204576 kb
Host smart-3385049f-18b0-4ffb-ab21-ca5039d98403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1700685946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.1700685946
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2124081463
Short name T2038
Test name
Test status
Simulation time 57489932 ps
CPU time 1.08 seconds
Started Jun 05 05:19:08 PM PDT 24
Finished Jun 05 05:19:10 PM PDT 24
Peak memory 204844 kb
Host smart-e64fc51a-f973-468c-b6e8-f60b306047bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2124081463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2124081463
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2408068373
Short name T2067
Test name
Test status
Simulation time 74399643 ps
CPU time 1.45 seconds
Started Jun 05 05:19:10 PM PDT 24
Finished Jun 05 05:19:13 PM PDT 24
Peak memory 212976 kb
Host smart-e3a172a1-0bc3-44a3-907f-878822c85216
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2408068373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.2408068373
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.4028661913
Short name T289
Test name
Test status
Simulation time 1483611975 ps
CPU time 6.16 seconds
Started Jun 05 05:19:12 PM PDT 24
Finished Jun 05 05:19:19 PM PDT 24
Peak memory 204872 kb
Host smart-26ba9c44-9ef2-48ed-ac0c-998105f34ad8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4028661913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.4028661913
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1345947682
Short name T242
Test name
Test status
Simulation time 124287675 ps
CPU time 3.29 seconds
Started Jun 05 05:18:29 PM PDT 24
Finished Jun 05 05:18:32 PM PDT 24
Peak memory 204816 kb
Host smart-937939ca-836e-43e9-9b84-1b89e56fdee1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1345947682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.1345947682
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.217921075
Short name T239
Test name
Test status
Simulation time 1140630241 ps
CPU time 4.63 seconds
Started Jun 05 05:18:30 PM PDT 24
Finished Jun 05 05:18:36 PM PDT 24
Peak memory 204788 kb
Host smart-973b74b7-91ab-4786-b667-78744727f4e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=217921075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.217921075
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2182534577
Short name T2042
Test name
Test status
Simulation time 76857464 ps
CPU time 0.92 seconds
Started Jun 05 05:18:28 PM PDT 24
Finished Jun 05 05:18:30 PM PDT 24
Peak memory 204608 kb
Host smart-87627ae0-aa60-4b60-9923-d1f290d4fb11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2182534577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2182534577
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2285999896
Short name T211
Test name
Test status
Simulation time 159795454 ps
CPU time 2.41 seconds
Started Jun 05 05:18:31 PM PDT 24
Finished Jun 05 05:18:34 PM PDT 24
Peak memory 213104 kb
Host smart-1acdba43-9126-4def-9183-a3d9a3ce220e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285999896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.2285999896
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.4094771682
Short name T243
Test name
Test status
Simulation time 84506392 ps
CPU time 0.89 seconds
Started Jun 05 05:18:33 PM PDT 24
Finished Jun 05 05:18:34 PM PDT 24
Peak memory 204604 kb
Host smart-6a13429e-8969-4495-9b2a-5f637d890ecb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4094771682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.4094771682
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.4254700691
Short name T2113
Test name
Test status
Simulation time 57028694 ps
CPU time 0.68 seconds
Started Jun 05 05:18:29 PM PDT 24
Finished Jun 05 05:18:31 PM PDT 24
Peak memory 204580 kb
Host smart-7113a9ad-aaa7-483e-a048-677faccbdc74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4254700691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.4254700691
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4254941997
Short name T245
Test name
Test status
Simulation time 202157565 ps
CPU time 2.49 seconds
Started Jun 05 05:18:29 PM PDT 24
Finished Jun 05 05:18:32 PM PDT 24
Peak memory 212972 kb
Host smart-133375f6-8cc6-4c2b-893e-4af175d3e5c8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4254941997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.4254941997
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3537546161
Short name T2094
Test name
Test status
Simulation time 274341568 ps
CPU time 2.66 seconds
Started Jun 05 05:18:28 PM PDT 24
Finished Jun 05 05:18:31 PM PDT 24
Peak memory 204812 kb
Host smart-445e24d9-83a2-4125-b311-8d2b88afe5ac
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3537546161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3537546161
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2333581635
Short name T189
Test name
Test status
Simulation time 114002733 ps
CPU time 1.21 seconds
Started Jun 05 05:18:32 PM PDT 24
Finished Jun 05 05:18:33 PM PDT 24
Peak memory 204756 kb
Host smart-2a805039-cd99-4afd-a27b-3b8710edfaac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2333581635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2333581635
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.529530902
Short name T2115
Test name
Test status
Simulation time 206586481 ps
CPU time 2.42 seconds
Started Jun 05 05:18:31 PM PDT 24
Finished Jun 05 05:18:34 PM PDT 24
Peak memory 213088 kb
Host smart-f390b2f0-216e-4435-9191-2dcd6d4578e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=529530902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.529530902
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.680409514
Short name T280
Test name
Test status
Simulation time 821881255 ps
CPU time 4.97 seconds
Started Jun 05 05:18:29 PM PDT 24
Finished Jun 05 05:18:35 PM PDT 24
Peak memory 204852 kb
Host smart-35c439a4-8f02-466c-8765-4eff12c8ae6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=680409514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.680409514
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2678902282
Short name T2091
Test name
Test status
Simulation time 50563192 ps
CPU time 0.71 seconds
Started Jun 05 05:19:10 PM PDT 24
Finished Jun 05 05:19:12 PM PDT 24
Peak memory 204588 kb
Host smart-55cb0976-6803-429d-8510-d23000faf2cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2678902282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2678902282
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1026968396
Short name T2055
Test name
Test status
Simulation time 71961884 ps
CPU time 0.74 seconds
Started Jun 05 05:19:10 PM PDT 24
Finished Jun 05 05:19:12 PM PDT 24
Peak memory 204572 kb
Host smart-2da729e5-cb7f-4a7a-a091-7302e1dd8509
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1026968396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1026968396
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1968984902
Short name T2119
Test name
Test status
Simulation time 52211181 ps
CPU time 0.73 seconds
Started Jun 05 05:19:09 PM PDT 24
Finished Jun 05 05:19:11 PM PDT 24
Peak memory 204592 kb
Host smart-136f3bc3-543a-40ce-8713-0f1f90ccd79e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1968984902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1968984902
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.490688267
Short name T2082
Test name
Test status
Simulation time 42249102 ps
CPU time 0.69 seconds
Started Jun 05 05:19:08 PM PDT 24
Finished Jun 05 05:19:10 PM PDT 24
Peak memory 204564 kb
Host smart-1e231034-c0db-47a5-b10a-98f24420c7a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=490688267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.490688267
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2251352495
Short name T2110
Test name
Test status
Simulation time 35383536 ps
CPU time 0.67 seconds
Started Jun 05 05:19:10 PM PDT 24
Finished Jun 05 05:19:11 PM PDT 24
Peak memory 204560 kb
Host smart-ab4b3e72-94cb-411d-936e-d1ee2af3c931
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2251352495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2251352495
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1268559843
Short name T2048
Test name
Test status
Simulation time 62978532 ps
CPU time 0.72 seconds
Started Jun 05 05:19:08 PM PDT 24
Finished Jun 05 05:19:09 PM PDT 24
Peak memory 204588 kb
Host smart-7691aa1b-4ee6-4f10-b462-e58d9fe2eea2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1268559843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1268559843
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2612019946
Short name T2049
Test name
Test status
Simulation time 68754348 ps
CPU time 0.7 seconds
Started Jun 05 05:19:10 PM PDT 24
Finished Jun 05 05:19:11 PM PDT 24
Peak memory 204548 kb
Host smart-73131328-c7ad-4341-93c9-399573936be4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2612019946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2612019946
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3908634039
Short name T279
Test name
Test status
Simulation time 32971003 ps
CPU time 0.68 seconds
Started Jun 05 05:19:13 PM PDT 24
Finished Jun 05 05:19:14 PM PDT 24
Peak memory 204584 kb
Host smart-2e1cad8e-ca8e-4977-8262-22224a712689
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3908634039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3908634039
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3301748892
Short name T2126
Test name
Test status
Simulation time 33687716 ps
CPU time 0.66 seconds
Started Jun 05 05:19:10 PM PDT 24
Finished Jun 05 05:19:12 PM PDT 24
Peak memory 204572 kb
Host smart-2e843733-66aa-48ce-add6-becebc9ad709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3301748892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3301748892
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2755706109
Short name T240
Test name
Test status
Simulation time 301839621 ps
CPU time 3.48 seconds
Started Jun 05 05:18:29 PM PDT 24
Finished Jun 05 05:18:33 PM PDT 24
Peak memory 204756 kb
Host smart-9296e51b-58d3-4c27-b480-325a0426f2ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2755706109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2755706109
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1779649157
Short name T238
Test name
Test status
Simulation time 1256771515 ps
CPU time 5.79 seconds
Started Jun 05 05:18:27 PM PDT 24
Finished Jun 05 05:18:34 PM PDT 24
Peak memory 204808 kb
Host smart-2bb25cd0-e3a2-4462-b6b0-06682968a9ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1779649157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1779649157
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.4123449883
Short name T2070
Test name
Test status
Simulation time 107244403 ps
CPU time 0.88 seconds
Started Jun 05 05:18:29 PM PDT 24
Finished Jun 05 05:18:31 PM PDT 24
Peak memory 204616 kb
Host smart-a40e2f5d-bb18-42a8-9045-8d82c1f74106
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4123449883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.4123449883
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.4095395853
Short name T2071
Test name
Test status
Simulation time 64076610 ps
CPU time 1.43 seconds
Started Jun 05 05:18:30 PM PDT 24
Finished Jun 05 05:18:32 PM PDT 24
Peak memory 213076 kb
Host smart-21347f81-943a-49f9-a60b-ca32841d59a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095395853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.4095395853
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2064194205
Short name T2098
Test name
Test status
Simulation time 83603415 ps
CPU time 0.86 seconds
Started Jun 05 05:18:28 PM PDT 24
Finished Jun 05 05:18:30 PM PDT 24
Peak memory 204604 kb
Host smart-8d5b7ec1-2e24-48c0-9650-029acd36b8cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2064194205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2064194205
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2554014014
Short name T2085
Test name
Test status
Simulation time 44289179 ps
CPU time 0.66 seconds
Started Jun 05 05:18:29 PM PDT 24
Finished Jun 05 05:18:30 PM PDT 24
Peak memory 204544 kb
Host smart-f5f12451-2ce6-4576-824b-2bdff1a49780
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2554014014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.2554014014
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2197931754
Short name T246
Test name
Test status
Simulation time 237687997 ps
CPU time 2.35 seconds
Started Jun 05 05:18:31 PM PDT 24
Finished Jun 05 05:18:34 PM PDT 24
Peak memory 212964 kb
Host smart-4909b283-1d0a-4dd4-b44f-58ca3359a080
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2197931754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2197931754
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2985542700
Short name T2065
Test name
Test status
Simulation time 102493543 ps
CPU time 2.27 seconds
Started Jun 05 05:18:30 PM PDT 24
Finished Jun 05 05:18:32 PM PDT 24
Peak memory 204772 kb
Host smart-6e75a036-3485-4b90-9363-e9f5c0b07b11
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2985542700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2985542700
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.770858703
Short name T267
Test name
Test status
Simulation time 110792432 ps
CPU time 1.16 seconds
Started Jun 05 05:18:29 PM PDT 24
Finished Jun 05 05:18:31 PM PDT 24
Peak memory 204816 kb
Host smart-a637225a-3b72-4a9f-9386-47f41cb9ce37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=770858703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.770858703
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3055535019
Short name T2103
Test name
Test status
Simulation time 343403843 ps
CPU time 3.61 seconds
Started Jun 05 05:18:31 PM PDT 24
Finished Jun 05 05:18:36 PM PDT 24
Peak memory 220508 kb
Host smart-0f6a7747-ad32-4005-86a6-727008d4afb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3055535019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3055535019
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.222034377
Short name T2061
Test name
Test status
Simulation time 732031438 ps
CPU time 3.45 seconds
Started Jun 05 05:18:29 PM PDT 24
Finished Jun 05 05:18:33 PM PDT 24
Peak memory 204856 kb
Host smart-6d3baa28-5574-4173-8115-f37d94521111
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=222034377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.222034377
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.606725176
Short name T2073
Test name
Test status
Simulation time 49207366 ps
CPU time 0.65 seconds
Started Jun 05 05:19:09 PM PDT 24
Finished Jun 05 05:19:10 PM PDT 24
Peak memory 204536 kb
Host smart-2b2bcd68-7d32-4976-be5e-0efea96339e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=606725176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.606725176
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1532333235
Short name T190
Test name
Test status
Simulation time 44093588 ps
CPU time 0.68 seconds
Started Jun 05 05:19:11 PM PDT 24
Finished Jun 05 05:19:13 PM PDT 24
Peak memory 204552 kb
Host smart-bbaee318-c91e-41ac-ae60-789a39bfda32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1532333235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.1532333235
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2862284386
Short name T278
Test name
Test status
Simulation time 72265148 ps
CPU time 0.68 seconds
Started Jun 05 05:19:09 PM PDT 24
Finished Jun 05 05:19:10 PM PDT 24
Peak memory 204556 kb
Host smart-f8c99db2-ca6d-4f4a-af82-236a7e5ff9a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2862284386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2862284386
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.701809668
Short name T2069
Test name
Test status
Simulation time 90841805 ps
CPU time 0.77 seconds
Started Jun 05 05:19:17 PM PDT 24
Finished Jun 05 05:19:19 PM PDT 24
Peak memory 204460 kb
Host smart-1b85e3d2-cfcb-4150-8056-67af382281be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=701809668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.701809668
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3711493721
Short name T2135
Test name
Test status
Simulation time 59784583 ps
CPU time 0.7 seconds
Started Jun 05 05:19:17 PM PDT 24
Finished Jun 05 05:19:19 PM PDT 24
Peak memory 204740 kb
Host smart-5007d29b-68ec-45cc-ab72-a10fb1d29168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3711493721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3711493721
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1057085061
Short name T274
Test name
Test status
Simulation time 42004360 ps
CPU time 0.7 seconds
Started Jun 05 05:19:17 PM PDT 24
Finished Jun 05 05:19:18 PM PDT 24
Peak memory 204588 kb
Host smart-af08510f-fa73-4879-ae3a-9da0989da3cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1057085061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1057085061
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2122149367
Short name T2088
Test name
Test status
Simulation time 34802095 ps
CPU time 0.69 seconds
Started Jun 05 05:19:14 PM PDT 24
Finished Jun 05 05:19:16 PM PDT 24
Peak memory 204584 kb
Host smart-e982380b-f6d6-4135-a33e-78d52eb45d67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2122149367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2122149367
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3984106913
Short name T191
Test name
Test status
Simulation time 91141108 ps
CPU time 0.71 seconds
Started Jun 05 05:19:18 PM PDT 24
Finished Jun 05 05:19:21 PM PDT 24
Peak memory 204548 kb
Host smart-0379dee3-46ab-4368-9d5b-0501705600f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3984106913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3984106913
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3553122942
Short name T276
Test name
Test status
Simulation time 88995817 ps
CPU time 0.78 seconds
Started Jun 05 05:19:17 PM PDT 24
Finished Jun 05 05:19:20 PM PDT 24
Peak memory 204584 kb
Host smart-65ccb6a2-02db-4509-95b6-eb6c6b0afa91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3553122942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3553122942
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.4113044957
Short name T2068
Test name
Test status
Simulation time 75711736 ps
CPU time 1.85 seconds
Started Jun 05 05:18:39 PM PDT 24
Finished Jun 05 05:18:42 PM PDT 24
Peak memory 204828 kb
Host smart-cb8cc92a-1e72-4c00-9e53-490f453bde64
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4113044957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.4113044957
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3664838965
Short name T2111
Test name
Test status
Simulation time 731581623 ps
CPU time 4.28 seconds
Started Jun 05 05:18:46 PM PDT 24
Finished Jun 05 05:18:51 PM PDT 24
Peak memory 204776 kb
Host smart-410f9002-1c06-4d99-833b-0123e6e5f291
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3664838965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3664838965
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.4080092692
Short name T2053
Test name
Test status
Simulation time 101921722 ps
CPU time 0.97 seconds
Started Jun 05 05:18:39 PM PDT 24
Finished Jun 05 05:18:41 PM PDT 24
Peak memory 204604 kb
Host smart-e630ce32-eea0-46a4-bc2d-e19064a722dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4080092692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.4080092692
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2322418936
Short name T217
Test name
Test status
Simulation time 105776690 ps
CPU time 2.73 seconds
Started Jun 05 05:18:43 PM PDT 24
Finished Jun 05 05:18:47 PM PDT 24
Peak memory 213040 kb
Host smart-0f965cbc-617b-45df-abdc-a7f708430093
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322418936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.2322418936
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.840761381
Short name T254
Test name
Test status
Simulation time 47277201 ps
CPU time 0.81 seconds
Started Jun 05 05:18:36 PM PDT 24
Finished Jun 05 05:18:37 PM PDT 24
Peak memory 204600 kb
Host smart-77205deb-7a8f-4c68-ac3f-4f95f82a0b80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=840761381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.840761381
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.888934180
Short name T2127
Test name
Test status
Simulation time 104637316 ps
CPU time 1.42 seconds
Started Jun 05 05:18:38 PM PDT 24
Finished Jun 05 05:18:41 PM PDT 24
Peak memory 213100 kb
Host smart-6a99b0ce-ff3a-4d6c-9a13-89e12b6d2aaf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=888934180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.888934180
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1232203161
Short name T2039
Test name
Test status
Simulation time 499164254 ps
CPU time 4.2 seconds
Started Jun 05 05:18:37 PM PDT 24
Finished Jun 05 05:18:42 PM PDT 24
Peak memory 204828 kb
Host smart-9f8fd2c1-f859-4459-9d4f-aca33c46ef55
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1232203161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1232203161
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2424480734
Short name T251
Test name
Test status
Simulation time 192991483 ps
CPU time 1.64 seconds
Started Jun 05 05:18:38 PM PDT 24
Finished Jun 05 05:18:40 PM PDT 24
Peak memory 204828 kb
Host smart-cf7c5852-3ab4-46de-9a57-063b156b6f7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2424480734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2424480734
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.424578317
Short name T2133
Test name
Test status
Simulation time 119146616 ps
CPU time 1.49 seconds
Started Jun 05 05:18:29 PM PDT 24
Finished Jun 05 05:18:31 PM PDT 24
Peak memory 213016 kb
Host smart-69c6af55-5265-4e89-8ac1-680d70097f23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=424578317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.424578317
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1374839082
Short name T2072
Test name
Test status
Simulation time 57670643 ps
CPU time 0.69 seconds
Started Jun 05 05:19:17 PM PDT 24
Finished Jun 05 05:19:20 PM PDT 24
Peak memory 204560 kb
Host smart-9a0736cc-398a-4a1a-a9e2-19fe5d7f205c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1374839082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.1374839082
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.190581767
Short name T2051
Test name
Test status
Simulation time 87247670 ps
CPU time 0.71 seconds
Started Jun 05 05:19:18 PM PDT 24
Finished Jun 05 05:19:21 PM PDT 24
Peak memory 204568 kb
Host smart-f471f776-4c9c-4359-b558-9e484636b84a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=190581767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.190581767
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1819041011
Short name T2059
Test name
Test status
Simulation time 42462411 ps
CPU time 0.69 seconds
Started Jun 05 05:19:18 PM PDT 24
Finished Jun 05 05:19:20 PM PDT 24
Peak memory 204584 kb
Host smart-394d914d-75e6-4234-bb22-7e2cb8fdc8f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1819041011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1819041011
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.831923524
Short name T2090
Test name
Test status
Simulation time 69408028 ps
CPU time 0.73 seconds
Started Jun 05 05:19:17 PM PDT 24
Finished Jun 05 05:19:18 PM PDT 24
Peak memory 204556 kb
Host smart-5de56f44-62e7-4a68-bfda-a5ee27dc509d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=831923524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.831923524
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3912436874
Short name T2064
Test name
Test status
Simulation time 40910096 ps
CPU time 0.7 seconds
Started Jun 05 05:19:17 PM PDT 24
Finished Jun 05 05:19:19 PM PDT 24
Peak memory 204608 kb
Host smart-ba5a6dce-e038-4f7a-b680-48656985857c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3912436874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3912436874
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3458008340
Short name T93
Test name
Test status
Simulation time 58401431 ps
CPU time 0.7 seconds
Started Jun 05 05:19:16 PM PDT 24
Finished Jun 05 05:19:17 PM PDT 24
Peak memory 204560 kb
Host smart-5a6753d3-fae9-4ad5-813f-ea30379d8385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3458008340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.3458008340
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2270494943
Short name T2130
Test name
Test status
Simulation time 56846873 ps
CPU time 0.72 seconds
Started Jun 05 05:19:17 PM PDT 24
Finished Jun 05 05:19:18 PM PDT 24
Peak memory 204764 kb
Host smart-08874cad-5b13-412d-9a85-f17699e389f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2270494943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2270494943
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1668144731
Short name T2052
Test name
Test status
Simulation time 58498253 ps
CPU time 0.69 seconds
Started Jun 05 05:19:18 PM PDT 24
Finished Jun 05 05:19:21 PM PDT 24
Peak memory 204552 kb
Host smart-cb358756-3585-47ea-962a-6814e0df45ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1668144731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1668144731
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1634389571
Short name T272
Test name
Test status
Simulation time 58731061 ps
CPU time 0.76 seconds
Started Jun 05 05:19:17 PM PDT 24
Finished Jun 05 05:19:18 PM PDT 24
Peak memory 204584 kb
Host smart-20148315-a40c-4dc0-b987-f8939db82828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1634389571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.1634389571
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.4235155044
Short name T2066
Test name
Test status
Simulation time 35594844 ps
CPU time 0.65 seconds
Started Jun 05 05:19:17 PM PDT 24
Finished Jun 05 05:19:18 PM PDT 24
Peak memory 204596 kb
Host smart-a7a9830a-0ff2-4973-8903-88c446f91f0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4235155044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.4235155044
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2362535462
Short name T221
Test name
Test status
Simulation time 79783774 ps
CPU time 1.21 seconds
Started Jun 05 05:18:37 PM PDT 24
Finished Jun 05 05:18:38 PM PDT 24
Peak memory 213056 kb
Host smart-c3c1e216-43cc-4309-b239-0d75d3747732
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362535462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.2362535462
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2989019728
Short name T2044
Test name
Test status
Simulation time 49441032 ps
CPU time 0.79 seconds
Started Jun 05 05:18:40 PM PDT 24
Finished Jun 05 05:18:43 PM PDT 24
Peak memory 204592 kb
Host smart-277c54c1-3c76-4744-b237-61ea96099085
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2989019728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.2989019728
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1188733152
Short name T2129
Test name
Test status
Simulation time 47953779 ps
CPU time 0.68 seconds
Started Jun 05 05:18:39 PM PDT 24
Finished Jun 05 05:18:42 PM PDT 24
Peak memory 204572 kb
Host smart-eaa93ed0-6cc1-4195-9ae7-1f2bd668826e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1188733152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1188733152
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3458809455
Short name T2122
Test name
Test status
Simulation time 247267040 ps
CPU time 1.52 seconds
Started Jun 05 05:18:37 PM PDT 24
Finished Jun 05 05:18:39 PM PDT 24
Peak memory 204756 kb
Host smart-ed61f597-b0ab-4746-b716-1b1de4a20b32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3458809455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.3458809455
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1769078066
Short name T210
Test name
Test status
Simulation time 140155300 ps
CPU time 1.68 seconds
Started Jun 05 05:18:46 PM PDT 24
Finished Jun 05 05:18:49 PM PDT 24
Peak memory 213016 kb
Host smart-8c9c6446-8278-4478-b695-45546ac426f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1769078066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1769078066
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3567327795
Short name T286
Test name
Test status
Simulation time 407401403 ps
CPU time 2.69 seconds
Started Jun 05 05:18:40 PM PDT 24
Finished Jun 05 05:18:44 PM PDT 24
Peak memory 204860 kb
Host smart-a76e9149-93c9-472c-92e6-915aed85b844
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3567327795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3567327795
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3203934737
Short name T2060
Test name
Test status
Simulation time 169846303 ps
CPU time 1.92 seconds
Started Jun 05 05:18:41 PM PDT 24
Finished Jun 05 05:18:44 PM PDT 24
Peak memory 213016 kb
Host smart-66e50623-cc32-4a06-a7da-425f20b3ff8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203934737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.3203934737
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2166466057
Short name T2047
Test name
Test status
Simulation time 73694921 ps
CPU time 0.72 seconds
Started Jun 05 05:18:39 PM PDT 24
Finished Jun 05 05:18:41 PM PDT 24
Peak memory 204552 kb
Host smart-efc32f68-774c-413d-a398-7022e761b065
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2166466057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2166466057
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.695189080
Short name T2083
Test name
Test status
Simulation time 100194364 ps
CPU time 1.13 seconds
Started Jun 05 05:18:43 PM PDT 24
Finished Jun 05 05:18:45 PM PDT 24
Peak memory 204848 kb
Host smart-db23c096-2243-46d9-94ea-9f32dbcf4b5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=695189080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.695189080
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2099546861
Short name T2106
Test name
Test status
Simulation time 109991901 ps
CPU time 1.41 seconds
Started Jun 05 05:18:38 PM PDT 24
Finished Jun 05 05:18:40 PM PDT 24
Peak memory 204856 kb
Host smart-5c8b2721-f723-4996-b4f2-8227abe5f2bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2099546861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2099546861
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.332831189
Short name T2104
Test name
Test status
Simulation time 1029188876 ps
CPU time 3.91 seconds
Started Jun 05 05:18:39 PM PDT 24
Finished Jun 05 05:18:44 PM PDT 24
Peak memory 204768 kb
Host smart-2a992638-7ac7-47e0-9193-d609ac655435
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=332831189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.332831189
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3019329720
Short name T2099
Test name
Test status
Simulation time 148766799 ps
CPU time 1.2 seconds
Started Jun 05 05:18:37 PM PDT 24
Finished Jun 05 05:18:39 PM PDT 24
Peak memory 212920 kb
Host smart-9d888f7f-7113-4dc5-a50e-5c5a7208453e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019329720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.3019329720
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3608492549
Short name T2105
Test name
Test status
Simulation time 85290554 ps
CPU time 1.02 seconds
Started Jun 05 05:18:37 PM PDT 24
Finished Jun 05 05:18:39 PM PDT 24
Peak memory 204784 kb
Host smart-e7c4b12a-ad1e-4cda-8af3-1bb587b1b2ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3608492549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3608492549
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.4075022840
Short name T92
Test name
Test status
Simulation time 38055516 ps
CPU time 0.65 seconds
Started Jun 05 05:18:46 PM PDT 24
Finished Jun 05 05:18:48 PM PDT 24
Peak memory 204564 kb
Host smart-ae551b0e-8d11-4e6a-bd6f-0f4c9215f3da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4075022840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.4075022840
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.875499504
Short name T2076
Test name
Test status
Simulation time 67648838 ps
CPU time 1.06 seconds
Started Jun 05 05:18:39 PM PDT 24
Finished Jun 05 05:18:41 PM PDT 24
Peak memory 204844 kb
Host smart-f083c274-75c6-4dfd-8182-52a1b2313193
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=875499504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.875499504
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2575197997
Short name T2078
Test name
Test status
Simulation time 199804035 ps
CPU time 2.3 seconds
Started Jun 05 05:18:39 PM PDT 24
Finished Jun 05 05:18:43 PM PDT 24
Peak memory 213040 kb
Host smart-04245ad8-a0b6-448d-8913-a97292eeb01b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2575197997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2575197997
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1734899664
Short name T285
Test name
Test status
Simulation time 644604518 ps
CPU time 4.59 seconds
Started Jun 05 05:18:37 PM PDT 24
Finished Jun 05 05:18:42 PM PDT 24
Peak memory 204772 kb
Host smart-0ed63f58-5a8a-43e2-a22b-f8fdba05970c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1734899664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1734899664
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2037653497
Short name T2058
Test name
Test status
Simulation time 217271644 ps
CPU time 1.97 seconds
Started Jun 05 05:18:52 PM PDT 24
Finished Jun 05 05:18:55 PM PDT 24
Peak memory 217448 kb
Host smart-4f884898-8408-46f2-bf47-9d4b7584afbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037653497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2037653497
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.958833650
Short name T250
Test name
Test status
Simulation time 131330211 ps
CPU time 1.12 seconds
Started Jun 05 05:18:49 PM PDT 24
Finished Jun 05 05:18:50 PM PDT 24
Peak memory 204772 kb
Host smart-50444087-7d67-46ac-9d37-21505001e309
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=958833650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.958833650
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.307502563
Short name T2109
Test name
Test status
Simulation time 52135351 ps
CPU time 0.69 seconds
Started Jun 05 05:18:46 PM PDT 24
Finished Jun 05 05:18:48 PM PDT 24
Peak memory 204572 kb
Host smart-5f00268d-8f8a-4abb-b814-199e3b9cced1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=307502563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.307502563
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2653545693
Short name T2050
Test name
Test status
Simulation time 205380762 ps
CPU time 1.87 seconds
Started Jun 05 05:18:43 PM PDT 24
Finished Jun 05 05:18:46 PM PDT 24
Peak memory 204720 kb
Host smart-fdf35bc4-3966-429f-a481-0bd39b126349
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2653545693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.2653545693
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.524563356
Short name T213
Test name
Test status
Simulation time 186253460 ps
CPU time 2.1 seconds
Started Jun 05 05:18:46 PM PDT 24
Finished Jun 05 05:18:49 PM PDT 24
Peak memory 204896 kb
Host smart-bce1de49-80d0-4f1e-a37a-0d15b66ec494
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=524563356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.524563356
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2938742881
Short name T2117
Test name
Test status
Simulation time 1779562586 ps
CPU time 5.94 seconds
Started Jun 05 05:18:47 PM PDT 24
Finished Jun 05 05:18:54 PM PDT 24
Peak memory 204792 kb
Host smart-2b6950db-58c2-4817-8a9a-fde40fc557d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2938742881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.2938742881
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1255033489
Short name T218
Test name
Test status
Simulation time 179817120 ps
CPU time 2.03 seconds
Started Jun 05 05:18:52 PM PDT 24
Finished Jun 05 05:18:55 PM PDT 24
Peak memory 212872 kb
Host smart-4354cdf9-76ff-4414-9e0a-e2481f258563
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255033489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.1255033489
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1090428950
Short name T264
Test name
Test status
Simulation time 66398728 ps
CPU time 0.91 seconds
Started Jun 05 05:18:45 PM PDT 24
Finished Jun 05 05:18:47 PM PDT 24
Peak memory 204788 kb
Host smart-d943d0b9-8034-4b7d-9696-79b902a458b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1090428950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1090428950
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.662033023
Short name T2116
Test name
Test status
Simulation time 68698335 ps
CPU time 0.72 seconds
Started Jun 05 05:18:47 PM PDT 24
Finished Jun 05 05:18:49 PM PDT 24
Peak memory 204568 kb
Host smart-dda0b78f-4d94-4c4f-b166-bc1c5b7beef2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=662033023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.662033023
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1465835849
Short name T2092
Test name
Test status
Simulation time 175881102 ps
CPU time 1.2 seconds
Started Jun 05 05:18:43 PM PDT 24
Finished Jun 05 05:18:46 PM PDT 24
Peak memory 204788 kb
Host smart-586b2180-f5c2-452f-b5a8-ecc5f25377da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1465835849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1465835849
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.306745094
Short name T205
Test name
Test status
Simulation time 332364954 ps
CPU time 3.1 seconds
Started Jun 05 05:18:45 PM PDT 24
Finished Jun 05 05:18:49 PM PDT 24
Peak memory 220552 kb
Host smart-81bee6a9-dc53-45f4-948f-4024cb79c1aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=306745094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.306745094
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.8503015
Short name T2114
Test name
Test status
Simulation time 1659460063 ps
CPU time 5.97 seconds
Started Jun 05 05:18:46 PM PDT 24
Finished Jun 05 05:18:53 PM PDT 24
Peak memory 204728 kb
Host smart-f06bd1cc-0397-46fd-ba98-7ac47a943e8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=8503015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.8503015
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.2914818805
Short name T387
Test name
Test status
Simulation time 10179496311 ps
CPU time 13.48 seconds
Started Jun 05 05:44:08 PM PDT 24
Finished Jun 05 05:44:22 PM PDT 24
Peak memory 205648 kb
Host smart-1c9961af-7b19-4450-9a96-b5940a97062c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2914818805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.2914818805
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.2772040238
Short name T1685
Test name
Test status
Simulation time 10072249085 ps
CPU time 13.83 seconds
Started Jun 05 05:44:17 PM PDT 24
Finished Jun 05 05:44:31 PM PDT 24
Peak memory 205548 kb
Host smart-0edfaa7b-c498-4218-8557-14c5e665b44c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2772040238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.2772040238
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.1209818763
Short name T841
Test name
Test status
Simulation time 10079325042 ps
CPU time 13.58 seconds
Started Jun 05 05:44:10 PM PDT 24
Finished Jun 05 05:44:24 PM PDT 24
Peak memory 205976 kb
Host smart-e02f4568-536e-43b6-8468-f24bfae7d536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12098
18763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.1209818763
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.1285111221
Short name T1101
Test name
Test status
Simulation time 13804391495 ps
CPU time 17.25 seconds
Started Jun 05 05:44:01 PM PDT 24
Finished Jun 05 05:44:19 PM PDT 24
Peak memory 205712 kb
Host smart-7b03a59e-7ff6-497b-8f74-fe544d36f2c8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1285111221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.1285111221
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.904648883
Short name T906
Test name
Test status
Simulation time 23307012425 ps
CPU time 28.95 seconds
Started Jun 05 05:44:03 PM PDT 24
Finished Jun 05 05:44:33 PM PDT 24
Peak memory 205776 kb
Host smart-2228b366-4320-4bfa-801f-2bf253617f46
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=904648883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.904648883
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.277909182
Short name T1781
Test name
Test status
Simulation time 10058995330 ps
CPU time 15.89 seconds
Started Jun 05 05:44:00 PM PDT 24
Finished Jun 05 05:44:16 PM PDT 24
Peak memory 205712 kb
Host smart-99dec809-99a5-49db-b1bb-3dc3ce88876a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27790
9182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.277909182
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.3213895675
Short name T1869
Test name
Test status
Simulation time 10553917592 ps
CPU time 14.95 seconds
Started Jun 05 05:44:02 PM PDT 24
Finished Jun 05 05:44:17 PM PDT 24
Peak memory 205708 kb
Host smart-8a43f158-c5f9-498b-b3df-ebbc02829760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32138
95675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.3213895675
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.849490498
Short name T404
Test name
Test status
Simulation time 10047174381 ps
CPU time 14.4 seconds
Started Jun 05 05:44:02 PM PDT 24
Finished Jun 05 05:44:17 PM PDT 24
Peak memory 205668 kb
Host smart-e2e5b08b-c6d4-4570-a5a8-ec20c0380d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84949
0498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.849490498
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.1889336341
Short name T1427
Test name
Test status
Simulation time 10066980203 ps
CPU time 13.01 seconds
Started Jun 05 05:44:03 PM PDT 24
Finished Jun 05 05:44:17 PM PDT 24
Peak memory 205656 kb
Host smart-b9be74c0-e91c-47d8-82e9-986a73965dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18893
36341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1889336341
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.3468230034
Short name T716
Test name
Test status
Simulation time 10792032250 ps
CPU time 18.09 seconds
Started Jun 05 05:44:01 PM PDT 24
Finished Jun 05 05:44:20 PM PDT 24
Peak memory 205708 kb
Host smart-472b132e-64ca-4ea6-a5cc-412af2f01d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34682
30034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3468230034
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.2434405816
Short name T1494
Test name
Test status
Simulation time 10355974789 ps
CPU time 14.27 seconds
Started Jun 05 05:44:03 PM PDT 24
Finished Jun 05 05:44:18 PM PDT 24
Peak memory 205768 kb
Host smart-63f5f032-7d8f-43fb-87eb-f33a1254d2d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24344
05816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.2434405816
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.3327367962
Short name T1822
Test name
Test status
Simulation time 10095694671 ps
CPU time 16.24 seconds
Started Jun 05 05:44:16 PM PDT 24
Finished Jun 05 05:44:33 PM PDT 24
Peak memory 205616 kb
Host smart-22c57fed-d3fc-41d4-bc26-8097b4dd3498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33273
67962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.3327367962
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2794044677
Short name T2021
Test name
Test status
Simulation time 10115210264 ps
CPU time 15.1 seconds
Started Jun 05 05:44:15 PM PDT 24
Finished Jun 05 05:44:31 PM PDT 24
Peak memory 205712 kb
Host smart-763905a9-2fd2-4717-b7cd-409f2d206ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27940
44677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2794044677
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2111935103
Short name T1526
Test name
Test status
Simulation time 10061611606 ps
CPU time 15.29 seconds
Started Jun 05 05:44:00 PM PDT 24
Finished Jun 05 05:44:16 PM PDT 24
Peak memory 205648 kb
Host smart-8ece3a36-519c-4341-a4b9-6462ba55b745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21119
35103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2111935103
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.3756199339
Short name T1838
Test name
Test status
Simulation time 10064416823 ps
CPU time 13.36 seconds
Started Jun 05 05:44:05 PM PDT 24
Finished Jun 05 05:44:19 PM PDT 24
Peak memory 205720 kb
Host smart-4b7c6d32-aa0c-4c39-a5d2-4dffd45128ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37561
99339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.3756199339
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.1325591468
Short name T388
Test name
Test status
Simulation time 13167059589 ps
CPU time 15.77 seconds
Started Jun 05 05:44:02 PM PDT 24
Finished Jun 05 05:44:19 PM PDT 24
Peak memory 205728 kb
Host smart-709d0f2e-ac70-4296-9f49-1c8e672e3c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13255
91468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.1325591468
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.1454634984
Short name T641
Test name
Test status
Simulation time 10088028777 ps
CPU time 15.55 seconds
Started Jun 05 05:44:01 PM PDT 24
Finished Jun 05 05:44:17 PM PDT 24
Peak memory 205716 kb
Host smart-c2922523-b9ef-4104-a461-e57df5ddbbc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14546
34984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.1454634984
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.2939420161
Short name T1295
Test name
Test status
Simulation time 23052138627 ps
CPU time 140.95 seconds
Started Jun 05 05:43:59 PM PDT 24
Finished Jun 05 05:46:20 PM PDT 24
Peak memory 205692 kb
Host smart-977faf0d-7f5b-46cc-8486-0597ccc035bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29394
20161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.2939420161
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.934572429
Short name T307
Test name
Test status
Simulation time 10114482441 ps
CPU time 15.43 seconds
Started Jun 05 05:44:01 PM PDT 24
Finished Jun 05 05:44:17 PM PDT 24
Peak memory 205736 kb
Host smart-76676f7a-bf69-4575-87e4-c6a7a3f40642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93457
2429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.934572429
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.4266935873
Short name T556
Test name
Test status
Simulation time 10108247357 ps
CPU time 13.49 seconds
Started Jun 05 05:44:03 PM PDT 24
Finished Jun 05 05:44:17 PM PDT 24
Peak memory 205756 kb
Host smart-631a6d99-8c9f-48b9-b78e-ebd6b9ccd18b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42669
35873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.4266935873
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3250225647
Short name T1947
Test name
Test status
Simulation time 10094784431 ps
CPU time 13.95 seconds
Started Jun 05 05:44:03 PM PDT 24
Finished Jun 05 05:44:18 PM PDT 24
Peak memory 205736 kb
Host smart-58cd6323-f2f1-4360-895f-27d66923845c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32502
25647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3250225647
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.799286903
Short name T539
Test name
Test status
Simulation time 10069083311 ps
CPU time 13.13 seconds
Started Jun 05 05:44:04 PM PDT 24
Finished Jun 05 05:44:18 PM PDT 24
Peak memory 205656 kb
Host smart-c4d696fd-f66e-4e0b-b154-a0dbb0d05bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79928
6903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.799286903
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.70073189
Short name T847
Test name
Test status
Simulation time 10081597862 ps
CPU time 14.2 seconds
Started Jun 05 05:44:10 PM PDT 24
Finished Jun 05 05:44:25 PM PDT 24
Peak memory 205712 kb
Host smart-d5a59daa-1b91-4cc6-b458-b34945cacc96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70073
189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.70073189
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2614665870
Short name T1584
Test name
Test status
Simulation time 10055538313 ps
CPU time 15.57 seconds
Started Jun 05 05:44:09 PM PDT 24
Finished Jun 05 05:44:25 PM PDT 24
Peak memory 205952 kb
Host smart-f0640e68-afb8-4db8-a6fa-bdaac621a4bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26146
65870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.2614665870
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.3084126252
Short name T39
Test name
Test status
Simulation time 10040939609 ps
CPU time 13.61 seconds
Started Jun 05 05:44:12 PM PDT 24
Finished Jun 05 05:44:26 PM PDT 24
Peak memory 205672 kb
Host smart-ff3213a0-66c3-4992-9c17-a1ad5968e176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30841
26252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.3084126252
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1906200542
Short name T502
Test name
Test status
Simulation time 10069666533 ps
CPU time 12.87 seconds
Started Jun 05 05:44:02 PM PDT 24
Finished Jun 05 05:44:16 PM PDT 24
Peak memory 205648 kb
Host smart-7633e89c-44b6-4484-a3d6-d28cf2bad833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19062
00542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1906200542
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.12083020
Short name T1384
Test name
Test status
Simulation time 10124240866 ps
CPU time 16.85 seconds
Started Jun 05 05:44:03 PM PDT 24
Finished Jun 05 05:44:21 PM PDT 24
Peak memory 205728 kb
Host smart-dcf34f34-70f0-4e23-93db-be883346cda2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12083
020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.12083020
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.4181262159
Short name T156
Test name
Test status
Simulation time 40666422434 ps
CPU time 804.75 seconds
Started Jun 05 05:44:03 PM PDT 24
Finished Jun 05 05:57:29 PM PDT 24
Peak memory 205768 kb
Host smart-32631d41-9e30-4373-b9bf-bdfb7460b53d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4181262159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.4181262159
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.3821045005
Short name T159
Test name
Test status
Simulation time 18724401187 ps
CPU time 74.08 seconds
Started Jun 05 05:44:04 PM PDT 24
Finished Jun 05 05:45:18 PM PDT 24
Peak memory 205588 kb
Host smart-e1c475ab-f10a-4473-805b-e92a70848d45
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3821045005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.3821045005
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.3497311651
Short name T1747
Test name
Test status
Simulation time 53492621042 ps
CPU time 402.1 seconds
Started Jun 05 05:44:03 PM PDT 24
Finished Jun 05 05:50:46 PM PDT 24
Peak memory 205788 kb
Host smart-f7c6b2f4-d08a-4d91-8fee-9ab784e123d1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3497311651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.3497311651
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.2545270280
Short name T622
Test name
Test status
Simulation time 10073904966 ps
CPU time 13.47 seconds
Started Jun 05 05:44:02 PM PDT 24
Finished Jun 05 05:44:16 PM PDT 24
Peak memory 205680 kb
Host smart-fcc1f315-1bdf-4cba-83c8-ffbe0086151c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25452
70280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.2545270280
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.1088022053
Short name T194
Test name
Test status
Simulation time 597809170 ps
CPU time 1.47 seconds
Started Jun 05 05:44:07 PM PDT 24
Finished Jun 05 05:44:09 PM PDT 24
Peak memory 222808 kb
Host smart-fdda00af-d9b4-44dd-a280-74eb942925f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1088022053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1088022053
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1508063821
Short name T1275
Test name
Test status
Simulation time 10057273338 ps
CPU time 13.88 seconds
Started Jun 05 05:44:09 PM PDT 24
Finished Jun 05 05:44:24 PM PDT 24
Peak memory 205728 kb
Host smart-1496262b-6f11-4f6a-8784-850fcc5a2a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15080
63821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1508063821
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.4123740491
Short name T987
Test name
Test status
Simulation time 10085474196 ps
CPU time 14.52 seconds
Started Jun 05 05:44:09 PM PDT 24
Finished Jun 05 05:44:24 PM PDT 24
Peak memory 205768 kb
Host smart-c502f151-72a1-4362-b08c-faf767e7a7e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41237
40491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.4123740491
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.4186297745
Short name T1037
Test name
Test status
Simulation time 10074946104 ps
CPU time 13.2 seconds
Started Jun 05 05:44:03 PM PDT 24
Finished Jun 05 05:44:17 PM PDT 24
Peak memory 205616 kb
Host smart-88c66ebb-2b93-4f73-b92d-70cfd726c771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41862
97745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.4186297745
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.3633057508
Short name T1056
Test name
Test status
Simulation time 21260430623 ps
CPU time 118.28 seconds
Started Jun 05 05:44:02 PM PDT 24
Finished Jun 05 05:46:01 PM PDT 24
Peak memory 205664 kb
Host smart-087a0c04-fcfb-4d01-9aaf-ef48ab23a264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36330
57508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.3633057508
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.1420478589
Short name T1580
Test name
Test status
Simulation time 35074320117 ps
CPU time 210.28 seconds
Started Jun 05 05:44:05 PM PDT 24
Finished Jun 05 05:47:36 PM PDT 24
Peak memory 205800 kb
Host smart-0a53fe15-0f21-47c1-a5fe-397b3567e2b2
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420478589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_
traffic.1420478589
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.3248695160
Short name T1860
Test name
Test status
Simulation time 10137853299 ps
CPU time 13.63 seconds
Started Jun 05 05:44:30 PM PDT 24
Finished Jun 05 05:44:44 PM PDT 24
Peak memory 205716 kb
Host smart-1a9cc6f0-e529-4044-9c91-4548a943fbec
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3248695160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.3248695160
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.1842154336
Short name T1876
Test name
Test status
Simulation time 10066928252 ps
CPU time 13.2 seconds
Started Jun 05 05:44:16 PM PDT 24
Finished Jun 05 05:44:30 PM PDT 24
Peak memory 205764 kb
Host smart-8132b59b-d879-486c-a27b-2cd1a1471837
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1842154336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.1842154336
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.100042246
Short name T1523
Test name
Test status
Simulation time 10109240375 ps
CPU time 12.64 seconds
Started Jun 05 05:44:21 PM PDT 24
Finished Jun 05 05:44:34 PM PDT 24
Peak memory 205720 kb
Host smart-b4e9b2f8-aa95-40b2-9d6b-07415c36f41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10004
2246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.100042246
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.2526060788
Short name T497
Test name
Test status
Simulation time 13372688131 ps
CPU time 16.84 seconds
Started Jun 05 05:44:16 PM PDT 24
Finished Jun 05 05:44:33 PM PDT 24
Peak memory 205644 kb
Host smart-3a96be1c-05cf-4f35-9aa1-8b04fd14cc97
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2526060788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.2526060788
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.1298843317
Short name T1389
Test name
Test status
Simulation time 23314813016 ps
CPU time 24.67 seconds
Started Jun 05 05:44:14 PM PDT 24
Finished Jun 05 05:44:39 PM PDT 24
Peak memory 205816 kb
Host smart-e4fd30d4-17fc-44ff-8eec-82fdb804fbd7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1298843317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.1298843317
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.2897779292
Short name T465
Test name
Test status
Simulation time 10051547554 ps
CPU time 13.75 seconds
Started Jun 05 05:44:09 PM PDT 24
Finished Jun 05 05:44:24 PM PDT 24
Peak memory 205600 kb
Host smart-656aa512-4636-4ea1-ba56-635c497bd659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28977
79292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2897779292
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.1996838068
Short name T827
Test name
Test status
Simulation time 10079611861 ps
CPU time 12.64 seconds
Started Jun 05 05:44:07 PM PDT 24
Finished Jun 05 05:44:21 PM PDT 24
Peak memory 205752 kb
Host smart-545e5202-f1be-4035-89d6-a4f27cd9a919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19968
38068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.1996838068
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.4157689383
Short name T1132
Test name
Test status
Simulation time 10691490728 ps
CPU time 15.24 seconds
Started Jun 05 05:44:09 PM PDT 24
Finished Jun 05 05:44:25 PM PDT 24
Peak memory 205520 kb
Host smart-7bdc12c7-fbcd-4412-802a-06c5441060f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41576
89383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.4157689383
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_enable.2375916571
Short name T1400
Test name
Test status
Simulation time 10059288351 ps
CPU time 13.08 seconds
Started Jun 05 05:44:09 PM PDT 24
Finished Jun 05 05:44:22 PM PDT 24
Peak memory 205732 kb
Host smart-5339e87f-65db-4d6e-92d0-d7e844b71619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23759
16571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.2375916571
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.2039148178
Short name T919
Test name
Test status
Simulation time 10831614612 ps
CPU time 15.3 seconds
Started Jun 05 05:44:09 PM PDT 24
Finished Jun 05 05:44:25 PM PDT 24
Peak memory 205736 kb
Host smart-0188954d-63ed-44ed-85f7-6b7656177e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20391
48178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.2039148178
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.4221226031
Short name T952
Test name
Test status
Simulation time 10188851180 ps
CPU time 14.7 seconds
Started Jun 05 05:44:10 PM PDT 24
Finished Jun 05 05:44:25 PM PDT 24
Peak memory 205788 kb
Host smart-7dabd350-babe-406b-94a6-32744b6b01ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42212
26031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.4221226031
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2419105177
Short name T1903
Test name
Test status
Simulation time 10093472162 ps
CPU time 14.06 seconds
Started Jun 05 05:44:18 PM PDT 24
Finished Jun 05 05:44:33 PM PDT 24
Peak memory 205648 kb
Host smart-2f9d3532-6ee0-4ec2-aced-49f5c76ae80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24191
05177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2419105177
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.1103351149
Short name T602
Test name
Test status
Simulation time 10041594994 ps
CPU time 15.42 seconds
Started Jun 05 05:44:28 PM PDT 24
Finished Jun 05 05:44:44 PM PDT 24
Peak memory 205680 kb
Host smart-a5ce34da-13b9-4351-9066-db3dc3d6290a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11033
51149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.1103351149
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.2033542773
Short name T1371
Test name
Test status
Simulation time 10162691171 ps
CPU time 15.71 seconds
Started Jun 05 05:44:20 PM PDT 24
Finished Jun 05 05:44:36 PM PDT 24
Peak memory 205740 kb
Host smart-bf7be2d2-6dae-4ea4-bade-379f3891d23c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20335
42773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.2033542773
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.388235116
Short name T1305
Test name
Test status
Simulation time 10078671218 ps
CPU time 13.83 seconds
Started Jun 05 05:44:15 PM PDT 24
Finished Jun 05 05:44:29 PM PDT 24
Peak memory 205732 kb
Host smart-fe0cd034-9bbf-4649-920d-b83767ad4fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38823
5116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.388235116
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.2779970261
Short name T384
Test name
Test status
Simulation time 13185297038 ps
CPU time 15.78 seconds
Started Jun 05 05:44:15 PM PDT 24
Finished Jun 05 05:44:31 PM PDT 24
Peak memory 205764 kb
Host smart-bf976ba0-39f1-4c13-8f9d-71c68f58b3ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27799
70261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.2779970261
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.1935304000
Short name T689
Test name
Test status
Simulation time 10115247153 ps
CPU time 13.74 seconds
Started Jun 05 05:44:14 PM PDT 24
Finished Jun 05 05:44:28 PM PDT 24
Peak memory 205716 kb
Host smart-e1cbff20-d07a-40cc-91db-a167d304aff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19353
04000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.1935304000
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.373508572
Short name T1239
Test name
Test status
Simulation time 18670187913 ps
CPU time 253.02 seconds
Started Jun 05 05:44:18 PM PDT 24
Finished Jun 05 05:48:32 PM PDT 24
Peak memory 205616 kb
Host smart-31d3b0ce-b634-4c65-9382-e57b7a2b9234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37350
8572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.373508572
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.3331169388
Short name T552
Test name
Test status
Simulation time 10038880022 ps
CPU time 12.45 seconds
Started Jun 05 05:44:17 PM PDT 24
Finished Jun 05 05:44:30 PM PDT 24
Peak memory 205536 kb
Host smart-26a82d52-981a-414c-ac04-558f108f9bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33311
69388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.3331169388
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.1209941195
Short name T481
Test name
Test status
Simulation time 10070533247 ps
CPU time 14.43 seconds
Started Jun 05 05:44:13 PM PDT 24
Finished Jun 05 05:44:28 PM PDT 24
Peak memory 205712 kb
Host smart-14351135-d2a4-4be9-b3eb-2f0bf3d0b8de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12099
41195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.1209941195
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2884324108
Short name T418
Test name
Test status
Simulation time 10117716413 ps
CPU time 12.85 seconds
Started Jun 05 05:44:07 PM PDT 24
Finished Jun 05 05:44:21 PM PDT 24
Peak memory 205620 kb
Host smart-99ca173c-2b3b-492c-bc18-c7c41a3c5a7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28843
24108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2884324108
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3197745198
Short name T671
Test name
Test status
Simulation time 10079256256 ps
CPU time 13.29 seconds
Started Jun 05 05:44:16 PM PDT 24
Finished Jun 05 05:44:30 PM PDT 24
Peak memory 205672 kb
Host smart-205408dc-1cac-4d07-8826-240df47cb209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31977
45198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3197745198
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.2622293345
Short name T1776
Test name
Test status
Simulation time 10059451090 ps
CPU time 13.62 seconds
Started Jun 05 05:44:21 PM PDT 24
Finished Jun 05 05:44:35 PM PDT 24
Peak memory 205716 kb
Host smart-9a6c2dd1-8004-44a8-a0c0-d998d6334be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26222
93345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.2622293345
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_eop_single_bit_handling.1212419634
Short name T1113
Test name
Test status
Simulation time 10088779415 ps
CPU time 12.74 seconds
Started Jun 05 05:44:16 PM PDT 24
Finished Jun 05 05:44:29 PM PDT 24
Peak memory 205704 kb
Host smart-b4a84172-8804-4df4-b36a-774b93208146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12124
19634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_eop_single_bit_handling.1212419634
Directory /workspace/1.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.2130390761
Short name T662
Test name
Test status
Simulation time 10085073625 ps
CPU time 14.43 seconds
Started Jun 05 05:44:20 PM PDT 24
Finished Jun 05 05:44:35 PM PDT 24
Peak memory 205776 kb
Host smart-1c7690ea-2177-4fb7-b2e0-4969f22a26f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21303
90761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.2130390761
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.3480168137
Short name T1598
Test name
Test status
Simulation time 29461611983 ps
CPU time 51.33 seconds
Started Jun 05 05:44:14 PM PDT 24
Finished Jun 05 05:45:06 PM PDT 24
Peak memory 205660 kb
Host smart-80625c14-7a86-4b1e-a618-47b7045798d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34801
68137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3480168137
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.3784014778
Short name T1510
Test name
Test status
Simulation time 10142851361 ps
CPU time 13.35 seconds
Started Jun 05 05:44:16 PM PDT 24
Finished Jun 05 05:44:30 PM PDT 24
Peak memory 205644 kb
Host smart-8929ac42-85e6-4496-8a7d-00bd9497b21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37840
14778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.3784014778
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1426236964
Short name T972
Test name
Test status
Simulation time 10112180312 ps
CPU time 15.26 seconds
Started Jun 05 05:44:09 PM PDT 24
Finished Jun 05 05:44:25 PM PDT 24
Peak memory 205700 kb
Host smart-6bda6cfb-327b-4db5-a03f-8b4b19541d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14262
36964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1426236964
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.1264237700
Short name T1967
Test name
Test status
Simulation time 29710098841 ps
CPU time 136.13 seconds
Started Jun 05 05:44:13 PM PDT 24
Finished Jun 05 05:46:30 PM PDT 24
Peak memory 205700 kb
Host smart-f491325d-1b1d-4e31-86ad-22710c069bf1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1264237700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.1264237700
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.3641908840
Short name T953
Test name
Test status
Simulation time 32668482090 ps
CPU time 562.97 seconds
Started Jun 05 05:44:19 PM PDT 24
Finished Jun 05 05:53:42 PM PDT 24
Peak memory 205668 kb
Host smart-6d8c977f-fd70-4f6e-a410-fad9c7cecbf1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3641908840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.3641908840
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.3420577351
Short name T1740
Test name
Test status
Simulation time 10064283162 ps
CPU time 13.56 seconds
Started Jun 05 05:44:20 PM PDT 24
Finished Jun 05 05:44:34 PM PDT 24
Peak memory 205604 kb
Host smart-0378583c-a9d7-403b-80d9-5d551c6df6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34205
77351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.3420577351
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.4173956315
Short name T835
Test name
Test status
Simulation time 10087367263 ps
CPU time 15.16 seconds
Started Jun 05 05:44:19 PM PDT 24
Finished Jun 05 05:44:34 PM PDT 24
Peak memory 205808 kb
Host smart-008246a4-076f-4421-af0f-264e20fbfb8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41739
56315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.4173956315
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.4117578420
Short name T193
Test name
Test status
Simulation time 298046914 ps
CPU time 1.11 seconds
Started Jun 05 05:44:18 PM PDT 24
Finished Jun 05 05:44:20 PM PDT 24
Peak memory 221716 kb
Host smart-828359e8-f4e9-483a-9289-1729fbdb2014
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4117578420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.4117578420
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3615581268
Short name T1205
Test name
Test status
Simulation time 10096023002 ps
CPU time 13.33 seconds
Started Jun 05 05:44:29 PM PDT 24
Finished Jun 05 05:44:43 PM PDT 24
Peak memory 205788 kb
Host smart-2e58b424-d840-43ec-beac-8f87657e275a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36155
81268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3615581268
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3992056293
Short name T137
Test name
Test status
Simulation time 10141775746 ps
CPU time 14.93 seconds
Started Jun 05 05:44:08 PM PDT 24
Finished Jun 05 05:44:24 PM PDT 24
Peak memory 205776 kb
Host smart-c922bc8c-beb0-4fa8-a71c-1fbef7e4a848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39920
56293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3992056293
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.2006652446
Short name T748
Test name
Test status
Simulation time 10073380852 ps
CPU time 13.89 seconds
Started Jun 05 05:44:18 PM PDT 24
Finished Jun 05 05:44:33 PM PDT 24
Peak memory 205744 kb
Host smart-4e49d1fd-a613-4180-a234-6bbf0713a0c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20066
52446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.2006652446
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.1647215180
Short name T1033
Test name
Test status
Simulation time 10050523763 ps
CPU time 13.06 seconds
Started Jun 05 05:44:29 PM PDT 24
Finished Jun 05 05:44:42 PM PDT 24
Peak memory 205712 kb
Host smart-0b421e58-35db-4383-bc2d-783a90b3069a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16472
15180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1647215180
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.775534073
Short name T920
Test name
Test status
Simulation time 15673219750 ps
CPU time 176.26 seconds
Started Jun 05 05:44:16 PM PDT 24
Finished Jun 05 05:47:13 PM PDT 24
Peak memory 205680 kb
Host smart-b5788daa-b2ee-40a2-a8aa-473698371786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77553
4073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.775534073
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.2695072769
Short name T154
Test name
Test status
Simulation time 30744138785 ps
CPU time 494.65 seconds
Started Jun 05 05:44:19 PM PDT 24
Finished Jun 05 05:52:34 PM PDT 24
Peak memory 205780 kb
Host smart-9481e1d4-ff34-4e0b-a134-5e0599444512
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695072769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_
traffic.2695072769
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.3913928344
Short name T296
Test name
Test status
Simulation time 10140551204 ps
CPU time 13.4 seconds
Started Jun 05 05:45:25 PM PDT 24
Finished Jun 05 05:45:39 PM PDT 24
Peak memory 205748 kb
Host smart-f8dfbf6f-87b2-4efc-946c-77ccddd4990a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3913928344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.3913928344
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.3938042552
Short name T326
Test name
Test status
Simulation time 10097905293 ps
CPU time 13.11 seconds
Started Jun 05 05:45:27 PM PDT 24
Finished Jun 05 05:45:41 PM PDT 24
Peak memory 205732 kb
Host smart-366df2fc-20c4-4ac3-91e4-fd8051698d06
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3938042552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.3938042552
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.2037113384
Short name T718
Test name
Test status
Simulation time 10115176514 ps
CPU time 13.31 seconds
Started Jun 05 05:45:26 PM PDT 24
Finished Jun 05 05:45:40 PM PDT 24
Peak memory 205644 kb
Host smart-b1c6b150-5c28-4fd8-8e36-4f5ed7bfb790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20371
13384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.2037113384
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.3770565471
Short name T1537
Test name
Test status
Simulation time 13473407645 ps
CPU time 17.87 seconds
Started Jun 05 05:45:22 PM PDT 24
Finished Jun 05 05:45:41 PM PDT 24
Peak memory 205784 kb
Host smart-6d0be702-d951-453e-b534-3842998ec045
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3770565471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.3770565471
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.1355104112
Short name T537
Test name
Test status
Simulation time 23312527592 ps
CPU time 27.38 seconds
Started Jun 05 05:45:23 PM PDT 24
Finished Jun 05 05:45:51 PM PDT 24
Peak memory 205760 kb
Host smart-8b01b2c2-63e3-4e3c-a490-4d7f3bce2950
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1355104112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.1355104112
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.1586750540
Short name T1279
Test name
Test status
Simulation time 10056759626 ps
CPU time 15.91 seconds
Started Jun 05 05:45:20 PM PDT 24
Finished Jun 05 05:45:37 PM PDT 24
Peak memory 205624 kb
Host smart-c4455bc3-8f92-4bf4-8669-37f3eb8d181d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15867
50540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.1586750540
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.491867963
Short name T1058
Test name
Test status
Simulation time 10404816592 ps
CPU time 14.49 seconds
Started Jun 05 05:45:21 PM PDT 24
Finished Jun 05 05:45:36 PM PDT 24
Peak memory 205700 kb
Host smart-0b75319c-f5c4-49d1-b9e0-38380560471e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49186
7963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.491867963
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.3480984154
Short name T1484
Test name
Test status
Simulation time 10040450842 ps
CPU time 12.67 seconds
Started Jun 05 05:45:19 PM PDT 24
Finished Jun 05 05:45:33 PM PDT 24
Peak memory 205696 kb
Host smart-ce9c1892-2415-403a-a37a-a6f44d85ca13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34809
84154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.3480984154
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.2325753946
Short name T369
Test name
Test status
Simulation time 10071641245 ps
CPU time 13.7 seconds
Started Jun 05 05:45:25 PM PDT 24
Finished Jun 05 05:45:40 PM PDT 24
Peak memory 205668 kb
Host smart-e2c90c80-061f-4fae-9143-c2d5b8bb63cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23257
53946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.2325753946
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.152589360
Short name T1559
Test name
Test status
Simulation time 10755330040 ps
CPU time 15.63 seconds
Started Jun 05 05:45:24 PM PDT 24
Finished Jun 05 05:45:40 PM PDT 24
Peak memory 205204 kb
Host smart-31963cab-cdd8-41a9-be67-8957229d782b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15258
9360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.152589360
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.187280071
Short name T1174
Test name
Test status
Simulation time 10128484067 ps
CPU time 13.97 seconds
Started Jun 05 05:45:21 PM PDT 24
Finished Jun 05 05:45:36 PM PDT 24
Peak memory 205692 kb
Host smart-a9e608b7-8ee3-4394-a120-193359eae6c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18728
0071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.187280071
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.2551720412
Short name T427
Test name
Test status
Simulation time 10103291957 ps
CPU time 13.18 seconds
Started Jun 05 05:45:32 PM PDT 24
Finished Jun 05 05:45:45 PM PDT 24
Peak memory 205680 kb
Host smart-19f7f5c8-8bf9-4189-848d-46dc4dcdc533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25517
20412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.2551720412
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.3188627604
Short name T1613
Test name
Test status
Simulation time 10080847279 ps
CPU time 13.92 seconds
Started Jun 05 05:45:33 PM PDT 24
Finished Jun 05 05:45:47 PM PDT 24
Peak memory 205748 kb
Host smart-a1ee7a0f-62be-4b35-9150-98e6fe4a8693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31886
27604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3188627604
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.2679232960
Short name T542
Test name
Test status
Simulation time 10106887549 ps
CPU time 13.81 seconds
Started Jun 05 05:45:23 PM PDT 24
Finished Jun 05 05:45:38 PM PDT 24
Peak memory 205760 kb
Host smart-5ba26c11-1196-441e-a582-96f03e45185e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26792
32960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.2679232960
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.1618761727
Short name T564
Test name
Test status
Simulation time 10069935469 ps
CPU time 15.26 seconds
Started Jun 05 05:45:23 PM PDT 24
Finished Jun 05 05:45:39 PM PDT 24
Peak memory 205836 kb
Host smart-7093eff1-9962-4c51-b823-f5f648c96be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16187
61727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.1618761727
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.1503600348
Short name T1234
Test name
Test status
Simulation time 13246918141 ps
CPU time 16.47 seconds
Started Jun 05 05:45:23 PM PDT 24
Finished Jun 05 05:45:40 PM PDT 24
Peak memory 205696 kb
Host smart-a10b7f17-81d7-49ef-8439-476618f7e97f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15036
00348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.1503600348
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.655854906
Short name T1143
Test name
Test status
Simulation time 10132697015 ps
CPU time 13.88 seconds
Started Jun 05 05:45:23 PM PDT 24
Finished Jun 05 05:45:37 PM PDT 24
Peak memory 205704 kb
Host smart-04e6b76e-43a5-41a8-8427-c8a547d9dea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65585
4906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.655854906
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.3681509062
Short name T818
Test name
Test status
Simulation time 15177497936 ps
CPU time 56.24 seconds
Started Jun 05 05:45:22 PM PDT 24
Finished Jun 05 05:46:19 PM PDT 24
Peak memory 205732 kb
Host smart-f3aab01b-fa0d-47d7-a6f4-48f37ab245a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36815
09062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.3681509062
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2008912929
Short name T770
Test name
Test status
Simulation time 10048317431 ps
CPU time 15.82 seconds
Started Jun 05 05:45:21 PM PDT 24
Finished Jun 05 05:45:38 PM PDT 24
Peak memory 205676 kb
Host smart-dbfb80c3-ea75-4f52-83b1-0b764e7de550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20089
12929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2008912929
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.1294536673
Short name T1550
Test name
Test status
Simulation time 10070477335 ps
CPU time 16 seconds
Started Jun 05 05:45:22 PM PDT 24
Finished Jun 05 05:45:39 PM PDT 24
Peak memory 205744 kb
Host smart-223e82d8-4b05-4ee5-a4ae-1b6f6f4eb8a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12945
36673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.1294536673
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.4051155495
Short name T1961
Test name
Test status
Simulation time 10069886395 ps
CPU time 16.5 seconds
Started Jun 05 05:45:21 PM PDT 24
Finished Jun 05 05:45:38 PM PDT 24
Peak memory 205736 kb
Host smart-5348d1d7-c0be-4783-bbc1-b29d1856aab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40511
55495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.4051155495
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.3170309787
Short name T422
Test name
Test status
Simulation time 10058323513 ps
CPU time 13.26 seconds
Started Jun 05 05:45:29 PM PDT 24
Finished Jun 05 05:45:42 PM PDT 24
Peak memory 205728 kb
Host smart-ae4832a1-1bcb-4790-8b46-b2c83c778736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31703
09787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.3170309787
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_eop_single_bit_handling.3927669696
Short name T528
Test name
Test status
Simulation time 10092033919 ps
CPU time 13.11 seconds
Started Jun 05 05:45:25 PM PDT 24
Finished Jun 05 05:45:38 PM PDT 24
Peak memory 205676 kb
Host smart-8b64afd7-6e46-4ca2-b13d-da03e84f9b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39276
69696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_eop_single_bit_handling.3927669696
Directory /workspace/10.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3983906426
Short name T1241
Test name
Test status
Simulation time 10069787749 ps
CPU time 12.85 seconds
Started Jun 05 05:45:31 PM PDT 24
Finished Jun 05 05:45:44 PM PDT 24
Peak memory 205816 kb
Host smart-c5a83f9a-608e-4590-a067-dde31184a26e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39839
06426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3983906426
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.4230616494
Short name T980
Test name
Test status
Simulation time 10032722193 ps
CPU time 13.17 seconds
Started Jun 05 05:45:32 PM PDT 24
Finished Jun 05 05:45:46 PM PDT 24
Peak memory 205680 kb
Host smart-07acddf5-0cd4-4f4c-a643-e611a355954a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42306
16494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.4230616494
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.2941737335
Short name T1556
Test name
Test status
Simulation time 27019620325 ps
CPU time 47.53 seconds
Started Jun 05 05:45:28 PM PDT 24
Finished Jun 05 05:46:16 PM PDT 24
Peak memory 205680 kb
Host smart-a1343074-8139-4de8-81b0-1a66b9d8e544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29417
37335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.2941737335
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.3286417317
Short name T1487
Test name
Test status
Simulation time 10078110443 ps
CPU time 13.86 seconds
Started Jun 05 05:45:33 PM PDT 24
Finished Jun 05 05:45:48 PM PDT 24
Peak memory 205700 kb
Host smart-7cb7041e-c848-403b-b2d6-90f88d7962b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32864
17317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.3286417317
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.3756620363
Short name T1973
Test name
Test status
Simulation time 10103535418 ps
CPU time 13.39 seconds
Started Jun 05 05:45:27 PM PDT 24
Finished Jun 05 05:45:41 PM PDT 24
Peak memory 205728 kb
Host smart-968120b2-9ff6-4e87-9ddc-8e51afc0f1f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37566
20363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.3756620363
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.2432048254
Short name T1018
Test name
Test status
Simulation time 10072405979 ps
CPU time 15 seconds
Started Jun 05 05:45:27 PM PDT 24
Finished Jun 05 05:45:43 PM PDT 24
Peak memory 205636 kb
Host smart-fdc2123e-3c6f-4d6e-a872-379d7903c111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24320
48254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.2432048254
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.4101664996
Short name T452
Test name
Test status
Simulation time 10037156536 ps
CPU time 14.28 seconds
Started Jun 05 05:45:29 PM PDT 24
Finished Jun 05 05:45:44 PM PDT 24
Peak memory 205728 kb
Host smart-403ddbbd-717c-46e6-bba9-721f2a4c6574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41016
64996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.4101664996
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1814253210
Short name T1079
Test name
Test status
Simulation time 10067276731 ps
CPU time 15.49 seconds
Started Jun 05 05:45:27 PM PDT 24
Finished Jun 05 05:45:43 PM PDT 24
Peak memory 205644 kb
Host smart-e7291814-9c7a-4f44-83ec-c6ec2b161939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18142
53210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1814253210
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.3243155233
Short name T1979
Test name
Test status
Simulation time 10100985794 ps
CPU time 15.35 seconds
Started Jun 05 05:45:28 PM PDT 24
Finished Jun 05 05:45:44 PM PDT 24
Peak memory 205808 kb
Host smart-fc89d8a3-6f1b-440e-adc6-933c0bf9812f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32431
55233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.3243155233
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.883503869
Short name T1334
Test name
Test status
Simulation time 10078630353 ps
CPU time 14.28 seconds
Started Jun 05 05:45:31 PM PDT 24
Finished Jun 05 05:45:46 PM PDT 24
Peak memory 205652 kb
Host smart-4811747b-9788-4661-a40f-12154207e031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88350
3869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.883503869
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.2179244890
Short name T380
Test name
Test status
Simulation time 10144746630 ps
CPU time 14.2 seconds
Started Jun 05 05:45:31 PM PDT 24
Finished Jun 05 05:45:45 PM PDT 24
Peak memory 205764 kb
Host smart-18b836f0-0f46-439e-8216-f09db2f8dcbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21792
44890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.2179244890
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.3716520416
Short name T1180
Test name
Test status
Simulation time 23797775260 ps
CPU time 147.61 seconds
Started Jun 05 05:45:28 PM PDT 24
Finished Jun 05 05:47:56 PM PDT 24
Peak memory 205704 kb
Host smart-ba66647e-d7f1-47e6-9b18-80726cf0c64d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37165
20416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.3716520416
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.332470865
Short name T255
Test name
Test status
Simulation time 10140029144 ps
CPU time 14.12 seconds
Started Jun 05 05:45:37 PM PDT 24
Finished Jun 05 05:45:52 PM PDT 24
Peak memory 205764 kb
Host smart-2bc8530e-d13f-4595-818f-a31c5cf9d5d6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=332470865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.332470865
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.126180955
Short name T2
Test name
Test status
Simulation time 10112925208 ps
CPU time 14.57 seconds
Started Jun 05 05:45:42 PM PDT 24
Finished Jun 05 05:45:58 PM PDT 24
Peak memory 205664 kb
Host smart-e255c1cc-e150-479d-95db-1d25505c536c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=126180955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.126180955
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.3140348097
Short name T494
Test name
Test status
Simulation time 10086994398 ps
CPU time 13.66 seconds
Started Jun 05 05:45:38 PM PDT 24
Finished Jun 05 05:45:53 PM PDT 24
Peak memory 205788 kb
Host smart-01e19229-627d-409f-8c01-e0ee25a2c076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31403
48097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.3140348097
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.607616406
Short name T1506
Test name
Test status
Simulation time 14055287114 ps
CPU time 16.65 seconds
Started Jun 05 05:45:32 PM PDT 24
Finished Jun 05 05:45:49 PM PDT 24
Peak memory 205652 kb
Host smart-1be92dd6-a9ba-4bb9-8db9-e0ecbc46a055
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=607616406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.607616406
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.1201063165
Short name T652
Test name
Test status
Simulation time 10045422077 ps
CPU time 12.4 seconds
Started Jun 05 05:45:28 PM PDT 24
Finished Jun 05 05:45:41 PM PDT 24
Peak memory 205640 kb
Host smart-2d85f4b4-c748-4a79-8939-2c6feb99a2a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12010
63165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.1201063165
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.3394948219
Short name T1706
Test name
Test status
Simulation time 10061485500 ps
CPU time 13.73 seconds
Started Jun 05 05:45:34 PM PDT 24
Finished Jun 05 05:45:48 PM PDT 24
Peak memory 205692 kb
Host smart-b85c579d-b144-48e4-a41f-67819a189446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33949
48219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.3394948219
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.1434117669
Short name T917
Test name
Test status
Simulation time 10067352423 ps
CPU time 13.32 seconds
Started Jun 05 05:45:29 PM PDT 24
Finished Jun 05 05:45:43 PM PDT 24
Peak memory 205640 kb
Host smart-8ac69121-e483-4783-a928-a3247d986c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14341
17669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.1434117669
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.1610503699
Short name T1191
Test name
Test status
Simulation time 10671770121 ps
CPU time 14.21 seconds
Started Jun 05 05:45:28 PM PDT 24
Finished Jun 05 05:45:43 PM PDT 24
Peak memory 205748 kb
Host smart-ea673745-b3d0-4d92-a271-b83d0494de00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16105
03699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.1610503699
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.2724238069
Short name T1167
Test name
Test status
Simulation time 10066459057 ps
CPU time 14.03 seconds
Started Jun 05 05:45:30 PM PDT 24
Finished Jun 05 05:45:44 PM PDT 24
Peak memory 205676 kb
Host smart-12df84e7-ec20-4131-9557-7ce2c515911a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27242
38069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.2724238069
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1136716562
Short name T1291
Test name
Test status
Simulation time 10049165309 ps
CPU time 14.45 seconds
Started Jun 05 05:45:37 PM PDT 24
Finished Jun 05 05:45:52 PM PDT 24
Peak memory 205756 kb
Host smart-1954456c-ed7d-4589-afda-c1fea0936966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11367
16562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1136716562
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.4282401396
Short name T1758
Test name
Test status
Simulation time 10144578645 ps
CPU time 13.46 seconds
Started Jun 05 05:45:28 PM PDT 24
Finished Jun 05 05:45:42 PM PDT 24
Peak memory 205736 kb
Host smart-60f29c77-ba75-4baa-8481-f8cbf7796629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42824
01396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.4282401396
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.4276944937
Short name T1666
Test name
Test status
Simulation time 10126357894 ps
CPU time 14.05 seconds
Started Jun 05 05:45:34 PM PDT 24
Finished Jun 05 05:45:49 PM PDT 24
Peak memory 205792 kb
Host smart-9441c8a8-ecd0-460f-a899-26b5f675c392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42769
44937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.4276944937
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.111350948
Short name T322
Test name
Test status
Simulation time 13224997922 ps
CPU time 17.21 seconds
Started Jun 05 05:45:38 PM PDT 24
Finished Jun 05 05:45:56 PM PDT 24
Peak memory 205584 kb
Host smart-7178ce7c-b849-41d1-b9eb-7e505ab65dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11135
0948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.111350948
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1507135463
Short name T1882
Test name
Test status
Simulation time 10087194658 ps
CPU time 14.08 seconds
Started Jun 05 05:45:36 PM PDT 24
Finished Jun 05 05:45:51 PM PDT 24
Peak memory 205752 kb
Host smart-096140b6-9b38-4e0e-bee6-924bf3824939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15071
35463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1507135463
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.1654644977
Short name T990
Test name
Test status
Simulation time 17266882663 ps
CPU time 81.22 seconds
Started Jun 05 05:45:41 PM PDT 24
Finished Jun 05 05:47:03 PM PDT 24
Peak memory 205688 kb
Host smart-ac3c6500-cbe9-4f1c-b912-7792803066ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16546
44977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.1654644977
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2673094230
Short name T1631
Test name
Test status
Simulation time 10045268937 ps
CPU time 15.2 seconds
Started Jun 05 05:45:38 PM PDT 24
Finished Jun 05 05:45:54 PM PDT 24
Peak memory 205664 kb
Host smart-6cd8d232-7225-4f03-87cb-ace9e49895f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26730
94230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2673094230
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.1349332442
Short name T734
Test name
Test status
Simulation time 10108642474 ps
CPU time 15.32 seconds
Started Jun 05 05:45:35 PM PDT 24
Finished Jun 05 05:45:51 PM PDT 24
Peak memory 205796 kb
Host smart-48cc70d6-e7a1-4db6-9694-ceb4b24f2cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13493
32442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.1349332442
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.3131039592
Short name T1524
Test name
Test status
Simulation time 10100931430 ps
CPU time 13.86 seconds
Started Jun 05 05:45:40 PM PDT 24
Finished Jun 05 05:45:55 PM PDT 24
Peak memory 205772 kb
Host smart-ef171c4b-afc0-43c8-a298-5aee450b8c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31310
39592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.3131039592
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.3324704047
Short name T1032
Test name
Test status
Simulation time 10112946773 ps
CPU time 12.46 seconds
Started Jun 05 05:45:38 PM PDT 24
Finished Jun 05 05:45:52 PM PDT 24
Peak memory 205688 kb
Host smart-1e4129ad-868d-4ad5-9cf9-0decc86cc661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33247
04047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.3324704047
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_eop_single_bit_handling.3652947968
Short name T1589
Test name
Test status
Simulation time 10149908899 ps
CPU time 16.04 seconds
Started Jun 05 05:45:34 PM PDT 24
Finished Jun 05 05:45:51 PM PDT 24
Peak memory 205716 kb
Host smart-bd5834e2-d34e-4e8d-b56b-965d467d1bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36529
47968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_eop_single_bit_handling.3652947968
Directory /workspace/11.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.779600647
Short name T683
Test name
Test status
Simulation time 10046923583 ps
CPU time 13.78 seconds
Started Jun 05 05:45:36 PM PDT 24
Finished Jun 05 05:45:51 PM PDT 24
Peak memory 205736 kb
Host smart-c4e2c187-0753-4565-8a5b-01db65c844c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77960
0647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.779600647
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1081513888
Short name T612
Test name
Test status
Simulation time 10052728869 ps
CPU time 14.55 seconds
Started Jun 05 05:45:35 PM PDT 24
Finished Jun 05 05:45:50 PM PDT 24
Peak memory 205628 kb
Host smart-b0343693-11d2-4479-a6d2-751a2ab8547c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10815
13888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1081513888
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.766794239
Short name T2008
Test name
Test status
Simulation time 10095222873 ps
CPU time 14.51 seconds
Started Jun 05 05:45:37 PM PDT 24
Finished Jun 05 05:45:52 PM PDT 24
Peak memory 205732 kb
Host smart-cf6c82d9-6369-4e9a-91bc-41967f7a97c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76679
4239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.766794239
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1973043884
Short name T930
Test name
Test status
Simulation time 10117224687 ps
CPU time 13.4 seconds
Started Jun 05 05:45:36 PM PDT 24
Finished Jun 05 05:45:50 PM PDT 24
Peak memory 205760 kb
Host smart-57ff054d-08c3-4e98-8c9e-dbf6ba89c9fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19730
43884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1973043884
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.170337716
Short name T1637
Test name
Test status
Simulation time 10081433747 ps
CPU time 13.08 seconds
Started Jun 05 05:45:33 PM PDT 24
Finished Jun 05 05:45:47 PM PDT 24
Peak memory 205708 kb
Host smart-2b9ecaef-55b0-411b-8fa0-5d2be33dd21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17033
7716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.170337716
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.2800754674
Short name T1310
Test name
Test status
Simulation time 10038050249 ps
CPU time 13.6 seconds
Started Jun 05 05:45:40 PM PDT 24
Finished Jun 05 05:45:54 PM PDT 24
Peak memory 205720 kb
Host smart-96a8a03c-8c49-4f4c-8b42-6159cda1c5fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28007
54674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.2800754674
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1847875815
Short name T1368
Test name
Test status
Simulation time 10062439237 ps
CPU time 14.61 seconds
Started Jun 05 05:45:35 PM PDT 24
Finished Jun 05 05:45:51 PM PDT 24
Peak memory 205728 kb
Host smart-e79f719e-0319-49cc-91c9-ed6f6d55623f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18478
75815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1847875815
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3037879760
Short name T1507
Test name
Test status
Simulation time 10054657549 ps
CPU time 13.96 seconds
Started Jun 05 05:45:37 PM PDT 24
Finished Jun 05 05:45:51 PM PDT 24
Peak memory 205760 kb
Host smart-984fcf5b-36c2-4c9e-8add-cf2ce6531cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30378
79760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3037879760
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.2455582777
Short name T133
Test name
Test status
Simulation time 10133226672 ps
CPU time 15.91 seconds
Started Jun 05 05:45:26 PM PDT 24
Finished Jun 05 05:45:42 PM PDT 24
Peak memory 205680 kb
Host smart-3a9e4c9b-8d46-499e-a3b0-cf0262056393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24555
82777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.2455582777
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.1215280683
Short name T1985
Test name
Test status
Simulation time 10096352025 ps
CPU time 14.11 seconds
Started Jun 05 05:45:34 PM PDT 24
Finished Jun 05 05:45:49 PM PDT 24
Peak memory 205752 kb
Host smart-a158c8cd-6d6a-40f7-b047-aaf8652165cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12152
80683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.1215280683
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.3784297162
Short name T1699
Test name
Test status
Simulation time 10055311473 ps
CPU time 14.36 seconds
Started Jun 05 05:45:34 PM PDT 24
Finished Jun 05 05:45:49 PM PDT 24
Peak memory 205756 kb
Host smart-5027a171-d0f6-44bd-b1b8-5a1ebe525ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37842
97162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3784297162
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.4036544313
Short name T964
Test name
Test status
Simulation time 14248978433 ps
CPU time 54.6 seconds
Started Jun 05 05:45:36 PM PDT 24
Finished Jun 05 05:46:31 PM PDT 24
Peak memory 205712 kb
Host smart-9b86f96a-b6fb-4fbb-ab1d-b352feb8081a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40365
44313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.4036544313
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.4076942548
Short name T604
Test name
Test status
Simulation time 10135928862 ps
CPU time 13.34 seconds
Started Jun 05 05:45:46 PM PDT 24
Finished Jun 05 05:46:00 PM PDT 24
Peak memory 205680 kb
Host smart-578bd8e4-6b3e-4d7b-b0b3-356eb994ee8a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4076942548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.4076942548
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.2974415618
Short name T1769
Test name
Test status
Simulation time 10119120130 ps
CPU time 13.36 seconds
Started Jun 05 05:45:43 PM PDT 24
Finished Jun 05 05:45:57 PM PDT 24
Peak memory 205776 kb
Host smart-1d88b854-6ece-4130-b2c8-c4e925f14226
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2974415618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.2974415618
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.2034015489
Short name T1964
Test name
Test status
Simulation time 10136746087 ps
CPU time 13.46 seconds
Started Jun 05 05:45:43 PM PDT 24
Finished Jun 05 05:45:57 PM PDT 24
Peak memory 205708 kb
Host smart-1f4a979f-28b7-4d68-97e5-b4dffd1a92b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20340
15489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.2034015489
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.2771776181
Short name T1483
Test name
Test status
Simulation time 14213657752 ps
CPU time 19.66 seconds
Started Jun 05 05:45:35 PM PDT 24
Finished Jun 05 05:45:55 PM PDT 24
Peak memory 205712 kb
Host smart-9d493984-53fe-4cfc-9791-f9325bd67e59
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2771776181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.2771776181
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.3278913140
Short name T1339
Test name
Test status
Simulation time 23304370406 ps
CPU time 23.96 seconds
Started Jun 05 05:45:37 PM PDT 24
Finished Jun 05 05:46:02 PM PDT 24
Peak memory 205656 kb
Host smart-7a4a2e85-b14a-45f7-a1b3-c504251b0b88
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3278913140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.3278913140
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.1021030865
Short name T2035
Test name
Test status
Simulation time 10050466081 ps
CPU time 12.97 seconds
Started Jun 05 05:45:37 PM PDT 24
Finished Jun 05 05:45:50 PM PDT 24
Peak memory 205624 kb
Host smart-2d154ca7-7601-40e6-a766-4bdeb872876d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10210
30865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1021030865
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.866550384
Short name T1887
Test name
Test status
Simulation time 10058932264 ps
CPU time 13.96 seconds
Started Jun 05 05:45:34 PM PDT 24
Finished Jun 05 05:45:48 PM PDT 24
Peak memory 205764 kb
Host smart-f7e03452-438d-44e5-901d-3cb8a31c4f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86655
0384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.866550384
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.3963342466
Short name T1622
Test name
Test status
Simulation time 10878743653 ps
CPU time 14.62 seconds
Started Jun 05 05:45:36 PM PDT 24
Finished Jun 05 05:45:51 PM PDT 24
Peak memory 205664 kb
Host smart-c06355b5-4c8d-4a67-a991-1655d781bcdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39633
42466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.3963342466
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.2071714680
Short name T1157
Test name
Test status
Simulation time 10045980465 ps
CPU time 15.11 seconds
Started Jun 05 05:45:38 PM PDT 24
Finished Jun 05 05:45:54 PM PDT 24
Peak memory 205720 kb
Host smart-ac92bc20-ff1e-4d3e-9bd3-99e3a8d3baaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20717
14680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2071714680
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.1798328987
Short name T1030
Test name
Test status
Simulation time 10052478694 ps
CPU time 13.64 seconds
Started Jun 05 05:45:35 PM PDT 24
Finished Jun 05 05:45:50 PM PDT 24
Peak memory 205668 kb
Host smart-793dca0a-d94a-4ba0-95c6-869f48a8b799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17983
28987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.1798328987
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.1055485300
Short name T1048
Test name
Test status
Simulation time 10922999255 ps
CPU time 15.36 seconds
Started Jun 05 05:45:34 PM PDT 24
Finished Jun 05 05:45:50 PM PDT 24
Peak memory 205736 kb
Host smart-f7dee6c8-5714-4963-8817-14ad4061f2c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10554
85300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.1055485300
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.1045745352
Short name T1261
Test name
Test status
Simulation time 10232491908 ps
CPU time 15.31 seconds
Started Jun 05 05:45:36 PM PDT 24
Finished Jun 05 05:45:52 PM PDT 24
Peak memory 205908 kb
Host smart-b6b4945f-130d-4bed-b065-3ff263e575f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10457
45352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.1045745352
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.677176977
Short name T1390
Test name
Test status
Simulation time 10059494364 ps
CPU time 13.51 seconds
Started Jun 05 05:45:46 PM PDT 24
Finished Jun 05 05:46:00 PM PDT 24
Peak memory 205800 kb
Host smart-c33248ac-7708-47c6-b92f-903e8b5d30f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67717
6977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.677176977
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.3850320327
Short name T1378
Test name
Test status
Simulation time 10050070506 ps
CPU time 13.33 seconds
Started Jun 05 05:45:44 PM PDT 24
Finished Jun 05 05:45:58 PM PDT 24
Peak memory 205748 kb
Host smart-fd2c8506-4a1f-4237-909c-026a695597dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38503
20327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.3850320327
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.2600781318
Short name T1155
Test name
Test status
Simulation time 10104627185 ps
CPU time 13.6 seconds
Started Jun 05 05:45:37 PM PDT 24
Finished Jun 05 05:45:51 PM PDT 24
Peak memory 205684 kb
Host smart-c3152e06-8f58-401c-bfca-66a25ba3405c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26007
81318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2600781318
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.2149163393
Short name T395
Test name
Test status
Simulation time 10145955938 ps
CPU time 15.45 seconds
Started Jun 05 05:45:35 PM PDT 24
Finished Jun 05 05:45:51 PM PDT 24
Peak memory 205760 kb
Host smart-1daa2d67-4cb9-4d89-94bc-aac8f2f2da57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21491
63393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.2149163393
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.3013772095
Short name T317
Test name
Test status
Simulation time 13157170488 ps
CPU time 17.49 seconds
Started Jun 05 05:45:35 PM PDT 24
Finished Jun 05 05:45:54 PM PDT 24
Peak memory 205764 kb
Host smart-15c46284-5673-4849-a54d-a888fd273be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30137
72095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.3013772095
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.329328310
Short name T1112
Test name
Test status
Simulation time 10123934745 ps
CPU time 13.62 seconds
Started Jun 05 05:45:37 PM PDT 24
Finished Jun 05 05:45:51 PM PDT 24
Peak memory 205716 kb
Host smart-85de00b7-ad4a-4183-8846-e3e80d209650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32932
8310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.329328310
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.3786718779
Short name T1474
Test name
Test status
Simulation time 15499718467 ps
CPU time 66.55 seconds
Started Jun 05 05:45:39 PM PDT 24
Finished Jun 05 05:46:46 PM PDT 24
Peak memory 205664 kb
Host smart-afdad0ce-5780-47a8-8885-0a9412aad5f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37867
18779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.3786718779
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.2024847928
Short name T1433
Test name
Test status
Simulation time 10073094567 ps
CPU time 14.22 seconds
Started Jun 05 05:45:36 PM PDT 24
Finished Jun 05 05:45:51 PM PDT 24
Peak memory 205796 kb
Host smart-dd80d457-1e2a-41ff-aa69-c811982a71d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20248
47928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2024847928
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.4239199549
Short name T438
Test name
Test status
Simulation time 10093522669 ps
CPU time 13.36 seconds
Started Jun 05 05:45:33 PM PDT 24
Finished Jun 05 05:45:47 PM PDT 24
Peak memory 205952 kb
Host smart-35641789-8c45-4488-948a-52905ef47642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42391
99549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.4239199549
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.4084054948
Short name T610
Test name
Test status
Simulation time 10072066420 ps
CPU time 14.52 seconds
Started Jun 05 05:45:50 PM PDT 24
Finished Jun 05 05:46:05 PM PDT 24
Peak memory 205764 kb
Host smart-693909d7-9436-4243-abb4-9539cac72963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40840
54948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.4084054948
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.897850776
Short name T1220
Test name
Test status
Simulation time 10095922639 ps
CPU time 13.68 seconds
Started Jun 05 05:45:47 PM PDT 24
Finished Jun 05 05:46:01 PM PDT 24
Peak memory 205712 kb
Host smart-af197da3-9ff1-4ab3-9522-bd7c1e33905b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89785
0776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.897850776
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.973888188
Short name T1743
Test name
Test status
Simulation time 10052407015 ps
CPU time 15.9 seconds
Started Jun 05 05:45:42 PM PDT 24
Finished Jun 05 05:45:59 PM PDT 24
Peak memory 205688 kb
Host smart-d02886da-990a-48bc-8e9e-e50ee8f61563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97388
8188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.973888188
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_eop_single_bit_handling.1045677500
Short name T1640
Test name
Test status
Simulation time 10091738366 ps
CPU time 16.06 seconds
Started Jun 05 05:45:46 PM PDT 24
Finished Jun 05 05:46:03 PM PDT 24
Peak memory 205640 kb
Host smart-f2624c30-ae11-46c0-aca3-fcdfc824a531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10456
77500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_eop_single_bit_handling.1045677500
Directory /workspace/12.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1721929191
Short name T43
Test name
Test status
Simulation time 10040083154 ps
CPU time 15.64 seconds
Started Jun 05 05:45:46 PM PDT 24
Finished Jun 05 05:46:02 PM PDT 24
Peak memory 205736 kb
Host smart-a4c32619-c0fa-4b92-9b2d-a7b3cb9dab21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17219
29191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1721929191
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3235870064
Short name T1151
Test name
Test status
Simulation time 10047802173 ps
CPU time 15.42 seconds
Started Jun 05 05:45:42 PM PDT 24
Finished Jun 05 05:45:58 PM PDT 24
Peak memory 205764 kb
Host smart-d53275c1-ec2d-4190-b8d5-3e677bf121d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32358
70064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3235870064
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.2134003283
Short name T231
Test name
Test status
Simulation time 28090990797 ps
CPU time 54.37 seconds
Started Jun 05 05:45:43 PM PDT 24
Finished Jun 05 05:46:38 PM PDT 24
Peak memory 205644 kb
Host smart-9b16f0a1-c0eb-4622-9471-e1d0825a5677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21340
03283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.2134003283
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.1718664587
Short name T1626
Test name
Test status
Simulation time 10156420942 ps
CPU time 13.59 seconds
Started Jun 05 05:45:47 PM PDT 24
Finished Jun 05 05:46:01 PM PDT 24
Peak memory 205768 kb
Host smart-95169624-ba24-47be-817b-f4120001ce1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17186
64587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.1718664587
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3313774341
Short name T1798
Test name
Test status
Simulation time 10102948000 ps
CPU time 14.25 seconds
Started Jun 05 05:45:46 PM PDT 24
Finished Jun 05 05:46:00 PM PDT 24
Peak memory 205632 kb
Host smart-4f1b005a-6c53-4a72-9b04-cf8e8766dbe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33137
74341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3313774341
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.987724374
Short name T1825
Test name
Test status
Simulation time 10109397832 ps
CPU time 13.78 seconds
Started Jun 05 05:45:42 PM PDT 24
Finished Jun 05 05:45:56 PM PDT 24
Peak memory 205700 kb
Host smart-f0c251a8-232f-413d-b4b5-57efc554daef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98772
4374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.987724374
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.2731588191
Short name T928
Test name
Test status
Simulation time 10036213289 ps
CPU time 13.22 seconds
Started Jun 05 05:45:50 PM PDT 24
Finished Jun 05 05:46:04 PM PDT 24
Peak memory 205760 kb
Host smart-e2163c6a-0688-4348-8926-952c799dfc90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27315
88191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.2731588191
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.2519104916
Short name T128
Test name
Test status
Simulation time 10057997853 ps
CPU time 13.46 seconds
Started Jun 05 05:45:46 PM PDT 24
Finished Jun 05 05:46:00 PM PDT 24
Peak memory 205696 kb
Host smart-ef5ea266-f3ef-4028-a8f9-5b0bc602ab53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25191
04916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.2519104916
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_smoke.817028172
Short name T735
Test name
Test status
Simulation time 10165788365 ps
CPU time 14.47 seconds
Started Jun 05 05:45:35 PM PDT 24
Finished Jun 05 05:45:50 PM PDT 24
Peak memory 205672 kb
Host smart-b931fa5c-21e5-4890-8363-ec6c2374b78c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81702
8172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.817028172
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.1278896558
Short name T487
Test name
Test status
Simulation time 10084520071 ps
CPU time 12.8 seconds
Started Jun 05 05:45:43 PM PDT 24
Finished Jun 05 05:45:57 PM PDT 24
Peak memory 205584 kb
Host smart-7880620b-d32f-4db8-b9dc-ad1793699934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12788
96558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.1278896558
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.4007386934
Short name T1457
Test name
Test status
Simulation time 10068896028 ps
CPU time 13.2 seconds
Started Jun 05 05:45:46 PM PDT 24
Finished Jun 05 05:45:59 PM PDT 24
Peak memory 205724 kb
Host smart-07bb2557-fbf2-4a7e-94a5-ed67155aa6d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40073
86934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.4007386934
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.1821819605
Short name T611
Test name
Test status
Simulation time 14279705690 ps
CPU time 127.78 seconds
Started Jun 05 05:45:43 PM PDT 24
Finished Jun 05 05:47:52 PM PDT 24
Peak memory 205712 kb
Host smart-12b6bdfb-8c4f-4853-a0dc-a7cec9839018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18218
19605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.1821819605
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.3028388304
Short name T1036
Test name
Test status
Simulation time 10219891666 ps
CPU time 13.23 seconds
Started Jun 05 05:45:49 PM PDT 24
Finished Jun 05 05:46:04 PM PDT 24
Peak memory 205744 kb
Host smart-be4feb78-4c5a-412b-b1e8-c7bae41cc17f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3028388304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.3028388304
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.2208234773
Short name T305
Test name
Test status
Simulation time 10052716967 ps
CPU time 13.18 seconds
Started Jun 05 05:45:52 PM PDT 24
Finished Jun 05 05:46:06 PM PDT 24
Peak memory 205736 kb
Host smart-587ed93e-b7f2-4fa7-82ad-3a91f66d3e23
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2208234773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.2208234773
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.3584224305
Short name T1370
Test name
Test status
Simulation time 10079118424 ps
CPU time 13.98 seconds
Started Jun 05 05:45:53 PM PDT 24
Finished Jun 05 05:46:08 PM PDT 24
Peak memory 205676 kb
Host smart-ecc770d7-04e1-4915-94a5-dea1c7bf46f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35842
24305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.3584224305
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.357857753
Short name T1516
Test name
Test status
Simulation time 14126876289 ps
CPU time 18 seconds
Started Jun 05 05:45:51 PM PDT 24
Finished Jun 05 05:46:11 PM PDT 24
Peak memory 205676 kb
Host smart-bc32f1b7-2a95-430c-b006-91d59d1e57d3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=357857753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.357857753
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.48103132
Short name T1760
Test name
Test status
Simulation time 23221485080 ps
CPU time 26.54 seconds
Started Jun 05 05:45:46 PM PDT 24
Finished Jun 05 05:46:13 PM PDT 24
Peak memory 205796 kb
Host smart-8b3772e3-9ef9-4bf6-8b48-3603f115f3cf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=48103132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.48103132
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.152814306
Short name T82
Test name
Test status
Simulation time 10059166422 ps
CPU time 15.52 seconds
Started Jun 05 05:45:50 PM PDT 24
Finished Jun 05 05:46:06 PM PDT 24
Peak memory 205648 kb
Host smart-f26979d0-a208-4ba4-82ad-1af744d3824c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15281
4306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.152814306
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.458450085
Short name T831
Test name
Test status
Simulation time 10574034825 ps
CPU time 16.68 seconds
Started Jun 05 05:45:43 PM PDT 24
Finished Jun 05 05:46:00 PM PDT 24
Peak memory 205960 kb
Host smart-2a4c9633-01d1-40c5-815b-329991e3d874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45845
0085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.458450085
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.967841512
Short name T534
Test name
Test status
Simulation time 10064261240 ps
CPU time 14.79 seconds
Started Jun 05 05:45:52 PM PDT 24
Finished Jun 05 05:46:08 PM PDT 24
Peak memory 205732 kb
Host smart-acacba28-8c7e-4a56-833b-1bf71b356e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96784
1512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.967841512
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.456412938
Short name T1820
Test name
Test status
Simulation time 10056074519 ps
CPU time 14.99 seconds
Started Jun 05 05:45:43 PM PDT 24
Finished Jun 05 05:45:59 PM PDT 24
Peak memory 205636 kb
Host smart-e0d3d41e-9fbd-43c0-9658-89045882f0d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45641
2938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.456412938
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.3105212587
Short name T867
Test name
Test status
Simulation time 10820061853 ps
CPU time 15.05 seconds
Started Jun 05 05:45:44 PM PDT 24
Finished Jun 05 05:46:00 PM PDT 24
Peak memory 205636 kb
Host smart-46e321e4-59fd-4c34-a4e0-cbeae64a1938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31052
12587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.3105212587
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2472070715
Short name T937
Test name
Test status
Simulation time 10062961650 ps
CPU time 14.49 seconds
Started Jun 05 05:45:45 PM PDT 24
Finished Jun 05 05:46:00 PM PDT 24
Peak memory 205664 kb
Host smart-c7855e74-2481-4bb0-a420-40d623958ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24720
70715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2472070715
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.3193799764
Short name T1467
Test name
Test status
Simulation time 10138185715 ps
CPU time 14.37 seconds
Started Jun 05 05:45:53 PM PDT 24
Finished Jun 05 05:46:08 PM PDT 24
Peak memory 205676 kb
Host smart-bb983fcf-d0af-43a8-a5af-be1c8589d2d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31937
99764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.3193799764
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.3426549133
Short name T1937
Test name
Test status
Simulation time 10046378857 ps
CPU time 12.62 seconds
Started Jun 05 05:45:56 PM PDT 24
Finished Jun 05 05:46:10 PM PDT 24
Peak memory 205604 kb
Host smart-6b53f67c-bd9a-44bf-823c-a5ee930acfa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34265
49133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.3426549133
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.3952072143
Short name T1711
Test name
Test status
Simulation time 10096268157 ps
CPU time 13.77 seconds
Started Jun 05 05:45:54 PM PDT 24
Finished Jun 05 05:46:09 PM PDT 24
Peak memory 205724 kb
Host smart-8e0124ed-4cfa-40d1-b982-620769e5362f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39520
72143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.3952072143
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.421754010
Short name T473
Test name
Test status
Simulation time 10099593687 ps
CPU time 16.25 seconds
Started Jun 05 05:45:54 PM PDT 24
Finished Jun 05 05:46:11 PM PDT 24
Peak memory 205772 kb
Host smart-a2899ba5-4aed-4c13-97ab-52f70862e980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42175
4010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.421754010
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.4208173433
Short name T1247
Test name
Test status
Simulation time 13180407496 ps
CPU time 15.98 seconds
Started Jun 05 05:45:50 PM PDT 24
Finished Jun 05 05:46:07 PM PDT 24
Peak memory 205732 kb
Host smart-857877c0-6b6d-44b8-92d4-228814f60ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42081
73433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.4208173433
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3481010347
Short name T449
Test name
Test status
Simulation time 10118956182 ps
CPU time 12.54 seconds
Started Jun 05 05:45:52 PM PDT 24
Finished Jun 05 05:46:06 PM PDT 24
Peak memory 205716 kb
Host smart-bd0f804d-bd7d-4c87-8e35-f6688ff7094b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34810
10347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3481010347
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.3688723262
Short name T1780
Test name
Test status
Simulation time 19994023374 ps
CPU time 109.9 seconds
Started Jun 05 05:45:49 PM PDT 24
Finished Jun 05 05:47:39 PM PDT 24
Peak memory 205704 kb
Host smart-417bf37e-9995-49b8-bc8a-f925b8a2d07c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36887
23262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.3688723262
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.578022700
Short name T658
Test name
Test status
Simulation time 10057518124 ps
CPU time 13.18 seconds
Started Jun 05 05:45:52 PM PDT 24
Finished Jun 05 05:46:07 PM PDT 24
Peak memory 205656 kb
Host smart-0224969b-ac90-4ffd-968a-9b4d37fec335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57802
2700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.578022700
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3076547856
Short name T2015
Test name
Test status
Simulation time 10100257978 ps
CPU time 13.84 seconds
Started Jun 05 05:45:52 PM PDT 24
Finished Jun 05 05:46:07 PM PDT 24
Peak memory 205736 kb
Host smart-04322553-c615-42a0-a198-5a5114691f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30765
47856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3076547856
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.3189540217
Short name T1299
Test name
Test status
Simulation time 10117967733 ps
CPU time 14.47 seconds
Started Jun 05 05:45:50 PM PDT 24
Finished Jun 05 05:46:06 PM PDT 24
Peak memory 205528 kb
Host smart-9ce36fcb-d8b4-4e80-ad60-25bd027ae069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31895
40217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.3189540217
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1420056942
Short name T1795
Test name
Test status
Simulation time 10078315501 ps
CPU time 13.25 seconds
Started Jun 05 05:45:56 PM PDT 24
Finished Jun 05 05:46:10 PM PDT 24
Peak memory 205688 kb
Host smart-7376b51f-e727-43a6-84fb-04a11afbde3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14200
56942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1420056942
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2969053416
Short name T1257
Test name
Test status
Simulation time 10103509751 ps
CPU time 13.13 seconds
Started Jun 05 05:45:52 PM PDT 24
Finished Jun 05 05:46:06 PM PDT 24
Peak memory 205736 kb
Host smart-62d18dbb-8475-4852-92ba-a0b15213a154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29690
53416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2969053416
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.1937561585
Short name T135
Test name
Test status
Simulation time 10062321624 ps
CPU time 13.57 seconds
Started Jun 05 05:45:50 PM PDT 24
Finished Jun 05 05:46:04 PM PDT 24
Peak memory 205676 kb
Host smart-6cb1ab1f-23dd-48c3-9e9c-8d79e7aa884c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19375
61585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.1937561585
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_eop_single_bit_handling.1156382391
Short name T732
Test name
Test status
Simulation time 10071130531 ps
CPU time 14.45 seconds
Started Jun 05 05:45:52 PM PDT 24
Finished Jun 05 05:46:08 PM PDT 24
Peak memory 205656 kb
Host smart-dabc6c3e-9228-4e5c-9db9-2f3956dffd78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11563
82391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_eop_single_bit_handling.1156382391
Directory /workspace/13.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.4124857685
Short name T1671
Test name
Test status
Simulation time 10073091345 ps
CPU time 13.4 seconds
Started Jun 05 05:45:50 PM PDT 24
Finished Jun 05 05:46:04 PM PDT 24
Peak memory 205920 kb
Host smart-c3fa39d9-59ca-40fb-9934-0e517f2f410a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41248
57685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.4124857685
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.188846988
Short name T1278
Test name
Test status
Simulation time 10041628386 ps
CPU time 13.15 seconds
Started Jun 05 05:45:53 PM PDT 24
Finished Jun 05 05:46:07 PM PDT 24
Peak memory 205756 kb
Host smart-80f93c22-d97e-479a-8b16-aec7c65343b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18884
6988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.188846988
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.838878321
Short name T1353
Test name
Test status
Simulation time 22871821530 ps
CPU time 40.93 seconds
Started Jun 05 05:45:56 PM PDT 24
Finished Jun 05 05:46:38 PM PDT 24
Peak memory 205632 kb
Host smart-f682da14-dd65-42c2-a46c-1837a35fa760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83887
8321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.838878321
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.1141334370
Short name T1123
Test name
Test status
Simulation time 10084064318 ps
CPU time 15.51 seconds
Started Jun 05 05:45:54 PM PDT 24
Finished Jun 05 05:46:10 PM PDT 24
Peak memory 205692 kb
Host smart-87c00c71-3ba9-4761-ade9-aeab369ba600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11413
34370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.1141334370
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.275690839
Short name T1906
Test name
Test status
Simulation time 10089118706 ps
CPU time 14.86 seconds
Started Jun 05 05:45:54 PM PDT 24
Finished Jun 05 05:46:10 PM PDT 24
Peak memory 205716 kb
Host smart-de7ccbe2-cccd-485a-84ee-817f5997d319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27569
0839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.275690839
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.4092131580
Short name T1720
Test name
Test status
Simulation time 10068756101 ps
CPU time 13.55 seconds
Started Jun 05 05:45:58 PM PDT 24
Finished Jun 05 05:46:12 PM PDT 24
Peak memory 205744 kb
Host smart-72db34d3-5ea5-4845-8d0f-58d476071c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40921
31580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.4092131580
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.408385332
Short name T1471
Test name
Test status
Simulation time 10039394750 ps
CPU time 13.47 seconds
Started Jun 05 05:45:51 PM PDT 24
Finished Jun 05 05:46:05 PM PDT 24
Peak memory 205732 kb
Host smart-0901b9e7-bdda-4e92-899a-6906a3728aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40838
5332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.408385332
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.1895310731
Short name T341
Test name
Test status
Simulation time 10070123177 ps
CPU time 13.65 seconds
Started Jun 05 05:45:51 PM PDT 24
Finished Jun 05 05:46:06 PM PDT 24
Peak memory 205884 kb
Host smart-a6fceadc-8d8a-4c7b-a353-771018ca5506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18953
10731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.1895310731
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.760695800
Short name T1245
Test name
Test status
Simulation time 10119901996 ps
CPU time 14.53 seconds
Started Jun 05 05:45:51 PM PDT 24
Finished Jun 05 05:46:07 PM PDT 24
Peak memory 205756 kb
Host smart-e4ffa61f-b5c2-40f7-8e28-1aa52e168fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76069
5800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.760695800
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.851109641
Short name T927
Test name
Test status
Simulation time 10086936634 ps
CPU time 13.15 seconds
Started Jun 05 05:45:52 PM PDT 24
Finished Jun 05 05:46:07 PM PDT 24
Peak memory 205684 kb
Host smart-f4429a3a-fe83-4913-b429-5e2ab5d604e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85110
9641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.851109641
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.3547534772
Short name T329
Test name
Test status
Simulation time 10087433978 ps
CPU time 15.45 seconds
Started Jun 05 05:45:51 PM PDT 24
Finished Jun 05 05:46:07 PM PDT 24
Peak memory 205664 kb
Host smart-3979ceaf-e8ab-4734-846e-a1490684bbf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35475
34772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.3547534772
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.576290904
Short name T1957
Test name
Test status
Simulation time 21659561042 ps
CPU time 99.72 seconds
Started Jun 05 05:45:54 PM PDT 24
Finished Jun 05 05:47:35 PM PDT 24
Peak memory 205616 kb
Host smart-1ec2a11e-9cf8-46ff-8bd1-aaa7621eb81d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57629
0904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.576290904
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.2367412895
Short name T1719
Test name
Test status
Simulation time 10134682856 ps
CPU time 13.98 seconds
Started Jun 05 05:46:03 PM PDT 24
Finished Jun 05 05:46:17 PM PDT 24
Peak memory 205684 kb
Host smart-093d4021-1c06-4767-87b4-0b07f4053396
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2367412895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.2367412895
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.286966404
Short name T765
Test name
Test status
Simulation time 10073327148 ps
CPU time 13.6 seconds
Started Jun 05 05:46:01 PM PDT 24
Finished Jun 05 05:46:15 PM PDT 24
Peak memory 205748 kb
Host smart-1380d17e-38de-4267-9534-45ac467fa1c0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=286966404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.286966404
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.529216256
Short name T1929
Test name
Test status
Simulation time 10068211549 ps
CPU time 14.11 seconds
Started Jun 05 05:45:59 PM PDT 24
Finished Jun 05 05:46:14 PM PDT 24
Peak memory 205760 kb
Host smart-38ec89bb-7f7c-4e36-b581-55bba3010eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52921
6256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.529216256
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.620733769
Short name T1936
Test name
Test status
Simulation time 13378018575 ps
CPU time 16.77 seconds
Started Jun 05 05:45:52 PM PDT 24
Finished Jun 05 05:46:10 PM PDT 24
Peak memory 205712 kb
Host smart-f20d965b-4a9b-4d3e-918c-6bf0c40b8795
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=620733769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.620733769
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.3813853367
Short name T1750
Test name
Test status
Simulation time 23223499442 ps
CPU time 24.97 seconds
Started Jun 05 05:45:49 PM PDT 24
Finished Jun 05 05:46:15 PM PDT 24
Peak memory 205716 kb
Host smart-830dac45-0f0f-4a1b-8b4f-29d65ca2c3dd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3813853367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.3813853367
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.3662216644
Short name T613
Test name
Test status
Simulation time 10052386457 ps
CPU time 12.8 seconds
Started Jun 05 05:45:51 PM PDT 24
Finished Jun 05 05:46:05 PM PDT 24
Peak memory 205732 kb
Host smart-10a12020-2ca8-4051-9e57-856102ef27b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36622
16644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3662216644
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.4142534779
Short name T796
Test name
Test status
Simulation time 11023476861 ps
CPU time 15.41 seconds
Started Jun 05 05:45:50 PM PDT 24
Finished Jun 05 05:46:06 PM PDT 24
Peak memory 205996 kb
Host smart-e42c7691-106a-4e99-9527-6de74e145df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41425
34779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.4142534779
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.3676901577
Short name T916
Test name
Test status
Simulation time 10069205051 ps
CPU time 13.78 seconds
Started Jun 05 05:46:00 PM PDT 24
Finished Jun 05 05:46:14 PM PDT 24
Peak memory 205680 kb
Host smart-d74583ff-945a-4025-8665-e1caec76ad6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36769
01577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.3676901577
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.2122989722
Short name T463
Test name
Test status
Simulation time 10047858689 ps
CPU time 15.44 seconds
Started Jun 05 05:45:53 PM PDT 24
Finished Jun 05 05:46:09 PM PDT 24
Peak memory 205656 kb
Host smart-37fbf4f5-2902-4243-b55b-ffa6fdfd08a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21229
89722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.2122989722
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.3570723256
Short name T1705
Test name
Test status
Simulation time 10851205862 ps
CPU time 14.81 seconds
Started Jun 05 05:45:52 PM PDT 24
Finished Jun 05 05:46:08 PM PDT 24
Peak memory 205688 kb
Host smart-50ce83a3-ab66-4a0a-81a1-d67650fe6eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35707
23256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.3570723256
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.1445738977
Short name T376
Test name
Test status
Simulation time 10053860741 ps
CPU time 13.4 seconds
Started Jun 05 05:45:59 PM PDT 24
Finished Jun 05 05:46:13 PM PDT 24
Peak memory 205800 kb
Host smart-1aa201aa-651f-422a-9149-e39061f8d6ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14457
38977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.1445738977
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3388268875
Short name T1049
Test name
Test status
Simulation time 10107092150 ps
CPU time 15.48 seconds
Started Jun 05 05:46:00 PM PDT 24
Finished Jun 05 05:46:16 PM PDT 24
Peak memory 205680 kb
Host smart-2894916b-559c-4af7-a106-4b832157589e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33882
68875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3388268875
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2518158048
Short name T1806
Test name
Test status
Simulation time 10151832769 ps
CPU time 13.77 seconds
Started Jun 05 05:45:50 PM PDT 24
Finished Jun 05 05:46:05 PM PDT 24
Peak memory 205644 kb
Host smart-89a43aaf-e154-4e16-ba89-4d74d4798fe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25181
58048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2518158048
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.3968930943
Short name T1513
Test name
Test status
Simulation time 10103352462 ps
CPU time 13.84 seconds
Started Jun 05 05:45:52 PM PDT 24
Finished Jun 05 05:46:08 PM PDT 24
Peak memory 205680 kb
Host smart-8b95e1ce-0f6a-4be2-a68c-1afef24dcfd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39689
30943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.3968930943
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.2133192121
Short name T1899
Test name
Test status
Simulation time 13156720579 ps
CPU time 17.95 seconds
Started Jun 05 05:45:56 PM PDT 24
Finished Jun 05 05:46:15 PM PDT 24
Peak memory 205716 kb
Host smart-ffccc83d-7b2d-4154-a6f2-73dac8d7b8c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21331
92121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.2133192121
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.2523630316
Short name T1902
Test name
Test status
Simulation time 10113486106 ps
CPU time 15.16 seconds
Started Jun 05 05:46:00 PM PDT 24
Finished Jun 05 05:46:16 PM PDT 24
Peak memory 205736 kb
Host smart-1d2120a7-75a8-4743-9c8e-5a4a644273f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25236
30316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.2523630316
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.1456580507
Short name T1482
Test name
Test status
Simulation time 14437989908 ps
CPU time 57.65 seconds
Started Jun 05 05:45:59 PM PDT 24
Finished Jun 05 05:46:58 PM PDT 24
Peak memory 205712 kb
Host smart-079c4015-fc39-4e76-beb7-ba89ce0b04d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14565
80507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.1456580507
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.311253544
Short name T1070
Test name
Test status
Simulation time 10050400496 ps
CPU time 13.16 seconds
Started Jun 05 05:46:01 PM PDT 24
Finished Jun 05 05:46:15 PM PDT 24
Peak memory 205776 kb
Host smart-4c79224d-539e-4c5e-b3d1-3529460310af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31125
3544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.311253544
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.3625002321
Short name T328
Test name
Test status
Simulation time 10148970315 ps
CPU time 15.02 seconds
Started Jun 05 05:46:00 PM PDT 24
Finished Jun 05 05:46:16 PM PDT 24
Peak memory 205672 kb
Host smart-71888961-661b-467d-b66e-7c0aeaa23f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36250
02321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.3625002321
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.3018630208
Short name T904
Test name
Test status
Simulation time 10074729686 ps
CPU time 12.93 seconds
Started Jun 05 05:45:58 PM PDT 24
Finished Jun 05 05:46:11 PM PDT 24
Peak memory 205684 kb
Host smart-2139ff9b-b994-4038-879a-bb5c9c086f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30186
30208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.3018630208
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1983304035
Short name T886
Test name
Test status
Simulation time 10058992030 ps
CPU time 13.01 seconds
Started Jun 05 05:45:58 PM PDT 24
Finished Jun 05 05:46:11 PM PDT 24
Peak memory 205704 kb
Host smart-4b7e3e5b-318f-4203-994b-486df90b85ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19833
04035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1983304035
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.3578342
Short name T168
Test name
Test status
Simulation time 10058984050 ps
CPU time 14.16 seconds
Started Jun 05 05:46:00 PM PDT 24
Finished Jun 05 05:46:15 PM PDT 24
Peak memory 205668 kb
Host smart-e64e4215-d55c-44de-addf-4b2d93b94b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35783
42 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.3578342
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_eop_single_bit_handling.1774622730
Short name T1266
Test name
Test status
Simulation time 10061554728 ps
CPU time 12.66 seconds
Started Jun 05 05:46:00 PM PDT 24
Finished Jun 05 05:46:13 PM PDT 24
Peak memory 205616 kb
Host smart-c7bcdfb0-208f-4b0a-94af-9698ccb4704b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17746
22730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_eop_single_bit_handling.1774622730
Directory /workspace/14.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.4117682443
Short name T1744
Test name
Test status
Simulation time 10090226270 ps
CPU time 13.99 seconds
Started Jun 05 05:45:55 PM PDT 24
Finished Jun 05 05:46:10 PM PDT 24
Peak memory 205784 kb
Host smart-3c871e16-8b7f-49aa-a43f-f6fccf00611f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41176
82443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.4117682443
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3824543153
Short name T1547
Test name
Test status
Simulation time 10050915067 ps
CPU time 14.08 seconds
Started Jun 05 05:45:57 PM PDT 24
Finished Jun 05 05:46:12 PM PDT 24
Peak memory 205652 kb
Host smart-4f770f2b-c5bc-48c3-ba50-c96a91f66210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38245
43153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3824543153
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.2575756045
Short name T1712
Test name
Test status
Simulation time 28057409627 ps
CPU time 57.44 seconds
Started Jun 05 05:45:56 PM PDT 24
Finished Jun 05 05:46:55 PM PDT 24
Peak memory 205652 kb
Host smart-acc7a8d9-c7bf-4552-b21a-266e2db85df8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25757
56045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.2575756045
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3829686665
Short name T1493
Test name
Test status
Simulation time 10093298108 ps
CPU time 13.58 seconds
Started Jun 05 05:45:59 PM PDT 24
Finished Jun 05 05:46:13 PM PDT 24
Peak memory 205736 kb
Host smart-45362549-435b-47d6-b8bb-aa7e73f95fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38296
86665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3829686665
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.312511739
Short name T1512
Test name
Test status
Simulation time 10065043521 ps
CPU time 13.14 seconds
Started Jun 05 05:46:08 PM PDT 24
Finished Jun 05 05:46:22 PM PDT 24
Peak memory 205584 kb
Host smart-76420946-b935-4c7f-b095-c1a507997556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31251
1739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.312511739
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.2960650546
Short name T1603
Test name
Test status
Simulation time 10100106796 ps
CPU time 14.93 seconds
Started Jun 05 05:45:59 PM PDT 24
Finished Jun 05 05:46:15 PM PDT 24
Peak memory 205668 kb
Host smart-1435b9e1-51b1-4f3a-9e04-91903f4568b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29606
50546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.2960650546
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.2595494146
Short name T763
Test name
Test status
Simulation time 10056971401 ps
CPU time 14.79 seconds
Started Jun 05 05:45:58 PM PDT 24
Finished Jun 05 05:46:14 PM PDT 24
Peak memory 205648 kb
Host smart-4e29d8bf-a5a2-4e63-ab23-926d9de19600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25954
94146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.2595494146
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.2090250766
Short name T710
Test name
Test status
Simulation time 10056698327 ps
CPU time 13.19 seconds
Started Jun 05 05:46:01 PM PDT 24
Finished Jun 05 05:46:15 PM PDT 24
Peak memory 205692 kb
Host smart-a0165255-0bc4-47ed-8c66-6693c877cbfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20902
50766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.2090250766
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.1799684721
Short name T1315
Test name
Test status
Simulation time 10060651973 ps
CPU time 12.96 seconds
Started Jun 05 05:45:59 PM PDT 24
Finished Jun 05 05:46:13 PM PDT 24
Peak memory 205708 kb
Host smart-ccf3fe4e-896a-43cf-99bc-8b614663a7a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17996
84721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.1799684721
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.912667493
Short name T1564
Test name
Test status
Simulation time 10189580347 ps
CPU time 14 seconds
Started Jun 05 05:45:52 PM PDT 24
Finished Jun 05 05:46:08 PM PDT 24
Peak memory 205748 kb
Host smart-80bdd93c-f253-4e1e-9373-7188f20c43c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91266
7493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.912667493
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.3331525993
Short name T1265
Test name
Test status
Simulation time 10055856661 ps
CPU time 14.08 seconds
Started Jun 05 05:45:58 PM PDT 24
Finished Jun 05 05:46:13 PM PDT 24
Peak memory 205780 kb
Host smart-3624f416-48bc-4b92-bb21-9266fab69d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33315
25993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.3331525993
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.2108119565
Short name T918
Test name
Test status
Simulation time 10083703798 ps
CPU time 13.38 seconds
Started Jun 05 05:45:57 PM PDT 24
Finished Jun 05 05:46:11 PM PDT 24
Peak memory 205652 kb
Host smart-391fe010-abb1-4ced-8352-6ae2b3bf759a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21081
19565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.2108119565
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.2730455026
Short name T2006
Test name
Test status
Simulation time 22016114245 ps
CPU time 98.93 seconds
Started Jun 05 05:46:00 PM PDT 24
Finished Jun 05 05:47:39 PM PDT 24
Peak memory 205928 kb
Host smart-5acd78cf-ed6a-4178-b0b5-aac8e60841fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27304
55026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.2730455026
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.3809778620
Short name T2026
Test name
Test status
Simulation time 10134610874 ps
CPU time 13.47 seconds
Started Jun 05 05:46:04 PM PDT 24
Finished Jun 05 05:46:17 PM PDT 24
Peak memory 205780 kb
Host smart-dffbdcaa-e07c-4a1a-b425-e1a82c744deb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3809778620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.3809778620
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.1820332018
Short name T686
Test name
Test status
Simulation time 10102733050 ps
CPU time 15.12 seconds
Started Jun 05 05:46:07 PM PDT 24
Finished Jun 05 05:46:23 PM PDT 24
Peak memory 205808 kb
Host smart-5944afc7-6e43-4393-9c70-b4034babc780
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1820332018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.1820332018
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.2354181559
Short name T1617
Test name
Test status
Simulation time 10146017032 ps
CPU time 15.85 seconds
Started Jun 05 05:46:04 PM PDT 24
Finished Jun 05 05:46:20 PM PDT 24
Peak memory 205756 kb
Host smart-f3a9e419-a9a4-4c15-b4a9-421512f209ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23541
81559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.2354181559
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.1719646964
Short name T1013
Test name
Test status
Simulation time 14066362499 ps
CPU time 16.12 seconds
Started Jun 05 05:46:08 PM PDT 24
Finished Jun 05 05:46:25 PM PDT 24
Peak memory 205784 kb
Host smart-5017f774-2bf0-4b98-a35e-7082f51bbac2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1719646964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.1719646964
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.3579572932
Short name T1748
Test name
Test status
Simulation time 10049265123 ps
CPU time 15.93 seconds
Started Jun 05 05:46:01 PM PDT 24
Finished Jun 05 05:46:17 PM PDT 24
Peak memory 205608 kb
Host smart-0b8303c1-409e-403c-a30b-e00ef46c1542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35795
72932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.3579572932
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.1319181859
Short name T1159
Test name
Test status
Simulation time 10121165809 ps
CPU time 13.39 seconds
Started Jun 05 05:46:02 PM PDT 24
Finished Jun 05 05:46:16 PM PDT 24
Peak memory 205552 kb
Host smart-5bd9547a-c7e1-4310-aa2c-f9b90f7c574b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13191
81859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.1319181859
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.1157070798
Short name T1357
Test name
Test status
Simulation time 10037623249 ps
CPU time 13.49 seconds
Started Jun 05 05:46:05 PM PDT 24
Finished Jun 05 05:46:19 PM PDT 24
Peak memory 205720 kb
Host smart-80a717d9-f582-4a5a-8312-0f0e21785b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11570
70798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.1157070798
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.2216152529
Short name T1307
Test name
Test status
Simulation time 10054989110 ps
CPU time 14.07 seconds
Started Jun 05 05:46:08 PM PDT 24
Finished Jun 05 05:46:22 PM PDT 24
Peak memory 205712 kb
Host smart-8da66209-5fe2-4f09-a9a6-4e2b59052132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22161
52529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.2216152529
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.1559492413
Short name T120
Test name
Test status
Simulation time 10722829991 ps
CPU time 16.59 seconds
Started Jun 05 05:45:59 PM PDT 24
Finished Jun 05 05:46:16 PM PDT 24
Peak memory 205696 kb
Host smart-f9476b0b-f912-40ac-9445-67ddc83c93d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15594
92413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.1559492413
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2424311815
Short name T1089
Test name
Test status
Simulation time 10087326273 ps
CPU time 14.33 seconds
Started Jun 05 05:46:08 PM PDT 24
Finished Jun 05 05:46:23 PM PDT 24
Peak memory 205672 kb
Host smart-9d717416-6619-4b8a-b8fb-1695d9851133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24243
11815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2424311815
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.1434283
Short name T2014
Test name
Test status
Simulation time 10109905468 ps
CPU time 15.59 seconds
Started Jun 05 05:46:03 PM PDT 24
Finished Jun 05 05:46:20 PM PDT 24
Peak memory 205784 kb
Host smart-b65f1469-2ba3-46e5-81f2-dcec90d58f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14342
83 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.1434283
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.4126602820
Short name T1560
Test name
Test status
Simulation time 10045669663 ps
CPU time 15.65 seconds
Started Jun 05 05:46:07 PM PDT 24
Finished Jun 05 05:46:24 PM PDT 24
Peak memory 205712 kb
Host smart-c0f603ef-5558-4a99-b1e8-fb81cf9bf788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41266
02820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.4126602820
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2263995884
Short name T1007
Test name
Test status
Simulation time 10071836633 ps
CPU time 13.3 seconds
Started Jun 05 05:45:59 PM PDT 24
Finished Jun 05 05:46:13 PM PDT 24
Peak memory 205700 kb
Host smart-6f4cdb83-7b9a-4407-805c-fc84937abe40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22639
95884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2263995884
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.17982927
Short name T2003
Test name
Test status
Simulation time 10114129618 ps
CPU time 14.08 seconds
Started Jun 05 05:45:58 PM PDT 24
Finished Jun 05 05:46:13 PM PDT 24
Peak memory 205792 kb
Host smart-6f72e51c-42e6-468f-810b-b43d3d99e904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17982
927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.17982927
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.3021838988
Short name T1195
Test name
Test status
Simulation time 13200288331 ps
CPU time 19.08 seconds
Started Jun 05 05:46:03 PM PDT 24
Finished Jun 05 05:46:22 PM PDT 24
Peak memory 205712 kb
Host smart-a81f54b9-187d-4749-9fad-c40ec138cd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30218
38988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.3021838988
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.2253564767
Short name T1978
Test name
Test status
Simulation time 10080103552 ps
CPU time 12.96 seconds
Started Jun 05 05:46:05 PM PDT 24
Finished Jun 05 05:46:18 PM PDT 24
Peak memory 205708 kb
Host smart-1560d3f7-4564-4b64-bc33-58c76a544a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22535
64767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.2253564767
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.2479872302
Short name T746
Test name
Test status
Simulation time 18791529458 ps
CPU time 78.49 seconds
Started Jun 05 05:46:04 PM PDT 24
Finished Jun 05 05:47:23 PM PDT 24
Peak memory 205656 kb
Host smart-e1f11e75-7f8f-4fcf-a3b0-6f21044e72b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24798
72302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.2479872302
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.2490327523
Short name T28
Test name
Test status
Simulation time 10067311975 ps
CPU time 14.12 seconds
Started Jun 05 05:46:05 PM PDT 24
Finished Jun 05 05:46:19 PM PDT 24
Peak memory 205840 kb
Host smart-20244ef6-ea1c-4036-b112-cd2a1a1f0273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24903
27523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.2490327523
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.79200950
Short name T1756
Test name
Test status
Simulation time 10069612243 ps
CPU time 16.64 seconds
Started Jun 05 05:46:06 PM PDT 24
Finished Jun 05 05:46:23 PM PDT 24
Peak memory 205760 kb
Host smart-10586750-71de-4a28-b767-3d3ad672b336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79200
950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.79200950
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.3108123629
Short name T1833
Test name
Test status
Simulation time 10065543488 ps
CPU time 15.11 seconds
Started Jun 05 05:46:07 PM PDT 24
Finished Jun 05 05:46:23 PM PDT 24
Peak memory 205756 kb
Host smart-dbea7af4-b2ed-4883-ba72-006ef8d43347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31081
23629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3108123629
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.2921111594
Short name T842
Test name
Test status
Simulation time 10084585359 ps
CPU time 15.83 seconds
Started Jun 05 05:46:03 PM PDT 24
Finished Jun 05 05:46:19 PM PDT 24
Peak memory 205760 kb
Host smart-7f7e3050-e44c-4179-88b8-71215d9b50f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29211
11594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2921111594
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.339191896
Short name T982
Test name
Test status
Simulation time 10047776044 ps
CPU time 14.94 seconds
Started Jun 05 05:46:11 PM PDT 24
Finished Jun 05 05:46:26 PM PDT 24
Peak memory 205780 kb
Host smart-a6be984f-cd97-4117-8529-a522664c7658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33919
1896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.339191896
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_eop_single_bit_handling.1737690560
Short name T1681
Test name
Test status
Simulation time 10085374785 ps
CPU time 13.5 seconds
Started Jun 05 05:46:05 PM PDT 24
Finished Jun 05 05:46:19 PM PDT 24
Peak memory 205676 kb
Host smart-73fff0f9-df4d-4024-85aa-a8786a7bc7a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17376
90560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_eop_single_bit_handling.1737690560
Directory /workspace/15.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.815889572
Short name T830
Test name
Test status
Simulation time 10046019316 ps
CPU time 14.54 seconds
Started Jun 05 05:46:06 PM PDT 24
Finished Jun 05 05:46:22 PM PDT 24
Peak memory 205616 kb
Host smart-22ec3ba9-aba3-4029-a881-f69d5c22d2fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81588
9572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.815889572
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3198545075
Short name T1879
Test name
Test status
Simulation time 10035941889 ps
CPU time 12.99 seconds
Started Jun 05 05:46:06 PM PDT 24
Finished Jun 05 05:46:20 PM PDT 24
Peak memory 205692 kb
Host smart-9db4f387-6ffd-4f87-b73b-e0e1306c7541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31985
45075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3198545075
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.673739880
Short name T1853
Test name
Test status
Simulation time 19151957803 ps
CPU time 32.88 seconds
Started Jun 05 05:46:06 PM PDT 24
Finished Jun 05 05:46:40 PM PDT 24
Peak memory 205728 kb
Host smart-66918e21-7836-4a5c-ab71-a77ed927da6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67373
9880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.673739880
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.4168796286
Short name T455
Test name
Test status
Simulation time 10070198091 ps
CPU time 13.61 seconds
Started Jun 05 05:46:05 PM PDT 24
Finished Jun 05 05:46:20 PM PDT 24
Peak memory 205792 kb
Host smart-9a3afbad-16e4-4fe3-acb8-d2b9f603b334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41687
96286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.4168796286
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.2070741473
Short name T994
Test name
Test status
Simulation time 10070458722 ps
CPU time 14.82 seconds
Started Jun 05 05:46:10 PM PDT 24
Finished Jun 05 05:46:26 PM PDT 24
Peak memory 205712 kb
Host smart-89245250-e0d5-4fa5-810e-f3155d34a397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20707
41473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2070741473
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.343316843
Short name T1023
Test name
Test status
Simulation time 10105302615 ps
CPU time 13.4 seconds
Started Jun 05 05:46:05 PM PDT 24
Finished Jun 05 05:46:18 PM PDT 24
Peak memory 205640 kb
Host smart-92f5fa2f-b994-4189-b6be-95022e8d63c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34331
6843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.343316843
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.626015577
Short name T681
Test name
Test status
Simulation time 10051163526 ps
CPU time 14.69 seconds
Started Jun 05 05:46:07 PM PDT 24
Finished Jun 05 05:46:22 PM PDT 24
Peak memory 205732 kb
Host smart-7637b9a9-f4b2-4abe-8565-a26cdb009a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62601
5577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.626015577
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2798596923
Short name T1984
Test name
Test status
Simulation time 10087457477 ps
CPU time 14.03 seconds
Started Jun 05 05:46:10 PM PDT 24
Finished Jun 05 05:46:24 PM PDT 24
Peak memory 205696 kb
Host smart-7ce06721-6c5b-4a30-a69e-cef8a653ee57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27985
96923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2798596923
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.730599104
Short name T935
Test name
Test status
Simulation time 10063555744 ps
CPU time 12.92 seconds
Started Jun 05 05:46:06 PM PDT 24
Finished Jun 05 05:46:20 PM PDT 24
Peak memory 205676 kb
Host smart-e0ed14e5-2a4e-46ae-aeaf-75b6b2328644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73059
9104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.730599104
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.580439549
Short name T1599
Test name
Test status
Simulation time 10156603477 ps
CPU time 16.73 seconds
Started Jun 05 05:45:58 PM PDT 24
Finished Jun 05 05:46:15 PM PDT 24
Peak memory 205672 kb
Host smart-fbed8d85-69a9-41ba-9f94-688df3a77e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58043
9549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.580439549
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.3139013442
Short name T256
Test name
Test status
Simulation time 10092568491 ps
CPU time 13.53 seconds
Started Jun 05 05:46:10 PM PDT 24
Finished Jun 05 05:46:24 PM PDT 24
Peak memory 205732 kb
Host smart-dd26f77d-57a6-4169-bbd7-7c8ac88a500a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31390
13442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.3139013442
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.1515273370
Short name T1969
Test name
Test status
Simulation time 10123803286 ps
CPU time 13.83 seconds
Started Jun 05 05:46:05 PM PDT 24
Finished Jun 05 05:46:20 PM PDT 24
Peak memory 205764 kb
Host smart-7beffee1-8d1f-4e0a-a547-f5bb242b1e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15152
73370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.1515273370
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.2889169651
Short name T1980
Test name
Test status
Simulation time 16751052785 ps
CPU time 76.06 seconds
Started Jun 05 05:46:05 PM PDT 24
Finished Jun 05 05:47:22 PM PDT 24
Peak memory 205704 kb
Host smart-0ff46129-c5c0-4759-a0e4-86cf362a1371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28891
69651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.2889169651
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.3386413082
Short name T729
Test name
Test status
Simulation time 10154765370 ps
CPU time 13.37 seconds
Started Jun 05 05:46:17 PM PDT 24
Finished Jun 05 05:46:31 PM PDT 24
Peak memory 205612 kb
Host smart-e8e38de7-5b43-4bb3-bebf-7c2a2afc34ae
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3386413082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.3386413082
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.480802730
Short name T1050
Test name
Test status
Simulation time 10072714906 ps
CPU time 13.37 seconds
Started Jun 05 05:46:15 PM PDT 24
Finished Jun 05 05:46:29 PM PDT 24
Peak memory 205652 kb
Host smart-89ca6a13-d175-4d44-8625-88f33dd72aef
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=480802730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.480802730
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.3649382009
Short name T1000
Test name
Test status
Simulation time 10076404770 ps
CPU time 12.62 seconds
Started Jun 05 05:46:11 PM PDT 24
Finished Jun 05 05:46:24 PM PDT 24
Peak memory 205728 kb
Host smart-9362852c-8567-419d-bdd6-ce544e6eca9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36493
82009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.3649382009
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.3751990816
Short name T8
Test name
Test status
Simulation time 23229147662 ps
CPU time 25.53 seconds
Started Jun 05 05:46:04 PM PDT 24
Finished Jun 05 05:46:30 PM PDT 24
Peak memory 205704 kb
Host smart-be0a2fc4-9d5f-4c2b-80af-0ae3ead83e76
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3751990816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.3751990816
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.4200683938
Short name T312
Test name
Test status
Simulation time 10060351511 ps
CPU time 15.88 seconds
Started Jun 05 05:46:06 PM PDT 24
Finished Jun 05 05:46:23 PM PDT 24
Peak memory 205736 kb
Host smart-2ad0835d-04fb-42cf-bbc9-a4366ec54153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42006
83938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.4200683938
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.2091556151
Short name T840
Test name
Test status
Simulation time 10155222602 ps
CPU time 13.86 seconds
Started Jun 05 05:46:08 PM PDT 24
Finished Jun 05 05:46:22 PM PDT 24
Peak memory 205664 kb
Host smart-a69c18a7-bd36-4d5f-9eae-fd1e3f2b1840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20915
56151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.2091556151
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.3196668069
Short name T571
Test name
Test status
Simulation time 10070210412 ps
CPU time 12.69 seconds
Started Jun 05 05:46:13 PM PDT 24
Finished Jun 05 05:46:26 PM PDT 24
Peak memory 205748 kb
Host smart-def42795-3176-4545-83f3-3f4dd610f875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31966
68069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.3196668069
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.3054412338
Short name T1464
Test name
Test status
Simulation time 10053568314 ps
CPU time 15.08 seconds
Started Jun 05 05:46:05 PM PDT 24
Finished Jun 05 05:46:21 PM PDT 24
Peak memory 205624 kb
Host smart-a4eff511-e266-48c1-8d7c-2b685691a4e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30544
12338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.3054412338
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.484319588
Short name T1423
Test name
Test status
Simulation time 10819444611 ps
CPU time 15.69 seconds
Started Jun 05 05:46:05 PM PDT 24
Finished Jun 05 05:46:21 PM PDT 24
Peak memory 205740 kb
Host smart-605d6f38-59d3-4036-90c9-09587a8ec26b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48431
9588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.484319588
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3516004587
Short name T1695
Test name
Test status
Simulation time 10091498519 ps
CPU time 14.92 seconds
Started Jun 05 05:46:06 PM PDT 24
Finished Jun 05 05:46:22 PM PDT 24
Peak memory 205648 kb
Host smart-070a8300-9b8e-4f56-b719-4edb25d34195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35160
04587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3516004587
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.2611661991
Short name T453
Test name
Test status
Simulation time 10126992525 ps
CPU time 13.82 seconds
Started Jun 05 05:46:15 PM PDT 24
Finished Jun 05 05:46:29 PM PDT 24
Peak memory 205748 kb
Host smart-eb7a9ae4-97b0-421b-8eca-7d199cc6c744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26116
61991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.2611661991
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.3770429981
Short name T1808
Test name
Test status
Simulation time 10043143296 ps
CPU time 14.05 seconds
Started Jun 05 05:46:11 PM PDT 24
Finished Jun 05 05:46:26 PM PDT 24
Peak memory 205872 kb
Host smart-338914f1-67e1-4e87-8258-b1fa36147d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37704
29981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3770429981
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.2993681873
Short name T941
Test name
Test status
Simulation time 10113507180 ps
CPU time 13.42 seconds
Started Jun 05 05:46:16 PM PDT 24
Finished Jun 05 05:46:30 PM PDT 24
Peak memory 205652 kb
Host smart-c2054cb7-b993-4d74-a528-966bb6ad1ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29936
81873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.2993681873
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.1814319194
Short name T203
Test name
Test status
Simulation time 10110597701 ps
CPU time 12.89 seconds
Started Jun 05 05:46:11 PM PDT 24
Finished Jun 05 05:46:25 PM PDT 24
Peak memory 205680 kb
Host smart-fe2421a6-df54-4e22-9437-ef100a12d4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18143
19194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.1814319194
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.1782056575
Short name T1531
Test name
Test status
Simulation time 13244835293 ps
CPU time 16.54 seconds
Started Jun 05 05:46:13 PM PDT 24
Finished Jun 05 05:46:30 PM PDT 24
Peak memory 205780 kb
Host smart-8b5b5b14-239d-4f2b-bb92-ff161f8c7f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17820
56575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.1782056575
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.2284957887
Short name T753
Test name
Test status
Simulation time 10110330212 ps
CPU time 13.32 seconds
Started Jun 05 05:46:14 PM PDT 24
Finished Jun 05 05:46:28 PM PDT 24
Peak memory 205756 kb
Host smart-49f11822-6d76-42eb-9490-b674fc3b70f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22849
57887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.2284957887
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.879816064
Short name T1554
Test name
Test status
Simulation time 19643460588 ps
CPU time 271.29 seconds
Started Jun 05 05:46:16 PM PDT 24
Finished Jun 05 05:50:48 PM PDT 24
Peak memory 205656 kb
Host smart-309c2fd2-36ce-4cad-af0b-f85b92da3235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87981
6064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.879816064
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1778015207
Short name T615
Test name
Test status
Simulation time 10040082688 ps
CPU time 13.09 seconds
Started Jun 05 05:46:16 PM PDT 24
Finished Jun 05 05:46:30 PM PDT 24
Peak memory 205752 kb
Host smart-8a30c104-ebd6-43ea-81fc-677a6f44bcd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17780
15207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1778015207
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.4233662761
Short name T1722
Test name
Test status
Simulation time 10108610566 ps
CPU time 14.94 seconds
Started Jun 05 05:46:13 PM PDT 24
Finished Jun 05 05:46:28 PM PDT 24
Peak memory 205812 kb
Host smart-d3665203-d24c-4ca9-8c59-6ec04d7a6774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42336
62761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.4233662761
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.1541862715
Short name T1831
Test name
Test status
Simulation time 10074034096 ps
CPU time 15.17 seconds
Started Jun 05 05:46:12 PM PDT 24
Finished Jun 05 05:46:28 PM PDT 24
Peak memory 205736 kb
Host smart-108c6616-dfb5-42f6-ae13-041464b28b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15418
62715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1541862715
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.786442554
Short name T1311
Test name
Test status
Simulation time 10044637179 ps
CPU time 15.96 seconds
Started Jun 05 05:46:14 PM PDT 24
Finished Jun 05 05:46:30 PM PDT 24
Peak memory 205780 kb
Host smart-56943faf-2f8f-4841-beba-684fcfd0fb0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78644
2554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.786442554
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.4085025041
Short name T1925
Test name
Test status
Simulation time 10058814959 ps
CPU time 14.2 seconds
Started Jun 05 05:46:14 PM PDT 24
Finished Jun 05 05:46:29 PM PDT 24
Peak memory 205680 kb
Host smart-50a5b063-523d-40db-b622-4dce20f0687d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40850
25041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.4085025041
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_eop_single_bit_handling.599207418
Short name T1421
Test name
Test status
Simulation time 10100728417 ps
CPU time 14.52 seconds
Started Jun 05 05:46:12 PM PDT 24
Finished Jun 05 05:46:27 PM PDT 24
Peak memory 205636 kb
Host smart-7f947054-d201-455a-8e33-5a7b27ed85ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59920
7418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_eop_single_bit_handling.599207418
Directory /workspace/16.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1207770743
Short name T706
Test name
Test status
Simulation time 10033939775 ps
CPU time 15.97 seconds
Started Jun 05 05:46:14 PM PDT 24
Finished Jun 05 05:46:31 PM PDT 24
Peak memory 205692 kb
Host smart-6a2b0e54-2d89-4f7b-aea5-93b7f4853f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12077
70743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1207770743
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.1290632139
Short name T40
Test name
Test status
Simulation time 10074468144 ps
CPU time 14.09 seconds
Started Jun 05 05:46:17 PM PDT 24
Finished Jun 05 05:46:32 PM PDT 24
Peak memory 205720 kb
Host smart-5482061b-63a1-4258-a356-2c3f3e147bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12906
32139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.1290632139
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3281443909
Short name T1169
Test name
Test status
Simulation time 20552681597 ps
CPU time 36.2 seconds
Started Jun 05 05:46:14 PM PDT 24
Finished Jun 05 05:46:51 PM PDT 24
Peak memory 205684 kb
Host smart-a9a473ea-3afd-409a-b97b-2a742581156c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32814
43909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3281443909
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3843749798
Short name T314
Test name
Test status
Simulation time 10090737782 ps
CPU time 13.76 seconds
Started Jun 05 05:46:18 PM PDT 24
Finished Jun 05 05:46:33 PM PDT 24
Peak memory 205540 kb
Host smart-49ba6beb-b3d3-47e5-9bec-0e5a239e0bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38437
49798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3843749798
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.2972735304
Short name T1029
Test name
Test status
Simulation time 10086754294 ps
CPU time 13.1 seconds
Started Jun 05 05:46:19 PM PDT 24
Finished Jun 05 05:46:33 PM PDT 24
Peak memory 205700 kb
Host smart-473ea66d-f34f-4cb3-b60e-47c8846cc47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29727
35304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.2972735304
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.2304445854
Short name T343
Test name
Test status
Simulation time 10052251977 ps
CPU time 13.86 seconds
Started Jun 05 05:46:14 PM PDT 24
Finished Jun 05 05:46:29 PM PDT 24
Peak memory 205672 kb
Host smart-b31795b7-7113-4a06-b1bb-c73af6de1ec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23044
45854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.2304445854
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.2235509177
Short name T1963
Test name
Test status
Simulation time 10058001185 ps
CPU time 12.94 seconds
Started Jun 05 05:46:14 PM PDT 24
Finished Jun 05 05:46:28 PM PDT 24
Peak memory 205664 kb
Host smart-10fb7989-6028-4c6a-955f-942b46629db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22355
09177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.2235509177
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.1779200845
Short name T1858
Test name
Test status
Simulation time 10134683310 ps
CPU time 15.3 seconds
Started Jun 05 05:46:13 PM PDT 24
Finished Jun 05 05:46:29 PM PDT 24
Peak memory 205712 kb
Host smart-ea1a5270-4e0f-47dc-ab83-ea885f577803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17792
00845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.1779200845
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.3910260821
Short name T1609
Test name
Test status
Simulation time 10057844480 ps
CPU time 12.66 seconds
Started Jun 05 05:46:18 PM PDT 24
Finished Jun 05 05:46:32 PM PDT 24
Peak memory 205616 kb
Host smart-dae79c91-df06-4f5d-b291-fda12a0ccfc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39102
60821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.3910260821
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.2911917463
Short name T1304
Test name
Test status
Simulation time 10159353536 ps
CPU time 16.19 seconds
Started Jun 05 05:46:07 PM PDT 24
Finished Jun 05 05:46:24 PM PDT 24
Peak memory 205632 kb
Host smart-7083e416-51a4-4fcd-a7a5-fc74ae24d9d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29119
17463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2911917463
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.1924656049
Short name T1270
Test name
Test status
Simulation time 10103320811 ps
CPU time 13.26 seconds
Started Jun 05 05:46:13 PM PDT 24
Finished Jun 05 05:46:27 PM PDT 24
Peak memory 205700 kb
Host smart-e7ae6eb7-7b90-44ef-9dd0-bffccb2c07c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19246
56049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.1924656049
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.3667658320
Short name T775
Test name
Test status
Simulation time 10075478192 ps
CPU time 13.51 seconds
Started Jun 05 05:46:15 PM PDT 24
Finished Jun 05 05:46:29 PM PDT 24
Peak memory 205676 kb
Host smart-c3fedd71-e2f9-4f41-94c2-9e57eab9c3d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36676
58320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.3667658320
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.3801093588
Short name T1690
Test name
Test status
Simulation time 23237143337 ps
CPU time 364.67 seconds
Started Jun 05 05:46:16 PM PDT 24
Finished Jun 05 05:52:21 PM PDT 24
Peak memory 205636 kb
Host smart-0fabdab2-b809-4dc5-8321-4530f676e5da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38010
93588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.3801093588
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.1985867879
Short name T722
Test name
Test status
Simulation time 10163883784 ps
CPU time 13.68 seconds
Started Jun 05 05:46:22 PM PDT 24
Finished Jun 05 05:46:37 PM PDT 24
Peak memory 205480 kb
Host smart-636d09f5-d832-4572-92eb-9ed5c898d31d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1985867879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.1985867879
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.3281256453
Short name T1852
Test name
Test status
Simulation time 10106662699 ps
CPU time 12.91 seconds
Started Jun 05 05:46:18 PM PDT 24
Finished Jun 05 05:46:31 PM PDT 24
Peak memory 205660 kb
Host smart-8de23f57-4a23-4f5c-827d-d68b6f06fdf1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3281256453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.3281256453
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.3679228794
Short name T647
Test name
Test status
Simulation time 10131393029 ps
CPU time 15.94 seconds
Started Jun 05 05:46:19 PM PDT 24
Finished Jun 05 05:46:36 PM PDT 24
Peak memory 205760 kb
Host smart-319bc2b7-4e57-4e72-92fe-94906db76fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36792
28794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.3679228794
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.1032551955
Short name T1379
Test name
Test status
Simulation time 13797704047 ps
CPU time 19.47 seconds
Started Jun 05 05:46:14 PM PDT 24
Finished Jun 05 05:46:34 PM PDT 24
Peak memory 205748 kb
Host smart-65af2e0b-135f-48a8-aa44-3c5b19598c32
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1032551955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.1032551955
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.1796022805
Short name T7
Test name
Test status
Simulation time 23392113744 ps
CPU time 24.81 seconds
Started Jun 05 05:46:15 PM PDT 24
Finished Jun 05 05:46:40 PM PDT 24
Peak memory 205668 kb
Host smart-69ef4521-f22b-4caf-a87b-bdb28ceb0b58
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1796022805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.1796022805
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.1067262457
Short name T1443
Test name
Test status
Simulation time 10065697667 ps
CPU time 12.76 seconds
Started Jun 05 05:46:17 PM PDT 24
Finished Jun 05 05:46:31 PM PDT 24
Peak memory 205720 kb
Host smart-8a3c569c-f996-480a-aebb-638eb53c243d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10672
62457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.1067262457
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1511972100
Short name T1600
Test name
Test status
Simulation time 10584106072 ps
CPU time 15.21 seconds
Started Jun 05 05:46:16 PM PDT 24
Finished Jun 05 05:46:32 PM PDT 24
Peak memory 205628 kb
Host smart-28821e27-b98d-4f5d-8007-1266d7f0db42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15119
72100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1511972100
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.462659370
Short name T644
Test name
Test status
Simulation time 10048645928 ps
CPU time 14.47 seconds
Started Jun 05 05:46:18 PM PDT 24
Finished Jun 05 05:46:34 PM PDT 24
Peak memory 205636 kb
Host smart-cc3bbc6c-c009-47df-95ae-a209f8e8b3dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46265
9370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.462659370
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.1793457708
Short name T1593
Test name
Test status
Simulation time 10052019749 ps
CPU time 15.09 seconds
Started Jun 05 05:46:12 PM PDT 24
Finished Jun 05 05:46:28 PM PDT 24
Peak memory 205636 kb
Host smart-4de60b54-7060-4ec9-9194-8f02915008da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17934
57708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1793457708
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.632460213
Short name T599
Test name
Test status
Simulation time 10915515224 ps
CPU time 14.75 seconds
Started Jun 05 05:46:17 PM PDT 24
Finished Jun 05 05:46:32 PM PDT 24
Peak memory 205764 kb
Host smart-3aa14b1c-5434-471c-925b-bf61b5f8c5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63246
0213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.632460213
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.3669929502
Short name T1313
Test name
Test status
Simulation time 10087587624 ps
CPU time 16.15 seconds
Started Jun 05 05:46:15 PM PDT 24
Finished Jun 05 05:46:32 PM PDT 24
Peak memory 205592 kb
Host smart-5e388870-ce6d-43df-a58c-a08432e158cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36699
29502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.3669929502
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.4173791919
Short name T1409
Test name
Test status
Simulation time 10055333378 ps
CPU time 13.56 seconds
Started Jun 05 05:46:20 PM PDT 24
Finished Jun 05 05:46:34 PM PDT 24
Peak memory 205644 kb
Host smart-4a8e8cb2-68b0-4a72-ae34-75b23b540b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41737
91919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.4173791919
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.1323882597
Short name T885
Test name
Test status
Simulation time 10075027018 ps
CPU time 13.78 seconds
Started Jun 05 05:46:21 PM PDT 24
Finished Jun 05 05:46:35 PM PDT 24
Peak memory 205732 kb
Host smart-f3164510-00f5-42eb-9ac3-abd3f9956508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13238
82597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.1323882597
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3801874327
Short name T551
Test name
Test status
Simulation time 10072370767 ps
CPU time 12.55 seconds
Started Jun 05 05:46:16 PM PDT 24
Finished Jun 05 05:46:29 PM PDT 24
Peak memory 205716 kb
Host smart-39cb978e-7c06-4b27-b2c6-d954570d928d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38018
74327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3801874327
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.3934051457
Short name T825
Test name
Test status
Simulation time 10086862502 ps
CPU time 15.7 seconds
Started Jun 05 05:46:15 PM PDT 24
Finished Jun 05 05:46:31 PM PDT 24
Peak memory 205620 kb
Host smart-88281c91-1c93-49f0-aae1-b83bcec43afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39340
51457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.3934051457
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.1159073924
Short name T1541
Test name
Test status
Simulation time 13208984789 ps
CPU time 15.52 seconds
Started Jun 05 05:46:19 PM PDT 24
Finished Jun 05 05:46:35 PM PDT 24
Peak memory 205636 kb
Host smart-adf861c6-0583-496a-be01-2bb1e915bc2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11590
73924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.1159073924
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.3612460601
Short name T1213
Test name
Test status
Simulation time 10099946353 ps
CPU time 13.03 seconds
Started Jun 05 05:46:18 PM PDT 24
Finished Jun 05 05:46:32 PM PDT 24
Peak memory 205720 kb
Host smart-8e26564b-aadc-4745-b002-261462227bde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36124
60601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3612460601
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.2736938617
Short name T1650
Test name
Test status
Simulation time 16275510644 ps
CPU time 197.26 seconds
Started Jun 05 05:46:16 PM PDT 24
Finished Jun 05 05:49:34 PM PDT 24
Peak memory 205656 kb
Host smart-69443ca9-015b-44f3-819d-81e2c7b4055e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27369
38617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.2736938617
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1900491180
Short name T856
Test name
Test status
Simulation time 10086805947 ps
CPU time 14.57 seconds
Started Jun 05 05:46:14 PM PDT 24
Finished Jun 05 05:46:29 PM PDT 24
Peak memory 205780 kb
Host smart-6e658ed7-2e7a-4199-8d5e-49b21d979e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19004
91180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1900491180
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.4223109845
Short name T1819
Test name
Test status
Simulation time 10102841542 ps
CPU time 12.86 seconds
Started Jun 05 05:46:17 PM PDT 24
Finished Jun 05 05:46:30 PM PDT 24
Peak memory 205796 kb
Host smart-afa28845-8a21-496c-bc14-5ac28c773c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42231
09845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.4223109845
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.673701076
Short name T1251
Test name
Test status
Simulation time 10089762540 ps
CPU time 13.43 seconds
Started Jun 05 05:46:17 PM PDT 24
Finished Jun 05 05:46:31 PM PDT 24
Peak memory 205756 kb
Host smart-b280fd53-2ded-4567-a61d-643519729268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67370
1076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.673701076
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.3421884282
Short name T1778
Test name
Test status
Simulation time 10078931050 ps
CPU time 13.87 seconds
Started Jun 05 05:46:20 PM PDT 24
Finished Jun 05 05:46:34 PM PDT 24
Peak memory 205752 kb
Host smart-cb283ef7-d7d8-4017-890c-b875422071c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34218
84282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.3421884282
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1208981028
Short name T821
Test name
Test status
Simulation time 10092462180 ps
CPU time 12.98 seconds
Started Jun 05 05:46:16 PM PDT 24
Finished Jun 05 05:46:29 PM PDT 24
Peak memory 205684 kb
Host smart-704d95c5-c51f-4c68-9ca3-1e05d00aa10a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12089
81028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1208981028
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1469490976
Short name T793
Test name
Test status
Simulation time 10052688037 ps
CPU time 12.68 seconds
Started Jun 05 05:46:20 PM PDT 24
Finished Jun 05 05:46:33 PM PDT 24
Peak memory 205668 kb
Host smart-b5f0d3e2-8723-4261-bafd-da43aca60395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14694
90976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1469490976
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_eop_single_bit_handling.1157669018
Short name T347
Test name
Test status
Simulation time 10072687871 ps
CPU time 15.68 seconds
Started Jun 05 05:46:21 PM PDT 24
Finished Jun 05 05:46:37 PM PDT 24
Peak memory 205664 kb
Host smart-2f525350-352e-442a-8d16-cf3832889036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11576
69018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_eop_single_bit_handling.1157669018
Directory /workspace/17.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3826646994
Short name T868
Test name
Test status
Simulation time 10060148804 ps
CPU time 14.34 seconds
Started Jun 05 05:46:22 PM PDT 24
Finished Jun 05 05:46:37 PM PDT 24
Peak memory 205768 kb
Host smart-f0b984f0-60de-47bd-a03a-8229ed5d50ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38266
46994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.3826646994
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.1818483322
Short name T41
Test name
Test status
Simulation time 10035559417 ps
CPU time 14.01 seconds
Started Jun 05 05:46:19 PM PDT 24
Finished Jun 05 05:46:34 PM PDT 24
Peak memory 205912 kb
Host smart-e6ca26c2-720c-4c49-bc2c-3381dfba29f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18184
83322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.1818483322
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.1251453011
Short name T85
Test name
Test status
Simulation time 19725501880 ps
CPU time 41.27 seconds
Started Jun 05 05:46:25 PM PDT 24
Finished Jun 05 05:47:06 PM PDT 24
Peak memory 205668 kb
Host smart-1404bfe4-a92f-4b9f-9e6e-d0dfcaf80c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12514
53011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.1251453011
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1934309909
Short name T1051
Test name
Test status
Simulation time 10090712796 ps
CPU time 15.17 seconds
Started Jun 05 05:46:21 PM PDT 24
Finished Jun 05 05:46:36 PM PDT 24
Peak memory 205752 kb
Host smart-fa8e5dec-2366-4914-862c-23394565457f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19343
09909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1934309909
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.1966579328
Short name T1829
Test name
Test status
Simulation time 10081504076 ps
CPU time 12.79 seconds
Started Jun 05 05:46:19 PM PDT 24
Finished Jun 05 05:46:33 PM PDT 24
Peak memory 205728 kb
Host smart-36293f19-c07e-4a99-a20a-4b11fe3c9da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19665
79328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.1966579328
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.2534448629
Short name T1916
Test name
Test status
Simulation time 10065860863 ps
CPU time 12.74 seconds
Started Jun 05 05:46:19 PM PDT 24
Finished Jun 05 05:46:33 PM PDT 24
Peak memory 205664 kb
Host smart-ba2f296b-0e12-42b1-9f65-616c9465e309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25344
48629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.2534448629
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.1636664391
Short name T1682
Test name
Test status
Simulation time 10046061577 ps
CPU time 12.81 seconds
Started Jun 05 05:46:23 PM PDT 24
Finished Jun 05 05:46:36 PM PDT 24
Peak memory 205772 kb
Host smart-ff4fbed4-f798-4bf0-ae9e-b9a076028a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16366
64391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.1636664391
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3348277803
Short name T1326
Test name
Test status
Simulation time 10077936463 ps
CPU time 13.32 seconds
Started Jun 05 05:46:22 PM PDT 24
Finished Jun 05 05:46:36 PM PDT 24
Peak memory 205612 kb
Host smart-e7efe710-20c2-4918-9673-fed2457567e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33482
77803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3348277803
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.1970633460
Short name T914
Test name
Test status
Simulation time 10073755556 ps
CPU time 13.48 seconds
Started Jun 05 05:46:17 PM PDT 24
Finished Jun 05 05:46:30 PM PDT 24
Peak memory 205808 kb
Host smart-0f49958b-7a0f-4a8f-a0e6-54c7d27f23fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19706
33460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.1970633460
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2367323983
Short name T2013
Test name
Test status
Simulation time 10067632309 ps
CPU time 13.76 seconds
Started Jun 05 05:46:18 PM PDT 24
Finished Jun 05 05:46:32 PM PDT 24
Peak memory 205732 kb
Host smart-73ffa259-f05f-434c-a596-9fd28bf4c9bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23673
23983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2367323983
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.3464480957
Short name T1448
Test name
Test status
Simulation time 10127027832 ps
CPU time 16.17 seconds
Started Jun 05 05:46:21 PM PDT 24
Finished Jun 05 05:46:37 PM PDT 24
Peak memory 205916 kb
Host smart-fcc5b0cc-28d8-4482-8491-93862e4bac17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34644
80957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.3464480957
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.2124294331
Short name T1998
Test name
Test status
Simulation time 23205210022 ps
CPU time 404.84 seconds
Started Jun 05 05:46:20 PM PDT 24
Finished Jun 05 05:53:05 PM PDT 24
Peak memory 205908 kb
Host smart-0f640ac7-ff26-4e92-b08e-3317778cec65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21242
94331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.2124294331
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.1986455743
Short name T1923
Test name
Test status
Simulation time 10157547834 ps
CPU time 13.04 seconds
Started Jun 05 05:46:26 PM PDT 24
Finished Jun 05 05:46:40 PM PDT 24
Peak memory 205652 kb
Host smart-26c623a2-e56a-450a-90be-db7f6abc4d59
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1986455743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.1986455743
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.1010415704
Short name T1017
Test name
Test status
Simulation time 10066555472 ps
CPU time 13.11 seconds
Started Jun 05 05:46:26 PM PDT 24
Finished Jun 05 05:46:40 PM PDT 24
Peak memory 205776 kb
Host smart-69c8df14-e627-402c-bccd-cd8f17ac186f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1010415704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.1010415704
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.2601594067
Short name T1612
Test name
Test status
Simulation time 10125946559 ps
CPU time 13.64 seconds
Started Jun 05 05:46:28 PM PDT 24
Finished Jun 05 05:46:42 PM PDT 24
Peak memory 205684 kb
Host smart-151db118-9358-4bd4-a75e-f0e8d3a447e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26015
94067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.2601594067
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.1536570795
Short name T447
Test name
Test status
Simulation time 13729204601 ps
CPU time 16.21 seconds
Started Jun 05 05:46:21 PM PDT 24
Finished Jun 05 05:46:38 PM PDT 24
Peak memory 205784 kb
Host smart-f083f4a4-93b1-4b51-9559-223915f710fb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1536570795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.1536570795
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.3578281521
Short name T836
Test name
Test status
Simulation time 23212074128 ps
CPU time 25.05 seconds
Started Jun 05 05:46:19 PM PDT 24
Finished Jun 05 05:46:45 PM PDT 24
Peak memory 205768 kb
Host smart-caeec41f-3ba8-492f-82dd-6c61eca60a03
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3578281521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.3578281521
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.39715677
Short name T1864
Test name
Test status
Simulation time 10058512246 ps
CPU time 14.05 seconds
Started Jun 05 05:46:19 PM PDT 24
Finished Jun 05 05:46:34 PM PDT 24
Peak memory 205780 kb
Host smart-cad0ac80-ac3d-4238-8224-94456f3f383a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39715
677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.39715677
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.4003246864
Short name T1530
Test name
Test status
Simulation time 11232079193 ps
CPU time 15.08 seconds
Started Jun 05 05:46:18 PM PDT 24
Finished Jun 05 05:46:34 PM PDT 24
Peak memory 205660 kb
Host smart-cb9bc21c-4dee-4444-a05e-af6c0ec66992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40032
46864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.4003246864
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.360456596
Short name T1146
Test name
Test status
Simulation time 10097003975 ps
CPU time 14.57 seconds
Started Jun 05 05:46:19 PM PDT 24
Finished Jun 05 05:46:35 PM PDT 24
Peak memory 205684 kb
Host smart-e1b6863c-1142-4f55-ba5a-3c4de96e6ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36045
6596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.360456596
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.3150895385
Short name T493
Test name
Test status
Simulation time 10078938275 ps
CPU time 13.27 seconds
Started Jun 05 05:46:21 PM PDT 24
Finished Jun 05 05:46:35 PM PDT 24
Peak memory 205652 kb
Host smart-acf9e187-242e-488d-8454-aaad5f009b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31508
95385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.3150895385
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.3393116981
Short name T1437
Test name
Test status
Simulation time 10655705253 ps
CPU time 13.7 seconds
Started Jun 05 05:46:23 PM PDT 24
Finished Jun 05 05:46:37 PM PDT 24
Peak memory 205728 kb
Host smart-7537620e-5ca4-47e5-9ce2-68a7b27a4ea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33931
16981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.3393116981
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2234152300
Short name T1240
Test name
Test status
Simulation time 10102453432 ps
CPU time 15.11 seconds
Started Jun 05 05:46:18 PM PDT 24
Finished Jun 05 05:46:34 PM PDT 24
Peak memory 205644 kb
Host smart-362c9da3-dbcb-428c-ade5-d0b2d1748e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22341
52300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2234152300
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.1813384137
Short name T669
Test name
Test status
Simulation time 10080177699 ps
CPU time 12.99 seconds
Started Jun 05 05:46:29 PM PDT 24
Finished Jun 05 05:46:43 PM PDT 24
Peak memory 205784 kb
Host smart-3776ab11-3c9c-484d-bfe4-637365c87738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18133
84137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.1813384137
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.369551679
Short name T1100
Test name
Test status
Simulation time 10040172308 ps
CPU time 12.98 seconds
Started Jun 05 05:46:27 PM PDT 24
Finished Jun 05 05:46:41 PM PDT 24
Peak memory 205708 kb
Host smart-9d1fa18a-fda5-4e9e-8869-77cb5b31c32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36955
1679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.369551679
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.105844925
Short name T1572
Test name
Test status
Simulation time 10128994722 ps
CPU time 17.08 seconds
Started Jun 05 05:46:25 PM PDT 24
Finished Jun 05 05:46:42 PM PDT 24
Peak memory 205764 kb
Host smart-1b29366b-2390-4b74-8e7b-8510485450a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10584
4925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.105844925
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.2758068846
Short name T593
Test name
Test status
Simulation time 10182974631 ps
CPU time 12.56 seconds
Started Jun 05 05:46:20 PM PDT 24
Finished Jun 05 05:46:33 PM PDT 24
Peak memory 205716 kb
Host smart-ab9d2342-da6c-4c78-b98b-3db8896e03ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27580
68846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.2758068846
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.2855533713
Short name T1934
Test name
Test status
Simulation time 13220690331 ps
CPU time 16.35 seconds
Started Jun 05 05:46:20 PM PDT 24
Finished Jun 05 05:46:37 PM PDT 24
Peak memory 205648 kb
Host smart-eeda737f-5169-4d0f-838d-518d906f1a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28555
33713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.2855533713
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.3298945693
Short name T586
Test name
Test status
Simulation time 10087887367 ps
CPU time 13.15 seconds
Started Jun 05 05:46:22 PM PDT 24
Finished Jun 05 05:46:35 PM PDT 24
Peak memory 205676 kb
Host smart-01971e33-5b88-4483-a841-761826fa0520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32989
45693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.3298945693
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.2485851076
Short name T826
Test name
Test status
Simulation time 18185719751 ps
CPU time 77.37 seconds
Started Jun 05 05:46:18 PM PDT 24
Finished Jun 05 05:47:37 PM PDT 24
Peak memory 205676 kb
Host smart-f990938a-7844-48ca-b202-db6022e81d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24858
51076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.2485851076
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1964405857
Short name T1177
Test name
Test status
Simulation time 10055175610 ps
CPU time 13.37 seconds
Started Jun 05 05:46:19 PM PDT 24
Finished Jun 05 05:46:34 PM PDT 24
Peak memory 205640 kb
Host smart-994d7237-533b-43aa-9152-e8f36d819f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19644
05857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1964405857
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.3942139896
Short name T601
Test name
Test status
Simulation time 10108270111 ps
CPU time 15.28 seconds
Started Jun 05 05:46:20 PM PDT 24
Finished Jun 05 05:46:36 PM PDT 24
Peak memory 205704 kb
Host smart-07e912da-9393-4945-8d38-939281911c97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39421
39896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.3942139896
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.2122582181
Short name T1481
Test name
Test status
Simulation time 10048530373 ps
CPU time 14.07 seconds
Started Jun 05 05:46:21 PM PDT 24
Finished Jun 05 05:46:35 PM PDT 24
Peak memory 205848 kb
Host smart-fd1a06b5-b561-4fc9-9a09-6febb9b498f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21225
82181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.2122582181
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.332528006
Short name T19
Test name
Test status
Simulation time 10058109345 ps
CPU time 12.93 seconds
Started Jun 05 05:46:23 PM PDT 24
Finished Jun 05 05:46:36 PM PDT 24
Peak memory 205724 kb
Host smart-0ac92328-2f68-4c50-be16-3b0c97671cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33252
8006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.332528006
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1867219400
Short name T123
Test name
Test status
Simulation time 10064423648 ps
CPU time 12.54 seconds
Started Jun 05 05:46:27 PM PDT 24
Finished Jun 05 05:46:40 PM PDT 24
Peak memory 205716 kb
Host smart-1ffb2215-bf51-480e-98a6-fd9224b3e0c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18672
19400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1867219400
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_eop_single_bit_handling.2550182759
Short name T619
Test name
Test status
Simulation time 10055781541 ps
CPU time 13.84 seconds
Started Jun 05 05:46:29 PM PDT 24
Finished Jun 05 05:46:44 PM PDT 24
Peak memory 205676 kb
Host smart-098f7e80-e5f0-4b98-aaa9-861d62094805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25501
82759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_eop_single_bit_handling.2550182759
Directory /workspace/18.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3449822373
Short name T1586
Test name
Test status
Simulation time 10045521618 ps
CPU time 13.58 seconds
Started Jun 05 05:46:27 PM PDT 24
Finished Jun 05 05:46:41 PM PDT 24
Peak memory 205812 kb
Host smart-4a073f93-6a0c-4efd-be87-088797c7c4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34498
22373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3449822373
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3345859633
Short name T1677
Test name
Test status
Simulation time 10052759821 ps
CPU time 13.83 seconds
Started Jun 05 05:46:26 PM PDT 24
Finished Jun 05 05:46:40 PM PDT 24
Peak memory 205932 kb
Host smart-7c7643b5-2199-4b1f-bffa-71b59ad98eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33458
59633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3345859633
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.4244512220
Short name T155
Test name
Test status
Simulation time 18426108048 ps
CPU time 30.38 seconds
Started Jun 05 05:46:26 PM PDT 24
Finished Jun 05 05:46:57 PM PDT 24
Peak memory 205664 kb
Host smart-416b8d59-6c64-4e16-a54c-c6c66299cada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42445
12220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.4244512220
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.1872844451
Short name T2005
Test name
Test status
Simulation time 10090536741 ps
CPU time 15.55 seconds
Started Jun 05 05:46:29 PM PDT 24
Finished Jun 05 05:46:45 PM PDT 24
Peak memory 205760 kb
Host smart-cb626a93-21b9-4ed5-95e8-30a63da60b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18728
44451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1872844451
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.4078967895
Short name T1498
Test name
Test status
Simulation time 10143800533 ps
CPU time 13.42 seconds
Started Jun 05 05:46:29 PM PDT 24
Finished Jun 05 05:46:43 PM PDT 24
Peak memory 205772 kb
Host smart-71d02aa4-aad5-470f-9322-5702718ea50d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40789
67895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.4078967895
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.1905130936
Short name T294
Test name
Test status
Simulation time 10054490543 ps
CPU time 13.66 seconds
Started Jun 05 05:46:29 PM PDT 24
Finished Jun 05 05:46:44 PM PDT 24
Peak memory 205648 kb
Host smart-84c6313d-e3d6-44e4-86fa-f3f372dabf07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19051
30936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.1905130936
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.2045109490
Short name T1911
Test name
Test status
Simulation time 10048439431 ps
CPU time 13.22 seconds
Started Jun 05 05:46:30 PM PDT 24
Finished Jun 05 05:46:43 PM PDT 24
Peak memory 205760 kb
Host smart-032a8cc5-7b60-46a6-9564-6e8fade74903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20451
09490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.2045109490
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.2232634524
Short name T136
Test name
Test status
Simulation time 10058556033 ps
CPU time 13.21 seconds
Started Jun 05 05:46:29 PM PDT 24
Finished Jun 05 05:46:43 PM PDT 24
Peak memory 205764 kb
Host smart-1e7c97fe-aae9-4332-9619-bea7ddb0db36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22326
34524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.2232634524
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1077227139
Short name T596
Test name
Test status
Simulation time 10046954964 ps
CPU time 13.61 seconds
Started Jun 05 05:46:27 PM PDT 24
Finished Jun 05 05:46:41 PM PDT 24
Peak memory 205648 kb
Host smart-2bae6b16-792a-4eb9-947f-7d2362e7ed82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10772
27139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1077227139
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.3223081933
Short name T1628
Test name
Test status
Simulation time 10111823824 ps
CPU time 13.65 seconds
Started Jun 05 05:46:19 PM PDT 24
Finished Jun 05 05:46:33 PM PDT 24
Peak memory 205920 kb
Host smart-2d58688b-614c-46dd-8155-3a2262e206e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32230
81933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.3223081933
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.2976163880
Short name T850
Test name
Test status
Simulation time 10082781526 ps
CPU time 16.38 seconds
Started Jun 05 05:46:30 PM PDT 24
Finished Jun 05 05:46:47 PM PDT 24
Peak memory 205752 kb
Host smart-977b59ab-867d-4f27-a3ad-4d0e67155d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29761
63880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.2976163880
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.2938122750
Short name T303
Test name
Test status
Simulation time 10081055247 ps
CPU time 13.52 seconds
Started Jun 05 05:46:24 PM PDT 24
Finished Jun 05 05:46:38 PM PDT 24
Peak memory 205680 kb
Host smart-80056b50-40a1-4e98-b92b-029cae45c26f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29381
22750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.2938122750
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.1297453959
Short name T353
Test name
Test status
Simulation time 13878628706 ps
CPU time 55.25 seconds
Started Jun 05 05:46:27 PM PDT 24
Finished Jun 05 05:47:23 PM PDT 24
Peak memory 205584 kb
Host smart-b9cfc6a7-9057-4c70-a022-3f8dea131602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12974
53959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.1297453959
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.2720038080
Short name T778
Test name
Test status
Simulation time 10145664520 ps
CPU time 14.2 seconds
Started Jun 05 05:46:36 PM PDT 24
Finished Jun 05 05:46:50 PM PDT 24
Peak memory 205600 kb
Host smart-66299775-bf0f-4c9e-a096-9262cd3e2999
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2720038080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.2720038080
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.2801602455
Short name T364
Test name
Test status
Simulation time 10065919859 ps
CPU time 15.86 seconds
Started Jun 05 05:46:31 PM PDT 24
Finished Jun 05 05:46:48 PM PDT 24
Peak memory 205780 kb
Host smart-b3f20449-c197-4d9d-8fa4-75406a50e47b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2801602455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.2801602455
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.3347553130
Short name T814
Test name
Test status
Simulation time 10124717026 ps
CPU time 14.38 seconds
Started Jun 05 05:46:31 PM PDT 24
Finished Jun 05 05:46:46 PM PDT 24
Peak memory 205716 kb
Host smart-74991561-28b1-4569-aed1-0dce2619e7fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33475
53130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.3347553130
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.1943388251
Short name T1002
Test name
Test status
Simulation time 13958666930 ps
CPU time 19.67 seconds
Started Jun 05 05:46:30 PM PDT 24
Finished Jun 05 05:46:50 PM PDT 24
Peak memory 205700 kb
Host smart-6e792402-aeb8-45ee-a9d5-d3d245e8729a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1943388251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.1943388251
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.3591942202
Short name T47
Test name
Test status
Simulation time 23259165346 ps
CPU time 28.27 seconds
Started Jun 05 05:46:28 PM PDT 24
Finished Jun 05 05:46:57 PM PDT 24
Peak memory 205772 kb
Host smart-2972f97c-2cc2-422f-9111-da00edcb5ced
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3591942202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.3591942202
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.70373592
Short name T1896
Test name
Test status
Simulation time 10051782039 ps
CPU time 14.99 seconds
Started Jun 05 05:46:29 PM PDT 24
Finished Jun 05 05:46:45 PM PDT 24
Peak memory 205792 kb
Host smart-852d06c8-d490-42e5-8c92-3e64b7695fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70373
592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.70373592
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.369247189
Short name T498
Test name
Test status
Simulation time 10044649907 ps
CPU time 14.07 seconds
Started Jun 05 05:46:30 PM PDT 24
Finished Jun 05 05:46:45 PM PDT 24
Peak memory 205724 kb
Host smart-12b675ad-298c-429e-b148-d97e86df7130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36924
7189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.369247189
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.2890105980
Short name T1730
Test name
Test status
Simulation time 10179154322 ps
CPU time 13.06 seconds
Started Jun 05 05:46:24 PM PDT 24
Finished Jun 05 05:46:38 PM PDT 24
Peak memory 205720 kb
Host smart-ca4de052-e110-4ac4-b564-3023d1e1e4cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28901
05980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.2890105980
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.3511479867
Short name T522
Test name
Test status
Simulation time 10089300872 ps
CPU time 15.66 seconds
Started Jun 05 05:46:34 PM PDT 24
Finished Jun 05 05:46:50 PM PDT 24
Peak memory 205700 kb
Host smart-ee2b7082-356d-4ac4-8e40-ba5bff418089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35114
79867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.3511479867
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.3562175829
Short name T1639
Test name
Test status
Simulation time 10070555929 ps
CPU time 12.83 seconds
Started Jun 05 05:46:25 PM PDT 24
Finished Jun 05 05:46:38 PM PDT 24
Peak memory 205684 kb
Host smart-117f9567-a620-4f46-bde4-9787da2942ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35621
75829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.3562175829
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.1119248881
Short name T1569
Test name
Test status
Simulation time 10656665385 ps
CPU time 13.69 seconds
Started Jun 05 05:46:26 PM PDT 24
Finished Jun 05 05:46:40 PM PDT 24
Peak memory 205808 kb
Host smart-3c35475b-e372-4d09-9bb3-d091b087a1eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11192
48881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.1119248881
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1072678209
Short name T957
Test name
Test status
Simulation time 10050963803 ps
CPU time 13.42 seconds
Started Jun 05 05:46:25 PM PDT 24
Finished Jun 05 05:46:39 PM PDT 24
Peak memory 205644 kb
Host smart-96c89f5a-068a-41a0-b861-1996c711cbda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10726
78209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1072678209
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3673845833
Short name T1905
Test name
Test status
Simulation time 10102857773 ps
CPU time 13.21 seconds
Started Jun 05 05:46:36 PM PDT 24
Finished Jun 05 05:46:50 PM PDT 24
Peak memory 205668 kb
Host smart-0592d436-a8e0-4914-8d38-53a55e0525fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36738
45833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3673845833
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.2333336903
Short name T589
Test name
Test status
Simulation time 10067642565 ps
CPU time 14.56 seconds
Started Jun 05 05:46:35 PM PDT 24
Finished Jun 05 05:46:50 PM PDT 24
Peak memory 205652 kb
Host smart-0a81894e-1989-4aab-aef0-1724c58a1031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23333
36903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.2333336903
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.1303763688
Short name T363
Test name
Test status
Simulation time 10160802128 ps
CPU time 13.43 seconds
Started Jun 05 05:46:25 PM PDT 24
Finished Jun 05 05:46:39 PM PDT 24
Peak memory 205540 kb
Host smart-7ce42de1-1829-468b-b976-eebb8d541fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13037
63688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.1303763688
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1352163156
Short name T1170
Test name
Test status
Simulation time 10110284647 ps
CPU time 13.76 seconds
Started Jun 05 05:46:27 PM PDT 24
Finished Jun 05 05:46:42 PM PDT 24
Peak memory 205760 kb
Host smart-9dff0fa4-e47b-4904-b3f9-90ac2aca2e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13521
63156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1352163156
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.4283953436
Short name T1784
Test name
Test status
Simulation time 13242916700 ps
CPU time 17.54 seconds
Started Jun 05 05:46:25 PM PDT 24
Finished Jun 05 05:46:43 PM PDT 24
Peak memory 205792 kb
Host smart-94f09cfd-2555-4122-b02c-d0489de19f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42839
53436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.4283953436
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1990748951
Short name T1388
Test name
Test status
Simulation time 10105026906 ps
CPU time 12.53 seconds
Started Jun 05 05:46:31 PM PDT 24
Finished Jun 05 05:46:44 PM PDT 24
Peak memory 205744 kb
Host smart-83a80fac-4695-47a1-8450-b3d79f5289e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19907
48951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1990748951
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.707603531
Short name T1047
Test name
Test status
Simulation time 22578622372 ps
CPU time 135.63 seconds
Started Jun 05 05:46:30 PM PDT 24
Finished Jun 05 05:48:46 PM PDT 24
Peak memory 205664 kb
Host smart-3042e403-52b4-43e4-a2db-cda10c17fb55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70760
3531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.707603531
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.2151544677
Short name T582
Test name
Test status
Simulation time 10049646946 ps
CPU time 13.4 seconds
Started Jun 05 05:46:34 PM PDT 24
Finished Jun 05 05:46:48 PM PDT 24
Peak memory 205752 kb
Host smart-f2defa89-4895-4952-b69b-06b7863032fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21515
44677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.2151544677
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2013284242
Short name T822
Test name
Test status
Simulation time 10102873869 ps
CPU time 16.22 seconds
Started Jun 05 05:46:34 PM PDT 24
Finished Jun 05 05:46:51 PM PDT 24
Peak memory 205780 kb
Host smart-4653d94c-c5a9-4570-964e-4248bbcc7efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20132
84242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2013284242
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.3503510712
Short name T685
Test name
Test status
Simulation time 10127939267 ps
CPU time 16.62 seconds
Started Jun 05 05:46:34 PM PDT 24
Finished Jun 05 05:46:52 PM PDT 24
Peak memory 205744 kb
Host smart-f5a3ffb1-e551-4d1f-854c-792b2b2739c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35035
10712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.3503510712
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.231014383
Short name T1253
Test name
Test status
Simulation time 10059863551 ps
CPU time 13.61 seconds
Started Jun 05 05:46:33 PM PDT 24
Finished Jun 05 05:46:47 PM PDT 24
Peak memory 205760 kb
Host smart-433112ad-c887-469f-9e44-5fa50be336a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23101
4383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.231014383
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.1698182495
Short name T1160
Test name
Test status
Simulation time 10085515765 ps
CPU time 15.93 seconds
Started Jun 05 05:46:34 PM PDT 24
Finished Jun 05 05:46:51 PM PDT 24
Peak memory 205656 kb
Host smart-70b3a09c-fef5-4dc8-ba02-d9b8d6eb6e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16981
82495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.1698182495
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.3994654306
Short name T29
Test name
Test status
Simulation time 10058889614 ps
CPU time 12.39 seconds
Started Jun 05 05:46:39 PM PDT 24
Finished Jun 05 05:46:52 PM PDT 24
Peak memory 205724 kb
Host smart-7afc8e40-6928-44ae-bb20-ae48c2eadb4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39946
54306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.3994654306
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_eop_single_bit_handling.3397113487
Short name T1287
Test name
Test status
Simulation time 10079059305 ps
CPU time 15.51 seconds
Started Jun 05 05:46:35 PM PDT 24
Finished Jun 05 05:46:51 PM PDT 24
Peak memory 205608 kb
Host smart-126ec88e-7a31-4d39-a3b3-d293d63574bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33971
13487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_eop_single_bit_handling.3397113487
Directory /workspace/19.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.1954498004
Short name T977
Test name
Test status
Simulation time 10049927487 ps
CPU time 13.07 seconds
Started Jun 05 05:46:37 PM PDT 24
Finished Jun 05 05:46:50 PM PDT 24
Peak memory 205688 kb
Host smart-76091658-906d-4836-8acc-391f97ca9bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19544
98004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.1954498004
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1807015081
Short name T1329
Test name
Test status
Simulation time 10073203598 ps
CPU time 15.76 seconds
Started Jun 05 05:46:37 PM PDT 24
Finished Jun 05 05:46:53 PM PDT 24
Peak memory 205768 kb
Host smart-c09888e2-2fa6-4743-9a2e-db905c6dd9ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18070
15081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1807015081
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.3941638732
Short name T171
Test name
Test status
Simulation time 20757492480 ps
CPU time 38.36 seconds
Started Jun 05 05:46:34 PM PDT 24
Finished Jun 05 05:47:13 PM PDT 24
Peak memory 205684 kb
Host smart-b1967cc3-65be-4266-a9b1-b47ba5c97aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39416
38732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.3941638732
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.2459841607
Short name T855
Test name
Test status
Simulation time 10056323202 ps
CPU time 14.63 seconds
Started Jun 05 05:46:38 PM PDT 24
Finished Jun 05 05:46:54 PM PDT 24
Peak memory 205616 kb
Host smart-daa4da52-91f2-4a80-9c67-281e4b6d8714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24598
41607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.2459841607
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.342188359
Short name T492
Test name
Test status
Simulation time 10079846894 ps
CPU time 14.18 seconds
Started Jun 05 05:46:36 PM PDT 24
Finished Jun 05 05:46:51 PM PDT 24
Peak memory 205656 kb
Host smart-41989143-0a0a-4a34-95da-89e4c431113f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34218
8359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.342188359
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.1860864817
Short name T1616
Test name
Test status
Simulation time 10051390186 ps
CPU time 16.48 seconds
Started Jun 05 05:46:35 PM PDT 24
Finished Jun 05 05:46:52 PM PDT 24
Peak memory 205728 kb
Host smart-08370349-1b15-4ed9-a70d-638824898c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18608
64817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.1860864817
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.1217392047
Short name T1793
Test name
Test status
Simulation time 10041839467 ps
CPU time 14.23 seconds
Started Jun 05 05:46:33 PM PDT 24
Finished Jun 05 05:46:47 PM PDT 24
Peak memory 205760 kb
Host smart-d19d92fc-9c58-412c-bd9c-ac0790a7a167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12173
92047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.1217392047
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.3350006894
Short name T17
Test name
Test status
Simulation time 10072412174 ps
CPU time 13.3 seconds
Started Jun 05 05:46:35 PM PDT 24
Finished Jun 05 05:46:49 PM PDT 24
Peak memory 205752 kb
Host smart-c2e47ad2-da44-49f9-96ad-ee6f3b111441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33500
06894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.3350006894
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.4271699982
Short name T1590
Test name
Test status
Simulation time 10050168444 ps
CPU time 13.78 seconds
Started Jun 05 05:46:33 PM PDT 24
Finished Jun 05 05:46:48 PM PDT 24
Peak memory 205756 kb
Host smart-178e5b3a-a1a4-4482-9b51-c63baf4a8d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42716
99982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.4271699982
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.1378087919
Short name T1503
Test name
Test status
Simulation time 10124456663 ps
CPU time 15.26 seconds
Started Jun 05 05:46:29 PM PDT 24
Finished Jun 05 05:46:45 PM PDT 24
Peak memory 205740 kb
Host smart-9dbccaf3-e79a-49ec-81d9-3423d65722ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13780
87919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.1378087919
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.3839699802
Short name T1716
Test name
Test status
Simulation time 10040679939 ps
CPU time 13.51 seconds
Started Jun 05 05:46:33 PM PDT 24
Finished Jun 05 05:46:47 PM PDT 24
Peak memory 205948 kb
Host smart-43df1eae-5e63-4819-bb1d-812a196fef77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38396
99802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.3839699802
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3653428097
Short name T1166
Test name
Test status
Simulation time 10065803666 ps
CPU time 14.01 seconds
Started Jun 05 05:46:35 PM PDT 24
Finished Jun 05 05:46:49 PM PDT 24
Peak memory 205716 kb
Host smart-88c74f9d-f0fc-4eed-9ee9-e986f7fc572c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36534
28097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3653428097
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.86150600
Short name T624
Test name
Test status
Simulation time 24733340917 ps
CPU time 147.07 seconds
Started Jun 05 05:46:32 PM PDT 24
Finished Jun 05 05:48:59 PM PDT 24
Peak memory 205952 kb
Host smart-944a2222-88e0-4c59-afa1-c27db671aa66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86150
600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.86150600
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.3329539665
Short name T745
Test name
Test status
Simulation time 10151329077 ps
CPU time 15.79 seconds
Started Jun 05 05:44:26 PM PDT 24
Finished Jun 05 05:44:42 PM PDT 24
Peak memory 205940 kb
Host smart-25ec46fa-3b43-4413-afa8-935651ab71de
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3329539665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.3329539665
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.2370822139
Short name T426
Test name
Test status
Simulation time 10050408722 ps
CPU time 15.79 seconds
Started Jun 05 05:44:22 PM PDT 24
Finished Jun 05 05:44:39 PM PDT 24
Peak memory 205700 kb
Host smart-ca5e0444-9eae-4224-b487-2aff60698d06
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2370822139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.2370822139
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.1601000697
Short name T1461
Test name
Test status
Simulation time 10127271988 ps
CPU time 13.18 seconds
Started Jun 05 05:44:22 PM PDT 24
Finished Jun 05 05:44:36 PM PDT 24
Peak memory 205704 kb
Host smart-7a47a2bb-9063-4aaf-8bbf-e0c92b8b0587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16010
00697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.1601000697
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.195724805
Short name T787
Test name
Test status
Simulation time 13570588707 ps
CPU time 17.76 seconds
Started Jun 05 05:44:16 PM PDT 24
Finished Jun 05 05:44:35 PM PDT 24
Peak memory 205604 kb
Host smart-9e914e62-62d1-4754-9684-d9197f98d57d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=195724805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.195724805
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.588479808
Short name T562
Test name
Test status
Simulation time 23189520572 ps
CPU time 25.65 seconds
Started Jun 05 05:44:29 PM PDT 24
Finished Jun 05 05:44:55 PM PDT 24
Peak memory 205820 kb
Host smart-6b0df110-3a4a-4b78-96ef-9a9f6ed76755
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=588479808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.588479808
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.3309586262
Short name T443
Test name
Test status
Simulation time 10052835056 ps
CPU time 13.65 seconds
Started Jun 05 05:44:29 PM PDT 24
Finished Jun 05 05:44:43 PM PDT 24
Peak memory 205792 kb
Host smart-ddc20e9f-5e18-4fbe-ab87-aa720e5b4cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33095
86262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.3309586262
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.1605144196
Short name T1904
Test name
Test status
Simulation time 10086778492 ps
CPU time 13.41 seconds
Started Jun 05 05:44:16 PM PDT 24
Finished Jun 05 05:44:30 PM PDT 24
Peak memory 205760 kb
Host smart-68d3d133-371f-49c2-8faa-9c3a0c7f74eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16051
44196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.1605144196
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.3509373478
Short name T1055
Test name
Test status
Simulation time 10590007965 ps
CPU time 13.53 seconds
Started Jun 05 05:44:21 PM PDT 24
Finished Jun 05 05:44:35 PM PDT 24
Peak memory 205732 kb
Host smart-486a0325-8515-4374-8ccc-8014cb9eb3d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35093
73478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.3509373478
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.1395775442
Short name T724
Test name
Test status
Simulation time 10049984094 ps
CPU time 12.98 seconds
Started Jun 05 05:44:14 PM PDT 24
Finished Jun 05 05:44:28 PM PDT 24
Peak memory 205720 kb
Host smart-2f12c1cb-99f0-4b5a-ab98-202cc06ccc3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13957
75442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.1395775442
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.698206530
Short name T1290
Test name
Test status
Simulation time 10068051134 ps
CPU time 13.14 seconds
Started Jun 05 05:44:29 PM PDT 24
Finished Jun 05 05:44:43 PM PDT 24
Peak memory 205796 kb
Host smart-24e4c7c2-d1ed-4686-9fa1-c0bb20e3aef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69820
6530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.698206530
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.4234594512
Short name T1930
Test name
Test status
Simulation time 10937294107 ps
CPU time 15.32 seconds
Started Jun 05 05:44:19 PM PDT 24
Finished Jun 05 05:44:34 PM PDT 24
Peak memory 205748 kb
Host smart-7b157914-26e1-4744-8e88-6fc173400b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42345
94512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.4234594512
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2439047274
Short name T444
Test name
Test status
Simulation time 10116502094 ps
CPU time 14.37 seconds
Started Jun 05 05:44:14 PM PDT 24
Finished Jun 05 05:44:29 PM PDT 24
Peak memory 205648 kb
Host smart-6ee87c42-ed0d-4232-85c0-b0a2869830c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24390
47274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2439047274
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.625781382
Short name T998
Test name
Test status
Simulation time 10193627040 ps
CPU time 15.08 seconds
Started Jun 05 05:44:26 PM PDT 24
Finished Jun 05 05:44:42 PM PDT 24
Peak memory 205740 kb
Host smart-5cbc531e-97bd-4f2b-8191-e5effdc53772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62578
1382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.625781382
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2889875883
Short name T538
Test name
Test status
Simulation time 10054449444 ps
CPU time 13.16 seconds
Started Jun 05 05:44:23 PM PDT 24
Finished Jun 05 05:44:37 PM PDT 24
Peak memory 205752 kb
Host smart-e4fd0c0c-473d-4716-b191-79af3ffdd478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28898
75883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2889875883
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.2253567500
Short name T1933
Test name
Test status
Simulation time 10149620697 ps
CPU time 13.39 seconds
Started Jun 05 05:44:16 PM PDT 24
Finished Jun 05 05:44:30 PM PDT 24
Peak memory 205792 kb
Host smart-ac11efaf-c6d0-4d1e-943f-3beac56162fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22535
67500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2253567500
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.2362023150
Short name T965
Test name
Test status
Simulation time 10108437042 ps
CPU time 14.96 seconds
Started Jun 05 05:44:15 PM PDT 24
Finished Jun 05 05:44:31 PM PDT 24
Peak memory 205652 kb
Host smart-c3dc3e98-62f2-4f11-b1a0-8e594952e2aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23620
23150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.2362023150
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.545863319
Short name T1629
Test name
Test status
Simulation time 13198936142 ps
CPU time 15.87 seconds
Started Jun 05 05:44:16 PM PDT 24
Finished Jun 05 05:44:32 PM PDT 24
Peak memory 205712 kb
Host smart-31692f8b-7742-49e2-a1e1-77041024cca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54586
3319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.545863319
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.594272620
Short name T844
Test name
Test status
Simulation time 10135221290 ps
CPU time 13.47 seconds
Started Jun 05 05:44:20 PM PDT 24
Finished Jun 05 05:44:33 PM PDT 24
Peak memory 205664 kb
Host smart-f7808d2c-a7e2-410a-b6d2-81f67a8fec20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59427
2620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.594272620
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.2369196848
Short name T121
Test name
Test status
Simulation time 24447633956 ps
CPU time 419.1 seconds
Started Jun 05 05:44:16 PM PDT 24
Finished Jun 05 05:51:16 PM PDT 24
Peak memory 205648 kb
Host smart-b720b44e-ea59-4d83-adc2-8d61c29316f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23691
96848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.2369196848
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.87697237
Short name T1759
Test name
Test status
Simulation time 10050077739 ps
CPU time 13.38 seconds
Started Jun 05 05:44:19 PM PDT 24
Finished Jun 05 05:44:33 PM PDT 24
Peak memory 205724 kb
Host smart-bb6f6ef6-d7f7-450a-a90b-a6325cf3e1fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87697
237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.87697237
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.487470457
Short name T1878
Test name
Test status
Simulation time 10122466762 ps
CPU time 13.63 seconds
Started Jun 05 05:44:16 PM PDT 24
Finished Jun 05 05:44:30 PM PDT 24
Peak memory 205800 kb
Host smart-1dbcbff5-8f92-484c-88e3-0d8b1f4e7573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48747
0457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.487470457
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.2752305155
Short name T694
Test name
Test status
Simulation time 10144532193 ps
CPU time 12.71 seconds
Started Jun 05 05:44:24 PM PDT 24
Finished Jun 05 05:44:37 PM PDT 24
Peak memory 205800 kb
Host smart-2e2b89d2-d8fb-4853-a96b-440ba73fe8fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27523
05155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.2752305155
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.4116453819
Short name T21
Test name
Test status
Simulation time 10057760001 ps
CPU time 13.66 seconds
Started Jun 05 05:44:21 PM PDT 24
Finished Jun 05 05:44:35 PM PDT 24
Peak memory 205764 kb
Host smart-278efe95-0804-4b67-b845-76df95890f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41164
53819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.4116453819
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.3864287641
Short name T344
Test name
Test status
Simulation time 10106246451 ps
CPU time 16.4 seconds
Started Jun 05 05:44:26 PM PDT 24
Finished Jun 05 05:44:43 PM PDT 24
Peak memory 205632 kb
Host smart-e64aad16-f981-4e4b-b16a-fd20d25a60fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38642
87641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.3864287641
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.2665704065
Short name T129
Test name
Test status
Simulation time 10070071633 ps
CPU time 13.43 seconds
Started Jun 05 05:44:22 PM PDT 24
Finished Jun 05 05:44:35 PM PDT 24
Peak memory 205648 kb
Host smart-a4777331-3650-4bd8-8732-3e3a6d8c7084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26657
04065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.2665704065
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_eop_single_bit_handling.2635574657
Short name T1453
Test name
Test status
Simulation time 10061962331 ps
CPU time 13.1 seconds
Started Jun 05 05:44:30 PM PDT 24
Finished Jun 05 05:44:44 PM PDT 24
Peak memory 205608 kb
Host smart-67c06308-8a70-4b3d-840d-5308a2c7233c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26355
74657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_eop_single_bit_handling.2635574657
Directory /workspace/2.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.469249720
Short name T181
Test name
Test status
Simulation time 10069916320 ps
CPU time 15.63 seconds
Started Jun 05 05:44:27 PM PDT 24
Finished Jun 05 05:44:43 PM PDT 24
Peak memory 205696 kb
Host smart-3e39bc50-f935-4437-84b8-25d357c419da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46924
9720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.469249720
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.782646168
Short name T2016
Test name
Test status
Simulation time 10045674689 ps
CPU time 13.04 seconds
Started Jun 05 05:44:21 PM PDT 24
Finished Jun 05 05:44:35 PM PDT 24
Peak memory 205724 kb
Host smart-5d7667fa-db03-4833-a2d1-717c9e1ebc99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78264
6168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.782646168
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.2952929485
Short name T1841
Test name
Test status
Simulation time 23380325684 ps
CPU time 40.85 seconds
Started Jun 05 05:44:22 PM PDT 24
Finished Jun 05 05:45:04 PM PDT 24
Peak memory 205708 kb
Host smart-e42ff3c8-1dbb-481a-a8fd-b7f09749ede4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29529
29485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.2952929485
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.4080216860
Short name T1927
Test name
Test status
Simulation time 10080283088 ps
CPU time 14.02 seconds
Started Jun 05 05:44:24 PM PDT 24
Finished Jun 05 05:44:39 PM PDT 24
Peak memory 205776 kb
Host smart-0b724718-b153-45a4-b8b9-b39f4a4d8a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40802
16860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.4080216860
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.1162702888
Short name T1283
Test name
Test status
Simulation time 10152295485 ps
CPU time 13.52 seconds
Started Jun 05 05:44:24 PM PDT 24
Finished Jun 05 05:44:39 PM PDT 24
Peak memory 205784 kb
Host smart-dde76e88-70fd-4513-81a0-6bc49970de90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11627
02888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1162702888
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.3725385397
Short name T175
Test name
Test status
Simulation time 21791918678 ps
CPU time 119.4 seconds
Started Jun 05 05:44:25 PM PDT 24
Finished Jun 05 05:46:25 PM PDT 24
Peak memory 205756 kb
Host smart-96f0f203-2897-430f-bfb6-530fab6bb1ec
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3725385397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.3725385397
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.3178915986
Short name T1014
Test name
Test status
Simulation time 22407827544 ps
CPU time 98.31 seconds
Started Jun 05 05:44:28 PM PDT 24
Finished Jun 05 05:46:07 PM PDT 24
Peak memory 205728 kb
Host smart-b7f96b27-0d1f-459e-b1d7-a826aa23d1ee
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3178915986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.3178915986
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.1131825167
Short name T1814
Test name
Test status
Simulation time 34945534809 ps
CPU time 222.06 seconds
Started Jun 05 05:44:22 PM PDT 24
Finished Jun 05 05:48:05 PM PDT 24
Peak memory 205796 kb
Host smart-d2ffeff2-053d-420b-afdd-4fc95a232c74
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1131825167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.1131825167
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.759286846
Short name T308
Test name
Test status
Simulation time 10114925651 ps
CPU time 13.19 seconds
Started Jun 05 05:44:22 PM PDT 24
Finished Jun 05 05:44:36 PM PDT 24
Peak memory 205640 kb
Host smart-4801b04d-6347-4d73-8604-e0530720259c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75928
6846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.759286846
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.2729691363
Short name T462
Test name
Test status
Simulation time 10049446788 ps
CPU time 13.08 seconds
Started Jun 05 05:44:23 PM PDT 24
Finished Jun 05 05:44:36 PM PDT 24
Peak memory 205744 kb
Host smart-ea1b44aa-51f3-4fa2-87d1-a2ef15322bb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27296
91363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.2729691363
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.2162653699
Short name T184
Test name
Test status
Simulation time 1761878208 ps
CPU time 2.89 seconds
Started Jun 05 05:44:24 PM PDT 24
Finished Jun 05 05:44:28 PM PDT 24
Peak memory 221776 kb
Host smart-586a27e8-3942-45c1-a5fd-88f966a7511c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2162653699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2162653699
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.3198459680
Short name T1078
Test name
Test status
Simulation time 10051608877 ps
CPU time 12.69 seconds
Started Jun 05 05:44:22 PM PDT 24
Finished Jun 05 05:44:36 PM PDT 24
Peak memory 205732 kb
Host smart-5b470d6f-91b0-40e2-b0a0-6657a272c51f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31984
59680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.3198459680
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3542960858
Short name T440
Test name
Test status
Simulation time 10047618773 ps
CPU time 13.39 seconds
Started Jun 05 05:44:23 PM PDT 24
Finished Jun 05 05:44:37 PM PDT 24
Peak memory 205640 kb
Host smart-0118f898-ee2f-414e-8501-e185fb44c5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35429
60858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3542960858
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.3680236337
Short name T490
Test name
Test status
Simulation time 10090100283 ps
CPU time 14.72 seconds
Started Jun 05 05:44:30 PM PDT 24
Finished Jun 05 05:44:45 PM PDT 24
Peak memory 205676 kb
Host smart-cbeb64a5-2ca2-4da3-9481-8986c391e9cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36802
36337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.3680236337
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.607769695
Short name T858
Test name
Test status
Simulation time 10111624039 ps
CPU time 13.06 seconds
Started Jun 05 05:44:24 PM PDT 24
Finished Jun 05 05:44:37 PM PDT 24
Peak memory 205696 kb
Host smart-5bc43a85-2225-49ca-95fe-830557d826a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60776
9695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.607769695
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.1628218971
Short name T352
Test name
Test status
Simulation time 10170899736 ps
CPU time 15.04 seconds
Started Jun 05 05:44:27 PM PDT 24
Finished Jun 05 05:44:42 PM PDT 24
Peak memory 205728 kb
Host smart-19dcced9-317f-49e5-b0b0-6196ccf4bb59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16282
18971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.1628218971
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.135542473
Short name T819
Test name
Test status
Simulation time 14342198646 ps
CPU time 47.03 seconds
Started Jun 05 05:44:26 PM PDT 24
Finished Jun 05 05:45:13 PM PDT 24
Peak memory 205928 kb
Host smart-dfa77954-6475-4fcd-b5ce-0f65e5a8ba17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13554
2473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.135542473
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.1257375785
Short name T532
Test name
Test status
Simulation time 17828343175 ps
CPU time 218.85 seconds
Started Jun 05 05:44:25 PM PDT 24
Finished Jun 05 05:48:05 PM PDT 24
Peak memory 205816 kb
Host smart-fe19f904-487a-4a17-b009-bf71e9b9356f
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257375785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_
traffic.1257375785
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.2716270453
Short name T1490
Test name
Test status
Simulation time 10140096116 ps
CPU time 14.26 seconds
Started Jun 05 05:46:43 PM PDT 24
Finished Jun 05 05:46:57 PM PDT 24
Peak memory 205792 kb
Host smart-ea1003a3-d572-4c1c-a7c5-847bbf967486
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2716270453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.2716270453
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.783368013
Short name T1300
Test name
Test status
Simulation time 10061017425 ps
CPU time 13.21 seconds
Started Jun 05 05:46:40 PM PDT 24
Finished Jun 05 05:46:54 PM PDT 24
Peak memory 205728 kb
Host smart-e19ac16b-e4bb-4a7f-b46e-cf1b6515c779
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=783368013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.783368013
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.2803750476
Short name T1139
Test name
Test status
Simulation time 10087584558 ps
CPU time 13.18 seconds
Started Jun 05 05:46:39 PM PDT 24
Finished Jun 05 05:46:53 PM PDT 24
Peak memory 205560 kb
Host smart-cfa0466b-6e31-4f18-aba5-bace22fb559e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28037
50476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.2803750476
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.762298940
Short name T696
Test name
Test status
Simulation time 13551216532 ps
CPU time 17.17 seconds
Started Jun 05 05:46:34 PM PDT 24
Finished Jun 05 05:46:52 PM PDT 24
Peak memory 205572 kb
Host smart-638783df-99ab-4c67-91f6-56d8fea5beaa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=762298940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.762298940
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.525144075
Short name T860
Test name
Test status
Simulation time 23394963990 ps
CPU time 25.26 seconds
Started Jun 05 05:46:38 PM PDT 24
Finished Jun 05 05:47:03 PM PDT 24
Peak memory 205680 kb
Host smart-08a6c2db-b981-483c-9579-9cb162f6413e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=525144075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.525144075
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.1607357452
Short name T627
Test name
Test status
Simulation time 10058587503 ps
CPU time 13.98 seconds
Started Jun 05 05:46:31 PM PDT 24
Finished Jun 05 05:46:45 PM PDT 24
Peak memory 205764 kb
Host smart-6a8b786b-69ba-422a-a79d-402c556f7fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16073
57452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1607357452
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.3882901639
Short name T1387
Test name
Test status
Simulation time 10067013291 ps
CPU time 12.71 seconds
Started Jun 05 05:46:33 PM PDT 24
Finished Jun 05 05:46:46 PM PDT 24
Peak memory 205748 kb
Host smart-aa9d43a6-a4e7-490f-af8b-a75a108c12a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38829
01639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.3882901639
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.3827037415
Short name T1767
Test name
Test status
Simulation time 10502690013 ps
CPU time 15.37 seconds
Started Jun 05 05:46:38 PM PDT 24
Finished Jun 05 05:46:54 PM PDT 24
Peak memory 205724 kb
Host smart-df13b505-29eb-49f1-bf3a-28ed460053ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38270
37415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.3827037415
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.647443404
Short name T1842
Test name
Test status
Simulation time 10059521904 ps
CPU time 12.5 seconds
Started Jun 05 05:46:43 PM PDT 24
Finished Jun 05 05:46:56 PM PDT 24
Peak memory 205696 kb
Host smart-938468b8-3823-4dda-b62c-6d3e9a7e3829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64744
3404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.647443404
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.3136434207
Short name T406
Test name
Test status
Simulation time 10066787250 ps
CPU time 14.77 seconds
Started Jun 05 05:46:35 PM PDT 24
Finished Jun 05 05:46:50 PM PDT 24
Peak memory 205636 kb
Host smart-21bb0942-ffb1-4206-bf9b-e91ac6f954b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31364
34207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.3136434207
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.1981579790
Short name T1515
Test name
Test status
Simulation time 10876175541 ps
CPU time 14.65 seconds
Started Jun 05 05:46:33 PM PDT 24
Finished Jun 05 05:46:48 PM PDT 24
Peak memory 205764 kb
Host smart-5406ce92-e6e1-4716-b080-68be5d816dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19815
79790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.1981579790
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.3211447487
Short name T1224
Test name
Test status
Simulation time 10300159516 ps
CPU time 14.89 seconds
Started Jun 05 05:46:34 PM PDT 24
Finished Jun 05 05:46:50 PM PDT 24
Peak memory 205708 kb
Host smart-0fc6e906-3b39-4d00-8193-43cce0a65a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32114
47487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3211447487
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.643445067
Short name T1660
Test name
Test status
Simulation time 10126061453 ps
CPU time 12.76 seconds
Started Jun 05 05:46:46 PM PDT 24
Finished Jun 05 05:46:59 PM PDT 24
Peak memory 205764 kb
Host smart-0708e25d-a1e3-4ac5-9734-9f7d15704adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64344
5067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.643445067
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.2760282303
Short name T1543
Test name
Test status
Simulation time 10056492699 ps
CPU time 12.71 seconds
Started Jun 05 05:46:47 PM PDT 24
Finished Jun 05 05:47:01 PM PDT 24
Peak memory 205736 kb
Host smart-036a9705-c72e-4484-82fc-025896247f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27602
82303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.2760282303
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.2731400003
Short name T1306
Test name
Test status
Simulation time 10112140389 ps
CPU time 14.44 seconds
Started Jun 05 05:46:39 PM PDT 24
Finished Jun 05 05:46:54 PM PDT 24
Peak memory 205804 kb
Host smart-39dd732b-40e4-42ac-a079-38d15a231056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27314
00003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.2731400003
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.3894970509
Short name T432
Test name
Test status
Simulation time 10129430409 ps
CPU time 14.3 seconds
Started Jun 05 05:46:35 PM PDT 24
Finished Jun 05 05:46:50 PM PDT 24
Peak memory 205636 kb
Host smart-0a9157d8-588c-4dbe-b3b9-6a7d03304283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38949
70509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3894970509
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.2798059414
Short name T1710
Test name
Test status
Simulation time 13173164674 ps
CPU time 16.7 seconds
Started Jun 05 05:46:34 PM PDT 24
Finished Jun 05 05:46:52 PM PDT 24
Peak memory 205584 kb
Host smart-a3bd1c7b-b17d-4a84-b7f5-a8fb3183ab39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27980
59414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.2798059414
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1101104229
Short name T660
Test name
Test status
Simulation time 10101810531 ps
CPU time 13.88 seconds
Started Jun 05 05:46:44 PM PDT 24
Finished Jun 05 05:46:59 PM PDT 24
Peak memory 205760 kb
Host smart-e989fe64-216d-4b3d-8982-52a58e194a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11011
04229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1101104229
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.2201472968
Short name T1697
Test name
Test status
Simulation time 14754450797 ps
CPU time 59.11 seconds
Started Jun 05 05:46:42 PM PDT 24
Finished Jun 05 05:47:42 PM PDT 24
Peak memory 205712 kb
Host smart-0ef52c01-a9c3-4899-ab5d-d2837f30c0b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22014
72968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.2201472968
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.4028077153
Short name T871
Test name
Test status
Simulation time 10064145444 ps
CPU time 13.09 seconds
Started Jun 05 05:46:35 PM PDT 24
Finished Jun 05 05:46:49 PM PDT 24
Peak memory 205664 kb
Host smart-0e09e74b-9d5e-4eb6-bb87-bf267cb4b1bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40280
77153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.4028077153
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.2741307801
Short name T1689
Test name
Test status
Simulation time 10094027733 ps
CPU time 13.58 seconds
Started Jun 05 05:46:42 PM PDT 24
Finished Jun 05 05:46:56 PM PDT 24
Peak memory 205788 kb
Host smart-9281e9c6-9cfe-4e2f-92e6-a29ca42b2def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27413
07801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.2741307801
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.1255212071
Short name T518
Test name
Test status
Simulation time 10102786523 ps
CPU time 14.31 seconds
Started Jun 05 05:46:38 PM PDT 24
Finished Jun 05 05:46:52 PM PDT 24
Peak memory 205720 kb
Host smart-806d2819-98d6-43ca-b826-ee0f902edc15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12552
12071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1255212071
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.722813437
Short name T1592
Test name
Test status
Simulation time 10097339857 ps
CPU time 14.18 seconds
Started Jun 05 05:46:39 PM PDT 24
Finished Jun 05 05:46:53 PM PDT 24
Peak memory 205760 kb
Host smart-cebe4803-386f-4f33-9c0e-3ca8401b5e4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72281
3437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.722813437
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.2434172532
Short name T1418
Test name
Test status
Simulation time 10058664518 ps
CPU time 15.84 seconds
Started Jun 05 05:46:41 PM PDT 24
Finished Jun 05 05:46:57 PM PDT 24
Peak memory 205700 kb
Host smart-055ecd8f-63d7-4cc6-bac1-65b6e37a2993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24341
72532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.2434172532
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_eop_single_bit_handling.1838313107
Short name T476
Test name
Test status
Simulation time 10060603733 ps
CPU time 12.76 seconds
Started Jun 05 05:46:39 PM PDT 24
Finished Jun 05 05:46:53 PM PDT 24
Peak memory 205724 kb
Host smart-6641e252-dda3-4266-8e4b-28f23ee9a98d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18383
13107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_eop_single_bit_handling.1838313107
Directory /workspace/20.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.3731780816
Short name T1473
Test name
Test status
Simulation time 10076080253 ps
CPU time 14.42 seconds
Started Jun 05 05:46:38 PM PDT 24
Finished Jun 05 05:46:53 PM PDT 24
Peak memory 205736 kb
Host smart-646a8878-111e-4eee-bea5-97fd723b5f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37317
80816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.3731780816
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.1475734775
Short name T711
Test name
Test status
Simulation time 10077701935 ps
CPU time 14.07 seconds
Started Jun 05 05:46:37 PM PDT 24
Finished Jun 05 05:46:52 PM PDT 24
Peak memory 206008 kb
Host smart-dcef4efe-17a7-42ac-8333-9fc03d83904f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14757
34775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.1475734775
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.953672451
Short name T1377
Test name
Test status
Simulation time 18388524930 ps
CPU time 31.66 seconds
Started Jun 05 05:46:43 PM PDT 24
Finished Jun 05 05:47:15 PM PDT 24
Peak memory 205700 kb
Host smart-4504a051-bfbe-4f22-873e-4a73253fe470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95367
2451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.953672451
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.1146337781
Short name T1026
Test name
Test status
Simulation time 10057883094 ps
CPU time 15.51 seconds
Started Jun 05 05:46:39 PM PDT 24
Finished Jun 05 05:46:55 PM PDT 24
Peak memory 205676 kb
Host smart-0afd7c0d-9777-4509-8b1b-65177f1116ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11463
37781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.1146337781
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.3584773024
Short name T872
Test name
Test status
Simulation time 10122042173 ps
CPU time 13.62 seconds
Started Jun 05 05:46:46 PM PDT 24
Finished Jun 05 05:47:00 PM PDT 24
Peak memory 205764 kb
Host smart-f9962f5e-fa3c-4458-af1b-1c45317235a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35847
73024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.3584773024
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.3770640724
Short name T355
Test name
Test status
Simulation time 10060178272 ps
CPU time 13.78 seconds
Started Jun 05 05:46:41 PM PDT 24
Finished Jun 05 05:46:55 PM PDT 24
Peak memory 205724 kb
Host smart-c82da0f9-ba1e-4777-9ae1-06c0f493a474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37706
40724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.3770640724
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.916502844
Short name T878
Test name
Test status
Simulation time 10061980654 ps
CPU time 13.93 seconds
Started Jun 05 05:46:38 PM PDT 24
Finished Jun 05 05:46:53 PM PDT 24
Peak memory 205652 kb
Host smart-df07e7b5-aad9-476c-bcac-6b94efa8b2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91650
2844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.916502844
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1454770279
Short name T1431
Test name
Test status
Simulation time 10104677017 ps
CPU time 13.56 seconds
Started Jun 05 05:46:39 PM PDT 24
Finished Jun 05 05:46:53 PM PDT 24
Peak memory 205748 kb
Host smart-672c2611-4a30-4a75-894d-2035bee94c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14547
70279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1454770279
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2739315362
Short name T1775
Test name
Test status
Simulation time 10106663375 ps
CPU time 15.22 seconds
Started Jun 05 05:46:47 PM PDT 24
Finished Jun 05 05:47:03 PM PDT 24
Peak memory 205764 kb
Host smart-76f92769-5602-4356-b1d8-3b8681e60463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27393
15362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2739315362
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1651580374
Short name T86
Test name
Test status
Simulation time 10112824712 ps
CPU time 13.83 seconds
Started Jun 05 05:46:34 PM PDT 24
Finished Jun 05 05:46:48 PM PDT 24
Peak memory 205668 kb
Host smart-f67aad61-79e4-49cc-98dc-6957c1ed7e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16515
80374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1651580374
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.4069960430
Short name T557
Test name
Test status
Simulation time 10059645708 ps
CPU time 14.61 seconds
Started Jun 05 05:46:39 PM PDT 24
Finished Jun 05 05:46:54 PM PDT 24
Peak memory 205764 kb
Host smart-0ac795c5-db5c-4a32-993e-7b96f57a764f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40699
60430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.4069960430
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.2706778383
Short name T79
Test name
Test status
Simulation time 10065156711 ps
CPU time 14.3 seconds
Started Jun 05 05:46:39 PM PDT 24
Finished Jun 05 05:46:54 PM PDT 24
Peak memory 205652 kb
Host smart-ec91c5d8-fb33-4ffb-8cd3-1a628b7b20b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27067
78383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.2706778383
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.1941272529
Short name T483
Test name
Test status
Simulation time 19483444031 ps
CPU time 77.67 seconds
Started Jun 05 05:46:41 PM PDT 24
Finished Jun 05 05:47:59 PM PDT 24
Peak memory 205744 kb
Host smart-7edcd577-588b-4c43-a105-2c90e264e8c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19412
72529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.1941272529
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.3008598848
Short name T27
Test name
Test status
Simulation time 10141139635 ps
CPU time 12.52 seconds
Started Jun 05 05:46:45 PM PDT 24
Finished Jun 05 05:46:58 PM PDT 24
Peak memory 205808 kb
Host smart-a03a49d8-7ba8-4811-85f8-0eb386baefb3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3008598848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.3008598848
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.3933380435
Short name T1354
Test name
Test status
Simulation time 10075061782 ps
CPU time 15.46 seconds
Started Jun 05 05:46:47 PM PDT 24
Finished Jun 05 05:47:03 PM PDT 24
Peak memory 205944 kb
Host smart-0071bd68-8f32-4ea4-9962-2412980bade1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3933380435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.3933380435
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.3620364572
Short name T1385
Test name
Test status
Simulation time 10092352936 ps
CPU time 13.35 seconds
Started Jun 05 05:46:45 PM PDT 24
Finished Jun 05 05:46:59 PM PDT 24
Peak memory 205724 kb
Host smart-5b1cca76-60f9-4932-a8e4-e8a0c6500dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36203
64572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.3620364572
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.3949044929
Short name T1395
Test name
Test status
Simulation time 14324965752 ps
CPU time 20.33 seconds
Started Jun 05 05:46:39 PM PDT 24
Finished Jun 05 05:47:00 PM PDT 24
Peak memory 205804 kb
Host smart-2fdce70c-da23-415e-95ca-011240063c56
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3949044929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.3949044929
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.4107034273
Short name T14
Test name
Test status
Simulation time 23324553031 ps
CPU time 30.46 seconds
Started Jun 05 05:46:47 PM PDT 24
Finished Jun 05 05:47:19 PM PDT 24
Peak memory 205740 kb
Host smart-bcfc1df7-cd23-4dcb-9c91-1f0c3496050e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4107034273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.4107034273
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2907810855
Short name T632
Test name
Test status
Simulation time 10076056655 ps
CPU time 13.44 seconds
Started Jun 05 05:46:47 PM PDT 24
Finished Jun 05 05:47:01 PM PDT 24
Peak memory 205772 kb
Host smart-e1cb06c0-9bf8-4c11-87d5-718ca59aeea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29078
10855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2907810855
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.2852881258
Short name T1294
Test name
Test status
Simulation time 10917810743 ps
CPU time 14.28 seconds
Started Jun 05 05:46:49 PM PDT 24
Finished Jun 05 05:47:04 PM PDT 24
Peak memory 205680 kb
Host smart-f6da7f3e-0b7c-48f2-a0d5-4c2b24bd0bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28528
81258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2852881258
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.3106804345
Short name T433
Test name
Test status
Simulation time 10068250659 ps
CPU time 13.71 seconds
Started Jun 05 05:46:45 PM PDT 24
Finished Jun 05 05:46:59 PM PDT 24
Peak memory 205728 kb
Host smart-8b41fd22-21aa-4a79-b042-56bce9f172f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31068
04345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.3106804345
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.600230167
Short name T785
Test name
Test status
Simulation time 10081256987 ps
CPU time 12.75 seconds
Started Jun 05 05:46:48 PM PDT 24
Finished Jun 05 05:47:01 PM PDT 24
Peak memory 205712 kb
Host smart-6480dd17-fb4a-4560-8f98-1b2dce8e5ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60023
0167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.600230167
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.2946732583
Short name T1996
Test name
Test status
Simulation time 10725882530 ps
CPU time 15.96 seconds
Started Jun 05 05:46:46 PM PDT 24
Finished Jun 05 05:47:03 PM PDT 24
Peak memory 205704 kb
Host smart-4ff06daa-3e29-4dff-8937-ad5ef6529219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29467
32583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.2946732583
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1466257916
Short name T1851
Test name
Test status
Simulation time 10264206378 ps
CPU time 14.12 seconds
Started Jun 05 05:46:57 PM PDT 24
Finished Jun 05 05:47:12 PM PDT 24
Peak memory 205756 kb
Host smart-db8262be-6d8a-4d9e-a206-c7c91649e14c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14662
57916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1466257916
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.1735019263
Short name T1465
Test name
Test status
Simulation time 10059184989 ps
CPU time 12.57 seconds
Started Jun 05 05:46:49 PM PDT 24
Finished Jun 05 05:47:02 PM PDT 24
Peak memory 205708 kb
Host smart-65556dd7-383b-4052-a673-ffbb327125aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17350
19263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.1735019263
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.4215312191
Short name T1733
Test name
Test status
Simulation time 10079769152 ps
CPU time 13.83 seconds
Started Jun 05 05:46:48 PM PDT 24
Finished Jun 05 05:47:02 PM PDT 24
Peak memory 205764 kb
Host smart-e1f18895-4f1f-47fb-a37a-6ce9a44d672e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42153
12191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.4215312191
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.4141387467
Short name T1966
Test name
Test status
Simulation time 10153475469 ps
CPU time 14.25 seconds
Started Jun 05 05:46:47 PM PDT 24
Finished Jun 05 05:47:02 PM PDT 24
Peak memory 205652 kb
Host smart-819823c6-8881-469c-aaa3-aab9301868a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41413
87467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.4141387467
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.1924948356
Short name T1458
Test name
Test status
Simulation time 13262437713 ps
CPU time 17.31 seconds
Started Jun 05 05:46:49 PM PDT 24
Finished Jun 05 05:47:07 PM PDT 24
Peak memory 205696 kb
Host smart-d4072973-c3a0-4c82-9666-0f1db48846f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19249
48356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.1924948356
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.167460176
Short name T1365
Test name
Test status
Simulation time 10106435285 ps
CPU time 12.3 seconds
Started Jun 05 05:46:48 PM PDT 24
Finished Jun 05 05:47:01 PM PDT 24
Peak memory 205700 kb
Host smart-967203d8-6438-464a-b509-492d034fe030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16746
0176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.167460176
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.688428059
Short name T516
Test name
Test status
Simulation time 16246049938 ps
CPU time 184.57 seconds
Started Jun 05 05:46:47 PM PDT 24
Finished Jun 05 05:49:52 PM PDT 24
Peak memory 205680 kb
Host smart-81f605ae-3bcd-4303-8aba-a9dc14417532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68842
8059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.688428059
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.2381864222
Short name T378
Test name
Test status
Simulation time 10096154248 ps
CPU time 14.3 seconds
Started Jun 05 05:46:46 PM PDT 24
Finished Jun 05 05:47:01 PM PDT 24
Peak memory 205668 kb
Host smart-d8f43cfe-1006-40f7-afd2-78a32cbf6142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23818
64222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.2381864222
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.2846633485
Short name T429
Test name
Test status
Simulation time 10093552151 ps
CPU time 17.06 seconds
Started Jun 05 05:46:47 PM PDT 24
Finished Jun 05 05:47:05 PM PDT 24
Peak memory 205772 kb
Host smart-7b78fd09-87cf-4782-8aec-133ae32bc5ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28466
33485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.2846633485
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.3483385468
Short name T962
Test name
Test status
Simulation time 10063039013 ps
CPU time 14.38 seconds
Started Jun 05 05:46:47 PM PDT 24
Finished Jun 05 05:47:02 PM PDT 24
Peak memory 205764 kb
Host smart-7fcfafb3-a79d-454e-872d-a83742f60be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34833
85468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.3483385468
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.752430991
Short name T698
Test name
Test status
Simulation time 10074665821 ps
CPU time 13.17 seconds
Started Jun 05 05:46:49 PM PDT 24
Finished Jun 05 05:47:03 PM PDT 24
Peak memory 205788 kb
Host smart-efd039d1-1c38-487f-9b56-00a5cec63e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75243
0991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.752430991
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.2257151932
Short name T605
Test name
Test status
Simulation time 10117526214 ps
CPU time 13.34 seconds
Started Jun 05 05:46:45 PM PDT 24
Finished Jun 05 05:46:59 PM PDT 24
Peak memory 206008 kb
Host smart-5723270b-6862-433f-889d-af4f6cb06357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22571
51932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.2257151932
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_eop_single_bit_handling.3488228548
Short name T1288
Test name
Test status
Simulation time 10091553866 ps
CPU time 14.55 seconds
Started Jun 05 05:46:48 PM PDT 24
Finished Jun 05 05:47:03 PM PDT 24
Peak memory 205704 kb
Host smart-99a85aa5-4e97-482e-aad6-3225209347a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34882
28548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_eop_single_bit_handling.3488228548
Directory /workspace/21.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.821944503
Short name T1091
Test name
Test status
Simulation time 10069756079 ps
CPU time 17.34 seconds
Started Jun 05 05:46:52 PM PDT 24
Finished Jun 05 05:47:10 PM PDT 24
Peak memory 205728 kb
Host smart-f3c7e0a9-81ab-451c-991d-de042359f92c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82194
4503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.821944503
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2488373449
Short name T1006
Test name
Test status
Simulation time 10122630163 ps
CPU time 13.6 seconds
Started Jun 05 05:46:47 PM PDT 24
Finished Jun 05 05:47:01 PM PDT 24
Peak memory 205688 kb
Host smart-4f9ac9c5-92ee-4004-ab69-c40b7bd65dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24883
73449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2488373449
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.732635039
Short name T83
Test name
Test status
Simulation time 17619878324 ps
CPU time 30.33 seconds
Started Jun 05 05:46:48 PM PDT 24
Finished Jun 05 05:47:19 PM PDT 24
Peak memory 205688 kb
Host smart-6f464062-1ba1-4883-a0ca-4f9c4f14c557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73263
5039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.732635039
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.4037674371
Short name T198
Test name
Test status
Simulation time 10074385200 ps
CPU time 15.86 seconds
Started Jun 05 05:46:47 PM PDT 24
Finished Jun 05 05:47:03 PM PDT 24
Peak memory 205708 kb
Host smart-a3a396be-d86c-46fd-8b8a-5a058981b4dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40376
74371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.4037674371
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.2637454297
Short name T1585
Test name
Test status
Simulation time 10148626524 ps
CPU time 13.16 seconds
Started Jun 05 05:46:50 PM PDT 24
Finished Jun 05 05:47:04 PM PDT 24
Peak memory 205652 kb
Host smart-9bd75ad2-2fb3-48af-9cf5-b4b627b9395c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26374
54297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2637454297
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.1684634901
Short name T1081
Test name
Test status
Simulation time 10064807550 ps
CPU time 13.1 seconds
Started Jun 05 05:46:47 PM PDT 24
Finished Jun 05 05:47:01 PM PDT 24
Peak memory 205540 kb
Host smart-0a0e32c8-0e1b-4827-ad86-2749f48463bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16846
34901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.1684634901
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.277385008
Short name T342
Test name
Test status
Simulation time 10051626520 ps
CPU time 12.74 seconds
Started Jun 05 05:46:45 PM PDT 24
Finished Jun 05 05:46:58 PM PDT 24
Peak memory 205736 kb
Host smart-0e5189e0-a6d0-4758-9ae4-bce8759fcecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27738
5008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.277385008
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.984388322
Short name T1268
Test name
Test status
Simulation time 10061515412 ps
CPU time 13.64 seconds
Started Jun 05 05:46:47 PM PDT 24
Finished Jun 05 05:47:02 PM PDT 24
Peak memory 205604 kb
Host smart-6b6dddd3-af4d-4c76-94c3-72b87ffa537f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98438
8322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.984388322
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1146388067
Short name T1272
Test name
Test status
Simulation time 10106854110 ps
CPU time 14.39 seconds
Started Jun 05 05:46:48 PM PDT 24
Finished Jun 05 05:47:03 PM PDT 24
Peak memory 205676 kb
Host smart-3e646bdc-b87a-42a5-a453-2d2ea1cdafb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11463
88067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1146388067
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.3800912108
Short name T2031
Test name
Test status
Simulation time 10106770845 ps
CPU time 13.73 seconds
Started Jun 05 05:46:39 PM PDT 24
Finished Jun 05 05:46:54 PM PDT 24
Peak memory 205776 kb
Host smart-61785c02-997d-4bd6-9dc2-cc15a3748d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38009
12108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3800912108
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.775288458
Short name T119
Test name
Test status
Simulation time 10123611099 ps
CPU time 12.81 seconds
Started Jun 05 05:46:49 PM PDT 24
Finished Jun 05 05:47:02 PM PDT 24
Peak memory 205636 kb
Host smart-50643e80-3130-477d-83d9-1fdfa3872c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77528
8458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.775288458
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.2135057567
Short name T521
Test name
Test status
Simulation time 10070628160 ps
CPU time 12.58 seconds
Started Jun 05 05:46:47 PM PDT 24
Finished Jun 05 05:47:00 PM PDT 24
Peak memory 205760 kb
Host smart-c01eb396-9d52-476e-a8bc-c96342892ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21350
57567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.2135057567
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.3264604658
Short name T812
Test name
Test status
Simulation time 21307009194 ps
CPU time 123.93 seconds
Started Jun 05 05:46:48 PM PDT 24
Finished Jun 05 05:48:53 PM PDT 24
Peak memory 205704 kb
Host smart-e2ce0aa0-e422-42af-931a-0da3796158f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32646
04658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.3264604658
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.2490499469
Short name T905
Test name
Test status
Simulation time 10176461573 ps
CPU time 15.23 seconds
Started Jun 05 05:47:03 PM PDT 24
Finished Jun 05 05:47:19 PM PDT 24
Peak memory 205808 kb
Host smart-bc397f53-c92f-437f-a66c-54f6f17ea9a7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2490499469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.2490499469
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.1237999184
Short name T733
Test name
Test status
Simulation time 10079320817 ps
CPU time 14.27 seconds
Started Jun 05 05:46:53 PM PDT 24
Finished Jun 05 05:47:09 PM PDT 24
Peak memory 205700 kb
Host smart-b5922092-b4d4-4e76-af14-2be4f7bd32b0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1237999184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.1237999184
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.1059675981
Short name T1783
Test name
Test status
Simulation time 10080961056 ps
CPU time 14.76 seconds
Started Jun 05 05:46:54 PM PDT 24
Finished Jun 05 05:47:09 PM PDT 24
Peak memory 205660 kb
Host smart-873756dc-aa4a-48c6-a92c-0139cc59c4e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10596
75981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.1059675981
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.187227935
Short name T1096
Test name
Test status
Simulation time 13548121877 ps
CPU time 16.66 seconds
Started Jun 05 05:46:47 PM PDT 24
Finished Jun 05 05:47:04 PM PDT 24
Peak memory 205652 kb
Host smart-bc08c967-713e-44a2-998a-12368dfe917a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=187227935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.187227935
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.2250156105
Short name T1088
Test name
Test status
Simulation time 23212285302 ps
CPU time 27.35 seconds
Started Jun 05 05:46:47 PM PDT 24
Finished Jun 05 05:47:15 PM PDT 24
Peak memory 205716 kb
Host smart-6978791a-7bdb-4885-b4d0-dd8b2aaf9721
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2250156105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.2250156105
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.371135204
Short name T908
Test name
Test status
Simulation time 10069979189 ps
CPU time 12.8 seconds
Started Jun 05 05:46:47 PM PDT 24
Finished Jun 05 05:47:01 PM PDT 24
Peak memory 205652 kb
Host smart-2da0ae69-80eb-4893-8ab0-48d1871281ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37113
5204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.371135204
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.365639055
Short name T747
Test name
Test status
Simulation time 10236308893 ps
CPU time 15.66 seconds
Started Jun 05 05:46:49 PM PDT 24
Finished Jun 05 05:47:05 PM PDT 24
Peak memory 205672 kb
Host smart-8e29d583-4db1-47a1-8013-6707dd0959e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36563
9055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.365639055
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.73392217
Short name T383
Test name
Test status
Simulation time 10051592046 ps
CPU time 14.09 seconds
Started Jun 05 05:46:55 PM PDT 24
Finished Jun 05 05:47:10 PM PDT 24
Peak memory 205696 kb
Host smart-746f5912-3a42-4772-b826-38218851e168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73392
217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.73392217
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.2642489549
Short name T409
Test name
Test status
Simulation time 10065232344 ps
CPU time 15.01 seconds
Started Jun 05 05:46:50 PM PDT 24
Finished Jun 05 05:47:06 PM PDT 24
Peak memory 205648 kb
Host smart-98cf3c30-5533-47f6-9752-6383eb25b0b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26424
89549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2642489549
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.3812855012
Short name T1800
Test name
Test status
Simulation time 10979318645 ps
CPU time 15.88 seconds
Started Jun 05 05:46:49 PM PDT 24
Finished Jun 05 05:47:05 PM PDT 24
Peak memory 205768 kb
Host smart-9324db46-16f4-4be0-ba3f-926f6eaa56a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38128
55012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.3812855012
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.3186137538
Short name T978
Test name
Test status
Simulation time 10127153439 ps
CPU time 15.49 seconds
Started Jun 05 05:46:57 PM PDT 24
Finished Jun 05 05:47:13 PM PDT 24
Peak memory 205756 kb
Host smart-896da978-9774-4c45-b6c3-b48da6b29fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31861
37538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3186137538
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.3426478682
Short name T434
Test name
Test status
Simulation time 10093010909 ps
CPU time 14.83 seconds
Started Jun 05 05:46:54 PM PDT 24
Finished Jun 05 05:47:10 PM PDT 24
Peak memory 205644 kb
Host smart-3069d700-bbe6-422f-b384-5e6214da072b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34264
78682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.3426478682
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.228664228
Short name T1544
Test name
Test status
Simulation time 10093818392 ps
CPU time 14.56 seconds
Started Jun 05 05:46:55 PM PDT 24
Finished Jun 05 05:47:10 PM PDT 24
Peak memory 205664 kb
Host smart-242927e7-d406-46b6-b909-774c778501d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22866
4228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.228664228
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.633984756
Short name T628
Test name
Test status
Simulation time 10090056428 ps
CPU time 14.12 seconds
Started Jun 05 05:46:50 PM PDT 24
Finished Jun 05 05:47:04 PM PDT 24
Peak memory 205700 kb
Host smart-f9a82b88-31f6-4a1f-a0c9-24bacb7b2ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63398
4756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.633984756
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.831463637
Short name T1297
Test name
Test status
Simulation time 10135557758 ps
CPU time 14.54 seconds
Started Jun 05 05:46:50 PM PDT 24
Finished Jun 05 05:47:05 PM PDT 24
Peak memory 205764 kb
Host smart-ce9b4144-5b43-4eef-a1ce-eeb5541d6362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83146
3637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.831463637
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.3995182608
Short name T1794
Test name
Test status
Simulation time 13166859764 ps
CPU time 15.44 seconds
Started Jun 05 05:46:48 PM PDT 24
Finished Jun 05 05:47:05 PM PDT 24
Peak memory 205648 kb
Host smart-b1fab25a-5431-4d12-98f6-40dfdf108d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39951
82608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.3995182608
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.602368134
Short name T912
Test name
Test status
Simulation time 10084361895 ps
CPU time 16.17 seconds
Started Jun 05 05:46:48 PM PDT 24
Finished Jun 05 05:47:05 PM PDT 24
Peak memory 205684 kb
Host smart-45fbfbcc-8f82-41ce-bb99-8aafa5d45931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60236
8134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.602368134
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.2525998799
Short name T668
Test name
Test status
Simulation time 18511916616 ps
CPU time 77.57 seconds
Started Jun 05 05:46:52 PM PDT 24
Finished Jun 05 05:48:10 PM PDT 24
Peak memory 205704 kb
Host smart-2857930e-aae9-4e18-820a-569882494756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25259
98799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.2525998799
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.29194771
Short name T1486
Test name
Test status
Simulation time 10060391501 ps
CPU time 13.56 seconds
Started Jun 05 05:46:54 PM PDT 24
Finished Jun 05 05:47:08 PM PDT 24
Peak memory 205720 kb
Host smart-96b2a43e-6ecf-4628-bc6c-4eff57b83b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29194
771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.29194771
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.3607690427
Short name T95
Test name
Test status
Simulation time 10080847064 ps
CPU time 13.78 seconds
Started Jun 05 05:46:55 PM PDT 24
Finished Jun 05 05:47:09 PM PDT 24
Peak memory 205764 kb
Host smart-15c6cf1b-7efc-485e-bbb3-0b3df73605e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36076
90427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3607690427
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.624703898
Short name T1060
Test name
Test status
Simulation time 10136999564 ps
CPU time 13.39 seconds
Started Jun 05 05:46:54 PM PDT 24
Finished Jun 05 05:47:08 PM PDT 24
Peak memory 205676 kb
Host smart-b6dab37e-9846-40c4-931e-fabc62000c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62470
3898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.624703898
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.4284458123
Short name T575
Test name
Test status
Simulation time 10150357287 ps
CPU time 13.28 seconds
Started Jun 05 05:46:55 PM PDT 24
Finished Jun 05 05:47:09 PM PDT 24
Peak memory 205684 kb
Host smart-e847d34d-f996-4b31-a70d-1ab9cd608ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42844
58123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.4284458123
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.499976526
Short name T1127
Test name
Test status
Simulation time 10067980757 ps
CPU time 16.78 seconds
Started Jun 05 05:46:53 PM PDT 24
Finished Jun 05 05:47:11 PM PDT 24
Peak memory 205756 kb
Host smart-23d38acc-c8b4-4757-8b11-79b0cd1801fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49997
6526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.499976526
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.2893739868
Short name T1466
Test name
Test status
Simulation time 10097036485 ps
CPU time 13.14 seconds
Started Jun 05 05:46:54 PM PDT 24
Finished Jun 05 05:47:08 PM PDT 24
Peak memory 205728 kb
Host smart-f0201ab9-bc15-4be7-af02-07f08fd91ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28937
39868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.2893739868
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_eop_single_bit_handling.2320772522
Short name T295
Test name
Test status
Simulation time 10074242076 ps
CPU time 14.43 seconds
Started Jun 05 05:46:59 PM PDT 24
Finished Jun 05 05:47:14 PM PDT 24
Peak memory 205660 kb
Host smart-eee87368-fa8d-4de3-9ec9-670f16ffb459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23207
72522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_eop_single_bit_handling.2320772522
Directory /workspace/22.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.3800146160
Short name T1818
Test name
Test status
Simulation time 10113340536 ps
CPU time 12.91 seconds
Started Jun 05 05:46:52 PM PDT 24
Finished Jun 05 05:47:06 PM PDT 24
Peak memory 205676 kb
Host smart-ace6763f-436f-48f8-aabd-0da68e11d5dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38001
46160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.3800146160
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.2605475046
Short name T1770
Test name
Test status
Simulation time 10039812460 ps
CPU time 14.86 seconds
Started Jun 05 05:46:55 PM PDT 24
Finished Jun 05 05:47:11 PM PDT 24
Peak memory 205640 kb
Host smart-f7718bcf-792e-4907-88ae-63efe010372a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26054
75046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.2605475046
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.1291944573
Short name T164
Test name
Test status
Simulation time 23986669198 ps
CPU time 42.96 seconds
Started Jun 05 05:46:53 PM PDT 24
Finished Jun 05 05:47:37 PM PDT 24
Peak memory 205704 kb
Host smart-6e9fc3dc-0c7b-48d4-bf77-d5ec30ba043a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12919
44573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.1291944573
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.1446677279
Short name T1383
Test name
Test status
Simulation time 10058346862 ps
CPU time 16.02 seconds
Started Jun 05 05:46:57 PM PDT 24
Finished Jun 05 05:47:13 PM PDT 24
Peak memory 205700 kb
Host smart-b47d684a-5bd0-491c-82e3-8f3ca5eabfe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14466
77279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.1446677279
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.4211769293
Short name T560
Test name
Test status
Simulation time 10117104701 ps
CPU time 13.68 seconds
Started Jun 05 05:46:59 PM PDT 24
Finished Jun 05 05:47:13 PM PDT 24
Peak memory 205768 kb
Host smart-1ede2152-f139-42ff-b976-d0c4ab5a146c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42117
69293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.4211769293
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.32097814
Short name T1429
Test name
Test status
Simulation time 10064880744 ps
CPU time 13.31 seconds
Started Jun 05 05:46:54 PM PDT 24
Finished Jun 05 05:47:08 PM PDT 24
Peak memory 205664 kb
Host smart-6b52a2ed-520b-4261-bbd5-9a763af6d4f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32097
814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.32097814
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.3053196072
Short name T639
Test name
Test status
Simulation time 10062625319 ps
CPU time 14.12 seconds
Started Jun 05 05:46:56 PM PDT 24
Finished Jun 05 05:47:11 PM PDT 24
Peak memory 205752 kb
Host smart-7435246c-212d-4b73-8838-3c750c278faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30531
96072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.3053196072
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.146967766
Short name T1337
Test name
Test status
Simulation time 10079498977 ps
CPU time 16.19 seconds
Started Jun 05 05:46:53 PM PDT 24
Finished Jun 05 05:47:10 PM PDT 24
Peak memory 205732 kb
Host smart-cdd5b4a8-f37b-46d7-aa0a-d2ecb7155f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14696
7766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.146967766
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.730398692
Short name T921
Test name
Test status
Simulation time 10049755369 ps
CPU time 13.28 seconds
Started Jun 05 05:46:53 PM PDT 24
Finished Jun 05 05:47:07 PM PDT 24
Peak memory 205676 kb
Host smart-48ce4210-b084-4550-8a8f-662e01731a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73039
8692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.730398692
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.1977525605
Short name T1721
Test name
Test status
Simulation time 10107618237 ps
CPU time 12.93 seconds
Started Jun 05 05:46:48 PM PDT 24
Finished Jun 05 05:47:02 PM PDT 24
Peak memory 205760 kb
Host smart-81205522-d6eb-4335-b135-146cb5f8f5c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19775
25605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1977525605
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.3912031400
Short name T1040
Test name
Test status
Simulation time 10121007762 ps
CPU time 12.81 seconds
Started Jun 05 05:46:53 PM PDT 24
Finished Jun 05 05:47:07 PM PDT 24
Peak memory 205764 kb
Host smart-6780eada-2596-47bf-9c14-d0b296699104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39120
31400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.3912031400
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.3700635582
Short name T1687
Test name
Test status
Simulation time 10087313478 ps
CPU time 13.62 seconds
Started Jun 05 05:46:54 PM PDT 24
Finished Jun 05 05:47:08 PM PDT 24
Peak memory 205792 kb
Host smart-5699bbbb-e4f8-4cc1-99e4-bbffb98e1f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37006
35582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.3700635582
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.827615104
Short name T1940
Test name
Test status
Simulation time 21529516097 ps
CPU time 352.92 seconds
Started Jun 05 05:46:52 PM PDT 24
Finished Jun 05 05:52:46 PM PDT 24
Peak memory 205680 kb
Host smart-6fbd0fb3-5b03-4b41-b699-1053f9cbe697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82761
5104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.827615104
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.2382542959
Short name T1374
Test name
Test status
Simulation time 10167714208 ps
CPU time 13.22 seconds
Started Jun 05 05:47:02 PM PDT 24
Finished Jun 05 05:47:16 PM PDT 24
Peak memory 205748 kb
Host smart-b3cd2463-c626-4604-aca5-8f5020b16db5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2382542959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.2382542959
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.3815939943
Short name T1358
Test name
Test status
Simulation time 10081755154 ps
CPU time 13.01 seconds
Started Jun 05 05:47:04 PM PDT 24
Finished Jun 05 05:47:18 PM PDT 24
Peak memory 205636 kb
Host smart-95706842-9a64-48c0-9a0d-ad71cb76f175
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3815939943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.3815939943
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.32149194
Short name T22
Test name
Test status
Simulation time 10137290905 ps
CPU time 12.87 seconds
Started Jun 05 05:47:05 PM PDT 24
Finished Jun 05 05:47:18 PM PDT 24
Peak memory 205764 kb
Host smart-7502da3b-d713-411f-89c8-8c574b561883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32149
194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.32149194
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.176463033
Short name T1181
Test name
Test status
Simulation time 13843257510 ps
CPU time 17.33 seconds
Started Jun 05 05:46:54 PM PDT 24
Finished Jun 05 05:47:12 PM PDT 24
Peak memory 205748 kb
Host smart-586e487f-ee8e-4be5-b58c-9bbd7e172194
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=176463033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.176463033
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.718951124
Short name T791
Test name
Test status
Simulation time 23247135931 ps
CPU time 25.18 seconds
Started Jun 05 05:46:56 PM PDT 24
Finished Jun 05 05:47:21 PM PDT 24
Peak memory 205536 kb
Host smart-b3cd1d17-7ec0-407e-a947-6206b5a6551e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=718951124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.718951124
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3406689183
Short name T635
Test name
Test status
Simulation time 10048396768 ps
CPU time 13.88 seconds
Started Jun 05 05:46:54 PM PDT 24
Finished Jun 05 05:47:08 PM PDT 24
Peak memory 205776 kb
Host smart-3557c7f8-0957-41dc-83f5-d763ef8bfa3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34066
89183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3406689183
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.1792146261
Short name T674
Test name
Test status
Simulation time 10879451806 ps
CPU time 14.88 seconds
Started Jun 05 05:46:54 PM PDT 24
Finished Jun 05 05:47:09 PM PDT 24
Peak memory 205664 kb
Host smart-4cfb116f-5505-4b29-8b11-eab735886a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17921
46261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.1792146261
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.2505848597
Short name T1641
Test name
Test status
Simulation time 10057936418 ps
CPU time 13.02 seconds
Started Jun 05 05:46:53 PM PDT 24
Finished Jun 05 05:47:07 PM PDT 24
Peak memory 205780 kb
Host smart-fc6dc09d-3817-48f0-a5e2-f8ca39d4ee34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25058
48597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.2505848597
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.554533607
Short name T333
Test name
Test status
Simulation time 10090432424 ps
CPU time 15.43 seconds
Started Jun 05 05:46:56 PM PDT 24
Finished Jun 05 05:47:12 PM PDT 24
Peak memory 205652 kb
Host smart-2d4eedaa-0ff1-40fe-a01d-95c402b606f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55453
3607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.554533607
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.467235642
Short name T926
Test name
Test status
Simulation time 10824847414 ps
CPU time 15.28 seconds
Started Jun 05 05:46:56 PM PDT 24
Finished Jun 05 05:47:12 PM PDT 24
Peak memory 205776 kb
Host smart-99efd2c3-d122-4cbd-bc28-c00f81ccae33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46723
5642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.467235642
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.4134654340
Short name T37
Test name
Test status
Simulation time 10149353303 ps
CPU time 15.11 seconds
Started Jun 05 05:46:55 PM PDT 24
Finished Jun 05 05:47:11 PM PDT 24
Peak memory 205708 kb
Host smart-23850333-c44e-4b1f-b80d-ddf495236b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41346
54340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.4134654340
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.1935685530
Short name T1843
Test name
Test status
Simulation time 10068031093 ps
CPU time 12.81 seconds
Started Jun 05 05:47:02 PM PDT 24
Finished Jun 05 05:47:16 PM PDT 24
Peak memory 205756 kb
Host smart-7844a58c-ea99-46ca-9b22-fc9452d48a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19356
85530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.1935685530
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.3421367385
Short name T504
Test name
Test status
Simulation time 10051613319 ps
CPU time 13.22 seconds
Started Jun 05 05:47:02 PM PDT 24
Finished Jun 05 05:47:16 PM PDT 24
Peak memory 205636 kb
Host smart-44b0e5d4-e957-4efe-8749-40bec85608ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34213
67385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3421367385
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.743423234
Short name T1889
Test name
Test status
Simulation time 10097279752 ps
CPU time 13.69 seconds
Started Jun 05 05:46:57 PM PDT 24
Finished Jun 05 05:47:12 PM PDT 24
Peak memory 205736 kb
Host smart-f9549f09-1294-45ff-95d9-a33d623ee19c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74342
3234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.743423234
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.3108887842
Short name T1407
Test name
Test status
Simulation time 10080390640 ps
CPU time 13.71 seconds
Started Jun 05 05:46:57 PM PDT 24
Finished Jun 05 05:47:11 PM PDT 24
Peak memory 205540 kb
Host smart-0c145112-0c05-4148-bd0c-05dd99d47c9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31088
87842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.3108887842
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.4161143657
Short name T651
Test name
Test status
Simulation time 13257890650 ps
CPU time 16.51 seconds
Started Jun 05 05:46:55 PM PDT 24
Finished Jun 05 05:47:12 PM PDT 24
Peak memory 205664 kb
Host smart-34c0f150-297b-4391-9cae-c2ed403bc99c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41611
43657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.4161143657
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3095649835
Short name T293
Test name
Test status
Simulation time 10085951530 ps
CPU time 15.56 seconds
Started Jun 05 05:46:51 PM PDT 24
Finished Jun 05 05:47:08 PM PDT 24
Peak memory 205676 kb
Host smart-c1ee7848-f05d-4916-80b5-3574719c95d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30956
49835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3095649835
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.809322260
Short name T1570
Test name
Test status
Simulation time 23960865092 ps
CPU time 105.92 seconds
Started Jun 05 05:47:07 PM PDT 24
Finished Jun 05 05:48:54 PM PDT 24
Peak memory 205708 kb
Host smart-7e1c088f-d43d-4e92-8258-2139cfb09178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80932
2260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.809322260
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3678076171
Short name T1692
Test name
Test status
Simulation time 10051205955 ps
CPU time 13.23 seconds
Started Jun 05 05:46:55 PM PDT 24
Finished Jun 05 05:47:09 PM PDT 24
Peak memory 205732 kb
Host smart-ad54855f-ea74-4aef-a79b-95d3a13aaac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36780
76171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3678076171
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.4119719606
Short name T111
Test name
Test status
Simulation time 10127560888 ps
CPU time 13.06 seconds
Started Jun 05 05:47:03 PM PDT 24
Finished Jun 05 05:47:17 PM PDT 24
Peak memory 205592 kb
Host smart-e8f60423-e64b-4229-956c-bdc76994ba58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41197
19606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.4119719606
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.3257488133
Short name T1717
Test name
Test status
Simulation time 10099014492 ps
CPU time 12.93 seconds
Started Jun 05 05:47:01 PM PDT 24
Finished Jun 05 05:47:15 PM PDT 24
Peak memory 205748 kb
Host smart-ad5a8a0e-47c1-46ac-abd3-f726fc643311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32574
88133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.3257488133
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.1913564781
Short name T1298
Test name
Test status
Simulation time 10102610449 ps
CPU time 14.08 seconds
Started Jun 05 05:47:04 PM PDT 24
Finished Jun 05 05:47:19 PM PDT 24
Peak memory 205656 kb
Host smart-67f6daa3-6599-430b-ad6b-bc7d17041593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19135
64781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.1913564781
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.428927154
Short name T1442
Test name
Test status
Simulation time 10057551103 ps
CPU time 13.46 seconds
Started Jun 05 05:47:04 PM PDT 24
Finished Jun 05 05:47:18 PM PDT 24
Peak memory 205696 kb
Host smart-d4dda0d7-4bc1-4abe-904d-e454a62d6e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42892
7154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.428927154
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.3035957106
Short name T1763
Test name
Test status
Simulation time 10049225085 ps
CPU time 13.07 seconds
Started Jun 05 05:47:01 PM PDT 24
Finished Jun 05 05:47:15 PM PDT 24
Peak memory 205672 kb
Host smart-35902203-19ed-44fb-94e1-74c19392603a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30359
57106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.3035957106
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_eop_single_bit_handling.416221443
Short name T673
Test name
Test status
Simulation time 10111195530 ps
CPU time 13.21 seconds
Started Jun 05 05:47:03 PM PDT 24
Finished Jun 05 05:47:17 PM PDT 24
Peak memory 205864 kb
Host smart-5c12d0f6-b05b-45d8-ae4e-526935786152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41622
1443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_eop_single_bit_handling.416221443
Directory /workspace/23.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.3727825922
Short name T1126
Test name
Test status
Simulation time 10040134184 ps
CPU time 12.77 seconds
Started Jun 05 05:47:02 PM PDT 24
Finished Jun 05 05:47:16 PM PDT 24
Peak memory 205704 kb
Host smart-30b26067-e245-4e61-98ff-511539ba3194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37278
25922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.3727825922
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1336892520
Short name T1391
Test name
Test status
Simulation time 10036647400 ps
CPU time 15.79 seconds
Started Jun 05 05:47:05 PM PDT 24
Finished Jun 05 05:47:22 PM PDT 24
Peak memory 205720 kb
Host smart-0ff10fbd-1215-43de-a259-0474a5ace8bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13368
92520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1336892520
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.3532721654
Short name T262
Test name
Test status
Simulation time 16631964649 ps
CPU time 28.04 seconds
Started Jun 05 05:47:03 PM PDT 24
Finished Jun 05 05:47:31 PM PDT 24
Peak memory 205676 kb
Host smart-0b5e36ba-0b68-4e49-b222-8ed412990250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35327
21654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3532721654
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.271280686
Short name T48
Test name
Test status
Simulation time 10087745863 ps
CPU time 15.01 seconds
Started Jun 05 05:47:15 PM PDT 24
Finished Jun 05 05:47:30 PM PDT 24
Peak memory 205768 kb
Host smart-46b22365-ca67-4927-8f90-fdf9de23a77d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27128
0686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.271280686
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.1611921868
Short name T1222
Test name
Test status
Simulation time 10125793713 ps
CPU time 14.37 seconds
Started Jun 05 05:47:03 PM PDT 24
Finished Jun 05 05:47:18 PM PDT 24
Peak memory 205732 kb
Host smart-779861b9-f43a-4edf-9076-af7d94c8e449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16119
21868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1611921868
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.3378016594
Short name T951
Test name
Test status
Simulation time 10105203722 ps
CPU time 15.43 seconds
Started Jun 05 05:47:02 PM PDT 24
Finished Jun 05 05:47:18 PM PDT 24
Peak memory 205704 kb
Host smart-7f202ff5-d380-41bc-b7b5-fe53fd8999d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33780
16594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.3378016594
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.3550385235
Short name T992
Test name
Test status
Simulation time 10048559719 ps
CPU time 14.76 seconds
Started Jun 05 05:47:03 PM PDT 24
Finished Jun 05 05:47:18 PM PDT 24
Peak memory 205212 kb
Host smart-74564196-b1f7-467a-ae0c-a59cb36f616b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35503
85235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.3550385235
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.2582907465
Short name T754
Test name
Test status
Simulation time 10096048456 ps
CPU time 14.24 seconds
Started Jun 05 05:47:03 PM PDT 24
Finished Jun 05 05:47:18 PM PDT 24
Peak memory 205652 kb
Host smart-d9ba93ba-3e6a-4711-a243-0c0d14835568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25829
07465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.2582907465
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.3123017652
Short name T2004
Test name
Test status
Simulation time 10056004831 ps
CPU time 13.24 seconds
Started Jun 05 05:47:03 PM PDT 24
Finished Jun 05 05:47:17 PM PDT 24
Peak memory 205756 kb
Host smart-2840c924-cbaf-4f12-bd1f-f23bad6647a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31230
17652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.3123017652
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.1163004051
Short name T899
Test name
Test status
Simulation time 10113958418 ps
CPU time 13.97 seconds
Started Jun 05 05:46:54 PM PDT 24
Finished Jun 05 05:47:09 PM PDT 24
Peak memory 205820 kb
Host smart-7f6b672d-a8b7-46bc-98d2-f8da272e2936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11630
04051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.1163004051
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3264375132
Short name T224
Test name
Test status
Simulation time 10072877687 ps
CPU time 16.21 seconds
Started Jun 05 05:47:03 PM PDT 24
Finished Jun 05 05:47:20 PM PDT 24
Peak memory 205716 kb
Host smart-207fe2ba-5983-4a29-bfb5-d3f9ea407c97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32643
75132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3264375132
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.569483916
Short name T348
Test name
Test status
Simulation time 10092200424 ps
CPU time 15.28 seconds
Started Jun 05 05:47:03 PM PDT 24
Finished Jun 05 05:47:19 PM PDT 24
Peak memory 205652 kb
Host smart-102561bb-2555-47be-a620-3677adb5f8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56948
3916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.569483916
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.498507844
Short name T309
Test name
Test status
Simulation time 14235080352 ps
CPU time 41.9 seconds
Started Jun 05 05:47:00 PM PDT 24
Finished Jun 05 05:47:43 PM PDT 24
Peak memory 205688 kb
Host smart-71f5f4ee-ee1c-417b-9969-90e1abe408c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49850
7844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.498507844
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.1796267185
Short name T958
Test name
Test status
Simulation time 10154902357 ps
CPU time 13.29 seconds
Started Jun 05 05:47:08 PM PDT 24
Finished Jun 05 05:47:22 PM PDT 24
Peak memory 205888 kb
Host smart-a48cb0b6-f067-47a4-abbf-6b9a78c459c6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1796267185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.1796267185
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.1008526102
Short name T391
Test name
Test status
Simulation time 10067217428 ps
CPU time 15.69 seconds
Started Jun 05 05:47:09 PM PDT 24
Finished Jun 05 05:47:25 PM PDT 24
Peak memory 205776 kb
Host smart-dc418339-16d3-4865-80c6-54fa614b46c9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1008526102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.1008526102
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.2185083581
Short name T543
Test name
Test status
Simulation time 10098383041 ps
CPU time 13.48 seconds
Started Jun 05 05:47:12 PM PDT 24
Finished Jun 05 05:47:26 PM PDT 24
Peak memory 205744 kb
Host smart-4cef2faa-3d6e-4aff-857b-31592e57c8dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21850
83581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.2185083581
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.2036424122
Short name T1807
Test name
Test status
Simulation time 13978758229 ps
CPU time 18.77 seconds
Started Jun 05 05:47:01 PM PDT 24
Finished Jun 05 05:47:21 PM PDT 24
Peak memory 205704 kb
Host smart-728e3071-a285-4557-9cf7-f331fa116b55
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2036424122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.2036424122
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.3807836026
Short name T9
Test name
Test status
Simulation time 23214317292 ps
CPU time 28.64 seconds
Started Jun 05 05:47:00 PM PDT 24
Finished Jun 05 05:47:30 PM PDT 24
Peak memory 205732 kb
Host smart-5916284a-b463-42ca-8804-321ad49b4891
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3807836026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.3807836026
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2009028576
Short name T579
Test name
Test status
Simulation time 10079111958 ps
CPU time 15.44 seconds
Started Jun 05 05:47:02 PM PDT 24
Finished Jun 05 05:47:18 PM PDT 24
Peak memory 205768 kb
Host smart-7f2c64cf-9eac-49fd-a5ca-9cdc7575b070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20090
28576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2009028576
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.3878864273
Short name T879
Test name
Test status
Simulation time 10706601185 ps
CPU time 15.24 seconds
Started Jun 05 05:47:02 PM PDT 24
Finished Jun 05 05:47:18 PM PDT 24
Peak memory 205944 kb
Host smart-5d2091aa-406b-4420-8532-341f3592a20d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38788
64273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.3878864273
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.2831366301
Short name T859
Test name
Test status
Simulation time 10056719934 ps
CPU time 13.75 seconds
Started Jun 05 05:46:59 PM PDT 24
Finished Jun 05 05:47:14 PM PDT 24
Peak memory 205620 kb
Host smart-2e909e66-a336-4415-aab4-ae101a24be26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28313
66301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.2831366301
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.4047350947
Short name T1372
Test name
Test status
Simulation time 10081367265 ps
CPU time 12.56 seconds
Started Jun 05 05:47:01 PM PDT 24
Finished Jun 05 05:47:14 PM PDT 24
Peak memory 205772 kb
Host smart-11b217e6-fc37-43d5-aa9d-f43032d7b5a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40473
50947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.4047350947
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.1884085850
Short name T1837
Test name
Test status
Simulation time 10857256207 ps
CPU time 16.73 seconds
Started Jun 05 05:47:00 PM PDT 24
Finished Jun 05 05:47:17 PM PDT 24
Peak memory 205668 kb
Host smart-c0616cc6-6049-4be2-a0ae-15e375b2c65a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18840
85850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.1884085850
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1361523483
Short name T940
Test name
Test status
Simulation time 10345892867 ps
CPU time 14.91 seconds
Started Jun 05 05:47:08 PM PDT 24
Finished Jun 05 05:47:23 PM PDT 24
Peak memory 205756 kb
Host smart-d0f6655d-7e79-4b38-adee-3a36ac76941b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13615
23483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1361523483
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.93178823
Short name T413
Test name
Test status
Simulation time 10049138410 ps
CPU time 13.1 seconds
Started Jun 05 05:47:12 PM PDT 24
Finished Jun 05 05:47:25 PM PDT 24
Peak memory 205752 kb
Host smart-0a3a7a56-537f-4172-b75b-be3641a4d646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93178
823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.93178823
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.1942563142
Short name T1568
Test name
Test status
Simulation time 10052803152 ps
CPU time 14.95 seconds
Started Jun 05 05:47:11 PM PDT 24
Finished Jun 05 05:47:26 PM PDT 24
Peak memory 205648 kb
Host smart-8b616735-6c13-4226-92cc-a06fd6df9444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19425
63142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.1942563142
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.1924302968
Short name T1948
Test name
Test status
Simulation time 10090380986 ps
CPU time 12.88 seconds
Started Jun 05 05:47:03 PM PDT 24
Finished Jun 05 05:47:17 PM PDT 24
Peak memory 205708 kb
Host smart-7939f7b5-a813-4bda-9950-58021aa9960a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19243
02968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.1924302968
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.2034544965
Short name T52
Test name
Test status
Simulation time 10114816924 ps
CPU time 14.45 seconds
Started Jun 05 05:47:00 PM PDT 24
Finished Jun 05 05:47:15 PM PDT 24
Peak memory 205612 kb
Host smart-7f6243b8-4db1-4cba-bcc3-8ae60f0684b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20345
44965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.2034544965
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.4126096062
Short name T1574
Test name
Test status
Simulation time 13192619091 ps
CPU time 16.76 seconds
Started Jun 05 05:47:15 PM PDT 24
Finished Jun 05 05:47:33 PM PDT 24
Peak memory 205776 kb
Host smart-5c26c2d6-e943-49cf-8c22-b65479b2a9a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41260
96062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.4126096062
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2346923224
Short name T901
Test name
Test status
Simulation time 10090989263 ps
CPU time 14.78 seconds
Started Jun 05 05:47:03 PM PDT 24
Finished Jun 05 05:47:19 PM PDT 24
Peak memory 205704 kb
Host smart-f04c50d2-6cfa-4e9f-96d7-c87f4a924b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23469
23224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2346923224
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.3800445757
Short name T1282
Test name
Test status
Simulation time 17291039784 ps
CPU time 64.77 seconds
Started Jun 05 05:47:04 PM PDT 24
Finished Jun 05 05:48:10 PM PDT 24
Peak memory 205732 kb
Host smart-5a54ead8-1464-49a0-9fad-855f0bacfa57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38004
45757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.3800445757
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.354421136
Short name T591
Test name
Test status
Simulation time 10072105853 ps
CPU time 15.75 seconds
Started Jun 05 05:47:01 PM PDT 24
Finished Jun 05 05:47:18 PM PDT 24
Peak memory 205780 kb
Host smart-736c8deb-1131-449a-b2a7-ac0fade18f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35442
1136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.354421136
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.2438098463
Short name T1785
Test name
Test status
Simulation time 10152150083 ps
CPU time 13.92 seconds
Started Jun 05 05:47:01 PM PDT 24
Finished Jun 05 05:47:16 PM PDT 24
Peak memory 205668 kb
Host smart-615fa057-92df-4fb3-83cb-aa9a25e07b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24380
98463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.2438098463
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.3094917050
Short name T1386
Test name
Test status
Simulation time 10120435902 ps
CPU time 13.65 seconds
Started Jun 05 05:47:05 PM PDT 24
Finished Jun 05 05:47:19 PM PDT 24
Peak memory 205808 kb
Host smart-1000f749-1dc9-4f0b-b059-497439bcf61c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30949
17050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.3094917050
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.868073871
Short name T955
Test name
Test status
Simulation time 10094813732 ps
CPU time 12.9 seconds
Started Jun 05 05:47:00 PM PDT 24
Finished Jun 05 05:47:14 PM PDT 24
Peak memory 205684 kb
Host smart-e123d5ce-e1c0-4d92-b319-5f8abf36c767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86807
3871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.868073871
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.76330336
Short name T2017
Test name
Test status
Simulation time 10069841033 ps
CPU time 15.39 seconds
Started Jun 05 05:47:15 PM PDT 24
Finished Jun 05 05:47:31 PM PDT 24
Peak memory 205612 kb
Host smart-1ddf52aa-ca4e-4783-8c8d-e7ea11edd1d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76330
336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.76330336
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.773133296
Short name T130
Test name
Test status
Simulation time 10085016916 ps
CPU time 13.78 seconds
Started Jun 05 05:47:08 PM PDT 24
Finished Jun 05 05:47:23 PM PDT 24
Peak memory 205728 kb
Host smart-506e7781-b66c-4792-b575-e6004a338918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77313
3296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.773133296
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_eop_single_bit_handling.2097172158
Short name T1855
Test name
Test status
Simulation time 10044050963 ps
CPU time 13 seconds
Started Jun 05 05:47:09 PM PDT 24
Finished Jun 05 05:47:23 PM PDT 24
Peak memory 205672 kb
Host smart-091bdf83-5121-4bee-b5e4-2e73ac42c75b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20971
72158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_eop_single_bit_handling.2097172158
Directory /workspace/24.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3164515288
Short name T638
Test name
Test status
Simulation time 10046203218 ps
CPU time 12.95 seconds
Started Jun 05 05:47:11 PM PDT 24
Finished Jun 05 05:47:24 PM PDT 24
Peak memory 205724 kb
Host smart-065c4f05-a29d-4d35-aea2-fdf6f877f403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31645
15288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3164515288
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.3042823954
Short name T1450
Test name
Test status
Simulation time 10036496082 ps
CPU time 14.22 seconds
Started Jun 05 05:47:07 PM PDT 24
Finished Jun 05 05:47:22 PM PDT 24
Peak memory 205708 kb
Host smart-20148157-2e5e-4d65-8f55-8aed3964133c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30428
23954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.3042823954
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.3133471292
Short name T1735
Test name
Test status
Simulation time 30270140703 ps
CPU time 58.57 seconds
Started Jun 05 05:47:03 PM PDT 24
Finished Jun 05 05:48:02 PM PDT 24
Peak memory 205224 kb
Host smart-40cc5146-f73e-42c5-9f0d-acc0b7ed9f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31334
71292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.3133471292
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.2750052506
Short name T723
Test name
Test status
Simulation time 10118551977 ps
CPU time 14.65 seconds
Started Jun 05 05:47:11 PM PDT 24
Finished Jun 05 05:47:26 PM PDT 24
Peak memory 205728 kb
Host smart-30354f58-78e7-44ee-85b8-d499d6e77742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27500
52506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.2750052506
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.382568641
Short name T1497
Test name
Test status
Simulation time 10076622138 ps
CPU time 14.59 seconds
Started Jun 05 05:47:10 PM PDT 24
Finished Jun 05 05:47:25 PM PDT 24
Peak memory 205780 kb
Host smart-c712231f-1f56-4909-a006-22eb76253260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38256
8641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.382568641
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.963207271
Short name T1742
Test name
Test status
Simulation time 10143532940 ps
CPU time 14.93 seconds
Started Jun 05 05:47:13 PM PDT 24
Finished Jun 05 05:47:28 PM PDT 24
Peak memory 205696 kb
Host smart-b04bc8db-db06-43bb-ae0b-65c87ebd2c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96320
7271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.963207271
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.1286435563
Short name T1610
Test name
Test status
Simulation time 10064816443 ps
CPU time 14.01 seconds
Started Jun 05 05:47:08 PM PDT 24
Finished Jun 05 05:47:22 PM PDT 24
Peak memory 205712 kb
Host smart-bc8a51f0-dcdf-427c-84a2-817329edf9d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12864
35563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.1286435563
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.3870102705
Short name T1528
Test name
Test status
Simulation time 10078358584 ps
CPU time 13.1 seconds
Started Jun 05 05:47:15 PM PDT 24
Finished Jun 05 05:47:29 PM PDT 24
Peak memory 205792 kb
Host smart-a5b73a9d-95c8-4bb4-a87f-dc5de2be7e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38701
02705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.3870102705
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.3551345400
Short name T567
Test name
Test status
Simulation time 10080636060 ps
CPU time 17.05 seconds
Started Jun 05 05:47:15 PM PDT 24
Finished Jun 05 05:47:33 PM PDT 24
Peak memory 205792 kb
Host smart-6d2a915a-bab6-4a3d-a8b3-3e182d5ddbda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35513
45400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3551345400
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.990235520
Short name T1908
Test name
Test status
Simulation time 10107372415 ps
CPU time 14.9 seconds
Started Jun 05 05:47:02 PM PDT 24
Finished Jun 05 05:47:17 PM PDT 24
Peak memory 205668 kb
Host smart-344c4ce3-ca79-45d0-930a-66f6795a04ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99023
5520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.990235520
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3190137118
Short name T984
Test name
Test status
Simulation time 10141826408 ps
CPU time 13.8 seconds
Started Jun 05 05:47:09 PM PDT 24
Finished Jun 05 05:47:24 PM PDT 24
Peak memory 205748 kb
Host smart-9126b3c2-bc22-4f9e-9449-5478a4555383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31901
37118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3190137118
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.275462299
Short name T1150
Test name
Test status
Simulation time 10059907239 ps
CPU time 14.9 seconds
Started Jun 05 05:47:09 PM PDT 24
Finished Jun 05 05:47:25 PM PDT 24
Peak memory 205716 kb
Host smart-e1e1afab-fc5f-4ca1-8eab-267c9f24dc01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27546
2299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.275462299
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.1493753438
Short name T1862
Test name
Test status
Simulation time 19135258538 ps
CPU time 268.21 seconds
Started Jun 05 05:47:14 PM PDT 24
Finished Jun 05 05:51:42 PM PDT 24
Peak memory 205724 kb
Host smart-92a0ccea-87fe-45bc-8cb7-3ec4998c4c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14937
53438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.1493753438
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.2691174245
Short name T375
Test name
Test status
Simulation time 10169803902 ps
CPU time 13.26 seconds
Started Jun 05 05:47:18 PM PDT 24
Finished Jun 05 05:47:32 PM PDT 24
Peak memory 205780 kb
Host smart-fba0db40-553e-48fd-b167-d9caa266fa2f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2691174245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.2691174245
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.612483418
Short name T932
Test name
Test status
Simulation time 10048545981 ps
CPU time 16.15 seconds
Started Jun 05 05:47:17 PM PDT 24
Finished Jun 05 05:47:33 PM PDT 24
Peak memory 205748 kb
Host smart-07be5015-95ef-4c5a-9de7-fa8b9607b402
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=612483418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.612483418
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.1008722516
Short name T1709
Test name
Test status
Simulation time 10116877523 ps
CPU time 16.02 seconds
Started Jun 05 05:47:18 PM PDT 24
Finished Jun 05 05:47:36 PM PDT 24
Peak memory 205760 kb
Host smart-cb1d44fd-6529-4c97-997b-619ac5009b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10087
22516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.1008722516
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.3442525200
Short name T1376
Test name
Test status
Simulation time 14331976374 ps
CPU time 17.05 seconds
Started Jun 05 05:47:09 PM PDT 24
Finished Jun 05 05:47:27 PM PDT 24
Peak memory 205720 kb
Host smart-7fab8df7-054c-4224-b3b8-a2eb22a86831
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3442525200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.3442525200
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.2000719269
Short name T461
Test name
Test status
Simulation time 23281800428 ps
CPU time 26.16 seconds
Started Jun 05 05:47:15 PM PDT 24
Finished Jun 05 05:47:41 PM PDT 24
Peak memory 205640 kb
Host smart-8da1f0d9-03ad-42be-8716-bbfe8410181d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2000719269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.2000719269
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.2829554326
Short name T31
Test name
Test status
Simulation time 10075652719 ps
CPU time 14.75 seconds
Started Jun 05 05:47:12 PM PDT 24
Finished Jun 05 05:47:28 PM PDT 24
Peak memory 205592 kb
Host smart-59b6f648-35c3-4be7-aa68-6a2dd6b8fb86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28295
54326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2829554326
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.3033279242
Short name T1255
Test name
Test status
Simulation time 10048266642 ps
CPU time 13.83 seconds
Started Jun 05 05:47:15 PM PDT 24
Finished Jun 05 05:47:29 PM PDT 24
Peak memory 205748 kb
Host smart-9aace293-e443-4bd8-860e-4de710fbf3c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30332
79242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.3033279242
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.1371419809
Short name T1678
Test name
Test status
Simulation time 10485457568 ps
CPU time 14.12 seconds
Started Jun 05 05:47:10 PM PDT 24
Finished Jun 05 05:47:25 PM PDT 24
Peak memory 205684 kb
Host smart-477c5faa-e595-4558-8dc7-127b867bc5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13714
19809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.1371419809
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.1237644845
Short name T336
Test name
Test status
Simulation time 10043222609 ps
CPU time 16.13 seconds
Started Jun 05 05:47:12 PM PDT 24
Finished Jun 05 05:47:29 PM PDT 24
Peak memory 205620 kb
Host smart-3dd1a19b-94f0-44e9-ac3f-4e83221c8280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12376
44845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.1237644845
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.9778565
Short name T1455
Test name
Test status
Simulation time 10054687492 ps
CPU time 12.87 seconds
Started Jun 05 05:47:14 PM PDT 24
Finished Jun 05 05:47:27 PM PDT 24
Peak memory 205788 kb
Host smart-85911be6-3b98-41cb-9c45-9bc6d0a23b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97785
65 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.9778565
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1947337504
Short name T374
Test name
Test status
Simulation time 10658344576 ps
CPU time 14.37 seconds
Started Jun 05 05:47:09 PM PDT 24
Finished Jun 05 05:47:24 PM PDT 24
Peak memory 205688 kb
Host smart-c89a8a3c-f4bf-4a56-a2eb-aafeed1e16d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19473
37504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1947337504
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.3372414028
Short name T642
Test name
Test status
Simulation time 10095129671 ps
CPU time 13.55 seconds
Started Jun 05 05:47:07 PM PDT 24
Finished Jun 05 05:47:21 PM PDT 24
Peak memory 205640 kb
Host smart-4ff5db1f-f3f1-489f-82b7-9a2bd3496598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33724
14028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.3372414028
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.1555847401
Short name T1508
Test name
Test status
Simulation time 10067434160 ps
CPU time 15.74 seconds
Started Jun 05 05:47:19 PM PDT 24
Finished Jun 05 05:47:36 PM PDT 24
Peak memory 205504 kb
Host smart-ce15247a-1d59-464f-a85c-66cc9fbd58e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15558
47401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.1555847401
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.2128188467
Short name T667
Test name
Test status
Simulation time 10041448061 ps
CPU time 13.13 seconds
Started Jun 05 05:47:17 PM PDT 24
Finished Jun 05 05:47:31 PM PDT 24
Peak memory 205652 kb
Host smart-ae19bdf5-2c9f-48c8-96db-be6697805dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21281
88467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2128188467
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.1854450733
Short name T396
Test name
Test status
Simulation time 10076655982 ps
CPU time 13.86 seconds
Started Jun 05 05:47:09 PM PDT 24
Finished Jun 05 05:47:24 PM PDT 24
Peak memory 205664 kb
Host smart-2d75f98b-4030-4c48-9298-fb0df34a6863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18544
50733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.1854450733
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.2430860625
Short name T1044
Test name
Test status
Simulation time 10133731964 ps
CPU time 16.06 seconds
Started Jun 05 05:47:09 PM PDT 24
Finished Jun 05 05:47:25 PM PDT 24
Peak memory 205712 kb
Host smart-d9638d7f-af8a-4fa5-99c5-aa2b414dadc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24308
60625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.2430860625
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.3522004677
Short name T1962
Test name
Test status
Simulation time 13197246234 ps
CPU time 15.61 seconds
Started Jun 05 05:47:07 PM PDT 24
Finished Jun 05 05:47:24 PM PDT 24
Peak memory 205616 kb
Host smart-88f5c4c5-e517-4ff9-a032-a35b79b2139d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35220
04677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.3522004677
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.3502150258
Short name T1080
Test name
Test status
Simulation time 10114420460 ps
CPU time 13.93 seconds
Started Jun 05 05:47:14 PM PDT 24
Finished Jun 05 05:47:28 PM PDT 24
Peak memory 205700 kb
Host smart-8b175175-ecfd-49ef-b5cd-270a8bfc6684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35021
50258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3502150258
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.3292674498
Short name T1456
Test name
Test status
Simulation time 21697997465 ps
CPU time 354.39 seconds
Started Jun 05 05:47:09 PM PDT 24
Finished Jun 05 05:53:05 PM PDT 24
Peak memory 205656 kb
Host smart-df9e8f55-edbc-46d8-b282-2d0eb06ee028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32926
74498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.3292674498
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.967436787
Short name T1207
Test name
Test status
Simulation time 10046611408 ps
CPU time 14.42 seconds
Started Jun 05 05:47:15 PM PDT 24
Finished Jun 05 05:47:30 PM PDT 24
Peak memory 205676 kb
Host smart-c741c20b-94b3-42f7-b4b4-06c58a6366b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96743
6787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.967436787
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1559608033
Short name T114
Test name
Test status
Simulation time 10102236626 ps
CPU time 12.68 seconds
Started Jun 05 05:47:09 PM PDT 24
Finished Jun 05 05:47:23 PM PDT 24
Peak memory 205672 kb
Host smart-107d8970-72b3-446c-aafe-1ee3f0e6dade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15596
08033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1559608033
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.4030354592
Short name T468
Test name
Test status
Simulation time 10085556440 ps
CPU time 14.12 seconds
Started Jun 05 05:47:15 PM PDT 24
Finished Jun 05 05:47:29 PM PDT 24
Peak memory 205692 kb
Host smart-d704774b-c1ae-417e-9f04-661e6240f954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40303
54592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.4030354592
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3674670017
Short name T979
Test name
Test status
Simulation time 10076252319 ps
CPU time 12.52 seconds
Started Jun 05 05:47:12 PM PDT 24
Finished Jun 05 05:47:25 PM PDT 24
Peak memory 205704 kb
Host smart-46964936-4790-42b2-a861-87b4663d64f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36746
70017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3674670017
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1361578644
Short name T1110
Test name
Test status
Simulation time 10070803466 ps
CPU time 14.58 seconds
Started Jun 05 05:47:13 PM PDT 24
Finished Jun 05 05:47:28 PM PDT 24
Peak memory 205752 kb
Host smart-bb50b101-7407-42bc-9feb-ecec052b7d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13615
78644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1361578644
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.3855047313
Short name T2020
Test name
Test status
Simulation time 10055474571 ps
CPU time 13.55 seconds
Started Jun 05 05:47:19 PM PDT 24
Finished Jun 05 05:47:33 PM PDT 24
Peak memory 205688 kb
Host smart-e4ae1add-e4c3-4765-96fc-0ce3f2096ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38550
47313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.3855047313
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_eop_single_bit_handling.3781617105
Short name T797
Test name
Test status
Simulation time 10088599844 ps
CPU time 14.41 seconds
Started Jun 05 05:47:14 PM PDT 24
Finished Jun 05 05:47:29 PM PDT 24
Peak memory 205648 kb
Host smart-141aa325-3e79-4589-b53f-2e5ca729aebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37816
17105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_eop_single_bit_handling.3781617105
Directory /workspace/25.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.2614111820
Short name T1702
Test name
Test status
Simulation time 10078235675 ps
CPU time 14.25 seconds
Started Jun 05 05:47:09 PM PDT 24
Finished Jun 05 05:47:24 PM PDT 24
Peak memory 205756 kb
Host smart-e94c9e60-d60a-4dfe-8453-61102d965dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26141
11820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.2614111820
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.1133315486
Short name T1238
Test name
Test status
Simulation time 10041924173 ps
CPU time 14.08 seconds
Started Jun 05 05:47:17 PM PDT 24
Finished Jun 05 05:47:32 PM PDT 24
Peak memory 205728 kb
Host smart-fc4e472f-92ca-4170-987b-22c9cec73a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11333
15486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.1133315486
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.3331018538
Short name T1296
Test name
Test status
Simulation time 23029668745 ps
CPU time 44.58 seconds
Started Jun 05 05:47:17 PM PDT 24
Finished Jun 05 05:48:02 PM PDT 24
Peak memory 205588 kb
Host smart-5d60c550-6778-4787-8a2b-0a196a67925d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33310
18538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.3331018538
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.267854838
Short name T1161
Test name
Test status
Simulation time 10097216795 ps
CPU time 13.64 seconds
Started Jun 05 05:47:15 PM PDT 24
Finished Jun 05 05:47:30 PM PDT 24
Peak memory 205668 kb
Host smart-4b9049e5-261e-4a99-ad0c-a6824593d0c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26785
4838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.267854838
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1559463442
Short name T1086
Test name
Test status
Simulation time 10153612512 ps
CPU time 12.52 seconds
Started Jun 05 05:47:14 PM PDT 24
Finished Jun 05 05:47:27 PM PDT 24
Peak memory 205804 kb
Host smart-e499c030-01ce-4de9-9de2-63d53c45cdb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15594
63442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1559463442
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.1495101400
Short name T606
Test name
Test status
Simulation time 10070199770 ps
CPU time 12.75 seconds
Started Jun 05 05:47:12 PM PDT 24
Finished Jun 05 05:47:26 PM PDT 24
Peak memory 205508 kb
Host smart-d8b92e04-4399-4bac-b78b-75053c2604e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14951
01400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.1495101400
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.4250543327
Short name T60
Test name
Test status
Simulation time 10040653193 ps
CPU time 13.21 seconds
Started Jun 05 05:47:09 PM PDT 24
Finished Jun 05 05:47:23 PM PDT 24
Peak memory 205664 kb
Host smart-c85d69a7-c7c5-4b6e-a2b5-4e2079960f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42505
43327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.4250543327
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.2136905914
Short name T1454
Test name
Test status
Simulation time 10082440117 ps
CPU time 13.56 seconds
Started Jun 05 05:47:11 PM PDT 24
Finished Jun 05 05:47:25 PM PDT 24
Peak memory 205620 kb
Host smart-12771261-dd11-4e9a-9e4b-da119a30d610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21369
05914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.2136905914
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3056463530
Short name T1202
Test name
Test status
Simulation time 10075113375 ps
CPU time 13.26 seconds
Started Jun 05 05:47:10 PM PDT 24
Finished Jun 05 05:47:24 PM PDT 24
Peak memory 205676 kb
Host smart-2aff675e-e7ac-48d4-bc17-57c086ce1d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30564
63530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3056463530
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.348777879
Short name T887
Test name
Test status
Simulation time 10118660949 ps
CPU time 12.93 seconds
Started Jun 05 05:47:15 PM PDT 24
Finished Jun 05 05:47:29 PM PDT 24
Peak memory 205796 kb
Host smart-af93907d-c51f-435e-88c1-c6e71689fade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34877
7879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.348777879
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.2662733875
Short name T1098
Test name
Test status
Simulation time 10144918025 ps
CPU time 13.28 seconds
Started Jun 05 05:47:12 PM PDT 24
Finished Jun 05 05:47:26 PM PDT 24
Peak memory 205776 kb
Host smart-c55a5d2c-8e05-4664-9c30-534677626540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26627
33875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.2662733875
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.1119975626
Short name T24
Test name
Test status
Simulation time 10080275896 ps
CPU time 13.44 seconds
Started Jun 05 05:47:09 PM PDT 24
Finished Jun 05 05:47:23 PM PDT 24
Peak memory 205728 kb
Host smart-52aced53-a11c-4a7b-ac63-f026b56626a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11199
75626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.1119975626
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.2142203676
Short name T1809
Test name
Test status
Simulation time 24023453926 ps
CPU time 152.86 seconds
Started Jun 05 05:47:12 PM PDT 24
Finished Jun 05 05:49:45 PM PDT 24
Peak memory 205672 kb
Host smart-1765f9d1-dd57-4921-9e62-a0e3c340c3d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21422
03676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.2142203676
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.3026418608
Short name T1540
Test name
Test status
Simulation time 10145222149 ps
CPU time 14.97 seconds
Started Jun 05 05:47:23 PM PDT 24
Finished Jun 05 05:47:38 PM PDT 24
Peak memory 205888 kb
Host smart-a13eb36c-e325-4086-8727-e6036889de47
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3026418608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.3026418608
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.57686026
Short name T1010
Test name
Test status
Simulation time 10069380700 ps
CPU time 14.17 seconds
Started Jun 05 05:47:17 PM PDT 24
Finished Jun 05 05:47:32 PM PDT 24
Peak memory 205796 kb
Host smart-b8955af6-8968-49b2-8d0f-f04996c4b07b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=57686026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.57686026
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.2770305436
Short name T1115
Test name
Test status
Simulation time 10101491691 ps
CPU time 13.12 seconds
Started Jun 05 05:47:20 PM PDT 24
Finished Jun 05 05:47:33 PM PDT 24
Peak memory 205688 kb
Host smart-e5c37555-0320-4bff-998d-886022513942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27703
05436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.2770305436
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.1206524900
Short name T1135
Test name
Test status
Simulation time 13978653726 ps
CPU time 17.7 seconds
Started Jun 05 05:47:22 PM PDT 24
Finished Jun 05 05:47:40 PM PDT 24
Peak memory 205784 kb
Host smart-78f1bdb4-db71-455d-9bb9-d8d847ae0e91
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1206524900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.1206524900
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.1080869007
Short name T1211
Test name
Test status
Simulation time 23319698660 ps
CPU time 25.34 seconds
Started Jun 05 05:47:22 PM PDT 24
Finished Jun 05 05:47:48 PM PDT 24
Peak memory 205764 kb
Host smart-f7e873f5-49b5-4cb0-99ed-2af4dcc1ee95
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1080869007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.1080869007
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.674013376
Short name T300
Test name
Test status
Simulation time 10059260099 ps
CPU time 13.92 seconds
Started Jun 05 05:47:18 PM PDT 24
Finished Jun 05 05:47:33 PM PDT 24
Peak memory 205728 kb
Host smart-ca696ed6-a8f7-406c-8cb9-06f777bd05ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67401
3376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.674013376
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.1367406142
Short name T1099
Test name
Test status
Simulation time 10044569997 ps
CPU time 13.88 seconds
Started Jun 05 05:47:17 PM PDT 24
Finished Jun 05 05:47:31 PM PDT 24
Peak memory 205728 kb
Host smart-030219ca-a118-4caa-a3ea-4f3d1606cd49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13674
06142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.1367406142
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.4050674407
Short name T172
Test name
Test status
Simulation time 11251641490 ps
CPU time 19.18 seconds
Started Jun 05 05:47:15 PM PDT 24
Finished Jun 05 05:47:35 PM PDT 24
Peak memory 205724 kb
Host smart-10b95c7c-b0bb-4c13-a5e2-55e079f1d9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40506
74407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.4050674407
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.2599526015
Short name T707
Test name
Test status
Simulation time 10040858981 ps
CPU time 14.79 seconds
Started Jun 05 05:47:20 PM PDT 24
Finished Jun 05 05:47:35 PM PDT 24
Peak memory 205720 kb
Host smart-679bff39-773f-40cb-8ec4-8eec127a273c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25995
26015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2599526015
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.2274953257
Short name T469
Test name
Test status
Simulation time 10062723792 ps
CPU time 14.33 seconds
Started Jun 05 05:47:17 PM PDT 24
Finished Jun 05 05:47:32 PM PDT 24
Peak memory 205652 kb
Host smart-87906567-9aa3-4ecc-951a-f422d1c5170d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22749
53257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2274953257
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.3644933678
Short name T848
Test name
Test status
Simulation time 10898534269 ps
CPU time 15.95 seconds
Started Jun 05 05:47:20 PM PDT 24
Finished Jun 05 05:47:37 PM PDT 24
Peak memory 205768 kb
Host smart-f5601aa6-e54e-4972-8d56-5fbfcb752175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36449
33678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.3644933678
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.710107912
Short name T1053
Test name
Test status
Simulation time 10096623702 ps
CPU time 13.82 seconds
Started Jun 05 05:47:19 PM PDT 24
Finished Jun 05 05:47:33 PM PDT 24
Peak memory 205600 kb
Host smart-f1b7f895-3115-464f-a788-016f3aa816c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71010
7912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.710107912
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.1338360016
Short name T67
Test name
Test status
Simulation time 10150642622 ps
CPU time 14.85 seconds
Started Jun 05 05:47:18 PM PDT 24
Finished Jun 05 05:47:33 PM PDT 24
Peak memory 205692 kb
Host smart-d98a496b-4090-44e5-bf5b-aa79427cf53a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13383
60016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.1338360016
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2862655007
Short name T915
Test name
Test status
Simulation time 10051896464 ps
CPU time 14.21 seconds
Started Jun 05 05:47:25 PM PDT 24
Finished Jun 05 05:47:40 PM PDT 24
Peak memory 205912 kb
Host smart-89d2b5b0-aa17-4935-ad53-7de4d5663721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28626
55007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2862655007
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.603099076
Short name T1975
Test name
Test status
Simulation time 10078843165 ps
CPU time 13.45 seconds
Started Jun 05 05:47:18 PM PDT 24
Finished Jun 05 05:47:33 PM PDT 24
Peak memory 205776 kb
Host smart-59392f02-6448-4b9c-a9aa-d84e1d18eb0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60309
9076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.603099076
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.2087400591
Short name T800
Test name
Test status
Simulation time 10154144412 ps
CPU time 16.62 seconds
Started Jun 05 05:47:20 PM PDT 24
Finished Jun 05 05:47:37 PM PDT 24
Peak memory 205720 kb
Host smart-8a9a8ddd-5d7e-48f5-99d6-036d94294db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20874
00591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.2087400591
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.1788897649
Short name T467
Test name
Test status
Simulation time 13236110981 ps
CPU time 16.39 seconds
Started Jun 05 05:47:17 PM PDT 24
Finished Jun 05 05:47:34 PM PDT 24
Peak memory 205876 kb
Host smart-4e24e5cd-2909-456c-ba71-8aa511d14961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17888
97649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.1788897649
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.288536773
Short name T475
Test name
Test status
Simulation time 10118018282 ps
CPU time 12.77 seconds
Started Jun 05 05:47:18 PM PDT 24
Finished Jun 05 05:47:32 PM PDT 24
Peak memory 205732 kb
Host smart-f22e1349-da96-405a-8696-a382f3912aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28853
6773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.288536773
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.497479721
Short name T1095
Test name
Test status
Simulation time 10046951462 ps
CPU time 14.09 seconds
Started Jun 05 05:47:20 PM PDT 24
Finished Jun 05 05:47:35 PM PDT 24
Peak memory 205684 kb
Host smart-8c16c7d7-1afe-442e-9c45-471380e2a3da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49747
9721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.497479721
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.1173081968
Short name T1438
Test name
Test status
Simulation time 10130485837 ps
CPU time 16.39 seconds
Started Jun 05 05:47:24 PM PDT 24
Finished Jun 05 05:47:42 PM PDT 24
Peak memory 205844 kb
Host smart-2b47d9ad-f276-4177-a628-87fc69ce8d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11730
81968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.1173081968
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.577035067
Short name T1158
Test name
Test status
Simulation time 10157789916 ps
CPU time 16.54 seconds
Started Jun 05 05:47:18 PM PDT 24
Finished Jun 05 05:47:36 PM PDT 24
Peak memory 205728 kb
Host smart-240de051-9e66-449d-9164-559b9369f737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57703
5067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.577035067
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.3492077724
Short name T691
Test name
Test status
Simulation time 10088488647 ps
CPU time 12.68 seconds
Started Jun 05 05:47:16 PM PDT 24
Finished Jun 05 05:47:29 PM PDT 24
Peak memory 205684 kb
Host smart-5dc6d117-7bc0-4ab3-8fb2-cd3412cdadbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34920
77724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.3492077724
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3286500947
Short name T1434
Test name
Test status
Simulation time 10081458097 ps
CPU time 16.35 seconds
Started Jun 05 05:47:19 PM PDT 24
Finished Jun 05 05:47:36 PM PDT 24
Peak memory 205616 kb
Host smart-1feaf363-4377-4598-9171-18e24689cb05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32865
00947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3286500947
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.3749441149
Short name T870
Test name
Test status
Simulation time 10051991269 ps
CPU time 17.8 seconds
Started Jun 05 05:47:20 PM PDT 24
Finished Jun 05 05:47:38 PM PDT 24
Peak memory 205720 kb
Host smart-f18e143a-b5db-4d12-851d-47b2c6865af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37494
41149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.3749441149
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_eop_single_bit_handling.3043250703
Short name T315
Test name
Test status
Simulation time 10077614681 ps
CPU time 14.25 seconds
Started Jun 05 05:47:21 PM PDT 24
Finished Jun 05 05:47:35 PM PDT 24
Peak memory 205708 kb
Host smart-a9591364-dc90-443a-b886-55f4ee6c1d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30432
50703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_eop_single_bit_handling.3043250703
Directory /workspace/26.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.1491432532
Short name T1341
Test name
Test status
Simulation time 10071376779 ps
CPU time 15.94 seconds
Started Jun 05 05:47:21 PM PDT 24
Finished Jun 05 05:47:37 PM PDT 24
Peak memory 205612 kb
Host smart-e5365f53-e390-4433-a1ad-6fda0bb339aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14914
32532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.1491432532
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3151599126
Short name T934
Test name
Test status
Simulation time 10027421517 ps
CPU time 12.91 seconds
Started Jun 05 05:47:17 PM PDT 24
Finished Jun 05 05:47:31 PM PDT 24
Peak memory 205672 kb
Host smart-17259d5f-23a1-4161-95af-4c54ed07a2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31515
99126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3151599126
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3644080538
Short name T1578
Test name
Test status
Simulation time 31952616600 ps
CPU time 60.27 seconds
Started Jun 05 05:47:19 PM PDT 24
Finished Jun 05 05:48:20 PM PDT 24
Peak memory 205700 kb
Host smart-ae8a36a5-f3a5-4428-a126-73f7a6da6c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36440
80538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3644080538
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.886853557
Short name T817
Test name
Test status
Simulation time 10064700866 ps
CPU time 13.24 seconds
Started Jun 05 05:47:15 PM PDT 24
Finished Jun 05 05:47:29 PM PDT 24
Peak memory 205696 kb
Host smart-de5e5d82-b825-4310-b7f5-bcb2c8bde62c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88685
3557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.886853557
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2767257360
Short name T1594
Test name
Test status
Simulation time 10087424882 ps
CPU time 14.18 seconds
Started Jun 05 05:47:22 PM PDT 24
Finished Jun 05 05:47:36 PM PDT 24
Peak memory 205728 kb
Host smart-cec57047-78c6-40d6-9ea5-9696eddc8f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27672
57360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2767257360
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.180261594
Short name T1900
Test name
Test status
Simulation time 10103090532 ps
CPU time 13.61 seconds
Started Jun 05 05:47:17 PM PDT 24
Finished Jun 05 05:47:31 PM PDT 24
Peak memory 205604 kb
Host smart-229df9ad-876f-40ab-97ae-0993568431df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18026
1594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.180261594
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.2580216622
Short name T424
Test name
Test status
Simulation time 10062653644 ps
CPU time 13.11 seconds
Started Jun 05 05:47:16 PM PDT 24
Finished Jun 05 05:47:30 PM PDT 24
Peak memory 205728 kb
Host smart-85b7cc1b-04cb-4883-89b2-dc366be1d767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25802
16622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.2580216622
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3100088227
Short name T1476
Test name
Test status
Simulation time 10050089114 ps
CPU time 15.87 seconds
Started Jun 05 05:47:20 PM PDT 24
Finished Jun 05 05:47:37 PM PDT 24
Peak memory 205680 kb
Host smart-a5979d80-d137-4598-b9af-57da9185edcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31000
88227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3100088227
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.3754499683
Short name T1320
Test name
Test status
Simulation time 10094223109 ps
CPU time 13.53 seconds
Started Jun 05 05:47:16 PM PDT 24
Finished Jun 05 05:47:30 PM PDT 24
Peak memory 205680 kb
Host smart-46634a7d-b4da-4a71-b126-02853eb22e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37544
99683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.3754499683
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.1113101119
Short name T131
Test name
Test status
Simulation time 10162836037 ps
CPU time 15.65 seconds
Started Jun 05 05:47:30 PM PDT 24
Finished Jun 05 05:47:46 PM PDT 24
Peak memory 205808 kb
Host smart-2cd5c478-8c41-4363-af0a-a19dd4310602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11131
01119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1113101119
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.2612293295
Short name T1149
Test name
Test status
Simulation time 10080907907 ps
CPU time 13.13 seconds
Started Jun 05 05:47:15 PM PDT 24
Finished Jun 05 05:47:29 PM PDT 24
Peak memory 205704 kb
Host smart-f90c667f-de65-482f-8d44-93639e2e3649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26122
93295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.2612293295
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.289369335
Short name T1215
Test name
Test status
Simulation time 10076134075 ps
CPU time 15.12 seconds
Started Jun 05 05:47:17 PM PDT 24
Finished Jun 05 05:47:32 PM PDT 24
Peak memory 205704 kb
Host smart-443fab71-596c-4f69-b50c-d695d5cfc5aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28936
9335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.289369335
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.2925942804
Short name T1312
Test name
Test status
Simulation time 21275292030 ps
CPU time 343.53 seconds
Started Jun 05 05:47:18 PM PDT 24
Finished Jun 05 05:53:02 PM PDT 24
Peak memory 205668 kb
Host smart-fa551c88-ac3e-455c-8003-90ab8dca8782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29259
42804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.2925942804
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.438063785
Short name T970
Test name
Test status
Simulation time 10140749518 ps
CPU time 13.65 seconds
Started Jun 05 05:47:24 PM PDT 24
Finished Jun 05 05:47:38 PM PDT 24
Peak memory 205664 kb
Host smart-b43a856b-5f30-4d3f-bb37-0a75cf46901d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=438063785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.438063785
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.1238428834
Short name T1121
Test name
Test status
Simulation time 10087194002 ps
CPU time 15.26 seconds
Started Jun 05 05:47:25 PM PDT 24
Finished Jun 05 05:47:41 PM PDT 24
Peak memory 205784 kb
Host smart-316ff08f-c2f3-4cbb-88a0-f3cb4174fb5c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1238428834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.1238428834
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.99023538
Short name T1736
Test name
Test status
Simulation time 10078520861 ps
CPU time 15.84 seconds
Started Jun 05 05:47:25 PM PDT 24
Finished Jun 05 05:47:42 PM PDT 24
Peak memory 205652 kb
Host smart-c15b81c1-8212-4e74-bb70-6acffeb1f262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99023
538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.99023538
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.1052137565
Short name T458
Test name
Test status
Simulation time 13886460734 ps
CPU time 18.26 seconds
Started Jun 05 05:47:31 PM PDT 24
Finished Jun 05 05:47:49 PM PDT 24
Peak memory 205628 kb
Host smart-a08b8203-5349-472e-b647-075750005807
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1052137565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.1052137565
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.719754307
Short name T1732
Test name
Test status
Simulation time 23304661936 ps
CPU time 24.59 seconds
Started Jun 05 05:47:22 PM PDT 24
Finished Jun 05 05:47:47 PM PDT 24
Peak memory 205884 kb
Host smart-bdeec33a-2e64-44fb-8ac8-b628ca3abef8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=719754307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.719754307
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2464234040
Short name T961
Test name
Test status
Simulation time 10076473578 ps
CPU time 13.72 seconds
Started Jun 05 05:47:32 PM PDT 24
Finished Jun 05 05:47:46 PM PDT 24
Peak memory 205716 kb
Host smart-cbc8745e-bf31-4cce-a479-89e2ec23df1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24642
34040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2464234040
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.787767354
Short name T1346
Test name
Test status
Simulation time 10664914434 ps
CPU time 14.02 seconds
Started Jun 05 05:47:27 PM PDT 24
Finished Jun 05 05:47:41 PM PDT 24
Peak memory 205892 kb
Host smart-5b2121ad-2da2-4133-8bbe-05b709065306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78776
7354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.787767354
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.767363600
Short name T1588
Test name
Test status
Simulation time 10036187818 ps
CPU time 13.07 seconds
Started Jun 05 05:47:29 PM PDT 24
Finished Jun 05 05:47:43 PM PDT 24
Peak memory 205652 kb
Host smart-e2053f60-1be5-4d92-a2f6-85ce3eecdc3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76736
3600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.767363600
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.3161797721
Short name T1138
Test name
Test status
Simulation time 10061763425 ps
CPU time 13.02 seconds
Started Jun 05 05:47:25 PM PDT 24
Finished Jun 05 05:47:39 PM PDT 24
Peak memory 205652 kb
Host smart-cb54f1e6-ff05-4bbf-8ee6-292d41da028a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31617
97721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.3161797721
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.848888199
Short name T519
Test name
Test status
Simulation time 10326920996 ps
CPU time 14.61 seconds
Started Jun 05 05:47:30 PM PDT 24
Finished Jun 05 05:47:45 PM PDT 24
Peak memory 205784 kb
Host smart-bb31498d-a701-41af-94de-4a254c23927f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84888
8199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.848888199
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.4097773090
Short name T1726
Test name
Test status
Simulation time 10133803336 ps
CPU time 12.94 seconds
Started Jun 05 05:47:24 PM PDT 24
Finished Jun 05 05:47:38 PM PDT 24
Peak memory 205788 kb
Host smart-8838645f-e346-4d49-ae55-d5255c92ddd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40977
73090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.4097773090
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.3667627622
Short name T759
Test name
Test status
Simulation time 10066529808 ps
CPU time 13.83 seconds
Started Jun 05 05:47:24 PM PDT 24
Finished Jun 05 05:47:39 PM PDT 24
Peak memory 206008 kb
Host smart-1e836b65-24d1-4d87-9249-e500d2999232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36676
27622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.3667627622
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.1997623153
Short name T1478
Test name
Test status
Simulation time 10073297146 ps
CPU time 15.14 seconds
Started Jun 05 05:47:26 PM PDT 24
Finished Jun 05 05:47:42 PM PDT 24
Peak memory 205664 kb
Host smart-29998f7a-3677-42d1-917b-32f81eec3e54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19976
23153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.1997623153
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.710579463
Short name T1583
Test name
Test status
Simulation time 10131218800 ps
CPU time 16.09 seconds
Started Jun 05 05:47:26 PM PDT 24
Finished Jun 05 05:47:43 PM PDT 24
Peak memory 205684 kb
Host smart-15a6e72d-2960-4f33-9c92-e9ccfa15d875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71057
9463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.710579463
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.2242088307
Short name T199
Test name
Test status
Simulation time 13181736303 ps
CPU time 19.46 seconds
Started Jun 05 05:47:25 PM PDT 24
Finished Jun 05 05:47:45 PM PDT 24
Peak memory 205620 kb
Host smart-aaf7d845-7114-428e-876c-b6c4998deb5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22420
88307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.2242088307
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2054091142
Short name T1072
Test name
Test status
Simulation time 10104971367 ps
CPU time 12.95 seconds
Started Jun 05 05:47:24 PM PDT 24
Finished Jun 05 05:47:38 PM PDT 24
Peak memory 205644 kb
Host smart-ccfa7756-a88a-48c2-9974-a014e31cd9a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20540
91142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2054091142
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.4185197530
Short name T1416
Test name
Test status
Simulation time 15135424685 ps
CPU time 63.45 seconds
Started Jun 05 05:47:24 PM PDT 24
Finished Jun 05 05:48:29 PM PDT 24
Peak memory 205696 kb
Host smart-23e93545-525a-4f05-8e08-50ed20cd50fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41851
97530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.4185197530
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.4247073286
Short name T30
Test name
Test status
Simulation time 10080387633 ps
CPU time 12.92 seconds
Started Jun 05 05:47:33 PM PDT 24
Finished Jun 05 05:47:47 PM PDT 24
Peak memory 205784 kb
Host smart-c7de0c83-fa17-4ef0-86f7-555041e1ddd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42470
73286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.4247073286
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1946962168
Short name T1836
Test name
Test status
Simulation time 10096609703 ps
CPU time 14 seconds
Started Jun 05 05:47:24 PM PDT 24
Finished Jun 05 05:47:39 PM PDT 24
Peak memory 205684 kb
Host smart-b65fa17d-5ecd-4151-9e0b-2d7bccc6a5c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19469
62168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1946962168
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.1407342112
Short name T77
Test name
Test status
Simulation time 10114663937 ps
CPU time 14.51 seconds
Started Jun 05 05:47:33 PM PDT 24
Finished Jun 05 05:47:48 PM PDT 24
Peak memory 205824 kb
Host smart-079a786f-6b98-4fde-8604-baee366ced44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14073
42112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.1407342112
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.3707213131
Short name T1983
Test name
Test status
Simulation time 10056415120 ps
CPU time 14.17 seconds
Started Jun 05 05:47:28 PM PDT 24
Finished Jun 05 05:47:43 PM PDT 24
Peak memory 205728 kb
Host smart-2f984adb-5cb6-40fb-97cb-4b41878938d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37072
13131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.3707213131
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.81002562
Short name T1549
Test name
Test status
Simulation time 10121842635 ps
CPU time 12.52 seconds
Started Jun 05 05:47:25 PM PDT 24
Finished Jun 05 05:47:38 PM PDT 24
Peak memory 205652 kb
Host smart-2bb4cd93-af94-429e-a687-86d11d5b2bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81002
562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.81002562
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.2195136522
Short name T1928
Test name
Test status
Simulation time 10095292242 ps
CPU time 13.55 seconds
Started Jun 05 05:47:23 PM PDT 24
Finished Jun 05 05:47:37 PM PDT 24
Peak memory 205716 kb
Host smart-d1b261a6-b9e4-4f00-9a88-13f1dcad5781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21951
36522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.2195136522
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_eop_single_bit_handling.1165676716
Short name T907
Test name
Test status
Simulation time 10115083707 ps
CPU time 14.05 seconds
Started Jun 05 05:47:32 PM PDT 24
Finished Jun 05 05:47:47 PM PDT 24
Peak memory 205728 kb
Host smart-39efefd7-9183-483b-91eb-095c12584b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11656
76716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_eop_single_bit_handling.1165676716
Directory /workspace/27.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.3286392772
Short name T1332
Test name
Test status
Simulation time 10065540832 ps
CPU time 13.37 seconds
Started Jun 05 05:47:26 PM PDT 24
Finished Jun 05 05:47:40 PM PDT 24
Peak memory 205756 kb
Host smart-ac43e50d-cf6d-4057-b979-c3dd5fcb6f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32863
92772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.3286392772
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3335719903
Short name T1615
Test name
Test status
Simulation time 10082834775 ps
CPU time 13.42 seconds
Started Jun 05 05:47:25 PM PDT 24
Finished Jun 05 05:47:39 PM PDT 24
Peak memory 205760 kb
Host smart-e39aeeb5-6c03-4bc3-a6d5-c2541d3303b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33357
19903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3335719903
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.38474613
Short name T161
Test name
Test status
Simulation time 28741630766 ps
CPU time 57.01 seconds
Started Jun 05 05:47:27 PM PDT 24
Finished Jun 05 05:48:25 PM PDT 24
Peak memory 205608 kb
Host smart-28ed179d-7a2e-42ee-af89-910aa02fa496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38474
613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.38474613
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.1443818279
Short name T1636
Test name
Test status
Simulation time 10106852130 ps
CPU time 15.17 seconds
Started Jun 05 05:47:24 PM PDT 24
Finished Jun 05 05:47:39 PM PDT 24
Peak memory 205648 kb
Host smart-37287470-3810-4a55-a899-3532f6fb8939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14438
18279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.1443818279
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.107875154
Short name T335
Test name
Test status
Simulation time 10140272527 ps
CPU time 13.89 seconds
Started Jun 05 05:47:25 PM PDT 24
Finished Jun 05 05:47:40 PM PDT 24
Peak memory 205732 kb
Host smart-3f7ed058-203f-4916-8813-9e48e010ac84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10787
5154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.107875154
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.2542950961
Short name T913
Test name
Test status
Simulation time 10123098149 ps
CPU time 12.9 seconds
Started Jun 05 05:47:33 PM PDT 24
Finished Jun 05 05:47:46 PM PDT 24
Peak memory 205736 kb
Host smart-59d49cb7-45af-4934-a1f5-7f1a9163091d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25429
50961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.2542950961
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.1348393863
Short name T1932
Test name
Test status
Simulation time 10041608730 ps
CPU time 13.14 seconds
Started Jun 05 05:47:22 PM PDT 24
Finished Jun 05 05:47:36 PM PDT 24
Peak memory 205648 kb
Host smart-79d36198-17a6-4b76-be64-5241e2c50776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13483
93863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.1348393863
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.695283358
Short name T815
Test name
Test status
Simulation time 10110637250 ps
CPU time 15.47 seconds
Started Jun 05 05:47:32 PM PDT 24
Finished Jun 05 05:47:49 PM PDT 24
Peak memory 205692 kb
Host smart-d4984679-857d-417a-bf06-e82bee6f4daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69528
3358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.695283358
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.2496119989
Short name T530
Test name
Test status
Simulation time 10050330082 ps
CPU time 14.2 seconds
Started Jun 05 05:47:27 PM PDT 24
Finished Jun 05 05:47:41 PM PDT 24
Peak memory 205672 kb
Host smart-3a27608c-2613-47eb-b811-b59d5bb1afb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24961
19989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.2496119989
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.1707547023
Short name T1063
Test name
Test status
Simulation time 10086688333 ps
CPU time 14.14 seconds
Started Jun 05 05:47:30 PM PDT 24
Finished Jun 05 05:47:45 PM PDT 24
Peak memory 205808 kb
Host smart-dbe747e3-f8e4-478f-b92f-66f6a8345496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17075
47023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.1707547023
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.1425925722
Short name T721
Test name
Test status
Simulation time 10042757449 ps
CPU time 13.98 seconds
Started Jun 05 05:47:24 PM PDT 24
Finished Jun 05 05:47:39 PM PDT 24
Peak memory 205732 kb
Host smart-b4fc6d26-c2e3-491b-8d5d-a263ebc1c300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14259
25722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.1425925722
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.866960405
Short name T1107
Test name
Test status
Simulation time 10145393537 ps
CPU time 12.99 seconds
Started Jun 05 05:47:27 PM PDT 24
Finished Jun 05 05:47:40 PM PDT 24
Peak memory 205756 kb
Host smart-ef0f348f-e5fa-4861-ac2c-8cf9044bec45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86696
0405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.866960405
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.1668623602
Short name T757
Test name
Test status
Simulation time 25062184753 ps
CPU time 424.25 seconds
Started Jun 05 05:47:27 PM PDT 24
Finished Jun 05 05:54:32 PM PDT 24
Peak memory 205652 kb
Host smart-91a52310-57e8-4842-917b-49598858ec0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16686
23602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.1668623602
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.2163438815
Short name T1579
Test name
Test status
Simulation time 10204685162 ps
CPU time 14.08 seconds
Started Jun 05 05:47:29 PM PDT 24
Finished Jun 05 05:47:44 PM PDT 24
Peak memory 205932 kb
Host smart-d8aa6139-c5fc-4497-9b76-122208451dcb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2163438815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.2163438815
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.2998504178
Short name T1893
Test name
Test status
Simulation time 10080351908 ps
CPU time 13.69 seconds
Started Jun 05 05:47:31 PM PDT 24
Finished Jun 05 05:47:45 PM PDT 24
Peak memory 205748 kb
Host smart-17c5fd64-fc79-4022-926e-5fabf2c7fb9e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2998504178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.2998504178
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.2625117708
Short name T1217
Test name
Test status
Simulation time 10076567325 ps
CPU time 14.07 seconds
Started Jun 05 05:47:35 PM PDT 24
Finished Jun 05 05:47:50 PM PDT 24
Peak memory 205680 kb
Host smart-73c9ff39-2960-4dd1-8dfc-7cd9cfb4ac70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26251
17708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.2625117708
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.3585947783
Short name T892
Test name
Test status
Simulation time 13615047431 ps
CPU time 17.64 seconds
Started Jun 05 05:47:32 PM PDT 24
Finished Jun 05 05:47:50 PM PDT 24
Peak memory 205784 kb
Host smart-18e0123a-dbaf-4257-a63a-fa0fe97a4646
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3585947783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.3585947783
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.4175857223
Short name T1680
Test name
Test status
Simulation time 23301474974 ps
CPU time 27.18 seconds
Started Jun 05 05:47:29 PM PDT 24
Finished Jun 05 05:47:57 PM PDT 24
Peak memory 205668 kb
Host smart-8209b2b9-dc66-4198-a48d-8ccd96a76896
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4175857223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.4175857223
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3353629708
Short name T1648
Test name
Test status
Simulation time 10056340299 ps
CPU time 16.06 seconds
Started Jun 05 05:47:33 PM PDT 24
Finished Jun 05 05:47:50 PM PDT 24
Peak memory 205636 kb
Host smart-27b86160-4ccc-44b3-9b4a-f704e59ceabc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33536
29708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3353629708
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.149922741
Short name T900
Test name
Test status
Simulation time 10368509963 ps
CPU time 16.09 seconds
Started Jun 05 05:47:33 PM PDT 24
Finished Jun 05 05:47:49 PM PDT 24
Peak memory 205736 kb
Host smart-5d740450-9a24-48f8-9820-c446daffc0d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14992
2741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.149922741
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.2813772084
Short name T480
Test name
Test status
Simulation time 10045178979 ps
CPU time 14.36 seconds
Started Jun 05 05:47:40 PM PDT 24
Finished Jun 05 05:47:54 PM PDT 24
Peak memory 205728 kb
Host smart-1b76855b-4af7-4d5c-95be-cb52ebcce687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28137
72084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.2813772084
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.2308046600
Short name T1511
Test name
Test status
Simulation time 10048920691 ps
CPU time 12.73 seconds
Started Jun 05 05:47:31 PM PDT 24
Finished Jun 05 05:47:45 PM PDT 24
Peak memory 205668 kb
Host smart-031a7918-f76f-4af1-8aae-1ce05db2c83b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23080
46600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.2308046600
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.1130909471
Short name T621
Test name
Test status
Simulation time 10755164713 ps
CPU time 14.65 seconds
Started Jun 05 05:47:31 PM PDT 24
Finished Jun 05 05:47:46 PM PDT 24
Peak memory 205700 kb
Host smart-06af3bb2-19c7-43c8-b759-ff8a365db280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11309
09471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.1130909471
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2465860802
Short name T875
Test name
Test status
Simulation time 10204550017 ps
CPU time 16.06 seconds
Started Jun 05 05:47:33 PM PDT 24
Finished Jun 05 05:47:50 PM PDT 24
Peak memory 205740 kb
Host smart-4ae39900-4b83-40ea-a838-49683dd4d14f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24658
60802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2465860802
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.1389171639
Short name T728
Test name
Test status
Simulation time 10116521247 ps
CPU time 12.49 seconds
Started Jun 05 05:47:28 PM PDT 24
Finished Jun 05 05:47:41 PM PDT 24
Peak memory 206004 kb
Host smart-28623448-6fdf-4971-ba73-2a02c3fe3cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13891
71639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.1389171639
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.4153815781
Short name T993
Test name
Test status
Simulation time 10079470221 ps
CPU time 13.34 seconds
Started Jun 05 05:47:30 PM PDT 24
Finished Jun 05 05:47:44 PM PDT 24
Peak memory 205728 kb
Host smart-2a610b1f-e1ab-4273-a07a-02b155b55180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41538
15781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.4153815781
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.442878904
Short name T1399
Test name
Test status
Simulation time 10073274017 ps
CPU time 13.25 seconds
Started Jun 05 05:47:39 PM PDT 24
Finished Jun 05 05:47:53 PM PDT 24
Peak memory 205776 kb
Host smart-4da3e36a-f3fb-4a96-9fa1-5084065122b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44287
8904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.442878904
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.2555974026
Short name T936
Test name
Test status
Simulation time 10148435663 ps
CPU time 13.73 seconds
Started Jun 05 05:47:34 PM PDT 24
Finished Jun 05 05:47:48 PM PDT 24
Peak memory 205640 kb
Host smart-65c5f25f-d103-4915-b5f6-a3f2ea6af5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25559
74026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.2555974026
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.4242448091
Short name T292
Test name
Test status
Simulation time 13216806576 ps
CPU time 18.73 seconds
Started Jun 05 05:47:32 PM PDT 24
Finished Jun 05 05:47:52 PM PDT 24
Peak memory 205664 kb
Host smart-af2afd1e-353c-4bcd-8ca5-b81c8873ead1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42424
48091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.4242448091
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2046407825
Short name T1646
Test name
Test status
Simulation time 10083152494 ps
CPU time 14.06 seconds
Started Jun 05 05:47:31 PM PDT 24
Finished Jun 05 05:47:46 PM PDT 24
Peak memory 205676 kb
Host smart-066efbe2-8b09-4fc8-abb6-41ea7152a683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20464
07825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2046407825
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.2782171065
Short name T320
Test name
Test status
Simulation time 16966776416 ps
CPU time 216.98 seconds
Started Jun 05 05:47:33 PM PDT 24
Finished Jun 05 05:51:11 PM PDT 24
Peak memory 205588 kb
Host smart-c9ccb01e-2566-49a6-8399-aa1a07ed366c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27821
71065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.2782171065
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.857468236
Short name T531
Test name
Test status
Simulation time 10042860949 ps
CPU time 13.13 seconds
Started Jun 05 05:47:38 PM PDT 24
Finished Jun 05 05:47:52 PM PDT 24
Peak memory 205684 kb
Host smart-cc789b31-dbc5-4023-b1ed-fd37b75c929c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85746
8236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.857468236
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.597993842
Short name T115
Test name
Test status
Simulation time 10103880599 ps
CPU time 15.28 seconds
Started Jun 05 05:47:35 PM PDT 24
Finished Jun 05 05:47:51 PM PDT 24
Peak memory 205732 kb
Host smart-86823e38-e20f-4f68-860b-8552c15e9594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59799
3842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.597993842
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.3868579205
Short name T1028
Test name
Test status
Simulation time 10057171249 ps
CPU time 14.76 seconds
Started Jun 05 05:47:31 PM PDT 24
Finished Jun 05 05:47:46 PM PDT 24
Peak memory 205756 kb
Host smart-f45407ad-6a72-45e8-b1ef-fa68e03938ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38685
79205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.3868579205
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.416111585
Short name T995
Test name
Test status
Simulation time 10046537590 ps
CPU time 14.61 seconds
Started Jun 05 05:47:32 PM PDT 24
Finished Jun 05 05:47:47 PM PDT 24
Peak memory 205620 kb
Host smart-61e30013-0553-4bc2-9acd-7da3bd337058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41611
1585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.416111585
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.3770653434
Short name T843
Test name
Test status
Simulation time 10068036935 ps
CPU time 13.33 seconds
Started Jun 05 05:47:33 PM PDT 24
Finished Jun 05 05:47:47 PM PDT 24
Peak memory 205696 kb
Host smart-ee8a7145-0e67-4f17-abdf-90961c7b949c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37706
53434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.3770653434
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.885034803
Short name T1019
Test name
Test status
Simulation time 10047998632 ps
CPU time 13.56 seconds
Started Jun 05 05:47:31 PM PDT 24
Finished Jun 05 05:47:45 PM PDT 24
Peak memory 205684 kb
Host smart-83aecafc-4523-401d-a740-74b89de7ccb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88503
4803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.885034803
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_eop_single_bit_handling.2640651780
Short name T583
Test name
Test status
Simulation time 10049081922 ps
CPU time 14.07 seconds
Started Jun 05 05:47:33 PM PDT 24
Finished Jun 05 05:47:48 PM PDT 24
Peak memory 205660 kb
Host smart-a4a64595-1fbb-43a4-a303-36172157b9a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26406
51780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_eop_single_bit_handling.2640651780
Directory /workspace/28.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3259329970
Short name T1228
Test name
Test status
Simulation time 10042612048 ps
CPU time 13.27 seconds
Started Jun 05 05:47:29 PM PDT 24
Finished Jun 05 05:47:43 PM PDT 24
Peak memory 205740 kb
Host smart-27aa3e2f-111d-4671-b9b8-b705b08abd65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32593
29970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3259329970
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.487981114
Short name T42
Test name
Test status
Simulation time 10043870567 ps
CPU time 13.58 seconds
Started Jun 05 05:47:35 PM PDT 24
Finished Jun 05 05:47:49 PM PDT 24
Peak memory 205764 kb
Host smart-11254f84-53c9-4835-8cf3-7c034ab1bb7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48798
1114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.487981114
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.3657775143
Short name T1375
Test name
Test status
Simulation time 31608371154 ps
CPU time 63.38 seconds
Started Jun 05 05:47:32 PM PDT 24
Finished Jun 05 05:48:36 PM PDT 24
Peak memory 205572 kb
Host smart-9654f4fd-8efb-42d4-a743-71b452647d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36577
75143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.3657775143
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2317962503
Short name T678
Test name
Test status
Simulation time 10088005259 ps
CPU time 15.2 seconds
Started Jun 05 05:47:32 PM PDT 24
Finished Jun 05 05:47:48 PM PDT 24
Peak memory 205640 kb
Host smart-7c378445-300b-4c06-aedb-a9e45a692572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23179
62503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2317962503
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.3233150577
Short name T1182
Test name
Test status
Simulation time 10099987341 ps
CPU time 13.58 seconds
Started Jun 05 05:47:31 PM PDT 24
Finished Jun 05 05:47:45 PM PDT 24
Peak memory 205624 kb
Host smart-15b0632f-187b-4b04-8a34-3fc88af99ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32331
50577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.3233150577
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.2852487545
Short name T1495
Test name
Test status
Simulation time 10062466707 ps
CPU time 13.52 seconds
Started Jun 05 05:47:35 PM PDT 24
Finished Jun 05 05:47:49 PM PDT 24
Peak memory 205488 kb
Host smart-6a0d00f8-ec28-42d5-87b5-c9f313d1a550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28524
87545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.2852487545
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.801977208
Short name T794
Test name
Test status
Simulation time 10035693514 ps
CPU time 14.66 seconds
Started Jun 05 05:47:32 PM PDT 24
Finished Jun 05 05:47:47 PM PDT 24
Peak memory 205796 kb
Host smart-8db7b805-6974-445d-b055-49477cfd2da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80197
7208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.801977208
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.1321261565
Short name T1057
Test name
Test status
Simulation time 10059968011 ps
CPU time 15.11 seconds
Started Jun 05 05:47:36 PM PDT 24
Finished Jun 05 05:47:52 PM PDT 24
Peak memory 205684 kb
Host smart-4c4a6dc2-4fb5-4ef7-a305-5472b76a66bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13212
61565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.1321261565
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.666848145
Short name T1209
Test name
Test status
Simulation time 10095685523 ps
CPU time 13.57 seconds
Started Jun 05 05:47:32 PM PDT 24
Finished Jun 05 05:47:47 PM PDT 24
Peak memory 205740 kb
Host smart-e77debdb-5370-4663-bd5a-59d17ff08c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66684
8145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.666848145
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.1481244612
Short name T1491
Test name
Test status
Simulation time 10066168371 ps
CPU time 12.78 seconds
Started Jun 05 05:47:31 PM PDT 24
Finished Jun 05 05:47:45 PM PDT 24
Peak memory 205812 kb
Host smart-fcf06d4c-2f55-4245-80c8-9a16749ad27f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14812
44612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.1481244612
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.2716866831
Short name T545
Test name
Test status
Simulation time 10107369908 ps
CPU time 13.54 seconds
Started Jun 05 05:47:33 PM PDT 24
Finished Jun 05 05:47:47 PM PDT 24
Peak memory 205768 kb
Host smart-d8983dd1-dca4-4b43-bb89-29d1524c683c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27168
66831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2716866831
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.1559843500
Short name T709
Test name
Test status
Simulation time 20494010355 ps
CPU time 108.21 seconds
Started Jun 05 05:47:35 PM PDT 24
Finished Jun 05 05:49:24 PM PDT 24
Peak memory 205684 kb
Host smart-75b9e2ab-1760-4bef-89cd-ff873a124469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15598
43500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.1559843500
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.2358568734
Short name T974
Test name
Test status
Simulation time 10175253110 ps
CPU time 14.19 seconds
Started Jun 05 05:47:40 PM PDT 24
Finished Jun 05 05:47:54 PM PDT 24
Peak memory 205776 kb
Host smart-91b86c07-ab84-4714-b4f9-15601558af6a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2358568734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.2358568734
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.1029666172
Short name T592
Test name
Test status
Simulation time 10056973199 ps
CPU time 15.31 seconds
Started Jun 05 05:47:46 PM PDT 24
Finished Jun 05 05:48:02 PM PDT 24
Peak memory 205820 kb
Host smart-27e88417-65b2-4400-93a0-28276a172b4d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1029666172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.1029666172
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.27330849
Short name T420
Test name
Test status
Simulation time 10077870470 ps
CPU time 13.27 seconds
Started Jun 05 05:47:42 PM PDT 24
Finished Jun 05 05:47:56 PM PDT 24
Peak memory 205788 kb
Host smart-e0015568-7a54-41ae-b07f-0564f6e95772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27330
849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.27330849
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1096879103
Short name T202
Test name
Test status
Simulation time 13491816627 ps
CPU time 21.04 seconds
Started Jun 05 05:47:35 PM PDT 24
Finished Jun 05 05:47:57 PM PDT 24
Peak memory 205472 kb
Host smart-575e7ac7-f4b4-4423-acf6-912ee0b8c104
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1096879103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.1096879103
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.1689032606
Short name T1848
Test name
Test status
Simulation time 23300046185 ps
CPU time 27.16 seconds
Started Jun 05 05:47:34 PM PDT 24
Finished Jun 05 05:48:02 PM PDT 24
Peak memory 205724 kb
Host smart-9e6dafa9-6ed9-4fa1-ad99-f228f7dc5cd1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1689032606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.1689032606
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1084476083
Short name T1725
Test name
Test status
Simulation time 10064053589 ps
CPU time 12.59 seconds
Started Jun 05 05:47:32 PM PDT 24
Finished Jun 05 05:47:45 PM PDT 24
Peak memory 205636 kb
Host smart-07509a72-9575-4fcb-a03c-22a36fa4bf37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10844
76083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1084476083
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.826712509
Short name T1787
Test name
Test status
Simulation time 11415093207 ps
CPU time 19.51 seconds
Started Jun 05 05:47:40 PM PDT 24
Finished Jun 05 05:48:00 PM PDT 24
Peak memory 205696 kb
Host smart-7e845b80-3b84-4853-85f7-94deaff809a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82671
2509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.826712509
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.1512458813
Short name T366
Test name
Test status
Simulation time 10098964754 ps
CPU time 13.89 seconds
Started Jun 05 05:47:40 PM PDT 24
Finished Jun 05 05:47:55 PM PDT 24
Peak memory 205664 kb
Host smart-cbeea246-93b3-4843-b3e8-2c6ed29358f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15124
58813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.1512458813
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.3604512025
Short name T997
Test name
Test status
Simulation time 10056514678 ps
CPU time 13.21 seconds
Started Jun 05 05:47:40 PM PDT 24
Finished Jun 05 05:47:54 PM PDT 24
Peak memory 205668 kb
Host smart-b6868dfa-e308-4141-a2ed-896427b3b01b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36045
12025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3604512025
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.688007491
Short name T316
Test name
Test status
Simulation time 10811950676 ps
CPU time 16.3 seconds
Started Jun 05 05:47:41 PM PDT 24
Finished Jun 05 05:47:58 PM PDT 24
Peak memory 205760 kb
Host smart-ca3403ae-4f19-4073-81b3-a50e6d9ee7c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68800
7491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.688007491
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.3315106469
Short name T655
Test name
Test status
Simulation time 10196725295 ps
CPU time 13.76 seconds
Started Jun 05 05:47:43 PM PDT 24
Finished Jun 05 05:47:57 PM PDT 24
Peak memory 205696 kb
Host smart-ab064a6b-92a7-42b2-b00b-7fb5b2a60b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33151
06469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3315106469
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.661765993
Short name T1463
Test name
Test status
Simulation time 10093371119 ps
CPU time 12.77 seconds
Started Jun 05 05:47:39 PM PDT 24
Finished Jun 05 05:47:52 PM PDT 24
Peak memory 205772 kb
Host smart-bc0be333-58ac-45e7-927d-219e01ba6e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66176
5993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.661765993
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.40338670
Short name T1184
Test name
Test status
Simulation time 10044912507 ps
CPU time 16.25 seconds
Started Jun 05 05:47:39 PM PDT 24
Finished Jun 05 05:47:56 PM PDT 24
Peak memory 205636 kb
Host smart-fa597e5c-bcc3-4f54-88ea-2c103360d95a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40338
670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.40338670
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.31003927
Short name T1866
Test name
Test status
Simulation time 10100264658 ps
CPU time 12.75 seconds
Started Jun 05 05:47:39 PM PDT 24
Finished Jun 05 05:47:53 PM PDT 24
Peak memory 205776 kb
Host smart-ea201ad2-323e-4d77-a356-b0c1b717891b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31003
927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.31003927
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.1604920529
Short name T414
Test name
Test status
Simulation time 10165015640 ps
CPU time 15.44 seconds
Started Jun 05 05:47:39 PM PDT 24
Finished Jun 05 05:47:55 PM PDT 24
Peak memory 205664 kb
Host smart-54f2630b-38c1-4526-bb27-dbebe652f518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16049
20529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.1604920529
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.3218756185
Short name T769
Test name
Test status
Simulation time 13158642587 ps
CPU time 16.68 seconds
Started Jun 05 05:47:37 PM PDT 24
Finished Jun 05 05:47:54 PM PDT 24
Peak memory 205980 kb
Host smart-afa0cdf9-c3e6-40b0-a92a-dfdc0b4f7d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32187
56185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.3218756185
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2837642884
Short name T1216
Test name
Test status
Simulation time 10145619531 ps
CPU time 14.92 seconds
Started Jun 05 05:47:41 PM PDT 24
Finished Jun 05 05:47:56 PM PDT 24
Peak memory 205928 kb
Host smart-decbbfef-f5c4-436e-ae5d-29f8a8f71efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28376
42884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2837642884
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.3597443898
Short name T1197
Test name
Test status
Simulation time 15721480665 ps
CPU time 66.63 seconds
Started Jun 05 05:47:41 PM PDT 24
Finished Jun 05 05:48:48 PM PDT 24
Peak memory 205736 kb
Host smart-d1546f52-f804-4e91-b7ba-a10f76880077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35974
43898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.3597443898
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.993422213
Short name T1728
Test name
Test status
Simulation time 10050845186 ps
CPU time 14.19 seconds
Started Jun 05 05:47:38 PM PDT 24
Finished Jun 05 05:47:53 PM PDT 24
Peak memory 205668 kb
Host smart-25dfbbc0-52f6-41ee-beb3-10741feda65d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99342
2213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.993422213
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.152175245
Short name T1647
Test name
Test status
Simulation time 10089999722 ps
CPU time 13.68 seconds
Started Jun 05 05:47:42 PM PDT 24
Finished Jun 05 05:47:56 PM PDT 24
Peak memory 205760 kb
Host smart-c997275d-087b-40af-ab9b-62d060d7099e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15217
5245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.152175245
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.4215426610
Short name T339
Test name
Test status
Simulation time 10072366668 ps
CPU time 15.89 seconds
Started Jun 05 05:47:40 PM PDT 24
Finished Jun 05 05:47:56 PM PDT 24
Peak memory 205704 kb
Host smart-305b1a49-f71c-4c51-8d21-bb530ae2e489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42154
26610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.4215426610
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.256845717
Short name T512
Test name
Test status
Simulation time 10083485323 ps
CPU time 12.59 seconds
Started Jun 05 05:47:40 PM PDT 24
Finished Jun 05 05:47:54 PM PDT 24
Peak memory 205712 kb
Host smart-227e5c47-0947-4f40-a343-90ae64c25c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25684
5717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.256845717
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.306013336
Short name T1891
Test name
Test status
Simulation time 10071563406 ps
CPU time 13.47 seconds
Started Jun 05 05:47:39 PM PDT 24
Finished Jun 05 05:47:53 PM PDT 24
Peak memory 205760 kb
Host smart-86e18ccd-cb28-43d1-a817-4d5217bfac17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30601
3336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.306013336
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_eop_single_bit_handling.991113579
Short name T223
Test name
Test status
Simulation time 10047169252 ps
CPU time 13.15 seconds
Started Jun 05 05:47:41 PM PDT 24
Finished Jun 05 05:47:55 PM PDT 24
Peak memory 205708 kb
Host smart-af344df3-8bb4-4ab1-ba94-22b52a4e3831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99111
3579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_eop_single_bit_handling.991113579
Directory /workspace/29.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.113229373
Short name T645
Test name
Test status
Simulation time 10099502685 ps
CPU time 13.43 seconds
Started Jun 05 05:47:42 PM PDT 24
Finished Jun 05 05:47:56 PM PDT 24
Peak memory 205716 kb
Host smart-ed6eff15-6916-4e6d-abf2-fe871e668358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11322
9373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.113229373
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2273667876
Short name T1267
Test name
Test status
Simulation time 10041923599 ps
CPU time 13.98 seconds
Started Jun 05 05:47:41 PM PDT 24
Finished Jun 05 05:47:56 PM PDT 24
Peak memory 205676 kb
Host smart-48d5d16d-d4d5-4163-817a-9338c18af553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22736
67876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2273667876
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.1108100271
Short name T232
Test name
Test status
Simulation time 28506050451 ps
CPU time 63.34 seconds
Started Jun 05 05:47:47 PM PDT 24
Finished Jun 05 05:48:51 PM PDT 24
Peak memory 205636 kb
Host smart-171901a9-3a5a-44a5-a70a-db3fff56189b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11081
00271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.1108100271
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.4093153069
Short name T400
Test name
Test status
Simulation time 10066365162 ps
CPU time 12.35 seconds
Started Jun 05 05:47:43 PM PDT 24
Finished Jun 05 05:47:56 PM PDT 24
Peak memory 205720 kb
Host smart-ad992a32-4f06-454a-9981-6234436ccbf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40931
53069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.4093153069
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.2283495458
Short name T896
Test name
Test status
Simulation time 10072719354 ps
CPU time 14.01 seconds
Started Jun 05 05:47:46 PM PDT 24
Finished Jun 05 05:48:01 PM PDT 24
Peak memory 205684 kb
Host smart-4be16f21-9a81-40ee-8c4d-99a79145979a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22834
95458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.2283495458
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.931077853
Short name T1989
Test name
Test status
Simulation time 10054739374 ps
CPU time 15.21 seconds
Started Jun 05 05:47:43 PM PDT 24
Finished Jun 05 05:47:59 PM PDT 24
Peak memory 205672 kb
Host smart-0730515b-a5e2-4df9-94ef-6b7f5761a5c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93107
7853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.931077853
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.191120730
Short name T1362
Test name
Test status
Simulation time 10038844831 ps
CPU time 13.55 seconds
Started Jun 05 05:47:39 PM PDT 24
Finished Jun 05 05:47:53 PM PDT 24
Peak memory 205732 kb
Host smart-24662b16-e30f-4594-b6a9-db6febec6ce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19112
0730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.191120730
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.737038881
Short name T882
Test name
Test status
Simulation time 10109091823 ps
CPU time 15.78 seconds
Started Jun 05 05:47:41 PM PDT 24
Finished Jun 05 05:47:57 PM PDT 24
Peak memory 205720 kb
Host smart-8448ace3-2ac9-473a-ba37-7203163889b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73703
8881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.737038881
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3419163478
Short name T1888
Test name
Test status
Simulation time 10066518921 ps
CPU time 13.74 seconds
Started Jun 05 05:47:42 PM PDT 24
Finished Jun 05 05:47:56 PM PDT 24
Peak memory 205688 kb
Host smart-14096219-3fe7-4790-a342-492e4c6ab2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34191
63478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3419163478
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.2125387959
Short name T1097
Test name
Test status
Simulation time 10187860689 ps
CPU time 16.52 seconds
Started Jun 05 05:47:33 PM PDT 24
Finished Jun 05 05:47:51 PM PDT 24
Peak memory 205728 kb
Host smart-b1d46439-a2b9-4036-ba5c-c211975c3fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21253
87959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2125387959
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.2052413848
Short name T491
Test name
Test status
Simulation time 10091440499 ps
CPU time 12.89 seconds
Started Jun 05 05:47:41 PM PDT 24
Finished Jun 05 05:47:54 PM PDT 24
Peak memory 205812 kb
Host smart-53b907a0-7ba4-462b-bfff-166c32e16e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20524
13848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.2052413848
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.1234907575
Short name T1480
Test name
Test status
Simulation time 10065390625 ps
CPU time 13.57 seconds
Started Jun 05 05:47:40 PM PDT 24
Finished Jun 05 05:47:54 PM PDT 24
Peak memory 205652 kb
Host smart-b3271d25-d468-432c-b4d4-bb0d92279c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12349
07575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.1234907575
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.2211938685
Short name T981
Test name
Test status
Simulation time 15544169408 ps
CPU time 55.28 seconds
Started Jun 05 05:47:42 PM PDT 24
Finished Jun 05 05:48:38 PM PDT 24
Peak memory 205664 kb
Host smart-22dd0924-e7e5-49bb-be8b-9c808aba038e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22119
38685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.2211938685
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.144489462
Short name T1779
Test name
Test status
Simulation time 10161794745 ps
CPU time 12.51 seconds
Started Jun 05 05:44:29 PM PDT 24
Finished Jun 05 05:44:42 PM PDT 24
Peak memory 205728 kb
Host smart-258470f3-7c9f-4352-9af5-be72ed41dd78
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=144489462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.144489462
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.3444855209
Short name T1345
Test name
Test status
Simulation time 10063127489 ps
CPU time 14.06 seconds
Started Jun 05 05:44:29 PM PDT 24
Finished Jun 05 05:44:44 PM PDT 24
Peak memory 205652 kb
Host smart-5ccbbcce-bd4e-4ed3-acd0-b0e6bca10272
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3444855209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.3444855209
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.4073987613
Short name T1638
Test name
Test status
Simulation time 10118205152 ps
CPU time 12.88 seconds
Started Jun 05 05:44:31 PM PDT 24
Finished Jun 05 05:44:44 PM PDT 24
Peak memory 205652 kb
Host smart-515ec316-25fc-4b06-8256-a282b6c71e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40739
87613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.4073987613
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.2560168340
Short name T1723
Test name
Test status
Simulation time 13815370851 ps
CPU time 18.97 seconds
Started Jun 05 05:44:23 PM PDT 24
Finished Jun 05 05:44:42 PM PDT 24
Peak memory 205732 kb
Host smart-ee80eb5b-0f57-43ee-8fc1-77d77f2f1cc9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2560168340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.2560168340
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.541908200
Short name T1704
Test name
Test status
Simulation time 23197624596 ps
CPU time 24.82 seconds
Started Jun 05 05:44:24 PM PDT 24
Finished Jun 05 05:44:49 PM PDT 24
Peak memory 205724 kb
Host smart-0ad0018a-0a8f-48b5-9c40-a7ff16af5f0f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=541908200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.541908200
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.4036482057
Short name T568
Test name
Test status
Simulation time 10053732682 ps
CPU time 15.01 seconds
Started Jun 05 05:44:22 PM PDT 24
Finished Jun 05 05:44:38 PM PDT 24
Peak memory 205732 kb
Host smart-a1cfb1a4-43f1-4846-9169-30b6a80e0c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40364
82057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.4036482057
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.621024391
Short name T587
Test name
Test status
Simulation time 10041666992 ps
CPU time 13.33 seconds
Started Jun 05 05:44:24 PM PDT 24
Finished Jun 05 05:44:38 PM PDT 24
Peak memory 205880 kb
Host smart-298400a6-ff8b-4d52-91c2-ae252f1402c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62102
4391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.621024391
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.4018828252
Short name T1986
Test name
Test status
Simulation time 10763809289 ps
CPU time 14.88 seconds
Started Jun 05 05:44:26 PM PDT 24
Finished Jun 05 05:44:41 PM PDT 24
Peak memory 205692 kb
Host smart-7fd98355-da0e-46fb-86ee-b96eab967634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40188
28252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.4018828252
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.965622414
Short name T318
Test name
Test status
Simulation time 10053515947 ps
CPU time 15.77 seconds
Started Jun 05 05:44:27 PM PDT 24
Finished Jun 05 05:44:43 PM PDT 24
Peak memory 205728 kb
Host smart-c2c2bd14-9770-4827-bc6b-ba86c0e3326e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96562
2414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.965622414
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.1304057020
Short name T1805
Test name
Test status
Simulation time 10058539030 ps
CPU time 12.85 seconds
Started Jun 05 05:44:23 PM PDT 24
Finished Jun 05 05:44:36 PM PDT 24
Peak memory 205664 kb
Host smart-1d6537f0-7e64-4079-abd0-2bafede3dc21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13040
57020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1304057020
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.150282784
Short name T1630
Test name
Test status
Simulation time 10723631244 ps
CPU time 13.5 seconds
Started Jun 05 05:44:25 PM PDT 24
Finished Jun 05 05:44:39 PM PDT 24
Peak memory 205668 kb
Host smart-1661e844-b537-4b26-98ea-af9063a07fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15028
2784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.150282784
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3142930732
Short name T1349
Test name
Test status
Simulation time 10207831690 ps
CPU time 14.57 seconds
Started Jun 05 05:44:27 PM PDT 24
Finished Jun 05 05:44:42 PM PDT 24
Peak memory 205756 kb
Host smart-5792881e-c58b-4309-9a7a-58c0382c2a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31429
30732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3142930732
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.285223173
Short name T811
Test name
Test status
Simulation time 10130500052 ps
CPU time 14.03 seconds
Started Jun 05 05:44:29 PM PDT 24
Finished Jun 05 05:44:44 PM PDT 24
Peak memory 205668 kb
Host smart-f114db3f-e1dd-47f0-8ede-4283d23cdebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28522
3173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.285223173
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.1748871815
Short name T666
Test name
Test status
Simulation time 10059715177 ps
CPU time 13.24 seconds
Started Jun 05 05:44:30 PM PDT 24
Finished Jun 05 05:44:44 PM PDT 24
Peak memory 205724 kb
Host smart-692b5e33-bea3-4753-860b-ab4a472e86d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17488
71815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.1748871815
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1789173656
Short name T381
Test name
Test status
Simulation time 10091277316 ps
CPU time 13.3 seconds
Started Jun 05 05:44:27 PM PDT 24
Finished Jun 05 05:44:40 PM PDT 24
Peak memory 205644 kb
Host smart-54cca974-259f-4160-b3df-c4d2c72498a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17891
73656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1789173656
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.3941833879
Short name T1533
Test name
Test status
Simulation time 10088644692 ps
CPU time 12.72 seconds
Started Jun 05 05:44:30 PM PDT 24
Finished Jun 05 05:44:43 PM PDT 24
Peak memory 205716 kb
Host smart-e74c527f-d714-402d-9d5e-fa551f391a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39418
33879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.3941833879
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.2379762204
Short name T1514
Test name
Test status
Simulation time 13249507542 ps
CPU time 15.89 seconds
Started Jun 05 05:44:24 PM PDT 24
Finished Jun 05 05:44:41 PM PDT 24
Peak memory 205932 kb
Host smart-5e0352d9-6c6d-4411-8259-d99172eaaea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23797
62204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2379762204
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.2647035347
Short name T1186
Test name
Test status
Simulation time 10090704683 ps
CPU time 13.83 seconds
Started Jun 05 05:44:23 PM PDT 24
Finished Jun 05 05:44:37 PM PDT 24
Peak memory 205764 kb
Host smart-0e56c535-64b9-47ee-a535-e22603015295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26470
35347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.2647035347
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.3826175671
Short name T1634
Test name
Test status
Simulation time 15914353242 ps
CPU time 169.13 seconds
Started Jun 05 05:44:23 PM PDT 24
Finished Jun 05 05:47:13 PM PDT 24
Peak memory 205708 kb
Host smart-794d2973-b712-4a61-b7d6-f68941fe2b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38261
75671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.3826175671
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.731443691
Short name T1686
Test name
Test status
Simulation time 10041558720 ps
CPU time 16.68 seconds
Started Jun 05 05:44:23 PM PDT 24
Finished Jun 05 05:44:41 PM PDT 24
Peak memory 205716 kb
Host smart-129ed4fc-383b-47fe-8b60-238d3db16096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73144
3691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.731443691
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.784497311
Short name T805
Test name
Test status
Simulation time 10130024049 ps
CPU time 12.75 seconds
Started Jun 05 05:44:30 PM PDT 24
Finished Jun 05 05:44:44 PM PDT 24
Peak memory 205400 kb
Host smart-e1549f0d-c848-42be-ac8c-901eaad3afb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78449
7311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.784497311
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.3396890837
Short name T1566
Test name
Test status
Simulation time 10090702313 ps
CPU time 12.71 seconds
Started Jun 05 05:44:32 PM PDT 24
Finished Jun 05 05:44:45 PM PDT 24
Peak memory 205660 kb
Host smart-0d982cd2-da8d-402f-a4a9-ec9ad481261e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33968
90837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.3396890837
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.4239509157
Short name T692
Test name
Test status
Simulation time 10096177894 ps
CPU time 13.79 seconds
Started Jun 05 05:44:29 PM PDT 24
Finished Jun 05 05:44:43 PM PDT 24
Peak memory 205960 kb
Host smart-2b501e05-c236-4792-a9f8-db21e93fd6f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42395
09157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.4239509157
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3990918534
Short name T959
Test name
Test status
Simulation time 10110783204 ps
CPU time 16 seconds
Started Jun 05 05:44:33 PM PDT 24
Finished Jun 05 05:44:49 PM PDT 24
Peak memory 205752 kb
Host smart-34ac1684-6c2b-4497-85c7-cd0922ce7271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39909
18534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3990918534
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.981601197
Short name T139
Test name
Test status
Simulation time 10045757694 ps
CPU time 14.37 seconds
Started Jun 05 05:44:32 PM PDT 24
Finished Jun 05 05:44:47 PM PDT 24
Peak memory 205732 kb
Host smart-6c62a688-df58-4d78-ad92-39df7f63040c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98160
1197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.981601197
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_eop_single_bit_handling.2647918305
Short name T379
Test name
Test status
Simulation time 10078092363 ps
CPU time 15.56 seconds
Started Jun 05 05:44:31 PM PDT 24
Finished Jun 05 05:44:47 PM PDT 24
Peak memory 205656 kb
Host smart-d189a7d0-dee0-437a-a186-db436490a700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26479
18305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_eop_single_bit_handling.2647918305
Directory /workspace/3.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2309823547
Short name T1284
Test name
Test status
Simulation time 10065318634 ps
CPU time 13.26 seconds
Started Jun 05 05:44:30 PM PDT 24
Finished Jun 05 05:44:45 PM PDT 24
Peak memory 205664 kb
Host smart-eca98c71-310f-4d0a-a328-acff5d57b4d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23098
23547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2309823547
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1888798526
Short name T1931
Test name
Test status
Simulation time 10049868776 ps
CPU time 14.3 seconds
Started Jun 05 05:44:34 PM PDT 24
Finished Jun 05 05:44:48 PM PDT 24
Peak memory 205748 kb
Host smart-205ed6d2-4ef5-4b14-a56c-3ca56f8dbe93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18887
98526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1888798526
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3935557033
Short name T939
Test name
Test status
Simulation time 21545817193 ps
CPU time 37.42 seconds
Started Jun 05 05:44:29 PM PDT 24
Finished Jun 05 05:45:07 PM PDT 24
Peak memory 205708 kb
Host smart-d5234f6f-4673-4494-83b7-4404f9b98a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39355
57033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3935557033
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.3847054911
Short name T544
Test name
Test status
Simulation time 10074694020 ps
CPU time 13.77 seconds
Started Jun 05 05:44:30 PM PDT 24
Finished Jun 05 05:44:45 PM PDT 24
Peak memory 205732 kb
Host smart-bcb0a2ef-46f3-4f59-bef7-5a69e0f5c3f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38470
54911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.3847054911
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.3242262199
Short name T1691
Test name
Test status
Simulation time 10074517711 ps
CPU time 13.02 seconds
Started Jun 05 05:44:31 PM PDT 24
Finished Jun 05 05:44:45 PM PDT 24
Peak memory 205744 kb
Host smart-2c6a91fb-4358-467d-9032-be8faad62950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32422
62199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.3242262199
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.3121195769
Short name T1960
Test name
Test status
Simulation time 22880887035 ps
CPU time 281.26 seconds
Started Jun 05 05:44:29 PM PDT 24
Finished Jun 05 05:49:11 PM PDT 24
Peak memory 205780 kb
Host smart-bcb76073-f3c3-457e-86dc-e7ee4b1774b0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3121195769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.3121195769
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.3974955042
Short name T152
Test name
Test status
Simulation time 20135605324 ps
CPU time 199 seconds
Started Jun 05 05:44:31 PM PDT 24
Finished Jun 05 05:47:50 PM PDT 24
Peak memory 205752 kb
Host smart-327115e4-2f8f-458d-9846-87adb9cf8bb9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3974955042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.3974955042
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.3037352597
Short name T445
Test name
Test status
Simulation time 21725801584 ps
CPU time 77.33 seconds
Started Jun 05 05:44:30 PM PDT 24
Finished Jun 05 05:45:48 PM PDT 24
Peak memory 205760 kb
Host smart-dc9311e3-16cb-461d-96d6-ae086782a0aa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3037352597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.3037352597
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.3202229469
Short name T676
Test name
Test status
Simulation time 10072994344 ps
CPU time 14.5 seconds
Started Jun 05 05:44:32 PM PDT 24
Finished Jun 05 05:44:47 PM PDT 24
Peak memory 205692 kb
Host smart-6e80d0be-2a87-4264-bb61-df9950150cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32022
29469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.3202229469
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.3930142057
Short name T489
Test name
Test status
Simulation time 10065007044 ps
CPU time 12.29 seconds
Started Jun 05 05:44:28 PM PDT 24
Finished Jun 05 05:44:41 PM PDT 24
Peak memory 205716 kb
Host smart-e770d804-b454-4196-a4ba-88589f087ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39301
42057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.3930142057
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.3283771790
Short name T183
Test name
Test status
Simulation time 558178320 ps
CPU time 1.35 seconds
Started Jun 05 05:44:34 PM PDT 24
Finished Jun 05 05:44:36 PM PDT 24
Peak memory 221716 kb
Host smart-1fee6a72-2e74-4ea5-a2aa-3657c8b08af8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3283771790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3283771790
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.1910105813
Short name T1319
Test name
Test status
Simulation time 10055913088 ps
CPU time 12.68 seconds
Started Jun 05 05:44:31 PM PDT 24
Finished Jun 05 05:44:45 PM PDT 24
Peak memory 205664 kb
Host smart-a37a253a-2f10-4e9d-bf92-1cec6ae38775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19101
05813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.1910105813
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2750920954
Short name T630
Test name
Test status
Simulation time 10051228228 ps
CPU time 13.97 seconds
Started Jun 05 05:44:28 PM PDT 24
Finished Jun 05 05:44:42 PM PDT 24
Peak memory 205644 kb
Host smart-23809806-3e16-4126-ad50-5e46104ad8a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27509
20954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2750920954
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.3989357907
Short name T1713
Test name
Test status
Simulation time 10170811192 ps
CPU time 14.29 seconds
Started Jun 05 05:44:25 PM PDT 24
Finished Jun 05 05:44:40 PM PDT 24
Peak memory 205728 kb
Host smart-05ac39f3-e4bc-486c-9281-69ac47e0f70b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39893
57907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.3989357907
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.440491473
Short name T1269
Test name
Test status
Simulation time 10131566776 ps
CPU time 12.43 seconds
Started Jun 05 05:44:30 PM PDT 24
Finished Jun 05 05:44:44 PM PDT 24
Peak memory 205488 kb
Host smart-68c04fd5-a788-40cf-848a-98e9f5dc1c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44049
1473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.440491473
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.3608506834
Short name T1061
Test name
Test status
Simulation time 10133916699 ps
CPU time 13.75 seconds
Started Jun 05 05:44:31 PM PDT 24
Finished Jun 05 05:44:45 PM PDT 24
Peak memory 205744 kb
Host smart-8b12b25d-c94e-4435-8ab8-bdcb427dfcce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36085
06834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.3608506834
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.2919359121
Short name T684
Test name
Test status
Simulation time 16325507255 ps
CPU time 192.37 seconds
Started Jun 05 05:44:29 PM PDT 24
Finished Jun 05 05:47:42 PM PDT 24
Peak memory 205680 kb
Host smart-c4e9ead2-85e4-47a8-989c-b30e0dcc9ae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29193
59121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.2919359121
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.495431446
Short name T1913
Test name
Test status
Simulation time 18130382792 ps
CPU time 60.97 seconds
Started Jun 05 05:44:32 PM PDT 24
Finished Jun 05 05:45:33 PM PDT 24
Peak memory 205736 kb
Host smart-fffaf067-ac4f-4ef5-b48c-537ee60f89e3
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495431446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bu
s_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_t
raffic.495431446
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.3502544382
Short name T726
Test name
Test status
Simulation time 10139301331 ps
CPU time 14.19 seconds
Started Jun 05 05:47:49 PM PDT 24
Finished Jun 05 05:48:04 PM PDT 24
Peak memory 205780 kb
Host smart-334410c6-8135-4966-9f08-e53f3160aea8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3502544382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.3502544382
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.1863452173
Short name T357
Test name
Test status
Simulation time 10056766057 ps
CPU time 16.42 seconds
Started Jun 05 05:47:51 PM PDT 24
Finished Jun 05 05:48:08 PM PDT 24
Peak memory 205760 kb
Host smart-3c050228-7723-4622-9dbd-9ff6e0d47cfa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1863452173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.1863452173
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.655610068
Short name T727
Test name
Test status
Simulation time 10117517044 ps
CPU time 14.76 seconds
Started Jun 05 05:47:46 PM PDT 24
Finished Jun 05 05:48:02 PM PDT 24
Peak memory 205640 kb
Host smart-c224d5cf-052a-4af3-8c38-2cd56144d5f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65561
0068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.655610068
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.1356613986
Short name T1657
Test name
Test status
Simulation time 13430751160 ps
CPU time 17.81 seconds
Started Jun 05 05:47:43 PM PDT 24
Finished Jun 05 05:48:01 PM PDT 24
Peak memory 205812 kb
Host smart-323ebb6d-3496-4515-a98b-1a8e5eb92252
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1356613986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.1356613986
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.543890058
Short name T712
Test name
Test status
Simulation time 23216035222 ps
CPU time 25.48 seconds
Started Jun 05 05:47:41 PM PDT 24
Finished Jun 05 05:48:07 PM PDT 24
Peak memory 205792 kb
Host smart-6fb4b03d-7475-4ce3-965c-9bfcb4e9d9aa
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=543890058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.543890058
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.2689673654
Short name T261
Test name
Test status
Simulation time 10101663552 ps
CPU time 12.83 seconds
Started Jun 05 05:47:40 PM PDT 24
Finished Jun 05 05:47:54 PM PDT 24
Peak memory 205924 kb
Host smart-f20b35d1-92b5-4774-8a49-cd1796da95a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26896
73654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2689673654
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.1886264197
Short name T653
Test name
Test status
Simulation time 10907443966 ps
CPU time 15.11 seconds
Started Jun 05 05:47:38 PM PDT 24
Finished Jun 05 05:47:54 PM PDT 24
Peak memory 205696 kb
Host smart-a93e752a-c946-4bc0-aa6e-250a2fdd0ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18862
64197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.1886264197
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.3226592406
Short name T985
Test name
Test status
Simulation time 10039670705 ps
CPU time 13.56 seconds
Started Jun 05 05:47:48 PM PDT 24
Finished Jun 05 05:48:02 PM PDT 24
Peak memory 205604 kb
Host smart-8baeb080-6181-4408-af52-0ea84a290c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32265
92406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.3226592406
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.462465596
Short name T527
Test name
Test status
Simulation time 10052668815 ps
CPU time 14.28 seconds
Started Jun 05 05:47:50 PM PDT 24
Finished Jun 05 05:48:05 PM PDT 24
Peak memory 205652 kb
Host smart-c779a4d1-4d4d-40dc-ab20-045c6b6db182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46246
5596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.462465596
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.187779518
Short name T742
Test name
Test status
Simulation time 10974765815 ps
CPU time 14.37 seconds
Started Jun 05 05:47:46 PM PDT 24
Finished Jun 05 05:48:01 PM PDT 24
Peak memory 205732 kb
Host smart-e9c7d5f1-df0b-40b6-a016-b5e8a34ab239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18777
9518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.187779518
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3696149707
Short name T1468
Test name
Test status
Simulation time 10214243981 ps
CPU time 18.02 seconds
Started Jun 05 05:47:49 PM PDT 24
Finished Jun 05 05:48:08 PM PDT 24
Peak memory 205752 kb
Host smart-7092e4e2-2f46-429c-a6eb-c7faeae64521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36961
49707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3696149707
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.4240325337
Short name T924
Test name
Test status
Simulation time 10124304232 ps
CPU time 15.49 seconds
Started Jun 05 05:47:45 PM PDT 24
Finished Jun 05 05:48:01 PM PDT 24
Peak memory 205756 kb
Host smart-42ec0b1d-51e2-48bf-9a75-981b22e0185f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42403
25337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.4240325337
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.1016556678
Short name T588
Test name
Test status
Simulation time 10049911125 ps
CPU time 13.05 seconds
Started Jun 05 05:47:48 PM PDT 24
Finished Jun 05 05:48:02 PM PDT 24
Peak memory 205724 kb
Host smart-9a29ff09-8d17-4f83-96bd-a2d254c5b65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10165
56678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.1016556678
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.3537763694
Short name T382
Test name
Test status
Simulation time 10163485099 ps
CPU time 16.46 seconds
Started Jun 05 05:47:46 PM PDT 24
Finished Jun 05 05:48:04 PM PDT 24
Peak memory 205708 kb
Host smart-2078e30a-5a79-4952-9ed2-14dc690bda96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35377
63694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.3537763694
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.3279095595
Short name T36
Test name
Test status
Simulation time 10107683466 ps
CPU time 12.77 seconds
Started Jun 05 05:47:45 PM PDT 24
Finished Jun 05 05:47:58 PM PDT 24
Peak memory 205712 kb
Host smart-d2919202-f26f-4d63-9b72-496772cae99c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32790
95595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.3279095595
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.943122091
Short name T1005
Test name
Test status
Simulation time 13218923803 ps
CPU time 17.19 seconds
Started Jun 05 05:47:46 PM PDT 24
Finished Jun 05 05:48:04 PM PDT 24
Peak memory 205744 kb
Host smart-e6286d9a-669c-453a-b400-b6596bd5b163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94312
2091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.943122091
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1706103532
Short name T680
Test name
Test status
Simulation time 10135300889 ps
CPU time 14.33 seconds
Started Jun 05 05:47:45 PM PDT 24
Finished Jun 05 05:48:00 PM PDT 24
Peak memory 205784 kb
Host smart-4b944ba8-b167-4d53-85a4-ee21b4782bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17061
03532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1706103532
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.2602300697
Short name T1850
Test name
Test status
Simulation time 23012845482 ps
CPU time 127.05 seconds
Started Jun 05 05:47:50 PM PDT 24
Finished Jun 05 05:49:58 PM PDT 24
Peak memory 205736 kb
Host smart-f4183282-1546-4729-adbc-735523e8c65e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26023
00697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.2602300697
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.3509888431
Short name T1065
Test name
Test status
Simulation time 10050822641 ps
CPU time 13.27 seconds
Started Jun 05 05:47:45 PM PDT 24
Finished Jun 05 05:48:00 PM PDT 24
Peak memory 205696 kb
Host smart-62575f47-649b-44d0-aef8-b53fd7faa584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35098
88431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.3509888431
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.1259007657
Short name T53
Test name
Test status
Simulation time 10132938647 ps
CPU time 13.58 seconds
Started Jun 05 05:47:45 PM PDT 24
Finished Jun 05 05:47:59 PM PDT 24
Peak memory 205764 kb
Host smart-0e0e4650-0914-4702-89b6-8dd600c9c73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12590
07657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.1259007657
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.1718317135
Short name T1655
Test name
Test status
Simulation time 10084842087 ps
CPU time 12.96 seconds
Started Jun 05 05:47:49 PM PDT 24
Finished Jun 05 05:48:03 PM PDT 24
Peak memory 205712 kb
Host smart-d6dea21c-142c-420d-88c9-302cc92ec132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17183
17135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.1718317135
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.3551337932
Short name T1883
Test name
Test status
Simulation time 10059862313 ps
CPU time 15.3 seconds
Started Jun 05 05:47:47 PM PDT 24
Finished Jun 05 05:48:03 PM PDT 24
Peak memory 205768 kb
Host smart-c663504b-bf04-4702-a978-d3b258acf58b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35513
37932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.3551337932
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.559035515
Short name T629
Test name
Test status
Simulation time 10095366999 ps
CPU time 14.34 seconds
Started Jun 05 05:47:43 PM PDT 24
Finished Jun 05 05:47:58 PM PDT 24
Peak memory 205732 kb
Host smart-04a1abba-bf2c-43f8-a774-cfb93183a5f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55903
5515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.559035515
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.681307866
Short name T1125
Test name
Test status
Simulation time 10058746459 ps
CPU time 14.43 seconds
Started Jun 05 05:47:51 PM PDT 24
Finished Jun 05 05:48:06 PM PDT 24
Peak memory 205748 kb
Host smart-1935ab27-d9c7-4309-a6f0-2a91bdd4ade6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68130
7866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.681307866
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_eop_single_bit_handling.1676399196
Short name T1791
Test name
Test status
Simulation time 10093757504 ps
CPU time 14.12 seconds
Started Jun 05 05:47:50 PM PDT 24
Finished Jun 05 05:48:04 PM PDT 24
Peak memory 205616 kb
Host smart-9ff5943f-af0d-4510-94dc-d86a35b0562a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16763
99196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_eop_single_bit_handling.1676399196
Directory /workspace/30.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.2912524594
Short name T1148
Test name
Test status
Simulation time 10047156638 ps
CPU time 14.43 seconds
Started Jun 05 05:47:47 PM PDT 24
Finished Jun 05 05:48:02 PM PDT 24
Peak memory 205756 kb
Host smart-0dc831ce-73a4-4ad9-8a50-7a1be9a5eedc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29125
24594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.2912524594
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.367343192
Short name T784
Test name
Test status
Simulation time 10044427190 ps
CPU time 13.53 seconds
Started Jun 05 05:47:49 PM PDT 24
Finished Jun 05 05:48:03 PM PDT 24
Peak memory 205608 kb
Host smart-a98338a8-a668-4381-833e-20dac96eb3f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36734
3192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.367343192
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.2943651576
Short name T861
Test name
Test status
Simulation time 31500690517 ps
CPU time 62.67 seconds
Started Jun 05 05:47:50 PM PDT 24
Finished Jun 05 05:48:53 PM PDT 24
Peak memory 205660 kb
Host smart-8958897d-abb2-4d99-b777-df37d6553cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29436
51576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.2943651576
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.3723419237
Short name T466
Test name
Test status
Simulation time 10057020978 ps
CPU time 12.81 seconds
Started Jun 05 05:47:46 PM PDT 24
Finished Jun 05 05:47:59 PM PDT 24
Peak memory 205684 kb
Host smart-c5520721-462b-4fe9-8b61-0ee578de068a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37234
19237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3723419237
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.3198732366
Short name T614
Test name
Test status
Simulation time 10124416277 ps
CPU time 16.66 seconds
Started Jun 05 05:47:46 PM PDT 24
Finished Jun 05 05:48:03 PM PDT 24
Peak memory 205680 kb
Host smart-cbc09217-9470-449b-a9a9-1783defb9576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31987
32366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.3198732366
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.3727048799
Short name T1252
Test name
Test status
Simulation time 10096360843 ps
CPU time 15.49 seconds
Started Jun 05 05:47:49 PM PDT 24
Finished Jun 05 05:48:05 PM PDT 24
Peak memory 205560 kb
Host smart-f1912cf4-fc85-4499-bc72-648a52212914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37270
48799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.3727048799
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.2057157883
Short name T1196
Test name
Test status
Simulation time 10032455668 ps
CPU time 14.92 seconds
Started Jun 05 05:47:46 PM PDT 24
Finished Jun 05 05:48:01 PM PDT 24
Peak memory 205712 kb
Host smart-13d4ed40-d0cc-42d5-8b12-7ea4899160f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20571
57883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.2057157883
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.3719042211
Short name T772
Test name
Test status
Simulation time 10058716039 ps
CPU time 12.85 seconds
Started Jun 05 05:47:47 PM PDT 24
Finished Jun 05 05:48:01 PM PDT 24
Peak memory 205536 kb
Host smart-776ccf83-0df9-415e-9667-b39f631bf693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37190
42211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.3719042211
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3176143070
Short name T975
Test name
Test status
Simulation time 10065914485 ps
CPU time 14.87 seconds
Started Jun 05 05:47:45 PM PDT 24
Finished Jun 05 05:48:01 PM PDT 24
Peak memory 205652 kb
Host smart-8ce2f549-7cbf-4ee5-91dd-8d3e7cf4724e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31761
43070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3176143070
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.1266341017
Short name T1684
Test name
Test status
Simulation time 10131836923 ps
CPU time 13.33 seconds
Started Jun 05 05:47:43 PM PDT 24
Finished Jun 05 05:47:56 PM PDT 24
Peak memory 205592 kb
Host smart-dd3e0eae-e20b-401d-a002-c751ba034344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12663
41017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.1266341017
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.1496317722
Short name T1591
Test name
Test status
Simulation time 10089094576 ps
CPU time 13.92 seconds
Started Jun 05 05:47:49 PM PDT 24
Finished Jun 05 05:48:03 PM PDT 24
Peak memory 205780 kb
Host smart-6888cdb4-6bb8-4b9f-a385-eb30c805f63c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14963
17722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.1496317722
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.1109195758
Short name T1619
Test name
Test status
Simulation time 10099771139 ps
CPU time 15.34 seconds
Started Jun 05 05:47:47 PM PDT 24
Finished Jun 05 05:48:03 PM PDT 24
Peak memory 205644 kb
Host smart-b8a0f3f7-3b78-4abe-a950-0391bb96d7d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11091
95758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.1109195758
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.2954575505
Short name T2028
Test name
Test status
Simulation time 22694523421 ps
CPU time 137.11 seconds
Started Jun 05 05:47:47 PM PDT 24
Finished Jun 05 05:50:05 PM PDT 24
Peak memory 205732 kb
Host smart-541c9a81-d33e-43fa-85fb-25192c395316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29545
75505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.2954575505
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.2031021467
Short name T558
Test name
Test status
Simulation time 10141308663 ps
CPU time 13.25 seconds
Started Jun 05 05:47:54 PM PDT 24
Finished Jun 05 05:48:08 PM PDT 24
Peak memory 205760 kb
Host smart-a2889d4c-4c98-4120-90ee-af469b3531c2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2031021467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.2031021467
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.1197302877
Short name T1995
Test name
Test status
Simulation time 10078620736 ps
CPU time 14.8 seconds
Started Jun 05 05:47:56 PM PDT 24
Finished Jun 05 05:48:12 PM PDT 24
Peak memory 205696 kb
Host smart-4fa5cc19-1eb7-4bdf-b5a0-765b9219fa91
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1197302877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.1197302877
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.3553792395
Short name T986
Test name
Test status
Simulation time 10095160954 ps
CPU time 13.84 seconds
Started Jun 05 05:47:55 PM PDT 24
Finished Jun 05 05:48:09 PM PDT 24
Peak memory 205776 kb
Host smart-2630204e-9df5-4e8a-b547-3d65ae96e048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35537
92395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.3553792395
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.2762858725
Short name T1830
Test name
Test status
Simulation time 14138791109 ps
CPU time 17.52 seconds
Started Jun 05 05:47:44 PM PDT 24
Finished Jun 05 05:48:03 PM PDT 24
Peak memory 205752 kb
Host smart-738c4e3a-0593-4078-a9c9-d9f3082dca6c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2762858725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.2762858725
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.3436324628
Short name T1799
Test name
Test status
Simulation time 23342113367 ps
CPU time 26.17 seconds
Started Jun 05 05:47:49 PM PDT 24
Finished Jun 05 05:48:16 PM PDT 24
Peak memory 205720 kb
Host smart-b42ceff6-de0f-46a1-9ff1-b54c7a4ef21a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3436324628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.3436324628
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.193770369
Short name T773
Test name
Test status
Simulation time 10087004682 ps
CPU time 13.55 seconds
Started Jun 05 05:47:47 PM PDT 24
Finished Jun 05 05:48:01 PM PDT 24
Peak memory 205608 kb
Host smart-3619ee6d-aa7b-47a7-8f28-c2f2a48a782e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19377
0369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.193770369
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.2992822510
Short name T158
Test name
Test status
Simulation time 10984279157 ps
CPU time 17.07 seconds
Started Jun 05 05:47:49 PM PDT 24
Finished Jun 05 05:48:07 PM PDT 24
Peak memory 205568 kb
Host smart-5397f853-9efc-4ec0-bfec-689195b4b8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29928
22510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.2992822510
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.2041128887
Short name T1401
Test name
Test status
Simulation time 10044708280 ps
CPU time 12.75 seconds
Started Jun 05 05:47:47 PM PDT 24
Finished Jun 05 05:48:00 PM PDT 24
Peak memory 205652 kb
Host smart-2311a041-3c64-4c20-864e-4177c9e77f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20411
28887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.2041128887
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.1733596519
Short name T597
Test name
Test status
Simulation time 10049170273 ps
CPU time 14.9 seconds
Started Jun 05 05:47:46 PM PDT 24
Finished Jun 05 05:48:02 PM PDT 24
Peak memory 205688 kb
Host smart-47f62a91-87ac-4097-9046-0610c401b9dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17335
96519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.1733596519
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.411396763
Short name T1656
Test name
Test status
Simulation time 10679350837 ps
CPU time 14.57 seconds
Started Jun 05 05:47:48 PM PDT 24
Finished Jun 05 05:48:03 PM PDT 24
Peak memory 205772 kb
Host smart-c14772ac-bd88-454d-88a7-6b238f8f81f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41139
6763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.411396763
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.93079479
Short name T1972
Test name
Test status
Simulation time 10147212952 ps
CPU time 15.7 seconds
Started Jun 05 05:47:48 PM PDT 24
Finished Jun 05 05:48:05 PM PDT 24
Peak memory 205752 kb
Host smart-c2ad0e3d-7f72-4240-8bab-c527752d0052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93079
479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.93079479
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.2692566721
Short name T971
Test name
Test status
Simulation time 10118190631 ps
CPU time 13.88 seconds
Started Jun 05 05:47:57 PM PDT 24
Finished Jun 05 05:48:12 PM PDT 24
Peak memory 205752 kb
Host smart-e98d2113-21a2-4252-a34e-694d618933fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26925
66721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.2692566721
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.1778161950
Short name T71
Test name
Test status
Simulation time 10043107485 ps
CPU time 15.73 seconds
Started Jun 05 05:47:59 PM PDT 24
Finished Jun 05 05:48:15 PM PDT 24
Peak memory 205664 kb
Host smart-8efb2dd5-785e-4b71-a188-9c4a182317e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17781
61950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.1778161950
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.2076308124
Short name T304
Test name
Test status
Simulation time 10112437619 ps
CPU time 12.4 seconds
Started Jun 05 05:47:45 PM PDT 24
Finished Jun 05 05:47:58 PM PDT 24
Peak memory 205684 kb
Host smart-4548a6eb-b520-480e-96a7-d50e26162c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20763
08124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2076308124
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.3714974800
Short name T2029
Test name
Test status
Simulation time 10122262032 ps
CPU time 16.5 seconds
Started Jun 05 05:47:49 PM PDT 24
Finished Jun 05 05:48:06 PM PDT 24
Peak memory 205764 kb
Host smart-d60c631e-a4d1-474a-84cf-f0e5fbf5f4fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37149
74800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.3714974800
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.3294385444
Short name T967
Test name
Test status
Simulation time 13247113418 ps
CPU time 19.71 seconds
Started Jun 05 05:47:47 PM PDT 24
Finished Jun 05 05:48:07 PM PDT 24
Peak memory 205696 kb
Host smart-57b682f0-7f24-4b5c-be62-2bfed304a039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32943
85444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.3294385444
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.3513905669
Short name T1582
Test name
Test status
Simulation time 10124486130 ps
CPU time 13.26 seconds
Started Jun 05 05:47:48 PM PDT 24
Finished Jun 05 05:48:02 PM PDT 24
Peak memory 205828 kb
Host smart-b586bbf9-5b7f-47e2-88ca-b672dccf055d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35139
05669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.3513905669
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.2607345209
Short name T1873
Test name
Test status
Simulation time 19188217315 ps
CPU time 273.1 seconds
Started Jun 05 05:47:49 PM PDT 24
Finished Jun 05 05:52:23 PM PDT 24
Peak memory 205684 kb
Host smart-08f0777c-bb73-4dbc-868d-f9e81d419918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26073
45209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.2607345209
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1664370230
Short name T1254
Test name
Test status
Simulation time 10094796286 ps
CPU time 13.48 seconds
Started Jun 05 05:47:46 PM PDT 24
Finished Jun 05 05:48:00 PM PDT 24
Peak memory 205804 kb
Host smart-7c274740-8c11-493b-b429-2fa2b6b81b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16643
70230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1664370230
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.855533700
Short name T740
Test name
Test status
Simulation time 10058672148 ps
CPU time 13.36 seconds
Started Jun 05 05:47:47 PM PDT 24
Finished Jun 05 05:48:01 PM PDT 24
Peak memory 205612 kb
Host smart-ec7e5f35-a962-450f-8783-5a23599eb29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85553
3700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.855533700
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.2471594560
Short name T1280
Test name
Test status
Simulation time 10151805328 ps
CPU time 13.54 seconds
Started Jun 05 05:47:47 PM PDT 24
Finished Jun 05 05:48:01 PM PDT 24
Peak memory 205780 kb
Host smart-69ccc314-f61d-4c9d-bd94-6a3610920cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24715
94560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.2471594560
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.214109371
Short name T656
Test name
Test status
Simulation time 10043365609 ps
CPU time 15.08 seconds
Started Jun 05 05:47:52 PM PDT 24
Finished Jun 05 05:48:08 PM PDT 24
Peak memory 205692 kb
Host smart-3763c9c9-9c4a-4a66-a7b2-67f0e4c1f773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21410
9371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.214109371
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_eop_single_bit_handling.2876967346
Short name T325
Test name
Test status
Simulation time 10076292798 ps
CPU time 14.17 seconds
Started Jun 05 05:47:57 PM PDT 24
Finished Jun 05 05:48:12 PM PDT 24
Peak memory 205656 kb
Host smart-f6bbb379-c717-4208-a940-1ce1fef49664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28769
67346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_eop_single_bit_handling.2876967346
Directory /workspace/31.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.1148082611
Short name T1264
Test name
Test status
Simulation time 10036688882 ps
CPU time 17.29 seconds
Started Jun 05 05:47:53 PM PDT 24
Finished Jun 05 05:48:11 PM PDT 24
Peak memory 205664 kb
Host smart-9f51d584-6c3c-405c-ba56-fea31fda44cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11480
82611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.1148082611
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.2664178752
Short name T84
Test name
Test status
Simulation time 32562015994 ps
CPU time 67.92 seconds
Started Jun 05 05:47:55 PM PDT 24
Finished Jun 05 05:49:04 PM PDT 24
Peak memory 205680 kb
Host smart-b2e8d1f6-5eb8-41b2-82a1-8d928f9a47e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26641
78752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.2664178752
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2029039325
Short name T1289
Test name
Test status
Simulation time 10123320289 ps
CPU time 16.42 seconds
Started Jun 05 05:47:56 PM PDT 24
Finished Jun 05 05:48:13 PM PDT 24
Peak memory 205564 kb
Host smart-20cea962-3f3f-49d5-b871-f7fca29d171c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20290
39325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2029039325
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.814274443
Short name T626
Test name
Test status
Simulation time 10172789727 ps
CPU time 14.91 seconds
Started Jun 05 05:47:58 PM PDT 24
Finished Jun 05 05:48:13 PM PDT 24
Peak memory 205664 kb
Host smart-d5ee7c0e-2fe1-4bfc-bf96-7017878e8f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81427
4443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.814274443
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.301982526
Short name T1420
Test name
Test status
Simulation time 10098160802 ps
CPU time 14.24 seconds
Started Jun 05 05:47:56 PM PDT 24
Finished Jun 05 05:48:11 PM PDT 24
Peak memory 205704 kb
Host smart-e3cab148-d513-43d0-a3c5-a700941121e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30198
2526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.301982526
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.3562360870
Short name T1659
Test name
Test status
Simulation time 10046144972 ps
CPU time 13.6 seconds
Started Jun 05 05:48:00 PM PDT 24
Finished Jun 05 05:48:14 PM PDT 24
Peak memory 205732 kb
Host smart-841f2ce8-09ce-43c0-a04e-a0a82e15b709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35623
60870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.3562360870
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.1183429749
Short name T1532
Test name
Test status
Simulation time 10054271326 ps
CPU time 12.99 seconds
Started Jun 05 05:48:00 PM PDT 24
Finished Jun 05 05:48:14 PM PDT 24
Peak memory 205688 kb
Host smart-f4cd2f1a-58b2-4ffd-b119-c92077cd2106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11834
29749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.1183429749
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.2776357238
Short name T373
Test name
Test status
Simulation time 10041564425 ps
CPU time 13.59 seconds
Started Jun 05 05:47:56 PM PDT 24
Finished Jun 05 05:48:11 PM PDT 24
Peak memory 205696 kb
Host smart-c4b34528-8869-4e96-9f00-5a310dd65d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27763
57238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.2776357238
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.2236991630
Short name T1322
Test name
Test status
Simulation time 10135191448 ps
CPU time 12.72 seconds
Started Jun 05 05:47:48 PM PDT 24
Finished Jun 05 05:48:01 PM PDT 24
Peak memory 205688 kb
Host smart-a4064963-77a6-4fb8-8c83-dbfd42e78cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22369
91630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2236991630
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.380797533
Short name T1815
Test name
Test status
Simulation time 10112406568 ps
CPU time 14.13 seconds
Started Jun 05 05:47:58 PM PDT 24
Finished Jun 05 05:48:13 PM PDT 24
Peak memory 205664 kb
Host smart-d835ea72-44b0-464d-a6c9-2593dcd0cfda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38079
7533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.380797533
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.2890428801
Short name T1190
Test name
Test status
Simulation time 10145677802 ps
CPU time 15.97 seconds
Started Jun 05 05:47:56 PM PDT 24
Finished Jun 05 05:48:13 PM PDT 24
Peak memory 205652 kb
Host smart-88e6ab49-e1d5-4bc7-a116-52fed80d59a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28904
28801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.2890428801
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.2530293721
Short name T933
Test name
Test status
Simulation time 20869961142 ps
CPU time 94.66 seconds
Started Jun 05 05:47:58 PM PDT 24
Finished Jun 05 05:49:34 PM PDT 24
Peak memory 205704 kb
Host smart-dca608a1-3b5b-41f9-8cc6-33096e4b83e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25302
93721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.2530293721
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.4109902056
Short name T402
Test name
Test status
Simulation time 10158032016 ps
CPU time 13.14 seconds
Started Jun 05 05:48:03 PM PDT 24
Finished Jun 05 05:48:16 PM PDT 24
Peak memory 205700 kb
Host smart-a2f753bd-a7e7-4785-966d-fb09b51142b0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4109902056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.4109902056
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.4113219777
Short name T798
Test name
Test status
Simulation time 10081529122 ps
CPU time 13.86 seconds
Started Jun 05 05:48:09 PM PDT 24
Finished Jun 05 05:48:23 PM PDT 24
Peak memory 205760 kb
Host smart-0a774e0b-f446-48c3-b94a-e6368c9e899a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4113219777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.4113219777
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.148090412
Short name T1509
Test name
Test status
Simulation time 10086663416 ps
CPU time 14.32 seconds
Started Jun 05 05:48:08 PM PDT 24
Finished Jun 05 05:48:23 PM PDT 24
Peak memory 205612 kb
Host smart-9fccdc86-254f-4e20-84a1-6f4f7146838e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14809
0412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.148090412
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.101935273
Short name T12
Test name
Test status
Simulation time 13433942067 ps
CPU time 19.5 seconds
Started Jun 05 05:47:54 PM PDT 24
Finished Jun 05 05:48:14 PM PDT 24
Peak memory 205976 kb
Host smart-ff0ed459-2619-4998-b6a6-ca519b7a53e7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=101935273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.101935273
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3796508768
Short name T820
Test name
Test status
Simulation time 23285146894 ps
CPU time 28.15 seconds
Started Jun 05 05:47:59 PM PDT 24
Finished Jun 05 05:48:28 PM PDT 24
Peak memory 205736 kb
Host smart-13e9100f-e4ec-4d00-aca7-c00e67dbadc9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3796508768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3796508768
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.3581856472
Short name T386
Test name
Test status
Simulation time 10105629835 ps
CPU time 15.4 seconds
Started Jun 05 05:48:01 PM PDT 24
Finished Jun 05 05:48:17 PM PDT 24
Peak memory 205764 kb
Host smart-33cb60fc-e6bd-4066-8bc3-36f14105aa5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35818
56472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3581856472
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.1005861939
Short name T1301
Test name
Test status
Simulation time 10072197650 ps
CPU time 13.44 seconds
Started Jun 05 05:48:01 PM PDT 24
Finished Jun 05 05:48:15 PM PDT 24
Peak memory 205760 kb
Host smart-51cbc9fc-9b60-47ff-bbe2-f708b8927529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10058
61939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.1005861939
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1438596503
Short name T1562
Test name
Test status
Simulation time 10689438835 ps
CPU time 15.17 seconds
Started Jun 05 05:47:54 PM PDT 24
Finished Jun 05 05:48:10 PM PDT 24
Peak memory 205912 kb
Host smart-33d1d285-728d-4764-b281-eb9bdd383229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14385
96503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1438596503
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.3792663851
Short name T324
Test name
Test status
Simulation time 10071963162 ps
CPU time 12.83 seconds
Started Jun 05 05:47:58 PM PDT 24
Finished Jun 05 05:48:11 PM PDT 24
Peak memory 205760 kb
Host smart-969bb7e6-56ba-4ae6-af1f-66f3852f0250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37926
63851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.3792663851
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2345738588
Short name T1920
Test name
Test status
Simulation time 10052486583 ps
CPU time 14.8 seconds
Started Jun 05 05:47:55 PM PDT 24
Finished Jun 05 05:48:10 PM PDT 24
Peak memory 205712 kb
Host smart-fff612b4-2248-48be-ab5b-8d6c5b09c2ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23457
38588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2345738588
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.2915342406
Short name T478
Test name
Test status
Simulation time 10777644396 ps
CPU time 13.91 seconds
Started Jun 05 05:47:57 PM PDT 24
Finished Jun 05 05:48:11 PM PDT 24
Peak memory 205704 kb
Host smart-15be7d88-2e2c-49b1-be90-7e828a07b258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29153
42406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.2915342406
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.45993786
Short name T177
Test name
Test status
Simulation time 10125728212 ps
CPU time 14.09 seconds
Started Jun 05 05:47:56 PM PDT 24
Finished Jun 05 05:48:11 PM PDT 24
Peak memory 205772 kb
Host smart-02b296c0-db8b-4e13-86e0-76c18b53b052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45993
786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.45993786
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.890110181
Short name T869
Test name
Test status
Simulation time 10078739254 ps
CPU time 13.38 seconds
Started Jun 05 05:48:04 PM PDT 24
Finished Jun 05 05:48:17 PM PDT 24
Peak memory 205676 kb
Host smart-58186396-8e5e-4c6f-b6e8-92a35ae437fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89011
0181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.890110181
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1864464685
Short name T535
Test name
Test status
Simulation time 10048982959 ps
CPU time 13.33 seconds
Started Jun 05 05:48:06 PM PDT 24
Finished Jun 05 05:48:20 PM PDT 24
Peak memory 205720 kb
Host smart-0dcd4f5b-c5ac-4bbd-bc5e-cd494b160ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18644
64685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1864464685
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.799439982
Short name T654
Test name
Test status
Simulation time 10108785882 ps
CPU time 13.23 seconds
Started Jun 05 05:48:02 PM PDT 24
Finished Jun 05 05:48:16 PM PDT 24
Peak memory 205708 kb
Host smart-aa83606e-a88b-44f8-af12-7adc1203d639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79943
9982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.799439982
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.1415283425
Short name T365
Test name
Test status
Simulation time 10141020796 ps
CPU time 15.27 seconds
Started Jun 05 05:47:59 PM PDT 24
Finished Jun 05 05:48:15 PM PDT 24
Peak memory 205764 kb
Host smart-d3127830-76a4-488c-8682-8758683988d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14152
83425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1415283425
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.2765520255
Short name T1075
Test name
Test status
Simulation time 13229984667 ps
CPU time 17.11 seconds
Started Jun 05 05:47:56 PM PDT 24
Finished Jun 05 05:48:14 PM PDT 24
Peak memory 205620 kb
Host smart-c31e7bd2-dd09-470a-970c-0b94362c1c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27655
20255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.2765520255
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1478577317
Short name T332
Test name
Test status
Simulation time 10092641509 ps
CPU time 15.19 seconds
Started Jun 05 05:47:56 PM PDT 24
Finished Jun 05 05:48:12 PM PDT 24
Peak memory 205740 kb
Host smart-d7fc6581-7051-447e-8aeb-3242f16dfd01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14785
77317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1478577317
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.95743328
Short name T204
Test name
Test status
Simulation time 19383335042 ps
CPU time 102.59 seconds
Started Jun 05 05:47:58 PM PDT 24
Finished Jun 05 05:49:41 PM PDT 24
Peak memory 205664 kb
Host smart-4a9053ff-1206-41f5-9887-8a7b3067e4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95743
328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.95743328
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1801462730
Short name T1625
Test name
Test status
Simulation time 10050037825 ps
CPU time 12.99 seconds
Started Jun 05 05:47:58 PM PDT 24
Finished Jun 05 05:48:11 PM PDT 24
Peak memory 205672 kb
Host smart-b17d967e-9c43-44b2-bb53-5ce5b89e0797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18014
62730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1801462730
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1258279739
Short name T101
Test name
Test status
Simulation time 10144110882 ps
CPU time 12.59 seconds
Started Jun 05 05:47:53 PM PDT 24
Finished Jun 05 05:48:07 PM PDT 24
Peak memory 205804 kb
Host smart-6ca5f81a-229a-493b-ba47-3b1da636d3f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12582
79739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1258279739
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.895199334
Short name T1145
Test name
Test status
Simulation time 10097850099 ps
CPU time 13.09 seconds
Started Jun 05 05:47:58 PM PDT 24
Finished Jun 05 05:48:12 PM PDT 24
Peak memory 205748 kb
Host smart-81fb03fd-46db-4af7-8a6a-c9dde15c9848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89519
9334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.895199334
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.3041176301
Short name T1994
Test name
Test status
Simulation time 10062032618 ps
CPU time 13.65 seconds
Started Jun 05 05:47:58 PM PDT 24
Finished Jun 05 05:48:12 PM PDT 24
Peak memory 205652 kb
Host smart-44843c36-5cb3-4fa9-8460-f37b06320a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30411
76301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.3041176301
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.3826622427
Short name T1323
Test name
Test status
Simulation time 10054607757 ps
CPU time 16.01 seconds
Started Jun 05 05:48:01 PM PDT 24
Finished Jun 05 05:48:18 PM PDT 24
Peak memory 205544 kb
Host smart-ea9954de-0125-4f92-b5ad-02abf61ceb81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38266
22427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.3826622427
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.722849033
Short name T1898
Test name
Test status
Simulation time 10060166890 ps
CPU time 13.29 seconds
Started Jun 05 05:48:04 PM PDT 24
Finished Jun 05 05:48:19 PM PDT 24
Peak memory 205732 kb
Host smart-5c80c577-b991-41cb-afa7-53131a147a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72284
9033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.722849033
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_eop_single_bit_handling.2190575674
Short name T714
Test name
Test status
Simulation time 10075492326 ps
CPU time 13.93 seconds
Started Jun 05 05:48:08 PM PDT 24
Finished Jun 05 05:48:23 PM PDT 24
Peak memory 205620 kb
Host smart-21d447d7-f9cb-4add-9621-188eb6103517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21905
75674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_eop_single_bit_handling.2190575674
Directory /workspace/32.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.1093048521
Short name T540
Test name
Test status
Simulation time 10054819582 ps
CPU time 13.16 seconds
Started Jun 05 05:48:08 PM PDT 24
Finished Jun 05 05:48:22 PM PDT 24
Peak memory 205736 kb
Host smart-4e24d250-826e-497d-be69-1144b6077e27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10930
48521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.1093048521
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1666976253
Short name T1844
Test name
Test status
Simulation time 10088648190 ps
CPU time 15.93 seconds
Started Jun 05 05:48:08 PM PDT 24
Finished Jun 05 05:48:25 PM PDT 24
Peak memory 205288 kb
Host smart-af997b4e-7f17-4811-9a22-ebdd6d216e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16669
76253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1666976253
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1567506201
Short name T1824
Test name
Test status
Simulation time 23393198231 ps
CPU time 46.01 seconds
Started Jun 05 05:48:01 PM PDT 24
Finished Jun 05 05:48:47 PM PDT 24
Peak memory 205420 kb
Host smart-ebab9df2-13fe-4955-9e5c-4195a7186697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15675
06201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1567506201
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3126526975
Short name T659
Test name
Test status
Simulation time 10079439867 ps
CPU time 13.3 seconds
Started Jun 05 05:48:00 PM PDT 24
Finished Jun 05 05:48:14 PM PDT 24
Peak memory 205652 kb
Host smart-7e906d7a-20bd-4fa1-b4f0-cedae8cba9ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31265
26975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3126526975
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.2102312649
Short name T1731
Test name
Test status
Simulation time 10073262370 ps
CPU time 15.34 seconds
Started Jun 05 05:47:59 PM PDT 24
Finished Jun 05 05:48:14 PM PDT 24
Peak memory 205664 kb
Host smart-ea4bd852-9d0c-4342-82cb-4e8d1372180e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21023
12649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.2102312649
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.2888049651
Short name T517
Test name
Test status
Simulation time 10088091384 ps
CPU time 14.28 seconds
Started Jun 05 05:47:56 PM PDT 24
Finished Jun 05 05:48:11 PM PDT 24
Peak memory 205616 kb
Host smart-129bc4b2-93aa-41d7-a557-79dbfdaa3b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28880
49651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.2888049651
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.1117942290
Short name T1277
Test name
Test status
Simulation time 10055945023 ps
CPU time 15.11 seconds
Started Jun 05 05:48:05 PM PDT 24
Finished Jun 05 05:48:21 PM PDT 24
Peak memory 205716 kb
Host smart-478a245f-95f3-4d1b-acf7-b53ba3323b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11179
42290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.1117942290
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.292647129
Short name T1052
Test name
Test status
Simulation time 10065842867 ps
CPU time 13.48 seconds
Started Jun 05 05:48:06 PM PDT 24
Finished Jun 05 05:48:20 PM PDT 24
Peak memory 205724 kb
Host smart-95e01852-e1f5-4823-88c3-d1679f44d955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29264
7129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.292647129
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.4116998598
Short name T1085
Test name
Test status
Simulation time 10066729211 ps
CPU time 13.32 seconds
Started Jun 05 05:48:04 PM PDT 24
Finished Jun 05 05:48:18 PM PDT 24
Peak memory 205740 kb
Host smart-7e3d660b-38c4-46ce-af83-53d7941a4b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41169
98598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.4116998598
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1368496461
Short name T898
Test name
Test status
Simulation time 10184306583 ps
CPU time 16.79 seconds
Started Jun 05 05:47:55 PM PDT 24
Finished Jun 05 05:48:13 PM PDT 24
Peak memory 205692 kb
Host smart-19483f17-8c63-49a3-a91f-0414b34d7a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13684
96461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1368496461
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.3051173247
Short name T996
Test name
Test status
Simulation time 10056474370 ps
CPU time 12.73 seconds
Started Jun 05 05:48:04 PM PDT 24
Finished Jun 05 05:48:18 PM PDT 24
Peak memory 205736 kb
Host smart-e8c836d1-c1e3-4a38-b9f5-20f3103f4714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30511
73247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.3051173247
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.2967557453
Short name T421
Test name
Test status
Simulation time 10046301248 ps
CPU time 13.08 seconds
Started Jun 05 05:47:58 PM PDT 24
Finished Jun 05 05:48:12 PM PDT 24
Peak memory 205672 kb
Host smart-8b0989a8-3d4e-4700-b4fa-380a3a5cc5c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29675
57453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.2967557453
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.2342591846
Short name T1417
Test name
Test status
Simulation time 23988059386 ps
CPU time 404.04 seconds
Started Jun 05 05:48:01 PM PDT 24
Finished Jun 05 05:54:46 PM PDT 24
Peak memory 205352 kb
Host smart-7e4d47c4-990e-4da6-b097-0de1ae6438a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23425
91846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.2342591846
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.2998243190
Short name T884
Test name
Test status
Simulation time 10143876774 ps
CPU time 12.78 seconds
Started Jun 05 05:48:05 PM PDT 24
Finished Jun 05 05:48:19 PM PDT 24
Peak memory 205820 kb
Host smart-082f2e27-02b1-4b34-ba17-8c6c96391ec8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2998243190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.2998243190
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.2857774270
Short name T459
Test name
Test status
Simulation time 10070402468 ps
CPU time 12.6 seconds
Started Jun 05 05:48:05 PM PDT 24
Finished Jun 05 05:48:18 PM PDT 24
Peak memory 205788 kb
Host smart-2e1e45f8-6c15-498d-a688-a854cc4f5f72
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2857774270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.2857774270
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.66711127
Short name T1968
Test name
Test status
Simulation time 10081593717 ps
CPU time 14.08 seconds
Started Jun 05 05:48:19 PM PDT 24
Finished Jun 05 05:48:35 PM PDT 24
Peak memory 205680 kb
Host smart-7fb912b6-0039-4b03-90aa-e265d6e1d948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66711
127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.66711127
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.629437973
Short name T208
Test name
Test status
Simulation time 13333791193 ps
CPU time 17.57 seconds
Started Jun 05 05:48:04 PM PDT 24
Finished Jun 05 05:48:22 PM PDT 24
Peak memory 205648 kb
Host smart-4b11dc12-52bb-496b-8c6c-dd9c4bcd61ff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=629437973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.629437973
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.314001944
Short name T704
Test name
Test status
Simulation time 23192424536 ps
CPU time 26.16 seconds
Started Jun 05 05:48:06 PM PDT 24
Finished Jun 05 05:48:33 PM PDT 24
Peak memory 205724 kb
Host smart-70bc483b-aef9-4ce0-b751-8d84e29d8294
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=314001944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.314001944
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.2622098184
Short name T260
Test name
Test status
Simulation time 10054649376 ps
CPU time 14.02 seconds
Started Jun 05 05:48:06 PM PDT 24
Finished Jun 05 05:48:21 PM PDT 24
Peak memory 205736 kb
Host smart-95f8b09f-0ef7-42fd-8f1e-332dfe93dd7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26220
98184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.2622098184
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.1644934760
Short name T1380
Test name
Test status
Simulation time 10323931100 ps
CPU time 13.8 seconds
Started Jun 05 05:48:07 PM PDT 24
Finished Jun 05 05:48:22 PM PDT 24
Peak memory 205692 kb
Host smart-c323e049-bef7-469d-b393-7d2a0758921b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16449
34760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.1644934760
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2569031396
Short name T44
Test name
Test status
Simulation time 10059661929 ps
CPU time 13.8 seconds
Started Jun 05 05:48:07 PM PDT 24
Finished Jun 05 05:48:22 PM PDT 24
Peak memory 205664 kb
Host smart-8f8e2e1a-dc2b-4ad6-912a-85410cea6327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25690
31396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2569031396
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.1418280897
Short name T1992
Test name
Test status
Simulation time 10054920570 ps
CPU time 13.4 seconds
Started Jun 05 05:48:04 PM PDT 24
Finished Jun 05 05:48:18 PM PDT 24
Peak memory 205656 kb
Host smart-cccbcef7-ee71-43c1-913e-6642d7f4e6ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14182
80897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1418280897
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.1123624485
Short name T956
Test name
Test status
Simulation time 10825382617 ps
CPU time 14.67 seconds
Started Jun 05 05:48:06 PM PDT 24
Finished Jun 05 05:48:21 PM PDT 24
Peak memory 205680 kb
Host smart-6f9553e6-53c0-4c26-874d-01b941e93335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11236
24485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.1123624485
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.4219116883
Short name T1204
Test name
Test status
Simulation time 10159045749 ps
CPU time 13.65 seconds
Started Jun 05 05:48:05 PM PDT 24
Finished Jun 05 05:48:20 PM PDT 24
Peak memory 205728 kb
Host smart-93cfe6e4-cd98-499e-aad5-0460ad0b0532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42191
16883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.4219116883
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.2937360490
Short name T1679
Test name
Test status
Simulation time 10072955499 ps
CPU time 14.57 seconds
Started Jun 05 05:48:03 PM PDT 24
Finished Jun 05 05:48:18 PM PDT 24
Peak memory 205724 kb
Host smart-4c24c78b-0f23-4d74-9788-447184c5b696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29373
60490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2937360490
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.4116255866
Short name T1601
Test name
Test status
Simulation time 10074360562 ps
CPU time 12.84 seconds
Started Jun 05 05:48:09 PM PDT 24
Finished Jun 05 05:48:23 PM PDT 24
Peak memory 205660 kb
Host smart-19da203c-b7d9-4a46-a23e-e72e6d94e356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41162
55866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.4116255866
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.597904452
Short name T1351
Test name
Test status
Simulation time 10138301262 ps
CPU time 13.85 seconds
Started Jun 05 05:48:03 PM PDT 24
Finished Jun 05 05:48:17 PM PDT 24
Peak memory 205748 kb
Host smart-3c43209e-0d2d-447c-8a09-c09911a99512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59790
4452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.597904452
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.1303631312
Short name T618
Test name
Test status
Simulation time 10056391951 ps
CPU time 16.09 seconds
Started Jun 05 05:48:04 PM PDT 24
Finished Jun 05 05:48:21 PM PDT 24
Peak memory 205788 kb
Host smart-dd04fec6-8401-48c6-856b-9b75c1f9032d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13036
31312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.1303631312
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.3631139496
Short name T1944
Test name
Test status
Simulation time 13166542321 ps
CPU time 18.3 seconds
Started Jun 05 05:48:18 PM PDT 24
Finished Jun 05 05:48:37 PM PDT 24
Peak memory 205788 kb
Host smart-457bf1fc-d6b3-405f-8696-57ac478aa2a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36311
39496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.3631139496
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1753355589
Short name T302
Test name
Test status
Simulation time 10097157717 ps
CPU time 16.09 seconds
Started Jun 05 05:48:08 PM PDT 24
Finished Jun 05 05:48:25 PM PDT 24
Peak memory 205764 kb
Host smart-6b4774eb-2a37-4809-8a9a-8fac9d7be9c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17533
55589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1753355589
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.15347427
Short name T949
Test name
Test status
Simulation time 16065045548 ps
CPU time 169 seconds
Started Jun 05 05:48:19 PM PDT 24
Finished Jun 05 05:51:09 PM PDT 24
Peak memory 205716 kb
Host smart-10b044a5-2016-4da2-a3f5-ebb8626b1b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15347
427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.15347427
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.1774940836
Short name T1845
Test name
Test status
Simulation time 10091491122 ps
CPU time 12.95 seconds
Started Jun 05 05:48:04 PM PDT 24
Finished Jun 05 05:48:18 PM PDT 24
Peak memory 205736 kb
Host smart-200a3dbb-be4f-4896-ba0d-d91c47747b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17749
40836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.1774940836
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.2082251808
Short name T2024
Test name
Test status
Simulation time 10119824206 ps
CPU time 13.84 seconds
Started Jun 05 05:48:09 PM PDT 24
Finished Jun 05 05:48:23 PM PDT 24
Peak memory 205716 kb
Host smart-ce11c572-8932-403c-a20c-508366619357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20822
51808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2082251808
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3325027805
Short name T1834
Test name
Test status
Simulation time 10075921296 ps
CPU time 15.21 seconds
Started Jun 05 05:48:05 PM PDT 24
Finished Jun 05 05:48:21 PM PDT 24
Peak memory 205656 kb
Host smart-40825ac1-2ccf-4889-9ffd-bf14a95686e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33250
27805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3325027805
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.3940523125
Short name T1664
Test name
Test status
Simulation time 10052647023 ps
CPU time 12.71 seconds
Started Jun 05 05:48:04 PM PDT 24
Finished Jun 05 05:48:18 PM PDT 24
Peak memory 205672 kb
Host smart-1ad96400-5e2b-4d2f-a827-352f34c62568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39405
23125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.3940523125
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.3111063009
Short name T1910
Test name
Test status
Simulation time 10054327500 ps
CPU time 16.46 seconds
Started Jun 05 05:48:09 PM PDT 24
Finished Jun 05 05:48:26 PM PDT 24
Peak memory 205668 kb
Host smart-29ffac50-48e8-494b-822b-ba8cd68a3b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31110
63009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.3111063009
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_eop_single_bit_handling.1978943996
Short name T1223
Test name
Test status
Simulation time 10085326721 ps
CPU time 14.01 seconds
Started Jun 05 05:48:05 PM PDT 24
Finished Jun 05 05:48:20 PM PDT 24
Peak memory 205692 kb
Host smart-17436d25-2793-4cb1-ad03-115908b215cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19789
43996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_eop_single_bit_handling.1978943996
Directory /workspace/33.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.3010922301
Short name T1823
Test name
Test status
Simulation time 10048664860 ps
CPU time 12.96 seconds
Started Jun 05 05:48:06 PM PDT 24
Finished Jun 05 05:48:19 PM PDT 24
Peak memory 205612 kb
Host smart-b26b7a05-e0e0-4218-8c54-ce386a5a8ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30109
22301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.3010922301
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1004093830
Short name T1436
Test name
Test status
Simulation time 10035819690 ps
CPU time 14.19 seconds
Started Jun 05 05:48:05 PM PDT 24
Finished Jun 05 05:48:20 PM PDT 24
Peak memory 205696 kb
Host smart-ee174e00-d9de-4211-85d5-51387c57b6f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10040
93830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1004093830
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.328786073
Short name T788
Test name
Test status
Simulation time 32295812871 ps
CPU time 61.98 seconds
Started Jun 05 05:48:04 PM PDT 24
Finished Jun 05 05:49:07 PM PDT 24
Peak memory 205676 kb
Host smart-a80aa4f3-379b-4057-8006-73c41d4beaca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32878
6073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.328786073
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.463093663
Short name T1555
Test name
Test status
Simulation time 10056370910 ps
CPU time 14.41 seconds
Started Jun 05 05:48:08 PM PDT 24
Finished Jun 05 05:48:23 PM PDT 24
Peak memory 205640 kb
Host smart-d0ea0d41-1cd2-407d-92f8-5e66414a6363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46309
3663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.463093663
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.1011944243
Short name T327
Test name
Test status
Simulation time 10124740113 ps
CPU time 15.8 seconds
Started Jun 05 05:48:05 PM PDT 24
Finished Jun 05 05:48:22 PM PDT 24
Peak memory 205788 kb
Host smart-787db3f1-c263-4c44-94db-b12460a9624e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10119
44243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.1011944243
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.1412634232
Short name T259
Test name
Test status
Simulation time 10102237853 ps
CPU time 13.25 seconds
Started Jun 05 05:48:04 PM PDT 24
Finished Jun 05 05:48:19 PM PDT 24
Peak memory 205696 kb
Host smart-9fad680f-f7f7-4f65-9796-9c92357654d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14126
34232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.1412634232
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1469007980
Short name T524
Test name
Test status
Simulation time 10058110132 ps
CPU time 15.67 seconds
Started Jun 05 05:48:04 PM PDT 24
Finished Jun 05 05:48:21 PM PDT 24
Peak memory 205700 kb
Host smart-f1ab86fb-d4eb-4e4a-8c74-059034fd0430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14690
07980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1469007980
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.1045968779
Short name T1012
Test name
Test status
Simulation time 10078099867 ps
CPU time 13.88 seconds
Started Jun 05 05:48:04 PM PDT 24
Finished Jun 05 05:48:18 PM PDT 24
Peak memory 205684 kb
Host smart-3070740b-b957-4de1-8535-5a6343d3855d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10459
68779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.1045968779
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.895763419
Short name T1700
Test name
Test status
Simulation time 10063513277 ps
CPU time 14.76 seconds
Started Jun 05 05:48:20 PM PDT 24
Finished Jun 05 05:48:35 PM PDT 24
Peak memory 205784 kb
Host smart-75f74bf6-a366-4cc6-9fcb-9263062d21f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89576
3419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.895763419
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.391110774
Short name T828
Test name
Test status
Simulation time 10124275686 ps
CPU time 14.97 seconds
Started Jun 05 05:48:18 PM PDT 24
Finished Jun 05 05:48:34 PM PDT 24
Peak memory 205708 kb
Host smart-9238c374-be63-4c22-9d05-3ff546338584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39111
0774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.391110774
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.36012759
Short name T430
Test name
Test status
Simulation time 10087549910 ps
CPU time 15.51 seconds
Started Jun 05 05:48:03 PM PDT 24
Finished Jun 05 05:48:19 PM PDT 24
Peak memory 205924 kb
Host smart-6b6cfc04-e80f-4f2e-8f1c-42c2c3781cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36012
759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.36012759
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.4242953593
Short name T1117
Test name
Test status
Simulation time 10084342002 ps
CPU time 14.21 seconds
Started Jun 05 05:48:06 PM PDT 24
Finished Jun 05 05:48:21 PM PDT 24
Peak memory 205648 kb
Host smart-91d1e481-1799-4a1a-9920-09505ba4b324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42429
53593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.4242953593
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.799468924
Short name T1517
Test name
Test status
Simulation time 17944224218 ps
CPU time 86.25 seconds
Started Jun 05 05:48:08 PM PDT 24
Finished Jun 05 05:49:35 PM PDT 24
Peak memory 205316 kb
Host smart-5c218f24-8a9f-47ce-8e7d-a5afd6e79cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79946
8924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.799468924
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.1704097839
Short name T1327
Test name
Test status
Simulation time 10133600899 ps
CPU time 15.19 seconds
Started Jun 05 05:48:11 PM PDT 24
Finished Jun 05 05:48:27 PM PDT 24
Peak memory 205628 kb
Host smart-515998e9-fae6-47a5-8b77-154dd4b17341
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1704097839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.1704097839
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.2272918857
Short name T1043
Test name
Test status
Simulation time 10063307333 ps
CPU time 14.73 seconds
Started Jun 05 05:48:15 PM PDT 24
Finished Jun 05 05:48:31 PM PDT 24
Peak memory 205636 kb
Host smart-dc37ba35-b9ae-46f4-9bed-a16746e1998e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2272918857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.2272918857
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.2759879740
Short name T846
Test name
Test status
Simulation time 10140012177 ps
CPU time 15.26 seconds
Started Jun 05 05:48:15 PM PDT 24
Finished Jun 05 05:48:31 PM PDT 24
Peak memory 205536 kb
Host smart-0f9b8252-3c88-46b0-b141-2dddd36233ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27598
79740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.2759879740
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.2859446370
Short name T897
Test name
Test status
Simulation time 13590126593 ps
CPU time 18.89 seconds
Started Jun 05 05:48:13 PM PDT 24
Finished Jun 05 05:48:33 PM PDT 24
Peak memory 205704 kb
Host smart-e40086af-fda4-4360-bb90-ef24b50ad3e0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2859446370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.2859446370
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.4275338365
Short name T179
Test name
Test status
Simulation time 23361823339 ps
CPU time 24.34 seconds
Started Jun 05 05:48:11 PM PDT 24
Finished Jun 05 05:48:36 PM PDT 24
Peak memory 205764 kb
Host smart-611daa3d-bd87-4dc5-bb3d-81b3ca67cc3a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4275338365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.4275338365
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.1683244110
Short name T1488
Test name
Test status
Simulation time 10053724281 ps
CPU time 15.61 seconds
Started Jun 05 05:48:11 PM PDT 24
Finished Jun 05 05:48:28 PM PDT 24
Peak memory 205652 kb
Host smart-35ec6665-57ec-464c-90ec-8d9be76bc588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16832
44110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.1683244110
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.1056052223
Short name T1548
Test name
Test status
Simulation time 10243512714 ps
CPU time 13.29 seconds
Started Jun 05 05:48:10 PM PDT 24
Finished Jun 05 05:48:25 PM PDT 24
Peak memory 205620 kb
Host smart-0ac8bd8e-d65f-450a-9d82-731f0afda2f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10560
52223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.1056052223
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.3642011408
Short name T229
Test name
Test status
Simulation time 10037993500 ps
CPU time 13.36 seconds
Started Jun 05 05:48:14 PM PDT 24
Finished Jun 05 05:48:29 PM PDT 24
Peak memory 205648 kb
Host smart-55bcd8c5-f4b9-4a46-9acf-6581ec233b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36420
11408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.3642011408
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.1142939459
Short name T672
Test name
Test status
Simulation time 10054770676 ps
CPU time 14.55 seconds
Started Jun 05 05:48:15 PM PDT 24
Finished Jun 05 05:48:31 PM PDT 24
Peak memory 205512 kb
Host smart-cfd351a9-4230-433c-adde-03cb53b266bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11429
39459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.1142939459
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.3830924210
Short name T1676
Test name
Test status
Simulation time 10815746377 ps
CPU time 14.57 seconds
Started Jun 05 05:48:11 PM PDT 24
Finished Jun 05 05:48:27 PM PDT 24
Peak memory 205652 kb
Host smart-ef067291-a10c-4bf3-8c7f-908c347daaa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38309
24210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.3830924210
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.3951692646
Short name T603
Test name
Test status
Simulation time 10190481105 ps
CPU time 17.42 seconds
Started Jun 05 05:48:11 PM PDT 24
Finished Jun 05 05:48:30 PM PDT 24
Peak memory 205728 kb
Host smart-4531e261-6850-47fe-91d2-9bb4650fbd96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39516
92646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.3951692646
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.883121787
Short name T1703
Test name
Test status
Simulation time 10126237954 ps
CPU time 13.18 seconds
Started Jun 05 05:48:10 PM PDT 24
Finished Jun 05 05:48:24 PM PDT 24
Peak memory 205676 kb
Host smart-3563519e-24c3-4259-8cfe-463c7972d59e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88312
1787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.883121787
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3323711546
Short name T550
Test name
Test status
Simulation time 10047827356 ps
CPU time 14.47 seconds
Started Jun 05 05:48:11 PM PDT 24
Finished Jun 05 05:48:27 PM PDT 24
Peak memory 205636 kb
Host smart-60b71976-3cc4-4ee8-ade1-aebd74990f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33237
11546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3323711546
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.885795227
Short name T1651
Test name
Test status
Simulation time 10136167459 ps
CPU time 12.88 seconds
Started Jun 05 05:48:11 PM PDT 24
Finished Jun 05 05:48:25 PM PDT 24
Peak memory 205700 kb
Host smart-d2f0c6a8-7f9f-4581-a4af-cd9917155ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88579
5227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.885795227
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.3743374225
Short name T744
Test name
Test status
Simulation time 10125219683 ps
CPU time 13.87 seconds
Started Jun 05 05:48:16 PM PDT 24
Finished Jun 05 05:48:31 PM PDT 24
Peak memory 205616 kb
Host smart-454276bd-7077-44c2-b592-3c2896f4a3f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37433
74225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.3743374225
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.1052327062
Short name T1233
Test name
Test status
Simulation time 13249323354 ps
CPU time 17.05 seconds
Started Jun 05 05:48:11 PM PDT 24
Finished Jun 05 05:48:29 PM PDT 24
Peak memory 205652 kb
Host smart-9ee07805-0f93-4c55-81ed-2d800bf49901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10523
27062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.1052327062
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.653828868
Short name T572
Test name
Test status
Simulation time 10093955813 ps
CPU time 14.81 seconds
Started Jun 05 05:48:14 PM PDT 24
Finished Jun 05 05:48:31 PM PDT 24
Peak memory 205656 kb
Host smart-05b409a5-d890-4baf-be9b-ebbbfbcf4c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65382
8868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.653828868
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.918556906
Short name T1633
Test name
Test status
Simulation time 21545603990 ps
CPU time 331.38 seconds
Started Jun 05 05:48:15 PM PDT 24
Finished Jun 05 05:53:47 PM PDT 24
Peak memory 205660 kb
Host smart-0b414960-ca17-45a7-9013-6b37637fb1fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91855
6906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.918556906
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.1701400472
Short name T969
Test name
Test status
Simulation time 10077289718 ps
CPU time 15.45 seconds
Started Jun 05 05:48:13 PM PDT 24
Finished Jun 05 05:48:30 PM PDT 24
Peak memory 205748 kb
Host smart-fe4845dc-f934-4e46-972f-3133cbb9b507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17014
00472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.1701400472
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.3341745683
Short name T113
Test name
Test status
Simulation time 10083715298 ps
CPU time 12.5 seconds
Started Jun 05 05:48:13 PM PDT 24
Finished Jun 05 05:48:26 PM PDT 24
Peak memory 205764 kb
Host smart-0d39c784-f835-4ab1-83c2-38e14505cc82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33417
45683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.3341745683
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.1453063043
Short name T1894
Test name
Test status
Simulation time 10096887871 ps
CPU time 14.03 seconds
Started Jun 05 05:48:12 PM PDT 24
Finished Jun 05 05:48:28 PM PDT 24
Peak memory 205652 kb
Host smart-3557c30f-1445-4bfc-b468-b21af3fcb174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14530
63043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.1453063043
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.3981996130
Short name T1501
Test name
Test status
Simulation time 10088671322 ps
CPU time 16.63 seconds
Started Jun 05 05:48:11 PM PDT 24
Finished Jun 05 05:48:28 PM PDT 24
Peak memory 205656 kb
Host smart-e6bc2c67-f45f-4b05-8a95-529d82f58f9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39819
96130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3981996130
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.3217456945
Short name T665
Test name
Test status
Simulation time 10103593493 ps
CPU time 13 seconds
Started Jun 05 05:48:12 PM PDT 24
Finished Jun 05 05:48:27 PM PDT 24
Peak memory 205648 kb
Host smart-6efd0563-a2eb-4422-8454-47844a4ee3d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32174
56945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.3217456945
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2320607948
Short name T1281
Test name
Test status
Simulation time 10073326931 ps
CPU time 12.85 seconds
Started Jun 05 05:48:14 PM PDT 24
Finished Jun 05 05:48:29 PM PDT 24
Peak memory 205704 kb
Host smart-dbda3b38-097f-4720-a063-c0b1d56bc72e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23206
07948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2320607948
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_eop_single_bit_handling.3185298516
Short name T361
Test name
Test status
Simulation time 10090898196 ps
CPU time 14.66 seconds
Started Jun 05 05:48:12 PM PDT 24
Finished Jun 05 05:48:28 PM PDT 24
Peak memory 205708 kb
Host smart-15e2669c-a064-4fd9-af2c-8f66eaed7175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31852
98516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_eop_single_bit_handling.3185298516
Directory /workspace/34.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.1455211142
Short name T570
Test name
Test status
Simulation time 10051911784 ps
CPU time 14.86 seconds
Started Jun 05 05:48:19 PM PDT 24
Finished Jun 05 05:48:35 PM PDT 24
Peak memory 205780 kb
Host smart-388144d0-22b5-4572-89a2-2a946e9b3a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14552
11142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.1455211142
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.1521139427
Short name T1103
Test name
Test status
Simulation time 10089925257 ps
CPU time 13.88 seconds
Started Jun 05 05:48:12 PM PDT 24
Finished Jun 05 05:48:27 PM PDT 24
Peak memory 205680 kb
Host smart-c3f0f984-16e6-41d8-98b2-a5046e1857fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15211
39427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.1521139427
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.3001512157
Short name T170
Test name
Test status
Simulation time 21767830068 ps
CPU time 40.85 seconds
Started Jun 05 05:48:14 PM PDT 24
Finished Jun 05 05:48:56 PM PDT 24
Peak memory 205676 kb
Host smart-5c01d343-57a2-46d9-b162-8fee53f752f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30015
12157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.3001512157
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.1879235057
Short name T416
Test name
Test status
Simulation time 10074653932 ps
CPU time 14.23 seconds
Started Jun 05 05:48:14 PM PDT 24
Finished Jun 05 05:48:30 PM PDT 24
Peak memory 205712 kb
Host smart-7f999c18-3f0f-4a4f-bf69-c381b49148e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18792
35057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.1879235057
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.4079968593
Short name T675
Test name
Test status
Simulation time 10101261792 ps
CPU time 15.12 seconds
Started Jun 05 05:48:10 PM PDT 24
Finished Jun 05 05:48:26 PM PDT 24
Peak memory 205708 kb
Host smart-161f454d-01c4-4bc5-8b98-4cde177cd5ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40799
68593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.4079968593
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.1257337498
Short name T310
Test name
Test status
Simulation time 10145587996 ps
CPU time 15.52 seconds
Started Jun 05 05:48:13 PM PDT 24
Finished Jun 05 05:48:30 PM PDT 24
Peak memory 205632 kb
Host smart-062b4f52-15d5-493c-8c1a-b718c709c613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12573
37498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.1257337498
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.1958636277
Short name T1772
Test name
Test status
Simulation time 10060051020 ps
CPU time 13.45 seconds
Started Jun 05 05:48:14 PM PDT 24
Finished Jun 05 05:48:29 PM PDT 24
Peak memory 205760 kb
Host smart-b5a93c6e-8d6c-4409-b484-df981fb37b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19586
36277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.1958636277
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.1531849180
Short name T938
Test name
Test status
Simulation time 10091187997 ps
CPU time 12.64 seconds
Started Jun 05 05:48:13 PM PDT 24
Finished Jun 05 05:48:27 PM PDT 24
Peak memory 205660 kb
Host smart-f0ce6a03-9a7d-4a6e-9388-3f01af04b291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15318
49180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.1531849180
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1014400505
Short name T874
Test name
Test status
Simulation time 10058337788 ps
CPU time 13.56 seconds
Started Jun 05 05:48:14 PM PDT 24
Finished Jun 05 05:48:29 PM PDT 24
Peak memory 205636 kb
Host smart-8677d011-ec4c-47b5-89b5-2b3579af4eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10144
00505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1014400505
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2681280536
Short name T132
Test name
Test status
Simulation time 10118437660 ps
CPU time 16.76 seconds
Started Jun 05 05:48:11 PM PDT 24
Finished Jun 05 05:48:29 PM PDT 24
Peak memory 205776 kb
Host smart-aa13704c-d81b-4f96-aded-7841dc2a2e27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26812
80536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2681280536
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.3918410966
Short name T2002
Test name
Test status
Simulation time 10100748654 ps
CPU time 13.14 seconds
Started Jun 05 05:48:15 PM PDT 24
Finished Jun 05 05:48:29 PM PDT 24
Peak memory 205748 kb
Host smart-c3cc4dc7-7e23-42ee-b285-8d35c2d180dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39184
10966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.3918410966
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.3200733778
Short name T1229
Test name
Test status
Simulation time 10154014739 ps
CPU time 13.51 seconds
Started Jun 05 05:48:14 PM PDT 24
Finished Jun 05 05:48:28 PM PDT 24
Peak memory 205620 kb
Host smart-1b23295a-520f-42ef-a67f-d92a08a2e1ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32007
33778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.3200733778
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.1007178539
Short name T474
Test name
Test status
Simulation time 18154547649 ps
CPU time 240.97 seconds
Started Jun 05 05:48:17 PM PDT 24
Finished Jun 05 05:52:19 PM PDT 24
Peak memory 205652 kb
Host smart-403ab65e-8e62-4608-8750-c43cc9afe970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10071
78539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.1007178539
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.2848397191
Short name T457
Test name
Test status
Simulation time 10139165912 ps
CPU time 13.69 seconds
Started Jun 05 05:48:22 PM PDT 24
Finished Jun 05 05:48:36 PM PDT 24
Peak memory 205740 kb
Host smart-75eaf2d7-bdef-4cb1-8296-d85c8f2f9430
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2848397191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.2848397191
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.3807721439
Short name T750
Test name
Test status
Simulation time 10065719139 ps
CPU time 12.89 seconds
Started Jun 05 05:48:22 PM PDT 24
Finished Jun 05 05:48:36 PM PDT 24
Peak memory 205748 kb
Host smart-b9ddfbbd-cdee-4dbf-aed2-a10a34dca79b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3807721439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.3807721439
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.3386983332
Short name T439
Test name
Test status
Simulation time 10128230004 ps
CPU time 13.01 seconds
Started Jun 05 05:48:19 PM PDT 24
Finished Jun 05 05:48:33 PM PDT 24
Peak memory 205760 kb
Host smart-bf241273-70e4-4d8f-80ac-56115939c06a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33869
83332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.3386983332
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.683887597
Short name T495
Test name
Test status
Simulation time 13935320236 ps
CPU time 17.16 seconds
Started Jun 05 05:48:14 PM PDT 24
Finished Jun 05 05:48:33 PM PDT 24
Peak memory 205716 kb
Host smart-42a4ff39-fe28-4227-b2ef-a15a76a163b0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=683887597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.683887597
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.952416923
Short name T1178
Test name
Test status
Simulation time 23265268070 ps
CPU time 24.21 seconds
Started Jun 05 05:48:11 PM PDT 24
Finished Jun 05 05:48:37 PM PDT 24
Peak memory 205784 kb
Host smart-c580122f-26a1-4f87-b543-1939a64305e1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=952416923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.952416923
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.2103345721
Short name T1066
Test name
Test status
Simulation time 10047520246 ps
CPU time 13.43 seconds
Started Jun 05 05:48:09 PM PDT 24
Finished Jun 05 05:48:23 PM PDT 24
Peak memory 205736 kb
Host smart-03a9251d-5f10-415a-a317-79404e8db494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21033
45721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2103345721
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.2735260528
Short name T890
Test name
Test status
Simulation time 10255645284 ps
CPU time 15.68 seconds
Started Jun 05 05:48:12 PM PDT 24
Finished Jun 05 05:48:29 PM PDT 24
Peak memory 205748 kb
Host smart-1ce414da-cb97-45f6-8c8f-404a6da89b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27352
60528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.2735260528
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.4212602734
Short name T45
Test name
Test status
Simulation time 10063629789 ps
CPU time 14.14 seconds
Started Jun 05 05:48:21 PM PDT 24
Finished Jun 05 05:48:36 PM PDT 24
Peak memory 205644 kb
Host smart-c80f0652-5285-40e3-a3ee-62ca9d44099e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42126
02734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.4212602734
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.1069020357
Short name T1452
Test name
Test status
Simulation time 10061780675 ps
CPU time 13.31 seconds
Started Jun 05 05:48:18 PM PDT 24
Finished Jun 05 05:48:33 PM PDT 24
Peak memory 205696 kb
Host smart-8513a8af-ac4f-45c8-8951-1cbdd6010a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10690
20357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.1069020357
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.3193393040
Short name T390
Test name
Test status
Simulation time 10952226717 ps
CPU time 15.86 seconds
Started Jun 05 05:48:17 PM PDT 24
Finished Jun 05 05:48:34 PM PDT 24
Peak memory 205700 kb
Host smart-e0e9f055-25bb-44b7-8605-daa8be98cd66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31933
93040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.3193393040
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.3145117411
Short name T423
Test name
Test status
Simulation time 10080597099 ps
CPU time 16.59 seconds
Started Jun 05 05:48:13 PM PDT 24
Finished Jun 05 05:48:31 PM PDT 24
Peak memory 205644 kb
Host smart-add1d04b-330c-4db6-b9fa-df6ccbb88d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31451
17411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.3145117411
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.814181561
Short name T574
Test name
Test status
Simulation time 10134952969 ps
CPU time 13.06 seconds
Started Jun 05 05:48:19 PM PDT 24
Finished Jun 05 05:48:33 PM PDT 24
Peak memory 205784 kb
Host smart-1d050928-430e-4b2a-8f35-2bac8dea602d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81418
1561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.814181561
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.53591408
Short name T69
Test name
Test status
Simulation time 10058966015 ps
CPU time 13.5 seconds
Started Jun 05 05:48:20 PM PDT 24
Finished Jun 05 05:48:34 PM PDT 24
Peak memory 205732 kb
Host smart-1c8f5b34-6a0c-4d9f-bb28-30ce7b29866c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53591
408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.53591408
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.1207031217
Short name T358
Test name
Test status
Simulation time 10080883498 ps
CPU time 15.79 seconds
Started Jun 05 05:48:20 PM PDT 24
Finished Jun 05 05:48:37 PM PDT 24
Peak memory 205712 kb
Host smart-0787f7b6-cc86-4abd-b90d-22027367445e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12070
31217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.1207031217
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.4285876213
Short name T1248
Test name
Test status
Simulation time 10100820478 ps
CPU time 12.97 seconds
Started Jun 05 05:48:18 PM PDT 24
Finished Jun 05 05:48:32 PM PDT 24
Peak memory 205616 kb
Host smart-204d51bb-cc25-461a-8e74-00d384a6f6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42858
76213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.4285876213
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.3653436083
Short name T649
Test name
Test status
Simulation time 13186188865 ps
CPU time 15.3 seconds
Started Jun 05 05:48:17 PM PDT 24
Finished Jun 05 05:48:33 PM PDT 24
Peak memory 205700 kb
Host smart-5ae64cdd-e84a-4249-a7f5-3dd06c4c3029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36534
36083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.3653436083
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.498432149
Short name T1119
Test name
Test status
Simulation time 10113047145 ps
CPU time 13.91 seconds
Started Jun 05 05:48:17 PM PDT 24
Finished Jun 05 05:48:32 PM PDT 24
Peak memory 205716 kb
Host smart-25d25c22-38ee-4df3-91ab-0909193fd5d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49843
2149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.498432149
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.789972618
Short name T403
Test name
Test status
Simulation time 19639401831 ps
CPU time 78.3 seconds
Started Jun 05 05:48:23 PM PDT 24
Finished Jun 05 05:49:42 PM PDT 24
Peak memory 205676 kb
Host smart-d503f7aa-ce92-4f57-b18b-07da72aed2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78997
2618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.789972618
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.3580507965
Short name T299
Test name
Test status
Simulation time 10064288845 ps
CPU time 12.3 seconds
Started Jun 05 05:48:18 PM PDT 24
Finished Jun 05 05:48:32 PM PDT 24
Peak memory 205712 kb
Host smart-4461e370-152d-460f-98e8-2315142b5cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35805
07965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.3580507965
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.4204961829
Short name T1130
Test name
Test status
Simulation time 10096883094 ps
CPU time 13.29 seconds
Started Jun 05 05:48:20 PM PDT 24
Finished Jun 05 05:48:34 PM PDT 24
Peak memory 205764 kb
Host smart-c8d930c2-52ff-4667-8ecd-447ac48bdbd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42049
61829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.4204961829
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.776932970
Short name T1246
Test name
Test status
Simulation time 10097863566 ps
CPU time 13.54 seconds
Started Jun 05 05:48:20 PM PDT 24
Finished Jun 05 05:48:34 PM PDT 24
Peak memory 205888 kb
Host smart-3cd9fd93-8b21-4e1c-bafc-7a1e33543535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77693
2970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.776932970
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.2338152045
Short name T1643
Test name
Test status
Simulation time 10105914211 ps
CPU time 13.42 seconds
Started Jun 05 05:48:20 PM PDT 24
Finished Jun 05 05:48:35 PM PDT 24
Peak memory 205760 kb
Host smart-8213ab9c-9347-44a0-8516-af66dc498126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23381
52045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.2338152045
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.2259093239
Short name T1880
Test name
Test status
Simulation time 10060971023 ps
CPU time 14.91 seconds
Started Jun 05 05:48:21 PM PDT 24
Finished Jun 05 05:48:37 PM PDT 24
Peak memory 205952 kb
Host smart-b4b2cba4-8a75-4239-a695-589976610f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22590
93239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.2259093239
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.4034883347
Short name T146
Test name
Test status
Simulation time 10076777288 ps
CPU time 15.06 seconds
Started Jun 05 05:48:20 PM PDT 24
Finished Jun 05 05:48:36 PM PDT 24
Peak memory 205756 kb
Host smart-7fa28d59-37c5-4a0d-aa34-843535fe1e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40348
83347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.4034883347
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_eop_single_bit_handling.2614512506
Short name T1771
Test name
Test status
Simulation time 10082982283 ps
CPU time 14.56 seconds
Started Jun 05 05:48:16 PM PDT 24
Finished Jun 05 05:48:32 PM PDT 24
Peak memory 205732 kb
Host smart-66049580-457d-4013-9460-9793220c18b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26145
12506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_eop_single_bit_handling.2614512506
Directory /workspace/35.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.461803876
Short name T484
Test name
Test status
Simulation time 10038336165 ps
CPU time 14.54 seconds
Started Jun 05 05:48:18 PM PDT 24
Finished Jun 05 05:48:33 PM PDT 24
Peak memory 205684 kb
Host smart-fe364237-174f-4905-a3dc-762672f5d349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46180
3876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.461803876
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.4274071680
Short name T1762
Test name
Test status
Simulation time 10038632333 ps
CPU time 16.99 seconds
Started Jun 05 05:48:20 PM PDT 24
Finished Jun 05 05:48:38 PM PDT 24
Peak memory 205676 kb
Host smart-cbc4b7bf-f707-40a5-b08c-0505f0999129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42740
71680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.4274071680
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.943168789
Short name T1350
Test name
Test status
Simulation time 29022665919 ps
CPU time 57.18 seconds
Started Jun 05 05:48:17 PM PDT 24
Finished Jun 05 05:49:15 PM PDT 24
Peak memory 205656 kb
Host smart-b97a335c-f909-44fc-84f7-2592313697a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94316
8789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.943168789
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.4026566374
Short name T810
Test name
Test status
Simulation time 10102447171 ps
CPU time 14.9 seconds
Started Jun 05 05:48:19 PM PDT 24
Finished Jun 05 05:48:35 PM PDT 24
Peak memory 205900 kb
Host smart-a1b34a29-8f3e-4f91-a859-574f8b7aa2fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40265
66374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.4026566374
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2702598465
Short name T1922
Test name
Test status
Simulation time 10121869741 ps
CPU time 14.15 seconds
Started Jun 05 05:48:21 PM PDT 24
Finished Jun 05 05:48:35 PM PDT 24
Peak memory 205668 kb
Host smart-59365545-78e5-4fd4-9921-3d5741e8eed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27025
98465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2702598465
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.88344718
Short name T1227
Test name
Test status
Simulation time 10083019722 ps
CPU time 14.17 seconds
Started Jun 05 05:48:20 PM PDT 24
Finished Jun 05 05:48:35 PM PDT 24
Peak memory 205640 kb
Host smart-4baf0cf0-54c1-47fd-bf4b-83791d25be62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88344
718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.88344718
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.4027247471
Short name T942
Test name
Test status
Simulation time 10037210410 ps
CPU time 16.17 seconds
Started Jun 05 05:48:19 PM PDT 24
Finished Jun 05 05:48:37 PM PDT 24
Peak memory 205792 kb
Host smart-960ba2ae-c314-439b-bbf8-755340ff5c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40272
47471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.4027247471
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.1761022993
Short name T140
Test name
Test status
Simulation time 10090731603 ps
CPU time 13.66 seconds
Started Jun 05 05:48:20 PM PDT 24
Finished Jun 05 05:48:35 PM PDT 24
Peak memory 205640 kb
Host smart-78281594-fcc6-43f7-8308-d221a1b574db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17610
22993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.1761022993
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1615067344
Short name T832
Test name
Test status
Simulation time 10050143702 ps
CPU time 12.27 seconds
Started Jun 05 05:48:18 PM PDT 24
Finished Jun 05 05:48:32 PM PDT 24
Peak memory 205684 kb
Host smart-7fbbd8a0-4ab8-4e3e-afe3-a6a6736af7fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16150
67344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1615067344
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.1796341259
Short name T661
Test name
Test status
Simulation time 10121856267 ps
CPU time 12.85 seconds
Started Jun 05 05:48:16 PM PDT 24
Finished Jun 05 05:48:30 PM PDT 24
Peak memory 205732 kb
Host smart-ef072fb2-f549-48bf-b74d-17f8dab2deda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17963
41259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.1796341259
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.2060886521
Short name T1926
Test name
Test status
Simulation time 10135463713 ps
CPU time 13.72 seconds
Started Jun 05 05:48:26 PM PDT 24
Finished Jun 05 05:48:41 PM PDT 24
Peak memory 205796 kb
Host smart-78c02c76-8bc7-482c-8003-4b412e8d457a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20608
86521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.2060886521
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.2603579473
Short name T743
Test name
Test status
Simulation time 10064314733 ps
CPU time 13.12 seconds
Started Jun 05 05:48:18 PM PDT 24
Finished Jun 05 05:48:32 PM PDT 24
Peak memory 205652 kb
Host smart-44782d70-d42d-4dbb-9081-1af79dd026a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26035
79473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.2603579473
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.2799249253
Short name T752
Test name
Test status
Simulation time 22238706312 ps
CPU time 106.15 seconds
Started Jun 05 05:48:19 PM PDT 24
Finished Jun 05 05:50:06 PM PDT 24
Peak memory 205700 kb
Host smart-feefed8c-877e-4e38-a80c-82233e049445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27992
49253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.2799249253
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.4022721455
Short name T367
Test name
Test status
Simulation time 10170956450 ps
CPU time 13.56 seconds
Started Jun 05 05:48:31 PM PDT 24
Finished Jun 05 05:48:45 PM PDT 24
Peak memory 205744 kb
Host smart-7155de75-b37b-4183-8cb9-0066dc605733
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4022721455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.4022721455
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.276452560
Short name T1232
Test name
Test status
Simulation time 10072526222 ps
CPU time 14.82 seconds
Started Jun 05 05:48:28 PM PDT 24
Finished Jun 05 05:48:44 PM PDT 24
Peak memory 205712 kb
Host smart-aad65daf-730b-4ad8-9bce-4ff322c0bbf3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=276452560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.276452560
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.2304438262
Short name T1214
Test name
Test status
Simulation time 10068676285 ps
CPU time 13.63 seconds
Started Jun 05 05:48:34 PM PDT 24
Finished Jun 05 05:48:49 PM PDT 24
Peak memory 205964 kb
Host smart-3fd204de-f0ff-4daa-877c-3b289d0c9392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23044
38262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.2304438262
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.769436065
Short name T1949
Test name
Test status
Simulation time 13872619208 ps
CPU time 17 seconds
Started Jun 05 05:48:19 PM PDT 24
Finished Jun 05 05:48:37 PM PDT 24
Peak memory 205732 kb
Host smart-2d614ed4-039f-4cb3-9dd4-ef074b13324a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=769436065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.769436065
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.650588431
Short name T1764
Test name
Test status
Simulation time 23299138680 ps
CPU time 31.62 seconds
Started Jun 05 05:48:32 PM PDT 24
Finished Jun 05 05:49:04 PM PDT 24
Peak memory 205740 kb
Host smart-5a2b8414-e03c-4795-8157-f2d9d0f9236a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=650588431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.650588431
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1229175155
Short name T1347
Test name
Test status
Simulation time 10052392001 ps
CPU time 12.82 seconds
Started Jun 05 05:48:23 PM PDT 24
Finished Jun 05 05:48:36 PM PDT 24
Peak memory 205652 kb
Host smart-c2438163-22ea-4239-8b90-e99c1ad812a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12291
75155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1229175155
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.4210542935
Short name T57
Test name
Test status
Simulation time 10105097853 ps
CPU time 13.14 seconds
Started Jun 05 05:48:18 PM PDT 24
Finished Jun 05 05:48:33 PM PDT 24
Peak memory 205932 kb
Host smart-9d772b68-4bb4-4aad-be0b-73c85aacb330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42105
42935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.4210542935
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.1720289614
Short name T1654
Test name
Test status
Simulation time 10051176147 ps
CPU time 14.56 seconds
Started Jun 05 05:48:24 PM PDT 24
Finished Jun 05 05:48:39 PM PDT 24
Peak memory 205644 kb
Host smart-5292ec6d-78b5-4bdb-9475-aee76b32fafc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17202
89614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.1720289614
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.269362049
Short name T1185
Test name
Test status
Simulation time 10128399786 ps
CPU time 14.43 seconds
Started Jun 05 05:48:24 PM PDT 24
Finished Jun 05 05:48:39 PM PDT 24
Peak memory 205568 kb
Host smart-887333ad-573d-4512-a5ce-09db2b733c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26936
2049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.269362049
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.3288154670
Short name T1644
Test name
Test status
Simulation time 10804188991 ps
CPU time 14.04 seconds
Started Jun 05 05:48:21 PM PDT 24
Finished Jun 05 05:48:36 PM PDT 24
Peak memory 205688 kb
Host smart-306e2cd2-0e8e-4fe7-b8f2-2abff40cbd01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32881
54670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.3288154670
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1546392142
Short name T1179
Test name
Test status
Simulation time 10148735936 ps
CPU time 14.53 seconds
Started Jun 05 05:48:17 PM PDT 24
Finished Jun 05 05:48:32 PM PDT 24
Peak memory 205728 kb
Host smart-fd016fac-b57e-4bea-b3e6-5105dc8ae4e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15463
92142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1546392142
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.1281755924
Short name T877
Test name
Test status
Simulation time 10121264037 ps
CPU time 16.82 seconds
Started Jun 05 05:48:30 PM PDT 24
Finished Jun 05 05:48:47 PM PDT 24
Peak memory 205756 kb
Host smart-31dfea8b-7202-4457-8baa-4f06d0774f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12817
55924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.1281755924
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.4183645353
Short name T983
Test name
Test status
Simulation time 10036551733 ps
CPU time 13.38 seconds
Started Jun 05 05:48:37 PM PDT 24
Finished Jun 05 05:48:51 PM PDT 24
Peak memory 205680 kb
Host smart-46496366-fa36-44d0-b1d1-8d33ab4d7cc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41836
45353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.4183645353
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.3881679589
Short name T1336
Test name
Test status
Simulation time 10077524237 ps
CPU time 14.07 seconds
Started Jun 05 05:48:21 PM PDT 24
Finished Jun 05 05:48:36 PM PDT 24
Peak memory 205944 kb
Host smart-0c9c9087-5df2-4505-98f3-7d14a74d1e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38816
79589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.3881679589
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.452912760
Short name T1546
Test name
Test status
Simulation time 10147820493 ps
CPU time 13.53 seconds
Started Jun 05 05:48:23 PM PDT 24
Finished Jun 05 05:48:37 PM PDT 24
Peak memory 205652 kb
Host smart-55199658-d460-469f-826b-eb127bb978a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45291
2760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.452912760
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.2279765532
Short name T306
Test name
Test status
Simulation time 13204028585 ps
CPU time 18.06 seconds
Started Jun 05 05:48:24 PM PDT 24
Finished Jun 05 05:48:43 PM PDT 24
Peak memory 205740 kb
Host smart-901272a2-5ab9-4185-98d0-d637c6a235df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22797
65532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.2279765532
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2399337040
Short name T925
Test name
Test status
Simulation time 10086548107 ps
CPU time 13.06 seconds
Started Jun 05 05:48:25 PM PDT 24
Finished Jun 05 05:48:38 PM PDT 24
Peak memory 205744 kb
Host smart-36a3812d-f081-4f25-9cca-4bad4e08706a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23993
37040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2399337040
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.1753580958
Short name T394
Test name
Test status
Simulation time 13838182833 ps
CPU time 40.4 seconds
Started Jun 05 05:48:23 PM PDT 24
Finished Jun 05 05:49:03 PM PDT 24
Peak memory 205708 kb
Host smart-9b9a4e88-a92f-4569-9146-b994771dcadb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17535
80958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.1753580958
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3569794926
Short name T576
Test name
Test status
Simulation time 10046711194 ps
CPU time 13.77 seconds
Started Jun 05 05:48:21 PM PDT 24
Finished Jun 05 05:48:35 PM PDT 24
Peak memory 205920 kb
Host smart-46830d6e-e143-42be-b551-c605664d26ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35697
94926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3569794926
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.3050472702
Short name T104
Test name
Test status
Simulation time 10107956817 ps
CPU time 15.62 seconds
Started Jun 05 05:48:26 PM PDT 24
Finished Jun 05 05:48:43 PM PDT 24
Peak memory 205784 kb
Host smart-94680ee1-860d-4ea1-b6a8-1381c768ff07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30504
72702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.3050472702
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3497404102
Short name T1276
Test name
Test status
Simulation time 10091467233 ps
CPU time 14.09 seconds
Started Jun 05 05:48:24 PM PDT 24
Finished Jun 05 05:48:38 PM PDT 24
Peak memory 205772 kb
Host smart-a651d320-f4b8-4e0b-976c-993437556e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34974
04102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3497404102
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3309290366
Short name T291
Test name
Test status
Simulation time 10088071421 ps
CPU time 13.47 seconds
Started Jun 05 05:48:24 PM PDT 24
Finished Jun 05 05:48:38 PM PDT 24
Peak memory 205796 kb
Host smart-2d4e0469-4255-4572-9ddd-acb8ce64a37b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33092
90366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3309290366
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.3241235062
Short name T1571
Test name
Test status
Simulation time 10079109031 ps
CPU time 16.42 seconds
Started Jun 05 05:48:21 PM PDT 24
Finished Jun 05 05:48:38 PM PDT 24
Peak memory 205684 kb
Host smart-5042213a-94d5-42c5-a6eb-2d36fe5b8eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32412
35062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.3241235062
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.3148333448
Short name T169
Test name
Test status
Simulation time 10040433111 ps
CPU time 15.63 seconds
Started Jun 05 05:48:26 PM PDT 24
Finished Jun 05 05:48:42 PM PDT 24
Peak memory 205684 kb
Host smart-1acfd5a0-872e-4113-895f-5cfe60991fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31483
33448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.3148333448
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_eop_single_bit_handling.438142416
Short name T330
Test name
Test status
Simulation time 10068882450 ps
CPU time 12.83 seconds
Started Jun 05 05:48:26 PM PDT 24
Finished Jun 05 05:48:39 PM PDT 24
Peak memory 205656 kb
Host smart-3850ab58-4f4a-4913-9fa8-ff03c3a25ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43814
2416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_eop_single_bit_handling.438142416
Directory /workspace/36.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3519928478
Short name T1102
Test name
Test status
Simulation time 10075517586 ps
CPU time 13.79 seconds
Started Jun 05 05:48:32 PM PDT 24
Finished Jun 05 05:48:46 PM PDT 24
Peak memory 205796 kb
Host smart-8a92b47c-4251-4826-9468-dc1b579c4234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35199
28478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3519928478
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.606002153
Short name T25
Test name
Test status
Simulation time 10042864117 ps
CPU time 14.69 seconds
Started Jun 05 05:48:26 PM PDT 24
Finished Jun 05 05:48:41 PM PDT 24
Peak memory 205716 kb
Host smart-8c69f859-5762-46f1-9d36-c7d8d2104101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60600
2153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.606002153
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.567213100
Short name T2009
Test name
Test status
Simulation time 23184739567 ps
CPU time 47.58 seconds
Started Jun 05 05:48:25 PM PDT 24
Finished Jun 05 05:49:13 PM PDT 24
Peak memory 205696 kb
Host smart-c8746664-9eb3-4a07-9287-9e0a015236fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56721
3100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.567213100
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.2308952372
Short name T616
Test name
Test status
Simulation time 10055970797 ps
CPU time 14.06 seconds
Started Jun 05 05:48:22 PM PDT 24
Finished Jun 05 05:48:37 PM PDT 24
Peak memory 205848 kb
Host smart-99cbaa37-5d62-4349-858d-9876f063fa5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23089
52372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2308952372
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3456040063
Short name T1183
Test name
Test status
Simulation time 10131976338 ps
CPU time 13.27 seconds
Started Jun 05 05:48:25 PM PDT 24
Finished Jun 05 05:48:38 PM PDT 24
Peak memory 205748 kb
Host smart-e1f067d0-5770-49f3-bea9-42bdde77d24c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34560
40063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3456040063
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.1403430535
Short name T663
Test name
Test status
Simulation time 10062683893 ps
CPU time 16.4 seconds
Started Jun 05 05:48:34 PM PDT 24
Finished Jun 05 05:48:51 PM PDT 24
Peak memory 205720 kb
Host smart-7e691c2c-6339-4854-a47d-89e0389022a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14034
30535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.1403430535
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.778496241
Short name T1094
Test name
Test status
Simulation time 10041591112 ps
CPU time 15.71 seconds
Started Jun 05 05:48:30 PM PDT 24
Finished Jun 05 05:48:46 PM PDT 24
Peak memory 205764 kb
Host smart-833dda29-fbed-4a68-85d4-ff1d34e05844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77849
6241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.778496241
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.1073806661
Short name T125
Test name
Test status
Simulation time 10051120705 ps
CPU time 13.03 seconds
Started Jun 05 05:48:39 PM PDT 24
Finished Jun 05 05:48:52 PM PDT 24
Peak memory 205740 kb
Host smart-4c06bee8-ef44-497e-bfca-074e3cebab96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10738
06661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1073806661
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1812165774
Short name T1082
Test name
Test status
Simulation time 10044873113 ps
CPU time 13.97 seconds
Started Jun 05 05:48:30 PM PDT 24
Finished Jun 05 05:48:45 PM PDT 24
Peak memory 205768 kb
Host smart-f687b327-78be-4f53-912f-89f900fdb1f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18121
65774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1812165774
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.2263778732
Short name T1381
Test name
Test status
Simulation time 10123463851 ps
CPU time 15.93 seconds
Started Jun 05 05:48:21 PM PDT 24
Finished Jun 05 05:48:37 PM PDT 24
Peak memory 205696 kb
Host smart-6089ca29-255c-4261-bb67-03b7dbdd6ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22637
78732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2263778732
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.1791422471
Short name T1849
Test name
Test status
Simulation time 10066658976 ps
CPU time 13.72 seconds
Started Jun 05 05:48:38 PM PDT 24
Finished Jun 05 05:48:52 PM PDT 24
Peak memory 205812 kb
Host smart-92e95696-8ba8-43bb-8fe0-75207e5f11b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17914
22471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.1791422471
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.31793589
Short name T851
Test name
Test status
Simulation time 10086442168 ps
CPU time 14.36 seconds
Started Jun 05 05:48:31 PM PDT 24
Finished Jun 05 05:48:46 PM PDT 24
Peak memory 205764 kb
Host smart-3e48b589-d3fb-4135-8de2-57f63426e4f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31793
589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.31793589
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.2993384910
Short name T301
Test name
Test status
Simulation time 16084696084 ps
CPU time 57.97 seconds
Started Jun 05 05:48:26 PM PDT 24
Finished Jun 05 05:49:25 PM PDT 24
Peak memory 205640 kb
Host smart-4d1820ab-f9d5-460d-8fb0-c002c1f223a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29933
84910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.2993384910
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.3428541858
Short name T1274
Test name
Test status
Simulation time 10154152503 ps
CPU time 13.3 seconds
Started Jun 05 05:48:35 PM PDT 24
Finished Jun 05 05:48:49 PM PDT 24
Peak memory 205776 kb
Host smart-4cd02b47-311f-4a2c-a2d3-5a195c9ea456
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3428541858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.3428541858
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.2919148657
Short name T359
Test name
Test status
Simulation time 10052588452 ps
CPU time 14.67 seconds
Started Jun 05 05:48:40 PM PDT 24
Finished Jun 05 05:48:56 PM PDT 24
Peak memory 205580 kb
Host smart-7a3a042a-af28-4d12-a57f-3c31137f3ca1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2919148657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.2919148657
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.3879837142
Short name T2036
Test name
Test status
Simulation time 10134672893 ps
CPU time 13.43 seconds
Started Jun 05 05:48:35 PM PDT 24
Finished Jun 05 05:48:50 PM PDT 24
Peak memory 205636 kb
Host smart-6679da7f-460a-476f-a84f-83a25f74fe0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38798
37142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.3879837142
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.4149434729
Short name T1396
Test name
Test status
Simulation time 13479358800 ps
CPU time 17.58 seconds
Started Jun 05 05:48:25 PM PDT 24
Finished Jun 05 05:48:43 PM PDT 24
Peak memory 205740 kb
Host smart-f400a8a6-45ff-4af7-ae09-23d33473d92f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4149434729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.4149434729
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.4178762276
Short name T1918
Test name
Test status
Simulation time 23334682552 ps
CPU time 24.85 seconds
Started Jun 05 05:48:26 PM PDT 24
Finished Jun 05 05:48:52 PM PDT 24
Peak memory 205668 kb
Host smart-68b39727-a751-4b9d-b541-d07cee8887ea
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4178762276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.4178762276
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3214456369
Short name T1046
Test name
Test status
Simulation time 10047733600 ps
CPU time 12.95 seconds
Started Jun 05 05:48:43 PM PDT 24
Finished Jun 05 05:48:57 PM PDT 24
Peak memory 205652 kb
Host smart-92748d98-40a8-44ab-923b-21e4cfbb9078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32144
56369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3214456369
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.3226224499
Short name T1120
Test name
Test status
Simulation time 10953871590 ps
CPU time 15.78 seconds
Started Jun 05 05:48:26 PM PDT 24
Finished Jun 05 05:48:42 PM PDT 24
Peak memory 205748 kb
Host smart-c9483b42-91f9-49a4-860e-0f805bbdb350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32262
24499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.3226224499
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.3368021593
Short name T1430
Test name
Test status
Simulation time 10049553512 ps
CPU time 12.84 seconds
Started Jun 05 05:48:29 PM PDT 24
Finished Jun 05 05:48:42 PM PDT 24
Peak memory 205760 kb
Host smart-d5992a5c-56ae-4835-b6f9-276c8edc3508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33680
21593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.3368021593
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.3909888072
Short name T561
Test name
Test status
Simulation time 10065236478 ps
CPU time 15.19 seconds
Started Jun 05 05:48:31 PM PDT 24
Finished Jun 05 05:48:47 PM PDT 24
Peak memory 205836 kb
Host smart-323f2541-58e5-4ad3-b024-b4210c80da8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39098
88072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.3909888072
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.3999493472
Short name T697
Test name
Test status
Simulation time 10666116161 ps
CPU time 15.58 seconds
Started Jun 05 05:48:33 PM PDT 24
Finished Jun 05 05:48:49 PM PDT 24
Peak memory 205696 kb
Host smart-3395906b-ff44-481c-83d3-2ba021e955ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39994
93472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.3999493472
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.1952478500
Short name T356
Test name
Test status
Simulation time 10290442487 ps
CPU time 15.22 seconds
Started Jun 05 05:48:31 PM PDT 24
Finished Jun 05 05:48:47 PM PDT 24
Peak memory 205724 kb
Host smart-d708561d-0ea9-4694-bfdb-fe15177e4987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19524
78500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.1952478500
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.1341482361
Short name T1987
Test name
Test status
Simulation time 10124693194 ps
CPU time 16.12 seconds
Started Jun 05 05:48:35 PM PDT 24
Finished Jun 05 05:48:52 PM PDT 24
Peak memory 205760 kb
Host smart-3dc699ac-e8f2-4696-9528-f7724fe9255e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13414
82361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.1341482361
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.2039892617
Short name T1991
Test name
Test status
Simulation time 10094634317 ps
CPU time 12.95 seconds
Started Jun 05 05:48:38 PM PDT 24
Finished Jun 05 05:48:51 PM PDT 24
Peak memory 205616 kb
Host smart-9cfebc0c-017b-47ab-a671-c3ef49d632cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20398
92617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.2039892617
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.922690211
Short name T412
Test name
Test status
Simulation time 10129875027 ps
CPU time 14.25 seconds
Started Jun 05 05:48:40 PM PDT 24
Finished Jun 05 05:48:55 PM PDT 24
Peak memory 205780 kb
Host smart-179f5f6b-311c-43af-bb43-91522695c390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92269
0211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.922690211
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.608677395
Short name T845
Test name
Test status
Simulation time 10105575714 ps
CPU time 13.85 seconds
Started Jun 05 05:48:33 PM PDT 24
Finished Jun 05 05:48:47 PM PDT 24
Peak memory 205664 kb
Host smart-e07e82af-0142-448f-b64d-5fd305a16b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60867
7395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.608677395
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.1010858294
Short name T346
Test name
Test status
Simulation time 13188950016 ps
CPU time 16.77 seconds
Started Jun 05 05:48:28 PM PDT 24
Finished Jun 05 05:48:46 PM PDT 24
Peak memory 205744 kb
Host smart-80911b93-3223-4b39-a903-8ec1d71c358b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10108
58294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.1010858294
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1591443309
Short name T1219
Test name
Test status
Simulation time 10120362429 ps
CPU time 12.72 seconds
Started Jun 05 05:48:41 PM PDT 24
Finished Jun 05 05:48:54 PM PDT 24
Peak memory 205688 kb
Host smart-8ea29fea-c14e-46cb-9dd9-2e29b52a89f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15914
43309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1591443309
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.1975558395
Short name T1673
Test name
Test status
Simulation time 23297069603 ps
CPU time 108.39 seconds
Started Jun 05 05:48:33 PM PDT 24
Finished Jun 05 05:50:21 PM PDT 24
Peak memory 205716 kb
Host smart-7d803a8e-5e8c-4af7-b735-2c5570d9e578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19755
58395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.1975558395
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.3385935324
Short name T737
Test name
Test status
Simulation time 10052907891 ps
CPU time 13.38 seconds
Started Jun 05 05:48:33 PM PDT 24
Finished Jun 05 05:48:47 PM PDT 24
Peak memory 205768 kb
Host smart-8242c0cb-2a7b-4faf-9a1e-ea1e02a0a454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33859
35324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.3385935324
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.2263213826
Short name T1162
Test name
Test status
Simulation time 10132649670 ps
CPU time 12.73 seconds
Started Jun 05 05:48:38 PM PDT 24
Finished Jun 05 05:48:51 PM PDT 24
Peak memory 205636 kb
Host smart-87ded3df-b611-43a7-b96e-bc2646eef4ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22632
13826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.2263213826
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.2492810893
Short name T1394
Test name
Test status
Simulation time 10108983683 ps
CPU time 12.7 seconds
Started Jun 05 05:48:26 PM PDT 24
Finished Jun 05 05:48:39 PM PDT 24
Peak memory 205772 kb
Host smart-e9af953a-1ba8-4477-a6cd-c69a49a87f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24928
10893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.2492810893
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.2023394160
Short name T411
Test name
Test status
Simulation time 10113817975 ps
CPU time 14.71 seconds
Started Jun 05 05:48:35 PM PDT 24
Finished Jun 05 05:48:51 PM PDT 24
Peak memory 205776 kb
Host smart-646fab74-2d0c-4b23-ae3c-1b3425bfa9b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20233
94160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.2023394160
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.3744428454
Short name T625
Test name
Test status
Simulation time 10057873450 ps
CPU time 14.42 seconds
Started Jun 05 05:48:38 PM PDT 24
Finished Jun 05 05:48:53 PM PDT 24
Peak memory 205688 kb
Host smart-4aeee771-2e8e-423c-8b88-0ba6b64ac823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37444
28454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3744428454
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.2364900172
Short name T1765
Test name
Test status
Simulation time 10041751865 ps
CPU time 13.37 seconds
Started Jun 05 05:48:40 PM PDT 24
Finished Jun 05 05:48:54 PM PDT 24
Peak memory 205764 kb
Host smart-a7ce2d5e-b730-4935-b8fe-17cdf9c1569a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23649
00172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.2364900172
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_eop_single_bit_handling.2145312368
Short name T650
Test name
Test status
Simulation time 10121009104 ps
CPU time 13.43 seconds
Started Jun 05 05:48:35 PM PDT 24
Finished Jun 05 05:48:49 PM PDT 24
Peak memory 205856 kb
Host smart-fbe911b5-6367-43b8-8623-e7b582ee37c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21453
12368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_eop_single_bit_handling.2145312368
Directory /workspace/37.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.769487940
Short name T1658
Test name
Test status
Simulation time 10051029255 ps
CPU time 13.06 seconds
Started Jun 05 05:48:35 PM PDT 24
Finished Jun 05 05:48:49 PM PDT 24
Peak memory 205732 kb
Host smart-716f47cc-ab5f-4820-a5b2-97ee4fc0c7d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76948
7940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.769487940
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.4191056613
Short name T1459
Test name
Test status
Simulation time 10045005860 ps
CPU time 13.45 seconds
Started Jun 05 05:48:34 PM PDT 24
Finished Jun 05 05:48:48 PM PDT 24
Peak memory 205696 kb
Host smart-783bcb5f-2f31-425b-b081-9292baadcc95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41910
56613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.4191056613
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.2335860355
Short name T853
Test name
Test status
Simulation time 16806262609 ps
CPU time 32.47 seconds
Started Jun 05 05:48:32 PM PDT 24
Finished Jun 05 05:49:05 PM PDT 24
Peak memory 205720 kb
Host smart-3859962f-4c06-4e7a-9355-cfbd9d8775c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23358
60355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.2335860355
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3868999125
Short name T795
Test name
Test status
Simulation time 10047061403 ps
CPU time 13.4 seconds
Started Jun 05 05:48:32 PM PDT 24
Finished Jun 05 05:48:46 PM PDT 24
Peak memory 205744 kb
Host smart-51518926-3afb-449f-bbcb-9bcec106daad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38689
99125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3868999125
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1085240642
Short name T1348
Test name
Test status
Simulation time 10122443265 ps
CPU time 14.97 seconds
Started Jun 05 05:48:37 PM PDT 24
Finished Jun 05 05:48:53 PM PDT 24
Peak memory 205768 kb
Host smart-ea4160d8-a14b-4621-8540-53045ea0198f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10852
40642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1085240642
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.2796920173
Short name T1595
Test name
Test status
Simulation time 10090095738 ps
CPU time 12.82 seconds
Started Jun 05 05:48:29 PM PDT 24
Finished Jun 05 05:48:43 PM PDT 24
Peak memory 205684 kb
Host smart-f9ba97fc-d985-40a1-ad69-c7da6715b856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27969
20173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.2796920173
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.2615090021
Short name T1258
Test name
Test status
Simulation time 10047131014 ps
CPU time 13.43 seconds
Started Jun 05 05:48:29 PM PDT 24
Finished Jun 05 05:48:43 PM PDT 24
Peak memory 205744 kb
Host smart-2429d99b-10b3-4204-ae11-8035a56480a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26150
90021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.2615090021
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.3415934305
Short name T148
Test name
Test status
Simulation time 10057029432 ps
CPU time 14.14 seconds
Started Jun 05 05:48:47 PM PDT 24
Finished Jun 05 05:49:02 PM PDT 24
Peak memory 205768 kb
Host smart-f5f7250b-c091-414f-a87c-c93ce67df745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34159
34305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.3415934305
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.3136531467
Short name T720
Test name
Test status
Simulation time 10069144961 ps
CPU time 13.79 seconds
Started Jun 05 05:48:28 PM PDT 24
Finished Jun 05 05:48:42 PM PDT 24
Peak memory 205708 kb
Host smart-980a5464-4abf-48ef-8818-9832082c14eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31365
31467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.3136531467
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.3672908918
Short name T1444
Test name
Test status
Simulation time 10116222126 ps
CPU time 13.77 seconds
Started Jun 05 05:48:38 PM PDT 24
Finished Jun 05 05:48:52 PM PDT 24
Peak memory 205620 kb
Host smart-7c82b971-0689-4b6c-a155-e44f0f5bdd1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36729
08918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3672908918
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.2743835909
Short name T862
Test name
Test status
Simulation time 10093773669 ps
CPU time 15.42 seconds
Started Jun 05 05:48:39 PM PDT 24
Finished Jun 05 05:48:54 PM PDT 24
Peak memory 205736 kb
Host smart-79e97e1f-53d6-403e-9da0-b1f5b21a36e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27438
35909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.2743835909
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.1579739765
Short name T525
Test name
Test status
Simulation time 10073753998 ps
CPU time 13.86 seconds
Started Jun 05 05:48:42 PM PDT 24
Finished Jun 05 05:48:56 PM PDT 24
Peak memory 205736 kb
Host smart-46e96eaf-acf9-4a80-800c-a5825ce2ab9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15797
39765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.1579739765
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.1132487021
Short name T1316
Test name
Test status
Simulation time 17596096953 ps
CPU time 64.13 seconds
Started Jun 05 05:48:29 PM PDT 24
Finished Jun 05 05:49:34 PM PDT 24
Peak memory 205704 kb
Host smart-b9a1665c-4470-4798-9bb6-f7c72b5dace3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11324
87021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.1132487021
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.2769244991
Short name T1393
Test name
Test status
Simulation time 10138495586 ps
CPU time 14.02 seconds
Started Jun 05 05:48:52 PM PDT 24
Finished Jun 05 05:49:07 PM PDT 24
Peak memory 205792 kb
Host smart-bed6120c-ea66-45a7-9ef2-e2e55f3d4a10
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2769244991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.2769244991
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.1654260037
Short name T1817
Test name
Test status
Simulation time 10082642216 ps
CPU time 14.06 seconds
Started Jun 05 05:48:35 PM PDT 24
Finished Jun 05 05:48:50 PM PDT 24
Peak memory 205744 kb
Host smart-1ddc3c4a-c98c-446d-ae8d-2bd2bcf50dfb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1654260037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.1654260037
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.2601795727
Short name T349
Test name
Test status
Simulation time 10097928621 ps
CPU time 14.25 seconds
Started Jun 05 05:48:56 PM PDT 24
Finished Jun 05 05:49:10 PM PDT 24
Peak memory 205764 kb
Host smart-162b696f-e5af-4a16-b7f7-31796c172909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26017
95727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.2601795727
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.1532298822
Short name T11
Test name
Test status
Simulation time 14168197265 ps
CPU time 16.52 seconds
Started Jun 05 05:48:32 PM PDT 24
Finished Jun 05 05:48:49 PM PDT 24
Peak memory 205780 kb
Host smart-d4452cf7-f6f4-44b4-b305-6f316ed78654
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1532298822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.1532298822
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.1472670161
Short name T559
Test name
Test status
Simulation time 23184640947 ps
CPU time 24.23 seconds
Started Jun 05 05:48:35 PM PDT 24
Finished Jun 05 05:49:01 PM PDT 24
Peak memory 205688 kb
Host smart-e11974ed-b82e-46ae-872d-88f296710d5e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1472670161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.1472670161
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.1497798468
Short name T1642
Test name
Test status
Simulation time 10056581865 ps
CPU time 13.68 seconds
Started Jun 05 05:48:50 PM PDT 24
Finished Jun 05 05:49:05 PM PDT 24
Peak memory 205736 kb
Host smart-07d038ce-da10-4f0d-b1f0-4bcc1481b774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14977
98468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.1497798468
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.3644015294
Short name T56
Test name
Test status
Simulation time 10079212928 ps
CPU time 14.46 seconds
Started Jun 05 05:48:34 PM PDT 24
Finished Jun 05 05:48:49 PM PDT 24
Peak memory 205648 kb
Host smart-69327a68-deee-4ae9-bf94-d9de07a52e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36440
15294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.3644015294
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.349084902
Short name T1863
Test name
Test status
Simulation time 10434747565 ps
CPU time 14.19 seconds
Started Jun 05 05:48:34 PM PDT 24
Finished Jun 05 05:48:49 PM PDT 24
Peak memory 205644 kb
Host smart-5582ffe2-bda9-4393-9bf0-64fd4bd37f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34908
4902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.349084902
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.2988298922
Short name T585
Test name
Test status
Simulation time 10045059642 ps
CPU time 13.44 seconds
Started Jun 05 05:48:35 PM PDT 24
Finished Jun 05 05:48:49 PM PDT 24
Peak memory 205776 kb
Host smart-74758d88-90d9-4bd3-a72b-f47a239e97e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29882
98922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.2988298922
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.3582796492
Short name T1244
Test name
Test status
Simulation time 10066629495 ps
CPU time 14.28 seconds
Started Jun 05 05:48:41 PM PDT 24
Finished Jun 05 05:48:56 PM PDT 24
Peak memory 205700 kb
Host smart-876f8efc-081c-4b36-8221-0169bf016347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35827
96492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.3582796492
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.3918575222
Short name T1545
Test name
Test status
Simulation time 10737635445 ps
CPU time 16.09 seconds
Started Jun 05 05:48:54 PM PDT 24
Finished Jun 05 05:49:11 PM PDT 24
Peak memory 205688 kb
Host smart-9b5c93a7-773b-44bf-9e45-1258d484bd55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39185
75222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.3918575222
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1483253250
Short name T1867
Test name
Test status
Simulation time 10118690411 ps
CPU time 14.53 seconds
Started Jun 05 05:48:35 PM PDT 24
Finished Jun 05 05:48:50 PM PDT 24
Peak memory 205644 kb
Host smart-58fc2022-55fc-41c8-afe6-ec429e4f1b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14832
53250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1483253250
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.790480255
Short name T1597
Test name
Test status
Simulation time 10075967874 ps
CPU time 13.44 seconds
Started Jun 05 05:48:51 PM PDT 24
Finished Jun 05 05:49:05 PM PDT 24
Peak memory 205796 kb
Host smart-8c7a0652-1d98-4d99-a66c-8632d937c7fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79048
0255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.790480255
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.185634544
Short name T1575
Test name
Test status
Simulation time 10056520470 ps
CPU time 14.08 seconds
Started Jun 05 05:48:36 PM PDT 24
Finished Jun 05 05:48:51 PM PDT 24
Peak memory 205664 kb
Host smart-d191e6e1-f61f-4e6c-ae33-27555db04d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18563
4544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.185634544
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.3830637852
Short name T1212
Test name
Test status
Simulation time 10080545070 ps
CPU time 13.86 seconds
Started Jun 05 05:48:37 PM PDT 24
Finished Jun 05 05:48:51 PM PDT 24
Peak memory 205732 kb
Host smart-622d96ac-dde1-47b6-9de0-e64ab5982cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38306
37852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.3830637852
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.3628010356
Short name T1260
Test name
Test status
Simulation time 10076921128 ps
CPU time 12.73 seconds
Started Jun 05 05:48:35 PM PDT 24
Finished Jun 05 05:48:49 PM PDT 24
Peak memory 205588 kb
Host smart-8bd39ef9-8ea2-4b78-9b75-782f94c23ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36280
10356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.3628010356
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.2144714096
Short name T1020
Test name
Test status
Simulation time 13161360578 ps
CPU time 19.32 seconds
Started Jun 05 05:48:51 PM PDT 24
Finished Jun 05 05:49:11 PM PDT 24
Peak memory 205804 kb
Host smart-5ce985b3-8662-4c64-8813-d889db427773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21447
14096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.2144714096
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1604678795
Short name T617
Test name
Test status
Simulation time 10139382006 ps
CPU time 13.48 seconds
Started Jun 05 05:48:33 PM PDT 24
Finished Jun 05 05:48:47 PM PDT 24
Peak memory 205728 kb
Host smart-afde698d-e147-4270-8b0e-2e1af2556277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16046
78795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1604678795
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.1087430201
Short name T1011
Test name
Test status
Simulation time 16657103210 ps
CPU time 198.5 seconds
Started Jun 05 05:48:35 PM PDT 24
Finished Jun 05 05:51:54 PM PDT 24
Peak memory 205896 kb
Host smart-55a1d35b-9fc0-4d31-a5cd-7344fbcf590a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10874
30201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.1087430201
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.282391161
Short name T392
Test name
Test status
Simulation time 10108093300 ps
CPU time 12.66 seconds
Started Jun 05 05:48:49 PM PDT 24
Finished Jun 05 05:49:03 PM PDT 24
Peak memory 205692 kb
Host smart-90374676-d204-4048-a899-8853da418278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28239
1161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.282391161
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.711621294
Short name T97
Test name
Test status
Simulation time 10084141913 ps
CPU time 13.8 seconds
Started Jun 05 05:48:57 PM PDT 24
Finished Jun 05 05:49:11 PM PDT 24
Peak memory 205664 kb
Host smart-d3478e8c-d773-4360-a2a4-9592508b41b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71162
1294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.711621294
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.811803802
Short name T903
Test name
Test status
Simulation time 10072663468 ps
CPU time 12.6 seconds
Started Jun 05 05:48:38 PM PDT 24
Finished Jun 05 05:48:51 PM PDT 24
Peak memory 205740 kb
Host smart-183b872d-f5e7-4d40-a66d-b6ec6db3bf84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81180
3802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.811803802
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.3554663297
Short name T311
Test name
Test status
Simulation time 10054998235 ps
CPU time 12.3 seconds
Started Jun 05 05:48:40 PM PDT 24
Finished Jun 05 05:48:53 PM PDT 24
Peak memory 205748 kb
Host smart-0d054508-fe99-47b6-a943-ce3f6ffb94bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35546
63297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3554663297
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.4204603223
Short name T1954
Test name
Test status
Simulation time 10119123216 ps
CPU time 14.29 seconds
Started Jun 05 05:48:35 PM PDT 24
Finished Jun 05 05:48:51 PM PDT 24
Peak memory 205644 kb
Host smart-067fc9a6-a5f0-4e71-bfc1-3567b5a5d444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42046
03223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.4204603223
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.2191694070
Short name T503
Test name
Test status
Simulation time 10053571511 ps
CPU time 14.13 seconds
Started Jun 05 05:48:52 PM PDT 24
Finished Jun 05 05:49:07 PM PDT 24
Peak memory 205804 kb
Host smart-6b064b9f-af97-4227-98fb-56230ed2179c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21916
94070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.2191694070
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_eop_single_bit_handling.2523198597
Short name T472
Test name
Test status
Simulation time 10104208249 ps
CPU time 12.93 seconds
Started Jun 05 05:48:40 PM PDT 24
Finished Jun 05 05:48:54 PM PDT 24
Peak memory 205688 kb
Host smart-3aeea328-5f22-48a2-b1d3-3cff16825b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25231
98597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_eop_single_bit_handling.2523198597
Directory /workspace/38.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3993178264
Short name T1827
Test name
Test status
Simulation time 10064106605 ps
CPU time 13.99 seconds
Started Jun 05 05:48:34 PM PDT 24
Finished Jun 05 05:48:48 PM PDT 24
Peak memory 205756 kb
Host smart-1f8b71a1-0687-4993-995d-314e493a903b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39931
78264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3993178264
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.3212393378
Short name T1022
Test name
Test status
Simulation time 10050037934 ps
CPU time 13.63 seconds
Started Jun 05 05:48:35 PM PDT 24
Finished Jun 05 05:48:49 PM PDT 24
Peak memory 205664 kb
Host smart-4871dc5e-ff94-4ed2-9294-bfc910e7c05c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32123
93378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.3212393378
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.3836628602
Short name T230
Test name
Test status
Simulation time 21234935481 ps
CPU time 38.06 seconds
Started Jun 05 05:48:48 PM PDT 24
Finished Jun 05 05:49:27 PM PDT 24
Peak memory 205664 kb
Host smart-0c4028cd-35e1-4fe3-9b5e-6e7f3e6629c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38366
28602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.3836628602
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.2452289396
Short name T514
Test name
Test status
Simulation time 10072892627 ps
CPU time 14.22 seconds
Started Jun 05 05:48:34 PM PDT 24
Finished Jun 05 05:48:49 PM PDT 24
Peak memory 205712 kb
Host smart-85b3096d-5bb5-4935-ab48-83a90b4ac5ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24522
89396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.2452289396
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.3878115156
Short name T506
Test name
Test status
Simulation time 10061685971 ps
CPU time 13.16 seconds
Started Jun 05 05:48:33 PM PDT 24
Finished Jun 05 05:48:47 PM PDT 24
Peak memory 205764 kb
Host smart-460d717e-a776-4af1-8f08-bced466ed04a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38781
15156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3878115156
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.3389845581
Short name T425
Test name
Test status
Simulation time 10125044498 ps
CPU time 16.31 seconds
Started Jun 05 05:48:41 PM PDT 24
Finished Jun 05 05:48:58 PM PDT 24
Peak memory 205704 kb
Host smart-6a2a67a8-d267-4803-b648-2dac676e25a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33898
45581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.3389845581
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.2687518868
Short name T1796
Test name
Test status
Simulation time 10036374096 ps
CPU time 12.79 seconds
Started Jun 05 05:48:33 PM PDT 24
Finished Jun 05 05:48:46 PM PDT 24
Peak memory 205648 kb
Host smart-2c45ec92-ec3c-496a-aad3-a2d7e982e3b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26875
18868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.2687518868
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.1227480570
Short name T1970
Test name
Test status
Simulation time 10045863924 ps
CPU time 12.97 seconds
Started Jun 05 05:48:49 PM PDT 24
Finished Jun 05 05:49:03 PM PDT 24
Peak memory 205768 kb
Host smart-511e78b9-fc5d-4686-af36-ebf50db491ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12274
80570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.1227480570
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.3108622675
Short name T417
Test name
Test status
Simulation time 10048992534 ps
CPU time 14.37 seconds
Started Jun 05 05:48:46 PM PDT 24
Finished Jun 05 05:49:01 PM PDT 24
Peak memory 205684 kb
Host smart-784564f2-7289-4355-9ee6-f6b6d1478bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31086
22675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.3108622675
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.2355409665
Short name T1106
Test name
Test status
Simulation time 10098865494 ps
CPU time 13.74 seconds
Started Jun 05 05:48:33 PM PDT 24
Finished Jun 05 05:48:48 PM PDT 24
Peak memory 205984 kb
Host smart-cc9ed3c1-bd9a-42f9-8a36-83220065697e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23554
09665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.2355409665
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.271975300
Short name T479
Test name
Test status
Simulation time 10081954177 ps
CPU time 13.75 seconds
Started Jun 05 05:48:37 PM PDT 24
Finished Jun 05 05:48:51 PM PDT 24
Peak memory 205756 kb
Host smart-9992d0f0-166f-4b1a-a8bd-8c3256cb8048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27197
5300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.271975300
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.1730354800
Short name T1792
Test name
Test status
Simulation time 10082730012 ps
CPU time 13.54 seconds
Started Jun 05 05:48:47 PM PDT 24
Finished Jun 05 05:49:01 PM PDT 24
Peak memory 205780 kb
Host smart-9bc68fd5-dd68-49da-885d-a24d6f99fca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17303
54800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1730354800
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.2512044711
Short name T2019
Test name
Test status
Simulation time 14476358028 ps
CPU time 133.65 seconds
Started Jun 05 05:48:46 PM PDT 24
Finished Jun 05 05:51:00 PM PDT 24
Peak memory 205616 kb
Host smart-4fde6ffb-66c2-4b81-b35f-40425234655b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25120
44711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.2512044711
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.1237936300
Short name T1828
Test name
Test status
Simulation time 10143699727 ps
CPU time 18.18 seconds
Started Jun 05 05:48:46 PM PDT 24
Finished Jun 05 05:49:05 PM PDT 24
Peak memory 205772 kb
Host smart-1a505fe9-7f14-45f8-a679-86d8ad451671
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1237936300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.1237936300
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.3079524492
Short name T1917
Test name
Test status
Simulation time 10090709943 ps
CPU time 13.08 seconds
Started Jun 05 05:48:57 PM PDT 24
Finished Jun 05 05:49:11 PM PDT 24
Peak memory 205748 kb
Host smart-3b11bc14-46e5-46d9-8476-3e117aded274
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3079524492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.3079524492
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.530946153
Short name T802
Test name
Test status
Simulation time 10147253653 ps
CPU time 13.92 seconds
Started Jun 05 05:48:58 PM PDT 24
Finished Jun 05 05:49:12 PM PDT 24
Peak memory 205764 kb
Host smart-8cfdeac5-69dc-47b7-a42f-37e2947d1bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53094
6153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.530946153
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.3920193592
Short name T1538
Test name
Test status
Simulation time 14014360971 ps
CPU time 18.8 seconds
Started Jun 05 05:48:55 PM PDT 24
Finished Jun 05 05:49:15 PM PDT 24
Peak memory 205752 kb
Host smart-c6ae39e5-b92a-4d54-8fa9-8d20e399a8e3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3920193592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.3920193592
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.181126283
Short name T1753
Test name
Test status
Simulation time 23264555513 ps
CPU time 25.98 seconds
Started Jun 05 05:48:48 PM PDT 24
Finished Jun 05 05:49:15 PM PDT 24
Peak memory 205808 kb
Host smart-450fad1d-b3cb-459f-92c5-ca7038781405
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=181126283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.181126283
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1345274638
Short name T485
Test name
Test status
Simulation time 10132886836 ps
CPU time 12.67 seconds
Started Jun 05 05:48:52 PM PDT 24
Finished Jun 05 05:49:06 PM PDT 24
Peak memory 205728 kb
Host smart-3e523394-88d7-4e89-ad56-9cae7c52c562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13452
74638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1345274638
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.2980548602
Short name T1324
Test name
Test status
Simulation time 10911306318 ps
CPU time 15.78 seconds
Started Jun 05 05:48:58 PM PDT 24
Finished Jun 05 05:49:15 PM PDT 24
Peak memory 205732 kb
Host smart-7f7920aa-20ae-40fa-b8fb-6d4ffbbb6238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29805
48602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.2980548602
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.2196689486
Short name T1804
Test name
Test status
Simulation time 10057783131 ps
CPU time 13.12 seconds
Started Jun 05 05:48:51 PM PDT 24
Finished Jun 05 05:49:05 PM PDT 24
Peak memory 205760 kb
Host smart-04476e95-17fd-4885-991e-82a6ec770a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21966
89486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.2196689486
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.3136104545
Short name T1152
Test name
Test status
Simulation time 10063434843 ps
CPU time 13.37 seconds
Started Jun 05 05:48:48 PM PDT 24
Finished Jun 05 05:49:02 PM PDT 24
Peak memory 205624 kb
Host smart-eebe1b51-7393-4218-8fe4-9edfc5a83fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31361
04545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3136104545
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.1229911114
Short name T620
Test name
Test status
Simulation time 10810557468 ps
CPU time 15.24 seconds
Started Jun 05 05:48:41 PM PDT 24
Finished Jun 05 05:48:57 PM PDT 24
Peak memory 205748 kb
Host smart-9a1349e0-bd9f-4a27-beb0-5e8916d58761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12299
11114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.1229911114
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.1629896098
Short name T1971
Test name
Test status
Simulation time 10210556824 ps
CPU time 15.2 seconds
Started Jun 05 05:48:49 PM PDT 24
Finished Jun 05 05:49:05 PM PDT 24
Peak memory 205760 kb
Host smart-353843cf-19db-44d1-9437-cf8a8236ef8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16298
96098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.1629896098
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2840687983
Short name T888
Test name
Test status
Simulation time 10121281112 ps
CPU time 12.93 seconds
Started Jun 05 05:48:45 PM PDT 24
Finished Jun 05 05:48:59 PM PDT 24
Peak memory 205740 kb
Host smart-cea00649-354b-4b98-b7ba-1dd277176cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28406
87983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2840687983
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.892492163
Short name T1872
Test name
Test status
Simulation time 10039797864 ps
CPU time 13.51 seconds
Started Jun 05 05:48:49 PM PDT 24
Finished Jun 05 05:49:03 PM PDT 24
Peak memory 205728 kb
Host smart-91a3b855-5c7f-47f7-965a-cad57e83215f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89249
2163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.892492163
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.2698732827
Short name T1330
Test name
Test status
Simulation time 10134991394 ps
CPU time 13.25 seconds
Started Jun 05 05:48:51 PM PDT 24
Finished Jun 05 05:49:05 PM PDT 24
Peak memory 205684 kb
Host smart-96303282-82da-40b7-b335-e2c459fff60a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26987
32827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2698732827
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.500168670
Short name T1083
Test name
Test status
Simulation time 10127729974 ps
CPU time 14.03 seconds
Started Jun 05 05:48:46 PM PDT 24
Finished Jun 05 05:49:00 PM PDT 24
Peak memory 205732 kb
Host smart-4485b9ae-1179-4ce6-8671-29ff056b1c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50016
8670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.500168670
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.2148478251
Short name T1414
Test name
Test status
Simulation time 13248717902 ps
CPU time 15.98 seconds
Started Jun 05 05:48:58 PM PDT 24
Finished Jun 05 05:49:15 PM PDT 24
Peak memory 205680 kb
Host smart-ff507260-2f3b-4206-a55d-d70f1cef24a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21484
78251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.2148478251
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.223004051
Short name T1810
Test name
Test status
Simulation time 10125119695 ps
CPU time 13.85 seconds
Started Jun 05 05:48:51 PM PDT 24
Finished Jun 05 05:49:05 PM PDT 24
Peak memory 205784 kb
Host smart-18956967-760e-4756-9572-f09c28d57f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22300
4051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.223004051
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.1885789127
Short name T526
Test name
Test status
Simulation time 16180499811 ps
CPU time 73.78 seconds
Started Jun 05 05:48:54 PM PDT 24
Finished Jun 05 05:50:08 PM PDT 24
Peak memory 205636 kb
Host smart-d5a38cd2-f964-476f-8e39-61b91c369e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18857
89127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.1885789127
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3123349516
Short name T1201
Test name
Test status
Simulation time 10066428708 ps
CPU time 13.1 seconds
Started Jun 05 05:48:50 PM PDT 24
Finished Jun 05 05:49:04 PM PDT 24
Peak memory 205676 kb
Host smart-af3550e7-04c5-41aa-bd3a-a049bb0ca53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31233
49516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3123349516
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3644555542
Short name T94
Test name
Test status
Simulation time 10117544045 ps
CPU time 14.84 seconds
Started Jun 05 05:48:46 PM PDT 24
Finished Jun 05 05:49:02 PM PDT 24
Peak memory 205700 kb
Host smart-0f81ad7c-47c1-4430-b8be-a99475655a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36445
55542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3644555542
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.1017361162
Short name T513
Test name
Test status
Simulation time 10124090439 ps
CPU time 14.72 seconds
Started Jun 05 05:48:46 PM PDT 24
Finished Jun 05 05:49:01 PM PDT 24
Peak memory 205700 kb
Host smart-75c49ae9-6105-4031-9de3-6dc3eaab2458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10173
61162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.1017361162
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.264256873
Short name T1768
Test name
Test status
Simulation time 10074705106 ps
CPU time 17.13 seconds
Started Jun 05 05:48:49 PM PDT 24
Finished Jun 05 05:49:07 PM PDT 24
Peak memory 205788 kb
Host smart-e0aff606-5680-4c15-8863-107de4ac3032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26425
6873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.264256873
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.2916062053
Short name T1077
Test name
Test status
Simulation time 10070846431 ps
CPU time 13.17 seconds
Started Jun 05 05:48:47 PM PDT 24
Finished Jun 05 05:49:01 PM PDT 24
Peak memory 205704 kb
Host smart-ed6a3ca4-017a-4dc1-8182-aad867d45bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29160
62053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.2916062053
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.3965964062
Short name T174
Test name
Test status
Simulation time 10050217733 ps
CPU time 14.5 seconds
Started Jun 05 05:48:43 PM PDT 24
Finished Jun 05 05:48:58 PM PDT 24
Peak memory 205796 kb
Host smart-34c91afd-a69e-4e6c-8a68-3a8812c718bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39659
64062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.3965964062
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_eop_single_bit_handling.3297907911
Short name T1068
Test name
Test status
Simulation time 10069695034 ps
CPU time 15 seconds
Started Jun 05 05:48:48 PM PDT 24
Finished Jun 05 05:49:03 PM PDT 24
Peak memory 205712 kb
Host smart-5a177533-dc42-463f-b621-2315653fcd83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32979
07911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_eop_single_bit_handling.3297907911
Directory /workspace/39.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1874466914
Short name T1446
Test name
Test status
Simulation time 10051295911 ps
CPU time 16.42 seconds
Started Jun 05 05:48:47 PM PDT 24
Finished Jun 05 05:49:04 PM PDT 24
Peak memory 205788 kb
Host smart-20c61104-2b61-46fd-ba9d-beb849a0c8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18744
66914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.1874466914
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3037657645
Short name T1797
Test name
Test status
Simulation time 10045640382 ps
CPU time 14.25 seconds
Started Jun 05 05:48:59 PM PDT 24
Finished Jun 05 05:49:14 PM PDT 24
Peak memory 205560 kb
Host smart-d4c47f92-048d-4ffe-ba39-268ba67b3156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30376
57645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3037657645
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.826814824
Short name T894
Test name
Test status
Simulation time 17185340411 ps
CPU time 29.09 seconds
Started Jun 05 05:48:40 PM PDT 24
Finished Jun 05 05:49:10 PM PDT 24
Peak memory 205652 kb
Host smart-e1f55039-7668-4d7a-8eda-e0b13bc5b773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82681
4824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.826814824
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.4158704480
Short name T1221
Test name
Test status
Simulation time 10054455016 ps
CPU time 13.13 seconds
Started Jun 05 05:48:48 PM PDT 24
Finished Jun 05 05:49:02 PM PDT 24
Peak memory 205760 kb
Host smart-a4a78810-4e24-4adc-8d2b-c2dbdf0cedd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41587
04480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.4158704480
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1180335844
Short name T565
Test name
Test status
Simulation time 10074925946 ps
CPU time 13.83 seconds
Started Jun 05 05:48:56 PM PDT 24
Finished Jun 05 05:49:10 PM PDT 24
Peak memory 205724 kb
Host smart-3e6154ee-aad3-4804-be79-b23ee41b9603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11803
35844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1180335844
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.2509478690
Short name T1835
Test name
Test status
Simulation time 10100411988 ps
CPU time 14.44 seconds
Started Jun 05 05:48:45 PM PDT 24
Finished Jun 05 05:49:00 PM PDT 24
Peak memory 205668 kb
Host smart-d4370cba-107f-4246-8eec-00fde63cbf22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25094
78690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.2509478690
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.2373542761
Short name T226
Test name
Test status
Simulation time 10056094039 ps
CPU time 14.03 seconds
Started Jun 05 05:48:50 PM PDT 24
Finished Jun 05 05:49:05 PM PDT 24
Peak memory 205732 kb
Host smart-c03b7f31-ebc5-436c-b6fd-96c484409032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23735
42761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.2373542761
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.3053451655
Short name T1128
Test name
Test status
Simulation time 10060683122 ps
CPU time 15.94 seconds
Started Jun 05 05:48:59 PM PDT 24
Finished Jun 05 05:49:16 PM PDT 24
Peak memory 205652 kb
Host smart-0aa6f2d0-c55c-40e1-8b36-5d525fa3f23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30534
51655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3053451655
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.3172261778
Short name T76
Test name
Test status
Simulation time 10054590637 ps
CPU time 14.5 seconds
Started Jun 05 05:48:47 PM PDT 24
Finished Jun 05 05:49:02 PM PDT 24
Peak memory 205760 kb
Host smart-cbff1553-63ff-461a-badc-bfe43d658b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31722
61778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.3172261778
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.2353897233
Short name T507
Test name
Test status
Simulation time 10163444572 ps
CPU time 13.71 seconds
Started Jun 05 05:48:50 PM PDT 24
Finished Jun 05 05:49:04 PM PDT 24
Peak memory 205696 kb
Host smart-3eaed078-ada1-41a2-8f06-c0c184b23624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23538
97233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2353897233
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.3922199823
Short name T1941
Test name
Test status
Simulation time 10126262201 ps
CPU time 14.59 seconds
Started Jun 05 05:48:50 PM PDT 24
Finished Jun 05 05:49:05 PM PDT 24
Peak memory 205780 kb
Host smart-78e4136e-ed85-49c9-8bd5-35f878955786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39221
99823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.3922199823
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1389935516
Short name T1953
Test name
Test status
Simulation time 10066202508 ps
CPU time 13.88 seconds
Started Jun 05 05:48:54 PM PDT 24
Finished Jun 05 05:49:09 PM PDT 24
Peak memory 205752 kb
Host smart-3d61af3a-0b6a-4ed0-a968-3aa17b94dcef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13899
35516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1389935516
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.3915945930
Short name T436
Test name
Test status
Simulation time 15288096577 ps
CPU time 156.58 seconds
Started Jun 05 05:48:49 PM PDT 24
Finished Jun 05 05:51:26 PM PDT 24
Peak memory 205648 kb
Host smart-79ca4e77-4f50-4dfb-acf6-f09e1ebe751b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39159
45930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.3915945930
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.3885081544
Short name T730
Test name
Test status
Simulation time 10158175999 ps
CPU time 13.61 seconds
Started Jun 05 05:44:38 PM PDT 24
Finished Jun 05 05:44:52 PM PDT 24
Peak memory 205792 kb
Host smart-b4f8230b-01d6-45b2-9f7b-06afb24694a6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3885081544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.3885081544
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.2768606150
Short name T456
Test name
Test status
Simulation time 10050877900 ps
CPU time 13.45 seconds
Started Jun 05 05:44:41 PM PDT 24
Finished Jun 05 05:44:55 PM PDT 24
Peak memory 205652 kb
Host smart-a58d769f-e2cf-4b81-9141-c1f84c2f5cd3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2768606150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.2768606150
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.1095392082
Short name T1871
Test name
Test status
Simulation time 10112887065 ps
CPU time 15.29 seconds
Started Jun 05 05:44:40 PM PDT 24
Finished Jun 05 05:44:56 PM PDT 24
Peak memory 205732 kb
Host smart-2398b3d6-88b1-4718-96ac-37b475ed3ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10953
92082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.1095392082
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.1367645080
Short name T1041
Test name
Test status
Simulation time 13407825666 ps
CPU time 16.24 seconds
Started Jun 05 05:44:30 PM PDT 24
Finished Jun 05 05:44:47 PM PDT 24
Peak memory 205736 kb
Host smart-8209fe42-c325-46db-aa59-fd65b22fbc14
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1367645080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.1367645080
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.2252048259
Short name T500
Test name
Test status
Simulation time 23336751232 ps
CPU time 30.61 seconds
Started Jun 05 05:44:29 PM PDT 24
Finished Jun 05 05:45:01 PM PDT 24
Peak memory 205716 kb
Host smart-c001e50f-dd2e-4d99-9283-54c6083f02a6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2252048259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.2252048259
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.921340255
Short name T1118
Test name
Test status
Simulation time 10053403781 ps
CPU time 13.91 seconds
Started Jun 05 05:44:29 PM PDT 24
Finished Jun 05 05:44:44 PM PDT 24
Peak memory 205648 kb
Host smart-f66ef299-0c57-4620-a37e-303c14bf1c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92134
0255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.921340255
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.3724081962
Short name T1766
Test name
Test status
Simulation time 10070399896 ps
CPU time 13.28 seconds
Started Jun 05 05:44:32 PM PDT 24
Finished Jun 05 05:44:46 PM PDT 24
Peak memory 205732 kb
Host smart-90f9be04-727e-41ed-9237-42da663781b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37240
81962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.3724081962
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.1159558139
Short name T1021
Test name
Test status
Simulation time 10700327220 ps
CPU time 15.37 seconds
Started Jun 05 05:44:30 PM PDT 24
Finished Jun 05 05:44:46 PM PDT 24
Peak memory 205636 kb
Host smart-19ac7202-9ce3-4e6d-be07-f558b4a98880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11595
58139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.1159558139
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.1823780077
Short name T1263
Test name
Test status
Simulation time 10045614148 ps
CPU time 15.94 seconds
Started Jun 05 05:44:39 PM PDT 24
Finished Jun 05 05:44:56 PM PDT 24
Peak memory 205692 kb
Host smart-c6f67de3-011b-4e92-9260-e0f580a393d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18237
80077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.1823780077
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.3585388081
Short name T1669
Test name
Test status
Simulation time 10070183243 ps
CPU time 13.86 seconds
Started Jun 05 05:44:28 PM PDT 24
Finished Jun 05 05:44:43 PM PDT 24
Peak memory 205636 kb
Host smart-ef1c3fc7-6adb-4870-99c1-5e8429c6a445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35853
88081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.3585388081
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.3405010904
Short name T371
Test name
Test status
Simulation time 10867649755 ps
CPU time 14.73 seconds
Started Jun 05 05:44:32 PM PDT 24
Finished Jun 05 05:44:47 PM PDT 24
Peak memory 205772 kb
Host smart-e932bfce-5af6-4c51-afaf-a53b4ace5d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34050
10904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.3405010904
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.4169725353
Short name T636
Test name
Test status
Simulation time 10319545046 ps
CPU time 15.19 seconds
Started Jun 05 05:44:41 PM PDT 24
Finished Jun 05 05:44:56 PM PDT 24
Peak memory 205716 kb
Host smart-bd47a960-86a2-4288-9014-6be92145cf1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41697
25353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.4169725353
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1842600428
Short name T533
Test name
Test status
Simulation time 10104222463 ps
CPU time 13.76 seconds
Started Jun 05 05:44:41 PM PDT 24
Finished Jun 05 05:44:55 PM PDT 24
Peak memory 205648 kb
Host smart-f187a76a-c68f-49d9-b25c-6f850c5bb2c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18426
00428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1842600428
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.3193578157
Short name T70
Test name
Test status
Simulation time 10041199684 ps
CPU time 14.48 seconds
Started Jun 05 05:44:41 PM PDT 24
Finished Jun 05 05:44:56 PM PDT 24
Peak memory 205752 kb
Host smart-f698ae73-e0df-41bc-9bba-9727093f85b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31935
78157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3193578157
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.3775102298
Short name T122
Test name
Test status
Simulation time 10148934525 ps
CPU time 14.02 seconds
Started Jun 05 05:44:39 PM PDT 24
Finished Jun 05 05:44:54 PM PDT 24
Peak memory 205692 kb
Host smart-e0b874ef-4b27-48eb-acb9-d2d27c5f2f1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37751
02298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.3775102298
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.2281549489
Short name T1500
Test name
Test status
Simulation time 10094621787 ps
CPU time 14.35 seconds
Started Jun 05 05:44:37 PM PDT 24
Finished Jun 05 05:44:52 PM PDT 24
Peak memory 205652 kb
Host smart-cdd26b34-6cce-46c1-ae39-2f6f01b8e8bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22815
49489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.2281549489
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.253952142
Short name T806
Test name
Test status
Simulation time 13250749904 ps
CPU time 15.86 seconds
Started Jun 05 05:44:38 PM PDT 24
Finished Jun 05 05:44:55 PM PDT 24
Peak memory 205744 kb
Host smart-8415b1e2-cc3b-4ab6-afe0-27ae2a1e4dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25395
2142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.253952142
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.2754836786
Short name T866
Test name
Test status
Simulation time 10093670604 ps
CPU time 13.91 seconds
Started Jun 05 05:44:41 PM PDT 24
Finished Jun 05 05:44:56 PM PDT 24
Peak memory 205748 kb
Host smart-ecb91ceb-b87a-4203-91f9-a8ac3be8a91f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27548
36786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.2754836786
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.585841280
Short name T6
Test name
Test status
Simulation time 22160154867 ps
CPU time 370.18 seconds
Started Jun 05 05:44:39 PM PDT 24
Finished Jun 05 05:50:50 PM PDT 24
Peak memory 205664 kb
Host smart-34c5c8ac-66a0-4df4-b751-e2ba736a008c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58584
1280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.585841280
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1952400340
Short name T1958
Test name
Test status
Simulation time 10054428043 ps
CPU time 13.95 seconds
Started Jun 05 05:44:39 PM PDT 24
Finished Jun 05 05:44:53 PM PDT 24
Peak memory 205732 kb
Host smart-bae67e66-9acd-4f20-bd0c-64747ddfd7ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19524
00340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1952400340
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.2856336345
Short name T1405
Test name
Test status
Simulation time 10132739729 ps
CPU time 13.41 seconds
Started Jun 05 05:44:39 PM PDT 24
Finished Jun 05 05:44:53 PM PDT 24
Peak memory 205664 kb
Host smart-55fa4e2b-c775-433a-b787-057c0f348727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28563
36345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.2856336345
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.3053283025
Short name T1460
Test name
Test status
Simulation time 10076850164 ps
CPU time 12.87 seconds
Started Jun 05 05:44:40 PM PDT 24
Finished Jun 05 05:44:53 PM PDT 24
Peak memory 205692 kb
Host smart-da083484-f2f4-401d-a8fc-e3f60191169a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30532
83025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.3053283025
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.3117120254
Short name T1352
Test name
Test status
Simulation time 10065870712 ps
CPU time 15.44 seconds
Started Jun 05 05:44:42 PM PDT 24
Finished Jun 05 05:44:58 PM PDT 24
Peak memory 205800 kb
Host smart-1fafb841-beab-4a54-ae42-afc628ebd99c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31171
20254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.3117120254
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.1070294942
Short name T864
Test name
Test status
Simulation time 10058496037 ps
CPU time 13.42 seconds
Started Jun 05 05:44:40 PM PDT 24
Finished Jun 05 05:44:54 PM PDT 24
Peak memory 205756 kb
Host smart-2a2d5b85-3812-4522-a966-02c1a4fa9b55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10702
94942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.1070294942
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1498248095
Short name T1398
Test name
Test status
Simulation time 10073996620 ps
CPU time 14.08 seconds
Started Jun 05 05:44:40 PM PDT 24
Finished Jun 05 05:44:55 PM PDT 24
Peak memory 205744 kb
Host smart-85bed423-6ac8-4ee2-a92c-f5e0591aafd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14982
48095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1498248095
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_eop_single_bit_handling.100125537
Short name T578
Test name
Test status
Simulation time 10082610861 ps
CPU time 14.94 seconds
Started Jun 05 05:44:38 PM PDT 24
Finished Jun 05 05:44:53 PM PDT 24
Peak memory 205740 kb
Host smart-7f09e440-5bd5-4e95-8973-988d758fdfaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10012
5537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_eop_single_bit_handling.100125537
Directory /workspace/4.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.2880576639
Short name T1392
Test name
Test status
Simulation time 10045455916 ps
CPU time 12.47 seconds
Started Jun 05 05:44:38 PM PDT 24
Finished Jun 05 05:44:51 PM PDT 24
Peak memory 205692 kb
Host smart-76e1eaca-7095-4087-9886-238ca93fd051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28805
76639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2880576639
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.2859279516
Short name T1614
Test name
Test status
Simulation time 10079856784 ps
CPU time 13.85 seconds
Started Jun 05 05:44:40 PM PDT 24
Finished Jun 05 05:44:54 PM PDT 24
Peak memory 205708 kb
Host smart-9d26c9bc-c9be-4ad3-99e7-a239458521ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28592
79516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.2859279516
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.1552178347
Short name T945
Test name
Test status
Simulation time 21386308188 ps
CPU time 38.43 seconds
Started Jun 05 05:44:38 PM PDT 24
Finished Jun 05 05:45:17 PM PDT 24
Peak memory 205708 kb
Host smart-822692bf-9fa3-47b1-b2c9-8480ac959ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15521
78347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.1552178347
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.1406071211
Short name T1525
Test name
Test status
Simulation time 10047913774 ps
CPU time 15.34 seconds
Started Jun 05 05:44:39 PM PDT 24
Finished Jun 05 05:44:55 PM PDT 24
Peak memory 205612 kb
Host smart-1de52ec5-c2cf-4cee-9c33-2a6d52209621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14060
71211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.1406071211
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.1370105109
Short name T1801
Test name
Test status
Simulation time 10076512235 ps
CPU time 13.73 seconds
Started Jun 05 05:44:43 PM PDT 24
Finished Jun 05 05:44:57 PM PDT 24
Peak memory 205740 kb
Host smart-35e3628d-a325-4e1e-b230-b6ee8fe37d9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13701
05109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.1370105109
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.1170577266
Short name T153
Test name
Test status
Simulation time 26769912780 ps
CPU time 139.55 seconds
Started Jun 05 05:44:37 PM PDT 24
Finished Jun 05 05:46:57 PM PDT 24
Peak memory 205788 kb
Host smart-5cab270f-2298-43c7-ac10-b5bf1a6edf8a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1170577266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.1170577266
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.4125841353
Short name T1696
Test name
Test status
Simulation time 38009824898 ps
CPU time 813.52 seconds
Started Jun 05 05:44:37 PM PDT 24
Finished Jun 05 05:58:11 PM PDT 24
Peak memory 205796 kb
Host smart-108c7b98-5218-4282-8b10-9d7c6a847106
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4125841353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.4125841353
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.2442128030
Short name T1404
Test name
Test status
Simulation time 31375954391 ps
CPU time 189.78 seconds
Started Jun 05 05:44:41 PM PDT 24
Finished Jun 05 05:47:52 PM PDT 24
Peak memory 205776 kb
Host smart-46887961-28a1-40cf-b59b-5c53f84a1909
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2442128030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.2442128030
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.74283051
Short name T713
Test name
Test status
Simulation time 10065508855 ps
CPU time 14.5 seconds
Started Jun 05 05:44:41 PM PDT 24
Finished Jun 05 05:44:56 PM PDT 24
Peak memory 205720 kb
Host smart-f8dba308-a0d0-4a15-ba7d-13ce54d83bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74283
051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.74283051
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.2898946874
Short name T989
Test name
Test status
Simulation time 10072218964 ps
CPU time 13.14 seconds
Started Jun 05 05:44:40 PM PDT 24
Finished Jun 05 05:44:53 PM PDT 24
Peak memory 205652 kb
Host smart-7927f8ca-d8c0-44cd-87b5-3ed924531992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28989
46874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.2898946874
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.1423648409
Short name T1885
Test name
Test status
Simulation time 10056110702 ps
CPU time 13.43 seconds
Started Jun 05 05:44:36 PM PDT 24
Finished Jun 05 05:44:50 PM PDT 24
Peak memory 205764 kb
Host smart-8a4c886a-3658-40fb-8f65-338063fc68b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14236
48409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.1423648409
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.3009810548
Short name T566
Test name
Test status
Simulation time 10066462258 ps
CPU time 13.38 seconds
Started Jun 05 05:44:40 PM PDT 24
Finished Jun 05 05:44:54 PM PDT 24
Peak memory 205760 kb
Host smart-868186eb-64ee-48c8-8079-b3359e7e2a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30098
10548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.3009810548
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.3986666045
Short name T1342
Test name
Test status
Simulation time 10123003693 ps
CPU time 12.26 seconds
Started Jun 05 05:44:28 PM PDT 24
Finished Jun 05 05:44:40 PM PDT 24
Peak memory 205764 kb
Host smart-f5e6f811-000e-41b4-b5ac-d3efb174c493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39866
66045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3986666045
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.3839734126
Short name T1171
Test name
Test status
Simulation time 10084770497 ps
CPU time 12.91 seconds
Started Jun 05 05:44:39 PM PDT 24
Finished Jun 05 05:44:52 PM PDT 24
Peak memory 205712 kb
Host smart-f9f9c4a4-2590-4f65-87cd-2c631e1a2385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38397
34126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.3839734126
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.3112448343
Short name T991
Test name
Test status
Simulation time 10073168320 ps
CPU time 13.04 seconds
Started Jun 05 05:44:39 PM PDT 24
Finished Jun 05 05:44:53 PM PDT 24
Peak memory 205696 kb
Host smart-7ae32d6c-82f0-47dc-a609-8ae5881c8bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31124
48343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.3112448343
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.1647651769
Short name T1813
Test name
Test status
Simulation time 19946006448 ps
CPU time 117.8 seconds
Started Jun 05 05:44:41 PM PDT 24
Finished Jun 05 05:46:40 PM PDT 24
Peak memory 205664 kb
Host smart-214626f4-3e52-490f-a589-d9efef3dd4b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16476
51769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.1647651769
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.1954499112
Short name T1667
Test name
Test status
Simulation time 18387466548 ps
CPU time 63.32 seconds
Started Jun 05 05:44:38 PM PDT 24
Finished Jun 05 05:45:42 PM PDT 24
Peak memory 205792 kb
Host smart-7899782b-261c-4201-8766-46ecc56874ad
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954499112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_
traffic.1954499112
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.3991941246
Short name T1308
Test name
Test status
Simulation time 10147281677 ps
CPU time 14.65 seconds
Started Jun 05 05:48:58 PM PDT 24
Finished Jun 05 05:49:14 PM PDT 24
Peak memory 205632 kb
Host smart-7c49d3e3-f69b-4be5-ae3e-37e3d0999392
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3991941246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.3991941246
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.2960751114
Short name T196
Test name
Test status
Simulation time 10071979980 ps
CPU time 13.22 seconds
Started Jun 05 05:48:54 PM PDT 24
Finished Jun 05 05:49:07 PM PDT 24
Peak memory 205692 kb
Host smart-7e9c44c8-ee98-43fd-a1dd-3fb1acfcbaa9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2960751114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.2960751114
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.2715915067
Short name T1624
Test name
Test status
Simulation time 10131940489 ps
CPU time 13.24 seconds
Started Jun 05 05:49:02 PM PDT 24
Finished Jun 05 05:49:16 PM PDT 24
Peak memory 205764 kb
Host smart-ae8ba5a6-9aae-487a-920e-3bfec5ee73dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27159
15067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.2715915067
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.2132655521
Short name T1877
Test name
Test status
Simulation time 13919453254 ps
CPU time 20.24 seconds
Started Jun 05 05:49:00 PM PDT 24
Finished Jun 05 05:49:20 PM PDT 24
Peak memory 205780 kb
Host smart-48bfe6cc-df69-41b9-93d1-6ee66e5c9c6c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2132655521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.2132655521
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.4212752777
Short name T1175
Test name
Test status
Simulation time 23284967565 ps
CPU time 27.24 seconds
Started Jun 05 05:48:58 PM PDT 24
Finished Jun 05 05:49:26 PM PDT 24
Peak memory 205640 kb
Host smart-c33910ff-05f7-4d7a-a205-bd8f60252687
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4212752777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.4212752777
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.675609577
Short name T1661
Test name
Test status
Simulation time 10108818958 ps
CPU time 14.83 seconds
Started Jun 05 05:48:47 PM PDT 24
Finished Jun 05 05:49:02 PM PDT 24
Peak memory 205676 kb
Host smart-fa79f941-bcc8-4782-a7a9-1d8c1056310c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67560
9577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.675609577
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.3268446003
Short name T1698
Test name
Test status
Simulation time 10115307528 ps
CPU time 12.61 seconds
Started Jun 05 05:48:49 PM PDT 24
Finished Jun 05 05:49:02 PM PDT 24
Peak memory 205676 kb
Host smart-9fb025ba-7d51-447c-b528-3aff310dfb54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32684
46003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.3268446003
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.4027972984
Short name T1173
Test name
Test status
Simulation time 10042571384 ps
CPU time 14.1 seconds
Started Jun 05 05:48:54 PM PDT 24
Finished Jun 05 05:49:09 PM PDT 24
Peak memory 205680 kb
Host smart-4c68d567-ef81-445b-85ce-75d3eb612621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40279
72984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.4027972984
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.845335240
Short name T1558
Test name
Test status
Simulation time 10051768834 ps
CPU time 16.65 seconds
Started Jun 05 05:48:47 PM PDT 24
Finished Jun 05 05:49:05 PM PDT 24
Peak memory 205656 kb
Host smart-477a419e-5b89-416e-8423-c15abfef1d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84533
5240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.845335240
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.3809023170
Short name T1701
Test name
Test status
Simulation time 10860819509 ps
CPU time 13.96 seconds
Started Jun 05 05:48:53 PM PDT 24
Finished Jun 05 05:49:07 PM PDT 24
Peak memory 205636 kb
Host smart-b9f13644-5fbe-4f48-912d-62ee587784cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38090
23170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.3809023170
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.945197082
Short name T760
Test name
Test status
Simulation time 10101167953 ps
CPU time 14.61 seconds
Started Jun 05 05:48:55 PM PDT 24
Finished Jun 05 05:49:11 PM PDT 24
Peak memory 205644 kb
Host smart-bc88934d-c371-4d81-935e-e144b74c8d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94519
7082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.945197082
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.1372230059
Short name T950
Test name
Test status
Simulation time 10154545893 ps
CPU time 13 seconds
Started Jun 05 05:48:48 PM PDT 24
Finished Jun 05 05:49:01 PM PDT 24
Peak memory 205696 kb
Host smart-ed8a6a7d-da92-4860-a746-95bdf97d2481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13722
30059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.1372230059
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.1295480652
Short name T1001
Test name
Test status
Simulation time 10051218697 ps
CPU time 13.54 seconds
Started Jun 05 05:48:49 PM PDT 24
Finished Jun 05 05:49:04 PM PDT 24
Peak memory 205684 kb
Host smart-06430b4f-ed83-4dea-aeb4-74a3fc6d6100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12954
80652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1295480652
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2253334452
Short name T1577
Test name
Test status
Simulation time 10194124323 ps
CPU time 13.46 seconds
Started Jun 05 05:48:50 PM PDT 24
Finished Jun 05 05:49:05 PM PDT 24
Peak memory 205756 kb
Host smart-606b85b6-fe50-47ca-9a86-cbd71ec3ce93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22533
34452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2253334452
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.2458426295
Short name T1981
Test name
Test status
Simulation time 10076404530 ps
CPU time 13.2 seconds
Started Jun 05 05:49:01 PM PDT 24
Finished Jun 05 05:49:15 PM PDT 24
Peak memory 205684 kb
Host smart-1da13a0d-27e3-4f17-b540-4e9841bbffd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24584
26295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.2458426295
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.4028699837
Short name T1187
Test name
Test status
Simulation time 13226208290 ps
CPU time 18.43 seconds
Started Jun 05 05:48:49 PM PDT 24
Finished Jun 05 05:49:08 PM PDT 24
Peak memory 205792 kb
Host smart-462ac5d7-a39d-4597-b1a6-3a4412592f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40286
99837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.4028699837
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.611869270
Short name T1230
Test name
Test status
Simulation time 10173917776 ps
CPU time 15.33 seconds
Started Jun 05 05:49:00 PM PDT 24
Finished Jun 05 05:49:15 PM PDT 24
Peak memory 205696 kb
Host smart-8378617d-8d18-492d-afa7-031d9f8c1431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61186
9270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.611869270
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.1580760984
Short name T372
Test name
Test status
Simulation time 21655761566 ps
CPU time 123.77 seconds
Started Jun 05 05:48:56 PM PDT 24
Finished Jun 05 05:51:01 PM PDT 24
Peak memory 205880 kb
Host smart-91cb5b18-be43-48c7-9b76-3da34a2bc514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15807
60984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.1580760984
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.1032219272
Short name T1122
Test name
Test status
Simulation time 10063761681 ps
CPU time 15.27 seconds
Started Jun 05 05:48:53 PM PDT 24
Finished Jun 05 05:49:09 PM PDT 24
Peak memory 205784 kb
Host smart-aaa9e2ba-ed61-4f87-be3b-d8bfb811f01c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10322
19272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.1032219272
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.3338594891
Short name T1382
Test name
Test status
Simulation time 10086166948 ps
CPU time 13.17 seconds
Started Jun 05 05:48:47 PM PDT 24
Finished Jun 05 05:49:01 PM PDT 24
Peak memory 205792 kb
Host smart-c0b24290-c29e-4083-a069-4167a29a6f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33385
94891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3338594891
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.4221615292
Short name T909
Test name
Test status
Simulation time 10072068397 ps
CPU time 12.86 seconds
Started Jun 05 05:49:00 PM PDT 24
Finished Jun 05 05:49:13 PM PDT 24
Peak memory 205812 kb
Host smart-c9573587-69c5-40c1-99b4-b239bb8d3e4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42216
15292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.4221615292
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.925977678
Short name T839
Test name
Test status
Simulation time 10150441538 ps
CPU time 15.86 seconds
Started Jun 05 05:48:53 PM PDT 24
Finished Jun 05 05:49:09 PM PDT 24
Peak memory 205680 kb
Host smart-9cfc7465-a256-4439-a6d4-a48704ecdfd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92597
7678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.925977678
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.3921546771
Short name T1502
Test name
Test status
Simulation time 10076523458 ps
CPU time 15.67 seconds
Started Jun 05 05:48:56 PM PDT 24
Finished Jun 05 05:49:12 PM PDT 24
Peak memory 205600 kb
Host smart-1d42ca43-08c4-4384-8663-b1cdf1e3254e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39215
46771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.3921546771
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.1694619580
Short name T643
Test name
Test status
Simulation time 10129568980 ps
CPU time 15.75 seconds
Started Jun 05 05:49:00 PM PDT 24
Finished Jun 05 05:49:16 PM PDT 24
Peak memory 205760 kb
Host smart-d4112453-e82e-4152-a6a5-7a1a0324342d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16946
19580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.1694619580
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_eop_single_bit_handling.2169929976
Short name T1338
Test name
Test status
Simulation time 10087481393 ps
CPU time 14.83 seconds
Started Jun 05 05:48:51 PM PDT 24
Finished Jun 05 05:49:07 PM PDT 24
Peak memory 205700 kb
Host smart-b2c01bbc-892b-4c8e-8c21-0e7e7e45e363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21699
29976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_eop_single_bit_handling.2169929976
Directory /workspace/40.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.3009000984
Short name T1935
Test name
Test status
Simulation time 10102294460 ps
CPU time 13.21 seconds
Started Jun 05 05:48:58 PM PDT 24
Finished Jun 05 05:49:12 PM PDT 24
Peak memory 205796 kb
Host smart-eab53254-b1d4-4f41-a2cb-b62722768858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30090
00984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.3009000984
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3057713935
Short name T1649
Test name
Test status
Simulation time 10046664969 ps
CPU time 12.58 seconds
Started Jun 05 05:48:47 PM PDT 24
Finished Jun 05 05:49:00 PM PDT 24
Peak memory 205748 kb
Host smart-94de8f60-7a3e-4303-a1c6-d562d3c1011c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30577
13935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3057713935
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.160658750
Short name T569
Test name
Test status
Simulation time 29436347317 ps
CPU time 54.71 seconds
Started Jun 05 05:48:47 PM PDT 24
Finished Jun 05 05:49:43 PM PDT 24
Peak memory 205676 kb
Host smart-8517d4f6-23c4-4885-98fa-e70a0df62908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16065
8750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.160658750
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.637154405
Short name T1259
Test name
Test status
Simulation time 10100989934 ps
CPU time 13.06 seconds
Started Jun 05 05:48:49 PM PDT 24
Finished Jun 05 05:49:03 PM PDT 24
Peak memory 205692 kb
Host smart-b594a7e2-df05-4994-b9dc-7b0ea7749f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63715
4405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.637154405
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.4187662119
Short name T1237
Test name
Test status
Simulation time 10100468006 ps
CPU time 14.43 seconds
Started Jun 05 05:48:54 PM PDT 24
Finished Jun 05 05:49:09 PM PDT 24
Peak memory 205792 kb
Host smart-1afa4c64-2509-4281-87c6-729c21b62eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41876
62119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.4187662119
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.1689361093
Short name T1786
Test name
Test status
Simulation time 10059485706 ps
CPU time 14.69 seconds
Started Jun 05 05:48:56 PM PDT 24
Finished Jun 05 05:49:11 PM PDT 24
Peak memory 205676 kb
Host smart-c8348a10-ddc8-41ba-a78c-54c364435067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16893
61093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.1689361093
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.2222008738
Short name T823
Test name
Test status
Simulation time 10060706600 ps
CPU time 12.97 seconds
Started Jun 05 05:48:47 PM PDT 24
Finished Jun 05 05:49:00 PM PDT 24
Peak memory 205668 kb
Host smart-3306ade3-9917-4b27-8731-710938815939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22220
08738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.2222008738
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.642820027
Short name T1250
Test name
Test status
Simulation time 10075101527 ps
CPU time 13.96 seconds
Started Jun 05 05:48:48 PM PDT 24
Finished Jun 05 05:49:03 PM PDT 24
Peak memory 205680 kb
Host smart-522f6db6-a909-48fe-b9d5-b8021aee3717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64282
0027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.642820027
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.4268765337
Short name T1124
Test name
Test status
Simulation time 10052850889 ps
CPU time 13.01 seconds
Started Jun 05 05:48:52 PM PDT 24
Finished Jun 05 05:49:06 PM PDT 24
Peak memory 205648 kb
Host smart-809530b2-3e40-4e49-8933-dd8f18458bda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42687
65337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.4268765337
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.901624610
Short name T144
Test name
Test status
Simulation time 10119213696 ps
CPU time 14.25 seconds
Started Jun 05 05:48:58 PM PDT 24
Finished Jun 05 05:49:13 PM PDT 24
Peak memory 205712 kb
Host smart-932ef79a-87ad-4ec5-842e-d11ce3d29ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90162
4610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.901624610
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.3246028380
Short name T1542
Test name
Test status
Simulation time 10166748249 ps
CPU time 13.78 seconds
Started Jun 05 05:48:49 PM PDT 24
Finished Jun 05 05:49:04 PM PDT 24
Peak memory 205780 kb
Host smart-d969608b-44da-4659-a34c-028b88cff07f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32460
28380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.3246028380
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1680136941
Short name T755
Test name
Test status
Simulation time 10075439283 ps
CPU time 13.11 seconds
Started Jun 05 05:48:48 PM PDT 24
Finished Jun 05 05:49:02 PM PDT 24
Peak memory 205752 kb
Host smart-8a7cd30d-d54d-455f-a594-1fb9bbc4e69c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16801
36941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1680136941
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.424463111
Short name T1519
Test name
Test status
Simulation time 20969019333 ps
CPU time 94.97 seconds
Started Jun 05 05:49:02 PM PDT 24
Finished Jun 05 05:50:38 PM PDT 24
Peak memory 205732 kb
Host smart-bec35e7e-988e-492b-8549-bed07f39340d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42446
3111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.424463111
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.1866969906
Short name T1907
Test name
Test status
Simulation time 10132367165 ps
CPU time 15.64 seconds
Started Jun 05 05:49:01 PM PDT 24
Finished Jun 05 05:49:18 PM PDT 24
Peak memory 205748 kb
Host smart-ceababe4-ff9e-43b2-a7c4-1630b4f15efa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1866969906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.1866969906
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.1877458679
Short name T1131
Test name
Test status
Simulation time 10087321318 ps
CPU time 12.78 seconds
Started Jun 05 05:49:02 PM PDT 24
Finished Jun 05 05:49:16 PM PDT 24
Peak memory 205760 kb
Host smart-6de6a868-a8e2-41ba-8ddd-b262260c4d87
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1877458679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.1877458679
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.1250466678
Short name T385
Test name
Test status
Simulation time 10077833444 ps
CPU time 14.11 seconds
Started Jun 05 05:49:03 PM PDT 24
Finished Jun 05 05:49:18 PM PDT 24
Peak memory 205728 kb
Host smart-39647cd9-efe6-4657-a349-92f3c72e2825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12504
66678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.1250466678
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.626137429
Short name T15
Test name
Test status
Simulation time 13991512166 ps
CPU time 17.51 seconds
Started Jun 05 05:48:48 PM PDT 24
Finished Jun 05 05:49:06 PM PDT 24
Peak memory 205796 kb
Host smart-1f966be7-3c0c-48f5-98cb-d6a4a9229032
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=626137429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.626137429
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.539311023
Short name T1951
Test name
Test status
Simulation time 23347835689 ps
CPU time 25.17 seconds
Started Jun 05 05:48:55 PM PDT 24
Finished Jun 05 05:49:21 PM PDT 24
Peak memory 205712 kb
Host smart-5779235f-db7d-4d5a-8b61-71a29b836167
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=539311023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.539311023
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1131398825
Short name T1608
Test name
Test status
Simulation time 10061276965 ps
CPU time 13.02 seconds
Started Jun 05 05:49:01 PM PDT 24
Finished Jun 05 05:49:15 PM PDT 24
Peak memory 205732 kb
Host smart-e2954a10-7c84-425d-af6a-5ef1f473104b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11313
98825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1131398825
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.2657825011
Short name T2011
Test name
Test status
Simulation time 10106874399 ps
CPU time 16.98 seconds
Started Jun 05 05:48:58 PM PDT 24
Finished Jun 05 05:49:16 PM PDT 24
Peak memory 205772 kb
Host smart-23249c74-94b7-48e0-b655-08a7f4c3f55e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26578
25011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.2657825011
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.287771781
Short name T1302
Test name
Test status
Simulation time 10871591396 ps
CPU time 17.32 seconds
Started Jun 05 05:49:00 PM PDT 24
Finished Jun 05 05:49:18 PM PDT 24
Peak memory 205772 kb
Host smart-fca2cb56-e93d-49a5-8101-0a96c5a19b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28777
1781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.287771781
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.4248668418
Short name T1752
Test name
Test status
Simulation time 10059037902 ps
CPU time 12.34 seconds
Started Jun 05 05:49:01 PM PDT 24
Finished Jun 05 05:49:14 PM PDT 24
Peak memory 205728 kb
Host smart-42205132-52a4-459c-97a5-01ca9f0b8745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42486
68418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.4248668418
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.3472448256
Short name T50
Test name
Test status
Simulation time 10057322210 ps
CPU time 17.21 seconds
Started Jun 05 05:48:52 PM PDT 24
Finished Jun 05 05:49:10 PM PDT 24
Peak memory 205684 kb
Host smart-488fa82a-3e84-472f-b373-d3abb3e9dcfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34724
48256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3472448256
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.570589356
Short name T1811
Test name
Test status
Simulation time 10838357050 ps
CPU time 15.36 seconds
Started Jun 05 05:48:50 PM PDT 24
Finished Jun 05 05:49:06 PM PDT 24
Peak memory 205688 kb
Host smart-4c90c43d-4ec7-4a2d-be1b-00486e7a7f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57058
9356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.570589356
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.1183593181
Short name T23
Test name
Test status
Simulation time 10162212466 ps
CPU time 14.13 seconds
Started Jun 05 05:49:07 PM PDT 24
Finished Jun 05 05:49:22 PM PDT 24
Peak memory 205800 kb
Host smart-cb313c92-fd3c-489a-a7af-76c81b621640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11835
93181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1183593181
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.2523201236
Short name T397
Test name
Test status
Simulation time 10113469957 ps
CPU time 13.06 seconds
Started Jun 05 05:49:05 PM PDT 24
Finished Jun 05 05:49:18 PM PDT 24
Peak memory 205648 kb
Host smart-ca77301f-e17b-4417-afa7-a2f8fd8e1044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25232
01236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.2523201236
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.188317847
Short name T719
Test name
Test status
Simulation time 10053447311 ps
CPU time 16.04 seconds
Started Jun 05 05:49:03 PM PDT 24
Finished Jun 05 05:49:20 PM PDT 24
Peak memory 205652 kb
Host smart-0451f1fa-90de-42a8-b8a3-1859e90bb6e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18831
7847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.188317847
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.4027848591
Short name T515
Test name
Test status
Simulation time 10112338709 ps
CPU time 13.46 seconds
Started Jun 05 05:48:56 PM PDT 24
Finished Jun 05 05:49:10 PM PDT 24
Peak memory 205684 kb
Host smart-438aea53-4652-4f0e-be9f-9ca340b7e892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40278
48591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.4027848591
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.3250775498
Short name T1534
Test name
Test status
Simulation time 10077563057 ps
CPU time 14.54 seconds
Started Jun 05 05:49:00 PM PDT 24
Finished Jun 05 05:49:15 PM PDT 24
Peak memory 206008 kb
Host smart-fdaec9ab-1636-4535-a70b-cf6907b27ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32507
75498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.3250775498
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.2453768226
Short name T2000
Test name
Test status
Simulation time 13164367459 ps
CPU time 18.73 seconds
Started Jun 05 05:49:02 PM PDT 24
Finished Jun 05 05:49:22 PM PDT 24
Peak memory 205724 kb
Host smart-546f6fb7-ecf5-42fe-9c7f-c43585b2feed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24537
68226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.2453768226
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.157242393
Short name T321
Test name
Test status
Simulation time 10092381727 ps
CPU time 17.24 seconds
Started Jun 05 05:48:57 PM PDT 24
Finished Jun 05 05:49:15 PM PDT 24
Peak memory 205764 kb
Host smart-4d9547b8-ea8f-439f-9bba-d8d9f9334f7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15724
2393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.157242393
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.1958728951
Short name T1912
Test name
Test status
Simulation time 23657691871 ps
CPU time 387.56 seconds
Started Jun 05 05:49:01 PM PDT 24
Finished Jun 05 05:55:30 PM PDT 24
Peak memory 205672 kb
Host smart-a0457fe6-601b-45a9-be8a-e07b1e056651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19587
28951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.1958728951
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.3462063685
Short name T505
Test name
Test status
Simulation time 10041753372 ps
CPU time 13.18 seconds
Started Jun 05 05:48:59 PM PDT 24
Finished Jun 05 05:49:13 PM PDT 24
Peak memory 205772 kb
Host smart-7454b3e7-d2ee-473d-9eeb-c947ba080e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34620
63685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.3462063685
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.1758381761
Short name T96
Test name
Test status
Simulation time 10192601836 ps
CPU time 13.42 seconds
Started Jun 05 05:49:03 PM PDT 24
Finished Jun 05 05:49:17 PM PDT 24
Peak memory 205736 kb
Host smart-af22f71a-1920-4172-b59a-a0ee93e9dc94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17583
81761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1758381761
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.726666642
Short name T1108
Test name
Test status
Simulation time 10109230528 ps
CPU time 14.64 seconds
Started Jun 05 05:49:03 PM PDT 24
Finished Jun 05 05:49:18 PM PDT 24
Peak memory 205660 kb
Host smart-c4eb9456-81c5-45fb-938c-e67d21ff84a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72666
6642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.726666642
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.1606257605
Short name T1163
Test name
Test status
Simulation time 10095167561 ps
CPU time 12.87 seconds
Started Jun 05 05:49:01 PM PDT 24
Finished Jun 05 05:49:15 PM PDT 24
Peak memory 205688 kb
Host smart-53e6d26d-a28b-4e2f-b9d9-3f7d0cf0eaeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16062
57605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.1606257605
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2450281048
Short name T1406
Test name
Test status
Simulation time 10073500452 ps
CPU time 15.09 seconds
Started Jun 05 05:48:59 PM PDT 24
Finished Jun 05 05:49:15 PM PDT 24
Peak memory 205656 kb
Host smart-d289d249-cbff-402f-b478-715f4c386b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24502
81048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2450281048
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3120723352
Short name T150
Test name
Test status
Simulation time 10081019852 ps
CPU time 12.79 seconds
Started Jun 05 05:49:02 PM PDT 24
Finished Jun 05 05:49:16 PM PDT 24
Peak memory 205748 kb
Host smart-220ca2a7-1dca-4bcd-b679-ecff365d465a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31207
23352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3120723352
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_eop_single_bit_handling.43978124
Short name T520
Test name
Test status
Simulation time 10082007650 ps
CPU time 15.19 seconds
Started Jun 05 05:49:01 PM PDT 24
Finished Jun 05 05:49:16 PM PDT 24
Peak memory 205708 kb
Host smart-9d7c6568-e0f7-4373-a649-598c7aa42d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43978
124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_eop_single_bit_handling.43978124
Directory /workspace/41.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.1676915646
Short name T889
Test name
Test status
Simulation time 10049326966 ps
CPU time 12.52 seconds
Started Jun 05 05:48:57 PM PDT 24
Finished Jun 05 05:49:10 PM PDT 24
Peak memory 205816 kb
Host smart-36bc1b5e-4910-4fe2-ad53-fa11ea202bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16769
15646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.1676915646
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3670452685
Short name T547
Test name
Test status
Simulation time 10083630195 ps
CPU time 13.52 seconds
Started Jun 05 05:49:00 PM PDT 24
Finished Jun 05 05:49:14 PM PDT 24
Peak memory 205616 kb
Host smart-e7b2e755-f91d-451c-bafc-9a6998d69955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36704
52685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3670452685
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.36681706
Short name T999
Test name
Test status
Simulation time 23699165351 ps
CPU time 43.66 seconds
Started Jun 05 05:48:59 PM PDT 24
Finished Jun 05 05:49:43 PM PDT 24
Peak memory 205588 kb
Host smart-271e0cd2-75e0-4c2a-97c8-b53fe78a1740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36681
706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.36681706
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1625082465
Short name T1208
Test name
Test status
Simulation time 10102879087 ps
CPU time 13.41 seconds
Started Jun 05 05:49:03 PM PDT 24
Finished Jun 05 05:49:18 PM PDT 24
Peak memory 205664 kb
Host smart-4ff53162-f629-49dd-a64a-1e4f77d91c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16250
82465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1625082465
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.1257498125
Short name T1432
Test name
Test status
Simulation time 10121509494 ps
CPU time 15.03 seconds
Started Jun 05 05:48:58 PM PDT 24
Finished Jun 05 05:49:14 PM PDT 24
Peak memory 205620 kb
Host smart-67ce3771-ce7f-4170-a913-301823338761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12574
98125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.1257498125
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.3297404258
Short name T929
Test name
Test status
Simulation time 10136122305 ps
CPU time 14.85 seconds
Started Jun 05 05:48:55 PM PDT 24
Finished Jun 05 05:49:11 PM PDT 24
Peak memory 205700 kb
Host smart-6ab1d05b-d4ee-4013-8ddd-5b5eaa1ef6ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32974
04258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.3297404258
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.1561801648
Short name T1839
Test name
Test status
Simulation time 10036570501 ps
CPU time 13.15 seconds
Started Jun 05 05:49:03 PM PDT 24
Finished Jun 05 05:49:17 PM PDT 24
Peak memory 205744 kb
Host smart-97bfb2c0-4fa1-499a-acc6-9e63750a931a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15618
01648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.1561801648
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.2166147622
Short name T138
Test name
Test status
Simulation time 10087020013 ps
CPU time 13.06 seconds
Started Jun 05 05:49:05 PM PDT 24
Finished Jun 05 05:49:19 PM PDT 24
Peak memory 205732 kb
Host smart-6045068c-6666-4d16-a346-bbcfcb4681a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21661
47622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.2166147622
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.1303730716
Short name T768
Test name
Test status
Simulation time 10126299452 ps
CPU time 13.05 seconds
Started Jun 05 05:49:01 PM PDT 24
Finished Jun 05 05:49:15 PM PDT 24
Peak memory 205760 kb
Host smart-138f17a5-7897-47ec-88ff-3099f89119d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13037
30716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.1303730716
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.242750811
Short name T1665
Test name
Test status
Simulation time 10103308783 ps
CPU time 13.06 seconds
Started Jun 05 05:48:57 PM PDT 24
Finished Jun 05 05:49:11 PM PDT 24
Peak memory 205684 kb
Host smart-58cce42d-7597-4afa-a3af-e9e6f9449a0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24275
0811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.242750811
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.1076718316
Short name T1670
Test name
Test status
Simulation time 10101168548 ps
CPU time 14.48 seconds
Started Jun 05 05:48:55 PM PDT 24
Finished Jun 05 05:49:10 PM PDT 24
Peak memory 205780 kb
Host smart-3b00e4d2-92de-4bda-98f0-399f4da079d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10767
18316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.1076718316
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.2037644903
Short name T1938
Test name
Test status
Simulation time 10053694197 ps
CPU time 13.46 seconds
Started Jun 05 05:48:57 PM PDT 24
Finished Jun 05 05:49:11 PM PDT 24
Peak memory 205664 kb
Host smart-434dfce6-3564-4696-9cdb-f6dac56d497e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20376
44903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.2037644903
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.2379398603
Short name T699
Test name
Test status
Simulation time 20610517950 ps
CPU time 322.38 seconds
Started Jun 05 05:48:58 PM PDT 24
Finished Jun 05 05:54:21 PM PDT 24
Peak memory 205540 kb
Host smart-fdbf0460-1666-4ace-9b82-e24dacf7392c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23793
98603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.2379398603
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.2003651222
Short name T2023
Test name
Test status
Simulation time 10150750234 ps
CPU time 14.67 seconds
Started Jun 05 05:49:09 PM PDT 24
Finished Jun 05 05:49:25 PM PDT 24
Peak memory 205804 kb
Host smart-d72f4028-56ac-429e-ad31-e269545d3a25
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2003651222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.2003651222
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.3081097821
Short name T1424
Test name
Test status
Simulation time 10086654613 ps
CPU time 13.66 seconds
Started Jun 05 05:49:07 PM PDT 24
Finished Jun 05 05:49:21 PM PDT 24
Peak memory 205772 kb
Host smart-243ddf99-476d-43b0-b15d-68b8cf3d705d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3081097821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.3081097821
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.958087333
Short name T731
Test name
Test status
Simulation time 10077206155 ps
CPU time 17.11 seconds
Started Jun 05 05:49:01 PM PDT 24
Finished Jun 05 05:49:19 PM PDT 24
Peak memory 205652 kb
Host smart-f93481b5-d705-42d9-82a6-07e5d0b24ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95808
7333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.958087333
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.3348218846
Short name T1840
Test name
Test status
Simulation time 13905172734 ps
CPU time 18.71 seconds
Started Jun 05 05:49:03 PM PDT 24
Finished Jun 05 05:49:23 PM PDT 24
Peak memory 205556 kb
Host smart-2bc72eb8-68d6-429e-9116-f1ec1011a321
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3348218846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.3348218846
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.666603015
Short name T1990
Test name
Test status
Simulation time 23237349411 ps
CPU time 27.55 seconds
Started Jun 05 05:49:09 PM PDT 24
Finished Jun 05 05:49:37 PM PDT 24
Peak memory 205820 kb
Host smart-d5035c2a-ae86-43f2-bc6d-e5f7a3b307cc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=666603015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.666603015
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.71386681
Short name T1090
Test name
Test status
Simulation time 10056384179 ps
CPU time 14.08 seconds
Started Jun 05 05:49:04 PM PDT 24
Finished Jun 05 05:49:19 PM PDT 24
Peak memory 205748 kb
Host smart-a68e3bac-c52e-4f8a-8a50-b316b6d1a123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71386
681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.71386681
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1786037334
Short name T163
Test name
Test status
Simulation time 11017195807 ps
CPU time 16.17 seconds
Started Jun 05 05:49:07 PM PDT 24
Finished Jun 05 05:49:23 PM PDT 24
Peak memory 205656 kb
Host smart-8018720c-6378-482a-84a3-5ec0c3812b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17860
37334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1786037334
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.1744135607
Short name T664
Test name
Test status
Simulation time 10086987874 ps
CPU time 15.01 seconds
Started Jun 05 05:49:09 PM PDT 24
Finished Jun 05 05:49:25 PM PDT 24
Peak memory 205756 kb
Host smart-ec0884e4-e35f-4c12-85e1-abc15dd6b8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17441
35607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.1744135607
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.342889339
Short name T471
Test name
Test status
Simulation time 10044589190 ps
CPU time 12.75 seconds
Started Jun 05 05:49:08 PM PDT 24
Finished Jun 05 05:49:21 PM PDT 24
Peak memory 205588 kb
Host smart-4aa4d53f-c197-48ab-ac32-1c43c79691c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34288
9339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.342889339
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.4148062826
Short name T1522
Test name
Test status
Simulation time 10924707332 ps
CPU time 16.25 seconds
Started Jun 05 05:49:08 PM PDT 24
Finished Jun 05 05:49:24 PM PDT 24
Peak memory 205736 kb
Host smart-fbb19c55-98a6-474f-9366-199f8439abd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41480
62826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.4148062826
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.707651523
Short name T501
Test name
Test status
Simulation time 10272591271 ps
CPU time 15.72 seconds
Started Jun 05 05:49:10 PM PDT 24
Finished Jun 05 05:49:27 PM PDT 24
Peak memory 205776 kb
Host smart-38e28234-7099-48f1-a339-7c76270e23e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70765
1523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.707651523
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.347900927
Short name T1652
Test name
Test status
Simulation time 10081303673 ps
CPU time 13.35 seconds
Started Jun 05 05:49:09 PM PDT 24
Finished Jun 05 05:49:23 PM PDT 24
Peak memory 205756 kb
Host smart-d1b0a56a-d1ad-4fe0-88f0-6d692f7bb816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34790
0927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.347900927
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.2065345567
Short name T829
Test name
Test status
Simulation time 10049182572 ps
CPU time 13.2 seconds
Started Jun 05 05:49:13 PM PDT 24
Finished Jun 05 05:49:27 PM PDT 24
Peak memory 205748 kb
Host smart-6854f3fd-8188-474f-ab33-75340e3b257f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20653
45567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2065345567
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2941867007
Short name T1707
Test name
Test status
Simulation time 10096531809 ps
CPU time 15.63 seconds
Started Jun 05 05:49:03 PM PDT 24
Finished Jun 05 05:49:19 PM PDT 24
Peak memory 205648 kb
Host smart-52f14c54-1da8-40f4-90a0-f3bc701014bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29418
67007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2941867007
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.1954461767
Short name T509
Test name
Test status
Simulation time 10148634695 ps
CPU time 15.86 seconds
Started Jun 05 05:49:04 PM PDT 24
Finished Jun 05 05:49:21 PM PDT 24
Peak memory 205764 kb
Host smart-0f77585d-dfb7-4d31-900b-26604a0ed32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19544
61767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.1954461767
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1088639304
Short name T508
Test name
Test status
Simulation time 13171931487 ps
CPU time 16.4 seconds
Started Jun 05 05:49:02 PM PDT 24
Finished Jun 05 05:49:19 PM PDT 24
Peak memory 205764 kb
Host smart-fa48bd77-e287-4bda-9097-54508b12848e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10886
39304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1088639304
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1850650939
Short name T1738
Test name
Test status
Simulation time 10118280579 ps
CPU time 13.25 seconds
Started Jun 05 05:49:04 PM PDT 24
Finished Jun 05 05:49:18 PM PDT 24
Peak memory 205676 kb
Host smart-0965164b-4fcb-4d7c-95e5-a9207e5a1871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18506
50939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1850650939
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.3534423719
Short name T1422
Test name
Test status
Simulation time 24403245142 ps
CPU time 150.59 seconds
Started Jun 05 05:49:07 PM PDT 24
Finished Jun 05 05:51:38 PM PDT 24
Peak memory 205668 kb
Host smart-627b4a2b-7bf5-41a7-88e2-d4e5aba90e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35344
23719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.3534423719
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.2113527439
Short name T1751
Test name
Test status
Simulation time 10095921684 ps
CPU time 14.25 seconds
Started Jun 05 05:49:06 PM PDT 24
Finished Jun 05 05:49:21 PM PDT 24
Peak memory 205768 kb
Host smart-239fa4a1-b2c8-49ea-ae0f-43c830d00f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21135
27439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.2113527439
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.2462352060
Short name T1754
Test name
Test status
Simulation time 10100019920 ps
CPU time 14.02 seconds
Started Jun 05 05:49:15 PM PDT 24
Finished Jun 05 05:49:30 PM PDT 24
Peak memory 205764 kb
Host smart-7aa7f5ef-ce99-430c-868a-c11cf5decf8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24623
52060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.2462352060
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.569606237
Short name T608
Test name
Test status
Simulation time 10118362553 ps
CPU time 12.96 seconds
Started Jun 05 05:49:09 PM PDT 24
Finished Jun 05 05:49:22 PM PDT 24
Peak memory 205648 kb
Host smart-3771a300-c6e6-4d9f-b536-0c9d5068b23b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56960
6237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.569606237
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3629355601
Short name T963
Test name
Test status
Simulation time 10063308031 ps
CPU time 13.27 seconds
Started Jun 05 05:49:05 PM PDT 24
Finished Jun 05 05:49:19 PM PDT 24
Peak memory 205684 kb
Host smart-b71123e4-183d-4607-b4dc-991806d19ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36293
55601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3629355601
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.2776557290
Short name T1745
Test name
Test status
Simulation time 10066278881 ps
CPU time 12.71 seconds
Started Jun 05 05:49:10 PM PDT 24
Finished Jun 05 05:49:24 PM PDT 24
Peak memory 205780 kb
Host smart-cc7bd11d-b899-4cde-a690-75b02657aed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27765
57290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2776557290
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3028922711
Short name T1340
Test name
Test status
Simulation time 10067587636 ps
CPU time 13.4 seconds
Started Jun 05 05:49:04 PM PDT 24
Finished Jun 05 05:49:19 PM PDT 24
Peak memory 205752 kb
Host smart-3679f942-ab76-45e6-9f5b-f7618ab187da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30289
22711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3028922711
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_eop_single_bit_handling.3083457421
Short name T943
Test name
Test status
Simulation time 10102083300 ps
CPU time 15.5 seconds
Started Jun 05 05:49:10 PM PDT 24
Finished Jun 05 05:49:26 PM PDT 24
Peak memory 205676 kb
Host smart-933ddc8f-b64a-4250-ad78-e89d83f36ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30834
57421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_eop_single_bit_handling.3083457421
Directory /workspace/42.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.1299946571
Short name T1256
Test name
Test status
Simulation time 10042345156 ps
CPU time 15.88 seconds
Started Jun 05 05:49:02 PM PDT 24
Finished Jun 05 05:49:19 PM PDT 24
Peak memory 205828 kb
Host smart-7b347a5f-bc81-43bb-9bf3-e87411ea00fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12999
46571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.1299946571
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.3523476985
Short name T581
Test name
Test status
Simulation time 10040196779 ps
CPU time 13.37 seconds
Started Jun 05 05:49:04 PM PDT 24
Finished Jun 05 05:49:18 PM PDT 24
Peak memory 205760 kb
Host smart-1db29310-15c5-4a2a-b3bb-1b567f065e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35234
76985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.3523476985
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.2277102249
Short name T1142
Test name
Test status
Simulation time 23510960302 ps
CPU time 39.41 seconds
Started Jun 05 05:49:06 PM PDT 24
Finished Jun 05 05:49:46 PM PDT 24
Peak memory 205688 kb
Host smart-9bf1ab75-f155-4df4-bf09-baa530d4459f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22771
02249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.2277102249
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.1512409428
Short name T1413
Test name
Test status
Simulation time 10074384745 ps
CPU time 13.49 seconds
Started Jun 05 05:49:09 PM PDT 24
Finished Jun 05 05:49:23 PM PDT 24
Peak memory 205764 kb
Host smart-9a246010-52bf-4802-9849-5102daadd07e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15124
09428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.1512409428
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.38154221
Short name T1109
Test name
Test status
Simulation time 10137093983 ps
CPU time 12.53 seconds
Started Jun 05 05:49:06 PM PDT 24
Finished Jun 05 05:49:20 PM PDT 24
Peak memory 205692 kb
Host smart-290991ec-874f-4169-a3de-2a25c2eaabb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38154
221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.38154221
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.1155730743
Short name T470
Test name
Test status
Simulation time 10074991430 ps
CPU time 13.32 seconds
Started Jun 05 05:49:14 PM PDT 24
Finished Jun 05 05:49:28 PM PDT 24
Peak memory 205700 kb
Host smart-6c9ac527-a5c4-4448-9d93-033a34ed946f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11557
30743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.1155730743
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1258533987
Short name T1821
Test name
Test status
Simulation time 10043994668 ps
CPU time 14.02 seconds
Started Jun 05 05:49:01 PM PDT 24
Finished Jun 05 05:49:16 PM PDT 24
Peak memory 205620 kb
Host smart-f139c344-a4b7-4728-9417-a30f44580e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12585
33987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1258533987
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.1705342080
Short name T1901
Test name
Test status
Simulation time 10064278925 ps
CPU time 15.54 seconds
Started Jun 05 05:49:00 PM PDT 24
Finished Jun 05 05:49:17 PM PDT 24
Peak memory 205664 kb
Host smart-0b6b349e-d9c3-4801-b484-2537bd251960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17053
42080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.1705342080
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.3047910627
Short name T1231
Test name
Test status
Simulation time 10049735624 ps
CPU time 12.69 seconds
Started Jun 05 05:49:02 PM PDT 24
Finished Jun 05 05:49:16 PM PDT 24
Peak memory 205748 kb
Host smart-80c70a67-5c77-4f31-8a3e-ea7b58102847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30479
10627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.3047910627
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2562202379
Short name T1092
Test name
Test status
Simulation time 10104323434 ps
CPU time 16.05 seconds
Started Jun 05 05:48:57 PM PDT 24
Finished Jun 05 05:49:13 PM PDT 24
Peak memory 205780 kb
Host smart-20f992b3-fdae-4e80-9f31-712cf6bf5463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25622
02379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2562202379
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.263010866
Short name T1832
Test name
Test status
Simulation time 10109930006 ps
CPU time 12.68 seconds
Started Jun 05 05:49:03 PM PDT 24
Finished Jun 05 05:49:16 PM PDT 24
Peak memory 205768 kb
Host smart-2ea31be6-489c-49e7-9ed4-99dbcb8ac0bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26301
0866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.263010866
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.514815657
Short name T600
Test name
Test status
Simulation time 10076552338 ps
CPU time 15.82 seconds
Started Jun 05 05:49:13 PM PDT 24
Finished Jun 05 05:49:29 PM PDT 24
Peak memory 205700 kb
Host smart-88ee9969-4ffa-473c-bdea-e872ac4bb72e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51481
5657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.514815657
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.3660121978
Short name T1188
Test name
Test status
Simulation time 20624106588 ps
CPU time 87.23 seconds
Started Jun 05 05:49:01 PM PDT 24
Finished Jun 05 05:50:29 PM PDT 24
Peak memory 205712 kb
Host smart-c17c8418-da46-4b21-9ca9-126d29f913d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36601
21978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.3660121978
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.4082191665
Short name T441
Test name
Test status
Simulation time 10156633515 ps
CPU time 13.03 seconds
Started Jun 05 05:49:10 PM PDT 24
Finished Jun 05 05:49:23 PM PDT 24
Peak memory 205748 kb
Host smart-c751ce6a-929d-4c7d-b94e-3c828c7dbe6f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4082191665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.4082191665
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.2736717637
Short name T1472
Test name
Test status
Simulation time 10053671600 ps
CPU time 12.96 seconds
Started Jun 05 05:49:12 PM PDT 24
Finished Jun 05 05:49:25 PM PDT 24
Peak memory 205808 kb
Host smart-0cf76dd0-c507-403e-8afa-5795dccd3664
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2736717637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.2736717637
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.2831370295
Short name T1489
Test name
Test status
Simulation time 10090982499 ps
CPU time 15.75 seconds
Started Jun 05 05:49:11 PM PDT 24
Finished Jun 05 05:49:28 PM PDT 24
Peak memory 205756 kb
Host smart-812e0dee-0158-43ab-8ab2-90fba77bc417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28313
70295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.2831370295
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.1894186453
Short name T1364
Test name
Test status
Simulation time 13724277445 ps
CPU time 16.58 seconds
Started Jun 05 05:49:01 PM PDT 24
Finished Jun 05 05:49:18 PM PDT 24
Peak memory 205752 kb
Host smart-95031df1-c023-422d-9f57-1135bfa6c353
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1894186453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.1894186453
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.2714923281
Short name T774
Test name
Test status
Simulation time 23434945763 ps
CPU time 27.13 seconds
Started Jun 05 05:49:01 PM PDT 24
Finished Jun 05 05:49:30 PM PDT 24
Peak memory 205736 kb
Host smart-cb9918ce-e6a5-4cde-83f3-77d32c24eecd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2714923281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.2714923281
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.888693541
Short name T1618
Test name
Test status
Simulation time 10054142581 ps
CPU time 14.38 seconds
Started Jun 05 05:49:07 PM PDT 24
Finished Jun 05 05:49:22 PM PDT 24
Peak memory 205788 kb
Host smart-bf659332-03df-463e-92a5-125254360313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88869
3541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.888693541
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.2799210563
Short name T1875
Test name
Test status
Simulation time 10034093233 ps
CPU time 13.43 seconds
Started Jun 05 05:49:09 PM PDT 24
Finished Jun 05 05:49:23 PM PDT 24
Peak memory 205740 kb
Host smart-4ab5142a-3a91-45a5-8514-f33de09128b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27992
10563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.2799210563
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.2275640016
Short name T1292
Test name
Test status
Simulation time 10050416593 ps
CPU time 16.91 seconds
Started Jun 05 05:49:09 PM PDT 24
Finished Jun 05 05:49:27 PM PDT 24
Peak memory 205652 kb
Host smart-d0b36cc7-e2c8-41d7-a05f-3040479b6c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22756
40016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.2275640016
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.977149889
Short name T703
Test name
Test status
Simulation time 10802152590 ps
CPU time 16.46 seconds
Started Jun 05 05:49:10 PM PDT 24
Finished Jun 05 05:49:28 PM PDT 24
Peak memory 205704 kb
Host smart-7a96a7a5-3450-4156-a954-28b74d4e0e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97714
9889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.977149889
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.448085187
Short name T767
Test name
Test status
Simulation time 10151500608 ps
CPU time 15.01 seconds
Started Jun 05 05:49:08 PM PDT 24
Finished Jun 05 05:49:24 PM PDT 24
Peak memory 205732 kb
Host smart-3b06e28b-dc3b-4032-a5b7-f474cbad4f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44808
5187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.448085187
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.1937074625
Short name T1977
Test name
Test status
Simulation time 10144265675 ps
CPU time 13.29 seconds
Started Jun 05 05:49:08 PM PDT 24
Finished Jun 05 05:49:22 PM PDT 24
Peak memory 205856 kb
Host smart-0a2074a2-93e6-45e2-b216-bb8f896f34a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19370
74625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.1937074625
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.1899772628
Short name T1153
Test name
Test status
Simulation time 10066958837 ps
CPU time 15.01 seconds
Started Jun 05 05:49:15 PM PDT 24
Finished Jun 05 05:49:30 PM PDT 24
Peak memory 205648 kb
Host smart-cce97355-c1c4-4303-8ef7-08624a985372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18997
72628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.1899772628
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3849898618
Short name T1688
Test name
Test status
Simulation time 10084582311 ps
CPU time 13.8 seconds
Started Jun 05 05:49:11 PM PDT 24
Finished Jun 05 05:49:26 PM PDT 24
Peak memory 205684 kb
Host smart-16fc18bd-cf87-47a4-a1d3-8b2daea9f7fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38498
98618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3849898618
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.3450212141
Short name T334
Test name
Test status
Simulation time 10076029819 ps
CPU time 13.29 seconds
Started Jun 05 05:49:11 PM PDT 24
Finished Jun 05 05:49:25 PM PDT 24
Peak memory 205764 kb
Host smart-6fd79c7d-59d5-43dd-919b-d2ecbdf0596f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34502
12141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.3450212141
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.3564595334
Short name T1632
Test name
Test status
Simulation time 13200722952 ps
CPU time 16.97 seconds
Started Jun 05 05:49:16 PM PDT 24
Finished Jun 05 05:49:34 PM PDT 24
Peak memory 205760 kb
Host smart-0918481d-db08-4ed7-8f46-97d900e38ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35645
95334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.3564595334
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.3488960190
Short name T973
Test name
Test status
Simulation time 10091372333 ps
CPU time 13.92 seconds
Started Jun 05 05:49:09 PM PDT 24
Finished Jun 05 05:49:23 PM PDT 24
Peak memory 205688 kb
Host smart-7b690c69-420e-4a76-86d5-0bf2fdb3fda9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34889
60190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.3488960190
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.334676058
Short name T323
Test name
Test status
Simulation time 25333031058 ps
CPU time 450.7 seconds
Started Jun 05 05:49:10 PM PDT 24
Finished Jun 05 05:56:41 PM PDT 24
Peak memory 205680 kb
Host smart-5a94380b-6d54-45d8-936c-3dbada0c6fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33467
6058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.334676058
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2022872491
Short name T1042
Test name
Test status
Simulation time 10060534224 ps
CPU time 16.38 seconds
Started Jun 05 05:49:16 PM PDT 24
Finished Jun 05 05:49:33 PM PDT 24
Peak memory 205672 kb
Host smart-8127dedc-c29b-479a-9b0f-02f044372f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20228
72491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2022872491
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.3135583112
Short name T54
Test name
Test status
Simulation time 10120720798 ps
CPU time 16.74 seconds
Started Jun 05 05:49:13 PM PDT 24
Finished Jun 05 05:49:30 PM PDT 24
Peak memory 205716 kb
Host smart-b6d19f22-ab5d-42c6-b659-2a2d4fd0a372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31355
83112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.3135583112
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2785446894
Short name T1206
Test name
Test status
Simulation time 10085158244 ps
CPU time 16.1 seconds
Started Jun 05 05:49:08 PM PDT 24
Finished Jun 05 05:49:24 PM PDT 24
Peak memory 205900 kb
Host smart-c78de34c-83a6-4afe-bb84-ed9a3c866fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27854
46894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2785446894
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.3955072290
Short name T1727
Test name
Test status
Simulation time 10053081186 ps
CPU time 15.78 seconds
Started Jun 05 05:49:11 PM PDT 24
Finished Jun 05 05:49:27 PM PDT 24
Peak memory 205652 kb
Host smart-f0b74087-b68e-42ad-8099-2db03379e80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39550
72290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.3955072290
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.690026428
Short name T1176
Test name
Test status
Simulation time 10052057811 ps
CPU time 13.65 seconds
Started Jun 05 05:49:09 PM PDT 24
Finished Jun 05 05:49:23 PM PDT 24
Peak memory 205764 kb
Host smart-e0b71680-2b7d-41ea-9e99-3b39ad2d528d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69002
6428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.690026428
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.3576648662
Short name T739
Test name
Test status
Simulation time 10064358496 ps
CPU time 13.25 seconds
Started Jun 05 05:49:20 PM PDT 24
Finished Jun 05 05:49:33 PM PDT 24
Peak memory 205700 kb
Host smart-4208bdae-6d7d-47f9-8f4b-2df595723178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35766
48662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.3576648662
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_eop_single_bit_handling.3157861662
Short name T1412
Test name
Test status
Simulation time 10154219679 ps
CPU time 14.33 seconds
Started Jun 05 05:49:10 PM PDT 24
Finished Jun 05 05:49:25 PM PDT 24
Peak memory 205688 kb
Host smart-af2b4b24-9172-4fb8-8276-8163bcdc5527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31578
61662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_eop_single_bit_handling.3157861662
Directory /workspace/43.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.543186250
Short name T1737
Test name
Test status
Simulation time 10148306909 ps
CPU time 13.29 seconds
Started Jun 05 05:49:15 PM PDT 24
Finished Jun 05 05:49:29 PM PDT 24
Peak memory 205652 kb
Host smart-a61ab612-4adb-4813-b747-c69a91158aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54318
6250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.543186250
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.2030079560
Short name T1076
Test name
Test status
Simulation time 10036613871 ps
CPU time 13.25 seconds
Started Jun 05 05:49:13 PM PDT 24
Finished Jun 05 05:49:27 PM PDT 24
Peak memory 205740 kb
Host smart-de249965-1e88-42ba-b028-1d44a9524e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20300
79560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.2030079560
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.114835025
Short name T166
Test name
Test status
Simulation time 31289688467 ps
CPU time 60.75 seconds
Started Jun 05 05:49:18 PM PDT 24
Finished Jun 05 05:50:19 PM PDT 24
Peak memory 205536 kb
Host smart-3feb0ccd-e48e-49bb-9993-d9b74aefc155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11483
5025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.114835025
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.1949357125
Short name T679
Test name
Test status
Simulation time 10090122147 ps
CPU time 16.18 seconds
Started Jun 05 05:49:13 PM PDT 24
Finished Jun 05 05:49:30 PM PDT 24
Peak memory 205764 kb
Host smart-294fd9ba-6d23-4c83-a36a-6b9e8227034b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19493
57125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.1949357125
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3238180528
Short name T1144
Test name
Test status
Simulation time 10108313574 ps
CPU time 12.66 seconds
Started Jun 05 05:49:10 PM PDT 24
Finished Jun 05 05:49:24 PM PDT 24
Peak memory 205668 kb
Host smart-43054a87-8069-4488-95be-ef05fdd4baa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32381
80528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3238180528
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.456216394
Short name T297
Test name
Test status
Simulation time 10096987643 ps
CPU time 13.46 seconds
Started Jun 05 05:49:09 PM PDT 24
Finished Jun 05 05:49:23 PM PDT 24
Peak memory 205672 kb
Host smart-60e34048-a8fa-43ee-bb8d-66678ae8d632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45621
6394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.456216394
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.3208767417
Short name T1563
Test name
Test status
Simulation time 10056043250 ps
CPU time 14.92 seconds
Started Jun 05 05:49:11 PM PDT 24
Finished Jun 05 05:49:27 PM PDT 24
Peak memory 205516 kb
Host smart-251a3357-85e9-4a25-9f11-d3bc7389e2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32087
67417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.3208767417
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.1458291140
Short name T1262
Test name
Test status
Simulation time 10044877059 ps
CPU time 13.73 seconds
Started Jun 05 05:49:11 PM PDT 24
Finished Jun 05 05:49:26 PM PDT 24
Peak memory 205636 kb
Host smart-116f3472-8594-4d47-919f-871d5ffa8eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14582
91140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.1458291140
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2588934210
Short name T75
Test name
Test status
Simulation time 10051953498 ps
CPU time 15.55 seconds
Started Jun 05 05:49:11 PM PDT 24
Finished Jun 05 05:49:27 PM PDT 24
Peak memory 205600 kb
Host smart-16686ea4-964b-4a2c-a88d-4239e0d79730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25889
34210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2588934210
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1614416139
Short name T134
Test name
Test status
Simulation time 10096680690 ps
CPU time 13.65 seconds
Started Jun 05 05:49:06 PM PDT 24
Finished Jun 05 05:49:20 PM PDT 24
Peak memory 205680 kb
Host smart-891f28ba-b41e-42da-b9ad-cb74145bc475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16144
16139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1614416139
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.3205292667
Short name T857
Test name
Test status
Simulation time 10052673826 ps
CPU time 14.16 seconds
Started Jun 05 05:49:09 PM PDT 24
Finished Jun 05 05:49:24 PM PDT 24
Peak memory 205744 kb
Host smart-0ccc4888-af2a-4ea5-afd5-29ce8c326bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32052
92667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.3205292667
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.593427789
Short name T783
Test name
Test status
Simulation time 10085095758 ps
CPU time 12.94 seconds
Started Jun 05 05:49:11 PM PDT 24
Finished Jun 05 05:49:25 PM PDT 24
Peak memory 205728 kb
Host smart-ef0f717f-d1d3-425f-b72a-d434dfdddcaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59342
7789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.593427789
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.2963486794
Short name T717
Test name
Test status
Simulation time 14536080797 ps
CPU time 47.44 seconds
Started Jun 05 05:49:09 PM PDT 24
Finished Jun 05 05:49:57 PM PDT 24
Peak memory 205704 kb
Host smart-ad90b84e-c121-4e9b-ae6d-e1deaa7f5533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29634
86794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.2963486794
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.938324953
Short name T1328
Test name
Test status
Simulation time 10182074609 ps
CPU time 13.49 seconds
Started Jun 05 05:49:19 PM PDT 24
Finished Jun 05 05:49:33 PM PDT 24
Peak memory 205620 kb
Host smart-b0e1dae0-b6a8-4345-add8-b046d0d73382
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=938324953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.938324953
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.3872444308
Short name T1576
Test name
Test status
Simulation time 10063262559 ps
CPU time 13.98 seconds
Started Jun 05 05:49:13 PM PDT 24
Finished Jun 05 05:49:28 PM PDT 24
Peak memory 205724 kb
Host smart-9e1bf13a-98e1-4b4a-bb57-abbbf13dcad7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3872444308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.3872444308
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.3615997277
Short name T1194
Test name
Test status
Simulation time 10099378485 ps
CPU time 14.37 seconds
Started Jun 05 05:49:16 PM PDT 24
Finished Jun 05 05:49:31 PM PDT 24
Peak memory 205648 kb
Host smart-48c3f9cd-d483-4a66-b49c-72e6d9cd1e54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36159
97277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.3615997277
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.3439152628
Short name T631
Test name
Test status
Simulation time 14202047935 ps
CPU time 18.07 seconds
Started Jun 05 05:49:12 PM PDT 24
Finished Jun 05 05:49:31 PM PDT 24
Peak memory 205688 kb
Host smart-8baafdcd-ffef-4950-bab0-fa559a4663a4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3439152628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.3439152628
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.4258015819
Short name T1552
Test name
Test status
Simulation time 23241888020 ps
CPU time 29.81 seconds
Started Jun 05 05:49:12 PM PDT 24
Finished Jun 05 05:49:42 PM PDT 24
Peak memory 205640 kb
Host smart-f69cf774-ab8a-41cf-9131-2ff79d358604
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4258015819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.4258015819
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.159252083
Short name T563
Test name
Test status
Simulation time 10078590391 ps
CPU time 14.78 seconds
Started Jun 05 05:49:20 PM PDT 24
Finished Jun 05 05:49:35 PM PDT 24
Peak memory 205716 kb
Host smart-4d1eeed4-3ea0-451a-8c49-0af885ab2859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15925
2083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.159252083
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.2000501340
Short name T58
Test name
Test status
Simulation time 10070916327 ps
CPU time 13.68 seconds
Started Jun 05 05:49:10 PM PDT 24
Finished Jun 05 05:49:25 PM PDT 24
Peak memory 205732 kb
Host smart-b6da8ea9-18cb-4c43-94db-c3df2e03b5f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20005
01340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.2000501340
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.1100617698
Short name T62
Test name
Test status
Simulation time 10735042434 ps
CPU time 13.99 seconds
Started Jun 05 05:49:09 PM PDT 24
Finished Jun 05 05:49:24 PM PDT 24
Peak memory 205696 kb
Host smart-a7418d0c-21d0-4bba-a14b-174263edd8a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11006
17698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.1100617698
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.1710106636
Short name T410
Test name
Test status
Simulation time 10044041395 ps
CPU time 13.44 seconds
Started Jun 05 05:49:13 PM PDT 24
Finished Jun 05 05:49:27 PM PDT 24
Peak memory 205700 kb
Host smart-437f0c10-b1b0-486b-8380-2dac145b4a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17101
06636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.1710106636
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.3414173344
Short name T1073
Test name
Test status
Simulation time 10061809640 ps
CPU time 15.65 seconds
Started Jun 05 05:49:10 PM PDT 24
Finished Jun 05 05:49:27 PM PDT 24
Peak memory 205732 kb
Host smart-466fd7c6-50af-4e4c-9f4c-bf33efc1f6df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34141
73344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.3414173344
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.646940493
Short name T435
Test name
Test status
Simulation time 10853974053 ps
CPU time 16.71 seconds
Started Jun 05 05:49:17 PM PDT 24
Finished Jun 05 05:49:34 PM PDT 24
Peak memory 205628 kb
Host smart-dbfacf66-fbc1-45c9-9fff-e2b6d39ca897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64694
0493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.646940493
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.3975106640
Short name T258
Test name
Test status
Simulation time 10278756404 ps
CPU time 14.89 seconds
Started Jun 05 05:49:11 PM PDT 24
Finished Jun 05 05:49:26 PM PDT 24
Peak memory 205672 kb
Host smart-cb071337-e53a-4351-b772-a93fe881183b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39751
06640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.3975106640
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.1466595586
Short name T766
Test name
Test status
Simulation time 10098315361 ps
CPU time 16 seconds
Started Jun 05 05:49:22 PM PDT 24
Finished Jun 05 05:49:39 PM PDT 24
Peak memory 205632 kb
Host smart-499f19f5-981e-4932-b40c-8cef924d1eab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14665
95586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.1466595586
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2706521562
Short name T1668
Test name
Test status
Simulation time 10133813692 ps
CPU time 13.84 seconds
Started Jun 05 05:49:17 PM PDT 24
Finished Jun 05 05:49:31 PM PDT 24
Peak memory 205728 kb
Host smart-dccb4050-9bfd-4a78-94ed-72e4ff99d37f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27065
21562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2706521562
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.1481973948
Short name T751
Test name
Test status
Simulation time 10067712475 ps
CPU time 14.42 seconds
Started Jun 05 05:49:19 PM PDT 24
Finished Jun 05 05:49:34 PM PDT 24
Peak memory 205728 kb
Host smart-1a6e5d10-faca-4c51-a33c-c98cc5ca7654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14819
73948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.1481973948
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.1321545112
Short name T370
Test name
Test status
Simulation time 10115057846 ps
CPU time 13.43 seconds
Started Jun 05 05:49:17 PM PDT 24
Finished Jun 05 05:49:31 PM PDT 24
Peak memory 205652 kb
Host smart-75809898-0bf4-4e6c-baee-ee988e809794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13215
45112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.1321545112
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.3534423388
Short name T1724
Test name
Test status
Simulation time 13229475492 ps
CPU time 15.11 seconds
Started Jun 05 05:49:16 PM PDT 24
Finished Jun 05 05:49:32 PM PDT 24
Peak memory 205764 kb
Host smart-58fd9bbe-2f59-4b32-877e-965efd41f553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35344
23388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.3534423388
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.19892185
Short name T634
Test name
Test status
Simulation time 10161453583 ps
CPU time 16.67 seconds
Started Jun 05 05:49:19 PM PDT 24
Finished Jun 05 05:49:37 PM PDT 24
Peak memory 205648 kb
Host smart-1f8694b7-4e06-42ef-a5a2-eb51e60ed25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19892
185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.19892185
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.1564074861
Short name T1410
Test name
Test status
Simulation time 21677487203 ps
CPU time 97.17 seconds
Started Jun 05 05:49:21 PM PDT 24
Finished Jun 05 05:50:58 PM PDT 24
Peak memory 205912 kb
Host smart-1a3008a3-9de0-40ed-abfd-5e72c46549a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15640
74861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.1564074861
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.663377469
Short name T1470
Test name
Test status
Simulation time 10097891811 ps
CPU time 13.35 seconds
Started Jun 05 05:49:23 PM PDT 24
Finished Jun 05 05:49:37 PM PDT 24
Peak memory 205784 kb
Host smart-de18e130-23c8-4525-8fef-251e38e4194d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66337
7469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.663377469
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.816135250
Short name T1210
Test name
Test status
Simulation time 10079368261 ps
CPU time 13.86 seconds
Started Jun 05 05:49:21 PM PDT 24
Finished Jun 05 05:49:35 PM PDT 24
Peak memory 205712 kb
Host smart-11381cdf-4c11-457e-899a-edd95b5e8720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81613
5250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.816135250
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.2537027027
Short name T725
Test name
Test status
Simulation time 10091199160 ps
CPU time 15.33 seconds
Started Jun 05 05:49:14 PM PDT 24
Finished Jun 05 05:49:30 PM PDT 24
Peak memory 205980 kb
Host smart-63877de5-efe8-4dba-9bff-68baba4d424a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25370
27027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2537027027
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3839205385
Short name T780
Test name
Test status
Simulation time 10076065645 ps
CPU time 12.86 seconds
Started Jun 05 05:49:19 PM PDT 24
Finished Jun 05 05:49:32 PM PDT 24
Peak memory 205736 kb
Host smart-1b3b2e83-1c50-4fbc-b10b-628e366b46a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38392
05385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3839205385
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3537905284
Short name T960
Test name
Test status
Simulation time 10091115065 ps
CPU time 14.71 seconds
Started Jun 05 05:49:25 PM PDT 24
Finished Jun 05 05:49:41 PM PDT 24
Peak memory 205624 kb
Host smart-6be0ffbb-a059-4d11-a9a3-5087a1a5f251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35379
05284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3537905284
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.159370300
Short name T1623
Test name
Test status
Simulation time 10056509967 ps
CPU time 16.24 seconds
Started Jun 05 05:49:25 PM PDT 24
Finished Jun 05 05:49:42 PM PDT 24
Peak memory 205792 kb
Host smart-e7c1a856-84bd-4810-bcad-485a9ffa3306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15937
0300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.159370300
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_eop_single_bit_handling.567196402
Short name T482
Test name
Test status
Simulation time 10076464534 ps
CPU time 12.68 seconds
Started Jun 05 05:49:15 PM PDT 24
Finished Jun 05 05:49:29 PM PDT 24
Peak memory 205696 kb
Host smart-dfb6b1de-2036-4b3d-940f-5c7d55747cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56719
6402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_eop_single_bit_handling.567196402
Directory /workspace/44.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1745499244
Short name T931
Test name
Test status
Simulation time 10091108780 ps
CPU time 13.16 seconds
Started Jun 05 05:49:22 PM PDT 24
Finished Jun 05 05:49:36 PM PDT 24
Peak memory 205756 kb
Host smart-46dbc366-c948-44dc-8c72-ab8e423eaf87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17454
99244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1745499244
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.46689106
Short name T944
Test name
Test status
Simulation time 10030662790 ps
CPU time 13.81 seconds
Started Jun 05 05:49:24 PM PDT 24
Finished Jun 05 05:49:39 PM PDT 24
Peak memory 205712 kb
Host smart-fa7443d6-50cb-44c6-b4e5-536cec477262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46689
106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.46689106
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.1731996823
Short name T809
Test name
Test status
Simulation time 20900032876 ps
CPU time 37.7 seconds
Started Jun 05 05:49:20 PM PDT 24
Finished Jun 05 05:49:58 PM PDT 24
Peak memory 205644 kb
Host smart-5b661fcc-2241-4f47-ad12-7d4e667896f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17319
96823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.1731996823
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.3084279167
Short name T801
Test name
Test status
Simulation time 10116445632 ps
CPU time 13.1 seconds
Started Jun 05 05:49:19 PM PDT 24
Finished Jun 05 05:49:33 PM PDT 24
Peak memory 205672 kb
Host smart-ede501ce-6ff1-42d0-bfb8-ae6410e5b199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30842
79167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.3084279167
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.2771622612
Short name T708
Test name
Test status
Simulation time 10113135837 ps
CPU time 13.28 seconds
Started Jun 05 05:49:16 PM PDT 24
Finished Jun 05 05:49:30 PM PDT 24
Peak memory 205692 kb
Host smart-ceadd700-db5a-4a70-a131-70d939492eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27716
22612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2771622612
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.3644643986
Short name T1168
Test name
Test status
Simulation time 10089524123 ps
CPU time 13.69 seconds
Started Jun 05 05:49:22 PM PDT 24
Finished Jun 05 05:49:36 PM PDT 24
Peak memory 205660 kb
Host smart-65149448-7a5f-4c1f-8fbd-d3a7a434e0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36446
43986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.3644643986
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.4241934047
Short name T360
Test name
Test status
Simulation time 10049939684 ps
CPU time 13.62 seconds
Started Jun 05 05:49:17 PM PDT 24
Finished Jun 05 05:49:31 PM PDT 24
Peak memory 205648 kb
Host smart-ebaddd02-95de-4f61-84bc-160f09394c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42419
34047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.4241934047
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.1846908982
Short name T1965
Test name
Test status
Simulation time 10075938074 ps
CPU time 16.18 seconds
Started Jun 05 05:49:23 PM PDT 24
Finished Jun 05 05:49:40 PM PDT 24
Peak memory 205712 kb
Host smart-eb0ccde1-43a2-48b8-95dc-c3c4919bf522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18469
08982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.1846908982
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3649828623
Short name T1318
Test name
Test status
Simulation time 10054702710 ps
CPU time 13.14 seconds
Started Jun 05 05:49:20 PM PDT 24
Finished Jun 05 05:49:34 PM PDT 24
Peak memory 205584 kb
Host smart-f4935809-069c-499a-b2b9-ea3411fd2556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36498
28623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3649828623
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.3498347238
Short name T1034
Test name
Test status
Simulation time 10138379289 ps
CPU time 15.75 seconds
Started Jun 05 05:49:11 PM PDT 24
Finished Jun 05 05:49:28 PM PDT 24
Peak memory 205776 kb
Host smart-418ada5a-72a7-4bf8-b6c9-9c5360c3b245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34983
47238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.3498347238
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.3278623327
Short name T648
Test name
Test status
Simulation time 10132760731 ps
CPU time 12.66 seconds
Started Jun 05 05:49:17 PM PDT 24
Finished Jun 05 05:49:30 PM PDT 24
Peak memory 205752 kb
Host smart-037ce06b-4a5b-4a83-83a0-268388296b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32786
23327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.3278623327
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.1898049712
Short name T415
Test name
Test status
Simulation time 10106674302 ps
CPU time 12.67 seconds
Started Jun 05 05:49:16 PM PDT 24
Finished Jun 05 05:49:29 PM PDT 24
Peak memory 205684 kb
Host smart-64d24eed-8737-4251-bafb-c50d7296088b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18980
49712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.1898049712
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.2946711505
Short name T902
Test name
Test status
Simulation time 17222813883 ps
CPU time 63.8 seconds
Started Jun 05 05:49:18 PM PDT 24
Finished Jun 05 05:50:23 PM PDT 24
Peak memory 205664 kb
Host smart-5e7138f4-7c9e-423f-bfe4-a9376ab6e7a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29467
11505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.2946711505
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.3598599977
Short name T693
Test name
Test status
Simulation time 10147691953 ps
CPU time 14.95 seconds
Started Jun 05 05:49:22 PM PDT 24
Finished Jun 05 05:49:37 PM PDT 24
Peak memory 205728 kb
Host smart-db2e70b0-6e99-432d-be64-120a0f9e3cf3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3598599977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.3598599977
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.1817051446
Short name T736
Test name
Test status
Simulation time 10063348564 ps
CPU time 14.68 seconds
Started Jun 05 05:49:25 PM PDT 24
Finished Jun 05 05:49:40 PM PDT 24
Peak memory 205796 kb
Host smart-684db662-3fe7-4f9e-aa3c-243d831b7696
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1817051446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.1817051446
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.2790025688
Short name T1774
Test name
Test status
Simulation time 10096792430 ps
CPU time 13.81 seconds
Started Jun 05 05:49:24 PM PDT 24
Finished Jun 05 05:49:39 PM PDT 24
Peak memory 205668 kb
Host smart-85d098f2-d21c-4f33-9a80-0fa248551c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27900
25688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.2790025688
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.3605418672
Short name T553
Test name
Test status
Simulation time 14300029217 ps
CPU time 16.87 seconds
Started Jun 05 05:49:18 PM PDT 24
Finished Jun 05 05:49:36 PM PDT 24
Peak memory 205732 kb
Host smart-97e407ad-4208-44c9-a55f-b29161c5e36d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3605418672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.3605418672
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.2481184172
Short name T1645
Test name
Test status
Simulation time 23287277654 ps
CPU time 31.28 seconds
Started Jun 05 05:49:19 PM PDT 24
Finished Jun 05 05:49:51 PM PDT 24
Peak memory 205756 kb
Host smart-051b96a6-3f61-4470-898c-651882eeb88c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2481184172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.2481184172
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.2530430176
Short name T1857
Test name
Test status
Simulation time 10057924645 ps
CPU time 13.86 seconds
Started Jun 05 05:49:21 PM PDT 24
Finished Jun 05 05:49:36 PM PDT 24
Peak memory 205748 kb
Host smart-8958b860-e3b0-41c6-a7e1-a919b7488524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25304
30176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.2530430176
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.2331082850
Short name T1136
Test name
Test status
Simulation time 11337317331 ps
CPU time 16.83 seconds
Started Jun 05 05:49:28 PM PDT 24
Finished Jun 05 05:49:45 PM PDT 24
Peak memory 205680 kb
Host smart-67f3ebd3-d5be-4793-9b49-855e675333c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23310
82850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.2331082850
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.1301709962
Short name T1790
Test name
Test status
Simulation time 10061067576 ps
CPU time 13.54 seconds
Started Jun 05 05:49:17 PM PDT 24
Finished Jun 05 05:49:31 PM PDT 24
Peak memory 205732 kb
Host smart-5bcd86e7-d13b-431a-9adc-dc0500411218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13017
09962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.1301709962
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.475144127
Short name T488
Test name
Test status
Simulation time 10099614965 ps
CPU time 12.53 seconds
Started Jun 05 05:49:17 PM PDT 24
Finished Jun 05 05:49:30 PM PDT 24
Peak memory 205744 kb
Host smart-8527ae11-2ddd-462d-97b7-5f5ee87d0ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47514
4127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.475144127
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.3851163593
Short name T1627
Test name
Test status
Simulation time 10802399155 ps
CPU time 16.27 seconds
Started Jun 05 05:49:18 PM PDT 24
Finished Jun 05 05:49:34 PM PDT 24
Peak memory 205796 kb
Host smart-ad0c984e-0c80-4627-a4b5-1c2868a180c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38511
63593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.3851163593
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.399661336
Short name T1235
Test name
Test status
Simulation time 10096882828 ps
CPU time 15.68 seconds
Started Jun 05 05:49:20 PM PDT 24
Finished Jun 05 05:49:36 PM PDT 24
Peak memory 205520 kb
Host smart-a151a018-4a07-4664-b118-02a8f8967f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39966
1336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.399661336
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.961994232
Short name T529
Test name
Test status
Simulation time 10200321434 ps
CPU time 13.59 seconds
Started Jun 05 05:49:25 PM PDT 24
Finished Jun 05 05:49:39 PM PDT 24
Peak memory 205724 kb
Host smart-7fc81b73-b851-45f8-8549-f4a92b9d58ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96199
4232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.961994232
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.430774139
Short name T1988
Test name
Test status
Simulation time 10046577144 ps
CPU time 16.08 seconds
Started Jun 05 05:49:28 PM PDT 24
Finished Jun 05 05:49:45 PM PDT 24
Peak memory 205664 kb
Host smart-7b2ff0dd-7017-4220-8029-f12847c4a1a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43077
4139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.430774139
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3297559636
Short name T313
Test name
Test status
Simulation time 10094100787 ps
CPU time 13.73 seconds
Started Jun 05 05:49:23 PM PDT 24
Finished Jun 05 05:49:38 PM PDT 24
Peak memory 205664 kb
Host smart-77604760-fc39-4254-8e8a-4b3620f6e0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32975
59636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3297559636
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.1871170245
Short name T510
Test name
Test status
Simulation time 10087606886 ps
CPU time 13.55 seconds
Started Jun 05 05:49:24 PM PDT 24
Finished Jun 05 05:49:38 PM PDT 24
Peak memory 205700 kb
Host smart-b63b75f4-f3ba-4ebe-a6ac-e3c3ded3de61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18711
70245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.1871170245
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.3876851099
Short name T1596
Test name
Test status
Simulation time 13176032858 ps
CPU time 16.17 seconds
Started Jun 05 05:49:20 PM PDT 24
Finished Jun 05 05:49:37 PM PDT 24
Peak memory 205652 kb
Host smart-5fd1fa92-8339-4b8d-8ec5-a74508dabbc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38768
51099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.3876851099
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.2405775259
Short name T609
Test name
Test status
Simulation time 10166071481 ps
CPU time 13.3 seconds
Started Jun 05 05:49:20 PM PDT 24
Finished Jun 05 05:49:34 PM PDT 24
Peak memory 205704 kb
Host smart-1b9b1508-d0d6-4e86-9d0a-cba14668368c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24057
75259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.2405775259
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.2410949551
Short name T1924
Test name
Test status
Simulation time 21933108860 ps
CPU time 357.59 seconds
Started Jun 05 05:49:18 PM PDT 24
Finished Jun 05 05:55:17 PM PDT 24
Peak memory 205688 kb
Host smart-e951480a-e9cb-4b87-8ffd-5de832fdc02f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24109
49551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.2410949551
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2525794739
Short name T1084
Test name
Test status
Simulation time 10051953207 ps
CPU time 12.78 seconds
Started Jun 05 05:49:18 PM PDT 24
Finished Jun 05 05:49:31 PM PDT 24
Peak memory 205664 kb
Host smart-20182ae2-0891-435c-a18a-0da43330988a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25257
94739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2525794739
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2822830869
Short name T102
Test name
Test status
Simulation time 10178170257 ps
CPU time 13.54 seconds
Started Jun 05 05:49:16 PM PDT 24
Finished Jun 05 05:49:30 PM PDT 24
Peak memory 205768 kb
Host smart-ffc858c9-9bec-4d57-af6b-38e73a138c28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28228
30869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2822830869
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.612006079
Short name T1757
Test name
Test status
Simulation time 10061280814 ps
CPU time 13.45 seconds
Started Jun 05 05:49:22 PM PDT 24
Finished Jun 05 05:49:36 PM PDT 24
Peak memory 205732 kb
Host smart-df41a16f-5c1f-4ab5-83bb-952bc2177c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61200
6079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.612006079
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.2040964809
Short name T1602
Test name
Test status
Simulation time 10100193927 ps
CPU time 13.25 seconds
Started Jun 05 05:49:20 PM PDT 24
Finished Jun 05 05:49:34 PM PDT 24
Peak memory 205796 kb
Host smart-95f3c95d-dd7e-4045-8ad5-10e24b3245f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20409
64809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.2040964809
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3907161333
Short name T319
Test name
Test status
Simulation time 10058303275 ps
CPU time 13.72 seconds
Started Jun 05 05:49:21 PM PDT 24
Finished Jun 05 05:49:35 PM PDT 24
Peak memory 205764 kb
Host smart-a714af6f-ee13-4877-aad8-e66c59d4e4af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39071
61333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3907161333
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.3164327115
Short name T1192
Test name
Test status
Simulation time 10092005279 ps
CPU time 13.1 seconds
Started Jun 05 05:49:24 PM PDT 24
Finished Jun 05 05:49:38 PM PDT 24
Peak memory 205748 kb
Host smart-b17b24b3-79af-439a-936c-53a43302d996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31643
27115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.3164327115
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_eop_single_bit_handling.910032346
Short name T1974
Test name
Test status
Simulation time 10091384719 ps
CPU time 13.41 seconds
Started Jun 05 05:49:26 PM PDT 24
Finished Jun 05 05:49:40 PM PDT 24
Peak memory 205696 kb
Host smart-9bba77ff-8108-43dd-9e63-deef80bfdc04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91003
2346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_eop_single_bit_handling.910032346
Directory /workspace/45.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.387183513
Short name T657
Test name
Test status
Simulation time 10053781503 ps
CPU time 14.04 seconds
Started Jun 05 05:49:24 PM PDT 24
Finished Jun 05 05:49:39 PM PDT 24
Peak memory 205764 kb
Host smart-79df4391-0f5c-48c9-a8bf-9fe73d729648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38718
3513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.387183513
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.2802600377
Short name T38
Test name
Test status
Simulation time 10057726724 ps
CPU time 14.11 seconds
Started Jun 05 05:49:22 PM PDT 24
Finished Jun 05 05:49:37 PM PDT 24
Peak memory 205668 kb
Host smart-376fca14-226d-4d50-bbb1-f92bb0b5d166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28026
00377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.2802600377
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.1517819219
Short name T1045
Test name
Test status
Simulation time 26183042263 ps
CPU time 49.66 seconds
Started Jun 05 05:49:27 PM PDT 24
Finished Jun 05 05:50:17 PM PDT 24
Peak memory 205676 kb
Host smart-5874156a-678b-41b4-8e43-8c3b22201672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15178
19219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.1517819219
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.481222195
Short name T1104
Test name
Test status
Simulation time 10081123335 ps
CPU time 13.92 seconds
Started Jun 05 05:49:16 PM PDT 24
Finished Jun 05 05:49:31 PM PDT 24
Peak memory 205664 kb
Host smart-61858559-744e-4ff6-abe1-2926eea8dc7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48122
2195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.481222195
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.1551946184
Short name T590
Test name
Test status
Simulation time 10181670121 ps
CPU time 14.2 seconds
Started Jun 05 05:49:17 PM PDT 24
Finished Jun 05 05:49:32 PM PDT 24
Peak memory 205756 kb
Host smart-84760cc8-a7af-475d-b2c8-7f85dbb6bdd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15519
46184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.1551946184
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.3091709688
Short name T1955
Test name
Test status
Simulation time 10088369068 ps
CPU time 13.07 seconds
Started Jun 05 05:49:27 PM PDT 24
Finished Jun 05 05:49:41 PM PDT 24
Peak memory 205692 kb
Host smart-5969b2cd-512e-4b2e-94e8-45d41c6bd59b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30917
09688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.3091709688
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.3377685674
Short name T758
Test name
Test status
Simulation time 10044575159 ps
CPU time 14.13 seconds
Started Jun 05 05:49:30 PM PDT 24
Finished Jun 05 05:49:45 PM PDT 24
Peak memory 205680 kb
Host smart-e52c20f0-1e24-4b46-95ee-862ef5b28c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33776
85674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.3377685674
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.1662524470
Short name T1718
Test name
Test status
Simulation time 10082929724 ps
CPU time 13.65 seconds
Started Jun 05 05:49:24 PM PDT 24
Finished Jun 05 05:49:38 PM PDT 24
Peak memory 205720 kb
Host smart-34ad6606-d280-437f-86e4-c3d7e1e94771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16625
24470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.1662524470
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.1527905954
Short name T1539
Test name
Test status
Simulation time 10054857952 ps
CPU time 13.47 seconds
Started Jun 05 05:49:25 PM PDT 24
Finished Jun 05 05:49:39 PM PDT 24
Peak memory 205644 kb
Host smart-5245d022-a5bf-411a-b41f-7205af04c500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15279
05954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.1527905954
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.1384503309
Short name T143
Test name
Test status
Simulation time 10148999928 ps
CPU time 13.16 seconds
Started Jun 05 05:49:19 PM PDT 24
Finished Jun 05 05:49:33 PM PDT 24
Peak memory 205668 kb
Host smart-a61d9162-6b89-43d3-9a60-ba534bcf1a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13845
03309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1384503309
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.911494714
Short name T968
Test name
Test status
Simulation time 10090800444 ps
CPU time 13.33 seconds
Started Jun 05 05:49:23 PM PDT 24
Finished Jun 05 05:49:37 PM PDT 24
Peak memory 205692 kb
Host smart-9a6782ca-e471-4d22-9e83-2beef4242148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91149
4714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.911494714
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.2323623072
Short name T446
Test name
Test status
Simulation time 10065386005 ps
CPU time 13.34 seconds
Started Jun 05 05:49:26 PM PDT 24
Finished Jun 05 05:49:40 PM PDT 24
Peak memory 205732 kb
Host smart-e17173cb-ef4d-4ef7-ba53-421964889186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23236
23072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.2323623072
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.4056007887
Short name T1408
Test name
Test status
Simulation time 21033030106 ps
CPU time 324.71 seconds
Started Jun 05 05:49:42 PM PDT 24
Finished Jun 05 05:55:07 PM PDT 24
Peak memory 205724 kb
Host smart-762299f0-d9d1-4b4c-868d-48e4f44ee7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40560
07887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.4056007887
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.4278053084
Short name T1359
Test name
Test status
Simulation time 10157278279 ps
CPU time 13.35 seconds
Started Jun 05 05:49:43 PM PDT 24
Finished Jun 05 05:49:57 PM PDT 24
Peak memory 205784 kb
Host smart-da91c11b-bcc7-4748-b460-330698634963
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4278053084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.4278053084
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.3447040100
Short name T804
Test name
Test status
Simulation time 10123019871 ps
CPU time 14.03 seconds
Started Jun 05 05:49:31 PM PDT 24
Finished Jun 05 05:49:46 PM PDT 24
Peak memory 205776 kb
Host smart-092d0293-88b1-4708-8f63-ea5c9455934a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3447040100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.3447040100
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.233776939
Short name T873
Test name
Test status
Simulation time 10119500204 ps
CPU time 12.95 seconds
Started Jun 05 05:49:38 PM PDT 24
Finished Jun 05 05:49:52 PM PDT 24
Peak memory 205780 kb
Host smart-4b33ecc6-aba3-4b96-8088-c5d5ccc761b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23377
6939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.233776939
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.310478985
Short name T1200
Test name
Test status
Simulation time 13455741500 ps
CPU time 17.73 seconds
Started Jun 05 05:49:23 PM PDT 24
Finished Jun 05 05:49:42 PM PDT 24
Peak memory 205768 kb
Host smart-d226a84a-5e02-40b7-9266-7c2e3276bfd1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=310478985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.310478985
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.955283633
Short name T1865
Test name
Test status
Simulation time 23392679694 ps
CPU time 25.99 seconds
Started Jun 05 05:49:26 PM PDT 24
Finished Jun 05 05:49:53 PM PDT 24
Peak memory 205760 kb
Host smart-57f76348-16c9-4b9d-a9b2-85ab5546f342
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=955283633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.955283633
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3553518389
Short name T450
Test name
Test status
Simulation time 10069604292 ps
CPU time 12.9 seconds
Started Jun 05 05:49:30 PM PDT 24
Finished Jun 05 05:49:43 PM PDT 24
Peak memory 205644 kb
Host smart-6bac3607-ac4b-45cd-9063-2a8c419f5d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35535
18389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3553518389
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.1484380391
Short name T1529
Test name
Test status
Simulation time 10904998195 ps
CPU time 14.94 seconds
Started Jun 05 05:49:36 PM PDT 24
Finished Jun 05 05:49:52 PM PDT 24
Peak memory 205608 kb
Host smart-acbea024-9687-45ee-be03-31de26c17571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14843
80391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.1484380391
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.607246676
Short name T1363
Test name
Test status
Simulation time 10063423296 ps
CPU time 14.01 seconds
Started Jun 05 05:49:38 PM PDT 24
Finished Jun 05 05:49:52 PM PDT 24
Peak memory 205740 kb
Host smart-1183eabf-ac3a-4a5c-a3a9-0564e747cfaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60724
6676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.607246676
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.1173810990
Short name T1303
Test name
Test status
Simulation time 10107820708 ps
CPU time 15.6 seconds
Started Jun 05 05:49:29 PM PDT 24
Finished Jun 05 05:49:46 PM PDT 24
Peak memory 205628 kb
Host smart-f1ed297d-5f71-4620-a2bc-1cb75ddb351b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11738
10990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.1173810990
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.458637797
Short name T511
Test name
Test status
Simulation time 10794029712 ps
CPU time 16.38 seconds
Started Jun 05 05:49:23 PM PDT 24
Finished Jun 05 05:49:40 PM PDT 24
Peak memory 205656 kb
Host smart-878ec909-96e7-4f35-ad18-3d71a402aceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45863
7797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.458637797
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.101457360
Short name T803
Test name
Test status
Simulation time 10245603999 ps
CPU time 14.83 seconds
Started Jun 05 05:49:29 PM PDT 24
Finished Jun 05 05:49:45 PM PDT 24
Peak memory 205772 kb
Host smart-51cd7101-6ce5-4f3d-b180-3c4192132bc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10145
7360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.101457360
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.465068654
Short name T776
Test name
Test status
Simulation time 10151485494 ps
CPU time 16.3 seconds
Started Jun 05 05:49:38 PM PDT 24
Finished Jun 05 05:49:55 PM PDT 24
Peak memory 205580 kb
Host smart-43c69207-6af2-4428-b3fb-767bb980e69b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46506
8654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.465068654
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3664272440
Short name T431
Test name
Test status
Simulation time 10054977948 ps
CPU time 12.93 seconds
Started Jun 05 05:49:44 PM PDT 24
Finished Jun 05 05:49:57 PM PDT 24
Peak memory 205716 kb
Host smart-6c71a32a-a122-44c7-9b12-be1879e55cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36642
72440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3664272440
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.523852836
Short name T1714
Test name
Test status
Simulation time 10169460177 ps
CPU time 13.1 seconds
Started Jun 05 05:49:27 PM PDT 24
Finished Jun 05 05:49:40 PM PDT 24
Peak memory 205744 kb
Host smart-f5d89cab-d0e9-45dd-8fc6-1f643d963410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52385
2836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.523852836
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.534075156
Short name T1881
Test name
Test status
Simulation time 10106772518 ps
CPU time 12.86 seconds
Started Jun 05 05:49:22 PM PDT 24
Finished Jun 05 05:49:35 PM PDT 24
Peak memory 205708 kb
Host smart-1b1f9f91-4e08-43f7-b138-abe15a6fdbde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53407
5156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.534075156
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.1260370010
Short name T881
Test name
Test status
Simulation time 13313671883 ps
CPU time 15.92 seconds
Started Jun 05 05:49:25 PM PDT 24
Finished Jun 05 05:49:41 PM PDT 24
Peak memory 205732 kb
Host smart-4440a41e-195a-4d2c-b84e-00271b52a1fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12603
70010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.1260370010
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.85301205
Short name T1361
Test name
Test status
Simulation time 10159645398 ps
CPU time 13.28 seconds
Started Jun 05 05:49:47 PM PDT 24
Finished Jun 05 05:50:01 PM PDT 24
Peak memory 205600 kb
Host smart-aedfdd72-0816-4724-9ff1-c9456082b123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85301
205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.85301205
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.3198922038
Short name T1141
Test name
Test status
Simulation time 13794204354 ps
CPU time 125.48 seconds
Started Jun 05 05:49:34 PM PDT 24
Finished Jun 05 05:51:39 PM PDT 24
Peak memory 205644 kb
Host smart-ec7b623d-f526-41fc-95b5-f960372d3c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31989
22038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.3198922038
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.153249310
Short name T1816
Test name
Test status
Simulation time 10057072565 ps
CPU time 12.49 seconds
Started Jun 05 05:49:36 PM PDT 24
Finished Jun 05 05:49:49 PM PDT 24
Peak memory 205748 kb
Host smart-63a71b95-4e6d-46d4-a18e-a778cb472166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15324
9310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.153249310
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.2478672660
Short name T108
Test name
Test status
Simulation time 10108529038 ps
CPU time 14.24 seconds
Started Jun 05 05:49:36 PM PDT 24
Finished Jun 05 05:49:51 PM PDT 24
Peak memory 205760 kb
Host smart-0a71592c-e373-4a88-8e4b-98adff734404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24786
72660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.2478672660
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.1679491087
Short name T222
Test name
Test status
Simulation time 10077742030 ps
CPU time 14.81 seconds
Started Jun 05 05:49:43 PM PDT 24
Finished Jun 05 05:49:58 PM PDT 24
Peak memory 205780 kb
Host smart-393f5eb8-3d2b-4533-928e-db41713ff971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16794
91087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.1679491087
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.3601991734
Short name T695
Test name
Test status
Simulation time 10079735572 ps
CPU time 14.16 seconds
Started Jun 05 05:49:35 PM PDT 24
Finished Jun 05 05:49:49 PM PDT 24
Peak memory 205764 kb
Host smart-ae83b13f-f6f6-4a89-9f64-2cdbeef596e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36019
91734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.3601991734
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3646840298
Short name T549
Test name
Test status
Simulation time 10087895550 ps
CPU time 13.36 seconds
Started Jun 05 05:49:29 PM PDT 24
Finished Jun 05 05:49:43 PM PDT 24
Peak memory 205652 kb
Host smart-0798ed8d-64f3-4240-9c4f-70579ad7ecb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36468
40298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3646840298
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.2571363953
Short name T1428
Test name
Test status
Simulation time 10064563664 ps
CPU time 13.77 seconds
Started Jun 05 05:49:39 PM PDT 24
Finished Jun 05 05:49:53 PM PDT 24
Peak memory 205684 kb
Host smart-b2bdbd81-ee18-4852-bc6a-93c2996f8100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25713
63953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.2571363953
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_eop_single_bit_handling.908296228
Short name T32
Test name
Test status
Simulation time 10116362591 ps
CPU time 13.73 seconds
Started Jun 05 05:49:48 PM PDT 24
Finished Jun 05 05:50:02 PM PDT 24
Peak memory 205660 kb
Host smart-5a579705-6c3e-4c2a-a938-e35f146c738d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90829
6228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_eop_single_bit_handling.908296228
Directory /workspace/46.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3692381625
Short name T893
Test name
Test status
Simulation time 10122160752 ps
CPU time 15.36 seconds
Started Jun 05 05:49:29 PM PDT 24
Finished Jun 05 05:49:45 PM PDT 24
Peak memory 205800 kb
Host smart-78e4cc77-7ab4-4a77-92ba-89bf262592a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36923
81625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3692381625
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3287802508
Short name T637
Test name
Test status
Simulation time 10067002893 ps
CPU time 14.68 seconds
Started Jun 05 05:49:37 PM PDT 24
Finished Jun 05 05:49:52 PM PDT 24
Peak memory 205744 kb
Host smart-fa1aef01-334e-42a1-82f6-820580e6367d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32878
02508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3287802508
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.2903604481
Short name T852
Test name
Test status
Simulation time 30652848633 ps
CPU time 60.58 seconds
Started Jun 05 05:49:33 PM PDT 24
Finished Jun 05 05:50:34 PM PDT 24
Peak memory 205660 kb
Host smart-53773ef6-09b6-4e68-aa0b-fd5c1f3926c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29036
04481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.2903604481
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.1375370882
Short name T227
Test name
Test status
Simulation time 10074885113 ps
CPU time 14.91 seconds
Started Jun 05 05:49:30 PM PDT 24
Finished Jun 05 05:49:45 PM PDT 24
Peak memory 205760 kb
Host smart-132c93c7-406f-4316-981d-17601805983c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13753
70882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.1375370882
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.11769288
Short name T257
Test name
Test status
Simulation time 10108238876 ps
CPU time 12.99 seconds
Started Jun 05 05:49:38 PM PDT 24
Finished Jun 05 05:49:52 PM PDT 24
Peak memory 205780 kb
Host smart-dfc81b95-0097-4317-8e85-5e7dc4e71407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11769
288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.11769288
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.3783180780
Short name T1273
Test name
Test status
Simulation time 10071789997 ps
CPU time 13.41 seconds
Started Jun 05 05:49:42 PM PDT 24
Finished Jun 05 05:49:56 PM PDT 24
Peak memory 205704 kb
Host smart-dcbb1b03-e184-4981-a6ea-79452fe55e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37831
80780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.3783180780
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.4233839394
Short name T1477
Test name
Test status
Simulation time 10041667488 ps
CPU time 14.18 seconds
Started Jun 05 05:49:47 PM PDT 24
Finished Jun 05 05:50:02 PM PDT 24
Peak memory 205728 kb
Host smart-98675e7d-e9bf-4168-a31f-5f15d071b87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42338
39394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.4233839394
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.3080757427
Short name T20
Test name
Test status
Simulation time 10051209609 ps
CPU time 13.69 seconds
Started Jun 05 05:49:39 PM PDT 24
Finished Jun 05 05:49:53 PM PDT 24
Peak memory 205992 kb
Host smart-3008407c-c891-4576-8bff-ac45ccaa1017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30807
57427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.3080757427
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.2399240466
Short name T393
Test name
Test status
Simulation time 10061534060 ps
CPU time 15.02 seconds
Started Jun 05 05:49:32 PM PDT 24
Finished Jun 05 05:49:47 PM PDT 24
Peak memory 205760 kb
Host smart-fe6e1109-19f6-43c6-a33a-650b55dda4c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23992
40466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.2399240466
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.976763048
Short name T1919
Test name
Test status
Simulation time 10218649254 ps
CPU time 14.05 seconds
Started Jun 05 05:49:23 PM PDT 24
Finished Jun 05 05:49:37 PM PDT 24
Peak memory 205740 kb
Host smart-24708b12-0abd-4091-8361-3b673f0332c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97676
3048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.976763048
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.46076456
Short name T1415
Test name
Test status
Simulation time 10093063455 ps
CPU time 16.19 seconds
Started Jun 05 05:49:44 PM PDT 24
Finished Jun 05 05:50:01 PM PDT 24
Peak memory 205680 kb
Host smart-dfbef16f-206e-4e39-99e9-b9bd255bfb24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46076
456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.46076456
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.1140216233
Short name T555
Test name
Test status
Simulation time 10094737140 ps
CPU time 14.29 seconds
Started Jun 05 05:49:29 PM PDT 24
Finished Jun 05 05:49:44 PM PDT 24
Peak memory 205792 kb
Host smart-1e921d74-94ee-4d53-bd84-f6019c0de36b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11402
16233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1140216233
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.10802487
Short name T2022
Test name
Test status
Simulation time 17116859460 ps
CPU time 84.84 seconds
Started Jun 05 05:49:42 PM PDT 24
Finished Jun 05 05:51:07 PM PDT 24
Peak memory 205708 kb
Host smart-2f388f91-5c43-4dc6-83ff-8ee9baae6012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10802
487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.10802487
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.1763929900
Short name T354
Test name
Test status
Simulation time 10141387562 ps
CPU time 14.12 seconds
Started Jun 05 05:49:48 PM PDT 24
Finished Jun 05 05:50:03 PM PDT 24
Peak memory 205668 kb
Host smart-cd4c93b6-c38b-4595-aac6-66368c861c34
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1763929900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.1763929900
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.2650543269
Short name T790
Test name
Test status
Simulation time 10074086112 ps
CPU time 14.54 seconds
Started Jun 05 05:49:44 PM PDT 24
Finished Jun 05 05:50:00 PM PDT 24
Peak memory 205808 kb
Host smart-e0a6900c-58b3-4c89-86c0-4f00626c5f3a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2650543269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.2650543269
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.445895072
Short name T1164
Test name
Test status
Simulation time 10115499489 ps
CPU time 13.93 seconds
Started Jun 05 05:49:45 PM PDT 24
Finished Jun 05 05:50:00 PM PDT 24
Peak memory 205792 kb
Host smart-1879ce2d-3ed0-4d8a-b060-ad7a699af037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44589
5072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.445895072
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.3570379209
Short name T10
Test name
Test status
Simulation time 13630465500 ps
CPU time 16.86 seconds
Started Jun 05 05:49:44 PM PDT 24
Finished Jun 05 05:50:02 PM PDT 24
Peak memory 205812 kb
Host smart-82b01942-61e4-4f4a-8449-f452c57dd1fa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3570379209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.3570379209
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.3653867216
Short name T1435
Test name
Test status
Simulation time 23259246399 ps
CPU time 25.87 seconds
Started Jun 05 05:49:30 PM PDT 24
Finished Jun 05 05:49:57 PM PDT 24
Peak memory 205716 kb
Host smart-49420e5d-b6f4-4c17-ad8a-e7ace4ef150d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3653867216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.3653867216
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1655053280
Short name T1812
Test name
Test status
Simulation time 10083553673 ps
CPU time 13.03 seconds
Started Jun 05 05:49:32 PM PDT 24
Finished Jun 05 05:49:45 PM PDT 24
Peak memory 205784 kb
Host smart-13b2465d-b24b-47cb-aac9-dc74024b9021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16550
53280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1655053280
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.1382406185
Short name T1156
Test name
Test status
Simulation time 10992898196 ps
CPU time 16.25 seconds
Started Jun 05 05:49:35 PM PDT 24
Finished Jun 05 05:49:52 PM PDT 24
Peak memory 205676 kb
Host smart-7c273196-7540-49b7-b515-46ced2e61f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13824
06185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.1382406185
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.813321842
Short name T1915
Test name
Test status
Simulation time 10065444538 ps
CPU time 14.15 seconds
Started Jun 05 05:49:37 PM PDT 24
Finished Jun 05 05:49:52 PM PDT 24
Peak memory 205876 kb
Host smart-40e7864f-c3a1-4abf-b2a3-8ec02abd2dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81332
1842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.813321842
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.2944730228
Short name T1031
Test name
Test status
Simulation time 10082919860 ps
CPU time 13.59 seconds
Started Jun 05 05:49:38 PM PDT 24
Finished Jun 05 05:49:52 PM PDT 24
Peak memory 205744 kb
Host smart-00574488-c83d-4eb6-9c73-a69b7f76a95d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29447
30228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2944730228
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.1786211589
Short name T1870
Test name
Test status
Simulation time 10724077690 ps
CPU time 16.53 seconds
Started Jun 05 05:49:36 PM PDT 24
Finished Jun 05 05:49:53 PM PDT 24
Peak memory 205688 kb
Host smart-199a1567-e216-4242-bc2f-86799c8b673e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17862
11589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.1786211589
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.2597367005
Short name T1496
Test name
Test status
Simulation time 10146390323 ps
CPU time 13.9 seconds
Started Jun 05 05:49:46 PM PDT 24
Finished Jun 05 05:50:00 PM PDT 24
Peak memory 205760 kb
Host smart-aa176fc4-7b97-4fa9-954a-3d380bd5b8e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25973
67005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.2597367005
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.2563285292
Short name T68
Test name
Test status
Simulation time 10156335211 ps
CPU time 16.74 seconds
Started Jun 05 05:49:41 PM PDT 24
Finished Jun 05 05:49:58 PM PDT 24
Peak memory 205760 kb
Host smart-b3afd028-cfdf-4a94-b4aa-a8183f6325d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25632
85292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.2563285292
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.1955417608
Short name T1343
Test name
Test status
Simulation time 10039377551 ps
CPU time 13.71 seconds
Started Jun 05 05:49:56 PM PDT 24
Finished Jun 05 05:50:11 PM PDT 24
Peak memory 205760 kb
Host smart-e2a686e4-f622-4ff8-8de8-616fe9daa3bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19554
17608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.1955417608
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.3520569445
Short name T1344
Test name
Test status
Simulation time 10119324593 ps
CPU time 13.33 seconds
Started Jun 05 05:49:33 PM PDT 24
Finished Jun 05 05:49:46 PM PDT 24
Peak memory 205684 kb
Host smart-7bd25d23-38b4-4c5e-85d8-0535c40a322e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35205
69445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3520569445
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.3420699925
Short name T1890
Test name
Test status
Simulation time 10145546334 ps
CPU time 12.84 seconds
Started Jun 05 05:49:37 PM PDT 24
Finished Jun 05 05:49:51 PM PDT 24
Peak memory 205508 kb
Host smart-09c626d9-5595-4ddb-a9e2-b9b4e35f30d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34206
99925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.3420699925
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.3532610326
Short name T1226
Test name
Test status
Simulation time 10143617629 ps
CPU time 14.95 seconds
Started Jun 05 05:49:40 PM PDT 24
Finished Jun 05 05:49:55 PM PDT 24
Peak memory 205628 kb
Host smart-cc1718ce-2419-4996-8611-17564a933985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35326
10326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.3532610326
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.3672430195
Short name T1403
Test name
Test status
Simulation time 17906817233 ps
CPU time 66.92 seconds
Started Jun 05 05:49:35 PM PDT 24
Finished Jun 05 05:50:42 PM PDT 24
Peak memory 205672 kb
Host smart-378f581e-f392-4356-acad-307c420c0aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36724
30195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.3672430195
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.2349974895
Short name T401
Test name
Test status
Simulation time 10056001490 ps
CPU time 16.28 seconds
Started Jun 05 05:49:37 PM PDT 24
Finished Jun 05 05:49:53 PM PDT 24
Peak memory 205532 kb
Host smart-13df9090-d6a0-4ae5-8b61-5327170e7b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23499
74895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.2349974895
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.759201198
Short name T88
Test name
Test status
Simulation time 10080297093 ps
CPU time 17.43 seconds
Started Jun 05 05:49:33 PM PDT 24
Finished Jun 05 05:49:51 PM PDT 24
Peak memory 205764 kb
Host smart-c153aae5-49e2-4cab-9029-8c479eaecbf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75920
1198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.759201198
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.1915535584
Short name T595
Test name
Test status
Simulation time 10085061066 ps
CPU time 13.15 seconds
Started Jun 05 05:49:46 PM PDT 24
Finished Jun 05 05:50:00 PM PDT 24
Peak memory 205732 kb
Host smart-d45ed98b-4431-4218-8ce3-f4a94b3b71c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19155
35584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.1915535584
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.2746794367
Short name T1355
Test name
Test status
Simulation time 10067292321 ps
CPU time 15.83 seconds
Started Jun 05 05:49:47 PM PDT 24
Finished Jun 05 05:50:04 PM PDT 24
Peak memory 205784 kb
Host smart-5a08afd8-3262-49c6-9cb9-ff0d6eb82c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27467
94367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.2746794367
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3300019280
Short name T1425
Test name
Test status
Simulation time 10104743337 ps
CPU time 13.57 seconds
Started Jun 05 05:49:46 PM PDT 24
Finished Jun 05 05:50:00 PM PDT 24
Peak memory 205668 kb
Host smart-2b879a82-0e37-41d5-8614-50d2674f4ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33000
19280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3300019280
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.625241353
Short name T1557
Test name
Test status
Simulation time 10060177468 ps
CPU time 14.67 seconds
Started Jun 05 05:49:54 PM PDT 24
Finished Jun 05 05:50:09 PM PDT 24
Peak memory 205724 kb
Host smart-a7ee6f43-5965-4b25-906c-b8decbd1b462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62524
1353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.625241353
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_eop_single_bit_handling.2603420874
Short name T1025
Test name
Test status
Simulation time 10080651617 ps
CPU time 14.53 seconds
Started Jun 05 05:49:50 PM PDT 24
Finished Jun 05 05:50:06 PM PDT 24
Peak memory 205736 kb
Host smart-aaaf64e7-10c8-41c0-a469-4c11b82181e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26034
20874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_eop_single_bit_handling.2603420874
Directory /workspace/47.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.2409272683
Short name T1426
Test name
Test status
Simulation time 10043874239 ps
CPU time 14.96 seconds
Started Jun 05 05:49:50 PM PDT 24
Finished Jun 05 05:50:05 PM PDT 24
Peak memory 205784 kb
Host smart-84adede1-e030-4987-aa33-799a473eb32c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24092
72683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.2409272683
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2319095410
Short name T1854
Test name
Test status
Simulation time 10041985751 ps
CPU time 13.28 seconds
Started Jun 05 05:49:55 PM PDT 24
Finished Jun 05 05:50:09 PM PDT 24
Peak memory 205728 kb
Host smart-ba045e91-6d67-4a0f-97dd-f35666e10608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23190
95410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2319095410
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1591563532
Short name T598
Test name
Test status
Simulation time 24183376551 ps
CPU time 46.8 seconds
Started Jun 05 05:49:52 PM PDT 24
Finished Jun 05 05:50:40 PM PDT 24
Peak memory 205384 kb
Host smart-54dc0d08-9290-4215-80f6-5e6fbc0ee1ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15915
63532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1591563532
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2351712150
Short name T1520
Test name
Test status
Simulation time 10115066865 ps
CPU time 14.6 seconds
Started Jun 05 05:49:48 PM PDT 24
Finished Jun 05 05:50:03 PM PDT 24
Peak memory 205680 kb
Host smart-ab05ac35-1f7b-4831-ba98-ce63855443c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23517
12150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2351712150
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.1876990455
Short name T1884
Test name
Test status
Simulation time 10073998523 ps
CPU time 13.08 seconds
Started Jun 05 05:49:47 PM PDT 24
Finished Jun 05 05:50:01 PM PDT 24
Peak memory 205704 kb
Host smart-098c2999-7aea-4f79-90ae-878b91bc5758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18769
90455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.1876990455
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.2079508372
Short name T61
Test name
Test status
Simulation time 10083480840 ps
CPU time 13.45 seconds
Started Jun 05 05:49:44 PM PDT 24
Finished Jun 05 05:49:58 PM PDT 24
Peak memory 205700 kb
Host smart-fc55a78a-b143-4ce8-b11b-5316be168a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20795
08372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.2079508372
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.2037443391
Short name T477
Test name
Test status
Simulation time 10057702978 ps
CPU time 12.41 seconds
Started Jun 05 05:49:44 PM PDT 24
Finished Jun 05 05:49:57 PM PDT 24
Peak memory 205772 kb
Host smart-05bb0c4a-b653-47e7-9cb8-765a1a621e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20374
43391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.2037443391
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.1283336504
Short name T1921
Test name
Test status
Simulation time 10066525655 ps
CPU time 15.7 seconds
Started Jun 05 05:49:55 PM PDT 24
Finished Jun 05 05:50:11 PM PDT 24
Peak memory 205648 kb
Host smart-faacce98-538a-440b-86b2-76e112aa9095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12833
36504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.1283336504
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.1971929922
Short name T1567
Test name
Test status
Simulation time 10089951661 ps
CPU time 14.39 seconds
Started Jun 05 05:49:30 PM PDT 24
Finished Jun 05 05:49:45 PM PDT 24
Peak memory 205696 kb
Host smart-d59a88f9-1390-48f8-a8dd-656e71c845db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19719
29922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1971929922
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.867962192
Short name T688
Test name
Test status
Simulation time 10106303911 ps
CPU time 13.95 seconds
Started Jun 05 05:49:43 PM PDT 24
Finished Jun 05 05:49:57 PM PDT 24
Peak memory 205760 kb
Host smart-597a625c-7132-4927-bd4a-c04ef0d9934f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86796
2192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.867962192
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2314566156
Short name T1945
Test name
Test status
Simulation time 10079924881 ps
CPU time 14.22 seconds
Started Jun 05 05:49:44 PM PDT 24
Finished Jun 05 05:50:00 PM PDT 24
Peak memory 205976 kb
Host smart-6ffeda2a-2320-4133-bbd0-37b17957d4bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23145
66156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2314566156
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.637312083
Short name T2030
Test name
Test status
Simulation time 22298774732 ps
CPU time 101.4 seconds
Started Jun 05 05:49:48 PM PDT 24
Finished Jun 05 05:51:30 PM PDT 24
Peak memory 205708 kb
Host smart-2f3e491d-5c46-4335-899f-c7c45c54e61a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63731
2083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.637312083
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.2990131052
Short name T448
Test name
Test status
Simulation time 10141599450 ps
CPU time 13.41 seconds
Started Jun 05 05:49:49 PM PDT 24
Finished Jun 05 05:50:03 PM PDT 24
Peak memory 205780 kb
Host smart-2d4a6ad6-9a68-4bfb-83fe-717be30fe638
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2990131052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.2990131052
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.3649405973
Short name T789
Test name
Test status
Simulation time 10056081610 ps
CPU time 16.25 seconds
Started Jun 05 05:49:53 PM PDT 24
Finished Jun 05 05:50:11 PM PDT 24
Peak memory 205740 kb
Host smart-6ab7386b-c9f1-4fcc-bc12-2daedd4e46e9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3649405973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.3649405973
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.1858635127
Short name T1462
Test name
Test status
Simulation time 10102941154 ps
CPU time 14.06 seconds
Started Jun 05 05:50:00 PM PDT 24
Finished Jun 05 05:50:15 PM PDT 24
Peak memory 205660 kb
Host smart-9193aae8-efcc-4b15-bcda-07335e89863e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18586
35127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.1858635127
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.972345428
Short name T849
Test name
Test status
Simulation time 13505568511 ps
CPU time 16.62 seconds
Started Jun 05 05:49:38 PM PDT 24
Finished Jun 05 05:49:55 PM PDT 24
Peak memory 205680 kb
Host smart-b189725b-eed2-445f-97bb-c944722f0a17
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=972345428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.972345428
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.212959359
Short name T1147
Test name
Test status
Simulation time 23268863963 ps
CPU time 25.78 seconds
Started Jun 05 05:49:49 PM PDT 24
Finished Jun 05 05:50:16 PM PDT 24
Peak memory 205788 kb
Host smart-9b66c8a4-4452-4a8a-98da-f77a6592dfa3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=212959359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.212959359
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.3794894594
Short name T1333
Test name
Test status
Simulation time 10081833073 ps
CPU time 13.58 seconds
Started Jun 05 05:49:52 PM PDT 24
Finished Jun 05 05:50:06 PM PDT 24
Peak memory 205768 kb
Host smart-59bb3201-2b8f-4d34-9e0d-7df041ddfd2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37948
94594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.3794894594
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.692490362
Short name T782
Test name
Test status
Simulation time 10043214497 ps
CPU time 14.02 seconds
Started Jun 05 05:49:49 PM PDT 24
Finished Jun 05 05:50:04 PM PDT 24
Peak memory 205732 kb
Host smart-1de9a2d5-10c9-47b5-be8f-6f597b711cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69249
0362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.692490362
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.2363978123
Short name T1749
Test name
Test status
Simulation time 10544510390 ps
CPU time 14.89 seconds
Started Jun 05 05:49:49 PM PDT 24
Finished Jun 05 05:50:05 PM PDT 24
Peak memory 205744 kb
Host smart-51a56b48-4fdf-4cf8-966e-c40cd807c88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23639
78123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.2363978123
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.1941617351
Short name T389
Test name
Test status
Simulation time 10108167205 ps
CPU time 15.38 seconds
Started Jun 05 05:49:50 PM PDT 24
Finished Jun 05 05:50:06 PM PDT 24
Peak memory 205760 kb
Host smart-a369f8ee-07b1-49d6-8281-c2c124496b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19416
17351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.1941617351
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.1793670751
Short name T1782
Test name
Test status
Simulation time 10104124523 ps
CPU time 12.64 seconds
Started Jun 05 05:49:40 PM PDT 24
Finished Jun 05 05:49:54 PM PDT 24
Peak memory 205716 kb
Host smart-7061bdd7-e60f-4ebf-8fb4-70454d23f8e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17936
70751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1793670751
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.3771351043
Short name T1952
Test name
Test status
Simulation time 10700351829 ps
CPU time 13.65 seconds
Started Jun 05 05:49:46 PM PDT 24
Finished Jun 05 05:50:00 PM PDT 24
Peak memory 205676 kb
Host smart-cc2e4e10-72d7-4535-8e01-b66c2ed23f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37713
51043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.3771351043
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.609013668
Short name T486
Test name
Test status
Simulation time 10128474043 ps
CPU time 14.31 seconds
Started Jun 05 05:49:35 PM PDT 24
Finished Jun 05 05:49:49 PM PDT 24
Peak memory 205680 kb
Host smart-2cd0c26c-17c2-422f-9d5d-00eae476fd56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60901
3668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.609013668
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3109438356
Short name T1999
Test name
Test status
Simulation time 10091858859 ps
CPU time 12.8 seconds
Started Jun 05 05:49:49 PM PDT 24
Finished Jun 05 05:50:03 PM PDT 24
Peak memory 205660 kb
Host smart-b0700f56-e33d-4c37-b67b-4c07bf90b530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31094
38356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3109438356
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1376689073
Short name T1451
Test name
Test status
Simulation time 10039291568 ps
CPU time 14.58 seconds
Started Jun 05 05:49:49 PM PDT 24
Finished Jun 05 05:50:05 PM PDT 24
Peak memory 205740 kb
Host smart-4afaf249-aca7-461a-9e57-e3929ae5e7e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13766
89073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1376689073
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.3875764976
Short name T1236
Test name
Test status
Simulation time 10172936786 ps
CPU time 13.52 seconds
Started Jun 05 05:49:46 PM PDT 24
Finished Jun 05 05:50:00 PM PDT 24
Peak memory 205672 kb
Host smart-ad47e244-5244-4949-a2f2-81e3201c528a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38757
64976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3875764976
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.3339180665
Short name T1536
Test name
Test status
Simulation time 10103116837 ps
CPU time 15.23 seconds
Started Jun 05 05:49:52 PM PDT 24
Finished Jun 05 05:50:08 PM PDT 24
Peak memory 205664 kb
Host smart-349c6631-6990-4630-8485-f3ca1be83aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33391
80665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.3339180665
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.301125661
Short name T2025
Test name
Test status
Simulation time 13199717941 ps
CPU time 18.15 seconds
Started Jun 05 05:49:45 PM PDT 24
Finished Jun 05 05:50:04 PM PDT 24
Peak memory 205760 kb
Host smart-8a6edadf-477d-42f0-9d90-1ea0f86a2041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30112
5661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.301125661
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.97796451
Short name T1675
Test name
Test status
Simulation time 10165832488 ps
CPU time 13.42 seconds
Started Jun 05 05:49:53 PM PDT 24
Finished Jun 05 05:50:07 PM PDT 24
Peak memory 205680 kb
Host smart-9c3149b4-f3de-4bca-95a5-b5030f286fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97796
451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.97796451
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.234492803
Short name T1087
Test name
Test status
Simulation time 16807897805 ps
CPU time 73.24 seconds
Started Jun 05 05:49:45 PM PDT 24
Finished Jun 05 05:50:59 PM PDT 24
Peak memory 205952 kb
Host smart-9280b917-2e53-450e-889a-2dc7fdc3bc37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23449
2803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.234492803
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.4237643911
Short name T1581
Test name
Test status
Simulation time 10049077118 ps
CPU time 15.35 seconds
Started Jun 05 05:49:50 PM PDT 24
Finished Jun 05 05:50:07 PM PDT 24
Peak memory 205756 kb
Host smart-21c29746-bac9-4962-8165-6ae5523c454a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42376
43911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.4237643911
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1049403899
Short name T109
Test name
Test status
Simulation time 10098295759 ps
CPU time 13.93 seconds
Started Jun 05 05:50:00 PM PDT 24
Finished Jun 05 05:50:16 PM PDT 24
Peak memory 205720 kb
Host smart-e6f377d5-0e69-4a66-90dc-4d05100262a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10494
03899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1049403899
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.3627429645
Short name T1611
Test name
Test status
Simulation time 10066767056 ps
CPU time 13.43 seconds
Started Jun 05 05:50:00 PM PDT 24
Finished Jun 05 05:50:15 PM PDT 24
Peak memory 205820 kb
Host smart-b7e0a610-bc58-44cb-b5d0-9e4111518d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36274
29645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.3627429645
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.4241246227
Short name T546
Test name
Test status
Simulation time 10059562137 ps
CPU time 14.6 seconds
Started Jun 05 05:49:50 PM PDT 24
Finished Jun 05 05:50:05 PM PDT 24
Peak memory 205664 kb
Host smart-71b32ad8-dcc7-456a-8090-f764146d8b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42412
46227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.4241246227
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.394430435
Short name T808
Test name
Test status
Simulation time 10053212883 ps
CPU time 13.03 seconds
Started Jun 05 05:49:56 PM PDT 24
Finished Jun 05 05:50:11 PM PDT 24
Peak memory 205612 kb
Host smart-129e836d-600a-40e8-b1ca-a97aa7a59240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39443
0435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.394430435
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.1188353222
Short name T891
Test name
Test status
Simulation time 10056403649 ps
CPU time 13.34 seconds
Started Jun 05 05:49:48 PM PDT 24
Finished Jun 05 05:50:02 PM PDT 24
Peak memory 205672 kb
Host smart-3302fad4-f4fe-4fcb-8946-a8d46e45d6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11883
53222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.1188353222
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_eop_single_bit_handling.3839000019
Short name T702
Test name
Test status
Simulation time 10052868897 ps
CPU time 13.7 seconds
Started Jun 05 05:49:47 PM PDT 24
Finished Jun 05 05:50:01 PM PDT 24
Peak memory 205724 kb
Host smart-83c03d53-e842-4e9e-9bbf-f40a09077b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38390
00019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_eop_single_bit_handling.3839000019
Directory /workspace/48.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.1990117566
Short name T762
Test name
Test status
Simulation time 10135251411 ps
CPU time 13.26 seconds
Started Jun 05 05:50:00 PM PDT 24
Finished Jun 05 05:50:15 PM PDT 24
Peak memory 205712 kb
Host smart-143f3498-37c4-49c2-935a-9bae627123c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19901
17566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.1990117566
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1414014592
Short name T1314
Test name
Test status
Simulation time 10048030007 ps
CPU time 13.54 seconds
Started Jun 05 05:49:49 PM PDT 24
Finished Jun 05 05:50:03 PM PDT 24
Peak memory 205680 kb
Host smart-706afffe-9e40-4125-9dc5-6e6eec4cbac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14140
14592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1414014592
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.2631405502
Short name T1943
Test name
Test status
Simulation time 28703865988 ps
CPU time 54.53 seconds
Started Jun 05 05:49:46 PM PDT 24
Finished Jun 05 05:50:41 PM PDT 24
Peak memory 205672 kb
Host smart-5b4e0b74-6f3e-41e7-9ed8-f9136d8ce51e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26314
05502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.2631405502
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.1764519444
Short name T580
Test name
Test status
Simulation time 10136438492 ps
CPU time 12.5 seconds
Started Jun 05 05:49:48 PM PDT 24
Finished Jun 05 05:50:01 PM PDT 24
Peak memory 205656 kb
Host smart-7f83407d-77db-4fe1-a255-aba0a7738535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17645
19444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.1764519444
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3591466556
Short name T700
Test name
Test status
Simulation time 10131184089 ps
CPU time 15.11 seconds
Started Jun 05 05:49:55 PM PDT 24
Finished Jun 05 05:50:11 PM PDT 24
Peak memory 205732 kb
Host smart-58682748-901c-49d0-b4c0-09d6046d54fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35914
66556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3591466556
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.137027847
Short name T834
Test name
Test status
Simulation time 10045641086 ps
CPU time 16.08 seconds
Started Jun 05 05:49:52 PM PDT 24
Finished Jun 05 05:50:09 PM PDT 24
Peak memory 205452 kb
Host smart-bb2e436d-0924-44b4-ad8a-620954e87f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13702
7847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.137027847
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.1303160913
Short name T1140
Test name
Test status
Simulation time 10053760039 ps
CPU time 14.36 seconds
Started Jun 05 05:49:54 PM PDT 24
Finished Jun 05 05:50:09 PM PDT 24
Peak memory 205612 kb
Host smart-b0d7298d-16e5-4530-871f-a54839c9e977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13031
60913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.1303160913
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.2118962834
Short name T1789
Test name
Test status
Simulation time 10042133620 ps
CPU time 14.19 seconds
Started Jun 05 05:49:58 PM PDT 24
Finished Jun 05 05:50:14 PM PDT 24
Peak memory 205760 kb
Host smart-c925450f-dedb-41cd-91c4-5cb7f211d50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21189
62834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.2118962834
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.1342284869
Short name T1198
Test name
Test status
Simulation time 10063238359 ps
CPU time 12.88 seconds
Started Jun 05 05:49:49 PM PDT 24
Finished Jun 05 05:50:02 PM PDT 24
Peak memory 205696 kb
Host smart-7cfd41dd-88f5-4076-a3cd-38dae9623044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13422
84869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1342284869
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2548033201
Short name T149
Test name
Test status
Simulation time 10142051650 ps
CPU time 13.81 seconds
Started Jun 05 05:49:47 PM PDT 24
Finished Jun 05 05:50:01 PM PDT 24
Peak memory 205740 kb
Host smart-571fbec0-8ca4-424d-b766-d7285d8eb29d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25480
33201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2548033201
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.3280580390
Short name T1606
Test name
Test status
Simulation time 10093462621 ps
CPU time 13.3 seconds
Started Jun 05 05:49:46 PM PDT 24
Finished Jun 05 05:50:00 PM PDT 24
Peak memory 205700 kb
Host smart-908ca3d6-8c4a-4c82-8004-68ac235fc0c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32805
80390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.3280580390
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.1625071338
Short name T1847
Test name
Test status
Simulation time 10059348190 ps
CPU time 14.7 seconds
Started Jun 05 05:49:51 PM PDT 24
Finished Jun 05 05:50:07 PM PDT 24
Peak memory 205764 kb
Host smart-3311259e-c992-4b00-a033-41aa2439a35d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16250
71338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.1625071338
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.140068142
Short name T225
Test name
Test status
Simulation time 17991473905 ps
CPU time 67.98 seconds
Started Jun 05 05:49:50 PM PDT 24
Finished Jun 05 05:50:59 PM PDT 24
Peak memory 205732 kb
Host smart-b440d528-3962-4d7a-a94a-10b34adb439e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14006
8142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.140068142
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.919030700
Short name T1285
Test name
Test status
Simulation time 10148742011 ps
CPU time 14.25 seconds
Started Jun 05 05:49:54 PM PDT 24
Finished Jun 05 05:50:09 PM PDT 24
Peak memory 205764 kb
Host smart-76c49a0f-5969-4f08-bfc0-8aa1f1490cb0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=919030700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.919030700
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.857470539
Short name T398
Test name
Test status
Simulation time 10143892935 ps
CPU time 14.6 seconds
Started Jun 05 05:50:04 PM PDT 24
Finished Jun 05 05:50:20 PM PDT 24
Peak memory 205700 kb
Host smart-d1e72fc4-8d0f-4d6d-9c76-562a538651a0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=857470539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.857470539
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.3712458577
Short name T1846
Test name
Test status
Simulation time 10150360507 ps
CPU time 15.9 seconds
Started Jun 05 05:49:57 PM PDT 24
Finished Jun 05 05:50:15 PM PDT 24
Peak memory 205788 kb
Host smart-893af755-4977-47d1-953d-c661c9eaa396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37124
58577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.3712458577
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.53260581
Short name T16
Test name
Test status
Simulation time 13426470510 ps
CPU time 19.05 seconds
Started Jun 05 05:49:50 PM PDT 24
Finished Jun 05 05:50:09 PM PDT 24
Peak memory 205712 kb
Host smart-72d1f46c-3c85-4977-8251-fb7246e82331
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=53260581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.53260581
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.1876559285
Short name T1856
Test name
Test status
Simulation time 23255158508 ps
CPU time 29.33 seconds
Started Jun 05 05:49:54 PM PDT 24
Finished Jun 05 05:50:24 PM PDT 24
Peak memory 205616 kb
Host smart-4c58e605-b979-4e1e-93df-1611c84cadf6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1876559285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.1876559285
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3297833246
Short name T837
Test name
Test status
Simulation time 10112437983 ps
CPU time 13.39 seconds
Started Jun 05 05:49:52 PM PDT 24
Finished Jun 05 05:50:06 PM PDT 24
Peak memory 205764 kb
Host smart-25c7b044-96c2-457c-afd9-59c77d38040a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32978
33246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3297833246
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.2632335076
Short name T72
Test name
Test status
Simulation time 10090845015 ps
CPU time 15.33 seconds
Started Jun 05 05:49:43 PM PDT 24
Finished Jun 05 05:49:59 PM PDT 24
Peak memory 205708 kb
Host smart-fed3e0f9-cd44-4b5d-b581-37586eac2a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26323
35076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.2632335076
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.1827440327
Short name T1069
Test name
Test status
Simulation time 10046331607 ps
CPU time 13.97 seconds
Started Jun 05 05:49:52 PM PDT 24
Finished Jun 05 05:50:07 PM PDT 24
Peak memory 205668 kb
Host smart-0f0aa968-738e-44be-98fc-fe732fe9ae4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18274
40327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.1827440327
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.748062440
Short name T1761
Test name
Test status
Simulation time 10113485649 ps
CPU time 13.18 seconds
Started Jun 05 05:49:52 PM PDT 24
Finished Jun 05 05:50:06 PM PDT 24
Peak memory 205588 kb
Host smart-534c56ba-f1fb-476c-98c3-b7a5dfc202d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74806
2440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.748062440
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.1207446610
Short name T1016
Test name
Test status
Simulation time 10695950994 ps
CPU time 13.85 seconds
Started Jun 05 05:49:52 PM PDT 24
Finished Jun 05 05:50:07 PM PDT 24
Peak memory 205728 kb
Host smart-59fca15e-d84d-4e41-b0d3-2637725d8203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12074
46610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.1207446610
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.3659852528
Short name T428
Test name
Test status
Simulation time 10091184537 ps
CPU time 16.95 seconds
Started Jun 05 05:49:50 PM PDT 24
Finished Jun 05 05:50:08 PM PDT 24
Peak memory 205756 kb
Host smart-0a206bcc-34a4-4cbe-b54c-f9d484cbe0f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36598
52528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3659852528
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1003364830
Short name T1976
Test name
Test status
Simulation time 10132666533 ps
CPU time 15.03 seconds
Started Jun 05 05:49:59 PM PDT 24
Finished Jun 05 05:50:15 PM PDT 24
Peak memory 205676 kb
Host smart-566e11b9-3e9e-4f66-ab01-eeeb4767ae91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10033
64830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1003364830
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.2227155262
Short name T910
Test name
Test status
Simulation time 10046325212 ps
CPU time 13.51 seconds
Started Jun 05 05:49:57 PM PDT 24
Finished Jun 05 05:50:12 PM PDT 24
Peak memory 205744 kb
Host smart-a3ee063c-fe6f-4739-8886-ae929522dd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22271
55262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.2227155262
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3120311469
Short name T854
Test name
Test status
Simulation time 10118237049 ps
CPU time 13.45 seconds
Started Jun 05 05:49:48 PM PDT 24
Finished Jun 05 05:50:02 PM PDT 24
Peak memory 205764 kb
Host smart-60a607df-919f-4cc7-9b46-e74af6c31296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31203
11469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3120311469
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.2921474484
Short name T792
Test name
Test status
Simulation time 10119211280 ps
CPU time 13.73 seconds
Started Jun 05 05:49:53 PM PDT 24
Finished Jun 05 05:50:07 PM PDT 24
Peak memory 205676 kb
Host smart-a144527e-eca9-4314-99f3-b9cd2f07e961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29214
74484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.2921474484
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.424307554
Short name T1674
Test name
Test status
Simulation time 13298253753 ps
CPU time 17.13 seconds
Started Jun 05 05:49:47 PM PDT 24
Finished Jun 05 05:50:05 PM PDT 24
Peak memory 205652 kb
Host smart-b6d7ac5f-bf41-4caa-8caf-6a4713ef4947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42430
7554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.424307554
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.1696545528
Short name T1218
Test name
Test status
Simulation time 10079969736 ps
CPU time 15.23 seconds
Started Jun 05 05:49:48 PM PDT 24
Finished Jun 05 05:50:04 PM PDT 24
Peak memory 205676 kb
Host smart-1c774151-9990-4655-9c20-e41f5b42e8e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16965
45528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.1696545528
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.1411133915
Short name T408
Test name
Test status
Simulation time 16573838619 ps
CPU time 203.27 seconds
Started Jun 05 05:49:50 PM PDT 24
Finished Jun 05 05:53:15 PM PDT 24
Peak memory 205684 kb
Host smart-1f111840-cb1c-402a-9782-f30906f360c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14111
33915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.1411133915
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.266896930
Short name T1331
Test name
Test status
Simulation time 10046568775 ps
CPU time 15.48 seconds
Started Jun 05 05:49:48 PM PDT 24
Finished Jun 05 05:50:04 PM PDT 24
Peak memory 205700 kb
Host smart-84483fc2-36de-4624-aa67-b70cb998e537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26689
6930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.266896930
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.4120481046
Short name T98
Test name
Test status
Simulation time 10076888654 ps
CPU time 13.72 seconds
Started Jun 05 05:49:50 PM PDT 24
Finished Jun 05 05:50:05 PM PDT 24
Peak memory 205640 kb
Host smart-77a52ebf-a584-42eb-a7d6-0df8868ab4a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41204
81046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.4120481046
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.2491228343
Short name T1621
Test name
Test status
Simulation time 10070250537 ps
CPU time 14.56 seconds
Started Jun 05 05:49:54 PM PDT 24
Finished Jun 05 05:50:10 PM PDT 24
Peak memory 205716 kb
Host smart-0af7077b-a5dc-4616-bf07-26c979c70ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24912
28343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.2491228343
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.2719141095
Short name T1003
Test name
Test status
Simulation time 10074193802 ps
CPU time 13.47 seconds
Started Jun 05 05:50:00 PM PDT 24
Finished Jun 05 05:50:15 PM PDT 24
Peak memory 205788 kb
Host smart-d22510ea-129b-45d7-996f-4a5b6fbf92f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27191
41095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.2719141095
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1984592666
Short name T1411
Test name
Test status
Simulation time 10048127197 ps
CPU time 16.69 seconds
Started Jun 05 05:49:54 PM PDT 24
Finished Jun 05 05:50:12 PM PDT 24
Peak memory 205736 kb
Host smart-cc2906d3-33a6-49c1-92ca-cd5e81371302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19845
92666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1984592666
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.2395387952
Short name T66
Test name
Test status
Simulation time 10063443500 ps
CPU time 15.28 seconds
Started Jun 05 05:49:56 PM PDT 24
Finished Jun 05 05:50:11 PM PDT 24
Peak memory 205712 kb
Host smart-d2bbb7b1-c0c2-4f7f-a6d5-3d7e196a5822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23953
87952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.2395387952
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_eop_single_bit_handling.2918208277
Short name T865
Test name
Test status
Simulation time 10044039360 ps
CPU time 14.77 seconds
Started Jun 05 05:50:04 PM PDT 24
Finished Jun 05 05:50:20 PM PDT 24
Peak memory 205660 kb
Host smart-044be92d-8bf6-42d0-8fc9-785faaa5199e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29182
08277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_eop_single_bit_handling.2918208277
Directory /workspace/49.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.996376421
Short name T954
Test name
Test status
Simulation time 10042042725 ps
CPU time 15.55 seconds
Started Jun 05 05:49:53 PM PDT 24
Finished Jun 05 05:50:09 PM PDT 24
Peak memory 205584 kb
Host smart-5cb33162-a11c-465b-9216-cb16041aa706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99637
6421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.996376421
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.2070944085
Short name T988
Test name
Test status
Simulation time 25752896066 ps
CPU time 45.93 seconds
Started Jun 05 05:49:49 PM PDT 24
Finished Jun 05 05:50:36 PM PDT 24
Peak memory 205676 kb
Host smart-5a93262e-5f17-4724-bd7c-eeb092812793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20709
44085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.2070944085
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1151554450
Short name T1499
Test name
Test status
Simulation time 10085417009 ps
CPU time 13.28 seconds
Started Jun 05 05:49:53 PM PDT 24
Finished Jun 05 05:50:08 PM PDT 24
Peak memory 205744 kb
Host smart-966294fd-a324-45cc-9720-cd36ca88dcdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11515
54450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1151554450
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.3338216921
Short name T640
Test name
Test status
Simulation time 10100230195 ps
CPU time 12.52 seconds
Started Jun 05 05:49:58 PM PDT 24
Finished Jun 05 05:50:12 PM PDT 24
Peak memory 205684 kb
Host smart-57787f0a-aeb1-4b98-9280-fedeac36b265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33382
16921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.3338216921
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.1796300706
Short name T350
Test name
Test status
Simulation time 10071133347 ps
CPU time 14.88 seconds
Started Jun 05 05:49:51 PM PDT 24
Finished Jun 05 05:50:07 PM PDT 24
Peak memory 205696 kb
Host smart-7f73bc3e-5b47-4e02-b6bc-69f054e32182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17963
00706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.1796300706
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.708709668
Short name T496
Test name
Test status
Simulation time 10046161019 ps
CPU time 13.91 seconds
Started Jun 05 05:50:01 PM PDT 24
Finished Jun 05 05:50:17 PM PDT 24
Peak memory 205684 kb
Host smart-1d048807-2b6d-4c94-bd57-899dcdaf75ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70870
9668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.708709668
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.2144722606
Short name T1059
Test name
Test status
Simulation time 10043979354 ps
CPU time 15.25 seconds
Started Jun 05 05:49:58 PM PDT 24
Finished Jun 05 05:50:14 PM PDT 24
Peak memory 205684 kb
Host smart-7b614e8d-beaf-4df5-948d-34f0176673da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21447
22606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.2144722606
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.593459791
Short name T922
Test name
Test status
Simulation time 10052380105 ps
CPU time 14.76 seconds
Started Jun 05 05:49:56 PM PDT 24
Finished Jun 05 05:50:12 PM PDT 24
Peak memory 205784 kb
Host smart-f2aaf7f7-7414-402d-9e4d-6facd1498794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59345
9791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.593459791
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.4267229642
Short name T1521
Test name
Test status
Simulation time 10138846048 ps
CPU time 13.47 seconds
Started Jun 05 05:49:44 PM PDT 24
Finished Jun 05 05:49:59 PM PDT 24
Peak memory 205696 kb
Host smart-69f8930d-087b-44f4-bd79-f560fb4bd558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42672
29642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.4267229642
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.4100887121
Short name T1551
Test name
Test status
Simulation time 10075924634 ps
CPU time 15.84 seconds
Started Jun 05 05:49:50 PM PDT 24
Finished Jun 05 05:50:07 PM PDT 24
Peak memory 205700 kb
Host smart-743a0976-9ced-46b7-ba45-ed1c7b0b836c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41008
87121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.4100887121
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1488488801
Short name T298
Test name
Test status
Simulation time 10065364664 ps
CPU time 14.52 seconds
Started Jun 05 05:49:54 PM PDT 24
Finished Jun 05 05:50:10 PM PDT 24
Peak memory 205724 kb
Host smart-e128a100-4aae-4b90-b8a3-f66967aee57a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14884
88801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1488488801
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.2971643390
Short name T1950
Test name
Test status
Simulation time 18947486778 ps
CPU time 95.25 seconds
Started Jun 05 05:49:52 PM PDT 24
Finished Jun 05 05:51:28 PM PDT 24
Peak memory 205692 kb
Host smart-3aceb7e4-0abd-435f-a47c-53e0af84d9be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29716
43390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.2971643390
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.1097375018
Short name T1027
Test name
Test status
Simulation time 10136917335 ps
CPU time 17.33 seconds
Started Jun 05 05:44:55 PM PDT 24
Finished Jun 05 05:45:13 PM PDT 24
Peak memory 205716 kb
Host smart-2b932d15-d1a6-4585-9df3-541b45ad0980
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1097375018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.1097375018
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.2545355566
Short name T682
Test name
Test status
Simulation time 10053775059 ps
CPU time 16.03 seconds
Started Jun 05 05:44:44 PM PDT 24
Finished Jun 05 05:45:01 PM PDT 24
Peak memory 205700 kb
Host smart-c187f5fc-af2a-417f-8415-c5052b8fd167
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2545355566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.2545355566
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.3757775177
Short name T554
Test name
Test status
Simulation time 10135111756 ps
CPU time 12.87 seconds
Started Jun 05 05:44:46 PM PDT 24
Finished Jun 05 05:45:00 PM PDT 24
Peak memory 205868 kb
Host smart-ddd7a8d4-3d7d-4aee-aebd-3725f22e4176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37577
75177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.3757775177
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.1084645230
Short name T1114
Test name
Test status
Simulation time 13646659205 ps
CPU time 20.74 seconds
Started Jun 05 05:44:38 PM PDT 24
Finished Jun 05 05:44:59 PM PDT 24
Peak memory 205732 kb
Host smart-d1ca0f85-5ff7-4476-a1c7-eec60ed290bb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1084645230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.1084645230
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2669691156
Short name T419
Test name
Test status
Simulation time 23201452134 ps
CPU time 24.12 seconds
Started Jun 05 05:44:46 PM PDT 24
Finished Jun 05 05:45:11 PM PDT 24
Peak memory 205808 kb
Host smart-9d349c84-ef11-4ecb-8f20-1442a9849eb3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2669691156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2669691156
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.3687813255
Short name T1734
Test name
Test status
Simulation time 10058968264 ps
CPU time 14.41 seconds
Started Jun 05 05:44:42 PM PDT 24
Finished Jun 05 05:44:58 PM PDT 24
Peak memory 205500 kb
Host smart-be4515bd-dcae-4031-9001-20361e813c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36878
13255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.3687813255
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.930571540
Short name T1335
Test name
Test status
Simulation time 10068545597 ps
CPU time 15.87 seconds
Started Jun 05 05:44:45 PM PDT 24
Finished Jun 05 05:45:02 PM PDT 24
Peak memory 205748 kb
Host smart-f20e8d58-305d-4fe7-bada-8d20b2b002fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93057
1540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.930571540
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.4125341513
Short name T151
Test name
Test status
Simulation time 11147987282 ps
CPU time 16.7 seconds
Started Jun 05 05:44:39 PM PDT 24
Finished Jun 05 05:44:56 PM PDT 24
Peak memory 205696 kb
Host smart-2452281c-dd29-4025-9eeb-30e0d742274c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41253
41513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.4125341513
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.3237440732
Short name T442
Test name
Test status
Simulation time 10044044620 ps
CPU time 14.67 seconds
Started Jun 05 05:44:45 PM PDT 24
Finished Jun 05 05:45:00 PM PDT 24
Peak memory 205732 kb
Host smart-320eead1-2f83-468c-b6ec-46702064a3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32374
40732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.3237440732
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.2971536074
Short name T1225
Test name
Test status
Simulation time 10055026862 ps
CPU time 13.49 seconds
Started Jun 05 05:44:45 PM PDT 24
Finished Jun 05 05:44:59 PM PDT 24
Peak memory 205688 kb
Host smart-f93a337a-8e5c-47c5-aa1a-dff5481f3134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29715
36074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2971536074
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.3505003105
Short name T911
Test name
Test status
Simulation time 10970316399 ps
CPU time 16.58 seconds
Started Jun 05 05:44:39 PM PDT 24
Finished Jun 05 05:44:56 PM PDT 24
Peak memory 205740 kb
Host smart-595d64f6-effe-4bca-8467-f1a78fc69df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35050
03105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.3505003105
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.619744400
Short name T923
Test name
Test status
Simulation time 10098582828 ps
CPU time 14.68 seconds
Started Jun 05 05:44:46 PM PDT 24
Finished Jun 05 05:45:01 PM PDT 24
Peak memory 205756 kb
Host smart-5fcc68b0-fbda-447b-99c3-08415bd3ab95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61974
4400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.619744400
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.771209518
Short name T738
Test name
Test status
Simulation time 10107653459 ps
CPU time 14.24 seconds
Started Jun 05 05:44:46 PM PDT 24
Finished Jun 05 05:45:01 PM PDT 24
Peak memory 205728 kb
Host smart-e74bd6b3-eb62-4bd7-ba8d-1c3017ffd6c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77120
9518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.771209518
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.3908600267
Short name T1419
Test name
Test status
Simulation time 10050020851 ps
CPU time 13.54 seconds
Started Jun 05 05:44:44 PM PDT 24
Finished Jun 05 05:44:58 PM PDT 24
Peak memory 205564 kb
Host smart-8db10194-5da1-42ee-bb92-ab4d6547031e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39086
00267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.3908600267
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.2682938783
Short name T1485
Test name
Test status
Simulation time 10187414425 ps
CPU time 16.44 seconds
Started Jun 05 05:44:55 PM PDT 24
Finished Jun 05 05:45:12 PM PDT 24
Peak memory 205716 kb
Host smart-79751e11-afac-4ae9-8885-d5978dd7c2a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26829
38783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.2682938783
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.3270188780
Short name T1189
Test name
Test status
Simulation time 10076017430 ps
CPU time 13.1 seconds
Started Jun 05 05:44:44 PM PDT 24
Finished Jun 05 05:44:58 PM PDT 24
Peak memory 205676 kb
Host smart-b6e5c748-0874-4b16-904f-eb9e17dac383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32701
88780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.3270188780
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.1547976283
Short name T340
Test name
Test status
Simulation time 13253654713 ps
CPU time 15.69 seconds
Started Jun 05 05:44:43 PM PDT 24
Finished Jun 05 05:44:59 PM PDT 24
Peak memory 205732 kb
Host smart-491f6fd4-ac3f-4fc9-a18a-5fe32abefee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15479
76283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.1547976283
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.379634180
Short name T1038
Test name
Test status
Simulation time 10152840099 ps
CPU time 15.66 seconds
Started Jun 05 05:44:46 PM PDT 24
Finished Jun 05 05:45:02 PM PDT 24
Peak memory 205656 kb
Host smart-c3cf7d14-768f-404b-b009-1995c69f00dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37963
4180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.379634180
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.1149119620
Short name T1054
Test name
Test status
Simulation time 15633300746 ps
CPU time 176.33 seconds
Started Jun 05 05:44:44 PM PDT 24
Finished Jun 05 05:47:41 PM PDT 24
Peak memory 205708 kb
Host smart-b78e748a-9d47-4f42-9822-41287d9baea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11491
19620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.1149119620
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.869505297
Short name T337
Test name
Test status
Simulation time 10069039134 ps
CPU time 16.35 seconds
Started Jun 05 05:44:43 PM PDT 24
Finished Jun 05 05:45:00 PM PDT 24
Peak memory 205680 kb
Host smart-d8ef03b6-8a55-4561-b6d6-5678ba77a9f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86950
5297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.869505297
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.4159856558
Short name T99
Test name
Test status
Simulation time 10063986463 ps
CPU time 13.01 seconds
Started Jun 05 05:44:42 PM PDT 24
Finished Jun 05 05:44:56 PM PDT 24
Peak memory 205760 kb
Host smart-af244ba9-42f1-4515-adea-3ce466fae8d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41598
56558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.4159856558
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.2770316100
Short name T78
Test name
Test status
Simulation time 10076388171 ps
CPU time 15.1 seconds
Started Jun 05 05:44:43 PM PDT 24
Finished Jun 05 05:44:59 PM PDT 24
Peak memory 205756 kb
Host smart-6a13759c-80c9-46ab-b32c-c107823e8942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27703
16100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.2770316100
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.2846641407
Short name T1447
Test name
Test status
Simulation time 10087260776 ps
CPU time 13.86 seconds
Started Jun 05 05:44:44 PM PDT 24
Finished Jun 05 05:44:59 PM PDT 24
Peak memory 205764 kb
Host smart-5593520b-3039-4a79-bbe3-45c61b3d106f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28466
41407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2846641407
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.380501296
Short name T1116
Test name
Test status
Simulation time 10087410390 ps
CPU time 15.04 seconds
Started Jun 05 05:44:43 PM PDT 24
Finished Jun 05 05:44:58 PM PDT 24
Peak memory 205640 kb
Host smart-a4ec0e09-6958-4a8a-b192-d52c6ae176e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38050
1296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.380501296
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3881935560
Short name T779
Test name
Test status
Simulation time 10053631647 ps
CPU time 13.16 seconds
Started Jun 05 05:44:44 PM PDT 24
Finished Jun 05 05:44:58 PM PDT 24
Peak memory 205644 kb
Host smart-ce4a9bc3-d8d5-4935-aa70-2fc68cf9838c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38819
35560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3881935560
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_eop_single_bit_handling.1689854798
Short name T197
Test name
Test status
Simulation time 10065120583 ps
CPU time 15.3 seconds
Started Jun 05 05:44:45 PM PDT 24
Finished Jun 05 05:45:01 PM PDT 24
Peak memory 205668 kb
Host smart-3fdc07d0-8cbf-4cfb-8f06-1bcad1a99c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16898
54798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_eop_single_bit_handling.1689854798
Directory /workspace/5.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.2983544496
Short name T895
Test name
Test status
Simulation time 10048635907 ps
CPU time 13.12 seconds
Started Jun 05 05:44:49 PM PDT 24
Finished Jun 05 05:45:02 PM PDT 24
Peak memory 205740 kb
Host smart-d6f33912-3ef6-436b-b0f8-233b24cad180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29835
44496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.2983544496
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.1982149871
Short name T1914
Test name
Test status
Simulation time 10057324380 ps
CPU time 16.07 seconds
Started Jun 05 05:44:44 PM PDT 24
Finished Jun 05 05:45:01 PM PDT 24
Peak memory 205708 kb
Host smart-3893e30c-08cf-4cd5-a00c-5cfcd30ea8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19821
49871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.1982149871
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.4019803454
Short name T1803
Test name
Test status
Simulation time 22331050249 ps
CPU time 39.75 seconds
Started Jun 05 05:44:42 PM PDT 24
Finished Jun 05 05:45:23 PM PDT 24
Peak memory 205656 kb
Host smart-b4d51c7b-48dc-4f32-9e71-bdf92486ac77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40198
03454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.4019803454
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.3177108690
Short name T1440
Test name
Test status
Simulation time 10075190413 ps
CPU time 14.4 seconds
Started Jun 05 05:44:45 PM PDT 24
Finished Jun 05 05:45:00 PM PDT 24
Peak memory 205744 kb
Host smart-49896758-7c70-45b9-a7ef-e6c1fd92e0ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31771
08690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3177108690
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.3927598271
Short name T816
Test name
Test status
Simulation time 10075216791 ps
CPU time 12.91 seconds
Started Jun 05 05:44:45 PM PDT 24
Finished Jun 05 05:44:59 PM PDT 24
Peak memory 205708 kb
Host smart-3fc3346d-90ba-4db1-8552-f1a9d50dbe0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39275
98271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.3927598271
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.2297241139
Short name T173
Test name
Test status
Simulation time 20808493306 ps
CPU time 83.08 seconds
Started Jun 05 05:44:45 PM PDT 24
Finished Jun 05 05:46:09 PM PDT 24
Peak memory 205784 kb
Host smart-c94cc288-3cd1-4000-a8fc-0e9bc2bbf5cd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2297241139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.2297241139
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.55277067
Short name T178
Test name
Test status
Simulation time 35031908406 ps
CPU time 220.95 seconds
Started Jun 05 05:44:55 PM PDT 24
Finished Jun 05 05:48:37 PM PDT 24
Peak memory 205612 kb
Host smart-3269f61b-f6bd-43cc-976e-d8ff81b9854f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=55277067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.55277067
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.2248428256
Short name T80
Test name
Test status
Simulation time 10083268900 ps
CPU time 12.95 seconds
Started Jun 05 05:44:42 PM PDT 24
Finished Jun 05 05:44:56 PM PDT 24
Peak memory 205704 kb
Host smart-10891ba2-4212-43cc-837f-5b712087763e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22484
28256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.2248428256
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.630671100
Short name T1039
Test name
Test status
Simulation time 10053731473 ps
CPU time 13.81 seconds
Started Jun 05 05:44:47 PM PDT 24
Finished Jun 05 05:45:01 PM PDT 24
Peak memory 205752 kb
Host smart-bc3fa656-d8cd-4509-9a28-362fd213929d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63067
1100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.630671100
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.2697064591
Short name T2018
Test name
Test status
Simulation time 10065343851 ps
CPU time 13.49 seconds
Started Jun 05 05:44:46 PM PDT 24
Finished Jun 05 05:45:00 PM PDT 24
Peak memory 205920 kb
Host smart-9435a29a-1fc3-4369-b5d4-f2ad0df74e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26970
64591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.2697064591
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.2294934926
Short name T786
Test name
Test status
Simulation time 10044830344 ps
CPU time 16.16 seconds
Started Jun 05 05:44:45 PM PDT 24
Finished Jun 05 05:45:02 PM PDT 24
Peak memory 205708 kb
Host smart-3e683527-7913-4c55-8561-9f0a9508208f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22949
34926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.2294934926
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1806056413
Short name T1959
Test name
Test status
Simulation time 10105305623 ps
CPU time 12.48 seconds
Started Jun 05 05:44:39 PM PDT 24
Finished Jun 05 05:44:52 PM PDT 24
Peak memory 205820 kb
Host smart-37f2b879-0b5e-4e92-8f78-9558ed8115a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18060
56413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1806056413
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.3024430720
Short name T1154
Test name
Test status
Simulation time 10050352892 ps
CPU time 17.26 seconds
Started Jun 05 05:44:42 PM PDT 24
Finished Jun 05 05:45:00 PM PDT 24
Peak memory 205768 kb
Host smart-f4ab8574-63b7-4991-a0c5-b1bc6c0338f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30244
30720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.3024430720
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.1567348293
Short name T1356
Test name
Test status
Simulation time 10094436383 ps
CPU time 14.78 seconds
Started Jun 05 05:44:46 PM PDT 24
Finished Jun 05 05:45:01 PM PDT 24
Peak memory 205976 kb
Host smart-c3f5ff4c-c0d3-404f-8e45-e291e7824a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15673
48293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.1567348293
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.2281544236
Short name T633
Test name
Test status
Simulation time 24753999796 ps
CPU time 121.93 seconds
Started Jun 05 05:44:44 PM PDT 24
Finished Jun 05 05:46:46 PM PDT 24
Peak memory 205672 kb
Host smart-d1888a8a-92a5-4d4a-baa7-4e75789fed71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22815
44236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.2281544236
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.2908620196
Short name T1663
Test name
Test status
Simulation time 10199369140 ps
CPU time 13.91 seconds
Started Jun 05 05:44:59 PM PDT 24
Finished Jun 05 05:45:13 PM PDT 24
Peak memory 205764 kb
Host smart-451e1951-53a0-406b-af39-209b63887619
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2908620196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.2908620196
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.3396342117
Short name T807
Test name
Test status
Simulation time 10059014896 ps
CPU time 13.91 seconds
Started Jun 05 05:44:57 PM PDT 24
Finished Jun 05 05:45:11 PM PDT 24
Peak memory 205620 kb
Host smart-d675bf4a-ae1e-43fa-97be-4db821cdc905
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3396342117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.3396342117
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.4248467092
Short name T1859
Test name
Test status
Simulation time 10129083840 ps
CPU time 13.03 seconds
Started Jun 05 05:44:58 PM PDT 24
Finished Jun 05 05:45:12 PM PDT 24
Peak memory 205784 kb
Host smart-7b42934d-0098-4650-ae4d-1d707240c2fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42484
67092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.4248467092
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.1664319809
Short name T1024
Test name
Test status
Simulation time 13437955580 ps
CPU time 16.31 seconds
Started Jun 05 05:44:55 PM PDT 24
Finished Jun 05 05:45:12 PM PDT 24
Peak memory 205512 kb
Host smart-4ef08cc6-7d76-4b67-9d39-6f48187bb2a4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1664319809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.1664319809
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.2781835413
Short name T1694
Test name
Test status
Simulation time 23322527143 ps
CPU time 24.52 seconds
Started Jun 05 05:44:44 PM PDT 24
Finished Jun 05 05:45:09 PM PDT 24
Peak memory 205760 kb
Host smart-0858fa92-4245-4904-887a-fcf24026687f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2781835413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.2781835413
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.4021827312
Short name T863
Test name
Test status
Simulation time 10057145741 ps
CPU time 13.56 seconds
Started Jun 05 05:44:43 PM PDT 24
Finished Jun 05 05:44:57 PM PDT 24
Peak memory 205764 kb
Host smart-9721de7c-f715-4f2b-8891-ed06666211d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40218
27312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.4021827312
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.2234291863
Short name T2012
Test name
Test status
Simulation time 10179211710 ps
CPU time 13.49 seconds
Started Jun 05 05:44:51 PM PDT 24
Finished Jun 05 05:45:05 PM PDT 24
Peak memory 205656 kb
Host smart-a7f7796b-853c-4b2d-9d0a-309a537e473a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22342
91863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.2234291863
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.1869196844
Short name T1939
Test name
Test status
Simulation time 10042323595 ps
CPU time 13.44 seconds
Started Jun 05 05:44:52 PM PDT 24
Finished Jun 05 05:45:06 PM PDT 24
Peak memory 205760 kb
Host smart-1f124ed0-f59a-4a02-8635-4ee96e9443f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18691
96844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.1869196844
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.2729599608
Short name T1492
Test name
Test status
Simulation time 10049316838 ps
CPU time 13.09 seconds
Started Jun 05 05:44:55 PM PDT 24
Finished Jun 05 05:45:09 PM PDT 24
Peak memory 205568 kb
Host smart-c458431b-76f0-454b-9726-4fa206db103d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27295
99608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.2729599608
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.2168026330
Short name T771
Test name
Test status
Simulation time 10738713919 ps
CPU time 16.94 seconds
Started Jun 05 05:44:55 PM PDT 24
Finished Jun 05 05:45:13 PM PDT 24
Peak memory 205728 kb
Host smart-5f9736f4-5d91-4d5f-873c-d51a65ac7cc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21680
26330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.2168026330
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.958959626
Short name T883
Test name
Test status
Simulation time 10297902984 ps
CPU time 14.37 seconds
Started Jun 05 05:44:53 PM PDT 24
Finished Jun 05 05:45:08 PM PDT 24
Peak memory 205780 kb
Host smart-652425d4-b0c8-4efc-8848-3b258c2682df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95895
9626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.958959626
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.2371658957
Short name T1074
Test name
Test status
Simulation time 10161878408 ps
CPU time 13.64 seconds
Started Jun 05 05:45:00 PM PDT 24
Finished Jun 05 05:45:15 PM PDT 24
Peak memory 205728 kb
Host smart-7a51dcaa-2957-415c-94f0-8d0f87e94193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23716
58957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.2371658957
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.2032110485
Short name T715
Test name
Test status
Simulation time 10042967986 ps
CPU time 14.25 seconds
Started Jun 05 05:45:00 PM PDT 24
Finished Jun 05 05:45:15 PM PDT 24
Peak memory 205764 kb
Host smart-ed38d82f-11f9-49e0-bb46-83eb1e538464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20321
10485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.2032110485
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.3034611365
Short name T1802
Test name
Test status
Simulation time 10178911353 ps
CPU time 15.85 seconds
Started Jun 05 05:44:54 PM PDT 24
Finished Jun 05 05:45:10 PM PDT 24
Peak memory 205668 kb
Host smart-f8bc8b5b-964e-4988-a4d9-68afbf656976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30346
11365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.3034611365
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.35446607
Short name T1009
Test name
Test status
Simulation time 10123238506 ps
CPU time 14.1 seconds
Started Jun 05 05:44:52 PM PDT 24
Finished Jun 05 05:45:06 PM PDT 24
Peak memory 205844 kb
Host smart-a9d19a79-f005-456b-aad1-09f90eb17812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35446
607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.35446607
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.3000794742
Short name T2027
Test name
Test status
Simulation time 13218951610 ps
CPU time 17.23 seconds
Started Jun 05 05:44:56 PM PDT 24
Finished Jun 05 05:45:14 PM PDT 24
Peak memory 205724 kb
Host smart-0d65343e-de70-4e73-8324-3ec1b15e2109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30007
94742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.3000794742
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1588496160
Short name T1746
Test name
Test status
Simulation time 10093515167 ps
CPU time 12.81 seconds
Started Jun 05 05:44:54 PM PDT 24
Finished Jun 05 05:45:08 PM PDT 24
Peak memory 205736 kb
Host smart-f977ef8f-d3f4-4cb7-ac25-064edf882dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15884
96160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1588496160
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.2459091087
Short name T1561
Test name
Test status
Simulation time 18948758113 ps
CPU time 264.67 seconds
Started Jun 05 05:44:54 PM PDT 24
Finished Jun 05 05:49:19 PM PDT 24
Peak memory 205660 kb
Host smart-f710bbeb-e07e-470f-8937-fe62364b21fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24590
91087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.2459091087
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.2731609428
Short name T1004
Test name
Test status
Simulation time 10038216362 ps
CPU time 15.88 seconds
Started Jun 05 05:44:54 PM PDT 24
Finished Jun 05 05:45:11 PM PDT 24
Peak memory 205724 kb
Host smart-d644f156-0cd8-48ae-ab24-65dcdfadb94b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27316
09428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.2731609428
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.1369836658
Short name T103
Test name
Test status
Simulation time 10110052875 ps
CPU time 14.32 seconds
Started Jun 05 05:44:53 PM PDT 24
Finished Jun 05 05:45:08 PM PDT 24
Peak memory 205664 kb
Host smart-58d5bbd5-8568-4cba-a8dc-948f0458402b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13698
36658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.1369836658
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.1194283356
Short name T523
Test name
Test status
Simulation time 10100594441 ps
CPU time 14.23 seconds
Started Jun 05 05:44:57 PM PDT 24
Finished Jun 05 05:45:11 PM PDT 24
Peak memory 205644 kb
Host smart-cfadb28b-22ba-4cd8-9201-ade7ee05244f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11942
83356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.1194283356
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.2225191333
Short name T1062
Test name
Test status
Simulation time 10101758235 ps
CPU time 13.25 seconds
Started Jun 05 05:44:54 PM PDT 24
Finished Jun 05 05:45:08 PM PDT 24
Peak memory 205680 kb
Host smart-2d247cdf-ec6c-419e-be0f-7ee177f757b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22251
91333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.2225191333
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1089102880
Short name T1015
Test name
Test status
Simulation time 10053489335 ps
CPU time 12.3 seconds
Started Jun 05 05:44:57 PM PDT 24
Finished Jun 05 05:45:10 PM PDT 24
Peak memory 205688 kb
Host smart-bbd6b982-20ee-4caf-9dfe-5a9f90690efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10891
02880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1089102880
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.1832038292
Short name T623
Test name
Test status
Simulation time 10095341158 ps
CPU time 13.74 seconds
Started Jun 05 05:44:57 PM PDT 24
Finished Jun 05 05:45:11 PM PDT 24
Peak memory 205752 kb
Host smart-a24be778-d25d-4ed0-a508-711183d1c66b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18320
38292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.1832038292
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_eop_single_bit_handling.3056847778
Short name T437
Test name
Test status
Simulation time 10100528181 ps
CPU time 13.58 seconds
Started Jun 05 05:44:59 PM PDT 24
Finished Jun 05 05:45:13 PM PDT 24
Peak memory 205688 kb
Host smart-35840b24-eea1-4d78-a53c-2dd3df7328f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30568
47778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_eop_single_bit_handling.3056847778
Directory /workspace/6.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.3510459504
Short name T1309
Test name
Test status
Simulation time 10049057211 ps
CPU time 16.5 seconds
Started Jun 05 05:44:58 PM PDT 24
Finished Jun 05 05:45:15 PM PDT 24
Peak memory 205764 kb
Host smart-84e7851a-100b-4abd-9098-59e271a373c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35104
59504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.3510459504
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.2276264209
Short name T18
Test name
Test status
Simulation time 10042247028 ps
CPU time 14.45 seconds
Started Jun 05 05:45:00 PM PDT 24
Finished Jun 05 05:45:16 PM PDT 24
Peak memory 205664 kb
Host smart-6c267789-717d-42a8-a3b3-f3cd6f8efe8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22762
64209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.2276264209
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.2131074963
Short name T1203
Test name
Test status
Simulation time 30761994769 ps
CPU time 73.73 seconds
Started Jun 05 05:44:57 PM PDT 24
Finished Jun 05 05:46:11 PM PDT 24
Peak memory 205896 kb
Host smart-25a5c86b-0849-489c-8d6a-c5fca74444b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21310
74963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.2131074963
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.3682628461
Short name T1286
Test name
Test status
Simulation time 10124124861 ps
CPU time 15.38 seconds
Started Jun 05 05:44:59 PM PDT 24
Finished Jun 05 05:45:15 PM PDT 24
Peak memory 205764 kb
Host smart-4a8e8d1e-9068-459b-a338-0972a3b8f53a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36826
28461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.3682628461
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2266655070
Short name T749
Test name
Test status
Simulation time 10111061898 ps
CPU time 14.36 seconds
Started Jun 05 05:44:57 PM PDT 24
Finished Jun 05 05:45:12 PM PDT 24
Peak memory 205680 kb
Host smart-a96acf3a-ced5-4a54-ae9d-e015c89be990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22666
55070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2266655070
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.896291456
Short name T1518
Test name
Test status
Simulation time 18395683871 ps
CPU time 75.27 seconds
Started Jun 05 05:44:56 PM PDT 24
Finished Jun 05 05:46:12 PM PDT 24
Peak memory 205792 kb
Host smart-6169c6f4-21f7-479a-90de-cd841cbc92e4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=896291456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.896291456
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.1367100702
Short name T5
Test name
Test status
Simulation time 30810586869 ps
CPU time 178.41 seconds
Started Jun 05 05:44:58 PM PDT 24
Finished Jun 05 05:47:57 PM PDT 24
Peak memory 205808 kb
Host smart-68dc1b44-5453-40af-a20b-4cd0af4a6b8e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1367100702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.1367100702
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.939381497
Short name T1129
Test name
Test status
Simulation time 10073673278 ps
CPU time 13.43 seconds
Started Jun 05 05:45:00 PM PDT 24
Finished Jun 05 05:45:14 PM PDT 24
Peak memory 205708 kb
Host smart-65f41f40-3268-405a-8e78-63e99d8d453f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93938
1497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.939381497
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.249467007
Short name T824
Test name
Test status
Simulation time 10042488365 ps
CPU time 14.46 seconds
Started Jun 05 05:44:58 PM PDT 24
Finished Jun 05 05:45:13 PM PDT 24
Peak memory 205732 kb
Host smart-2bda9ac2-d0c7-45ff-a650-62e471fb10ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24946
7007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.249467007
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.313722753
Short name T1729
Test name
Test status
Simulation time 10067550385 ps
CPU time 13.15 seconds
Started Jun 05 05:44:59 PM PDT 24
Finished Jun 05 05:45:13 PM PDT 24
Peak memory 205764 kb
Host smart-2bf04756-3c35-4697-a4be-d01d27f4b7fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31372
2753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.313722753
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.782564118
Short name T74
Test name
Test status
Simulation time 10054794570 ps
CPU time 14.59 seconds
Started Jun 05 05:44:59 PM PDT 24
Finished Jun 05 05:45:15 PM PDT 24
Peak memory 206004 kb
Host smart-1fa515ed-d25d-406b-a7de-d55a09971c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78256
4118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.782564118
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.2972392090
Short name T1035
Test name
Test status
Simulation time 10131067837 ps
CPU time 12.74 seconds
Started Jun 05 05:44:43 PM PDT 24
Finished Jun 05 05:44:56 PM PDT 24
Peak memory 205780 kb
Host smart-ebfbaddd-1094-4c5d-970c-79e6c6c0d81f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29723
92090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2972392090
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.105221694
Short name T1993
Test name
Test status
Simulation time 10100007893 ps
CPU time 13.72 seconds
Started Jun 05 05:44:57 PM PDT 24
Finished Jun 05 05:45:11 PM PDT 24
Peak memory 205748 kb
Host smart-6f2e12f4-7a89-4624-aec2-a93581810d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10522
1694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.105221694
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.790125153
Short name T705
Test name
Test status
Simulation time 10065476649 ps
CPU time 14.93 seconds
Started Jun 05 05:45:00 PM PDT 24
Finished Jun 05 05:45:16 PM PDT 24
Peak memory 205764 kb
Host smart-b36ae356-6dad-4e6d-bde5-f0f1a4e98cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79012
5153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.790125153
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.2054258757
Short name T701
Test name
Test status
Simulation time 16992089654 ps
CPU time 206.44 seconds
Started Jun 05 05:44:58 PM PDT 24
Finished Jun 05 05:48:25 PM PDT 24
Peak memory 205584 kb
Host smart-c9773a54-8773-4207-ba34-d6b54cec20e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20542
58757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.2054258757
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.2086596356
Short name T741
Test name
Test status
Simulation time 10192610071 ps
CPU time 16.55 seconds
Started Jun 05 05:45:05 PM PDT 24
Finished Jun 05 05:45:22 PM PDT 24
Peak memory 205692 kb
Host smart-e98e3ec4-72e2-4b2a-8dc8-a1c87313b1c6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2086596356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.2086596356
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.3590767438
Short name T756
Test name
Test status
Simulation time 10052200449 ps
CPU time 15.96 seconds
Started Jun 05 05:45:08 PM PDT 24
Finished Jun 05 05:45:25 PM PDT 24
Peak memory 205616 kb
Host smart-8d457dbb-e021-45a8-9c19-596d7e9246af
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3590767438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.3590767438
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.988849714
Short name T946
Test name
Test status
Simulation time 10105639932 ps
CPU time 14.01 seconds
Started Jun 05 05:45:07 PM PDT 24
Finished Jun 05 05:45:22 PM PDT 24
Peak memory 205764 kb
Host smart-b65e26bf-c808-422f-996d-d3c54ba3285f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98884
9714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.988849714
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.1740395237
Short name T1105
Test name
Test status
Simulation time 13601971009 ps
CPU time 17.31 seconds
Started Jun 05 05:45:00 PM PDT 24
Finished Jun 05 05:45:18 PM PDT 24
Peak memory 205784 kb
Host smart-96322464-8d7a-4c13-a5ac-f4fd0b701142
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1740395237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.1740395237
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.1649628193
Short name T1367
Test name
Test status
Simulation time 23226623461 ps
CPU time 23.61 seconds
Started Jun 05 05:44:59 PM PDT 24
Finished Jun 05 05:45:24 PM PDT 24
Peak memory 205808 kb
Host smart-f138c9b9-c7c3-4546-b8c5-2fa5875880f4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1649628193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.1649628193
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2953361390
Short name T338
Test name
Test status
Simulation time 10049076429 ps
CPU time 13.27 seconds
Started Jun 05 05:44:58 PM PDT 24
Finished Jun 05 05:45:12 PM PDT 24
Peak memory 205708 kb
Host smart-bb5cc4d5-c550-456f-ab0e-c6986f4d9998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29533
61390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2953361390
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.3166645441
Short name T781
Test name
Test status
Simulation time 10063234241 ps
CPU time 12.91 seconds
Started Jun 05 05:45:01 PM PDT 24
Finished Jun 05 05:45:15 PM PDT 24
Peak memory 205584 kb
Host smart-c9c63852-a2d3-4fe6-a9f3-4c937f3d87e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31666
45441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.3166645441
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.1391224122
Short name T1317
Test name
Test status
Simulation time 11112225268 ps
CPU time 15.15 seconds
Started Jun 05 05:45:00 PM PDT 24
Finished Jun 05 05:45:16 PM PDT 24
Peak memory 205728 kb
Host smart-be3847cd-3aa8-4d00-8d90-e3aece112f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13912
24122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.1391224122
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.1043605214
Short name T1715
Test name
Test status
Simulation time 10046363891 ps
CPU time 13.78 seconds
Started Jun 05 05:45:13 PM PDT 24
Finished Jun 05 05:45:28 PM PDT 24
Peak memory 205676 kb
Host smart-208e69dc-0b2d-4cee-9c12-5ef242b9fa9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10436
05214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.1043605214
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.2902877822
Short name T2007
Test name
Test status
Simulation time 10043452228 ps
CPU time 13.94 seconds
Started Jun 05 05:45:06 PM PDT 24
Finished Jun 05 05:45:21 PM PDT 24
Peak memory 205720 kb
Host smart-0c11a643-05d5-4c07-b5cb-6b3dd90a0921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29028
77822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2902877822
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.1834989518
Short name T1093
Test name
Test status
Simulation time 10812662452 ps
CPU time 14.53 seconds
Started Jun 05 05:45:05 PM PDT 24
Finished Jun 05 05:45:20 PM PDT 24
Peak memory 205672 kb
Host smart-6e0c370f-8970-49fa-9604-55864293a6c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18349
89518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.1834989518
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1659456426
Short name T1635
Test name
Test status
Simulation time 10128212584 ps
CPU time 14.06 seconds
Started Jun 05 05:45:07 PM PDT 24
Finished Jun 05 05:45:22 PM PDT 24
Peak memory 205616 kb
Host smart-d1117d84-da87-4f04-bfd6-182719bee0c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16594
56426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1659456426
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.2186091411
Short name T1565
Test name
Test status
Simulation time 10067453939 ps
CPU time 15.09 seconds
Started Jun 05 05:45:10 PM PDT 24
Finished Jun 05 05:45:26 PM PDT 24
Peak memory 205784 kb
Host smart-fb738b6d-edf0-44fc-8a2f-e87a6d5f20c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21860
91411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2186091411
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.319082290
Short name T1137
Test name
Test status
Simulation time 10042438745 ps
CPU time 13.99 seconds
Started Jun 05 05:45:07 PM PDT 24
Finished Jun 05 05:45:22 PM PDT 24
Peak memory 205692 kb
Host smart-4424eb5d-70f6-4165-8eaa-020a4a932f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31908
2290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.319082290
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3803489788
Short name T646
Test name
Test status
Simulation time 10126533365 ps
CPU time 12.97 seconds
Started Jun 05 05:45:09 PM PDT 24
Finished Jun 05 05:45:22 PM PDT 24
Peak memory 205792 kb
Host smart-9f1f08d8-f789-4c8e-bac7-300c18913ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38034
89788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3803489788
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.1965425077
Short name T1366
Test name
Test status
Simulation time 10169222847 ps
CPU time 13.72 seconds
Started Jun 05 05:45:06 PM PDT 24
Finished Jun 05 05:45:21 PM PDT 24
Peak memory 205688 kb
Host smart-3a645ffb-21e4-4a8a-aa8d-bd73b06e47a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19654
25077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.1965425077
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.2033949209
Short name T1897
Test name
Test status
Simulation time 13197112218 ps
CPU time 16.7 seconds
Started Jun 05 05:45:07 PM PDT 24
Finished Jun 05 05:45:25 PM PDT 24
Peak memory 205792 kb
Host smart-b8548388-0976-4c71-a361-f888210be120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20339
49209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.2033949209
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3944375365
Short name T451
Test name
Test status
Simulation time 10105029460 ps
CPU time 13.6 seconds
Started Jun 05 05:45:06 PM PDT 24
Finished Jun 05 05:45:20 PM PDT 24
Peak memory 205708 kb
Host smart-e848e048-4de5-4d4c-931e-3a80e52abb94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39443
75365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3944375365
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.2290715839
Short name T1008
Test name
Test status
Simulation time 17723070324 ps
CPU time 65.8 seconds
Started Jun 05 05:45:05 PM PDT 24
Finished Jun 05 05:46:12 PM PDT 24
Peak memory 205672 kb
Host smart-290457c2-726e-489f-9459-020c72a2d734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22907
15839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.2290715839
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2022394285
Short name T1199
Test name
Test status
Simulation time 10043899351 ps
CPU time 13.86 seconds
Started Jun 05 05:45:10 PM PDT 24
Finished Jun 05 05:45:24 PM PDT 24
Peak memory 205716 kb
Host smart-3525edc4-57a9-4cef-9887-123db5e1324d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20223
94285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2022394285
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3079060812
Short name T813
Test name
Test status
Simulation time 10115515085 ps
CPU time 13.26 seconds
Started Jun 05 05:45:07 PM PDT 24
Finished Jun 05 05:45:22 PM PDT 24
Peak memory 205700 kb
Host smart-f0cb9ebc-e74d-477d-bffd-eccaf8d903e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30790
60812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3079060812
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.4248368646
Short name T1693
Test name
Test status
Simulation time 10097547535 ps
CPU time 12.52 seconds
Started Jun 05 05:45:05 PM PDT 24
Finished Jun 05 05:45:19 PM PDT 24
Peak memory 205696 kb
Host smart-2f8e27dd-bd61-4b4d-8bac-3aebed6e9d50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42483
68646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.4248368646
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.606177464
Short name T1892
Test name
Test status
Simulation time 10067414671 ps
CPU time 13.86 seconds
Started Jun 05 05:45:12 PM PDT 24
Finished Jun 05 05:45:27 PM PDT 24
Peak memory 205776 kb
Host smart-a0b0c543-367d-47d3-9022-8c726830d192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60617
7464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.606177464
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.1135178138
Short name T1826
Test name
Test status
Simulation time 10104369064 ps
CPU time 13.94 seconds
Started Jun 05 05:45:08 PM PDT 24
Finished Jun 05 05:45:22 PM PDT 24
Peak memory 205960 kb
Host smart-19bd6cf1-b37c-4599-89f5-104f76ab9801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11351
78138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.1135178138
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.3042062521
Short name T1755
Test name
Test status
Simulation time 10079662616 ps
CPU time 12.28 seconds
Started Jun 05 05:45:06 PM PDT 24
Finished Jun 05 05:45:19 PM PDT 24
Peak memory 205720 kb
Host smart-fa3e307e-ba20-4e5c-9265-198f3babef17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30420
62521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.3042062521
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_eop_single_bit_handling.1662400003
Short name T677
Test name
Test status
Simulation time 10051394959 ps
CPU time 13.2 seconds
Started Jun 05 05:45:11 PM PDT 24
Finished Jun 05 05:45:25 PM PDT 24
Peak memory 205700 kb
Host smart-3e55d494-9567-4cc2-b4a5-97ac112a6a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16624
00003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_eop_single_bit_handling.1662400003
Directory /workspace/7.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.1977062536
Short name T536
Test name
Test status
Simulation time 10045492950 ps
CPU time 12.75 seconds
Started Jun 05 05:45:08 PM PDT 24
Finished Jun 05 05:45:22 PM PDT 24
Peak memory 205652 kb
Host smart-b88e7d31-ecd1-4117-912c-2bae4bcc7d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19770
62536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.1977062536
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.1109322969
Short name T799
Test name
Test status
Simulation time 10043391387 ps
CPU time 13.42 seconds
Started Jun 05 05:45:07 PM PDT 24
Finished Jun 05 05:45:21 PM PDT 24
Peak memory 205756 kb
Host smart-02a8a9ea-9025-4296-b95d-35d44972fbbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11093
22969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.1109322969
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.1203816746
Short name T1777
Test name
Test status
Simulation time 24379085677 ps
CPU time 44.24 seconds
Started Jun 05 05:45:12 PM PDT 24
Finished Jun 05 05:45:57 PM PDT 24
Peak memory 205700 kb
Host smart-0b2ea790-4f88-40e1-94f7-5b2507b2a70b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12038
16746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.1203816746
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.1775521362
Short name T607
Test name
Test status
Simulation time 10113461003 ps
CPU time 15.54 seconds
Started Jun 05 05:45:08 PM PDT 24
Finished Jun 05 05:45:24 PM PDT 24
Peak memory 205804 kb
Host smart-6eb84146-8836-429f-a5a7-8a9bf1819fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17755
21362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1775521362
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.2718331214
Short name T584
Test name
Test status
Simulation time 10212681698 ps
CPU time 13.41 seconds
Started Jun 05 05:45:06 PM PDT 24
Finished Jun 05 05:45:21 PM PDT 24
Peak memory 205800 kb
Host smart-67f448b5-0621-4e31-82e9-8031a2ef81a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27183
31214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.2718331214
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.359070165
Short name T1773
Test name
Test status
Simulation time 32199403056 ps
CPU time 227.86 seconds
Started Jun 05 05:45:07 PM PDT 24
Finished Jun 05 05:48:55 PM PDT 24
Peak memory 205732 kb
Host smart-f0f8e636-d6a7-4537-8e74-2f1539191d04
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=359070165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.359070165
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.2693826017
Short name T1874
Test name
Test status
Simulation time 20051856020 ps
CPU time 106.37 seconds
Started Jun 05 05:45:05 PM PDT 24
Finished Jun 05 05:46:53 PM PDT 24
Peak memory 205796 kb
Host smart-9fe9bba9-49f9-4efe-a6cb-982b378f73e3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2693826017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.2693826017
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.4052848263
Short name T1479
Test name
Test status
Simulation time 30892189146 ps
CPU time 176.16 seconds
Started Jun 05 05:45:12 PM PDT 24
Finished Jun 05 05:48:09 PM PDT 24
Peak memory 205804 kb
Host smart-59fa756a-bebb-4996-830a-9a3c436f5a84
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4052848263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.4052848263
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.2014175319
Short name T368
Test name
Test status
Simulation time 10111948298 ps
CPU time 15.32 seconds
Started Jun 05 05:45:07 PM PDT 24
Finished Jun 05 05:45:23 PM PDT 24
Peak memory 205652 kb
Host smart-fd4902d4-b12c-4793-9147-03df84f95b0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20141
75319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.2014175319
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.324189254
Short name T1535
Test name
Test status
Simulation time 10087847283 ps
CPU time 15.15 seconds
Started Jun 05 05:45:07 PM PDT 24
Finished Jun 05 05:45:23 PM PDT 24
Peak memory 205676 kb
Host smart-3ef96eb1-e97c-47e2-933a-b61b46e3cc0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32418
9254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.324189254
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.1281925365
Short name T65
Test name
Test status
Simulation time 10070864585 ps
CPU time 14.52 seconds
Started Jun 05 05:45:04 PM PDT 24
Finished Jun 05 05:45:19 PM PDT 24
Peak memory 205760 kb
Host smart-256bbf56-3a59-410e-a3bd-0cd60512078b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12819
25365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.1281925365
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2219151989
Short name T1369
Test name
Test status
Simulation time 10059033033 ps
CPU time 13.66 seconds
Started Jun 05 05:45:06 PM PDT 24
Finished Jun 05 05:45:21 PM PDT 24
Peak memory 205616 kb
Host smart-835c3f28-76c0-4d4c-a043-b36acb4e3fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22191
51989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2219151989
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2329000349
Short name T87
Test name
Test status
Simulation time 10080217283 ps
CPU time 13.29 seconds
Started Jun 05 05:44:59 PM PDT 24
Finished Jun 05 05:45:13 PM PDT 24
Peak memory 205696 kb
Host smart-bc745c1b-05e2-4dd4-96f1-c0bef475aa8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23290
00349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2329000349
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.1008603175
Short name T764
Test name
Test status
Simulation time 10100318507 ps
CPU time 13.11 seconds
Started Jun 05 05:45:07 PM PDT 24
Finished Jun 05 05:45:21 PM PDT 24
Peak memory 205716 kb
Host smart-2e8605c8-0862-4308-953f-59ba17b7cabe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10086
03175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1008603175
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.813371895
Short name T1909
Test name
Test status
Simulation time 10093842826 ps
CPU time 15.54 seconds
Started Jun 05 05:45:05 PM PDT 24
Finished Jun 05 05:45:22 PM PDT 24
Peak memory 205664 kb
Host smart-04b0f1f4-d98d-4147-a293-daf32f2298d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81337
1895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.813371895
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.3302071018
Short name T1193
Test name
Test status
Simulation time 24401354876 ps
CPU time 117.55 seconds
Started Jun 05 05:45:11 PM PDT 24
Finished Jun 05 05:47:09 PM PDT 24
Peak memory 205716 kb
Host smart-e261db32-45ec-4b78-be00-ef2d26cd11d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33020
71018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.3302071018
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.2321854233
Short name T1325
Test name
Test status
Simulation time 10187562342 ps
CPU time 14.6 seconds
Started Jun 05 05:45:17 PM PDT 24
Finished Jun 05 05:45:33 PM PDT 24
Peak memory 205632 kb
Host smart-f2201ca2-2959-4f86-ba1e-2358b17f2399
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2321854233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.2321854233
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.1507489125
Short name T1708
Test name
Test status
Simulation time 10055354803 ps
CPU time 15.12 seconds
Started Jun 05 05:45:13 PM PDT 24
Finished Jun 05 05:45:29 PM PDT 24
Peak memory 205620 kb
Host smart-2d5aef93-a897-4a57-8888-1e2320227194
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1507489125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.1507489125
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.4114703610
Short name T1662
Test name
Test status
Simulation time 10132259281 ps
CPU time 15.91 seconds
Started Jun 05 05:45:12 PM PDT 24
Finished Jun 05 05:45:29 PM PDT 24
Peak memory 205672 kb
Host smart-882673b9-6bf6-4fa4-bc2b-484ac27f5f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41147
03610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.4114703610
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.652405392
Short name T1653
Test name
Test status
Simulation time 13484329961 ps
CPU time 18.68 seconds
Started Jun 05 05:45:07 PM PDT 24
Finished Jun 05 05:45:26 PM PDT 24
Peak memory 205764 kb
Host smart-e2e44bb5-6872-415a-85ee-0ecbccb82c15
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=652405392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.652405392
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.2576248386
Short name T1607
Test name
Test status
Simulation time 23280716894 ps
CPU time 31.78 seconds
Started Jun 05 05:45:07 PM PDT 24
Finished Jun 05 05:45:40 PM PDT 24
Peak memory 205772 kb
Host smart-84750683-ab4b-458e-a716-ac30fcb4c883
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2576248386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.2576248386
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1492120792
Short name T1133
Test name
Test status
Simulation time 10071364984 ps
CPU time 13.4 seconds
Started Jun 05 05:45:07 PM PDT 24
Finished Jun 05 05:45:21 PM PDT 24
Peak memory 205648 kb
Host smart-68335594-3fcb-488a-babb-cdb13acb9270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14921
20792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1492120792
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.2187986601
Short name T1321
Test name
Test status
Simulation time 10780236246 ps
CPU time 14.15 seconds
Started Jun 05 05:45:10 PM PDT 24
Finished Jun 05 05:45:25 PM PDT 24
Peak memory 205724 kb
Host smart-ccc02b3b-0acf-411b-81f4-6d787e35edc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21879
86601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.2187986601
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.1373292008
Short name T577
Test name
Test status
Simulation time 10048229741 ps
CPU time 14.74 seconds
Started Jun 05 05:45:15 PM PDT 24
Finished Jun 05 05:45:30 PM PDT 24
Peak memory 205696 kb
Host smart-03c73489-249f-400c-a329-30a9123e6410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13732
92008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.1373292008
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.319272569
Short name T1605
Test name
Test status
Simulation time 10050222795 ps
CPU time 13.65 seconds
Started Jun 05 05:45:15 PM PDT 24
Finished Jun 05 05:45:30 PM PDT 24
Peak memory 205640 kb
Host smart-8c1100b1-636d-4a2f-97d4-e43676b8f19e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31927
2569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.319272569
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.49023985
Short name T1475
Test name
Test status
Simulation time 10646198776 ps
CPU time 15.72 seconds
Started Jun 05 05:45:13 PM PDT 24
Finished Jun 05 05:45:29 PM PDT 24
Peak memory 205688 kb
Host smart-ca3e9ce1-5296-4ec7-ae4f-df241df85c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49023
985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.49023985
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1479612108
Short name T2034
Test name
Test status
Simulation time 10139815092 ps
CPU time 15.31 seconds
Started Jun 05 05:45:12 PM PDT 24
Finished Jun 05 05:45:28 PM PDT 24
Peak memory 205668 kb
Host smart-74903dbf-be42-4a05-a9c5-3c579ab8d66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14796
12108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1479612108
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.3438078600
Short name T399
Test name
Test status
Simulation time 10090050592 ps
CPU time 13.97 seconds
Started Jun 05 05:45:12 PM PDT 24
Finished Jun 05 05:45:27 PM PDT 24
Peak memory 205728 kb
Host smart-dd7dc1f3-10a4-46a9-b4bd-c65e5bf2cbe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34380
78600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.3438078600
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.649643324
Short name T2033
Test name
Test status
Simulation time 10054159926 ps
CPU time 12.9 seconds
Started Jun 05 05:45:18 PM PDT 24
Finished Jun 05 05:45:32 PM PDT 24
Peak memory 205696 kb
Host smart-cd39e2b3-9a87-4e60-9af1-73f271c6255c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64964
3324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.649643324
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.1380278102
Short name T1067
Test name
Test status
Simulation time 10049147926 ps
CPU time 14.01 seconds
Started Jun 05 05:45:18 PM PDT 24
Finished Jun 05 05:45:34 PM PDT 24
Peak memory 205744 kb
Host smart-52324d5f-2698-4fdd-a224-1451dcf49749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13802
78102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.1380278102
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.2789705292
Short name T976
Test name
Test status
Simulation time 10114608960 ps
CPU time 13.83 seconds
Started Jun 05 05:45:16 PM PDT 24
Finished Jun 05 05:45:30 PM PDT 24
Peak memory 205644 kb
Host smart-15ef2251-ebf9-4301-9ec8-61d12fc61112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27897
05292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.2789705292
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.1169174010
Short name T1397
Test name
Test status
Simulation time 13167719156 ps
CPU time 17.06 seconds
Started Jun 05 05:45:11 PM PDT 24
Finished Jun 05 05:45:29 PM PDT 24
Peak memory 205744 kb
Host smart-12ee2dbc-2f49-4b3d-99f6-e72cc21f08e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11691
74010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.1169174010
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3341806138
Short name T407
Test name
Test status
Simulation time 10090280016 ps
CPU time 12.82 seconds
Started Jun 05 05:45:12 PM PDT 24
Finished Jun 05 05:45:26 PM PDT 24
Peak memory 205672 kb
Host smart-f6e3826f-b2f0-4e9b-9e45-8cdbcd4015dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33418
06138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3341806138
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.2941529627
Short name T2032
Test name
Test status
Simulation time 18736517392 ps
CPU time 254.92 seconds
Started Jun 05 05:45:12 PM PDT 24
Finished Jun 05 05:49:28 PM PDT 24
Peak memory 205688 kb
Host smart-49116429-e2ca-4533-93c0-b413699f2090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29415
29627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.2941529627
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.966758528
Short name T1956
Test name
Test status
Simulation time 10051919933 ps
CPU time 13.83 seconds
Started Jun 05 05:45:12 PM PDT 24
Finished Jun 05 05:45:26 PM PDT 24
Peak memory 205792 kb
Host smart-ecd1890f-1d9e-4414-af72-322ffc78ec0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96675
8528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.966758528
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3937501852
Short name T105
Test name
Test status
Simulation time 10105422836 ps
CPU time 12.42 seconds
Started Jun 05 05:45:18 PM PDT 24
Finished Jun 05 05:45:32 PM PDT 24
Peak memory 205664 kb
Host smart-d00c49d7-da9a-4ca9-b84f-5daa4ddb1e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39375
01852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3937501852
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.985271799
Short name T1360
Test name
Test status
Simulation time 10083594649 ps
CPU time 15.93 seconds
Started Jun 05 05:45:15 PM PDT 24
Finished Jun 05 05:45:31 PM PDT 24
Peak memory 205724 kb
Host smart-f2acc717-6464-46b8-a98f-4d8f9368a920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98527
1799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.985271799
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.2694899074
Short name T362
Test name
Test status
Simulation time 10068849703 ps
CPU time 13.34 seconds
Started Jun 05 05:45:11 PM PDT 24
Finished Jun 05 05:45:25 PM PDT 24
Peak memory 205584 kb
Host smart-9e80b484-bf1b-42b5-90f4-f7b88c941649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26948
99074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.2694899074
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.2628800902
Short name T1441
Test name
Test status
Simulation time 10070759160 ps
CPU time 13.7 seconds
Started Jun 05 05:45:11 PM PDT 24
Finished Jun 05 05:45:25 PM PDT 24
Peak memory 205732 kb
Host smart-4b500e7b-3a2a-4b0b-96f1-6f98d34044d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26288
00902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.2628800902
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.2696284026
Short name T1868
Test name
Test status
Simulation time 10078543413 ps
CPU time 13.47 seconds
Started Jun 05 05:45:13 PM PDT 24
Finished Jun 05 05:45:27 PM PDT 24
Peak memory 205684 kb
Host smart-025f8294-1135-4495-bb0e-ef848a285fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26962
84026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.2696284026
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_eop_single_bit_handling.2302054173
Short name T670
Test name
Test status
Simulation time 10082215435 ps
CPU time 15.07 seconds
Started Jun 05 05:45:18 PM PDT 24
Finished Jun 05 05:45:34 PM PDT 24
Peak memory 205688 kb
Host smart-3f6be6cd-2a12-4236-baa8-546499a21129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23020
54173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_eop_single_bit_handling.2302054173
Directory /workspace/8.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.3787569582
Short name T64
Test name
Test status
Simulation time 10044599567 ps
CPU time 12.97 seconds
Started Jun 05 05:45:13 PM PDT 24
Finished Jun 05 05:45:27 PM PDT 24
Peak memory 205764 kb
Host smart-485d43e2-c0bb-4013-8308-050f089f7f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37875
69582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.3787569582
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2925002499
Short name T1946
Test name
Test status
Simulation time 10040000636 ps
CPU time 14.89 seconds
Started Jun 05 05:45:14 PM PDT 24
Finished Jun 05 05:45:30 PM PDT 24
Peak memory 205772 kb
Host smart-b385f65b-96a9-45b5-a9cc-65da657a5c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29250
02499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2925002499
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.56752229
Short name T1573
Test name
Test status
Simulation time 24303454488 ps
CPU time 45.08 seconds
Started Jun 05 05:45:13 PM PDT 24
Finished Jun 05 05:45:59 PM PDT 24
Peak memory 205676 kb
Host smart-89276c4d-a9d0-421d-8c46-5bf34cfce050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56752
229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.56752229
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.564856524
Short name T947
Test name
Test status
Simulation time 10095768272 ps
CPU time 14.15 seconds
Started Jun 05 05:45:13 PM PDT 24
Finished Jun 05 05:45:28 PM PDT 24
Peak memory 205680 kb
Host smart-e341a1fb-cf39-469b-9b3b-6207e385da8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56485
6524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.564856524
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.1949391718
Short name T1672
Test name
Test status
Simulation time 10101853445 ps
CPU time 13.5 seconds
Started Jun 05 05:45:22 PM PDT 24
Finished Jun 05 05:45:36 PM PDT 24
Peak memory 205620 kb
Host smart-a814b7a9-ac77-44b0-a990-e34bf3f269fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19493
91718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1949391718
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.263271363
Short name T167
Test name
Test status
Simulation time 30606146976 ps
CPU time 133.21 seconds
Started Jun 05 05:45:17 PM PDT 24
Finished Jun 05 05:47:31 PM PDT 24
Peak memory 205716 kb
Host smart-5e125021-531f-4254-a072-639e67a0398b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=263271363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.263271363
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.1346684828
Short name T1553
Test name
Test status
Simulation time 20950645600 ps
CPU time 95.34 seconds
Started Jun 05 05:45:12 PM PDT 24
Finished Jun 05 05:46:49 PM PDT 24
Peak memory 205740 kb
Host smart-e319f4a1-8fc3-4749-8fa9-7f4701f43ab7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1346684828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.1346684828
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.4025510193
Short name T690
Test name
Test status
Simulation time 42091392434 ps
CPU time 281.95 seconds
Started Jun 05 05:45:12 PM PDT 24
Finished Jun 05 05:49:55 PM PDT 24
Peak memory 205792 kb
Host smart-3c6966f2-0190-4758-8a21-8d90d6540d36
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4025510193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.4025510193
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.2150544111
Short name T405
Test name
Test status
Simulation time 10053857067 ps
CPU time 13.58 seconds
Started Jun 05 05:45:12 PM PDT 24
Finished Jun 05 05:45:26 PM PDT 24
Peak memory 205704 kb
Host smart-c877a80c-3568-4aec-8cd2-8e0189a2a4b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21505
44111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.2150544111
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.2777990876
Short name T1071
Test name
Test status
Simulation time 10048481093 ps
CPU time 15.18 seconds
Started Jun 05 05:45:11 PM PDT 24
Finished Jun 05 05:45:27 PM PDT 24
Peak memory 205656 kb
Host smart-82e7fb9e-7827-45f2-a76e-421aa4c7a79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27779
90876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.2777990876
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.2894779844
Short name T126
Test name
Test status
Simulation time 10054389085 ps
CPU time 14.11 seconds
Started Jun 05 05:45:18 PM PDT 24
Finished Jun 05 05:45:33 PM PDT 24
Peak memory 205744 kb
Host smart-7bb64fcc-a06d-4e7a-9ba5-1df417efd9ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28947
79844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.2894779844
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.1886427207
Short name T1165
Test name
Test status
Simulation time 10059584331 ps
CPU time 13.28 seconds
Started Jun 05 05:45:12 PM PDT 24
Finished Jun 05 05:45:26 PM PDT 24
Peak memory 205648 kb
Host smart-371fe721-fcbf-42c2-9c16-973dbd149290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18864
27207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.1886427207
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1043744395
Short name T1172
Test name
Test status
Simulation time 10094575859 ps
CPU time 13.24 seconds
Started Jun 05 05:45:07 PM PDT 24
Finished Jun 05 05:45:21 PM PDT 24
Peak memory 205724 kb
Host smart-ff62f537-218f-4b0e-89d5-b7e5b03092fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10437
44395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1043744395
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.3916329471
Short name T1469
Test name
Test status
Simulation time 10104766953 ps
CPU time 12.92 seconds
Started Jun 05 05:45:14 PM PDT 24
Finished Jun 05 05:45:28 PM PDT 24
Peak memory 205668 kb
Host smart-d5b85b3f-c926-453c-85d9-6dee2c06c3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39163
29471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.3916329471
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2004569408
Short name T1886
Test name
Test status
Simulation time 10104213135 ps
CPU time 16.09 seconds
Started Jun 05 05:45:11 PM PDT 24
Finished Jun 05 05:45:28 PM PDT 24
Peak memory 205732 kb
Host smart-50d29c04-4d84-4836-b087-72b1b3f8152a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20045
69408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2004569408
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.3314808436
Short name T2001
Test name
Test status
Simulation time 14950567765 ps
CPU time 60.37 seconds
Started Jun 05 05:45:13 PM PDT 24
Finished Jun 05 05:46:14 PM PDT 24
Peak memory 205744 kb
Host smart-e1a6633d-6665-40f9-876a-7aa9c108c26a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33148
08436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.3314808436
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.2890607394
Short name T1445
Test name
Test status
Simulation time 10160283104 ps
CPU time 12.9 seconds
Started Jun 05 05:45:20 PM PDT 24
Finished Jun 05 05:45:34 PM PDT 24
Peak memory 205728 kb
Host smart-39beabe8-d905-43af-ba94-c5008957cdf2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2890607394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.2890607394
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.291684209
Short name T499
Test name
Test status
Simulation time 10063408489 ps
CPU time 16.51 seconds
Started Jun 05 05:45:25 PM PDT 24
Finished Jun 05 05:45:42 PM PDT 24
Peak memory 205768 kb
Host smart-61a618c7-a52f-42fb-bdb5-64fa868480ae
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=291684209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.291684209
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.3732246631
Short name T1982
Test name
Test status
Simulation time 10144173173 ps
CPU time 12.9 seconds
Started Jun 05 05:45:23 PM PDT 24
Finished Jun 05 05:45:36 PM PDT 24
Peak memory 205748 kb
Host smart-699d8043-00fa-463b-868f-646e080f1928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37322
46631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.3732246631
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.1857302091
Short name T207
Test name
Test status
Simulation time 13800626884 ps
CPU time 16.52 seconds
Started Jun 05 05:45:13 PM PDT 24
Finished Jun 05 05:45:30 PM PDT 24
Peak memory 205768 kb
Host smart-a6849a0a-072e-46f4-8da3-7926d669e02f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1857302091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.1857302091
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.2167237109
Short name T1739
Test name
Test status
Simulation time 23250414628 ps
CPU time 24.66 seconds
Started Jun 05 05:45:20 PM PDT 24
Finished Jun 05 05:45:46 PM PDT 24
Peak memory 205648 kb
Host smart-660080a9-7fdc-4cdc-9a99-a5ea2ddf4b55
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2167237109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.2167237109
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.1189940815
Short name T1620
Test name
Test status
Simulation time 10039746862 ps
CPU time 12.91 seconds
Started Jun 05 05:45:23 PM PDT 24
Finished Jun 05 05:45:36 PM PDT 24
Peak memory 205588 kb
Host smart-0d979b51-a7cb-402c-b7a5-bb38b0315627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11899
40815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1189940815
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.893081594
Short name T59
Test name
Test status
Simulation time 10100293547 ps
CPU time 14.05 seconds
Started Jun 05 05:45:18 PM PDT 24
Finished Jun 05 05:45:34 PM PDT 24
Peak memory 205744 kb
Host smart-90dfa7bc-3cd4-43aa-acda-eac3f911f0ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89308
1594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.893081594
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.3096911651
Short name T1449
Test name
Test status
Simulation time 10902091608 ps
CPU time 16.43 seconds
Started Jun 05 05:45:12 PM PDT 24
Finished Jun 05 05:45:30 PM PDT 24
Peak memory 205736 kb
Host smart-1f1b378b-c52f-4022-85a6-87ce345c1e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30969
11651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.3096911651
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.1995102925
Short name T1293
Test name
Test status
Simulation time 10103151408 ps
CPU time 13.54 seconds
Started Jun 05 05:45:24 PM PDT 24
Finished Jun 05 05:45:38 PM PDT 24
Peak memory 205540 kb
Host smart-480749fc-6880-4342-9128-aeeb141c1186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19951
02925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1995102925
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.3345622470
Short name T331
Test name
Test status
Simulation time 10062545669 ps
CPU time 14.43 seconds
Started Jun 05 05:45:21 PM PDT 24
Finished Jun 05 05:45:36 PM PDT 24
Peak memory 205652 kb
Host smart-8ceb9c08-710c-4951-a8ee-71deb9df87f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33456
22470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.3345622470
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.1869357939
Short name T777
Test name
Test status
Simulation time 10904529186 ps
CPU time 15.64 seconds
Started Jun 05 05:45:11 PM PDT 24
Finished Jun 05 05:45:28 PM PDT 24
Peak memory 205604 kb
Host smart-b1a99c50-dc0b-49e7-8636-01c368942a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18693
57939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.1869357939
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1757861221
Short name T1942
Test name
Test status
Simulation time 10152776424 ps
CPU time 15.07 seconds
Started Jun 05 05:45:22 PM PDT 24
Finished Jun 05 05:45:38 PM PDT 24
Peak memory 205752 kb
Host smart-1fe67e57-116f-4c97-8fea-2584a0ebecdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17578
61221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1757861221
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.2497590157
Short name T1504
Test name
Test status
Simulation time 10172734417 ps
CPU time 14.45 seconds
Started Jun 05 05:45:19 PM PDT 24
Finished Jun 05 05:45:34 PM PDT 24
Peak memory 205616 kb
Host smart-18e3bb58-a4e7-4c70-8e39-894626eaa0c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24975
90157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.2497590157
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.2420087599
Short name T1861
Test name
Test status
Simulation time 10090730539 ps
CPU time 12.54 seconds
Started Jun 05 05:45:19 PM PDT 24
Finished Jun 05 05:45:32 PM PDT 24
Peak memory 205760 kb
Host smart-6fe9821a-6411-4c84-b708-6203fc3a2eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24200
87599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.2420087599
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.1206202149
Short name T687
Test name
Test status
Simulation time 10156697788 ps
CPU time 13.78 seconds
Started Jun 05 05:45:20 PM PDT 24
Finished Jun 05 05:45:35 PM PDT 24
Peak memory 205668 kb
Host smart-5fa3eddf-345f-43f4-b0e8-5e0aef81751a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12062
02149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.1206202149
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.1013717133
Short name T1111
Test name
Test status
Simulation time 10077826582 ps
CPU time 13.37 seconds
Started Jun 05 05:45:22 PM PDT 24
Finished Jun 05 05:45:37 PM PDT 24
Peak memory 205692 kb
Host smart-a4615886-9771-44a2-b17a-387a2d077917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10137
17133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.1013717133
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.1119125087
Short name T345
Test name
Test status
Simulation time 13188803864 ps
CPU time 16.9 seconds
Started Jun 05 05:45:21 PM PDT 24
Finished Jun 05 05:45:39 PM PDT 24
Peak memory 205640 kb
Host smart-79af6c40-bc4f-4731-92b2-5eb30d506e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11191
25087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.1119125087
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3661492513
Short name T1271
Test name
Test status
Simulation time 10098937753 ps
CPU time 13.19 seconds
Started Jun 05 05:45:20 PM PDT 24
Finished Jun 05 05:45:34 PM PDT 24
Peak memory 205940 kb
Host smart-75acc17b-e347-42ef-8dd5-aab45b700c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36614
92513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3661492513
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.4211799566
Short name T228
Test name
Test status
Simulation time 17079738068 ps
CPU time 78.52 seconds
Started Jun 05 05:45:24 PM PDT 24
Finished Jun 05 05:46:43 PM PDT 24
Peak memory 205536 kb
Host smart-95d33b47-7b08-4cc5-b8cc-077cf7c7b0c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42117
99566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.4211799566
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3981780916
Short name T1402
Test name
Test status
Simulation time 10044647807 ps
CPU time 15.21 seconds
Started Jun 05 05:45:21 PM PDT 24
Finished Jun 05 05:45:37 PM PDT 24
Peak memory 205764 kb
Host smart-94bd9f84-a5e0-47df-afb3-7b6683c34353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39817
80916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3981780916
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.4289004852
Short name T100
Test name
Test status
Simulation time 10073225084 ps
CPU time 13.01 seconds
Started Jun 05 05:45:20 PM PDT 24
Finished Jun 05 05:45:33 PM PDT 24
Peak memory 205712 kb
Host smart-70357564-71f5-4625-8d08-462ba2fad0e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42890
04852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.4289004852
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.432943787
Short name T1604
Test name
Test status
Simulation time 10147490069 ps
CPU time 16.36 seconds
Started Jun 05 05:45:23 PM PDT 24
Finished Jun 05 05:45:40 PM PDT 24
Peak memory 205872 kb
Host smart-4049308f-0af7-4795-9947-023ec9c19065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43294
3787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.432943787
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.1600204028
Short name T1788
Test name
Test status
Simulation time 10124650083 ps
CPU time 13.82 seconds
Started Jun 05 05:45:21 PM PDT 24
Finished Jun 05 05:45:36 PM PDT 24
Peak memory 205744 kb
Host smart-119830bd-bc8c-455a-9af4-3b12a10646b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16002
04028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.1600204028
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.4019860702
Short name T880
Test name
Test status
Simulation time 10098789359 ps
CPU time 14.63 seconds
Started Jun 05 05:45:24 PM PDT 24
Finished Jun 05 05:45:40 PM PDT 24
Peak memory 205616 kb
Host smart-e0fff54c-2bf9-4d98-a476-09359d951d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40198
60702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.4019860702
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.2576932534
Short name T1741
Test name
Test status
Simulation time 10053239075 ps
CPU time 14.42 seconds
Started Jun 05 05:45:24 PM PDT 24
Finished Jun 05 05:45:39 PM PDT 24
Peak memory 205952 kb
Host smart-9695bb29-2ada-4576-9702-8a158c9be89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25769
32534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.2576932534
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_eop_single_bit_handling.2604578890
Short name T81
Test name
Test status
Simulation time 10069480369 ps
CPU time 12.81 seconds
Started Jun 05 05:45:25 PM PDT 24
Finished Jun 05 05:45:38 PM PDT 24
Peak memory 205700 kb
Host smart-c82c20e3-79e4-4dfa-ba3d-254f37e364f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26045
78890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_eop_single_bit_handling.2604578890
Directory /workspace/9.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.328408471
Short name T594
Test name
Test status
Simulation time 10048854141 ps
CPU time 13.6 seconds
Started Jun 05 05:45:20 PM PDT 24
Finished Jun 05 05:45:35 PM PDT 24
Peak memory 205736 kb
Host smart-ada9fce7-ea1e-409d-a06d-001766f8f474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32840
8471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.328408471
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2189129466
Short name T548
Test name
Test status
Simulation time 10057195629 ps
CPU time 13.06 seconds
Started Jun 05 05:45:30 PM PDT 24
Finished Jun 05 05:45:43 PM PDT 24
Peak memory 205676 kb
Host smart-185e7b9a-b7db-423a-8806-aab3fc6891ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21891
29466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2189129466
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.2869482332
Short name T948
Test name
Test status
Simulation time 18573627161 ps
CPU time 34.73 seconds
Started Jun 05 05:45:23 PM PDT 24
Finished Jun 05 05:45:58 PM PDT 24
Peak memory 205876 kb
Host smart-05b4d5c2-2b1a-4cff-bcb2-490f37c5654d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28694
82332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.2869482332
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.85585854
Short name T1134
Test name
Test status
Simulation time 10079148326 ps
CPU time 13.92 seconds
Started Jun 05 05:45:19 PM PDT 24
Finished Jun 05 05:45:34 PM PDT 24
Peak memory 205712 kb
Host smart-78427538-540d-4128-8751-1d26114f5223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85585
854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.85585854
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.1805651379
Short name T573
Test name
Test status
Simulation time 10167014885 ps
CPU time 13.06 seconds
Started Jun 05 05:45:21 PM PDT 24
Finished Jun 05 05:45:35 PM PDT 24
Peak memory 205748 kb
Host smart-02cd32b1-a48b-437b-bb8d-c46f12f8cd74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18056
51379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1805651379
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.2363566566
Short name T162
Test name
Test status
Simulation time 32216923152 ps
CPU time 224.77 seconds
Started Jun 05 05:45:20 PM PDT 24
Finished Jun 05 05:49:06 PM PDT 24
Peak memory 205780 kb
Host smart-0774b577-7a42-4ebe-a7c5-0d6b07f8c148
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2363566566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.2363566566
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.1866169897
Short name T2010
Test name
Test status
Simulation time 29643517273 ps
CPU time 124.72 seconds
Started Jun 05 05:45:22 PM PDT 24
Finished Jun 05 05:47:28 PM PDT 24
Peak memory 205768 kb
Host smart-f568798b-c9e4-4b5b-8922-cea67591bd55
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1866169897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.1866169897
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.2165709549
Short name T541
Test name
Test status
Simulation time 23259270865 ps
CPU time 288.06 seconds
Started Jun 05 05:45:18 PM PDT 24
Finished Jun 05 05:50:08 PM PDT 24
Peak memory 205820 kb
Host smart-5c829f0f-0c41-43b5-b167-39b3db536f15
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2165709549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.2165709549
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.3076756582
Short name T1439
Test name
Test status
Simulation time 10071570915 ps
CPU time 14.26 seconds
Started Jun 05 05:45:24 PM PDT 24
Finished Jun 05 05:45:39 PM PDT 24
Peak memory 205540 kb
Host smart-c1e086a8-869d-4f79-ab07-3dfeaa660775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30767
56582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.3076756582
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.857135914
Short name T1249
Test name
Test status
Simulation time 10051321440 ps
CPU time 15.72 seconds
Started Jun 05 05:45:21 PM PDT 24
Finished Jun 05 05:45:38 PM PDT 24
Peak memory 205696 kb
Host smart-8b2e7f52-3cf7-425b-95fe-0e80d9a663ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85713
5914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.857135914
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.1680190097
Short name T1997
Test name
Test status
Simulation time 10069345222 ps
CPU time 13.32 seconds
Started Jun 05 05:45:20 PM PDT 24
Finished Jun 05 05:45:35 PM PDT 24
Peak memory 205724 kb
Host smart-831f3e81-1784-4d66-816e-0788c684bccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16801
90097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.1680190097
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.3921869569
Short name T833
Test name
Test status
Simulation time 10120262724 ps
CPU time 15.39 seconds
Started Jun 05 05:45:21 PM PDT 24
Finished Jun 05 05:45:37 PM PDT 24
Peak memory 205752 kb
Host smart-6fa76e5c-8ed0-4a88-9b2e-4be57be9ff7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39218
69569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.3921869569
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2424110796
Short name T838
Test name
Test status
Simulation time 10093870381 ps
CPU time 16.42 seconds
Started Jun 05 05:45:13 PM PDT 24
Finished Jun 05 05:45:30 PM PDT 24
Peak memory 205696 kb
Host smart-489d0239-8b76-4ddd-bbc4-8226f9c310d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24241
10796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2424110796
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.4079529303
Short name T1505
Test name
Test status
Simulation time 10081527781 ps
CPU time 14.78 seconds
Started Jun 05 05:45:21 PM PDT 24
Finished Jun 05 05:45:37 PM PDT 24
Peak memory 205768 kb
Host smart-58972196-a09c-43b2-9360-b1344f97fed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40795
29303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.4079529303
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.2002721379
Short name T1587
Test name
Test status
Simulation time 10115587216 ps
CPU time 12.69 seconds
Started Jun 05 05:45:22 PM PDT 24
Finished Jun 05 05:45:36 PM PDT 24
Peak memory 205728 kb
Host smart-e84650ee-de65-4bdc-986a-755e43b69c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20027
21379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.2002721379
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.2963283870
Short name T351
Test name
Test status
Simulation time 25166670145 ps
CPU time 155.47 seconds
Started Jun 05 05:45:24 PM PDT 24
Finished Jun 05 05:48:00 PM PDT 24
Peak memory 205652 kb
Host smart-1c0b9bca-8154-4fad-816d-ab6af05947db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29632
83870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.2963283870
Directory /workspace/9.usbdev_streaming_out/latest
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