Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	118660	1		T1	2		T2	2		T3	2
all_values[1]	118660	1		T1	2		T2	2		T3	2
all_values[2]	118660	1		T1	2		T2	2		T3	2
all_values[3]	118660	1		T1	2		T2	2		T3	2
all_values[4]	118660	1		T1	2		T2	2		T3	2
all_values[5]	118660	1		T1	2		T2	2		T3	2
all_values[6]	118660	1		T1	2		T2	2		T3	2
all_values[7]	118660	1		T1	2		T2	2		T3	2
all_values[8]	118660	1		T1	2		T2	2		T3	2
all_values[9]	118660	1		T1	2		T2	2		T3	2
all_values[10]	118660	1		T1	2		T2	2		T3	2
all_values[11]	118660	1		T1	2		T2	2		T3	2
all_values[12]	118660	1		T1	2		T2	2		T3	2
all_values[13]	118660	1		T1	2		T2	2		T3	2
all_values[14]	118660	1		T1	2		T2	2		T3	2
all_values[15]	118660	1		T1	2		T2	2		T3	2
all_values[16]	118660	1		T1	2		T2	2		T3	2
all_values[17]	118660	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2129803	1		T1	34		T2	36		T3	36
auto[1]	6077	1		T1	2		T35	20		T39	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2130866	1		T1	36		T2	36		T3	36
auto[1]	5014	1		T104	125		T105	135		T106	128

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	117645	1		T1	2		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	157	1		T104	3		T105	3		T106	4
all_values[0]	auto[1]	auto[0]	719	1		T52	3		T53	4		T54	3
all_values[0]	auto[1]	auto[1]	139	1		T105	5		T106	4		T198	3
all_values[1]	auto[0]	auto[0]	116109	1		T1	2		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	144	1		T104	7		T105	6		T106	4
all_values[1]	auto[1]	auto[0]	2262	1		T35	20		T39	3		T51	4
all_values[1]	auto[1]	auto[1]	145	1		T104	1		T105	2		T106	4
all_values[2]	auto[0]	auto[0]	118263	1		T2	2		T3	2		T4	2
all_values[2]	auto[0]	auto[1]	131	1		T104	4		T105	2		T198	5
all_values[2]	auto[1]	auto[0]	115	1		T1	2		T47	2		T23	2
all_values[2]	auto[1]	auto[1]	151	1		T104	3		T105	6		T106	7
all_values[3]	auto[0]	auto[0]	118363	1		T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	131	1		T105	2		T106	6		T198	6
all_values[3]	auto[1]	auto[0]	26	1		T104	3		T277	2		T281	1
all_values[3]	auto[1]	auto[1]	140	1		T105	5		T106	2		T198	2
all_values[4]	auto[0]	auto[0]	118354	1		T1	2		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	151	1		T104	6		T105	2		T106	5
all_values[4]	auto[1]	auto[0]	31	1		T104	1		T106	1		T277	1
all_values[4]	auto[1]	auto[1]	124	1		T104	1		T105	6		T198	3
all_values[5]	auto[0]	auto[0]	118352	1		T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	151	1		T104	2		T105	7		T106	4
all_values[5]	auto[1]	auto[0]	16	1		T279	1		T282	1		T283	1
all_values[5]	auto[1]	auto[1]	141	1		T104	6		T105	1		T106	4
all_values[6]	auto[0]	auto[0]	118361	1		T1	2		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	143	1		T104	3		T105	2		T198	4
all_values[6]	auto[1]	auto[0]	26	1		T105	1		T198	1		T277	3
all_values[6]	auto[1]	auto[1]	130	1		T104	5		T105	5		T106	8
all_values[7]	auto[0]	auto[0]	118353	1		T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	132	1		T104	4		T105	4		T106	2
all_values[7]	auto[1]	auto[0]	21	1		T106	2		T278	4		T279	1
all_values[7]	auto[1]	auto[1]	154	1		T104	4		T105	4		T106	4
all_values[8]	auto[0]	auto[0]	118359	1		T1	2		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	149	1		T104	2		T105	7		T106	4
all_values[8]	auto[1]	auto[0]	26	1		T106	2		T198	1		T277	1
all_values[8]	auto[1]	auto[1]	126	1		T104	5		T105	1		T106	1
all_values[9]	auto[0]	auto[0]	118357	1		T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	137	1		T104	2		T105	4		T106	5
all_values[9]	auto[1]	auto[0]	29	1		T106	1		T198	1		T277	4
all_values[9]	auto[1]	auto[1]	137	1		T104	6		T105	4		T106	1
all_values[10]	auto[0]	auto[0]	118374	1		T1	2		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	137	1		T104	5		T105	6		T106	5
all_values[10]	auto[1]	auto[0]	28	1		T277	1		T284	1		T279	1
all_values[10]	auto[1]	auto[1]	121	1		T104	2		T105	1		T106	3
all_values[11]	auto[0]	auto[0]	118259	1		T1	2		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	136	1		T104	4		T105	6		T106	6
all_values[11]	auto[1]	auto[0]	128	1		T63	2		T64	2		T65	2
all_values[11]	auto[1]	auto[1]	137	1		T104	4		T105	2		T106	2
all_values[12]	auto[0]	auto[0]	118353	1		T1	2		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	134	1		T104	4		T105	2		T106	4
all_values[12]	auto[1]	auto[0]	20	1		T277	1		T284	1		T279	1
all_values[12]	auto[1]	auto[1]	153	1		T104	4		T105	6		T106	3
all_values[13]	auto[0]	auto[0]	118369	1		T1	2		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	138	1		T104	5		T105	5		T106	2
all_values[13]	auto[1]	auto[0]	32	1		T106	1		T278	2		T285	1
all_values[13]	auto[1]	auto[1]	121	1		T104	2		T105	2		T106	4
all_values[14]	auto[0]	auto[0]	118348	1		T1	2		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	147	1		T104	3		T105	3		T106	6
all_values[14]	auto[1]	auto[0]	24	1		T105	2		T198	1		T277	1
all_values[14]	auto[1]	auto[1]	141	1		T104	5		T105	3		T106	2
all_values[15]	auto[0]	auto[0]	118367	1		T1	2		T2	2		T3	2
all_values[15]	auto[0]	auto[1]	129	1		T104	2		T105	1		T106	4
all_values[15]	auto[1]	auto[0]	25	1		T105	1		T281	1		T280	2
all_values[15]	auto[1]	auto[1]	139	1		T104	6		T105	6		T106	4
all_values[16]	auto[0]	auto[0]	118349	1		T1	2		T2	2		T3	2
all_values[16]	auto[0]	auto[1]	123	1		T104	3		T105	2		T106	3
all_values[16]	auto[1]	auto[0]	29	1		T106	1		T277	2		T282	1
all_values[16]	auto[1]	auto[1]	159	1		T104	4		T105	6		T106	3
all_values[17]	auto[0]	auto[0]	118355	1		T1	2		T2	2		T3	2
all_values[17]	auto[0]	auto[1]	143	1		T104	5		T105	4		T106	5
all_values[17]	auto[1]	auto[0]	19	1		T105	2		T277	2		T280	1
all_values[17]	auto[1]	auto[1]	143	1		T104	3		T105	2		T106	3