Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	118660	1		T1	2		T2	2		T3	2
all_pins[1]	118660	1		T1	2		T2	2		T3	2
all_pins[2]	118660	1		T1	2		T2	2		T3	2
all_pins[3]	118660	1		T1	2		T2	2		T3	2
all_pins[4]	118660	1		T1	2		T2	2		T3	2
all_pins[5]	118660	1		T1	2		T2	2		T3	2
all_pins[6]	118660	1		T1	2		T2	2		T3	2
all_pins[7]	118660	1		T1	2		T2	2		T3	2
all_pins[8]	118660	1		T1	2		T2	2		T3	2
all_pins[9]	118660	1		T1	2		T2	2		T3	2
all_pins[10]	118660	1		T1	2		T2	2		T3	2
all_pins[11]	118660	1		T1	2		T2	2		T3	2
all_pins[12]	118660	1		T1	2		T2	2		T3	2
all_pins[13]	118660	1		T1	2		T2	2		T3	2
all_pins[14]	118660	1		T1	2		T2	2		T3	2
all_pins[15]	118660	1		T1	2		T2	2		T3	2
all_pins[16]	118660	1		T1	2		T2	2		T3	2
all_pins[17]	118660	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2133367	1		T1	35		T2	36		T3	36
values[0x1]	2513	1		T1	1		T35	18		T39	1
transitions[0x0=>0x1]	2258	1		T1	1		T35	18		T39	1
transitions[0x1=>0x0]	2266	1		T1	1		T35	18		T39	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	118492	1		T1	2		T2	2		T3	2
all_pins[0]	values[0x1]	168	1		T53	1		T17	1		T24	1
all_pins[0]	transitions[0x0=>0x1]	155	1		T53	1		T17	1		T24	1
all_pins[0]	transitions[0x1=>0x0]	1255	1		T35	18		T39	1		T51	2
all_pins[1]	values[0x0]	117392	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	1268	1		T35	18		T39	1		T51	2
all_pins[1]	transitions[0x0=>0x1]	1253	1		T35	18		T39	1		T51	2
all_pins[1]	transitions[0x1=>0x0]	107	1		T1	1		T47	1		T23	1
all_pins[2]	values[0x0]	118538	1		T1	1		T2	2		T3	2
all_pins[2]	values[0x1]	122	1		T1	1		T47	1		T23	1
all_pins[2]	transitions[0x0=>0x1]	109	1		T1	1		T47	1		T23	1
all_pins[2]	transitions[0x1=>0x0]	51	1		T105	2		T198	1		T277	3
all_pins[3]	values[0x0]	118596	1		T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	64	1		T105	2		T106	1		T198	2
all_pins[3]	transitions[0x0=>0x1]	48	1		T105	2		T106	1		T277	2
all_pins[3]	transitions[0x1=>0x0]	34	1		T105	1		T277	1		T278	2
all_pins[4]	values[0x0]	118610	1		T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	50	1		T105	1		T198	2		T277	2
all_pins[4]	transitions[0x0=>0x1]	44	1		T105	1		T198	2		T277	2
all_pins[4]	transitions[0x1=>0x0]	51	1		T104	2		T106	2		T198	1
all_pins[5]	values[0x0]	118603	1		T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	57	1		T104	2		T106	2		T198	1
all_pins[5]	transitions[0x0=>0x1]	42	1		T104	2		T198	1		T277	1
all_pins[5]	transitions[0x1=>0x0]	50	1		T104	3		T105	2		T106	4
all_pins[6]	values[0x0]	118595	1		T1	2		T2	2		T3	2
all_pins[6]	values[0x1]	65	1		T104	3		T105	2		T106	6
all_pins[6]	transitions[0x0=>0x1]	51	1		T104	2		T105	2		T106	6
all_pins[6]	transitions[0x1=>0x0]	42	1		T105	1		T198	1		T277	2
all_pins[7]	values[0x0]	118604	1		T1	2		T2	2		T3	2
all_pins[7]	values[0x1]	56	1		T104	1		T105	1		T198	1
all_pins[7]	transitions[0x0=>0x1]	46	1		T104	1		T105	1		T198	1
all_pins[7]	transitions[0x1=>0x0]	40	1		T104	2		T105	1		T106	1
all_pins[8]	values[0x0]	118610	1		T1	2		T2	2		T3	2
all_pins[8]	values[0x1]	50	1		T104	2		T105	1		T106	1
all_pins[8]	transitions[0x0=>0x1]	34	1		T104	1		T105	1		T106	1
all_pins[8]	transitions[0x1=>0x0]	53	1		T104	2		T105	4		T106	1
all_pins[9]	values[0x0]	118591	1		T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	69	1		T104	3		T105	4		T106	1
all_pins[9]	transitions[0x0=>0x1]	59	1		T104	3		T105	3		T106	1
all_pins[9]	transitions[0x1=>0x0]	43	1		T104	1		T106	2		T278	1
all_pins[10]	values[0x0]	118607	1		T1	2		T2	2		T3	2
all_pins[10]	values[0x1]	53	1		T104	1		T105	1		T106	2
all_pins[10]	transitions[0x0=>0x1]	37	1		T105	1		T106	1		T278	1
all_pins[10]	transitions[0x1=>0x0]	95	1		T63	1		T64	1		T65	1
all_pins[11]	values[0x0]	118549	1		T1	2		T2	2		T3	2
all_pins[11]	values[0x1]	111	1		T63	1		T64	1		T65	1
all_pins[11]	transitions[0x0=>0x1]	96	1		T63	1		T64	1		T65	1
all_pins[11]	transitions[0x1=>0x0]	51	1		T105	1		T198	1		T277	1
all_pins[12]	values[0x0]	118594	1		T1	2		T2	2		T3	2
all_pins[12]	values[0x1]	66	1		T104	1		T105	1		T198	2
all_pins[12]	transitions[0x0=>0x1]	54	1		T104	1		T198	1		T277	1
all_pins[12]	transitions[0x1=>0x0]	47	1		T104	1		T105	1		T106	3
all_pins[13]	values[0x0]	118601	1		T1	2		T2	2		T3	2
all_pins[13]	values[0x1]	59	1		T104	1		T105	2		T106	3
all_pins[13]	transitions[0x0=>0x1]	43	1		T106	3		T198	2		T278	4
all_pins[13]	transitions[0x1=>0x0]	44	1		T104	3		T105	1		T106	1
all_pins[14]	values[0x0]	118600	1		T1	2		T2	2		T3	2
all_pins[14]	values[0x1]	60	1		T104	4		T105	3		T106	1
all_pins[14]	transitions[0x0=>0x1]	45	1		T104	4		T105	2		T198	1
all_pins[14]	transitions[0x1=>0x0]	52	1		T104	2		T105	3		T106	3
all_pins[15]	values[0x0]	118593	1		T1	2		T2	2		T3	2
all_pins[15]	values[0x1]	67	1		T104	2		T105	4		T106	4
all_pins[15]	transitions[0x0=>0x1]	50	1		T104	2		T105	3		T106	3
all_pins[15]	transitions[0x1=>0x0]	57	1		T105	1		T277	2		T278	3
all_pins[16]	values[0x0]	118586	1		T1	2		T2	2		T3	2
all_pins[16]	values[0x1]	74	1		T105	2		T106	1		T198	1
all_pins[16]	transitions[0x0=>0x1]	62	1		T105	2		T198	1		T277	2
all_pins[16]	transitions[0x1=>0x0]	42	1		T104	1		T105	2		T106	2
all_pins[17]	values[0x0]	118606	1		T1	2		T2	2		T3	2
all_pins[17]	values[0x1]	54	1		T104	1		T105	2		T106	3
all_pins[17]	transitions[0x0=>0x1]	30	1		T104	1		T105	1		T106	3
all_pins[17]	transitions[0x1=>0x0]	152	1		T53	1		T17	1		T24	1