Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1		T104	7		T105	7		T106	7
all_values[1]	278	1		T104	7		T105	7		T106	7
all_values[2]	278	1		T104	7		T105	7		T106	7
all_values[3]	278	1		T104	7		T105	7		T106	7
all_values[4]	278	1		T104	7		T105	7		T106	7
all_values[5]	278	1		T104	7		T105	7		T106	7
all_values[6]	278	1		T104	7		T105	7		T106	7
all_values[7]	278	1		T104	7		T105	7		T106	7
all_values[8]	278	1		T104	7		T105	7		T106	7
all_values[9]	278	1		T104	7		T105	7		T106	7
all_values[10]	278	1		T104	7		T105	7		T106	7
all_values[11]	278	1		T104	7		T105	7		T106	7
all_values[12]	278	1		T104	7		T105	7		T106	7
all_values[13]	278	1		T104	7		T105	7		T106	7
all_values[14]	278	1		T104	7		T105	7		T106	7
all_values[15]	278	1		T104	7		T105	7		T106	7
all_values[16]	278	1		T104	7		T105	7		T106	7
all_values[17]	278	1		T104	7		T105	7		T106	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2740	1		T104	67		T105	65		T106	64
auto[1]	2264	1		T104	59		T105	61		T106	62

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	845	1		T104	18		T105	9		T106	16
auto[1]	4159	1		T104	108		T105	117		T106	110

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2917	1		T104	70		T105	66		T106	75
auto[1]	2087	1		T104	56		T105	60		T106	51

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	20	1		T104	3		T277	1		T281	1
all_values[0]	auto[0]	auto[0]	auto[1]	63	1		T104	1		T105	2		T106	2
all_values[0]	auto[0]	auto[1]	auto[0]	11	1		T104	2		T198	1		T277	2
all_values[0]	auto[0]	auto[1]	auto[1]	59	1		T105	2		T106	2		T198	2
all_values[0]	auto[1]	auto[0]	auto[1]	67	1		T105	2		T106	2		T198	1
all_values[0]	auto[1]	auto[1]	auto[1]	58	1		T104	1		T105	1		T106	1
all_values[1]	auto[0]	auto[0]	auto[0]	20	1		T277	1		T284	1		T280	1
all_values[1]	auto[0]	auto[0]	auto[1]	59	1		T104	2		T105	3		T106	4
all_values[1]	auto[0]	auto[1]	auto[0]	19	1		T278	4		T279	1		T280	1
all_values[1]	auto[0]	auto[1]	auto[1]	55	1		T105	1		T106	1		T198	4
all_values[1]	auto[1]	auto[0]	auto[1]	64	1		T104	3		T105	1		T198	1
all_values[1]	auto[1]	auto[1]	auto[1]	61	1		T104	2		T105	2		T106	2
all_values[2]	auto[0]	auto[0]	auto[0]	32	1		T106	1		T277	1		T284	1
all_values[2]	auto[0]	auto[0]	auto[1]	52	1		T104	1		T198	3		T277	2
all_values[2]	auto[0]	auto[1]	auto[0]	11	1		T104	1		T279	2		T286	1
all_values[2]	auto[0]	auto[1]	auto[1]	62	1		T104	1		T105	4		T106	4
all_values[2]	auto[1]	auto[0]	auto[1]	67	1		T105	2		T106	1		T198	1
all_values[2]	auto[1]	auto[1]	auto[1]	54	1		T104	4		T105	1		T106	1
all_values[3]	auto[0]	auto[0]	auto[0]	32	1		T104	2		T105	1		T277	2
all_values[3]	auto[0]	auto[0]	auto[1]	57	1		T106	3		T198	3		T278	3
all_values[3]	auto[0]	auto[1]	auto[0]	23	1		T104	5		T277	2		T279	1
all_values[3]	auto[0]	auto[1]	auto[1]	59	1		T105	3		T277	1		T278	1
all_values[3]	auto[1]	auto[0]	auto[1]	60	1		T105	1		T106	2		T198	3
all_values[3]	auto[1]	auto[1]	auto[1]	47	1		T105	2		T106	2		T198	1
all_values[4]	auto[0]	auto[0]	auto[0]	29	1		T106	2		T277	1		T281	1
all_values[4]	auto[0]	auto[0]	auto[1]	69	1		T104	4		T106	3		T198	4
all_values[4]	auto[0]	auto[1]	auto[0]	21	1		T104	1		T106	1		T280	2
all_values[4]	auto[0]	auto[1]	auto[1]	45	1		T105	3		T277	2		T278	2
all_values[4]	auto[1]	auto[0]	auto[1]	65	1		T104	1		T105	2		T198	2
all_values[4]	auto[1]	auto[1]	auto[1]	49	1		T104	1		T105	2		T106	1
all_values[5]	auto[0]	auto[0]	auto[0]	25	1		T280	3		T283	1		T287	1
all_values[5]	auto[0]	auto[0]	auto[1]	60	1		T105	1		T106	1		T198	3
all_values[5]	auto[0]	auto[1]	auto[0]	11	1		T279	1		T282	1		T288	3
all_values[5]	auto[0]	auto[1]	auto[1]	58	1		T104	3		T105	1		T106	3
all_values[5]	auto[1]	auto[0]	auto[1]	66	1		T104	2		T105	4		T106	1
all_values[5]	auto[1]	auto[1]	auto[1]	58	1		T104	2		T105	1		T106	2
all_values[6]	auto[0]	auto[0]	auto[0]	32	1		T105	1		T198	3		T277	2
all_values[6]	auto[0]	auto[0]	auto[1]	60	1		T104	2		T105	2		T198	2
all_values[6]	auto[0]	auto[1]	auto[0]	20	1		T277	2		T283	1		T287	1
all_values[6]	auto[0]	auto[1]	auto[1]	53	1		T104	2		T105	2		T106	3
all_values[6]	auto[1]	auto[0]	auto[1]	69	1		T104	2		T278	4		T281	2
all_values[6]	auto[1]	auto[1]	auto[1]	44	1		T104	1		T105	2		T106	4
all_values[7]	auto[0]	auto[0]	auto[0]	23	1		T279	2		T287	3		T288	1
all_values[7]	auto[0]	auto[0]	auto[1]	56	1		T104	1		T105	3		T106	1
all_values[7]	auto[0]	auto[1]	auto[0]	16	1		T106	2		T278	4		T279	1
all_values[7]	auto[0]	auto[1]	auto[1]	70	1		T104	2		T105	2		T106	2
all_values[7]	auto[1]	auto[0]	auto[1]	63	1		T104	3		T105	1		T106	2
all_values[7]	auto[1]	auto[1]	auto[1]	50	1		T104	1		T105	1		T198	2
all_values[8]	auto[0]	auto[0]	auto[0]	32	1		T104	1		T106	1		T198	1
all_values[8]	auto[0]	auto[0]	auto[1]	53	1		T105	2		T106	3		T198	1
all_values[8]	auto[0]	auto[1]	auto[0]	19	1		T106	2		T198	2		T281	1
all_values[8]	auto[0]	auto[1]	auto[1]	60	1		T104	2		T277	2		T281	1
all_values[8]	auto[1]	auto[0]	auto[1]	67	1		T104	3		T105	5		T106	1
all_values[8]	auto[1]	auto[1]	auto[1]	47	1		T104	1		T277	3		T278	1
all_values[9]	auto[0]	auto[0]	auto[0]	35	1		T106	2		T198	2		T277	3
all_values[9]	auto[0]	auto[0]	auto[1]	55	1		T104	1		T105	1		T106	2
all_values[9]	auto[0]	auto[1]	auto[0]	16	1		T198	1		T277	4		T281	1
all_values[9]	auto[0]	auto[1]	auto[1]	61	1		T104	2		T105	2		T106	1
all_values[9]	auto[1]	auto[0]	auto[1]	58	1		T104	2		T105	2		T106	1
all_values[9]	auto[1]	auto[1]	auto[1]	53	1		T104	2		T105	2		T106	1
all_values[10]	auto[0]	auto[0]	auto[0]	43	1		T104	1		T105	1		T277	2
all_values[10]	auto[0]	auto[0]	auto[1]	59	1		T104	3		T105	2		T106	1
all_values[10]	auto[0]	auto[1]	auto[0]	23	1		T287	2		T288	1		T289	1
all_values[10]	auto[0]	auto[1]	auto[1]	55	1		T104	2		T106	2		T277	1
all_values[10]	auto[1]	auto[0]	auto[1]	69	1		T104	1		T105	4		T106	3
all_values[10]	auto[1]	auto[1]	auto[1]	29	1		T106	1		T277	2		T278	1
all_values[11]	auto[0]	auto[0]	auto[0]	35	1		T278	4		T280	1		T290	1
all_values[11]	auto[0]	auto[0]	auto[1]	62	1		T104	2		T105	3		T106	4
all_values[11]	auto[0]	auto[1]	auto[0]	16	1		T288	1		T291	2		T292	1
all_values[11]	auto[0]	auto[1]	auto[1]	49	1		T104	1		T105	1		T198	1
all_values[11]	auto[1]	auto[0]	auto[1]	64	1		T104	1		T105	2		T106	1
all_values[11]	auto[1]	auto[1]	auto[1]	52	1		T104	3		T105	1		T106	2
all_values[12]	auto[0]	auto[0]	auto[0]	29	1		T106	1		T277	1		T284	1
all_values[12]	auto[0]	auto[0]	auto[1]	56	1		T104	3		T105	1		T106	2
all_values[12]	auto[0]	auto[1]	auto[0]	11	1		T279	1		T293	1		T292	1
all_values[12]	auto[0]	auto[1]	auto[1]	62	1		T104	2		T105	3		T106	2
all_values[12]	auto[1]	auto[0]	auto[1]	63	1		T104	1		T105	1		T106	1
all_values[12]	auto[1]	auto[1]	auto[1]	57	1		T104	1		T105	2		T106	1
all_values[13]	auto[0]	auto[0]	auto[0]	47	1		T104	1		T105	1		T106	2
all_values[13]	auto[0]	auto[0]	auto[1]	53	1		T104	2		T105	1		T198	1
all_values[13]	auto[0]	auto[1]	auto[0]	16	1		T278	2		T285	1		T287	1
all_values[13]	auto[0]	auto[1]	auto[1]	47	1		T105	1		T106	1		T198	2
all_values[13]	auto[1]	auto[0]	auto[1]	61	1		T104	2		T105	2		T106	1
all_values[13]	auto[1]	auto[1]	auto[1]	54	1		T104	2		T105	2		T106	3
all_values[14]	auto[0]	auto[0]	auto[0]	22	1		T105	1		T277	1		T278	1
all_values[14]	auto[0]	auto[0]	auto[1]	58	1		T104	1		T105	2		T106	1
all_values[14]	auto[0]	auto[1]	auto[0]	16	1		T105	1		T198	1		T277	1
all_values[14]	auto[0]	auto[1]	auto[1]	64	1		T104	1		T105	1		T106	1
all_values[14]	auto[1]	auto[0]	auto[1]	60	1		T104	4		T106	3		T198	1
all_values[14]	auto[1]	auto[1]	auto[1]	58	1		T104	1		T105	2		T106	2
all_values[15]	auto[0]	auto[0]	auto[0]	41	1		T105	1		T278	2		T281	1
all_values[15]	auto[0]	auto[0]	auto[1]	58	1		T104	1		T106	3		T198	1
all_values[15]	auto[0]	auto[1]	auto[0]	15	1		T280	1		T290	1		T294	4
all_values[15]	auto[0]	auto[1]	auto[1]	51	1		T104	2		T105	3		T106	1
all_values[15]	auto[1]	auto[0]	auto[1]	53	1		T198	1		T277	4		T278	1
all_values[15]	auto[1]	auto[1]	auto[1]	60	1		T104	4		T105	3		T106	3
all_values[16]	auto[0]	auto[0]	auto[0]	21	1		T104	1		T277	1		T278	1
all_values[16]	auto[0]	auto[0]	auto[1]	50	1		T104	3		T105	2		T106	2
all_values[16]	auto[0]	auto[1]	auto[0]	22	1		T106	2		T277	1		T285	1
all_values[16]	auto[0]	auto[1]	auto[1]	64	1		T104	1		T105	2		T106	2
all_values[16]	auto[1]	auto[0]	auto[1]	58	1		T104	2		T105	1		T198	2
all_values[16]	auto[1]	auto[1]	auto[1]	63	1		T105	2		T106	1		T198	3
all_values[17]	auto[0]	auto[0]	auto[0]	32	1		T105	1		T277	1		T284	2
all_values[17]	auto[0]	auto[0]	auto[1]	67	1		T104	1		T105	1		T106	2
all_values[17]	auto[0]	auto[1]	auto[0]	9	1		T105	1		T277	1		T290	1
all_values[17]	auto[0]	auto[1]	auto[1]	51	1		T104	3		T198	1		T277	1
all_values[17]	auto[1]	auto[0]	auto[1]	69	1		T104	3		T105	2		T106	2
all_values[17]	auto[1]	auto[1]	auto[1]	50	1		T105	2		T106	3		T198	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal