Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.41 97.48 92.23 97.86 68.75 95.77 98.17 96.58


Total test records in report: 2133
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T218 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.645158266 Jun 06 02:20:16 PM PDT 24 Jun 06 02:20:21 PM PDT 24 455292420 ps
T219 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.4215436881 Jun 06 02:20:09 PM PDT 24 Jun 06 02:20:17 PM PDT 24 893129051 ps
T250 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1409822789 Jun 06 02:20:01 PM PDT 24 Jun 06 02:20:10 PM PDT 24 675732515 ps
T2039 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3772505874 Jun 06 02:20:18 PM PDT 24 Jun 06 02:20:21 PM PDT 24 112362764 ps
T2040 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.87567077 Jun 06 02:20:24 PM PDT 24 Jun 06 02:20:27 PM PDT 24 271337043 ps
T251 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1497041051 Jun 06 02:20:06 PM PDT 24 Jun 06 02:20:13 PM PDT 24 813387791 ps
T233 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3483129163 Jun 06 02:20:16 PM PDT 24 Jun 06 02:20:21 PM PDT 24 470460115 ps
T252 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2763671074 Jun 06 02:20:07 PM PDT 24 Jun 06 02:20:11 PM PDT 24 118602877 ps
T253 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1424465310 Jun 06 02:19:59 PM PDT 24 Jun 06 02:20:08 PM PDT 24 68115990 ps
T287 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1209769939 Jun 06 02:20:45 PM PDT 24 Jun 06 02:20:46 PM PDT 24 38901901 ps
T288 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1708877346 Jun 06 02:20:13 PM PDT 24 Jun 06 02:20:15 PM PDT 24 72745545 ps
T291 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.4236193708 Jun 06 02:20:12 PM PDT 24 Jun 06 02:20:14 PM PDT 24 41573516 ps
T300 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.742569754 Jun 06 02:20:18 PM PDT 24 Jun 06 02:20:23 PM PDT 24 623875250 ps
T234 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3443643570 Jun 06 02:20:20 PM PDT 24 Jun 06 02:20:22 PM PDT 24 87979929 ps
T2041 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1737667108 Jun 06 02:19:58 PM PDT 24 Jun 06 02:20:00 PM PDT 24 36866499 ps
T235 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1787456385 Jun 06 02:20:17 PM PDT 24 Jun 06 02:20:22 PM PDT 24 571881710 ps
T2042 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2444790899 Jun 06 02:20:09 PM PDT 24 Jun 06 02:20:12 PM PDT 24 143897523 ps
T289 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2383071209 Jun 06 02:20:04 PM PDT 24 Jun 06 02:20:07 PM PDT 24 35784697 ps
T301 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3747865477 Jun 06 02:20:07 PM PDT 24 Jun 06 02:20:12 PM PDT 24 409865510 ps
T294 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2389685341 Jun 06 02:20:33 PM PDT 24 Jun 06 02:20:34 PM PDT 24 97745055 ps
T254 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1066307666 Jun 06 02:20:16 PM PDT 24 Jun 06 02:20:18 PM PDT 24 50027519 ps
T295 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2211381138 Jun 06 02:20:19 PM PDT 24 Jun 06 02:20:26 PM PDT 24 1728037425 ps
T275 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2861167791 Jun 06 02:20:19 PM PDT 24 Jun 06 02:20:25 PM PDT 24 821802651 ps
T2043 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3052707139 Jun 06 02:20:27 PM PDT 24 Jun 06 02:20:29 PM PDT 24 110271988 ps
T2044 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.804343081 Jun 06 02:20:31 PM PDT 24 Jun 06 02:20:32 PM PDT 24 59958195 ps
T2045 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3273988806 Jun 06 02:19:58 PM PDT 24 Jun 06 02:20:00 PM PDT 24 76026229 ps
T276 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2280003654 Jun 06 02:19:57 PM PDT 24 Jun 06 02:20:04 PM PDT 24 1443724852 ps
T286 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.318713860 Jun 06 02:20:24 PM PDT 24 Jun 06 02:20:26 PM PDT 24 90153658 ps
T2046 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2499993343 Jun 06 02:20:01 PM PDT 24 Jun 06 02:20:07 PM PDT 24 615476967 ps
T225 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.4031118888 Jun 06 02:20:04 PM PDT 24 Jun 06 02:20:09 PM PDT 24 238152032 ps
T2047 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3117717681 Jun 06 02:20:21 PM PDT 24 Jun 06 02:20:24 PM PDT 24 125940498 ps
T2048 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3275581269 Jun 06 02:20:31 PM PDT 24 Jun 06 02:20:33 PM PDT 24 51120959 ps
T2049 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2227943346 Jun 06 02:20:04 PM PDT 24 Jun 06 02:20:08 PM PDT 24 57279024 ps
T2050 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2902370917 Jun 06 02:20:03 PM PDT 24 Jun 06 02:20:06 PM PDT 24 88302531 ps
T223 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.842112275 Jun 06 02:20:08 PM PDT 24 Jun 06 02:20:13 PM PDT 24 116201433 ps
T2051 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.212840166 Jun 06 02:20:10 PM PDT 24 Jun 06 02:20:15 PM PDT 24 411261412 ps
T224 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.670899581 Jun 06 02:20:18 PM PDT 24 Jun 06 02:20:21 PM PDT 24 112700613 ps
T292 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.44935910 Jun 06 02:20:34 PM PDT 24 Jun 06 02:20:35 PM PDT 24 36515032 ps
T2052 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.802006812 Jun 06 02:20:02 PM PDT 24 Jun 06 02:20:04 PM PDT 24 55756048 ps
T2053 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.597498198 Jun 06 02:20:03 PM PDT 24 Jun 06 02:20:07 PM PDT 24 171813007 ps
T255 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4110398289 Jun 06 02:19:50 PM PDT 24 Jun 06 02:19:53 PM PDT 24 52008216 ps
T2054 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.658973192 Jun 06 02:20:17 PM PDT 24 Jun 06 02:20:18 PM PDT 24 63701536 ps
T2055 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2000694860 Jun 06 02:20:14 PM PDT 24 Jun 06 02:20:16 PM PDT 24 80918090 ps
T296 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2357647735 Jun 06 02:20:06 PM PDT 24 Jun 06 02:20:15 PM PDT 24 2403363566 ps
T229 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.4108205319 Jun 06 02:20:09 PM PDT 24 Jun 06 02:20:14 PM PDT 24 244313395 ps
T2056 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2955001676 Jun 06 02:19:52 PM PDT 24 Jun 06 02:19:56 PM PDT 24 242108352 ps
T2057 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.4075658217 Jun 06 02:20:01 PM PDT 24 Jun 06 02:20:05 PM PDT 24 158806371 ps
T228 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.433759633 Jun 06 02:20:08 PM PDT 24 Jun 06 02:20:12 PM PDT 24 92995185 ps
T227 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3886067276 Jun 06 02:20:19 PM PDT 24 Jun 06 02:20:21 PM PDT 24 150867056 ps
T2058 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.47884105 Jun 06 02:20:29 PM PDT 24 Jun 06 02:20:30 PM PDT 24 36985899 ps
T258 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.4048060444 Jun 06 02:20:23 PM PDT 24 Jun 06 02:20:25 PM PDT 24 105502324 ps
T2059 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1512677339 Jun 06 02:19:52 PM PDT 24 Jun 06 02:19:54 PM PDT 24 115125957 ps
T2060 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3733680740 Jun 06 02:20:31 PM PDT 24 Jun 06 02:20:35 PM PDT 24 118098818 ps
T2061 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3219067577 Jun 06 02:20:27 PM PDT 24 Jun 06 02:20:29 PM PDT 24 41609064 ps
T2062 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.626316273 Jun 06 02:20:20 PM PDT 24 Jun 06 02:20:22 PM PDT 24 170282954 ps
T256 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1591202782 Jun 06 02:20:08 PM PDT 24 Jun 06 02:20:12 PM PDT 24 74663960 ps
T298 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.949392818 Jun 06 02:20:13 PM PDT 24 Jun 06 02:20:22 PM PDT 24 1780868274 ps
T2063 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.4232623611 Jun 06 02:20:30 PM PDT 24 Jun 06 02:20:31 PM PDT 24 36010102 ps
T2064 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1847661788 Jun 06 02:20:21 PM PDT 24 Jun 06 02:20:23 PM PDT 24 38675944 ps
T2065 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3973346572 Jun 06 02:20:00 PM PDT 24 Jun 06 02:20:08 PM PDT 24 1812342822 ps
T2066 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.380886902 Jun 06 02:20:28 PM PDT 24 Jun 06 02:20:31 PM PDT 24 78957945 ps
T2067 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.636752215 Jun 06 02:20:06 PM PDT 24 Jun 06 02:20:10 PM PDT 24 143301348 ps
T2068 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2001330375 Jun 06 02:20:21 PM PDT 24 Jun 06 02:20:23 PM PDT 24 43575389 ps
T2069 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.880405601 Jun 06 02:19:58 PM PDT 24 Jun 06 02:20:01 PM PDT 24 61686265 ps
T2070 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.786795207 Jun 06 02:20:04 PM PDT 24 Jun 06 02:20:08 PM PDT 24 181967500 ps
T231 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2342793374 Jun 06 02:20:01 PM PDT 24 Jun 06 02:20:05 PM PDT 24 137577842 ps
T2071 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3949926245 Jun 06 02:20:23 PM PDT 24 Jun 06 02:20:27 PM PDT 24 360369040 ps
T2072 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2670247268 Jun 06 02:20:05 PM PDT 24 Jun 06 02:20:11 PM PDT 24 111493645 ps
T2073 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3173275022 Jun 06 02:20:19 PM PDT 24 Jun 06 02:20:22 PM PDT 24 67522350 ps
T2074 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3609910701 Jun 06 02:20:23 PM PDT 24 Jun 06 02:20:25 PM PDT 24 57959967 ps
T2075 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1913699117 Jun 06 02:20:05 PM PDT 24 Jun 06 02:20:08 PM PDT 24 79022316 ps
T2076 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1926887147 Jun 06 02:20:38 PM PDT 24 Jun 06 02:20:40 PM PDT 24 39001335 ps
T2077 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3555009456 Jun 06 02:20:04 PM PDT 24 Jun 06 02:20:10 PM PDT 24 105359234 ps
T2078 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2484296230 Jun 06 02:20:00 PM PDT 24 Jun 06 02:20:01 PM PDT 24 37465285 ps
T2079 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.205445146 Jun 06 02:20:07 PM PDT 24 Jun 06 02:20:11 PM PDT 24 146346636 ps
T2080 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.569139107 Jun 06 02:19:57 PM PDT 24 Jun 06 02:20:00 PM PDT 24 216416237 ps
T257 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1754639152 Jun 06 02:20:22 PM PDT 24 Jun 06 02:20:25 PM PDT 24 111094171 ps
T2081 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3473660740 Jun 06 02:19:58 PM PDT 24 Jun 06 02:20:01 PM PDT 24 52376637 ps
T2082 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3170559440 Jun 06 02:20:09 PM PDT 24 Jun 06 02:20:14 PM PDT 24 204645298 ps
T299 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3871812649 Jun 06 02:20:07 PM PDT 24 Jun 06 02:20:13 PM PDT 24 618851262 ps
T2083 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.914161852 Jun 06 02:20:12 PM PDT 24 Jun 06 02:20:15 PM PDT 24 162746024 ps
T2084 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2182616140 Jun 06 02:20:24 PM PDT 24 Jun 06 02:20:27 PM PDT 24 67121717 ps
T2085 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.877639277 Jun 06 02:19:57 PM PDT 24 Jun 06 02:19:59 PM PDT 24 129660200 ps
T2086 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.430308984 Jun 06 02:20:07 PM PDT 24 Jun 06 02:20:11 PM PDT 24 47351214 ps
T2087 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1734107573 Jun 06 02:20:20 PM PDT 24 Jun 06 02:20:22 PM PDT 24 129499926 ps
T2088 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2725950030 Jun 06 02:20:05 PM PDT 24 Jun 06 02:20:11 PM PDT 24 294835847 ps
T2089 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2647705319 Jun 06 02:20:24 PM PDT 24 Jun 06 02:20:26 PM PDT 24 42913169 ps
T259 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.4098749938 Jun 06 02:20:04 PM PDT 24 Jun 06 02:20:09 PM PDT 24 228861206 ps
T2090 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3601176 Jun 06 02:20:16 PM PDT 24 Jun 06 02:20:19 PM PDT 24 185766743 ps
T2091 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.4231378803 Jun 06 02:19:58 PM PDT 24 Jun 06 02:20:00 PM PDT 24 40516939 ps
T2092 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.368909286 Jun 06 02:20:06 PM PDT 24 Jun 06 02:20:09 PM PDT 24 98958680 ps
T2093 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1305314463 Jun 06 02:19:57 PM PDT 24 Jun 06 02:20:01 PM PDT 24 129509773 ps
T2094 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.603342562 Jun 06 02:20:05 PM PDT 24 Jun 06 02:20:10 PM PDT 24 194045197 ps
T2095 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.868168332 Jun 06 02:20:12 PM PDT 24 Jun 06 02:20:15 PM PDT 24 108439730 ps
T2096 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.675639440 Jun 06 02:20:02 PM PDT 24 Jun 06 02:20:05 PM PDT 24 82650452 ps
T2097 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1976365503 Jun 06 02:19:57 PM PDT 24 Jun 06 02:20:00 PM PDT 24 162875348 ps
T2098 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3445565987 Jun 06 02:20:35 PM PDT 24 Jun 06 02:20:36 PM PDT 24 48087767 ps
T2099 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2452357330 Jun 06 02:20:08 PM PDT 24 Jun 06 02:20:12 PM PDT 24 93785592 ps
T297 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.110007446 Jun 06 02:20:17 PM PDT 24 Jun 06 02:20:23 PM PDT 24 854196043 ps
T2100 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.191860673 Jun 06 02:19:56 PM PDT 24 Jun 06 02:19:58 PM PDT 24 63640336 ps
T2101 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2751427195 Jun 06 02:20:24 PM PDT 24 Jun 06 02:20:26 PM PDT 24 42568388 ps
T2102 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.929834290 Jun 06 02:20:18 PM PDT 24 Jun 06 02:20:20 PM PDT 24 111091494 ps
T2103 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1748133423 Jun 06 02:20:42 PM PDT 24 Jun 06 02:20:44 PM PDT 24 51828316 ps
T2104 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3078533856 Jun 06 02:20:20 PM PDT 24 Jun 06 02:20:24 PM PDT 24 114580502 ps
T2105 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.4268924560 Jun 06 02:20:19 PM PDT 24 Jun 06 02:20:25 PM PDT 24 1435715369 ps
T2106 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.213920097 Jun 06 02:20:20 PM PDT 24 Jun 06 02:20:21 PM PDT 24 53783557 ps
T2107 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.4258865948 Jun 06 02:20:20 PM PDT 24 Jun 06 02:20:22 PM PDT 24 53278494 ps
T2108 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.881516113 Jun 06 02:20:36 PM PDT 24 Jun 06 02:20:38 PM PDT 24 48985030 ps
T2109 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.282384419 Jun 06 02:20:28 PM PDT 24 Jun 06 02:20:30 PM PDT 24 79844087 ps
T2110 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1606322176 Jun 06 02:20:16 PM PDT 24 Jun 06 02:20:19 PM PDT 24 379232191 ps
T2111 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.302186619 Jun 06 02:20:05 PM PDT 24 Jun 06 02:20:08 PM PDT 24 64878391 ps
T2112 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3325764227 Jun 06 02:19:59 PM PDT 24 Jun 06 02:20:04 PM PDT 24 366793320 ps
T2113 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2136891449 Jun 06 02:19:58 PM PDT 24 Jun 06 02:20:00 PM PDT 24 84223015 ps
T2114 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3013117562 Jun 06 02:20:18 PM PDT 24 Jun 06 02:20:23 PM PDT 24 543692900 ps
T2115 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3693111259 Jun 06 02:20:19 PM PDT 24 Jun 06 02:20:21 PM PDT 24 42128107 ps
T2116 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3683654539 Jun 06 02:20:08 PM PDT 24 Jun 06 02:20:14 PM PDT 24 241700054 ps
T2117 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1069497241 Jun 06 02:20:20 PM PDT 24 Jun 06 02:20:22 PM PDT 24 147824251 ps
T2118 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.250468216 Jun 06 02:20:02 PM PDT 24 Jun 06 02:20:04 PM PDT 24 123824775 ps
T2119 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.4257419573 Jun 06 02:20:13 PM PDT 24 Jun 06 02:20:15 PM PDT 24 95431190 ps
T2120 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.110118830 Jun 06 02:20:06 PM PDT 24 Jun 06 02:20:11 PM PDT 24 298683140 ps
T2121 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.880650205 Jun 06 02:20:04 PM PDT 24 Jun 06 02:20:08 PM PDT 24 95062939 ps
T2122 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3220562129 Jun 06 02:20:41 PM PDT 24 Jun 06 02:20:43 PM PDT 24 44753186 ps
T2123 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2987364514 Jun 06 02:20:03 PM PDT 24 Jun 06 02:20:10 PM PDT 24 318079744 ps
T2124 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1448995907 Jun 06 02:20:22 PM PDT 24 Jun 06 02:20:24 PM PDT 24 63935888 ps
T2125 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.974030186 Jun 06 02:20:23 PM PDT 24 Jun 06 02:20:27 PM PDT 24 130984108 ps
T2126 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.788102407 Jun 06 02:20:09 PM PDT 24 Jun 06 02:20:14 PM PDT 24 245006085 ps
T2127 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3062717048 Jun 06 02:20:22 PM PDT 24 Jun 06 02:20:24 PM PDT 24 69945279 ps
T2128 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3151728048 Jun 06 02:19:59 PM PDT 24 Jun 06 02:20:08 PM PDT 24 1205450999 ps
T2129 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.181869116 Jun 06 02:20:04 PM PDT 24 Jun 06 02:20:09 PM PDT 24 418718250 ps
T2130 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1793169815 Jun 06 02:20:06 PM PDT 24 Jun 06 02:20:09 PM PDT 24 38297932 ps
T2131 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2979164068 Jun 06 02:20:28 PM PDT 24 Jun 06 02:20:30 PM PDT 24 44614791 ps
T2132 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2978188842 Jun 06 02:20:00 PM PDT 24 Jun 06 02:20:02 PM PDT 24 141503586 ps
T2133 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.658815187 Jun 06 02:20:06 PM PDT 24 Jun 06 02:20:09 PM PDT 24 191823371 ps

Test location /workspace/coverage/default/26.usbdev_streaming_out.1166494259
Short name T3
Test name
Test status
Simulation time 16110712304 ps
CPU time 173.73 seconds
Started Jun 06 01:49:47 PM PDT 24
Finished Jun 06 01:52:42 PM PDT 24
Peak memory 205616 kb
Host smart-31af5f61-b881-4ce9-bca2-779c623c7f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11664
94259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.1166494259
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1404808325
Short name T277
Test name
Test status
Simulation time 106271417 ps
CPU time 0.76 seconds
Started Jun 06 02:20:22 PM PDT 24
Finished Jun 06 02:20:24 PM PDT 24
Peak memory 204960 kb
Host smart-7ae24598-aa8f-44b4-bf6e-7ffb0849a4e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1404808325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1404808325
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.1432736060
Short name T35
Test name
Test status
Simulation time 10802280639 ps
CPU time 14.56 seconds
Started Jun 06 01:49:29 PM PDT 24
Finished Jun 06 01:49:44 PM PDT 24
Peak memory 205704 kb
Host smart-36909302-8817-4bc1-9db2-ddf712114b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14327
36060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.1432736060
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.3237108344
Short name T7
Test name
Test status
Simulation time 23263685310 ps
CPU time 24.24 seconds
Started Jun 06 01:45:22 PM PDT 24
Finished Jun 06 01:45:48 PM PDT 24
Peak memory 205704 kb
Host smart-19a7b2ba-a08e-404a-afd5-0e84b7166c07
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3237108344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.3237108344
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3130638139
Short name T193
Test name
Test status
Simulation time 169520773 ps
CPU time 1.71 seconds
Started Jun 06 02:20:04 PM PDT 24
Finished Jun 06 02:20:09 PM PDT 24
Peak memory 213404 kb
Host smart-2609ff5f-aca6-4a98-9d8a-9ec49c6dacdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130638139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.3130638139
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2903983134
Short name T279
Test name
Test status
Simulation time 114790412 ps
CPU time 0.76 seconds
Started Jun 06 02:20:28 PM PDT 24
Finished Jun 06 02:20:29 PM PDT 24
Peak memory 204948 kb
Host smart-d078ce18-1273-4189-a86a-7af0a28b8b96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2903983134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2903983134
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.411309878
Short name T550
Test name
Test status
Simulation time 10069883476 ps
CPU time 13.89 seconds
Started Jun 06 01:47:22 PM PDT 24
Finished Jun 06 01:47:37 PM PDT 24
Peak memory 206004 kb
Host smart-551f3303-0bc4-4728-8b7b-338aaf1311bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41130
9878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.411309878
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.893952577
Short name T133
Test name
Test status
Simulation time 10056971766 ps
CPU time 13.97 seconds
Started Jun 06 01:51:04 PM PDT 24
Finished Jun 06 01:51:19 PM PDT 24
Peak memory 205712 kb
Host smart-9fe6ce51-8d5c-4a21-8c0c-c959bd9e7976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89395
2577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.893952577
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.1806902382
Short name T47
Test name
Test status
Simulation time 10047371813 ps
CPU time 13.83 seconds
Started Jun 06 01:53:16 PM PDT 24
Finished Jun 06 01:53:31 PM PDT 24
Peak memory 205720 kb
Host smart-05235098-35f5-4632-bea3-b6d43198983c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18069
02382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.1806902382
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.3233380410
Short name T501
Test name
Test status
Simulation time 10152164518 ps
CPU time 13.4 seconds
Started Jun 06 01:47:14 PM PDT 24
Finished Jun 06 01:47:29 PM PDT 24
Peak memory 205604 kb
Host smart-db5760aa-2355-4424-9a34-520627d596ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32333
80410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.3233380410
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.645158266
Short name T218
Test name
Test status
Simulation time 455292420 ps
CPU time 4.16 seconds
Started Jun 06 02:20:16 PM PDT 24
Finished Jun 06 02:20:21 PM PDT 24
Peak memory 205232 kb
Host smart-f5aa1b6f-e19d-4cd1-9832-13e837de287a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=645158266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.645158266
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.1384883963
Short name T454
Test name
Test status
Simulation time 13372618609 ps
CPU time 16.71 seconds
Started Jun 06 01:47:04 PM PDT 24
Finished Jun 06 01:47:21 PM PDT 24
Peak memory 205744 kb
Host smart-8de307af-30c3-4870-8cd0-2f9e67752e0f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1384883963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.1384883963
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.140547886
Short name T40
Test name
Test status
Simulation time 10033958154 ps
CPU time 16.36 seconds
Started Jun 06 01:45:11 PM PDT 24
Finished Jun 06 01:45:28 PM PDT 24
Peak memory 205652 kb
Host smart-5e5bf1b0-51d4-4708-bfad-a21c1246e156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14054
7886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.140547886
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.1793816618
Short name T31
Test name
Test status
Simulation time 10036464359 ps
CPU time 14.68 seconds
Started Jun 06 01:45:48 PM PDT 24
Finished Jun 06 01:46:03 PM PDT 24
Peak memory 205636 kb
Host smart-e1bf6d0d-4300-45dd-a5c8-4d1f7502b991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17938
16618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.1793816618
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.2830307531
Short name T73
Test name
Test status
Simulation time 11048482415 ps
CPU time 15.17 seconds
Started Jun 06 01:44:16 PM PDT 24
Finished Jun 06 01:44:32 PM PDT 24
Peak memory 205616 kb
Host smart-7d48e25c-66f7-4136-96cc-b8cd3f43186c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28303
07531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.2830307531
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.3885217680
Short name T21
Test name
Test status
Simulation time 10067519531 ps
CPU time 14.6 seconds
Started Jun 06 01:50:14 PM PDT 24
Finished Jun 06 01:50:29 PM PDT 24
Peak memory 205656 kb
Host smart-3958c372-7ef6-4348-b7dd-b5fb5caaad16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38852
17680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.3885217680
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.2242673805
Short name T190
Test name
Test status
Simulation time 962075576 ps
CPU time 1.77 seconds
Started Jun 06 01:44:36 PM PDT 24
Finished Jun 06 01:44:38 PM PDT 24
Peak memory 222852 kb
Host smart-88c123f2-05c4-4fcd-90de-96b36817b1b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2242673805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2242673805
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/22.usbdev_smoke.2851464362
Short name T52
Test name
Test status
Simulation time 10117097049 ps
CPU time 14.99 seconds
Started Jun 06 01:49:01 PM PDT 24
Finished Jun 06 01:49:17 PM PDT 24
Peak memory 205732 kb
Host smart-3e10cfc4-7483-411f-8db8-b828903bc262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28514
64362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.2851464362
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.4092561530
Short name T358
Test name
Test status
Simulation time 10277678233 ps
CPU time 14.22 seconds
Started Jun 06 01:47:51 PM PDT 24
Finished Jun 06 01:48:07 PM PDT 24
Peak memory 205736 kb
Host smart-0adb07a9-b26c-42c7-ab5f-5d84a0ef60e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40925
61530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.4092561530
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.35271859
Short name T247
Test name
Test status
Simulation time 88075958 ps
CPU time 0.98 seconds
Started Jun 06 02:19:57 PM PDT 24
Finished Jun 06 02:19:59 PM PDT 24
Peak memory 205112 kb
Host smart-6ffaf40c-a209-41d6-a434-cbd15344e454
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=35271859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.35271859
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3052707139
Short name T2043
Test name
Test status
Simulation time 110271988 ps
CPU time 0.74 seconds
Started Jun 06 02:20:27 PM PDT 24
Finished Jun 06 02:20:29 PM PDT 24
Peak memory 204944 kb
Host smart-20cd3221-909e-4d0b-91d7-0e9069bab4aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3052707139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3052707139
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.3225087065
Short name T469
Test name
Test status
Simulation time 10038167943 ps
CPU time 13.31 seconds
Started Jun 06 01:48:06 PM PDT 24
Finished Jun 06 01:48:20 PM PDT 24
Peak memory 205720 kb
Host smart-c1564a77-31c5-474a-a1c4-9627236ee77a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32250
87065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.3225087065
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.50307342
Short name T195
Test name
Test status
Simulation time 119549766 ps
CPU time 3.45 seconds
Started Jun 06 02:20:10 PM PDT 24
Finished Jun 06 02:20:15 PM PDT 24
Peak memory 221020 kb
Host smart-43494500-92c5-4d29-b873-42e832ef5ca2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=50307342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.50307342
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1152852789
Short name T106
Test name
Test status
Simulation time 38894757 ps
CPU time 0.7 seconds
Started Jun 06 02:20:22 PM PDT 24
Finished Jun 06 02:20:24 PM PDT 24
Peak memory 204948 kb
Host smart-e23aee27-445e-478d-af51-e5764175ecbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1152852789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1152852789
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.2995925063
Short name T49
Test name
Test status
Simulation time 35528844634 ps
CPU time 641.23 seconds
Started Jun 06 01:44:34 PM PDT 24
Finished Jun 06 01:55:16 PM PDT 24
Peak memory 205684 kb
Host smart-e80a16bd-4861-48a2-b3f0-caf1c687b19d
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995925063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_
traffic.2995925063
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.110007446
Short name T297
Test name
Test status
Simulation time 854196043 ps
CPU time 5 seconds
Started Jun 06 02:20:17 PM PDT 24
Finished Jun 06 02:20:23 PM PDT 24
Peak memory 205140 kb
Host smart-e06f028b-a997-4433-b4a3-ee8f762d6038
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=110007446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.110007446
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1388686117
Short name T17
Test name
Test status
Simulation time 10086362320 ps
CPU time 16.69 seconds
Started Jun 06 01:50:13 PM PDT 24
Finished Jun 06 01:50:30 PM PDT 24
Peak memory 205604 kb
Host smart-5c62f4fd-8884-4394-a53e-731ba02c403a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13886
86117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1388686117
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1708877346
Short name T288
Test name
Test status
Simulation time 72745545 ps
CPU time 0.72 seconds
Started Jun 06 02:20:13 PM PDT 24
Finished Jun 06 02:20:15 PM PDT 24
Peak memory 204932 kb
Host smart-3fb0ffa9-03a4-4f37-bf50-3ebe0b9fe871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1708877346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1708877346
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.1374601694
Short name T70
Test name
Test status
Simulation time 11045368568 ps
CPU time 15.08 seconds
Started Jun 06 01:52:55 PM PDT 24
Finished Jun 06 01:53:11 PM PDT 24
Peak memory 205672 kb
Host smart-44ef5300-147f-4872-90e0-ec840cd0fc51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13746
01694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.1374601694
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2651496974
Short name T124
Test name
Test status
Simulation time 10099676939 ps
CPU time 13.47 seconds
Started Jun 06 01:48:33 PM PDT 24
Finished Jun 06 01:48:47 PM PDT 24
Peak memory 205696 kb
Host smart-8e604627-ff74-4c3a-8a58-6ef062647084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26514
96974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2651496974
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.680328687
Short name T187
Test name
Test status
Simulation time 45796488866 ps
CPU time 1071.43 seconds
Started Jun 06 01:46:12 PM PDT 24
Finished Jun 06 02:04:05 PM PDT 24
Peak memory 205748 kb
Host smart-6ab451ba-705b-4f23-995e-5847ffdd426c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=680328687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.680328687
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.3239896835
Short name T99
Test name
Test status
Simulation time 5136133891 ps
CPU time 132.9 seconds
Started Jun 06 01:43:46 PM PDT 24
Finished Jun 06 01:46:00 PM PDT 24
Peak memory 205636 kb
Host smart-4892c6a7-480b-46e3-bd00-5db27b10675e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32398
96835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.3239896835
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.676785656
Short name T68
Test name
Test status
Simulation time 10121300126 ps
CPU time 13.2 seconds
Started Jun 06 01:43:47 PM PDT 24
Finished Jun 06 01:44:01 PM PDT 24
Peak memory 205684 kb
Host smart-d1ffcf99-cca8-40f4-bd8e-fdfdec01f47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67678
5656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.676785656
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3871812649
Short name T299
Test name
Test status
Simulation time 618851262 ps
CPU time 3.18 seconds
Started Jun 06 02:20:07 PM PDT 24
Finished Jun 06 02:20:13 PM PDT 24
Peak memory 205144 kb
Host smart-9a328116-ee9e-40e7-9c26-80842a5e280c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3871812649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.3871812649
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.4215436881
Short name T219
Test name
Test status
Simulation time 893129051 ps
CPU time 5.08 seconds
Started Jun 06 02:20:09 PM PDT 24
Finished Jun 06 02:20:17 PM PDT 24
Peak memory 205164 kb
Host smart-7b49b2c0-59e2-4132-921c-ffa400b65363
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4215436881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.4215436881
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.505854523
Short name T175
Test name
Test status
Simulation time 30225007291 ps
CPU time 56.4 seconds
Started Jun 06 01:49:48 PM PDT 24
Finished Jun 06 01:50:45 PM PDT 24
Peak memory 205668 kb
Host smart-20bd5883-adfa-4d10-bfe5-c390bc30f160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50585
4523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.505854523
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.4100763999
Short name T327
Test name
Test status
Simulation time 10057170442 ps
CPU time 13.94 seconds
Started Jun 06 01:47:15 PM PDT 24
Finished Jun 06 01:47:30 PM PDT 24
Peak memory 205760 kb
Host smart-02b428e5-0be9-4330-b4e3-07c2364c4d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41007
63999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.4100763999
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3555009456
Short name T2077
Test name
Test status
Simulation time 105359234 ps
CPU time 2.77 seconds
Started Jun 06 02:20:04 PM PDT 24
Finished Jun 06 02:20:10 PM PDT 24
Peak memory 221092 kb
Host smart-2e4e6759-b600-49fe-bb62-8c6fdfc656e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3555009456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3555009456
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.2965054960
Short name T150
Test name
Test status
Simulation time 10076378584 ps
CPU time 15.99 seconds
Started Jun 06 01:44:35 PM PDT 24
Finished Jun 06 01:44:52 PM PDT 24
Peak memory 205732 kb
Host smart-d7b18e2c-6914-4b7f-acce-b8cbd0bdcfc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29650
54960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.2965054960
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.112334283
Short name T449
Test name
Test status
Simulation time 10067309559 ps
CPU time 13.79 seconds
Started Jun 06 01:47:28 PM PDT 24
Finished Jun 06 01:47:42 PM PDT 24
Peak memory 205736 kb
Host smart-715f4c4f-96e3-4f2e-b9e3-3af80adc1738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11233
4283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.112334283
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1507144192
Short name T528
Test name
Test status
Simulation time 10051659527 ps
CPU time 16.68 seconds
Started Jun 06 01:44:07 PM PDT 24
Finished Jun 06 01:44:25 PM PDT 24
Peak memory 205676 kb
Host smart-11a485b8-731e-49cf-b76a-fdd951327e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15071
44192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1507144192
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.1455369545
Short name T1657
Test name
Test status
Simulation time 10082405778 ps
CPU time 13.2 seconds
Started Jun 06 01:44:10 PM PDT 24
Finished Jun 06 01:44:24 PM PDT 24
Peak memory 205732 kb
Host smart-b8bc1100-b649-458e-a53e-eb6c68bc4335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14553
69545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.1455369545
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.557612672
Short name T717
Test name
Test status
Simulation time 10066833995 ps
CPU time 14.51 seconds
Started Jun 06 01:46:57 PM PDT 24
Finished Jun 06 01:47:12 PM PDT 24
Peak memory 205792 kb
Host smart-09227465-6671-477f-9ade-4fc43706590b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55761
2672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.557612672
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3716112367
Short name T1238
Test name
Test status
Simulation time 10050631585 ps
CPU time 15.07 seconds
Started Jun 06 01:47:00 PM PDT 24
Finished Jun 06 01:47:15 PM PDT 24
Peak memory 205712 kb
Host smart-c545a57f-cc02-4df8-b713-4839ca563eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37161
12367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3716112367
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_smoke.625384950
Short name T1320
Test name
Test status
Simulation time 10152695527 ps
CPU time 16.36 seconds
Started Jun 06 01:47:01 PM PDT 24
Finished Jun 06 01:47:18 PM PDT 24
Peak memory 205724 kb
Host smart-19f28b52-74e9-4dce-b968-a4b5cfa343f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62538
4950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.625384950
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.883055178
Short name T826
Test name
Test status
Simulation time 10044843884 ps
CPU time 15.68 seconds
Started Jun 06 01:47:21 PM PDT 24
Finished Jun 06 01:47:38 PM PDT 24
Peak memory 205768 kb
Host smart-1b130892-c657-4781-8fd0-c1a577902c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88305
5178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.883055178
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.3175797595
Short name T473
Test name
Test status
Simulation time 10093385439 ps
CPU time 12.73 seconds
Started Jun 06 01:47:32 PM PDT 24
Finished Jun 06 01:47:46 PM PDT 24
Peak memory 205676 kb
Host smart-bf568584-5876-4016-8ff0-4890ea8c1738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31757
97595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.3175797595
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.834756999
Short name T138
Test name
Test status
Simulation time 10128284969 ps
CPU time 14.27 seconds
Started Jun 06 01:47:59 PM PDT 24
Finished Jun 06 01:48:15 PM PDT 24
Peak memory 205728 kb
Host smart-20006acf-63ec-49e2-8fd0-d3f16e3eafcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83475
6999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.834756999
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.2281417989
Short name T1470
Test name
Test status
Simulation time 10097515836 ps
CPU time 12.33 seconds
Started Jun 06 01:47:50 PM PDT 24
Finished Jun 06 01:48:03 PM PDT 24
Peak memory 205644 kb
Host smart-cedd88a0-90f3-4507-acb5-7a52598ab368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22814
17989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.2281417989
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.3646085421
Short name T1505
Test name
Test status
Simulation time 10064070408 ps
CPU time 13.52 seconds
Started Jun 06 01:48:13 PM PDT 24
Finished Jun 06 01:48:28 PM PDT 24
Peak memory 205592 kb
Host smart-6f7558d2-8fe0-41d1-97dc-c05ae8cb4f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36460
85421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.3646085421
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.974030186
Short name T2125
Test name
Test status
Simulation time 130984108 ps
CPU time 2.85 seconds
Started Jun 06 02:20:23 PM PDT 24
Finished Jun 06 02:20:27 PM PDT 24
Peak memory 213424 kb
Host smart-8e715334-508f-47d2-87bc-b4959664def2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974030186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbde
v_csr_mem_rw_with_rand_reset.974030186
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.1861292412
Short name T749
Test name
Test status
Simulation time 10138355825 ps
CPU time 13.57 seconds
Started Jun 06 01:44:00 PM PDT 24
Finished Jun 06 01:44:14 PM PDT 24
Peak memory 205676 kb
Host smart-63f39bc5-9b40-497d-bf8a-432d4600ec6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18612
92412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1861292412
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.3144198908
Short name T1272
Test name
Test status
Simulation time 29194081959 ps
CPU time 533.31 seconds
Started Jun 06 01:44:01 PM PDT 24
Finished Jun 06 01:52:56 PM PDT 24
Peak memory 205720 kb
Host smart-aef03d9f-89d1-40b0-837b-b102cdd30c30
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3144198908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.3144198908
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.2148552819
Short name T123
Test name
Test status
Simulation time 10107498631 ps
CPU time 13.13 seconds
Started Jun 06 01:44:25 PM PDT 24
Finished Jun 06 01:44:39 PM PDT 24
Peak memory 205660 kb
Host smart-6d236700-74f9-4330-9e75-3c9aabb59a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21485
52819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.2148552819
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.3927553863
Short name T1415
Test name
Test status
Simulation time 10124816048 ps
CPU time 12.57 seconds
Started Jun 06 01:46:52 PM PDT 24
Finished Jun 06 01:47:06 PM PDT 24
Peak memory 205716 kb
Host smart-55d7a42c-2526-4427-8bfe-766f86a2e731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39275
53863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.3927553863
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.1655230443
Short name T112
Test name
Test status
Simulation time 10097280315 ps
CPU time 14.89 seconds
Started Jun 06 01:47:22 PM PDT 24
Finished Jun 06 01:47:38 PM PDT 24
Peak memory 205692 kb
Host smart-93d36e0d-0cb5-433f-8c05-032f58fb4902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16552
30443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.1655230443
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.284591125
Short name T120
Test name
Test status
Simulation time 10112904944 ps
CPU time 12.86 seconds
Started Jun 06 01:47:22 PM PDT 24
Finished Jun 06 01:47:37 PM PDT 24
Peak memory 205996 kb
Host smart-71949b28-1e6c-4e4a-82cf-37a79d302f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28459
1125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.284591125
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.1988314505
Short name T127
Test name
Test status
Simulation time 10109148952 ps
CPU time 14.68 seconds
Started Jun 06 01:47:42 PM PDT 24
Finished Jun 06 01:47:57 PM PDT 24
Peak memory 205648 kb
Host smart-88f0a2fa-e0b3-4dd8-87bc-2af51939eb77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19883
14505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.1988314505
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1653209634
Short name T131
Test name
Test status
Simulation time 10057484996 ps
CPU time 14.62 seconds
Started Jun 06 01:47:59 PM PDT 24
Finished Jun 06 01:48:15 PM PDT 24
Peak memory 205668 kb
Host smart-17e9f32f-f4a6-4195-8419-2fb8a9a19685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16532
09634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1653209634
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.4007756118
Short name T1134
Test name
Test status
Simulation time 11365937135 ps
CPU time 15.94 seconds
Started Jun 06 01:48:14 PM PDT 24
Finished Jun 06 01:48:31 PM PDT 24
Peak memory 205720 kb
Host smart-66703028-dfd6-4a72-bf7e-ff4f320d74dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40077
56118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.4007756118
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.2088477828
Short name T113
Test name
Test status
Simulation time 10081036466 ps
CPU time 13.86 seconds
Started Jun 06 01:49:01 PM PDT 24
Finished Jun 06 01:49:15 PM PDT 24
Peak memory 205636 kb
Host smart-534ec9d4-d465-4625-922b-2a5ef09c4007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20884
77828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.2088477828
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.4093199160
Short name T57
Test name
Test status
Simulation time 10102615540 ps
CPU time 13.56 seconds
Started Jun 06 01:49:19 PM PDT 24
Finished Jun 06 01:49:34 PM PDT 24
Peak memory 205720 kb
Host smart-d18a7945-ccfd-4a33-9598-afde7d9edc46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40931
99160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.4093199160
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.181741645
Short name T97
Test name
Test status
Simulation time 32816343925 ps
CPU time 62.59 seconds
Started Jun 06 01:49:10 PM PDT 24
Finished Jun 06 01:50:13 PM PDT 24
Peak memory 205644 kb
Host smart-d38d27f0-e454-42e9-b96f-d346e4d498ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18174
1645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.181741645
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.1970382104
Short name T103
Test name
Test status
Simulation time 10069957718 ps
CPU time 13.89 seconds
Started Jun 06 01:49:45 PM PDT 24
Finished Jun 06 01:50:00 PM PDT 24
Peak memory 205676 kb
Host smart-24be7fbe-76dc-4c09-89f6-068494e5b6f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19703
82104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.1970382104
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.1657927969
Short name T83
Test name
Test status
Simulation time 10042264882 ps
CPU time 13.87 seconds
Started Jun 06 01:50:14 PM PDT 24
Finished Jun 06 01:50:28 PM PDT 24
Peak memory 205708 kb
Host smart-3ea63baf-9983-41e0-a51f-5bfee2a0652d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16579
27969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.1657927969
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1305314463
Short name T2093
Test name
Test status
Simulation time 129509773 ps
CPU time 3.31 seconds
Started Jun 06 02:19:57 PM PDT 24
Finished Jun 06 02:20:01 PM PDT 24
Peak memory 205404 kb
Host smart-acbbe005-e391-4bd9-8807-d02b7753a659
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1305314463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1305314463
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3151728048
Short name T2128
Test name
Test status
Simulation time 1205450999 ps
CPU time 7.97 seconds
Started Jun 06 02:19:59 PM PDT 24
Finished Jun 06 02:20:08 PM PDT 24
Peak memory 205112 kb
Host smart-ac419dc6-06f0-4ab8-a5eb-79790085c848
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3151728048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3151728048
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.302186619
Short name T2111
Test name
Test status
Simulation time 64878391 ps
CPU time 0.79 seconds
Started Jun 06 02:20:05 PM PDT 24
Finished Jun 06 02:20:08 PM PDT 24
Peak memory 204900 kb
Host smart-c7000801-ea9d-40e6-913a-a3c310e3b1f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=302186619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.302186619
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1512677339
Short name T2059
Test name
Test status
Simulation time 115125957 ps
CPU time 1.26 seconds
Started Jun 06 02:19:52 PM PDT 24
Finished Jun 06 02:19:54 PM PDT 24
Peak memory 213448 kb
Host smart-09547723-f81b-4357-915a-2df21fd47ec2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512677339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.1512677339
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3273988806
Short name T2045
Test name
Test status
Simulation time 76026229 ps
CPU time 0.98 seconds
Started Jun 06 02:19:58 PM PDT 24
Finished Jun 06 02:20:00 PM PDT 24
Peak memory 204992 kb
Host smart-5ab51637-2f41-4a49-8c77-c2d4316a3419
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3273988806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3273988806
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.4231378803
Short name T2091
Test name
Test status
Simulation time 40516939 ps
CPU time 0.66 seconds
Started Jun 06 02:19:58 PM PDT 24
Finished Jun 06 02:20:00 PM PDT 24
Peak memory 204904 kb
Host smart-59c73827-6e02-4829-ad3d-2f247e9e6100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4231378803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.4231378803
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3473660740
Short name T2081
Test name
Test status
Simulation time 52376637 ps
CPU time 1.35 seconds
Started Jun 06 02:19:58 PM PDT 24
Finished Jun 06 02:20:01 PM PDT 24
Peak memory 213376 kb
Host smart-7f272e68-4603-4652-966c-bf7066adf2e0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3473660740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3473660740
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.997680714
Short name T2035
Test name
Test status
Simulation time 263257065 ps
CPU time 2.5 seconds
Started Jun 06 02:20:07 PM PDT 24
Finished Jun 06 02:20:12 PM PDT 24
Peak memory 205208 kb
Host smart-d8658fa0-8aae-4cd1-bd7c-08d892055171
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=997680714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.997680714
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.569139107
Short name T2080
Test name
Test status
Simulation time 216416237 ps
CPU time 1.83 seconds
Started Jun 06 02:19:57 PM PDT 24
Finished Jun 06 02:20:00 PM PDT 24
Peak memory 205088 kb
Host smart-64bf3bfa-5425-4cc0-b2e6-ba2a8187dc8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=569139107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.569139107
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.191860673
Short name T2100
Test name
Test status
Simulation time 63640336 ps
CPU time 1.4 seconds
Started Jun 06 02:19:56 PM PDT 24
Finished Jun 06 02:19:58 PM PDT 24
Peak memory 205228 kb
Host smart-a6f12eed-6982-43a7-8a19-ca5946e1b0a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=191860673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.191860673
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2955001676
Short name T2056
Test name
Test status
Simulation time 242108352 ps
CPU time 2.12 seconds
Started Jun 06 02:19:52 PM PDT 24
Finished Jun 06 02:19:56 PM PDT 24
Peak memory 205124 kb
Host smart-6f9168dd-c184-461f-802f-8c9184cc3e00
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2955001676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2955001676
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1497041051
Short name T251
Test name
Test status
Simulation time 813387791 ps
CPU time 4.6 seconds
Started Jun 06 02:20:06 PM PDT 24
Finished Jun 06 02:20:13 PM PDT 24
Peak memory 205200 kb
Host smart-f48ee29f-e672-43cc-a9db-ea2de234b687
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1497041051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1497041051
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.877639277
Short name T2085
Test name
Test status
Simulation time 129660200 ps
CPU time 0.97 seconds
Started Jun 06 02:19:57 PM PDT 24
Finished Jun 06 02:19:59 PM PDT 24
Peak memory 204948 kb
Host smart-ba4d357a-5ca9-4c12-a690-915836728f1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=877639277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.877639277
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.597498198
Short name T2053
Test name
Test status
Simulation time 171813007 ps
CPU time 2.05 seconds
Started Jun 06 02:20:03 PM PDT 24
Finished Jun 06 02:20:07 PM PDT 24
Peak memory 217488 kb
Host smart-a66e1e72-f3f9-435b-b33e-722431fbf951
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597498198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev
_csr_mem_rw_with_rand_reset.597498198
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2763671074
Short name T252
Test name
Test status
Simulation time 118602877 ps
CPU time 1.01 seconds
Started Jun 06 02:20:07 PM PDT 24
Finished Jun 06 02:20:11 PM PDT 24
Peak memory 205248 kb
Host smart-128c32c3-7874-4d8d-a995-7854f0b3104e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2763671074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2763671074
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1737667108
Short name T2041
Test name
Test status
Simulation time 36866499 ps
CPU time 0.64 seconds
Started Jun 06 02:19:58 PM PDT 24
Finished Jun 06 02:20:00 PM PDT 24
Peak memory 204896 kb
Host smart-6e20cb00-cc74-473f-b7e5-7aeae4f0f11e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1737667108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1737667108
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1424465310
Short name T253
Test name
Test status
Simulation time 68115990 ps
CPU time 2.27 seconds
Started Jun 06 02:19:59 PM PDT 24
Finished Jun 06 02:20:08 PM PDT 24
Peak memory 213600 kb
Host smart-665451c9-02f0-4c59-9c00-69971a7e1cce
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1424465310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1424465310
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2499993343
Short name T2046
Test name
Test status
Simulation time 615476967 ps
CPU time 4.54 seconds
Started Jun 06 02:20:01 PM PDT 24
Finished Jun 06 02:20:07 PM PDT 24
Peak memory 205276 kb
Host smart-55da20fe-7230-4fa5-8839-71f8ff6987ff
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2499993343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2499993343
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.658815187
Short name T2133
Test name
Test status
Simulation time 191823371 ps
CPU time 1.15 seconds
Started Jun 06 02:20:06 PM PDT 24
Finished Jun 06 02:20:09 PM PDT 24
Peak memory 205224 kb
Host smart-752b74f0-0854-45ac-bfb0-4ad0b95f9140
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=658815187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.658815187
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.4108205319
Short name T229
Test name
Test status
Simulation time 244313395 ps
CPU time 2.54 seconds
Started Jun 06 02:20:09 PM PDT 24
Finished Jun 06 02:20:14 PM PDT 24
Peak memory 213396 kb
Host smart-4de899e3-c55c-42de-9fe5-558268d253c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4108205319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.4108205319
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.4031118888
Short name T225
Test name
Test status
Simulation time 238152032 ps
CPU time 1.74 seconds
Started Jun 06 02:20:04 PM PDT 24
Finished Jun 06 02:20:09 PM PDT 24
Peak memory 213492 kb
Host smart-4bacb83e-4f2b-4c5e-9353-48e725bc0d36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031118888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.4031118888
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.658973192
Short name T2054
Test name
Test status
Simulation time 63701536 ps
CPU time 0.83 seconds
Started Jun 06 02:20:17 PM PDT 24
Finished Jun 06 02:20:18 PM PDT 24
Peak memory 204984 kb
Host smart-6092ceec-efbd-44cf-9cf5-d23aa3d15d63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=658973192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.658973192
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1914666419
Short name T2038
Test name
Test status
Simulation time 235852637 ps
CPU time 1.24 seconds
Started Jun 06 02:20:21 PM PDT 24
Finished Jun 06 02:20:23 PM PDT 24
Peak memory 205264 kb
Host smart-072e0c17-8b9a-4194-ae18-584426c38dec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1914666419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.1914666419
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.842112275
Short name T223
Test name
Test status
Simulation time 116201433 ps
CPU time 2 seconds
Started Jun 06 02:20:08 PM PDT 24
Finished Jun 06 02:20:13 PM PDT 24
Peak memory 213396 kb
Host smart-72a0ac8f-ea06-4cad-8769-03f350791ea3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=842112275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.842112275
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.742569754
Short name T300
Test name
Test status
Simulation time 623875250 ps
CPU time 4.17 seconds
Started Jun 06 02:20:18 PM PDT 24
Finished Jun 06 02:20:23 PM PDT 24
Peak memory 205148 kb
Host smart-1b530ed2-a1c8-4821-8432-ac495394e2ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=742569754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.742569754
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2182616140
Short name T2084
Test name
Test status
Simulation time 67121717 ps
CPU time 1.71 seconds
Started Jun 06 02:20:24 PM PDT 24
Finished Jun 06 02:20:27 PM PDT 24
Peak memory 213424 kb
Host smart-0502a1bf-fd50-4035-9615-bdeec01770da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182616140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2182616140
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.551424474
Short name T248
Test name
Test status
Simulation time 131936252 ps
CPU time 1.04 seconds
Started Jun 06 02:20:17 PM PDT 24
Finished Jun 06 02:20:18 PM PDT 24
Peak memory 205132 kb
Host smart-18503bd6-4d8d-4ba6-901d-ebef1a288c94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=551424474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.551424474
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1926887147
Short name T2076
Test name
Test status
Simulation time 39001335 ps
CPU time 0.65 seconds
Started Jun 06 02:20:38 PM PDT 24
Finished Jun 06 02:20:40 PM PDT 24
Peak memory 204916 kb
Host smart-07b0f324-935a-496a-b5c5-b922a92e3328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1926887147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1926887147
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1069497241
Short name T2117
Test name
Test status
Simulation time 147824251 ps
CPU time 1.57 seconds
Started Jun 06 02:20:20 PM PDT 24
Finished Jun 06 02:20:22 PM PDT 24
Peak memory 205156 kb
Host smart-d8f15d28-49c6-49aa-8dfe-ff05d55fa585
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1069497241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.1069497241
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.205445146
Short name T2079
Test name
Test status
Simulation time 146346636 ps
CPU time 1.73 seconds
Started Jun 06 02:20:07 PM PDT 24
Finished Jun 06 02:20:11 PM PDT 24
Peak memory 213432 kb
Host smart-04c4012f-5c1a-4bd5-bc33-d57c4f4b3c0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=205445146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.205445146
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1606322176
Short name T2110
Test name
Test status
Simulation time 379232191 ps
CPU time 2.7 seconds
Started Jun 06 02:20:16 PM PDT 24
Finished Jun 06 02:20:19 PM PDT 24
Peak memory 205176 kb
Host smart-3b7ec0cc-5190-4013-8997-1d00b1b614bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1606322176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1606322176
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.433759633
Short name T228
Test name
Test status
Simulation time 92995185 ps
CPU time 1.42 seconds
Started Jun 06 02:20:08 PM PDT 24
Finished Jun 06 02:20:12 PM PDT 24
Peak memory 213340 kb
Host smart-51a0f5d2-a23e-494e-b923-8873be62f292
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433759633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.433759633
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1734107573
Short name T2087
Test name
Test status
Simulation time 129499926 ps
CPU time 1.07 seconds
Started Jun 06 02:20:20 PM PDT 24
Finished Jun 06 02:20:22 PM PDT 24
Peak memory 205232 kb
Host smart-e418addd-e39e-4bad-9115-99abc9c728fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1734107573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1734107573
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2484897226
Short name T293
Test name
Test status
Simulation time 70097060 ps
CPU time 0.67 seconds
Started Jun 06 02:20:08 PM PDT 24
Finished Jun 06 02:20:12 PM PDT 24
Peak memory 204916 kb
Host smart-f4e12cb6-ce40-4d03-98c9-3fcd4e91b180
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2484897226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2484897226
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.282384419
Short name T2109
Test name
Test status
Simulation time 79844087 ps
CPU time 1 seconds
Started Jun 06 02:20:28 PM PDT 24
Finished Jun 06 02:20:30 PM PDT 24
Peak memory 205256 kb
Host smart-2d687a8f-0296-4e16-9a30-c8ca0fc27f65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=282384419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.282384419
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3173275022
Short name T2073
Test name
Test status
Simulation time 67522350 ps
CPU time 1.68 seconds
Started Jun 06 02:20:19 PM PDT 24
Finished Jun 06 02:20:22 PM PDT 24
Peak memory 205268 kb
Host smart-efe18579-b7c8-47fe-b6d4-705a626b142f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3173275022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3173275022
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3733680740
Short name T2060
Test name
Test status
Simulation time 118098818 ps
CPU time 2.82 seconds
Started Jun 06 02:20:31 PM PDT 24
Finished Jun 06 02:20:35 PM PDT 24
Peak memory 213460 kb
Host smart-ffbea15f-531a-41cc-a1e3-7d338349d4c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733680740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.3733680740
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2526131044
Short name T211
Test name
Test status
Simulation time 62668656 ps
CPU time 0.81 seconds
Started Jun 06 02:20:11 PM PDT 24
Finished Jun 06 02:20:13 PM PDT 24
Peak memory 205216 kb
Host smart-2d106b98-383f-48d2-aeee-5f164e1aec8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2526131044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2526131044
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.4257419573
Short name T2119
Test name
Test status
Simulation time 95431190 ps
CPU time 0.73 seconds
Started Jun 06 02:20:13 PM PDT 24
Finished Jun 06 02:20:15 PM PDT 24
Peak memory 204972 kb
Host smart-25e32a69-7988-423f-9bae-6452b3d88b1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4257419573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.4257419573
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1480060016
Short name T260
Test name
Test status
Simulation time 135938907 ps
CPU time 1.15 seconds
Started Jun 06 02:20:11 PM PDT 24
Finished Jun 06 02:20:14 PM PDT 24
Peak memory 205200 kb
Host smart-4af52a41-2574-4ab3-a27f-12e16ce4d1d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1480060016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1480060016
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.380886902
Short name T2066
Test name
Test status
Simulation time 78957945 ps
CPU time 1.75 seconds
Started Jun 06 02:20:28 PM PDT 24
Finished Jun 06 02:20:31 PM PDT 24
Peak memory 205252 kb
Host smart-b6177b64-c055-41e0-85ce-4620fc5fe23e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=380886902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.380886902
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2357647735
Short name T296
Test name
Test status
Simulation time 2403363566 ps
CPU time 7.07 seconds
Started Jun 06 02:20:06 PM PDT 24
Finished Jun 06 02:20:15 PM PDT 24
Peak memory 205272 kb
Host smart-ab75313d-4db1-4dd3-b517-b3b44908048c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2357647735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.2357647735
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3117717681
Short name T2047
Test name
Test status
Simulation time 125940498 ps
CPU time 1.03 seconds
Started Jun 06 02:20:21 PM PDT 24
Finished Jun 06 02:20:24 PM PDT 24
Peak memory 204976 kb
Host smart-cb9ab520-01f2-4e80-abfb-f9e1d550c783
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3117717681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3117717681
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3478914463
Short name T265
Test name
Test status
Simulation time 112738063 ps
CPU time 1.13 seconds
Started Jun 06 02:20:13 PM PDT 24
Finished Jun 06 02:20:15 PM PDT 24
Peak memory 205100 kb
Host smart-72cd2f59-5a91-414a-a67a-613ac51a5c00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3478914463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.3478914463
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3886067276
Short name T227
Test name
Test status
Simulation time 150867056 ps
CPU time 1.7 seconds
Started Jun 06 02:20:19 PM PDT 24
Finished Jun 06 02:20:21 PM PDT 24
Peak memory 205228 kb
Host smart-1e20c42f-57d2-42a5-8eb9-2d2459f10557
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3886067276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3886067276
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.949392818
Short name T298
Test name
Test status
Simulation time 1780868274 ps
CPU time 7.33 seconds
Started Jun 06 02:20:13 PM PDT 24
Finished Jun 06 02:20:22 PM PDT 24
Peak memory 205216 kb
Host smart-c16cb599-ebcd-4abf-b6c5-f3b10aa22d1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=949392818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.949392818
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.869392673
Short name T226
Test name
Test status
Simulation time 66911685 ps
CPU time 1.3 seconds
Started Jun 06 02:20:18 PM PDT 24
Finished Jun 06 02:20:20 PM PDT 24
Peak memory 215100 kb
Host smart-be38beaf-4a5e-4ebe-9da4-83b07362e865
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869392673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.869392673
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.4048060444
Short name T258
Test name
Test status
Simulation time 105502324 ps
CPU time 1.1 seconds
Started Jun 06 02:20:23 PM PDT 24
Finished Jun 06 02:20:25 PM PDT 24
Peak memory 205240 kb
Host smart-ba628142-2341-4aec-a67a-b32f3d813374
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4048060444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.4048060444
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2000694860
Short name T2055
Test name
Test status
Simulation time 80918090 ps
CPU time 0.79 seconds
Started Jun 06 02:20:14 PM PDT 24
Finished Jun 06 02:20:16 PM PDT 24
Peak memory 204972 kb
Host smart-f36906ba-d4ca-4881-bd0c-09a2cd8cd4c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2000694860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2000694860
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.4181183287
Short name T261
Test name
Test status
Simulation time 169476682 ps
CPU time 1.66 seconds
Started Jun 06 02:20:16 PM PDT 24
Finished Jun 06 02:20:19 PM PDT 24
Peak memory 205192 kb
Host smart-0ca63d8a-19d6-445d-99ed-d23345b6eb70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4181183287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.4181183287
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3897198794
Short name T210
Test name
Test status
Simulation time 198884897 ps
CPU time 1.95 seconds
Started Jun 06 02:20:11 PM PDT 24
Finished Jun 06 02:20:15 PM PDT 24
Peak memory 205412 kb
Host smart-4ae037b5-ed3b-4367-bb90-204f605dd5b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3897198794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3897198794
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2211381138
Short name T295
Test name
Test status
Simulation time 1728037425 ps
CPU time 6.08 seconds
Started Jun 06 02:20:19 PM PDT 24
Finished Jun 06 02:20:26 PM PDT 24
Peak memory 205256 kb
Host smart-aa3adf07-c3ac-4d37-aba0-3b5d0bee3aee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2211381138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2211381138
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3443643570
Short name T234
Test name
Test status
Simulation time 87979929 ps
CPU time 1.3 seconds
Started Jun 06 02:20:20 PM PDT 24
Finished Jun 06 02:20:22 PM PDT 24
Peak memory 213408 kb
Host smart-8b70267a-d932-4506-9e7f-bb36d1221851
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443643570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.3443643570
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2452357330
Short name T2099
Test name
Test status
Simulation time 93785592 ps
CPU time 1 seconds
Started Jun 06 02:20:08 PM PDT 24
Finished Jun 06 02:20:12 PM PDT 24
Peak memory 205168 kb
Host smart-8860cabf-ce47-4c37-9a42-2ac73926bbfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2452357330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2452357330
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.318713860
Short name T286
Test name
Test status
Simulation time 90153658 ps
CPU time 0.71 seconds
Started Jun 06 02:20:24 PM PDT 24
Finished Jun 06 02:20:26 PM PDT 24
Peak memory 204952 kb
Host smart-24310185-8e69-4557-8b62-969a15e7cab2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=318713860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.318713860
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3601176
Short name T2090
Test name
Test status
Simulation time 185766743 ps
CPU time 1.81 seconds
Started Jun 06 02:20:16 PM PDT 24
Finished Jun 06 02:20:19 PM PDT 24
Peak memory 205164 kb
Host smart-eecc6513-b67d-44d5-b6e0-b6d131a96ac5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3601176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3601176
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3949926245
Short name T2071
Test name
Test status
Simulation time 360369040 ps
CPU time 3.4 seconds
Started Jun 06 02:20:23 PM PDT 24
Finished Jun 06 02:20:27 PM PDT 24
Peak memory 221120 kb
Host smart-6a97b337-23b3-4c9d-8b7e-1eb252d3f041
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3949926245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3949926245
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3013117562
Short name T2114
Test name
Test status
Simulation time 543692900 ps
CPU time 4.03 seconds
Started Jun 06 02:20:18 PM PDT 24
Finished Jun 06 02:20:23 PM PDT 24
Peak memory 205160 kb
Host smart-64b2b1c7-794e-4b3a-b8e8-89e2b659c040
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3013117562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3013117562
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1893030978
Short name T230
Test name
Test status
Simulation time 90408477 ps
CPU time 2.05 seconds
Started Jun 06 02:20:15 PM PDT 24
Finished Jun 06 02:20:18 PM PDT 24
Peak memory 213372 kb
Host smart-705a26ca-c157-4a69-a499-7c9827484346
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893030978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1893030978
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1066307666
Short name T254
Test name
Test status
Simulation time 50027519 ps
CPU time 0.97 seconds
Started Jun 06 02:20:16 PM PDT 24
Finished Jun 06 02:20:18 PM PDT 24
Peak memory 205224 kb
Host smart-3661f129-68ac-450d-b1ff-ef0e31c6adbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1066307666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1066307666
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3609910701
Short name T2074
Test name
Test status
Simulation time 57959967 ps
CPU time 0.66 seconds
Started Jun 06 02:20:23 PM PDT 24
Finished Jun 06 02:20:25 PM PDT 24
Peak memory 204932 kb
Host smart-d3969a17-dd4e-427b-bcdb-52d279895e0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3609910701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.3609910701
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.587991190
Short name T264
Test name
Test status
Simulation time 48397731 ps
CPU time 0.93 seconds
Started Jun 06 02:20:11 PM PDT 24
Finished Jun 06 02:20:14 PM PDT 24
Peak memory 205112 kb
Host smart-f45a2edd-9ee0-4536-a128-f945fc9d8a14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=587991190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.587991190
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2031205044
Short name T194
Test name
Test status
Simulation time 186353358 ps
CPU time 2.32 seconds
Started Jun 06 02:20:18 PM PDT 24
Finished Jun 06 02:20:21 PM PDT 24
Peak memory 205348 kb
Host smart-1422252e-9054-48fe-b8d6-3f574f2f9cec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2031205044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2031205044
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3483129163
Short name T233
Test name
Test status
Simulation time 470460115 ps
CPU time 4.38 seconds
Started Jun 06 02:20:16 PM PDT 24
Finished Jun 06 02:20:21 PM PDT 24
Peak memory 205136 kb
Host smart-f80f3479-cbec-4853-8f14-506e5cfe45e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3483129163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3483129163
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1439550847
Short name T214
Test name
Test status
Simulation time 99721817 ps
CPU time 1.81 seconds
Started Jun 06 02:20:24 PM PDT 24
Finished Jun 06 02:20:27 PM PDT 24
Peak memory 221592 kb
Host smart-6dd04d51-7f83-4a12-b71d-b4d1e6046c3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439550847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.1439550847
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2783916588
Short name T262
Test name
Test status
Simulation time 80801380 ps
CPU time 0.95 seconds
Started Jun 06 02:20:12 PM PDT 24
Finished Jun 06 02:20:14 PM PDT 24
Peak memory 205192 kb
Host smart-fb4779ff-0eb1-4c69-b51a-3c02db950ac4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2783916588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2783916588
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2830922685
Short name T105
Test name
Test status
Simulation time 38689193 ps
CPU time 0.7 seconds
Started Jun 06 02:20:24 PM PDT 24
Finished Jun 06 02:20:26 PM PDT 24
Peak memory 204888 kb
Host smart-63b5d366-3ce1-45ef-acaa-8d7c84038827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2830922685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.2830922685
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3772505874
Short name T2039
Test name
Test status
Simulation time 112362764 ps
CPU time 1.06 seconds
Started Jun 06 02:20:18 PM PDT 24
Finished Jun 06 02:20:21 PM PDT 24
Peak memory 205216 kb
Host smart-ca8db1cf-ee28-46d4-b1ba-d1c9fe5dc9ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3772505874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3772505874
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2725950030
Short name T2088
Test name
Test status
Simulation time 294835847 ps
CPU time 3.58 seconds
Started Jun 06 02:20:05 PM PDT 24
Finished Jun 06 02:20:11 PM PDT 24
Peak memory 214400 kb
Host smart-5f803f19-fe87-4343-b563-534cbae35862
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2725950030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.2725950030
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1787456385
Short name T235
Test name
Test status
Simulation time 571881710 ps
CPU time 4.1 seconds
Started Jun 06 02:20:17 PM PDT 24
Finished Jun 06 02:20:22 PM PDT 24
Peak memory 205272 kb
Host smart-9e647f4b-4ed5-4696-895c-1ea8fc60159d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1787456385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1787456385
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.626316273
Short name T2062
Test name
Test status
Simulation time 170282954 ps
CPU time 1.88 seconds
Started Jun 06 02:20:20 PM PDT 24
Finished Jun 06 02:20:22 PM PDT 24
Peak memory 217472 kb
Host smart-cf5fab0a-060a-4953-bf4d-0de25c906e79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626316273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbde
v_csr_mem_rw_with_rand_reset.626316273
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1754639152
Short name T257
Test name
Test status
Simulation time 111094171 ps
CPU time 1.08 seconds
Started Jun 06 02:20:22 PM PDT 24
Finished Jun 06 02:20:25 PM PDT 24
Peak memory 205264 kb
Host smart-103a520f-54b7-47d9-a194-176eb6423f39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1754639152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1754639152
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2389685341
Short name T294
Test name
Test status
Simulation time 97745055 ps
CPU time 0.82 seconds
Started Jun 06 02:20:33 PM PDT 24
Finished Jun 06 02:20:34 PM PDT 24
Peak memory 204928 kb
Host smart-384d93a2-64f7-4f52-a589-ce131f41992e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2389685341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2389685341
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2896348348
Short name T263
Test name
Test status
Simulation time 226018674 ps
CPU time 1.8 seconds
Started Jun 06 02:20:19 PM PDT 24
Finished Jun 06 02:20:22 PM PDT 24
Peak memory 205132 kb
Host smart-2822eeae-b101-456f-b2a0-7a615bdaed1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2896348348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2896348348
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.914161852
Short name T2083
Test name
Test status
Simulation time 162746024 ps
CPU time 2 seconds
Started Jun 06 02:20:12 PM PDT 24
Finished Jun 06 02:20:15 PM PDT 24
Peak memory 205188 kb
Host smart-ee05d52a-d36f-4bd8-a7ac-348a9ce88dce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=914161852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.914161852
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.4268924560
Short name T2105
Test name
Test status
Simulation time 1435715369 ps
CPU time 5.25 seconds
Started Jun 06 02:20:19 PM PDT 24
Finished Jun 06 02:20:25 PM PDT 24
Peak memory 205176 kb
Host smart-3297bd29-78fb-4087-8151-5f1c3555d664
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4268924560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.4268924560
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3325764227
Short name T2112
Test name
Test status
Simulation time 366793320 ps
CPU time 3.63 seconds
Started Jun 06 02:19:59 PM PDT 24
Finished Jun 06 02:20:04 PM PDT 24
Peak memory 205164 kb
Host smart-e524959d-b57e-4eee-9c23-4365f5a9ead5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3325764227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3325764227
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2225782121
Short name T196
Test name
Test status
Simulation time 2289577039 ps
CPU time 13.41 seconds
Started Jun 06 02:19:52 PM PDT 24
Finished Jun 06 02:20:07 PM PDT 24
Peak memory 205516 kb
Host smart-76ce12f0-e5c8-4114-b669-6400a98da66c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2225782121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.2225782121
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2978188842
Short name T2132
Test name
Test status
Simulation time 141503586 ps
CPU time 1.01 seconds
Started Jun 06 02:20:00 PM PDT 24
Finished Jun 06 02:20:02 PM PDT 24
Peak memory 204920 kb
Host smart-96824439-b9f1-44d9-9471-f808be23b99c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2978188842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2978188842
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.880405601
Short name T2069
Test name
Test status
Simulation time 61686265 ps
CPU time 1.58 seconds
Started Jun 06 02:19:58 PM PDT 24
Finished Jun 06 02:20:01 PM PDT 24
Peak memory 213420 kb
Host smart-92266a10-0da5-4831-970f-0fc5af6e6daf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880405601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev
_csr_mem_rw_with_rand_reset.880405601
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1793169815
Short name T2130
Test name
Test status
Simulation time 38297932 ps
CPU time 0.67 seconds
Started Jun 06 02:20:06 PM PDT 24
Finished Jun 06 02:20:09 PM PDT 24
Peak memory 204952 kb
Host smart-6b9253d6-0ccf-4032-9a4c-b7e00aa93d92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1793169815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.1793169815
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4110398289
Short name T255
Test name
Test status
Simulation time 52008216 ps
CPU time 1.34 seconds
Started Jun 06 02:19:50 PM PDT 24
Finished Jun 06 02:19:53 PM PDT 24
Peak memory 213384 kb
Host smart-44135269-943a-4b23-80d0-8f5f82ffb13c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4110398289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.4110398289
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.151303785
Short name T2036
Test name
Test status
Simulation time 166959606 ps
CPU time 4.1 seconds
Started Jun 06 02:20:01 PM PDT 24
Finished Jun 06 02:20:06 PM PDT 24
Peak memory 205128 kb
Host smart-31d8918a-5f05-4f56-8cbf-79c167624bcc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=151303785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.151303785
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.250468216
Short name T2118
Test name
Test status
Simulation time 123824775 ps
CPU time 1.21 seconds
Started Jun 06 02:20:02 PM PDT 24
Finished Jun 06 02:20:04 PM PDT 24
Peak memory 205180 kb
Host smart-62bd5007-070f-46c0-a053-f85ae7426edc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=250468216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.250468216
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2342793374
Short name T231
Test name
Test status
Simulation time 137577842 ps
CPU time 2.84 seconds
Started Jun 06 02:20:01 PM PDT 24
Finished Jun 06 02:20:05 PM PDT 24
Peak memory 221100 kb
Host smart-bbb8a852-04f5-4510-89a8-449a706abc59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2342793374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2342793374
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2280003654
Short name T276
Test name
Test status
Simulation time 1443724852 ps
CPU time 5.86 seconds
Started Jun 06 02:19:57 PM PDT 24
Finished Jun 06 02:20:04 PM PDT 24
Peak memory 205204 kb
Host smart-b7738fdd-83f4-4584-b19b-9b588460d5f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2280003654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2280003654
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2979164068
Short name T2131
Test name
Test status
Simulation time 44614791 ps
CPU time 0.72 seconds
Started Jun 06 02:20:28 PM PDT 24
Finished Jun 06 02:20:30 PM PDT 24
Peak memory 204944 kb
Host smart-4be3fcff-b837-4764-a7fa-73671754d5ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2979164068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2979164068
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.4258865948
Short name T2107
Test name
Test status
Simulation time 53278494 ps
CPU time 0.68 seconds
Started Jun 06 02:20:20 PM PDT 24
Finished Jun 06 02:20:22 PM PDT 24
Peak memory 204980 kb
Host smart-a8f244ff-99f3-45de-ac11-1df91b42e2d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4258865948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.4258865948
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.26878331
Short name T284
Test name
Test status
Simulation time 39132443 ps
CPU time 0.66 seconds
Started Jun 06 02:20:23 PM PDT 24
Finished Jun 06 02:20:25 PM PDT 24
Peak memory 204928 kb
Host smart-a19e6765-d6d8-4f5a-a96b-0504a07d432d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=26878331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.26878331
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.213920097
Short name T2106
Test name
Test status
Simulation time 53783557 ps
CPU time 0.69 seconds
Started Jun 06 02:20:20 PM PDT 24
Finished Jun 06 02:20:21 PM PDT 24
Peak memory 204932 kb
Host smart-cb6e963e-0267-4cec-bdf6-341bf23a7627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=213920097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.213920097
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.4236193708
Short name T291
Test name
Test status
Simulation time 41573516 ps
CPU time 0.68 seconds
Started Jun 06 02:20:12 PM PDT 24
Finished Jun 06 02:20:14 PM PDT 24
Peak memory 204972 kb
Host smart-a84b76ba-e9e4-40cb-828b-1d5b81cabfc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4236193708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.4236193708
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2073761857
Short name T278
Test name
Test status
Simulation time 62492264 ps
CPU time 0.72 seconds
Started Jun 06 02:20:24 PM PDT 24
Finished Jun 06 02:20:26 PM PDT 24
Peak memory 204944 kb
Host smart-a57ba0e2-109d-4651-9101-f22daf682715
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2073761857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2073761857
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.4232623611
Short name T2063
Test name
Test status
Simulation time 36010102 ps
CPU time 0.65 seconds
Started Jun 06 02:20:30 PM PDT 24
Finished Jun 06 02:20:31 PM PDT 24
Peak memory 204980 kb
Host smart-4d9bbff3-cb39-4af4-bb03-e38ced0dd571
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4232623611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.4232623611
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3693111259
Short name T2115
Test name
Test status
Simulation time 42128107 ps
CPU time 0.66 seconds
Started Jun 06 02:20:19 PM PDT 24
Finished Jun 06 02:20:21 PM PDT 24
Peak memory 204944 kb
Host smart-ba4250bb-d1f2-445b-a65f-4b947b891f4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3693111259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3693111259
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3275581269
Short name T2048
Test name
Test status
Simulation time 51120959 ps
CPU time 0.7 seconds
Started Jun 06 02:20:31 PM PDT 24
Finished Jun 06 02:20:33 PM PDT 24
Peak memory 204944 kb
Host smart-02da6b39-2587-4ac3-b26c-06264a50c767
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3275581269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3275581269
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1748133423
Short name T2103
Test name
Test status
Simulation time 51828316 ps
CPU time 0.69 seconds
Started Jun 06 02:20:42 PM PDT 24
Finished Jun 06 02:20:44 PM PDT 24
Peak memory 204896 kb
Host smart-2007a691-028f-41f5-af89-09934f46affd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1748133423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1748133423
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.4075658217
Short name T2057
Test name
Test status
Simulation time 158806371 ps
CPU time 3.13 seconds
Started Jun 06 02:20:01 PM PDT 24
Finished Jun 06 02:20:05 PM PDT 24
Peak memory 205248 kb
Host smart-3a39d343-c5c6-4213-90dd-1e70f409fe3b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4075658217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.4075658217
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2987364514
Short name T2123
Test name
Test status
Simulation time 318079744 ps
CPU time 4.36 seconds
Started Jun 06 02:20:03 PM PDT 24
Finished Jun 06 02:20:10 PM PDT 24
Peak memory 205084 kb
Host smart-e31554bf-3998-4f38-aca7-7a88b95f755e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2987364514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2987364514
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2136891449
Short name T2113
Test name
Test status
Simulation time 84223015 ps
CPU time 0.94 seconds
Started Jun 06 02:19:58 PM PDT 24
Finished Jun 06 02:20:00 PM PDT 24
Peak memory 204944 kb
Host smart-901efdf8-26d6-44b0-ad61-9217a8780f58
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2136891449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2136891449
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.880650205
Short name T2121
Test name
Test status
Simulation time 95062939 ps
CPU time 1.97 seconds
Started Jun 06 02:20:04 PM PDT 24
Finished Jun 06 02:20:08 PM PDT 24
Peak memory 213392 kb
Host smart-70aad844-6eea-4550-906e-e249fe2e8c0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880650205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev
_csr_mem_rw_with_rand_reset.880650205
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2001330375
Short name T2068
Test name
Test status
Simulation time 43575389 ps
CPU time 0.76 seconds
Started Jun 06 02:20:21 PM PDT 24
Finished Jun 06 02:20:23 PM PDT 24
Peak memory 204984 kb
Host smart-5acb6331-a174-4fad-80aa-458bab6251e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2001330375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2001330375
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.802006812
Short name T2052
Test name
Test status
Simulation time 55756048 ps
CPU time 0.71 seconds
Started Jun 06 02:20:02 PM PDT 24
Finished Jun 06 02:20:04 PM PDT 24
Peak memory 204952 kb
Host smart-90e51f94-d9f3-44cb-871d-8a720551f0a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=802006812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.802006812
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.4098749938
Short name T259
Test name
Test status
Simulation time 228861206 ps
CPU time 2.3 seconds
Started Jun 06 02:20:04 PM PDT 24
Finished Jun 06 02:20:09 PM PDT 24
Peak memory 213380 kb
Host smart-09b2570b-b6be-4c47-a98e-317da7accd07
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4098749938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.4098749938
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.811370648
Short name T2033
Test name
Test status
Simulation time 385628162 ps
CPU time 2.71 seconds
Started Jun 06 02:19:59 PM PDT 24
Finished Jun 06 02:20:02 PM PDT 24
Peak memory 205176 kb
Host smart-fa865f01-cb87-4327-8f59-05cf2735d875
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=811370648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.811370648
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4251054537
Short name T2037
Test name
Test status
Simulation time 59738461 ps
CPU time 1.07 seconds
Started Jun 06 02:20:15 PM PDT 24
Finished Jun 06 02:20:17 PM PDT 24
Peak memory 205176 kb
Host smart-2f7f5463-6127-4220-9f95-65722869f175
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4251054537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.4251054537
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.181869116
Short name T2129
Test name
Test status
Simulation time 418718250 ps
CPU time 2.88 seconds
Started Jun 06 02:20:04 PM PDT 24
Finished Jun 06 02:20:09 PM PDT 24
Peak memory 205188 kb
Host smart-f98334b7-b6d9-459a-a020-efd020b8344a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=181869116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.181869116
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2452542022
Short name T290
Test name
Test status
Simulation time 40320542 ps
CPU time 0.65 seconds
Started Jun 06 02:20:22 PM PDT 24
Finished Jun 06 02:20:28 PM PDT 24
Peak memory 204960 kb
Host smart-9bebc0a8-2e36-46ad-8f6f-c8b731ff9810
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2452542022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2452542022
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.44935910
Short name T292
Test name
Test status
Simulation time 36515032 ps
CPU time 0.66 seconds
Started Jun 06 02:20:34 PM PDT 24
Finished Jun 06 02:20:35 PM PDT 24
Peak memory 204916 kb
Host smart-73fd2e9f-24c4-4bbd-b5f7-cd9057b18e31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=44935910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.44935910
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.47884105
Short name T2058
Test name
Test status
Simulation time 36985899 ps
CPU time 0.65 seconds
Started Jun 06 02:20:29 PM PDT 24
Finished Jun 06 02:20:30 PM PDT 24
Peak memory 204904 kb
Host smart-ebfcd3fb-961d-4047-9595-0afe154e859d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=47884105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.47884105
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1448995907
Short name T2124
Test name
Test status
Simulation time 63935888 ps
CPU time 0.67 seconds
Started Jun 06 02:20:22 PM PDT 24
Finished Jun 06 02:20:24 PM PDT 24
Peak memory 204956 kb
Host smart-ef6501a6-050f-48cc-8f78-ddc9f05065a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1448995907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1448995907
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3323164990
Short name T280
Test name
Test status
Simulation time 67267057 ps
CPU time 0.74 seconds
Started Jun 06 02:20:27 PM PDT 24
Finished Jun 06 02:20:29 PM PDT 24
Peak memory 204960 kb
Host smart-d21f7084-b2fc-4bbb-bd9a-c9d27e5449c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3323164990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3323164990
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.804343081
Short name T2044
Test name
Test status
Simulation time 59958195 ps
CPU time 0.66 seconds
Started Jun 06 02:20:31 PM PDT 24
Finished Jun 06 02:20:32 PM PDT 24
Peak memory 204928 kb
Host smart-80ee063f-696d-4b90-b82a-c719292d0b3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=804343081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.804343081
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.814204355
Short name T198
Test name
Test status
Simulation time 49617975 ps
CPU time 0.67 seconds
Started Jun 06 02:20:42 PM PDT 24
Finished Jun 06 02:20:44 PM PDT 24
Peak memory 204932 kb
Host smart-6e2e681f-4547-42bc-8489-7cd57ca7c2c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=814204355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.814204355
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2647705319
Short name T2089
Test name
Test status
Simulation time 42913169 ps
CPU time 0.71 seconds
Started Jun 06 02:20:24 PM PDT 24
Finished Jun 06 02:20:26 PM PDT 24
Peak memory 204972 kb
Host smart-ad9078f2-699b-4980-860f-c3dbf95f6830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2647705319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2647705319
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.24867473
Short name T285
Test name
Test status
Simulation time 40634753 ps
CPU time 0.67 seconds
Started Jun 06 02:20:29 PM PDT 24
Finished Jun 06 02:20:31 PM PDT 24
Peak memory 204908 kb
Host smart-600bb675-fc48-46ea-815f-4fd091042537
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=24867473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.24867473
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3062717048
Short name T2127
Test name
Test status
Simulation time 69945279 ps
CPU time 0.71 seconds
Started Jun 06 02:20:22 PM PDT 24
Finished Jun 06 02:20:24 PM PDT 24
Peak memory 204972 kb
Host smart-b0a4e9fe-4040-4576-ad6c-56d16bbd6760
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3062717048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3062717048
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.110118830
Short name T2120
Test name
Test status
Simulation time 298683140 ps
CPU time 3.29 seconds
Started Jun 06 02:20:06 PM PDT 24
Finished Jun 06 02:20:11 PM PDT 24
Peak memory 205148 kb
Host smart-c3d40852-8c1b-401f-a10c-01a529e5a04f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=110118830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.110118830
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1409822789
Short name T250
Test name
Test status
Simulation time 675732515 ps
CPU time 8.38 seconds
Started Jun 06 02:20:01 PM PDT 24
Finished Jun 06 02:20:10 PM PDT 24
Peak memory 205192 kb
Host smart-934e1947-c519-4143-8ea1-1b5d65b0cc08
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1409822789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1409822789
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.868168332
Short name T2095
Test name
Test status
Simulation time 108439730 ps
CPU time 0.91 seconds
Started Jun 06 02:20:12 PM PDT 24
Finished Jun 06 02:20:15 PM PDT 24
Peak memory 204912 kb
Host smart-1b649670-c74a-4066-b707-8e28ccee29b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=868168332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.868168332
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2902370917
Short name T2050
Test name
Test status
Simulation time 88302531 ps
CPU time 2.09 seconds
Started Jun 06 02:20:03 PM PDT 24
Finished Jun 06 02:20:06 PM PDT 24
Peak memory 213372 kb
Host smart-f0ce17f4-349c-4731-876a-52a705b11695
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902370917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.2902370917
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1591202782
Short name T256
Test name
Test status
Simulation time 74663960 ps
CPU time 1.07 seconds
Started Jun 06 02:20:08 PM PDT 24
Finished Jun 06 02:20:12 PM PDT 24
Peak memory 205252 kb
Host smart-b44bf128-7e1b-412e-a5c1-f76bf3e6c9df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1591202782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1591202782
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.430308984
Short name T2086
Test name
Test status
Simulation time 47351214 ps
CPU time 0.76 seconds
Started Jun 06 02:20:07 PM PDT 24
Finished Jun 06 02:20:11 PM PDT 24
Peak memory 204932 kb
Host smart-cd7cdd70-c03c-4c19-bbb5-2b3974eccd00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=430308984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.430308984
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.788102407
Short name T2126
Test name
Test status
Simulation time 245006085 ps
CPU time 2.46 seconds
Started Jun 06 02:20:09 PM PDT 24
Finished Jun 06 02:20:14 PM PDT 24
Peak memory 213424 kb
Host smart-89e1b8a9-2270-4c46-be1b-98aad875ca2d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=788102407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.788102407
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1830580019
Short name T2034
Test name
Test status
Simulation time 377957436 ps
CPU time 2.73 seconds
Started Jun 06 02:20:12 PM PDT 24
Finished Jun 06 02:20:16 PM PDT 24
Peak memory 205208 kb
Host smart-32077381-0bd1-425e-a346-cf9c612567ec
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1830580019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1830580019
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.755078477
Short name T197
Test name
Test status
Simulation time 244534186 ps
CPU time 1.86 seconds
Started Jun 06 02:20:08 PM PDT 24
Finished Jun 06 02:20:13 PM PDT 24
Peak memory 205184 kb
Host smart-ca88cd91-dea9-42bc-9d35-c47abd889d23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=755078477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.755078477
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.670899581
Short name T224
Test name
Test status
Simulation time 112700613 ps
CPU time 2.6 seconds
Started Jun 06 02:20:18 PM PDT 24
Finished Jun 06 02:20:21 PM PDT 24
Peak memory 220848 kb
Host smart-5edffd30-9730-4afc-bea7-13ce1bcdcd16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=670899581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.670899581
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.4123713933
Short name T217
Test name
Test status
Simulation time 510481769 ps
CPU time 4.03 seconds
Started Jun 06 02:20:20 PM PDT 24
Finished Jun 06 02:20:25 PM PDT 24
Peak memory 205208 kb
Host smart-18df8b49-e8bd-443c-95c7-db3131a13f86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4123713933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.4123713933
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3219067577
Short name T2061
Test name
Test status
Simulation time 41609064 ps
CPU time 0.68 seconds
Started Jun 06 02:20:27 PM PDT 24
Finished Jun 06 02:20:29 PM PDT 24
Peak memory 204916 kb
Host smart-5e5b7b40-04b8-4813-9aef-03a932d259a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3219067577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3219067577
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3672401635
Short name T282
Test name
Test status
Simulation time 95765043 ps
CPU time 0.74 seconds
Started Jun 06 02:20:27 PM PDT 24
Finished Jun 06 02:20:29 PM PDT 24
Peak memory 204960 kb
Host smart-2290e89f-af51-4961-87fa-a7c19237601a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3672401635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.3672401635
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3220562129
Short name T2122
Test name
Test status
Simulation time 44753186 ps
CPU time 0.67 seconds
Started Jun 06 02:20:41 PM PDT 24
Finished Jun 06 02:20:43 PM PDT 24
Peak memory 204936 kb
Host smart-11d72815-54d3-4fd1-a338-07fb4f41d147
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3220562129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.3220562129
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3548710166
Short name T104
Test name
Test status
Simulation time 38175259 ps
CPU time 0.7 seconds
Started Jun 06 02:20:49 PM PDT 24
Finished Jun 06 02:20:50 PM PDT 24
Peak memory 204964 kb
Host smart-eaa0dcf5-affd-45e4-9ea4-549f34ac3cbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3548710166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3548710166
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1847661788
Short name T2064
Test name
Test status
Simulation time 38675944 ps
CPU time 0.7 seconds
Started Jun 06 02:20:21 PM PDT 24
Finished Jun 06 02:20:23 PM PDT 24
Peak memory 204932 kb
Host smart-06bd2612-ac2a-4bc1-bf82-a71b3fe5c643
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1847661788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1847661788
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3445565987
Short name T2098
Test name
Test status
Simulation time 48087767 ps
CPU time 0.64 seconds
Started Jun 06 02:20:35 PM PDT 24
Finished Jun 06 02:20:36 PM PDT 24
Peak memory 204968 kb
Host smart-68b58032-08bd-4fb8-a734-628ae4864279
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3445565987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3445565987
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1209769939
Short name T287
Test name
Test status
Simulation time 38901901 ps
CPU time 0.66 seconds
Started Jun 06 02:20:45 PM PDT 24
Finished Jun 06 02:20:46 PM PDT 24
Peak memory 204932 kb
Host smart-b310f4fd-9bb5-410f-939b-06efa62102b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1209769939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1209769939
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.881516113
Short name T2108
Test name
Test status
Simulation time 48985030 ps
CPU time 0.66 seconds
Started Jun 06 02:20:36 PM PDT 24
Finished Jun 06 02:20:38 PM PDT 24
Peak memory 204880 kb
Host smart-de9eee38-9ab3-412a-b9e7-442ce9da36e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=881516113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.881516113
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.368909286
Short name T2092
Test name
Test status
Simulation time 98958680 ps
CPU time 1.05 seconds
Started Jun 06 02:20:06 PM PDT 24
Finished Jun 06 02:20:09 PM PDT 24
Peak memory 205196 kb
Host smart-6308cd01-93ff-4da8-8b8f-b74c5d23ead9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=368909286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.368909286
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2383071209
Short name T289
Test name
Test status
Simulation time 35784697 ps
CPU time 0.65 seconds
Started Jun 06 02:20:04 PM PDT 24
Finished Jun 06 02:20:07 PM PDT 24
Peak memory 204916 kb
Host smart-dbedc01f-4ad3-4a1d-b387-6c7111ac72a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2383071209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2383071209
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.636752215
Short name T2067
Test name
Test status
Simulation time 143301348 ps
CPU time 1.43 seconds
Started Jun 06 02:20:06 PM PDT 24
Finished Jun 06 02:20:10 PM PDT 24
Peak memory 205184 kb
Host smart-1e5d53fe-1676-4c9d-99d3-089b5befe24c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=636752215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.636752215
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2861167791
Short name T275
Test name
Test status
Simulation time 821802651 ps
CPU time 5.2 seconds
Started Jun 06 02:20:19 PM PDT 24
Finished Jun 06 02:20:25 PM PDT 24
Peak memory 205188 kb
Host smart-ebcfc75c-fb2f-4d4c-b113-8848357bc64c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2861167791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2861167791
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.603342562
Short name T2094
Test name
Test status
Simulation time 194045197 ps
CPU time 2.09 seconds
Started Jun 06 02:20:05 PM PDT 24
Finished Jun 06 02:20:10 PM PDT 24
Peak memory 213384 kb
Host smart-4b5a4ece-01cb-4eda-8481-01e7500e5c96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603342562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev
_csr_mem_rw_with_rand_reset.603342562
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1913699117
Short name T2075
Test name
Test status
Simulation time 79022316 ps
CPU time 1.03 seconds
Started Jun 06 02:20:05 PM PDT 24
Finished Jun 06 02:20:08 PM PDT 24
Peak memory 205232 kb
Host smart-6b37dc13-2d3b-4f0a-9640-0d92330cb14b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1913699117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1913699117
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2484296230
Short name T2078
Test name
Test status
Simulation time 37465285 ps
CPU time 0.65 seconds
Started Jun 06 02:20:00 PM PDT 24
Finished Jun 06 02:20:01 PM PDT 24
Peak memory 204920 kb
Host smart-4b1c8916-7068-459b-901b-f5dbf6f499e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2484296230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2484296230
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2227943346
Short name T2049
Test name
Test status
Simulation time 57279024 ps
CPU time 1.08 seconds
Started Jun 06 02:20:04 PM PDT 24
Finished Jun 06 02:20:08 PM PDT 24
Peak memory 205216 kb
Host smart-8e240599-b04d-4af8-8244-fd973124e71d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2227943346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.2227943346
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3078533856
Short name T2104
Test name
Test status
Simulation time 114580502 ps
CPU time 3.1 seconds
Started Jun 06 02:20:20 PM PDT 24
Finished Jun 06 02:20:24 PM PDT 24
Peak memory 221060 kb
Host smart-d2648744-d73f-43d3-9920-9fcb1a43318b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3078533856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3078533856
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3973346572
Short name T2065
Test name
Test status
Simulation time 1812342822 ps
CPU time 7.19 seconds
Started Jun 06 02:20:00 PM PDT 24
Finished Jun 06 02:20:08 PM PDT 24
Peak memory 205184 kb
Host smart-1009c22d-43a2-4e8b-85e0-d34148e4c01e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3973346572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3973346572
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.675639440
Short name T2096
Test name
Test status
Simulation time 82650452 ps
CPU time 1.92 seconds
Started Jun 06 02:20:02 PM PDT 24
Finished Jun 06 02:20:05 PM PDT 24
Peak memory 213360 kb
Host smart-a8a0c31d-f513-47e9-8ca4-f3c0212e715e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675639440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev
_csr_mem_rw_with_rand_reset.675639440
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.951519673
Short name T246
Test name
Test status
Simulation time 82007139 ps
CPU time 1.02 seconds
Started Jun 06 02:20:03 PM PDT 24
Finished Jun 06 02:20:07 PM PDT 24
Peak memory 205240 kb
Host smart-88281df8-4033-477b-85fc-2a4438c6c73d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=951519673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.951519673
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2444790899
Short name T2042
Test name
Test status
Simulation time 143897523 ps
CPU time 1.35 seconds
Started Jun 06 02:20:09 PM PDT 24
Finished Jun 06 02:20:12 PM PDT 24
Peak memory 205132 kb
Host smart-e9ed386d-66c3-4df0-bbeb-af767dd0a4ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2444790899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2444790899
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2670247268
Short name T2072
Test name
Test status
Simulation time 111493645 ps
CPU time 2.91 seconds
Started Jun 06 02:20:05 PM PDT 24
Finished Jun 06 02:20:11 PM PDT 24
Peak memory 205256 kb
Host smart-77197117-7339-44b4-8938-88e7285a5c78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2670247268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2670247268
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.929834290
Short name T2102
Test name
Test status
Simulation time 111091494 ps
CPU time 1.35 seconds
Started Jun 06 02:20:18 PM PDT 24
Finished Jun 06 02:20:20 PM PDT 24
Peak memory 213448 kb
Host smart-85c7cd4c-fa22-47d1-ae59-e790f4717f07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929834290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev
_csr_mem_rw_with_rand_reset.929834290
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2751427195
Short name T2101
Test name
Test status
Simulation time 42568388 ps
CPU time 0.75 seconds
Started Jun 06 02:20:24 PM PDT 24
Finished Jun 06 02:20:26 PM PDT 24
Peak memory 204956 kb
Host smart-a41b416a-1726-454b-9fd4-0aab846973ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2751427195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2751427195
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2268845451
Short name T283
Test name
Test status
Simulation time 35188898 ps
CPU time 0.67 seconds
Started Jun 06 02:20:21 PM PDT 24
Finished Jun 06 02:20:22 PM PDT 24
Peak memory 204920 kb
Host smart-3be99d10-db15-429b-a76f-83ab69bcf96e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2268845451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2268845451
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.87567077
Short name T2040
Test name
Test status
Simulation time 271337043 ps
CPU time 1.8 seconds
Started Jun 06 02:20:24 PM PDT 24
Finished Jun 06 02:20:27 PM PDT 24
Peak memory 205244 kb
Host smart-7dbdbc12-9140-4fc4-a5f7-fe4edbf5ac17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=87567077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.87567077
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3170559440
Short name T2082
Test name
Test status
Simulation time 204645298 ps
CPU time 2.02 seconds
Started Jun 06 02:20:09 PM PDT 24
Finished Jun 06 02:20:14 PM PDT 24
Peak memory 205228 kb
Host smart-4726436b-fddb-42bb-913d-816166f175c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3170559440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.3170559440
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.212840166
Short name T2051
Test name
Test status
Simulation time 411261412 ps
CPU time 2.79 seconds
Started Jun 06 02:20:10 PM PDT 24
Finished Jun 06 02:20:15 PM PDT 24
Peak memory 205068 kb
Host smart-f8ca19ad-9fbf-4c9f-8f02-f4025557a355
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=212840166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.212840166
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.786795207
Short name T2070
Test name
Test status
Simulation time 181967500 ps
CPU time 1.83 seconds
Started Jun 06 02:20:04 PM PDT 24
Finished Jun 06 02:20:08 PM PDT 24
Peak memory 216960 kb
Host smart-81b9fd2d-2070-4f58-add4-1c50872302ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786795207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev
_csr_mem_rw_with_rand_reset.786795207
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1849344289
Short name T249
Test name
Test status
Simulation time 57202438 ps
CPU time 0.82 seconds
Started Jun 06 02:20:02 PM PDT 24
Finished Jun 06 02:20:04 PM PDT 24
Peak memory 204960 kb
Host smart-a722c87c-a011-4e92-87ec-ab085dd80b0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1849344289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1849344289
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2683308670
Short name T281
Test name
Test status
Simulation time 44569503 ps
CPU time 0.68 seconds
Started Jun 06 02:20:15 PM PDT 24
Finished Jun 06 02:20:17 PM PDT 24
Peak memory 204948 kb
Host smart-fa5e27b7-1dea-42e7-a8df-6d740c8c706d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2683308670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.2683308670
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1976365503
Short name T2097
Test name
Test status
Simulation time 162875348 ps
CPU time 1.69 seconds
Started Jun 06 02:19:57 PM PDT 24
Finished Jun 06 02:20:00 PM PDT 24
Peak memory 205152 kb
Host smart-d2ee54a6-9ab2-4ca7-a8e6-63392f19dbb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1976365503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1976365503
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3683654539
Short name T2116
Test name
Test status
Simulation time 241700054 ps
CPU time 2.87 seconds
Started Jun 06 02:20:08 PM PDT 24
Finished Jun 06 02:20:14 PM PDT 24
Peak memory 221216 kb
Host smart-807a14d7-59b8-45bd-a364-22dcf7b9e057
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3683654539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3683654539
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3747865477
Short name T301
Test name
Test status
Simulation time 409865510 ps
CPU time 2.44 seconds
Started Jun 06 02:20:07 PM PDT 24
Finished Jun 06 02:20:12 PM PDT 24
Peak memory 205188 kb
Host smart-7fc4ffa4-895d-44a3-801e-39426e4c13c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3747865477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3747865477
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.3531814488
Short name T379
Test name
Test status
Simulation time 10147168287 ps
CPU time 13.1 seconds
Started Jun 06 01:44:09 PM PDT 24
Finished Jun 06 01:44:24 PM PDT 24
Peak memory 205688 kb
Host smart-9109d3b5-8253-4a5a-bbec-8586954d8a50
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3531814488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.3531814488
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.4002114177
Short name T1046
Test name
Test status
Simulation time 10073531021 ps
CPU time 14.33 seconds
Started Jun 06 01:44:08 PM PDT 24
Finished Jun 06 01:44:24 PM PDT 24
Peak memory 205704 kb
Host smart-147b19cc-1ae1-4206-910c-daa385773c01
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4002114177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.4002114177
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.3860243127
Short name T1042
Test name
Test status
Simulation time 10127444608 ps
CPU time 13.74 seconds
Started Jun 06 01:44:09 PM PDT 24
Finished Jun 06 01:44:24 PM PDT 24
Peak memory 205708 kb
Host smart-6e1db387-a7b1-4339-8d23-fb2fb9fe5e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38602
43127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.3860243127
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.791744654
Short name T1967
Test name
Test status
Simulation time 14170716107 ps
CPU time 17.62 seconds
Started Jun 06 01:43:48 PM PDT 24
Finished Jun 06 01:44:07 PM PDT 24
Peak memory 205736 kb
Host smart-e00b1537-3c63-4ecf-a01d-e6db00eca35c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=791744654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.791744654
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.1878056986
Short name T665
Test name
Test status
Simulation time 23312695226 ps
CPU time 24.43 seconds
Started Jun 06 01:43:48 PM PDT 24
Finished Jun 06 01:44:13 PM PDT 24
Peak memory 205732 kb
Host smart-bf16590f-0ab3-4a76-8e61-9ce6b255e5d7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1878056986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.1878056986
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.2486543617
Short name T1050
Test name
Test status
Simulation time 10052028890 ps
CPU time 13.3 seconds
Started Jun 06 01:43:45 PM PDT 24
Finished Jun 06 01:43:59 PM PDT 24
Peak memory 205644 kb
Host smart-6b72f9b1-809a-4e79-8326-0cc979b3c5e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24865
43617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.2486543617
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.3262658678
Short name T1312
Test name
Test status
Simulation time 10877388359 ps
CPU time 15.34 seconds
Started Jun 06 01:43:47 PM PDT 24
Finished Jun 06 01:44:03 PM PDT 24
Peak memory 205628 kb
Host smart-35a20390-977b-493c-84bd-2d52e9d09f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32626
58678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.3262658678
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.3980130193
Short name T336
Test name
Test status
Simulation time 10054334201 ps
CPU time 12.93 seconds
Started Jun 06 01:43:58 PM PDT 24
Finished Jun 06 01:44:12 PM PDT 24
Peak memory 205672 kb
Host smart-d7bdc330-8d24-4d44-8393-d91471067777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39801
30193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.3980130193
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.2763274491
Short name T929
Test name
Test status
Simulation time 10055063138 ps
CPU time 14.41 seconds
Started Jun 06 01:43:49 PM PDT 24
Finished Jun 06 01:44:04 PM PDT 24
Peak memory 205876 kb
Host smart-bbdf5425-b925-4331-95ac-152859195736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27632
74491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2763274491
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.2031806568
Short name T421
Test name
Test status
Simulation time 10751353506 ps
CPU time 14.61 seconds
Started Jun 06 01:43:48 PM PDT 24
Finished Jun 06 01:44:03 PM PDT 24
Peak memory 205648 kb
Host smart-b100239f-de1c-4146-9234-87a8c39edee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20318
06568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.2031806568
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.3374595291
Short name T1741
Test name
Test status
Simulation time 10068458204 ps
CPU time 13.75 seconds
Started Jun 06 01:43:48 PM PDT 24
Finished Jun 06 01:44:02 PM PDT 24
Peak memory 205624 kb
Host smart-6d8f05b4-bd56-43c3-be9c-880a37adedb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33745
95291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.3374595291
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1700605167
Short name T742
Test name
Test status
Simulation time 10096953791 ps
CPU time 13.79 seconds
Started Jun 06 01:44:07 PM PDT 24
Finished Jun 06 01:44:22 PM PDT 24
Peak memory 205704 kb
Host smart-4b80c378-70a1-41fc-8613-4dfeb52f2d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17006
05167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1700605167
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.3138290262
Short name T1509
Test name
Test status
Simulation time 10042189980 ps
CPU time 13.84 seconds
Started Jun 06 01:44:08 PM PDT 24
Finished Jun 06 01:44:24 PM PDT 24
Peak memory 205652 kb
Host smart-313701a5-c766-4424-aa18-ff674c9bc34c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31382
90262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.3138290262
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.695634297
Short name T522
Test name
Test status
Simulation time 10080202043 ps
CPU time 13.25 seconds
Started Jun 06 01:44:01 PM PDT 24
Finished Jun 06 01:44:15 PM PDT 24
Peak memory 205664 kb
Host smart-b9516be1-43ed-4fde-bfd8-d5b4bccf2e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69563
4297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.695634297
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.1678085516
Short name T1385
Test name
Test status
Simulation time 10091773564 ps
CPU time 17.6 seconds
Started Jun 06 01:44:00 PM PDT 24
Finished Jun 06 01:44:19 PM PDT 24
Peak memory 205752 kb
Host smart-477725fe-3c09-4954-b26f-b77c4a7bc326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16780
85516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.1678085516
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.2701896982
Short name T1458
Test name
Test status
Simulation time 13253563455 ps
CPU time 16.22 seconds
Started Jun 06 01:43:58 PM PDT 24
Finished Jun 06 01:44:15 PM PDT 24
Peak memory 205760 kb
Host smart-a8c6547a-5c26-4726-ac0e-fd57b8876a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27018
96982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.2701896982
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2740381181
Short name T1761
Test name
Test status
Simulation time 10093957878 ps
CPU time 15.34 seconds
Started Jun 06 01:44:00 PM PDT 24
Finished Jun 06 01:44:17 PM PDT 24
Peak memory 205704 kb
Host smart-a6cd1262-5c71-426e-80da-708d6cb7192f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27403
81181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2740381181
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.3711032716
Short name T1406
Test name
Test status
Simulation time 20312599602 ps
CPU time 298.34 seconds
Started Jun 06 01:43:59 PM PDT 24
Finished Jun 06 01:48:59 PM PDT 24
Peak memory 205668 kb
Host smart-0bfa2966-e647-405c-bbc0-454d9d780105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37110
32716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.3711032716
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1739286828
Short name T1269
Test name
Test status
Simulation time 10058105331 ps
CPU time 13.76 seconds
Started Jun 06 01:43:59 PM PDT 24
Finished Jun 06 01:44:14 PM PDT 24
Peak memory 205772 kb
Host smart-76d7ac73-8710-4c91-8f78-b16e792f8a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17392
86828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1739286828
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.2994961707
Short name T1131
Test name
Test status
Simulation time 10103617049 ps
CPU time 15.94 seconds
Started Jun 06 01:44:01 PM PDT 24
Finished Jun 06 01:44:18 PM PDT 24
Peak memory 205684 kb
Host smart-736fc7a4-74dd-4096-a023-c08a72c3f84d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29949
61707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.2994961707
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.876719744
Short name T426
Test name
Test status
Simulation time 10093755644 ps
CPU time 14.04 seconds
Started Jun 06 01:43:58 PM PDT 24
Finished Jun 06 01:44:13 PM PDT 24
Peak memory 205712 kb
Host smart-106e86f6-9486-41f8-890f-133c82c348d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87671
9744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.876719744
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2791655319
Short name T540
Test name
Test status
Simulation time 10087085568 ps
CPU time 12.86 seconds
Started Jun 06 01:43:57 PM PDT 24
Finished Jun 06 01:44:11 PM PDT 24
Peak memory 205744 kb
Host smart-5add097f-94a7-41ed-9a66-6017839d0865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27916
55319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2791655319
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.443999932
Short name T885
Test name
Test status
Simulation time 10048874434 ps
CPU time 13.13 seconds
Started Jun 06 01:44:10 PM PDT 24
Finished Jun 06 01:44:24 PM PDT 24
Peak memory 205632 kb
Host smart-f050b457-ebb5-4440-9d44-cd6ed32f6826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44399
9932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.443999932
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2906849856
Short name T1767
Test name
Test status
Simulation time 10083636972 ps
CPU time 13.7 seconds
Started Jun 06 01:44:09 PM PDT 24
Finished Jun 06 01:44:24 PM PDT 24
Peak memory 205768 kb
Host smart-f36692b2-af59-4832-a5ff-2a1e536a12ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29068
49856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.2906849856
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.1570143741
Short name T808
Test name
Test status
Simulation time 10062170700 ps
CPU time 14.36 seconds
Started Jun 06 01:44:09 PM PDT 24
Finished Jun 06 01:44:25 PM PDT 24
Peak memory 205572 kb
Host smart-19dc0ca3-011a-497b-8ced-7483be90b41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15701
43741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.1570143741
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.991506853
Short name T176
Test name
Test status
Simulation time 27214730780 ps
CPU time 56.51 seconds
Started Jun 06 01:43:59 PM PDT 24
Finished Jun 06 01:44:57 PM PDT 24
Peak memory 205684 kb
Host smart-028cf2f8-e27b-45f0-82e2-defb46af334f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99150
6853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.991506853
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.841004421
Short name T1151
Test name
Test status
Simulation time 10061802061 ps
CPU time 14.77 seconds
Started Jun 06 01:43:59 PM PDT 24
Finished Jun 06 01:44:15 PM PDT 24
Peak memory 205680 kb
Host smart-135d601b-dfe8-450b-8e30-bfed0d57be7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84100
4421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.841004421
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.635640521
Short name T315
Test name
Test status
Simulation time 10110942231 ps
CPU time 14.79 seconds
Started Jun 06 01:43:58 PM PDT 24
Finished Jun 06 01:44:14 PM PDT 24
Peak memory 205668 kb
Host smart-0b786636-6530-49a7-863e-fd7f50af0b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63564
0521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.635640521
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.3797556291
Short name T48
Test name
Test status
Simulation time 21321227223 ps
CPU time 75.2 seconds
Started Jun 06 01:43:59 PM PDT 24
Finished Jun 06 01:45:16 PM PDT 24
Peak memory 205780 kb
Host smart-cc8a84dc-3b2b-4aec-8b56-0e3674bb3247
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3797556291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.3797556291
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.751128356
Short name T4
Test name
Test status
Simulation time 50246548134 ps
CPU time 381.46 seconds
Started Jun 06 01:43:58 PM PDT 24
Finished Jun 06 01:50:21 PM PDT 24
Peak memory 205744 kb
Host smart-d9bb18be-ff6b-4bc0-9108-2079bc3cdaa5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=751128356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.751128356
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.1724498598
Short name T735
Test name
Test status
Simulation time 10118943773 ps
CPU time 13.22 seconds
Started Jun 06 01:43:59 PM PDT 24
Finished Jun 06 01:44:14 PM PDT 24
Peak memory 205708 kb
Host smart-573841b5-4d2c-4d76-bf45-cba11bd5bd79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17244
98598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.1724498598
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.914415186
Short name T902
Test name
Test status
Simulation time 10053796340 ps
CPU time 12.8 seconds
Started Jun 06 01:44:00 PM PDT 24
Finished Jun 06 01:44:14 PM PDT 24
Peak memory 205748 kb
Host smart-4dba77b7-2735-4502-94ec-869fe1a89c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91441
5186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.914415186
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2410998381
Short name T192
Test name
Test status
Simulation time 459043941 ps
CPU time 1.38 seconds
Started Jun 06 01:44:17 PM PDT 24
Finished Jun 06 01:44:20 PM PDT 24
Peak memory 222868 kb
Host smart-766c6356-cb73-4920-b7d6-16eed848ffb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2410998381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2410998381
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.3691399449
Short name T896
Test name
Test status
Simulation time 10056570234 ps
CPU time 14.98 seconds
Started Jun 06 01:44:09 PM PDT 24
Finished Jun 06 01:44:26 PM PDT 24
Peak memory 205724 kb
Host smart-411c9c2f-4d70-4f1e-8e65-56f731724968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36913
99449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.3691399449
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1851684910
Short name T1370
Test name
Test status
Simulation time 10114082371 ps
CPU time 12.83 seconds
Started Jun 06 01:43:47 PM PDT 24
Finished Jun 06 01:44:01 PM PDT 24
Peak memory 205708 kb
Host smart-abc9e42c-52cb-454e-b3a4-837c00e8ea94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18516
84910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1851684910
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.3179676327
Short name T964
Test name
Test status
Simulation time 10065261790 ps
CPU time 16.29 seconds
Started Jun 06 01:44:08 PM PDT 24
Finished Jun 06 01:44:25 PM PDT 24
Peak memory 205696 kb
Host smart-fd7b13cb-562b-4c6f-b115-cd4edea84ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31796
76327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.3179676327
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.2340098531
Short name T624
Test name
Test status
Simulation time 10050856789 ps
CPU time 13.77 seconds
Started Jun 06 01:43:59 PM PDT 24
Finished Jun 06 01:44:14 PM PDT 24
Peak memory 205884 kb
Host smart-c1492910-aa30-4e29-999e-9079509380f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23400
98531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.2340098531
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.1842991034
Short name T904
Test name
Test status
Simulation time 15428872229 ps
CPU time 163.15 seconds
Started Jun 06 01:43:58 PM PDT 24
Finished Jun 06 01:46:42 PM PDT 24
Peak memory 205660 kb
Host smart-7979aeb3-8db1-403c-94ee-35389f2b6143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18429
91034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.1842991034
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.1424033604
Short name T1598
Test name
Test status
Simulation time 31955222600 ps
CPU time 138.27 seconds
Started Jun 06 01:43:57 PM PDT 24
Finished Jun 06 01:46:16 PM PDT 24
Peak memory 205752 kb
Host smart-6b36b31a-1ff8-4eb8-bee9-844bbc7994d5
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424033604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_
traffic.1424033604
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.363619675
Short name T321
Test name
Test status
Simulation time 10150607763 ps
CPU time 15.79 seconds
Started Jun 06 01:44:35 PM PDT 24
Finished Jun 06 01:44:51 PM PDT 24
Peak memory 205716 kb
Host smart-7882a3af-0044-4c8a-91f3-a1f5fff14878
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=363619675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.363619675
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.486154447
Short name T937
Test name
Test status
Simulation time 10047416751 ps
CPU time 14.29 seconds
Started Jun 06 01:44:35 PM PDT 24
Finished Jun 06 01:44:50 PM PDT 24
Peak memory 205748 kb
Host smart-1d12c98f-2b34-44e7-9111-9b186df38006
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=486154447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.486154447
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.1441163457
Short name T1020
Test name
Test status
Simulation time 10114904597 ps
CPU time 14.44 seconds
Started Jun 06 01:44:34 PM PDT 24
Finished Jun 06 01:44:49 PM PDT 24
Peak memory 205620 kb
Host smart-e0675688-f9bc-456b-8035-76c32299315d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14411
63457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.1441163457
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.338438106
Short name T1793
Test name
Test status
Simulation time 13492949400 ps
CPU time 16.32 seconds
Started Jun 06 01:44:17 PM PDT 24
Finished Jun 06 01:44:34 PM PDT 24
Peak memory 205636 kb
Host smart-d76cc3b6-17cf-4eb4-9636-3fc2639d6e22
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=338438106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.338438106
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.1691739005
Short name T1948
Test name
Test status
Simulation time 23220157595 ps
CPU time 24.84 seconds
Started Jun 06 01:44:15 PM PDT 24
Finished Jun 06 01:44:41 PM PDT 24
Peak memory 205704 kb
Host smart-3911ad96-b802-4b60-8b66-39496477314c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1691739005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.1691739005
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.3473143299
Short name T1490
Test name
Test status
Simulation time 10054911036 ps
CPU time 12.71 seconds
Started Jun 06 01:44:17 PM PDT 24
Finished Jun 06 01:44:31 PM PDT 24
Peak memory 205624 kb
Host smart-27bd7809-60d0-409b-bad2-287f782d6fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34731
43299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.3473143299
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.3151004094
Short name T1088
Test name
Test status
Simulation time 10065508535 ps
CPU time 13.25 seconds
Started Jun 06 01:44:18 PM PDT 24
Finished Jun 06 01:44:33 PM PDT 24
Peak memory 205580 kb
Host smart-5800ece5-21f5-4b42-8cbb-d686b54873e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31510
04094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.3151004094
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.3116298975
Short name T1526
Test name
Test status
Simulation time 10065732636 ps
CPU time 17.1 seconds
Started Jun 06 01:44:16 PM PDT 24
Finished Jun 06 01:44:34 PM PDT 24
Peak memory 205656 kb
Host smart-f230546e-896f-4c56-992b-5f623cccd287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31162
98975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.3116298975
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.1976578941
Short name T1517
Test name
Test status
Simulation time 10059603724 ps
CPU time 13.63 seconds
Started Jun 06 01:44:15 PM PDT 24
Finished Jun 06 01:44:29 PM PDT 24
Peak memory 205612 kb
Host smart-12444687-39bc-42ed-8913-d3b6042b966e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19765
78941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.1976578941
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.2883044970
Short name T900
Test name
Test status
Simulation time 10677388420 ps
CPU time 13.98 seconds
Started Jun 06 01:44:16 PM PDT 24
Finished Jun 06 01:44:31 PM PDT 24
Peak memory 205712 kb
Host smart-dfd33193-f816-470e-9cc5-e6764d59b3bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28830
44970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.2883044970
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.2746636671
Short name T1902
Test name
Test status
Simulation time 10196194821 ps
CPU time 17.5 seconds
Started Jun 06 01:44:17 PM PDT 24
Finished Jun 06 01:44:35 PM PDT 24
Peak memory 205740 kb
Host smart-7990e486-b3d5-46a8-9c46-b710764847a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27466
36671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2746636671
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.3981711516
Short name T1854
Test name
Test status
Simulation time 10172581097 ps
CPU time 15.43 seconds
Started Jun 06 01:44:36 PM PDT 24
Finished Jun 06 01:44:52 PM PDT 24
Peak memory 205596 kb
Host smart-d47d1508-ab10-4d3a-b033-aa6d2ce9e1af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39817
11516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.3981711516
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.1708993703
Short name T356
Test name
Test status
Simulation time 10087265154 ps
CPU time 12.73 seconds
Started Jun 06 01:44:32 PM PDT 24
Finished Jun 06 01:44:46 PM PDT 24
Peak memory 205600 kb
Host smart-90075e38-c8a3-45a7-b2da-2b65982ed8df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17089
93703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.1708993703
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.1349344644
Short name T335
Test name
Test status
Simulation time 10127042087 ps
CPU time 13.63 seconds
Started Jun 06 01:44:16 PM PDT 24
Finished Jun 06 01:44:30 PM PDT 24
Peak memory 205716 kb
Host smart-b69ee71a-474a-4163-8a60-f2d6dc2d9d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13493
44644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1349344644
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.1155135866
Short name T906
Test name
Test status
Simulation time 10135673001 ps
CPU time 13.57 seconds
Started Jun 06 01:44:16 PM PDT 24
Finished Jun 06 01:44:31 PM PDT 24
Peak memory 205700 kb
Host smart-c4c146e6-c936-45b2-8037-97c102bdf8f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11551
35866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.1155135866
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.2482826016
Short name T1190
Test name
Test status
Simulation time 13231851387 ps
CPU time 16.35 seconds
Started Jun 06 01:44:16 PM PDT 24
Finished Jun 06 01:44:34 PM PDT 24
Peak memory 205696 kb
Host smart-a4d2d3a8-4220-408e-b924-d4dc36d67b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24828
26016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.2482826016
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2925274671
Short name T1683
Test name
Test status
Simulation time 10134898825 ps
CPU time 14.96 seconds
Started Jun 06 01:44:16 PM PDT 24
Finished Jun 06 01:44:32 PM PDT 24
Peak memory 205704 kb
Host smart-71cdc6fb-349f-4250-8dde-64a7c19fc900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29252
74671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2925274671
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.3277324615
Short name T1214
Test name
Test status
Simulation time 18130169454 ps
CPU time 238.62 seconds
Started Jun 06 01:44:23 PM PDT 24
Finished Jun 06 01:48:22 PM PDT 24
Peak memory 205680 kb
Host smart-10e721eb-bcfa-4875-af48-a9e4f098b031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32773
24615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.3277324615
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.4171095393
Short name T708
Test name
Test status
Simulation time 10048041751 ps
CPU time 13.36 seconds
Started Jun 06 01:44:16 PM PDT 24
Finished Jun 06 01:44:31 PM PDT 24
Peak memory 205632 kb
Host smart-5b8070e7-3b62-4ba4-b333-1265a714854f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41710
95393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.4171095393
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.3653977456
Short name T955
Test name
Test status
Simulation time 10043290111 ps
CPU time 13.72 seconds
Started Jun 06 01:44:26 PM PDT 24
Finished Jun 06 01:44:41 PM PDT 24
Peak memory 205628 kb
Host smart-ca4aa1e6-e06b-4396-b181-b18bfb19fae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36539
77456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.3653977456
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.735960410
Short name T1224
Test name
Test status
Simulation time 10067329637 ps
CPU time 12.78 seconds
Started Jun 06 01:44:27 PM PDT 24
Finished Jun 06 01:44:40 PM PDT 24
Peak memory 205716 kb
Host smart-d6a35a99-9884-4710-b016-ece049f068c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73596
0410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.735960410
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.2241805724
Short name T677
Test name
Test status
Simulation time 10110471063 ps
CPU time 14.26 seconds
Started Jun 06 01:44:25 PM PDT 24
Finished Jun 06 01:44:40 PM PDT 24
Peak memory 205720 kb
Host smart-a3a79ace-1dd2-4c92-92f1-078f6259c6a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22418
05724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.2241805724
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_eop_single_bit_handling.4285569268
Short name T456
Test name
Test status
Simulation time 10088881680 ps
CPU time 14.73 seconds
Started Jun 06 01:44:34 PM PDT 24
Finished Jun 06 01:44:50 PM PDT 24
Peak memory 205748 kb
Host smart-8d0bf602-bfd7-4ab6-b975-c157ca108f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42855
69268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_eop_single_bit_handling.4285569268
Directory /workspace/1.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.702691314
Short name T1468
Test name
Test status
Simulation time 10046077012 ps
CPU time 13.04 seconds
Started Jun 06 01:44:35 PM PDT 24
Finished Jun 06 01:44:49 PM PDT 24
Peak memory 205600 kb
Host smart-e94f3829-76ef-4519-b127-8c41d5438fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70269
1314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.702691314
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1867079743
Short name T726
Test name
Test status
Simulation time 10038948950 ps
CPU time 13.5 seconds
Started Jun 06 01:44:35 PM PDT 24
Finished Jun 06 01:44:49 PM PDT 24
Peak memory 205604 kb
Host smart-4b229a04-e83d-4403-9414-3f27f0702cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18670
79743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1867079743
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.2293573084
Short name T1025
Test name
Test status
Simulation time 22450234089 ps
CPU time 43.65 seconds
Started Jun 06 01:44:28 PM PDT 24
Finished Jun 06 01:45:12 PM PDT 24
Peak memory 205696 kb
Host smart-ef7eba46-4595-44e9-8842-b0d8690f3ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22935
73084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.2293573084
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.3848954858
Short name T1614
Test name
Test status
Simulation time 10062621892 ps
CPU time 13.01 seconds
Started Jun 06 01:44:23 PM PDT 24
Finished Jun 06 01:44:37 PM PDT 24
Peak memory 205652 kb
Host smart-67ea7bc7-c842-40c0-ac16-55da9c64a3cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38489
54858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.3848954858
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.911706495
Short name T1277
Test name
Test status
Simulation time 10083325409 ps
CPU time 13.47 seconds
Started Jun 06 01:44:26 PM PDT 24
Finished Jun 06 01:44:40 PM PDT 24
Peak memory 205648 kb
Host smart-e50cadfc-b62d-493f-9813-684a9b14a550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91170
6495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.911706495
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.1640728065
Short name T1356
Test name
Test status
Simulation time 21108200460 ps
CPU time 95.84 seconds
Started Jun 06 01:44:23 PM PDT 24
Finished Jun 06 01:45:59 PM PDT 24
Peak memory 205764 kb
Host smart-61d19284-698b-413c-befb-731b01902986
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1640728065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.1640728065
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.2367094190
Short name T171
Test name
Test status
Simulation time 41770000428 ps
CPU time 835.1 seconds
Started Jun 06 01:44:24 PM PDT 24
Finished Jun 06 01:58:21 PM PDT 24
Peak memory 205700 kb
Host smart-f24e463e-a4f1-4938-9441-935b68ec8500
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2367094190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2367094190
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.3667721855
Short name T134
Test name
Test status
Simulation time 44451885895 ps
CPU time 889.2 seconds
Started Jun 06 01:44:28 PM PDT 24
Finished Jun 06 01:59:18 PM PDT 24
Peak memory 205784 kb
Host smart-c59b0b7f-c6a6-4fe4-b1ee-06278515aabe
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3667721855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.3667721855
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.2234845628
Short name T1589
Test name
Test status
Simulation time 10060576000 ps
CPU time 13.12 seconds
Started Jun 06 01:44:24 PM PDT 24
Finished Jun 06 01:44:37 PM PDT 24
Peak memory 205608 kb
Host smart-2202a1d4-10f1-461e-862e-aa30f23df620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22348
45628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.2234845628
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.1162947720
Short name T1841
Test name
Test status
Simulation time 10056944571 ps
CPU time 13.2 seconds
Started Jun 06 01:44:34 PM PDT 24
Finished Jun 06 01:44:49 PM PDT 24
Peak memory 205736 kb
Host smart-2ee750e4-1b66-4f0a-ad67-cd697117f20f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11629
47720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.1162947720
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.3097708551
Short name T151
Test name
Test status
Simulation time 10047501891 ps
CPU time 13.75 seconds
Started Jun 06 01:44:34 PM PDT 24
Finished Jun 06 01:44:49 PM PDT 24
Peak memory 205616 kb
Host smart-d8a0c198-eb86-4625-9ad8-b78893b6fdab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30977
08551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.3097708551
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3257899343
Short name T685
Test name
Test status
Simulation time 10058634565 ps
CPU time 13.27 seconds
Started Jun 06 01:44:38 PM PDT 24
Finished Jun 06 01:44:52 PM PDT 24
Peak memory 205624 kb
Host smart-59d94786-9f4f-4a26-b95b-ad7b45dc891c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32578
99343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3257899343
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3574445053
Short name T1977
Test name
Test status
Simulation time 10137631400 ps
CPU time 13.5 seconds
Started Jun 06 01:44:14 PM PDT 24
Finished Jun 06 01:44:29 PM PDT 24
Peak memory 205656 kb
Host smart-33996221-f54c-4ff5-bd4d-0732615c4664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35744
45053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3574445053
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.3331190498
Short name T1474
Test name
Test status
Simulation time 10061396443 ps
CPU time 13.7 seconds
Started Jun 06 01:44:35 PM PDT 24
Finished Jun 06 01:44:50 PM PDT 24
Peak memory 205604 kb
Host smart-08a88eb9-5f78-4e04-8517-89db4b19f56f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33311
90498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.3331190498
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.2035778679
Short name T1437
Test name
Test status
Simulation time 10084387203 ps
CPU time 12.87 seconds
Started Jun 06 01:44:28 PM PDT 24
Finished Jun 06 01:44:41 PM PDT 24
Peak memory 205720 kb
Host smart-f6d4f380-bdab-48c6-bf7f-a09319db6f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20357
78679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.2035778679
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.2507126313
Short name T1318
Test name
Test status
Simulation time 22839715389 ps
CPU time 144.78 seconds
Started Jun 06 01:44:35 PM PDT 24
Finished Jun 06 01:47:01 PM PDT 24
Peak memory 205708 kb
Host smart-76161417-00bd-42c5-a825-67736b2d408a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25071
26313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.2507126313
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.348075285
Short name T316
Test name
Test status
Simulation time 10137728876 ps
CPU time 13.6 seconds
Started Jun 06 01:47:04 PM PDT 24
Finished Jun 06 01:47:18 PM PDT 24
Peak memory 205684 kb
Host smart-f7301c97-fcf6-48ea-8b4e-08b2f1b94bfb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=348075285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.348075285
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.2432008150
Short name T1336
Test name
Test status
Simulation time 10064130648 ps
CPU time 14.56 seconds
Started Jun 06 01:46:55 PM PDT 24
Finished Jun 06 01:47:10 PM PDT 24
Peak memory 205672 kb
Host smart-657fbb0c-167e-4ade-a888-1d04f33d9496
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2432008150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.2432008150
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.1191324874
Short name T1228
Test name
Test status
Simulation time 10136743197 ps
CPU time 15.3 seconds
Started Jun 06 01:46:52 PM PDT 24
Finished Jun 06 01:47:08 PM PDT 24
Peak memory 205728 kb
Host smart-9e38dadc-8509-4f24-a046-8424b64fe767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11913
24874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.1191324874
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.3056181582
Short name T1438
Test name
Test status
Simulation time 14058312257 ps
CPU time 16.94 seconds
Started Jun 06 01:47:05 PM PDT 24
Finished Jun 06 01:47:23 PM PDT 24
Peak memory 205652 kb
Host smart-76507381-0875-4258-a760-ce0d9375d822
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3056181582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.3056181582
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.1789167437
Short name T573
Test name
Test status
Simulation time 23322549366 ps
CPU time 29.58 seconds
Started Jun 06 01:46:43 PM PDT 24
Finished Jun 06 01:47:13 PM PDT 24
Peak memory 205652 kb
Host smart-41eb9d54-4934-4829-8d36-42797ce1aeaa
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1789167437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.1789167437
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.3331486631
Short name T1987
Test name
Test status
Simulation time 10061595070 ps
CPU time 15.77 seconds
Started Jun 06 01:46:52 PM PDT 24
Finished Jun 06 01:47:08 PM PDT 24
Peak memory 205760 kb
Host smart-978379a6-e28d-4ad8-aa60-670fb495af0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33314
86631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3331486631
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.1589846998
Short name T1430
Test name
Test status
Simulation time 10389864296 ps
CPU time 16.6 seconds
Started Jun 06 01:46:53 PM PDT 24
Finished Jun 06 01:47:10 PM PDT 24
Peak memory 205620 kb
Host smart-96fb5d91-88cd-4799-ad06-9e36512817cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15898
46998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.1589846998
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.1309699989
Short name T1097
Test name
Test status
Simulation time 10035676332 ps
CPU time 14.38 seconds
Started Jun 06 01:46:53 PM PDT 24
Finished Jun 06 01:47:08 PM PDT 24
Peak memory 205732 kb
Host smart-952cd26f-1289-4f28-b349-da7f8702c59c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13096
99989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.1309699989
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.1970716608
Short name T485
Test name
Test status
Simulation time 10099690155 ps
CPU time 15.67 seconds
Started Jun 06 01:46:54 PM PDT 24
Finished Jun 06 01:47:10 PM PDT 24
Peak memory 205656 kb
Host smart-f35d17bd-e1e5-44c4-a666-91709c90501b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19707
16608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1970716608
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.3168095577
Short name T1576
Test name
Test status
Simulation time 10819898186 ps
CPU time 15.62 seconds
Started Jun 06 01:46:54 PM PDT 24
Finished Jun 06 01:47:11 PM PDT 24
Peak memory 205604 kb
Host smart-9e555d57-847f-433f-87b2-5a1c04bfcbee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31680
95577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.3168095577
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.4118047431
Short name T820
Test name
Test status
Simulation time 10084424483 ps
CPU time 15.54 seconds
Started Jun 06 01:46:55 PM PDT 24
Finished Jun 06 01:47:11 PM PDT 24
Peak memory 205668 kb
Host smart-b22c1f18-ce81-449c-8075-373f0078aee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41180
47431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.4118047431
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.773031165
Short name T930
Test name
Test status
Simulation time 10088001183 ps
CPU time 13.08 seconds
Started Jun 06 01:46:53 PM PDT 24
Finished Jun 06 01:47:07 PM PDT 24
Peak memory 205616 kb
Host smart-aca56f8a-2663-43c5-9e51-237e465d7d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77303
1165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.773031165
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.1758028336
Short name T1862
Test name
Test status
Simulation time 10046282503 ps
CPU time 13.87 seconds
Started Jun 06 01:46:55 PM PDT 24
Finished Jun 06 01:47:10 PM PDT 24
Peak memory 205692 kb
Host smart-9e67f730-612c-4059-addf-50ed9934de1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17580
28336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.1758028336
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3293601262
Short name T1715
Test name
Test status
Simulation time 10079364649 ps
CPU time 13.96 seconds
Started Jun 06 01:46:53 PM PDT 24
Finished Jun 06 01:47:08 PM PDT 24
Peak memory 205588 kb
Host smart-9fb337ee-739d-439b-897b-07345f5790d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32936
01262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3293601262
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.2947363234
Short name T1199
Test name
Test status
Simulation time 10107496924 ps
CPU time 12.72 seconds
Started Jun 06 01:46:54 PM PDT 24
Finished Jun 06 01:47:08 PM PDT 24
Peak memory 205748 kb
Host smart-2f5f9732-7e97-42ff-85ef-d2da039d20cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29473
63234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.2947363234
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.4074453821
Short name T1358
Test name
Test status
Simulation time 13231587465 ps
CPU time 16.63 seconds
Started Jun 06 01:46:59 PM PDT 24
Finished Jun 06 01:47:17 PM PDT 24
Peak memory 205664 kb
Host smart-19fc26e0-5858-409e-91cb-6cfc290134e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40744
53821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.4074453821
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1690797471
Short name T640
Test name
Test status
Simulation time 10108045478 ps
CPU time 13.17 seconds
Started Jun 06 01:46:53 PM PDT 24
Finished Jun 06 01:47:07 PM PDT 24
Peak memory 205744 kb
Host smart-2bba960c-15d3-4d3e-8dee-ff4c9208ff85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16907
97471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1690797471
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.4210631327
Short name T638
Test name
Test status
Simulation time 16863892449 ps
CPU time 195.27 seconds
Started Jun 06 01:46:54 PM PDT 24
Finished Jun 06 01:50:10 PM PDT 24
Peak memory 205668 kb
Host smart-b92e160f-bd11-41b4-8b06-0cca125729c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42106
31327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.4210631327
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.4005981247
Short name T849
Test name
Test status
Simulation time 10046643026 ps
CPU time 17.75 seconds
Started Jun 06 01:46:54 PM PDT 24
Finished Jun 06 01:47:13 PM PDT 24
Peak memory 205680 kb
Host smart-418ca5f8-cf70-4224-a354-8fc982bf819e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40059
81247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.4005981247
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.2894347487
Short name T1763
Test name
Test status
Simulation time 10111033582 ps
CPU time 13.76 seconds
Started Jun 06 01:46:59 PM PDT 24
Finished Jun 06 01:47:13 PM PDT 24
Peak memory 205632 kb
Host smart-54e2e1f1-adad-49da-9203-50d63406e299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28943
47487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.2894347487
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.1067348826
Short name T203
Test name
Test status
Simulation time 10096229282 ps
CPU time 16.04 seconds
Started Jun 06 01:46:54 PM PDT 24
Finished Jun 06 01:47:11 PM PDT 24
Peak memory 205596 kb
Host smart-5f1e8d34-0843-4415-b2e2-f45eb3a5a396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10673
48826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.1067348826
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.3485446638
Short name T745
Test name
Test status
Simulation time 10069169280 ps
CPU time 13.27 seconds
Started Jun 06 01:46:54 PM PDT 24
Finished Jun 06 01:47:09 PM PDT 24
Peak memory 205648 kb
Host smart-b9727aa1-6f2b-4580-be97-65462cc70eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34854
46638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.3485446638
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_eop_single_bit_handling.3186996153
Short name T1837
Test name
Test status
Simulation time 10062399972 ps
CPU time 12.73 seconds
Started Jun 06 01:46:56 PM PDT 24
Finished Jun 06 01:47:09 PM PDT 24
Peak memory 205772 kb
Host smart-169b4d7a-fdda-4fe4-8bad-1722af3a65ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31869
96153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_eop_single_bit_handling.3186996153
Directory /workspace/10.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.1262241652
Short name T1758
Test name
Test status
Simulation time 10119004080 ps
CPU time 12.39 seconds
Started Jun 06 01:46:55 PM PDT 24
Finished Jun 06 01:47:08 PM PDT 24
Peak memory 205756 kb
Host smart-d2111c81-3543-4b64-9146-3c882d31dd0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12622
41652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.1262241652
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.4111727921
Short name T2015
Test name
Test status
Simulation time 10035727688 ps
CPU time 12.88 seconds
Started Jun 06 01:46:59 PM PDT 24
Finished Jun 06 01:47:13 PM PDT 24
Peak memory 205660 kb
Host smart-94c01db3-6d38-49c8-b518-17295d11630a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41117
27921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.4111727921
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.4104839752
Short name T184
Test name
Test status
Simulation time 17267060215 ps
CPU time 33.83 seconds
Started Jun 06 01:46:54 PM PDT 24
Finished Jun 06 01:47:28 PM PDT 24
Peak memory 205704 kb
Host smart-f4cc4756-c992-4ab8-93c0-eabc414d53ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41048
39752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.4104839752
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.2788116884
Short name T406
Test name
Test status
Simulation time 10124860095 ps
CPU time 13.72 seconds
Started Jun 06 01:46:54 PM PDT 24
Finished Jun 06 01:47:09 PM PDT 24
Peak memory 205696 kb
Host smart-d6895008-d4ad-4c14-944f-89ea8e4916af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27881
16884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.2788116884
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.2411496860
Short name T502
Test name
Test status
Simulation time 10152273655 ps
CPU time 13.79 seconds
Started Jun 06 01:46:54 PM PDT 24
Finished Jun 06 01:47:08 PM PDT 24
Peak memory 205616 kb
Host smart-2e72d5d4-2e06-4c5b-820b-5567a0fd075a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24114
96860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2411496860
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.48521321
Short name T840
Test name
Test status
Simulation time 10059514331 ps
CPU time 16.53 seconds
Started Jun 06 01:46:51 PM PDT 24
Finished Jun 06 01:47:09 PM PDT 24
Peak memory 205740 kb
Host smart-9fffb832-53ef-44c8-b8bc-52d4928f1e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48521
321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.48521321
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.3392930210
Short name T1830
Test name
Test status
Simulation time 10073629148 ps
CPU time 18.1 seconds
Started Jun 06 01:46:53 PM PDT 24
Finished Jun 06 01:47:12 PM PDT 24
Peak memory 205676 kb
Host smart-625e1cfa-2610-4a39-a45c-06c769119ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33929
30210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.3392930210
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1291299360
Short name T1188
Test name
Test status
Simulation time 10053796932 ps
CPU time 13.8 seconds
Started Jun 06 01:46:56 PM PDT 24
Finished Jun 06 01:47:10 PM PDT 24
Peak memory 205704 kb
Host smart-efaf8a8d-f6bb-457e-98d2-4834dc74f77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12912
99360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1291299360
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.7597663
Short name T1694
Test name
Test status
Simulation time 10174487802 ps
CPU time 15.06 seconds
Started Jun 06 01:46:44 PM PDT 24
Finished Jun 06 01:47:00 PM PDT 24
Peak memory 205760 kb
Host smart-b1961dbb-6d2c-48a9-a76e-fef31585ac8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75976
63 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.7597663
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.1571606354
Short name T1426
Test name
Test status
Simulation time 10077698605 ps
CPU time 13.25 seconds
Started Jun 06 01:46:54 PM PDT 24
Finished Jun 06 01:47:08 PM PDT 24
Peak memory 205680 kb
Host smart-fdc4e567-b6f3-484a-82e3-55de02567ee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15716
06354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.1571606354
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.1883006319
Short name T363
Test name
Test status
Simulation time 10064559633 ps
CPU time 13.59 seconds
Started Jun 06 01:46:59 PM PDT 24
Finished Jun 06 01:47:13 PM PDT 24
Peak memory 205664 kb
Host smart-ceac4724-65ec-48cc-8a00-3617357eeccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18830
06319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.1883006319
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.588614515
Short name T1535
Test name
Test status
Simulation time 23390258937 ps
CPU time 140.06 seconds
Started Jun 06 01:46:52 PM PDT 24
Finished Jun 06 01:49:13 PM PDT 24
Peak memory 205676 kb
Host smart-a6371d11-cc86-4a69-92c0-a2227e7305a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58861
4515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.588614515
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.783562410
Short name T238
Test name
Test status
Simulation time 10150495101 ps
CPU time 14.96 seconds
Started Jun 06 01:47:12 PM PDT 24
Finished Jun 06 01:47:28 PM PDT 24
Peak memory 205616 kb
Host smart-2ec6197d-94db-45fc-b740-110e31ef3b1c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=783562410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.783562410
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.1642059077
Short name T1323
Test name
Test status
Simulation time 10068544317 ps
CPU time 13.09 seconds
Started Jun 06 01:47:13 PM PDT 24
Finished Jun 06 01:47:27 PM PDT 24
Peak memory 205628 kb
Host smart-2dad73b8-2ff1-4928-83c9-67b0c5b5c1f9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1642059077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.1642059077
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.3992651166
Short name T936
Test name
Test status
Simulation time 10086868660 ps
CPU time 13.06 seconds
Started Jun 06 01:47:12 PM PDT 24
Finished Jun 06 01:47:26 PM PDT 24
Peak memory 205672 kb
Host smart-c7862b55-cad7-4a3e-8a0b-115d4791ab02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39926
51166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.3992651166
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.2774692791
Short name T2032
Test name
Test status
Simulation time 23258627609 ps
CPU time 25.44 seconds
Started Jun 06 01:47:03 PM PDT 24
Finished Jun 06 01:47:29 PM PDT 24
Peak memory 205720 kb
Host smart-3618b333-a75d-4454-90ec-f01cbe6f3940
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2774692791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.2774692791
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.2318278226
Short name T1964
Test name
Test status
Simulation time 10063152754 ps
CPU time 14.49 seconds
Started Jun 06 01:47:05 PM PDT 24
Finished Jun 06 01:47:20 PM PDT 24
Peak memory 205756 kb
Host smart-0bbc13c3-bae9-446e-a1b1-9c1c6dc08d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23182
78226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.2318278226
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.3583094626
Short name T1183
Test name
Test status
Simulation time 10519445183 ps
CPU time 17.99 seconds
Started Jun 06 01:47:03 PM PDT 24
Finished Jun 06 01:47:22 PM PDT 24
Peak memory 205644 kb
Host smart-11c88d97-7d87-452a-9c65-8c40a8f42ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35830
94626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.3583094626
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.2159111474
Short name T571
Test name
Test status
Simulation time 10040635452 ps
CPU time 14.31 seconds
Started Jun 06 01:47:04 PM PDT 24
Finished Jun 06 01:47:19 PM PDT 24
Peak memory 205660 kb
Host smart-3be6c377-9530-4d0e-989a-8662413e4f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21591
11474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.2159111474
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.3211957358
Short name T1860
Test name
Test status
Simulation time 10089631444 ps
CPU time 13.31 seconds
Started Jun 06 01:47:00 PM PDT 24
Finished Jun 06 01:47:14 PM PDT 24
Peak memory 205584 kb
Host smart-9ef45955-28e5-47d5-808a-778e5a54ddbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32119
57358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3211957358
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.4251778111
Short name T1604
Test name
Test status
Simulation time 10880053102 ps
CPU time 17.91 seconds
Started Jun 06 01:47:01 PM PDT 24
Finished Jun 06 01:47:20 PM PDT 24
Peak memory 205668 kb
Host smart-7ff8f3a3-df83-4aff-9a63-ed890ea43dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42517
78111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.4251778111
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3125862399
Short name T864
Test name
Test status
Simulation time 10266855326 ps
CPU time 15.7 seconds
Started Jun 06 01:47:04 PM PDT 24
Finished Jun 06 01:47:20 PM PDT 24
Peak memory 205692 kb
Host smart-995c8752-87c6-45cf-9e02-553180e233cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31258
62399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3125862399
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1449906281
Short name T1583
Test name
Test status
Simulation time 10063089184 ps
CPU time 14.03 seconds
Started Jun 06 01:47:11 PM PDT 24
Finished Jun 06 01:47:25 PM PDT 24
Peak memory 205720 kb
Host smart-d074feca-57d2-4449-8d78-97be3f9e192d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14499
06281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1449906281
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.3674963497
Short name T1900
Test name
Test status
Simulation time 10099570555 ps
CPU time 17.56 seconds
Started Jun 06 01:47:01 PM PDT 24
Finished Jun 06 01:47:19 PM PDT 24
Peak memory 205736 kb
Host smart-f0143b45-3883-4ad2-80a7-dcff3732f967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36749
63497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.3674963497
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.1339827271
Short name T1744
Test name
Test status
Simulation time 10122435874 ps
CPU time 14.81 seconds
Started Jun 06 01:47:01 PM PDT 24
Finished Jun 06 01:47:17 PM PDT 24
Peak memory 205680 kb
Host smart-79de6685-9f31-4c24-a00e-c50d4035bc07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13398
27271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.1339827271
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.2520673484
Short name T1261
Test name
Test status
Simulation time 13164450119 ps
CPU time 19.4 seconds
Started Jun 06 01:47:02 PM PDT 24
Finished Jun 06 01:47:22 PM PDT 24
Peak memory 205568 kb
Host smart-d4d2bd6c-6971-4ef9-907b-cf3a6907d7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25206
73484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.2520673484
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1506597035
Short name T696
Test name
Test status
Simulation time 10121664028 ps
CPU time 15.86 seconds
Started Jun 06 01:47:04 PM PDT 24
Finished Jun 06 01:47:21 PM PDT 24
Peak memory 205704 kb
Host smart-960a7757-d028-4648-8e4b-018ff58be03f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15065
97035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1506597035
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.1577287089
Short name T1418
Test name
Test status
Simulation time 25025981158 ps
CPU time 443.03 seconds
Started Jun 06 01:47:04 PM PDT 24
Finished Jun 06 01:54:28 PM PDT 24
Peak memory 205640 kb
Host smart-8eaa1644-e393-4ca9-acfa-b7d43df9ff65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15772
87089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.1577287089
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.1811273139
Short name T220
Test name
Test status
Simulation time 10061134869 ps
CPU time 13.77 seconds
Started Jun 06 01:47:02 PM PDT 24
Finished Jun 06 01:47:17 PM PDT 24
Peak memory 205780 kb
Host smart-0a8e485d-2a8c-4d91-975f-9bafc7f659d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18112
73139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.1811273139
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.549088567
Short name T1740
Test name
Test status
Simulation time 10097010908 ps
CPU time 13.53 seconds
Started Jun 06 01:47:12 PM PDT 24
Finished Jun 06 01:47:27 PM PDT 24
Peak memory 205720 kb
Host smart-29e93c36-fd61-49b1-a139-cf67a247324f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54908
8567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.549088567
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3646183301
Short name T221
Test name
Test status
Simulation time 10075324479 ps
CPU time 16.01 seconds
Started Jun 06 01:47:14 PM PDT 24
Finished Jun 06 01:47:31 PM PDT 24
Peak memory 205720 kb
Host smart-5a0366ed-c7ef-46ff-988a-14aab6b89908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36461
83301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3646183301
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1794529305
Short name T1207
Test name
Test status
Simulation time 10151817457 ps
CPU time 13.19 seconds
Started Jun 06 01:47:22 PM PDT 24
Finished Jun 06 01:47:37 PM PDT 24
Peak memory 205632 kb
Host smart-f775500d-fb3a-4065-a004-6990fdc03111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17945
29305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1794529305
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.1092837807
Short name T66
Test name
Test status
Simulation time 10072059250 ps
CPU time 15.57 seconds
Started Jun 06 01:47:15 PM PDT 24
Finished Jun 06 01:47:32 PM PDT 24
Peak memory 205752 kb
Host smart-dc9e1ee4-053f-4f0a-8215-4654310a80d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10928
37807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.1092837807
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_eop_single_bit_handling.360245274
Short name T1191
Test name
Test status
Simulation time 10069866070 ps
CPU time 15.77 seconds
Started Jun 06 01:47:11 PM PDT 24
Finished Jun 06 01:47:28 PM PDT 24
Peak memory 205732 kb
Host smart-a1550d6c-fd07-42c1-9198-573a3685c16c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36024
5274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_eop_single_bit_handling.360245274
Directory /workspace/11.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3217774715
Short name T1553
Test name
Test status
Simulation time 10053262215 ps
CPU time 12.68 seconds
Started Jun 06 01:47:11 PM PDT 24
Finished Jun 06 01:47:25 PM PDT 24
Peak memory 205704 kb
Host smart-33a0d302-829a-4e67-bf40-54e3da42fc13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32177
74715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3217774715
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.3363679915
Short name T180
Test name
Test status
Simulation time 24817242106 ps
CPU time 47.48 seconds
Started Jun 06 01:47:12 PM PDT 24
Finished Jun 06 01:48:01 PM PDT 24
Peak memory 205688 kb
Host smart-b2a4f247-3bae-4b62-9c51-b498f54f31b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33636
79915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.3363679915
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.3284470019
Short name T1428
Test name
Test status
Simulation time 10056124928 ps
CPU time 14.08 seconds
Started Jun 06 01:47:12 PM PDT 24
Finished Jun 06 01:47:27 PM PDT 24
Peak memory 205616 kb
Host smart-1792f059-21bf-438b-8810-a75c9024728d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32844
70019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3284470019
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1064770390
Short name T1465
Test name
Test status
Simulation time 10176018100 ps
CPU time 13.03 seconds
Started Jun 06 01:47:22 PM PDT 24
Finished Jun 06 01:47:36 PM PDT 24
Peak memory 205692 kb
Host smart-2a7a9199-6394-4320-9173-b0cc40614f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10647
70390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1064770390
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.976845290
Short name T422
Test name
Test status
Simulation time 10059430329 ps
CPU time 13.56 seconds
Started Jun 06 01:47:11 PM PDT 24
Finished Jun 06 01:47:26 PM PDT 24
Peak memory 205664 kb
Host smart-7be48b79-4259-406a-b43b-39f5c298382e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97684
5290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.976845290
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.2020774708
Short name T1908
Test name
Test status
Simulation time 10043818010 ps
CPU time 13.33 seconds
Started Jun 06 01:47:22 PM PDT 24
Finished Jun 06 01:47:36 PM PDT 24
Peak memory 205660 kb
Host smart-f0b5f248-dad8-467a-8278-c16e6b6baf46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20207
74708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.2020774708
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.2645590981
Short name T158
Test name
Test status
Simulation time 10072469387 ps
CPU time 12.87 seconds
Started Jun 06 01:47:14 PM PDT 24
Finished Jun 06 01:47:28 PM PDT 24
Peak memory 205688 kb
Host smart-f2f5dda1-6903-4298-a2e8-1c3b2b1844ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26455
90981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.2645590981
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.63970482
Short name T1579
Test name
Test status
Simulation time 10071481104 ps
CPU time 13.45 seconds
Started Jun 06 01:47:13 PM PDT 24
Finished Jun 06 01:47:27 PM PDT 24
Peak memory 205784 kb
Host smart-368354c3-a2fb-4039-a0ff-67682a1816e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63970
482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.63970482
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.996629213
Short name T568
Test name
Test status
Simulation time 10087169962 ps
CPU time 14.08 seconds
Started Jun 06 01:47:14 PM PDT 24
Finished Jun 06 01:47:29 PM PDT 24
Peak memory 205732 kb
Host smart-4dabfa0d-c147-4012-80c3-f61e4ddcee6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99662
9213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.996629213
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.4049161699
Short name T1780
Test name
Test status
Simulation time 10054435314 ps
CPU time 12.86 seconds
Started Jun 06 01:47:14 PM PDT 24
Finished Jun 06 01:47:28 PM PDT 24
Peak memory 205760 kb
Host smart-ca593554-25d3-434e-a533-45196a0ae7ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40491
61699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.4049161699
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.694144079
Short name T1268
Test name
Test status
Simulation time 17333660423 ps
CPU time 85.58 seconds
Started Jun 06 01:47:11 PM PDT 24
Finished Jun 06 01:48:37 PM PDT 24
Peak memory 205712 kb
Host smart-77576c16-68e5-4b4c-b51b-26b0b1f709ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69414
4079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.694144079
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.938806396
Short name T1491
Test name
Test status
Simulation time 10165184700 ps
CPU time 13.98 seconds
Started Jun 06 01:47:23 PM PDT 24
Finished Jun 06 01:47:38 PM PDT 24
Peak memory 205736 kb
Host smart-6fdc5348-85eb-45e8-926d-ef01172879af
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=938806396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.938806396
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.2713507269
Short name T1484
Test name
Test status
Simulation time 10056347742 ps
CPU time 14.21 seconds
Started Jun 06 01:47:23 PM PDT 24
Finished Jun 06 01:47:39 PM PDT 24
Peak memory 205648 kb
Host smart-4eded0bc-975f-4576-8483-e946ac3d2530
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2713507269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.2713507269
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.329645249
Short name T757
Test name
Test status
Simulation time 10107906068 ps
CPU time 14.98 seconds
Started Jun 06 01:47:22 PM PDT 24
Finished Jun 06 01:47:38 PM PDT 24
Peak memory 205628 kb
Host smart-e373e824-698d-46c3-bf31-a647db9b761a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32964
5249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.329645249
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.842288218
Short name T1090
Test name
Test status
Simulation time 13738376937 ps
CPU time 17.64 seconds
Started Jun 06 01:47:14 PM PDT 24
Finished Jun 06 01:47:33 PM PDT 24
Peak memory 205728 kb
Host smart-ffb5bd79-9e7f-41dd-a7fb-7d824656c642
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=842288218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.842288218
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.1565153437
Short name T1501
Test name
Test status
Simulation time 23321072903 ps
CPU time 27.67 seconds
Started Jun 06 01:47:20 PM PDT 24
Finished Jun 06 01:47:48 PM PDT 24
Peak memory 205664 kb
Host smart-518eaa96-d511-4166-a898-bf22a3c9c3d8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1565153437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.1565153437
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2925159994
Short name T872
Test name
Test status
Simulation time 10057217380 ps
CPU time 14.41 seconds
Started Jun 06 01:47:11 PM PDT 24
Finished Jun 06 01:47:27 PM PDT 24
Peak memory 205664 kb
Host smart-9950c0d9-151f-46f1-875f-21c8494c6185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29251
59994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2925159994
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.807233154
Short name T62
Test name
Test status
Simulation time 10046574523 ps
CPU time 15.47 seconds
Started Jun 06 01:47:20 PM PDT 24
Finished Jun 06 01:47:37 PM PDT 24
Peak memory 205660 kb
Host smart-62a0a0d0-689b-4a1f-ae0f-0db07a2572dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80723
3154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.807233154
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.2389214579
Short name T679
Test name
Test status
Simulation time 11181133929 ps
CPU time 15.46 seconds
Started Jun 06 01:47:16 PM PDT 24
Finished Jun 06 01:47:32 PM PDT 24
Peak memory 205600 kb
Host smart-5957f819-5801-42bc-8189-8efb089d2e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23892
14579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.2389214579
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.2046065833
Short name T763
Test name
Test status
Simulation time 10049566979 ps
CPU time 13.11 seconds
Started Jun 06 01:47:24 PM PDT 24
Finished Jun 06 01:47:39 PM PDT 24
Peak memory 205640 kb
Host smart-e79b7118-4bdb-4761-b7c6-576e3b4d7080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20460
65833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2046065833
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.3315807571
Short name T610
Test name
Test status
Simulation time 10060897111 ps
CPU time 13.81 seconds
Started Jun 06 01:47:21 PM PDT 24
Finished Jun 06 01:47:36 PM PDT 24
Peak memory 205612 kb
Host smart-4c3243ce-50d6-449d-9f52-58dae17cd183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33158
07571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.3315807571
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.2053310816
Short name T441
Test name
Test status
Simulation time 10782811504 ps
CPU time 14.88 seconds
Started Jun 06 01:47:12 PM PDT 24
Finished Jun 06 01:47:28 PM PDT 24
Peak memory 205736 kb
Host smart-e807c957-4ad5-41cd-a636-f0312d1bf10e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20533
10816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.2053310816
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3544208348
Short name T1001
Test name
Test status
Simulation time 10059932954 ps
CPU time 13.68 seconds
Started Jun 06 01:47:21 PM PDT 24
Finished Jun 06 01:47:36 PM PDT 24
Peak memory 205604 kb
Host smart-33b92599-1be9-4edf-88ad-201a34bab034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35442
08348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3544208348
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.74536827
Short name T1885
Test name
Test status
Simulation time 10096608615 ps
CPU time 15.12 seconds
Started Jun 06 01:47:20 PM PDT 24
Finished Jun 06 01:47:36 PM PDT 24
Peak memory 205712 kb
Host smart-e9baee41-572f-4cb3-9601-d19622f03c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74536
827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.74536827
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.937269301
Short name T871
Test name
Test status
Simulation time 10051078797 ps
CPU time 13.28 seconds
Started Jun 06 01:47:23 PM PDT 24
Finished Jun 06 01:47:37 PM PDT 24
Peak memory 205612 kb
Host smart-12449ce9-c908-4ebb-b224-45183faca77b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93726
9301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.937269301
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.671339363
Short name T496
Test name
Test status
Simulation time 10197435539 ps
CPU time 15.96 seconds
Started Jun 06 01:47:23 PM PDT 24
Finished Jun 06 01:47:40 PM PDT 24
Peak memory 205688 kb
Host smart-741c2a65-e8ca-4589-8bb9-a8e198ded01f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67133
9363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.671339363
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.562275670
Short name T32
Test name
Test status
Simulation time 10075751220 ps
CPU time 14.35 seconds
Started Jun 06 01:47:22 PM PDT 24
Finished Jun 06 01:47:38 PM PDT 24
Peak memory 205648 kb
Host smart-f3b055be-bb4d-4ebf-a3df-0dd35205a415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56227
5670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.562275670
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.2206468710
Short name T317
Test name
Test status
Simulation time 13195140376 ps
CPU time 19.46 seconds
Started Jun 06 01:47:21 PM PDT 24
Finished Jun 06 01:47:42 PM PDT 24
Peak memory 205744 kb
Host smart-45ab1269-285f-41db-bbaf-dddfd09a459d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22064
68710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.2206468710
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1355060476
Short name T1395
Test name
Test status
Simulation time 10094953341 ps
CPU time 17.62 seconds
Started Jun 06 01:47:22 PM PDT 24
Finished Jun 06 01:47:41 PM PDT 24
Peak memory 205768 kb
Host smart-49077a66-6ace-4537-9453-f7edacd822c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13550
60476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1355060476
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.2555239150
Short name T1931
Test name
Test status
Simulation time 16659511495 ps
CPU time 76.4 seconds
Started Jun 06 01:47:25 PM PDT 24
Finished Jun 06 01:48:43 PM PDT 24
Peak memory 205720 kb
Host smart-cfff5762-f1ff-4d61-a87a-55bd64107c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25552
39150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.2555239150
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.910249810
Short name T1076
Test name
Test status
Simulation time 10067443966 ps
CPU time 13.72 seconds
Started Jun 06 01:47:24 PM PDT 24
Finished Jun 06 01:47:40 PM PDT 24
Peak memory 205728 kb
Host smart-18a3b4b7-e6fb-43b3-a0d2-e2be496273e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91024
9810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.910249810
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.40547979
Short name T1124
Test name
Test status
Simulation time 10076941089 ps
CPU time 13.46 seconds
Started Jun 06 01:47:20 PM PDT 24
Finished Jun 06 01:47:35 PM PDT 24
Peak memory 205660 kb
Host smart-4055a012-fd54-40e8-b723-64a24ed2a8d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40547
979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.40547979
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.3131032658
Short name T1332
Test name
Test status
Simulation time 10051672728 ps
CPU time 14.3 seconds
Started Jun 06 01:47:22 PM PDT 24
Finished Jun 06 01:47:38 PM PDT 24
Peak memory 205648 kb
Host smart-1da6c8d7-5bda-4ce4-904c-8bbe3b5c1134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31310
32658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.3131032658
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_eop_single_bit_handling.217485186
Short name T1988
Test name
Test status
Simulation time 10083222241 ps
CPU time 14.03 seconds
Started Jun 06 01:47:23 PM PDT 24
Finished Jun 06 01:47:39 PM PDT 24
Peak memory 205740 kb
Host smart-dc1afe51-bc05-4ca0-ae8b-b9003093d259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21748
5186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_eop_single_bit_handling.217485186
Directory /workspace/12.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.2497474004
Short name T799
Test name
Test status
Simulation time 10047841155 ps
CPU time 17.02 seconds
Started Jun 06 01:47:21 PM PDT 24
Finished Jun 06 01:47:39 PM PDT 24
Peak memory 205676 kb
Host smart-41c233e1-fb3c-49bd-a893-cbbbf16d36d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24974
74004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.2497474004
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.74797134
Short name T1239
Test name
Test status
Simulation time 10055196281 ps
CPU time 14.34 seconds
Started Jun 06 01:47:22 PM PDT 24
Finished Jun 06 01:47:38 PM PDT 24
Peak memory 205600 kb
Host smart-6264f424-5b9f-4b5a-8ae8-0f008a23d683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74797
134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.74797134
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.1628458074
Short name T1846
Test name
Test status
Simulation time 32534159967 ps
CPU time 60.82 seconds
Started Jun 06 01:47:22 PM PDT 24
Finished Jun 06 01:48:24 PM PDT 24
Peak memory 205660 kb
Host smart-bad8d604-892c-4214-8d02-29f6e3130fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16284
58074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.1628458074
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.2945714523
Short name T359
Test name
Test status
Simulation time 10083201771 ps
CPU time 12.95 seconds
Started Jun 06 01:47:24 PM PDT 24
Finished Jun 06 01:47:39 PM PDT 24
Peak memory 205616 kb
Host smart-f30f3f13-2bdb-4ff0-b093-1ceeefb5bb84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29457
14523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.2945714523
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3597592481
Short name T365
Test name
Test status
Simulation time 10115400718 ps
CPU time 16.09 seconds
Started Jun 06 01:47:25 PM PDT 24
Finished Jun 06 01:47:42 PM PDT 24
Peak memory 205728 kb
Host smart-89ebab35-9a3b-4ca7-a288-29bd526411d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35975
92481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3597592481
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.2177108399
Short name T1686
Test name
Test status
Simulation time 10076784856 ps
CPU time 13.47 seconds
Started Jun 06 01:47:22 PM PDT 24
Finished Jun 06 01:47:37 PM PDT 24
Peak memory 205844 kb
Host smart-1fb70ff5-14c5-4c5e-bfd1-ebee2d3a4a62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21771
08399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.2177108399
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.1089344412
Short name T1574
Test name
Test status
Simulation time 10038173202 ps
CPU time 13.45 seconds
Started Jun 06 01:47:21 PM PDT 24
Finished Jun 06 01:47:36 PM PDT 24
Peak memory 205604 kb
Host smart-0e9f7c1f-6862-47d1-9b1e-f26dbb5a5f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10893
44412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.1089344412
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.2051086525
Short name T1859
Test name
Test status
Simulation time 10079172772 ps
CPU time 15.77 seconds
Started Jun 06 01:47:24 PM PDT 24
Finished Jun 06 01:47:41 PM PDT 24
Peak memory 205704 kb
Host smart-caceb753-3f0e-4cf6-b583-40d11c736c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20510
86525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.2051086525
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.2490517614
Short name T1235
Test name
Test status
Simulation time 10048533984 ps
CPU time 14.22 seconds
Started Jun 06 01:47:21 PM PDT 24
Finished Jun 06 01:47:36 PM PDT 24
Peak memory 205644 kb
Host smart-9aea73fe-0bd3-4350-b4b8-f868e2dd3f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24905
17614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.2490517614
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.1558960603
Short name T156
Test name
Test status
Simulation time 10083243011 ps
CPU time 12.91 seconds
Started Jun 06 01:47:20 PM PDT 24
Finished Jun 06 01:47:34 PM PDT 24
Peak memory 205612 kb
Host smart-8f3719be-dd89-4b4a-a3bf-2d21fe442e27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15589
60603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.1558960603
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.964773768
Short name T328
Test name
Test status
Simulation time 10093760873 ps
CPU time 12.87 seconds
Started Jun 06 01:47:21 PM PDT 24
Finished Jun 06 01:47:35 PM PDT 24
Peak memory 205768 kb
Host smart-b1051cbe-83aa-42c1-86d6-e6d49cf25604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96477
3768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.964773768
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.629052836
Short name T1935
Test name
Test status
Simulation time 10075403557 ps
CPU time 13.01 seconds
Started Jun 06 01:47:23 PM PDT 24
Finished Jun 06 01:47:37 PM PDT 24
Peak memory 205660 kb
Host smart-4cc70ec3-ef00-48c9-8a2d-75acd6097149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62905
2836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.629052836
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.920143461
Short name T575
Test name
Test status
Simulation time 14619141002 ps
CPU time 59.92 seconds
Started Jun 06 01:47:23 PM PDT 24
Finished Jun 06 01:48:24 PM PDT 24
Peak memory 205704 kb
Host smart-f810a5cf-c915-45f7-95bf-6edc5754dab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92014
3461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.920143461
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.519530377
Short name T1141
Test name
Test status
Simulation time 10144623836 ps
CPU time 14.23 seconds
Started Jun 06 01:47:27 PM PDT 24
Finished Jun 06 01:47:42 PM PDT 24
Peak memory 205772 kb
Host smart-ac8b31fc-7958-4b4e-b81f-4ef4cfeb29ea
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=519530377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.519530377
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.3561110888
Short name T477
Test name
Test status
Simulation time 10063209881 ps
CPU time 14.2 seconds
Started Jun 06 01:47:28 PM PDT 24
Finished Jun 06 01:47:43 PM PDT 24
Peak memory 206016 kb
Host smart-1eeb8729-51db-4b57-8678-5518387fb014
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3561110888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.3561110888
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.2554517703
Short name T465
Test name
Test status
Simulation time 10137432493 ps
CPU time 15.09 seconds
Started Jun 06 01:47:29 PM PDT 24
Finished Jun 06 01:47:45 PM PDT 24
Peak memory 205640 kb
Host smart-62bd36df-2176-4680-af51-bfc178e0ccc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25545
17703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.2554517703
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.2305089775
Short name T488
Test name
Test status
Simulation time 13459583896 ps
CPU time 16.92 seconds
Started Jun 06 01:47:19 PM PDT 24
Finished Jun 06 01:47:37 PM PDT 24
Peak memory 205744 kb
Host smart-5d552dda-46c0-4547-b30c-b5c07c5665ce
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2305089775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.2305089775
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.2327088812
Short name T1041
Test name
Test status
Simulation time 23237367162 ps
CPU time 28.61 seconds
Started Jun 06 01:47:25 PM PDT 24
Finished Jun 06 01:47:55 PM PDT 24
Peak memory 205692 kb
Host smart-32c7e342-9e41-43ba-8827-d3d7fea26d7c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2327088812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.2327088812
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.4278426139
Short name T370
Test name
Test status
Simulation time 10043487331 ps
CPU time 14.35 seconds
Started Jun 06 01:47:24 PM PDT 24
Finished Jun 06 01:47:40 PM PDT 24
Peak memory 205696 kb
Host smart-f5791a09-9b16-4c88-ab3f-0d2f78002886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42784
26139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.4278426139
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.1828718446
Short name T890
Test name
Test status
Simulation time 10063493624 ps
CPU time 14.57 seconds
Started Jun 06 01:47:24 PM PDT 24
Finished Jun 06 01:47:40 PM PDT 24
Peak memory 205748 kb
Host smart-795bc36f-0472-4e51-9f6a-c6920214fc7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18287
18446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.1828718446
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.2142706797
Short name T1511
Test name
Test status
Simulation time 10539955092 ps
CPU time 16.33 seconds
Started Jun 06 01:47:22 PM PDT 24
Finished Jun 06 01:47:40 PM PDT 24
Peak memory 205616 kb
Host smart-7b32abe1-34bf-4d6f-89b5-96d1d9239c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21427
06797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.2142706797
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.842516889
Short name T1542
Test name
Test status
Simulation time 10039163779 ps
CPU time 12.33 seconds
Started Jun 06 01:47:19 PM PDT 24
Finished Jun 06 01:47:32 PM PDT 24
Peak memory 205688 kb
Host smart-298f26ad-2086-4eaf-913c-12e6ba06dd10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84251
6889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.842516889
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.3630050411
Short name T916
Test name
Test status
Simulation time 10068170739 ps
CPU time 14.55 seconds
Started Jun 06 01:47:24 PM PDT 24
Finished Jun 06 01:47:40 PM PDT 24
Peak memory 205628 kb
Host smart-0559ba07-1350-41a8-b4d5-af066da88d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36300
50411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.3630050411
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.1707253081
Short name T468
Test name
Test status
Simulation time 10765972143 ps
CPU time 15.82 seconds
Started Jun 06 01:47:24 PM PDT 24
Finished Jun 06 01:47:42 PM PDT 24
Peak memory 205672 kb
Host smart-6a0fc8cb-4722-4dbf-9d5d-3f957e3265f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17072
53081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.1707253081
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2129425975
Short name T1815
Test name
Test status
Simulation time 10066844384 ps
CPU time 14.43 seconds
Started Jun 06 01:47:24 PM PDT 24
Finished Jun 06 01:47:40 PM PDT 24
Peak memory 205584 kb
Host smart-618d4380-b32f-4fd7-bcc3-87525baeb85c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21294
25975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2129425975
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.4098522031
Short name T1575
Test name
Test status
Simulation time 10110188513 ps
CPU time 13.93 seconds
Started Jun 06 01:47:32 PM PDT 24
Finished Jun 06 01:47:46 PM PDT 24
Peak memory 205992 kb
Host smart-4c0863d2-0ea9-412e-a57c-107960e4ae63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40985
22031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.4098522031
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.2865222065
Short name T81
Test name
Test status
Simulation time 10040942768 ps
CPU time 14.18 seconds
Started Jun 06 01:47:32 PM PDT 24
Finished Jun 06 01:47:47 PM PDT 24
Peak memory 205648 kb
Host smart-4bcfa2f8-4d4d-46d4-a98d-418843460213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28652
22065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.2865222065
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.432472161
Short name T1000
Test name
Test status
Simulation time 10088878701 ps
CPU time 13.24 seconds
Started Jun 06 01:47:20 PM PDT 24
Finished Jun 06 01:47:34 PM PDT 24
Peak memory 205764 kb
Host smart-6b853c74-8569-47e7-90a8-a639f98c60fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43247
2161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.432472161
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.585567660
Short name T1557
Test name
Test status
Simulation time 10068434010 ps
CPU time 14.52 seconds
Started Jun 06 01:47:24 PM PDT 24
Finished Jun 06 01:47:40 PM PDT 24
Peak memory 205748 kb
Host smart-dc518219-2cc6-4c58-89db-1de15f9693fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58556
7660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.585567660
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.2486965276
Short name T674
Test name
Test status
Simulation time 13170815015 ps
CPU time 16.16 seconds
Started Jun 06 01:47:26 PM PDT 24
Finished Jun 06 01:47:43 PM PDT 24
Peak memory 205700 kb
Host smart-4b434126-38c4-4fed-acf6-8038edfd4d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24869
65276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.2486965276
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.259118812
Short name T1572
Test name
Test status
Simulation time 10088727869 ps
CPU time 13.09 seconds
Started Jun 06 01:47:21 PM PDT 24
Finished Jun 06 01:47:35 PM PDT 24
Peak memory 205752 kb
Host smart-39cfd5ba-5326-4374-85e8-59679f0b215d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25911
8812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.259118812
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.3848361241
Short name T908
Test name
Test status
Simulation time 20567878488 ps
CPU time 114.8 seconds
Started Jun 06 01:47:25 PM PDT 24
Finished Jun 06 01:49:21 PM PDT 24
Peak memory 205672 kb
Host smart-a1b1c93a-5fae-43ad-ba69-0455104a7fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38483
61241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.3848361241
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.269409628
Short name T384
Test name
Test status
Simulation time 10040436895 ps
CPU time 15.27 seconds
Started Jun 06 01:47:25 PM PDT 24
Finished Jun 06 01:47:41 PM PDT 24
Peak memory 205704 kb
Host smart-95e1273c-6788-46bc-94c6-2088b6b12f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26940
9628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.269409628
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.698663711
Short name T110
Test name
Test status
Simulation time 10154039676 ps
CPU time 15.25 seconds
Started Jun 06 01:47:24 PM PDT 24
Finished Jun 06 01:47:41 PM PDT 24
Peak memory 205668 kb
Host smart-94863235-823d-484b-b74a-cc44cb95780d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69866
3711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.698663711
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.240413102
Short name T558
Test name
Test status
Simulation time 10083477441 ps
CPU time 15.2 seconds
Started Jun 06 01:47:34 PM PDT 24
Finished Jun 06 01:47:49 PM PDT 24
Peak memory 205656 kb
Host smart-b6a3961d-fe02-4f52-936d-f4fbded634c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24041
3102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.240413102
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.3113030256
Short name T339
Test name
Test status
Simulation time 10083791350 ps
CPU time 13.97 seconds
Started Jun 06 01:47:36 PM PDT 24
Finished Jun 06 01:47:51 PM PDT 24
Peak memory 205736 kb
Host smart-e6de316b-2818-4353-bff5-359a1376dc8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31130
30256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3113030256
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.3699531120
Short name T1746
Test name
Test status
Simulation time 10059138730 ps
CPU time 15.94 seconds
Started Jun 06 01:47:27 PM PDT 24
Finished Jun 06 01:47:44 PM PDT 24
Peak memory 205612 kb
Host smart-fbfc829a-d73a-4a4b-a612-d7b75a844baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36995
31120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.3699531120
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.3043013745
Short name T1938
Test name
Test status
Simulation time 10082905641 ps
CPU time 17.03 seconds
Started Jun 06 01:47:29 PM PDT 24
Finished Jun 06 01:47:47 PM PDT 24
Peak memory 205780 kb
Host smart-50ef3733-eedc-4d88-8b9d-bead6ae61ae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30430
13745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.3043013745
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_eop_single_bit_handling.1776165357
Short name T1608
Test name
Test status
Simulation time 10101988807 ps
CPU time 15.76 seconds
Started Jun 06 01:47:30 PM PDT 24
Finished Jun 06 01:47:46 PM PDT 24
Peak memory 205668 kb
Host smart-8e1a52e0-2123-4afe-a3a6-ea2362b97968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17761
65357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_eop_single_bit_handling.1776165357
Directory /workspace/13.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.3148809159
Short name T387
Test name
Test status
Simulation time 10053826189 ps
CPU time 13.44 seconds
Started Jun 06 01:47:34 PM PDT 24
Finished Jun 06 01:47:49 PM PDT 24
Peak memory 205604 kb
Host smart-2e68d271-3dda-410e-93bf-93d0af5f7a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31488
09159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.3148809159
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.590484964
Short name T1383
Test name
Test status
Simulation time 10050326209 ps
CPU time 17.27 seconds
Started Jun 06 01:47:28 PM PDT 24
Finished Jun 06 01:47:47 PM PDT 24
Peak memory 205732 kb
Host smart-33038bde-64a1-4893-8b93-20e91b4b6d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59048
4964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.590484964
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1638820200
Short name T1402
Test name
Test status
Simulation time 32742554329 ps
CPU time 63.55 seconds
Started Jun 06 01:47:31 PM PDT 24
Finished Jun 06 01:48:35 PM PDT 24
Peak memory 205604 kb
Host smart-a8b631f8-e43d-479c-877e-20ad1e0edee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16388
20200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1638820200
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.926279833
Short name T877
Test name
Test status
Simulation time 10056125694 ps
CPU time 13.74 seconds
Started Jun 06 01:47:28 PM PDT 24
Finished Jun 06 01:47:43 PM PDT 24
Peak memory 205676 kb
Host smart-213797ce-8b98-4251-9f2a-07923d2f6fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92627
9833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.926279833
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.691283980
Short name T574
Test name
Test status
Simulation time 10121161084 ps
CPU time 15.31 seconds
Started Jun 06 01:47:34 PM PDT 24
Finished Jun 06 01:47:50 PM PDT 24
Peak memory 205628 kb
Host smart-9f248475-6446-4b15-bcb7-6f61d08d791a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69128
3980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.691283980
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.3816687748
Short name T16
Test name
Test status
Simulation time 10071314474 ps
CPU time 13.19 seconds
Started Jun 06 01:47:35 PM PDT 24
Finished Jun 06 01:47:49 PM PDT 24
Peak memory 205660 kb
Host smart-33c1569a-e305-4628-aa1e-ee4105cc660e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38166
87748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.3816687748
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.2916988377
Short name T1502
Test name
Test status
Simulation time 10057971509 ps
CPU time 13.44 seconds
Started Jun 06 01:47:32 PM PDT 24
Finished Jun 06 01:47:47 PM PDT 24
Peak memory 205692 kb
Host smart-42e7d33a-ad94-47d6-b8a2-65426af051d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29169
88377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.2916988377
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1369426669
Short name T859
Test name
Test status
Simulation time 10168887132 ps
CPU time 17.13 seconds
Started Jun 06 01:47:23 PM PDT 24
Finished Jun 06 01:47:42 PM PDT 24
Peak memory 205604 kb
Host smart-3e89733c-6bae-4f7e-a6ee-03a63a58fd04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13694
26669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1369426669
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1114309162
Short name T1463
Test name
Test status
Simulation time 10067520883 ps
CPU time 13.67 seconds
Started Jun 06 01:47:28 PM PDT 24
Finished Jun 06 01:47:42 PM PDT 24
Peak memory 205756 kb
Host smart-ae9b28bd-42ff-448d-8416-1ee3078346a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11143
09162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1114309162
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.3103553020
Short name T549
Test name
Test status
Simulation time 10092357546 ps
CPU time 14.14 seconds
Started Jun 06 01:47:34 PM PDT 24
Finished Jun 06 01:47:49 PM PDT 24
Peak memory 205764 kb
Host smart-5d982e17-fad3-44e4-9a0f-d06b31f4ffba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31035
53020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.3103553020
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.4220296789
Short name T222
Test name
Test status
Simulation time 16828616348 ps
CPU time 198.09 seconds
Started Jun 06 01:47:31 PM PDT 24
Finished Jun 06 01:50:50 PM PDT 24
Peak memory 205664 kb
Host smart-5b3980ce-755b-4ed0-82f4-14480df62716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42202
96789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.4220296789
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.2078637297
Short name T1136
Test name
Test status
Simulation time 10147580382 ps
CPU time 13.79 seconds
Started Jun 06 01:47:51 PM PDT 24
Finished Jun 06 01:48:06 PM PDT 24
Peak memory 205664 kb
Host smart-44c0ad53-70dd-4bb1-b88d-79daab611b3b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2078637297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.2078637297
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.1604512748
Short name T1651
Test name
Test status
Simulation time 10092136107 ps
CPU time 16.31 seconds
Started Jun 06 01:47:52 PM PDT 24
Finished Jun 06 01:48:10 PM PDT 24
Peak memory 205800 kb
Host smart-4647351b-92f0-4bec-aa36-887c0469126f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1604512748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.1604512748
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.3635199750
Short name T500
Test name
Test status
Simulation time 10143858980 ps
CPU time 13.18 seconds
Started Jun 06 01:47:51 PM PDT 24
Finished Jun 06 01:48:06 PM PDT 24
Peak memory 205648 kb
Host smart-642cda62-4cab-41a9-93f6-2d1e5ef867aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36351
99750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.3635199750
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.1154239014
Short name T1100
Test name
Test status
Simulation time 13484592330 ps
CPU time 16.92 seconds
Started Jun 06 01:47:29 PM PDT 24
Finished Jun 06 01:47:47 PM PDT 24
Peak memory 205632 kb
Host smart-f22f4f13-5e46-4f88-8ff3-8f886447dbff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1154239014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.1154239014
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.1360772248
Short name T1195
Test name
Test status
Simulation time 23295852843 ps
CPU time 26.84 seconds
Started Jun 06 01:47:38 PM PDT 24
Finished Jun 06 01:48:06 PM PDT 24
Peak memory 205744 kb
Host smart-41da6f78-f8ba-4c64-a68d-88b2c343b870
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1360772248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.1360772248
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2337401596
Short name T621
Test name
Test status
Simulation time 10049901568 ps
CPU time 16.51 seconds
Started Jun 06 01:47:27 PM PDT 24
Finished Jun 06 01:47:44 PM PDT 24
Peak memory 205680 kb
Host smart-2a77d19a-7b96-4e22-af20-9c392c2eb378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23374
01596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2337401596
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.302221040
Short name T1352
Test name
Test status
Simulation time 11108941866 ps
CPU time 17.25 seconds
Started Jun 06 01:47:38 PM PDT 24
Finished Jun 06 01:47:56 PM PDT 24
Peak memory 205756 kb
Host smart-e8909e55-827d-4e4b-a47c-1b7d01a4afb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30222
1040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.302221040
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.756397402
Short name T1035
Test name
Test status
Simulation time 10035463466 ps
CPU time 14.58 seconds
Started Jun 06 01:47:40 PM PDT 24
Finished Jun 06 01:47:55 PM PDT 24
Peak memory 205596 kb
Host smart-d8b1d2de-213e-4797-87dc-c26f08ac388f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75639
7402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.756397402
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.1386002414
Short name T1244
Test name
Test status
Simulation time 10061607131 ps
CPU time 15.05 seconds
Started Jun 06 01:47:32 PM PDT 24
Finished Jun 06 01:47:47 PM PDT 24
Peak memory 205672 kb
Host smart-5f824098-1da3-446b-947c-78c74f0aefd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13860
02414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1386002414
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.976500936
Short name T480
Test name
Test status
Simulation time 10937564942 ps
CPU time 19.26 seconds
Started Jun 06 01:47:38 PM PDT 24
Finished Jun 06 01:47:58 PM PDT 24
Peak memory 205748 kb
Host smart-cb43e259-bfbb-4b94-aad7-e7422c4b83d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97650
0936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.976500936
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.724711097
Short name T1563
Test name
Test status
Simulation time 10102033884 ps
CPU time 15.37 seconds
Started Jun 06 01:47:42 PM PDT 24
Finished Jun 06 01:47:58 PM PDT 24
Peak memory 205660 kb
Host smart-8aa0eb8f-5832-40bb-99db-341027158409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72471
1097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.724711097
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.2027465580
Short name T1942
Test name
Test status
Simulation time 10101050173 ps
CPU time 12.6 seconds
Started Jun 06 01:47:49 PM PDT 24
Finished Jun 06 01:48:03 PM PDT 24
Peak memory 205748 kb
Host smart-747a073b-91a9-462f-be69-c753667051be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20274
65580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.2027465580
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1300939554
Short name T534
Test name
Test status
Simulation time 10077771993 ps
CPU time 15.54 seconds
Started Jun 06 01:47:50 PM PDT 24
Finished Jun 06 01:48:07 PM PDT 24
Peak memory 205604 kb
Host smart-a9539817-f26c-4d5f-b1ff-758796a2da62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13009
39554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1300939554
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.1492501333
Short name T90
Test name
Test status
Simulation time 10163133585 ps
CPU time 14.11 seconds
Started Jun 06 01:47:41 PM PDT 24
Finished Jun 06 01:47:56 PM PDT 24
Peak memory 205628 kb
Host smart-0d5041b3-0ee1-4236-884c-caf4897f8d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14925
01333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.1492501333
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.792921061
Short name T1049
Test name
Test status
Simulation time 10095128619 ps
CPU time 15.47 seconds
Started Jun 06 01:47:42 PM PDT 24
Finished Jun 06 01:47:58 PM PDT 24
Peak memory 205964 kb
Host smart-f9bcb8ae-278b-4353-ac6f-a94d56b295e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79292
1061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.792921061
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.3607018949
Short name T527
Test name
Test status
Simulation time 13210089224 ps
CPU time 16.48 seconds
Started Jun 06 01:47:41 PM PDT 24
Finished Jun 06 01:47:58 PM PDT 24
Peak memory 205732 kb
Host smart-a42aac74-32ef-4375-8f05-bad6016b2d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36070
18949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.3607018949
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.1259888055
Short name T1245
Test name
Test status
Simulation time 10100360154 ps
CPU time 13.22 seconds
Started Jun 06 01:47:42 PM PDT 24
Finished Jun 06 01:47:56 PM PDT 24
Peak memory 205652 kb
Host smart-c01472b3-f5ca-49e2-9f90-fd7801cf81f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12598
88055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1259888055
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.1076609297
Short name T556
Test name
Test status
Simulation time 18461828109 ps
CPU time 255.01 seconds
Started Jun 06 01:47:39 PM PDT 24
Finished Jun 06 01:51:55 PM PDT 24
Peak memory 205644 kb
Host smart-8c79774b-1402-4f58-b762-256d4d227998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10766
09297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.1076609297
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.828079487
Short name T1887
Test name
Test status
Simulation time 10055717009 ps
CPU time 13.54 seconds
Started Jun 06 01:47:41 PM PDT 24
Finished Jun 06 01:47:56 PM PDT 24
Peak memory 205692 kb
Host smart-f547a064-70db-4164-8f5e-2cdf26fcda9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82807
9487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.828079487
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.620666475
Short name T1800
Test name
Test status
Simulation time 10075225912 ps
CPU time 13.49 seconds
Started Jun 06 01:47:40 PM PDT 24
Finished Jun 06 01:47:54 PM PDT 24
Peak memory 205816 kb
Host smart-cf7ac6b4-5906-49ae-9ad9-5b7471c109ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62066
6475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.620666475
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.3816182774
Short name T323
Test name
Test status
Simulation time 10092224015 ps
CPU time 13.58 seconds
Started Jun 06 01:47:40 PM PDT 24
Finished Jun 06 01:47:54 PM PDT 24
Peak memory 205632 kb
Host smart-74bb19cd-75a5-475b-96dc-3544bebaf66e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38161
82774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.3816182774
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1692962270
Short name T487
Test name
Test status
Simulation time 10058631375 ps
CPU time 13.56 seconds
Started Jun 06 01:47:40 PM PDT 24
Finished Jun 06 01:47:55 PM PDT 24
Peak memory 205700 kb
Host smart-4724eb75-093c-46a5-ad03-a9002206d1f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16929
62270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1692962270
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_eop_single_bit_handling.1235777337
Short name T364
Test name
Test status
Simulation time 10060895259 ps
CPU time 14.05 seconds
Started Jun 06 01:47:56 PM PDT 24
Finished Jun 06 01:48:11 PM PDT 24
Peak memory 205776 kb
Host smart-a6f75f8f-202a-4a3f-ad28-1f81612d4a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12357
77337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_eop_single_bit_handling.1235777337
Directory /workspace/14.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.968713816
Short name T641
Test name
Test status
Simulation time 10043397842 ps
CPU time 15.93 seconds
Started Jun 06 01:47:49 PM PDT 24
Finished Jun 06 01:48:06 PM PDT 24
Peak memory 205604 kb
Host smart-6aae8db4-5629-4028-800a-78476581950e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96871
3816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.968713816
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.1934548663
Short name T1236
Test name
Test status
Simulation time 10035311466 ps
CPU time 13.88 seconds
Started Jun 06 01:47:50 PM PDT 24
Finished Jun 06 01:48:04 PM PDT 24
Peak memory 205552 kb
Host smart-381d8f56-b584-4733-997d-0b613f879752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19345
48663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.1934548663
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3633314202
Short name T1375
Test name
Test status
Simulation time 20988038389 ps
CPU time 37.18 seconds
Started Jun 06 01:47:44 PM PDT 24
Finished Jun 06 01:48:22 PM PDT 24
Peak memory 205700 kb
Host smart-90048cc6-f12b-4a81-9fc9-f39e2f4f1757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36333
14202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3633314202
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.1213492019
Short name T1027
Test name
Test status
Simulation time 10122128522 ps
CPU time 12.66 seconds
Started Jun 06 01:47:39 PM PDT 24
Finished Jun 06 01:47:53 PM PDT 24
Peak memory 205604 kb
Host smart-36df74c0-3753-4b31-8eeb-b2bba2785c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12134
92019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.1213492019
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.1649467720
Short name T471
Test name
Test status
Simulation time 10137977165 ps
CPU time 13.22 seconds
Started Jun 06 01:47:41 PM PDT 24
Finished Jun 06 01:47:55 PM PDT 24
Peak memory 205720 kb
Host smart-871e5d9e-e58f-4de4-b4d7-213e557e3831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16494
67720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1649467720
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.3952223209
Short name T1919
Test name
Test status
Simulation time 10060565651 ps
CPU time 14.58 seconds
Started Jun 06 01:47:40 PM PDT 24
Finished Jun 06 01:47:56 PM PDT 24
Peak memory 205604 kb
Host smart-1564122f-6341-4fa3-bd6f-dfb8f7adb03f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39522
23209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.3952223209
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.1464829962
Short name T1229
Test name
Test status
Simulation time 10043103192 ps
CPU time 13.02 seconds
Started Jun 06 01:47:52 PM PDT 24
Finished Jun 06 01:48:06 PM PDT 24
Peak memory 205696 kb
Host smart-d604fae4-c6de-4bb6-8384-0dcbd16cd0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14648
29962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.1464829962
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.750922272
Short name T684
Test name
Test status
Simulation time 10106585787 ps
CPU time 14.84 seconds
Started Jun 06 01:47:49 PM PDT 24
Finished Jun 06 01:48:05 PM PDT 24
Peak memory 205752 kb
Host smart-e434c95b-89c1-42fd-9ec2-9fa8942c4d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75092
2272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.750922272
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1774372033
Short name T1368
Test name
Test status
Simulation time 10131572799 ps
CPU time 13.06 seconds
Started Jun 06 01:47:30 PM PDT 24
Finished Jun 06 01:47:43 PM PDT 24
Peak memory 205640 kb
Host smart-4b4cf757-8db0-4a89-afff-6fd13697652b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17743
72033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1774372033
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.3532131699
Short name T1817
Test name
Test status
Simulation time 10081377152 ps
CPU time 13.24 seconds
Started Jun 06 01:47:55 PM PDT 24
Finished Jun 06 01:48:09 PM PDT 24
Peak memory 205776 kb
Host smart-848b4a0e-b6da-4a4b-96f2-dcc571e93cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35321
31699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.3532131699
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.1065067898
Short name T1613
Test name
Test status
Simulation time 10067527640 ps
CPU time 14.68 seconds
Started Jun 06 01:47:39 PM PDT 24
Finished Jun 06 01:47:54 PM PDT 24
Peak memory 205628 kb
Host smart-41bc00ac-67d9-46c7-a8a9-a1f544895cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10650
67898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.1065067898
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.2367041506
Short name T927
Test name
Test status
Simulation time 20324892636 ps
CPU time 293.93 seconds
Started Jun 06 01:47:40 PM PDT 24
Finished Jun 06 01:52:34 PM PDT 24
Peak memory 205672 kb
Host smart-6c129cd4-f4b7-4b21-9afe-2b0af30b4686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23670
41506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.2367041506
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.4191714758
Short name T337
Test name
Test status
Simulation time 10196565916 ps
CPU time 14.18 seconds
Started Jun 06 01:47:59 PM PDT 24
Finished Jun 06 01:48:14 PM PDT 24
Peak memory 205652 kb
Host smart-470fcb3a-859b-4cc8-b3a8-756f1584731b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4191714758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.4191714758
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.422875931
Short name T848
Test name
Test status
Simulation time 10062936821 ps
CPU time 14.28 seconds
Started Jun 06 01:48:03 PM PDT 24
Finished Jun 06 01:48:18 PM PDT 24
Peak memory 205744 kb
Host smart-d775e43b-5cab-4820-8d3c-776908fff342
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=422875931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.422875931
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.3287048566
Short name T1086
Test name
Test status
Simulation time 10139613260 ps
CPU time 13.59 seconds
Started Jun 06 01:48:08 PM PDT 24
Finished Jun 06 01:48:22 PM PDT 24
Peak memory 205732 kb
Host smart-b5a1ddd7-e198-403b-abaa-9cd030b0b1df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32870
48566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.3287048566
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.2144945816
Short name T741
Test name
Test status
Simulation time 14258249995 ps
CPU time 19.09 seconds
Started Jun 06 01:47:50 PM PDT 24
Finished Jun 06 01:48:10 PM PDT 24
Peak memory 205724 kb
Host smart-7532433b-3c91-4554-9b72-9e015249dc3a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2144945816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.2144945816
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.976863048
Short name T1736
Test name
Test status
Simulation time 23274107913 ps
CPU time 29.93 seconds
Started Jun 06 01:47:52 PM PDT 24
Finished Jun 06 01:48:23 PM PDT 24
Peak memory 205792 kb
Host smart-a6554a79-b8e0-4ec7-bdcb-181b237e2e5f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=976863048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.976863048
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2834948312
Short name T863
Test name
Test status
Simulation time 10059427768 ps
CPU time 13.81 seconds
Started Jun 06 01:47:50 PM PDT 24
Finished Jun 06 01:48:05 PM PDT 24
Peak memory 205624 kb
Host smart-7357fb6b-4314-4fbe-8623-44eb0d62fdc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28349
48312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2834948312
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.2436408572
Short name T215
Test name
Test status
Simulation time 10085885667 ps
CPU time 16.86 seconds
Started Jun 06 01:47:51 PM PDT 24
Finished Jun 06 01:48:09 PM PDT 24
Peak memory 205708 kb
Host smart-371f1392-2ff8-420c-80dc-4280bac53510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24364
08572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.2436408572
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.229607474
Short name T958
Test name
Test status
Simulation time 11379539977 ps
CPU time 17.09 seconds
Started Jun 06 01:47:52 PM PDT 24
Finished Jun 06 01:48:10 PM PDT 24
Peak memory 205704 kb
Host smart-1c9f0c62-d6bb-4c0d-a1f8-9536a2d8c69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22960
7474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.229607474
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.897919190
Short name T1580
Test name
Test status
Simulation time 10042006506 ps
CPU time 16.01 seconds
Started Jun 06 01:47:56 PM PDT 24
Finished Jun 06 01:48:13 PM PDT 24
Peak memory 205668 kb
Host smart-2df4d0f4-7953-461b-81e3-e67aa1ce66d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89791
9190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.897919190
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.254378908
Short name T1762
Test name
Test status
Simulation time 10091518717 ps
CPU time 13.34 seconds
Started Jun 06 01:47:52 PM PDT 24
Finished Jun 06 01:48:07 PM PDT 24
Peak memory 205628 kb
Host smart-2d07a5e6-9a01-42d1-8b75-9743194b27ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25437
8908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.254378908
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.528358588
Short name T1829
Test name
Test status
Simulation time 10806609892 ps
CPU time 18.76 seconds
Started Jun 06 01:47:54 PM PDT 24
Finished Jun 06 01:48:14 PM PDT 24
Peak memory 205772 kb
Host smart-76c7aabe-a067-4f43-b8fd-40c435d946e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52835
8588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.528358588
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.1193497695
Short name T1805
Test name
Test status
Simulation time 10063608052 ps
CPU time 13.39 seconds
Started Jun 06 01:48:00 PM PDT 24
Finished Jun 06 01:48:14 PM PDT 24
Peak memory 205764 kb
Host smart-a3a5f8ee-d0c6-498a-87a7-4f6825e19fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11934
97695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.1193497695
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.696459537
Short name T1690
Test name
Test status
Simulation time 10041270083 ps
CPU time 15.03 seconds
Started Jun 06 01:48:04 PM PDT 24
Finished Jun 06 01:48:20 PM PDT 24
Peak memory 205752 kb
Host smart-9ab7eb0f-ff99-46d1-8d64-d5412dc80f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69645
9537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.696459537
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.1200571797
Short name T1241
Test name
Test status
Simulation time 10197466341 ps
CPU time 14.77 seconds
Started Jun 06 01:47:54 PM PDT 24
Finished Jun 06 01:48:09 PM PDT 24
Peak memory 205780 kb
Host smart-4d001759-a43c-40e7-a3c2-75f404fd7b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12005
71797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.1200571797
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.3726588607
Short name T1554
Test name
Test status
Simulation time 10189499381 ps
CPU time 16.19 seconds
Started Jun 06 01:47:54 PM PDT 24
Finished Jun 06 01:48:11 PM PDT 24
Peak memory 205704 kb
Host smart-260e698f-d0a0-4e79-ac79-3624d39cff9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37265
88607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.3726588607
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.4217341230
Short name T1559
Test name
Test status
Simulation time 13174336809 ps
CPU time 18.66 seconds
Started Jun 06 01:47:50 PM PDT 24
Finished Jun 06 01:48:10 PM PDT 24
Peak memory 205752 kb
Host smart-272ae85d-8449-4c39-af2e-e06375ba6336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42173
41230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.4217341230
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.2252687348
Short name T1279
Test name
Test status
Simulation time 10092479863 ps
CPU time 12.57 seconds
Started Jun 06 01:47:51 PM PDT 24
Finished Jun 06 01:48:05 PM PDT 24
Peak memory 205632 kb
Host smart-9198799b-8bfa-4b40-940c-089dda098299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22526
87348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.2252687348
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.1419631562
Short name T1200
Test name
Test status
Simulation time 24169380307 ps
CPU time 430.83 seconds
Started Jun 06 01:47:52 PM PDT 24
Finished Jun 06 01:55:04 PM PDT 24
Peak memory 205636 kb
Host smart-a8a57a8b-b02b-4137-a03f-31e99f19cccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14196
31562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.1419631562
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.107836210
Short name T822
Test name
Test status
Simulation time 10062910366 ps
CPU time 13.38 seconds
Started Jun 06 01:47:50 PM PDT 24
Finished Jun 06 01:48:04 PM PDT 24
Peak memory 205596 kb
Host smart-be5ec3d0-878d-4ec7-9a1d-e44ddd9bb406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10783
6210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.107836210
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.3186848459
Short name T1655
Test name
Test status
Simulation time 10086924806 ps
CPU time 16.75 seconds
Started Jun 06 01:47:54 PM PDT 24
Finished Jun 06 01:48:11 PM PDT 24
Peak memory 205780 kb
Host smart-1bf13aeb-005a-4ba7-8d46-f83da1c023ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31868
48459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.3186848459
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.3980960095
Short name T946
Test name
Test status
Simulation time 10089174701 ps
CPU time 15.15 seconds
Started Jun 06 01:47:50 PM PDT 24
Finished Jun 06 01:48:05 PM PDT 24
Peak memory 205712 kb
Host smart-cf229c7e-2da5-47a5-949c-79217e00523d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39809
60095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3980960095
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.1240148881
Short name T376
Test name
Test status
Simulation time 10062865235 ps
CPU time 15.42 seconds
Started Jun 06 01:47:53 PM PDT 24
Finished Jun 06 01:48:10 PM PDT 24
Peak memory 205620 kb
Host smart-521e722b-73b1-4c9a-8eec-fedd487ec396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12401
48881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.1240148881
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.3796210119
Short name T605
Test name
Test status
Simulation time 10111250053 ps
CPU time 13.5 seconds
Started Jun 06 01:47:58 PM PDT 24
Finished Jun 06 01:48:12 PM PDT 24
Peak memory 205764 kb
Host smart-785f844c-2aba-4fee-a041-53f803396e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37962
10119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.3796210119
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_eop_single_bit_handling.1446333394
Short name T505
Test name
Test status
Simulation time 10066841366 ps
CPU time 13.22 seconds
Started Jun 06 01:47:58 PM PDT 24
Finished Jun 06 01:48:12 PM PDT 24
Peak memory 205672 kb
Host smart-c80069ed-2367-4af8-a1d6-9b329d7416b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14463
33394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_eop_single_bit_handling.1446333394
Directory /workspace/15.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.3828678326
Short name T1664
Test name
Test status
Simulation time 10055641282 ps
CPU time 14.59 seconds
Started Jun 06 01:47:57 PM PDT 24
Finished Jun 06 01:48:13 PM PDT 24
Peak memory 205644 kb
Host smart-4a47db1b-67b3-42b7-8e46-1ce7d42b7eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38286
78326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.3828678326
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.2930066690
Short name T1868
Test name
Test status
Simulation time 10052207803 ps
CPU time 13.75 seconds
Started Jun 06 01:48:06 PM PDT 24
Finished Jun 06 01:48:21 PM PDT 24
Peak memory 205728 kb
Host smart-839db305-3125-4f16-aadd-6011154cc310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29300
66690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.2930066690
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.2800922163
Short name T879
Test name
Test status
Simulation time 28250286548 ps
CPU time 56.79 seconds
Started Jun 06 01:47:52 PM PDT 24
Finished Jun 06 01:48:50 PM PDT 24
Peak memory 205628 kb
Host smart-50c2d048-f731-4673-ad6b-f26cf3a31ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28009
22163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.2800922163
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.2396590801
Short name T432
Test name
Test status
Simulation time 10071022334 ps
CPU time 12.82 seconds
Started Jun 06 01:47:49 PM PDT 24
Finished Jun 06 01:48:02 PM PDT 24
Peak memory 205692 kb
Host smart-8b661c0f-291c-4e42-b008-950941b87a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23965
90801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2396590801
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.1989375913
Short name T1459
Test name
Test status
Simulation time 10069689014 ps
CPU time 14.24 seconds
Started Jun 06 01:47:56 PM PDT 24
Finished Jun 06 01:48:11 PM PDT 24
Peak memory 205716 kb
Host smart-dd3e0beb-c05b-475b-ab03-819167bd3dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19893
75913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1989375913
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.2938812299
Short name T622
Test name
Test status
Simulation time 10082907243 ps
CPU time 15.79 seconds
Started Jun 06 01:47:52 PM PDT 24
Finished Jun 06 01:48:09 PM PDT 24
Peak memory 205744 kb
Host smart-c4a6dfb0-f2f5-4ccb-a6d9-0684af7aafe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29388
12299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.2938812299
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.198653223
Short name T1513
Test name
Test status
Simulation time 10044912423 ps
CPU time 14.61 seconds
Started Jun 06 01:48:02 PM PDT 24
Finished Jun 06 01:48:17 PM PDT 24
Peak memory 205648 kb
Host smart-8b687a98-6aa2-4150-af84-320898c616ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19865
3223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.198653223
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.1992463880
Short name T834
Test name
Test status
Simulation time 10067022035 ps
CPU time 13.86 seconds
Started Jun 06 01:48:05 PM PDT 24
Finished Jun 06 01:48:19 PM PDT 24
Peak memory 205684 kb
Host smart-d38af67d-d1a1-4989-81e8-5472234f0a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19924
63880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.1992463880
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2023024205
Short name T1961
Test name
Test status
Simulation time 10159524220 ps
CPU time 14.07 seconds
Started Jun 06 01:47:50 PM PDT 24
Finished Jun 06 01:48:05 PM PDT 24
Peak memory 205684 kb
Host smart-ed10901e-0dc8-41b6-90e4-ed77dbfc24c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20230
24205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2023024205
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1820318366
Short name T1248
Test name
Test status
Simulation time 10091788615 ps
CPU time 14.13 seconds
Started Jun 06 01:47:58 PM PDT 24
Finished Jun 06 01:48:13 PM PDT 24
Peak memory 205712 kb
Host smart-23e501a1-e22d-4a93-b94f-9d9043e5bce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18203
18366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1820318366
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.3018761933
Short name T567
Test name
Test status
Simulation time 10083927332 ps
CPU time 13.85 seconds
Started Jun 06 01:47:53 PM PDT 24
Finished Jun 06 01:48:07 PM PDT 24
Peak memory 205716 kb
Host smart-ced55276-c320-445f-bb37-31e472e72e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30187
61933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.3018761933
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.2446215953
Short name T1104
Test name
Test status
Simulation time 21015609126 ps
CPU time 302.44 seconds
Started Jun 06 01:47:53 PM PDT 24
Finished Jun 06 01:52:56 PM PDT 24
Peak memory 205672 kb
Host smart-8bd2228e-d661-4aed-a6f0-0f0c6531ebfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24462
15953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.2446215953
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.1195697346
Short name T867
Test name
Test status
Simulation time 10147393381 ps
CPU time 14.55 seconds
Started Jun 06 01:48:17 PM PDT 24
Finished Jun 06 01:48:33 PM PDT 24
Peak memory 205764 kb
Host smart-4d66e80b-a3db-4a3d-a981-cf79b184e838
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1195697346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.1195697346
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.577712161
Short name T1562
Test name
Test status
Simulation time 10097925996 ps
CPU time 13.21 seconds
Started Jun 06 01:48:14 PM PDT 24
Finished Jun 06 01:48:28 PM PDT 24
Peak memory 205768 kb
Host smart-f3f2d9e8-d33b-42ea-b382-b2602b12b429
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=577712161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.577712161
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.1181151359
Short name T2011
Test name
Test status
Simulation time 10116978895 ps
CPU time 17.07 seconds
Started Jun 06 01:48:15 PM PDT 24
Finished Jun 06 01:48:33 PM PDT 24
Peak memory 205760 kb
Host smart-a39c3cd0-6b8a-4a29-8c13-a3c16cbce90c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11811
51359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.1181151359
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.1484476995
Short name T911
Test name
Test status
Simulation time 13336963589 ps
CPU time 16.68 seconds
Started Jun 06 01:48:01 PM PDT 24
Finished Jun 06 01:48:18 PM PDT 24
Peak memory 205748 kb
Host smart-8a59a621-5ab2-4e8f-9986-3379dc3bee4b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1484476995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.1484476995
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.327892205
Short name T212
Test name
Test status
Simulation time 23264519846 ps
CPU time 27.42 seconds
Started Jun 06 01:47:58 PM PDT 24
Finished Jun 06 01:48:26 PM PDT 24
Peak memory 205624 kb
Host smart-8f13e4ce-8e1a-43e5-8c15-069c0b4b3712
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=327892205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.327892205
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.305131488
Short name T1456
Test name
Test status
Simulation time 10062170819 ps
CPU time 16.85 seconds
Started Jun 06 01:47:58 PM PDT 24
Finished Jun 06 01:48:16 PM PDT 24
Peak memory 205580 kb
Host smart-2bb0b587-d5a3-4922-ba6f-66e3bf90c79f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30513
1488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.305131488
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1538418336
Short name T699
Test name
Test status
Simulation time 10148038901 ps
CPU time 14.1 seconds
Started Jun 06 01:48:01 PM PDT 24
Finished Jun 06 01:48:16 PM PDT 24
Peak memory 205712 kb
Host smart-3b8db4ea-e8c3-4f88-84ce-34430ac8166b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15384
18336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1538418336
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.1771654617
Short name T1002
Test name
Test status
Simulation time 10042211685 ps
CPU time 15.93 seconds
Started Jun 06 01:47:59 PM PDT 24
Finished Jun 06 01:48:15 PM PDT 24
Peak memory 205644 kb
Host smart-47fdfb9c-a29e-4b95-8e26-f65b81c8ea59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17716
54617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.1771654617
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1722169781
Short name T609
Test name
Test status
Simulation time 10065671430 ps
CPU time 13.39 seconds
Started Jun 06 01:47:59 PM PDT 24
Finished Jun 06 01:48:13 PM PDT 24
Peak memory 205560 kb
Host smart-11b07adb-b1cd-4ad8-b18c-aeda113fd329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17221
69781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1722169781
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.1523255407
Short name T966
Test name
Test status
Simulation time 10806490662 ps
CPU time 14.88 seconds
Started Jun 06 01:47:58 PM PDT 24
Finished Jun 06 01:48:14 PM PDT 24
Peak memory 205652 kb
Host smart-436fd47b-1544-4f8b-b896-4037f4ade9be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15232
55407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.1523255407
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.2265227517
Short name T1618
Test name
Test status
Simulation time 10097525323 ps
CPU time 14.17 seconds
Started Jun 06 01:48:03 PM PDT 24
Finished Jun 06 01:48:18 PM PDT 24
Peak memory 205068 kb
Host smart-c25dcbf6-38ba-413d-a3e3-8624d29c8a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22652
27517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.2265227517
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3055994679
Short name T1015
Test name
Test status
Simulation time 10084664408 ps
CPU time 13.18 seconds
Started Jun 06 01:48:11 PM PDT 24
Finished Jun 06 01:48:25 PM PDT 24
Peak memory 205692 kb
Host smart-15d62d92-dc99-4a80-93cf-5f6f2568122d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30559
94679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3055994679
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.459537235
Short name T1024
Test name
Test status
Simulation time 10044150025 ps
CPU time 13.66 seconds
Started Jun 06 01:48:14 PM PDT 24
Finished Jun 06 01:48:29 PM PDT 24
Peak memory 205684 kb
Host smart-cf39fbed-fe78-44ca-b345-c48047eb7a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45953
7235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.459537235
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.3356541302
Short name T746
Test name
Test status
Simulation time 10063877351 ps
CPU time 14.23 seconds
Started Jun 06 01:47:59 PM PDT 24
Finished Jun 06 01:48:14 PM PDT 24
Peak memory 205808 kb
Host smart-bc808713-9081-47ec-a6a7-86a9176887fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33565
41302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.3356541302
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.3587912875
Short name T1018
Test name
Test status
Simulation time 10175671596 ps
CPU time 15.28 seconds
Started Jun 06 01:48:00 PM PDT 24
Finished Jun 06 01:48:16 PM PDT 24
Peak memory 205736 kb
Host smart-06590e53-c711-45ad-aa97-14f0b38645e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35879
12875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3587912875
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.1015569255
Short name T933
Test name
Test status
Simulation time 13186148021 ps
CPU time 15.9 seconds
Started Jun 06 01:48:02 PM PDT 24
Finished Jun 06 01:48:18 PM PDT 24
Peak memory 205748 kb
Host smart-f2607866-631b-4152-bd4a-d3ca036fc7bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10155
69255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.1015569255
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.2187908087
Short name T768
Test name
Test status
Simulation time 10105975472 ps
CPU time 16.13 seconds
Started Jun 06 01:48:01 PM PDT 24
Finished Jun 06 01:48:18 PM PDT 24
Peak memory 205732 kb
Host smart-96619538-d2b0-4cc0-874e-24e783244e46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21879
08087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.2187908087
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.2191289817
Short name T1710
Test name
Test status
Simulation time 22830633404 ps
CPU time 375.26 seconds
Started Jun 06 01:48:08 PM PDT 24
Finished Jun 06 01:54:24 PM PDT 24
Peak memory 205656 kb
Host smart-18b944a0-09ad-48a9-b5fa-d1fed587ea5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21912
89817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.2191289817
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.2044831112
Short name T515
Test name
Test status
Simulation time 10071983316 ps
CPU time 14.53 seconds
Started Jun 06 01:48:00 PM PDT 24
Finished Jun 06 01:48:16 PM PDT 24
Peak memory 205748 kb
Host smart-1df97569-805c-449f-99a2-3f71aa952e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20448
31112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.2044831112
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.2373952923
Short name T1822
Test name
Test status
Simulation time 10109449381 ps
CPU time 13.84 seconds
Started Jun 06 01:48:00 PM PDT 24
Finished Jun 06 01:48:15 PM PDT 24
Peak memory 205744 kb
Host smart-f7a4cbca-59b5-442f-a6c9-33de61470a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23739
52923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2373952923
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.1832556273
Short name T2018
Test name
Test status
Simulation time 10072232849 ps
CPU time 12.91 seconds
Started Jun 06 01:48:05 PM PDT 24
Finished Jun 06 01:48:19 PM PDT 24
Peak memory 205768 kb
Host smart-471c62be-1ecd-4e53-aa0c-f09b98fbb8c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18325
56273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.1832556273
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.2228386713
Short name T1883
Test name
Test status
Simulation time 10101713509 ps
CPU time 14.05 seconds
Started Jun 06 01:48:06 PM PDT 24
Finished Jun 06 01:48:21 PM PDT 24
Peak memory 205736 kb
Host smart-25fbd80f-d13e-498a-9c57-2d81ff9ad38f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22283
86713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.2228386713
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.1324239381
Short name T1870
Test name
Test status
Simulation time 10153123475 ps
CPU time 15.58 seconds
Started Jun 06 01:48:07 PM PDT 24
Finished Jun 06 01:48:24 PM PDT 24
Peak memory 205644 kb
Host smart-f121dda1-4b4d-4f48-bfd1-7a84dde6b6ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13242
39381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1324239381
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_eop_single_bit_handling.4157767008
Short name T1620
Test name
Test status
Simulation time 10064123619 ps
CPU time 13.21 seconds
Started Jun 06 01:48:14 PM PDT 24
Finished Jun 06 01:48:28 PM PDT 24
Peak memory 205764 kb
Host smart-b1cfe884-2120-4f17-af98-3d0d66edd836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41577
67008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_eop_single_bit_handling.4157767008
Directory /workspace/16.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.799717839
Short name T518
Test name
Test status
Simulation time 10083293288 ps
CPU time 14.58 seconds
Started Jun 06 01:48:14 PM PDT 24
Finished Jun 06 01:48:30 PM PDT 24
Peak memory 205716 kb
Host smart-f429dc2f-1ab4-4a3a-9f7f-7a4cc3d58c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79971
7839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.799717839
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2871653654
Short name T26
Test name
Test status
Simulation time 10085507218 ps
CPU time 13.47 seconds
Started Jun 06 01:48:14 PM PDT 24
Finished Jun 06 01:48:28 PM PDT 24
Peak memory 205660 kb
Host smart-b022c6db-db38-441f-a195-1bdcdcb1ee87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28716
53654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2871653654
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3887833172
Short name T1807
Test name
Test status
Simulation time 21339168256 ps
CPU time 42.12 seconds
Started Jun 06 01:48:14 PM PDT 24
Finished Jun 06 01:48:57 PM PDT 24
Peak memory 205652 kb
Host smart-9f5d638a-56e4-4b8a-a3dd-10800466f862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38878
33172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3887833172
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.738494221
Short name T623
Test name
Test status
Simulation time 10083342552 ps
CPU time 17.06 seconds
Started Jun 06 01:48:12 PM PDT 24
Finished Jun 06 01:48:30 PM PDT 24
Peak memory 205712 kb
Host smart-9e93ad70-7afd-4f34-afb7-2eb6c4bd3807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73849
4221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.738494221
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.3521640361
Short name T1103
Test name
Test status
Simulation time 10140763176 ps
CPU time 16.42 seconds
Started Jun 06 01:48:19 PM PDT 24
Finished Jun 06 01:48:36 PM PDT 24
Peak memory 205736 kb
Host smart-a4c905cc-2ca5-4bfd-b6d8-c5f052e34f0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35216
40361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.3521640361
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.4023657654
Short name T1334
Test name
Test status
Simulation time 10127097304 ps
CPU time 14.68 seconds
Started Jun 06 01:48:18 PM PDT 24
Finished Jun 06 01:48:33 PM PDT 24
Peak memory 205752 kb
Host smart-9cba0df0-bf80-4ea8-b5ba-2315c7bb2124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40236
57654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.4023657654
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.3559910378
Short name T1738
Test name
Test status
Simulation time 10048959914 ps
CPU time 15.56 seconds
Started Jun 06 01:48:16 PM PDT 24
Finished Jun 06 01:48:32 PM PDT 24
Peak memory 205636 kb
Host smart-38db21d2-023b-4d9d-9ec4-406c3bd9c486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35599
10378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.3559910378
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.2837419012
Short name T1635
Test name
Test status
Simulation time 10053042259 ps
CPU time 15.1 seconds
Started Jun 06 01:48:12 PM PDT 24
Finished Jun 06 01:48:28 PM PDT 24
Peak memory 205676 kb
Host smart-a86a1c95-4a76-402a-99e9-70ce1f47f5e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28374
19012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.2837419012
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.235901034
Short name T1658
Test name
Test status
Simulation time 10052652980 ps
CPU time 14.27 seconds
Started Jun 06 01:48:13 PM PDT 24
Finished Jun 06 01:48:29 PM PDT 24
Peak memory 205636 kb
Host smart-b7ae43d4-612f-42bb-8ec9-043b8edc3a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23590
1034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.235901034
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.887877711
Short name T731
Test name
Test status
Simulation time 10145856257 ps
CPU time 13.12 seconds
Started Jun 06 01:48:00 PM PDT 24
Finished Jun 06 01:48:14 PM PDT 24
Peak memory 205728 kb
Host smart-8fce0b47-6279-49c7-9cb3-6a2852aeb73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88787
7711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.887877711
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2928220525
Short name T1077
Test name
Test status
Simulation time 10121827196 ps
CPU time 16.79 seconds
Started Jun 06 01:48:13 PM PDT 24
Finished Jun 06 01:48:31 PM PDT 24
Peak memory 205668 kb
Host smart-4365074b-c5de-49d2-888a-17d9ce3c824e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29282
20525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2928220525
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.3081344094
Short name T1003
Test name
Test status
Simulation time 10057822433 ps
CPU time 14.06 seconds
Started Jun 06 01:48:13 PM PDT 24
Finished Jun 06 01:48:28 PM PDT 24
Peak memory 205672 kb
Host smart-c38c9f1f-ce34-4275-bb41-1cacaadd053f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30813
44094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.3081344094
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.3400562614
Short name T1561
Test name
Test status
Simulation time 25021469125 ps
CPU time 152.19 seconds
Started Jun 06 01:48:14 PM PDT 24
Finished Jun 06 01:50:48 PM PDT 24
Peak memory 205728 kb
Host smart-3ae1ef80-dea1-429b-8bd5-c156e2cc3ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34005
62614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.3400562614
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.1437251879
Short name T764
Test name
Test status
Simulation time 10194258725 ps
CPU time 13.24 seconds
Started Jun 06 01:48:25 PM PDT 24
Finished Jun 06 01:48:40 PM PDT 24
Peak memory 205736 kb
Host smart-45ae2bfa-e536-489a-be5e-4cf02fb8c158
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1437251879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.1437251879
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.2345853895
Short name T1875
Test name
Test status
Simulation time 10052219538 ps
CPU time 13.95 seconds
Started Jun 06 01:48:24 PM PDT 24
Finished Jun 06 01:48:38 PM PDT 24
Peak memory 205648 kb
Host smart-c347af8a-3325-4f56-9d72-55a49c1bf0f8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2345853895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.2345853895
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.1096012488
Short name T804
Test name
Test status
Simulation time 10130839387 ps
CPU time 14.26 seconds
Started Jun 06 01:48:23 PM PDT 24
Finished Jun 06 01:48:38 PM PDT 24
Peak memory 205672 kb
Host smart-80c6dc19-db92-4700-b433-3851396eff18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10960
12488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.1096012488
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.4018344631
Short name T1773
Test name
Test status
Simulation time 14335341786 ps
CPU time 17.52 seconds
Started Jun 06 01:48:14 PM PDT 24
Finished Jun 06 01:48:33 PM PDT 24
Peak memory 205744 kb
Host smart-b2e10174-ded9-4091-9893-4798ec058af2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4018344631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.4018344631
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.1567231310
Short name T969
Test name
Test status
Simulation time 23229141760 ps
CPU time 26.41 seconds
Started Jun 06 01:48:13 PM PDT 24
Finished Jun 06 01:48:41 PM PDT 24
Peak memory 205704 kb
Host smart-5f60a212-7eb0-4873-b244-b8990f1657f1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1567231310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.1567231310
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.2931253248
Short name T413
Test name
Test status
Simulation time 10056097375 ps
CPU time 15.17 seconds
Started Jun 06 01:48:15 PM PDT 24
Finished Jun 06 01:48:31 PM PDT 24
Peak memory 205652 kb
Host smart-22bf96a8-9270-40ed-b55e-38e96b8fc2f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29312
53248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.2931253248
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.3287437359
Short name T310
Test name
Test status
Simulation time 10046946938 ps
CPU time 15.82 seconds
Started Jun 06 01:48:26 PM PDT 24
Finished Jun 06 01:48:43 PM PDT 24
Peak memory 205708 kb
Host smart-75be5a3f-d3cc-4cbd-94b0-da968f0e29f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32874
37359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.3287437359
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.2661395492
Short name T1545
Test name
Test status
Simulation time 10042194885 ps
CPU time 13.71 seconds
Started Jun 06 01:48:13 PM PDT 24
Finished Jun 06 01:48:28 PM PDT 24
Peak memory 205712 kb
Host smart-5a338815-6e88-4573-9d45-1060b5a334dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26613
95492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2661395492
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.1311903865
Short name T378
Test name
Test status
Simulation time 10780237546 ps
CPU time 14.6 seconds
Started Jun 06 01:48:14 PM PDT 24
Finished Jun 06 01:48:29 PM PDT 24
Peak memory 205668 kb
Host smart-573f5eaf-cc9c-4ccb-bc2b-d39ff19246e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13119
03865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.1311903865
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.3153583641
Short name T1612
Test name
Test status
Simulation time 10091278499 ps
CPU time 16.19 seconds
Started Jun 06 01:48:14 PM PDT 24
Finished Jun 06 01:48:31 PM PDT 24
Peak memory 205644 kb
Host smart-d74ce5bb-8922-4ccc-ba9c-a32ba226a7e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31535
83641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.3153583641
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.289506993
Short name T1819
Test name
Test status
Simulation time 10118792819 ps
CPU time 15.51 seconds
Started Jun 06 01:48:27 PM PDT 24
Finished Jun 06 01:48:43 PM PDT 24
Peak memory 205600 kb
Host smart-01cbe371-9994-4a56-8e9d-fbab9467f479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28950
6993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.289506993
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.4230098340
Short name T349
Test name
Test status
Simulation time 10041531952 ps
CPU time 15.3 seconds
Started Jun 06 01:48:25 PM PDT 24
Finished Jun 06 01:48:42 PM PDT 24
Peak memory 205720 kb
Host smart-2887d5da-fc79-4af0-938d-966f476593ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42300
98340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.4230098340
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.2447406153
Short name T686
Test name
Test status
Simulation time 10065123579 ps
CPU time 14.72 seconds
Started Jun 06 01:48:12 PM PDT 24
Finished Jun 06 01:48:28 PM PDT 24
Peak memory 205712 kb
Host smart-1b63284d-ac2d-4b53-8e0a-3df997ad305f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24474
06153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.2447406153
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.415580827
Short name T2003
Test name
Test status
Simulation time 10120369409 ps
CPU time 15.06 seconds
Started Jun 06 01:48:14 PM PDT 24
Finished Jun 06 01:48:30 PM PDT 24
Peak memory 205592 kb
Host smart-f529002e-90d8-481c-a4e0-161fa99dd69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41558
0827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.415580827
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.1947596531
Short name T2002
Test name
Test status
Simulation time 13220967128 ps
CPU time 18.83 seconds
Started Jun 06 01:48:22 PM PDT 24
Finished Jun 06 01:48:42 PM PDT 24
Peak memory 205652 kb
Host smart-82173075-a621-43f9-9c33-f8c2c591c29f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19475
96531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.1947596531
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.4002211164
Short name T909
Test name
Test status
Simulation time 10089912666 ps
CPU time 14.82 seconds
Started Jun 06 01:48:33 PM PDT 24
Finished Jun 06 01:48:49 PM PDT 24
Peak memory 205592 kb
Host smart-f01f6166-fb66-43af-9488-80983422d27f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40022
11164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.4002211164
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.2223300010
Short name T366
Test name
Test status
Simulation time 21017932463 ps
CPU time 311.15 seconds
Started Jun 06 01:48:28 PM PDT 24
Finished Jun 06 01:53:41 PM PDT 24
Peak memory 205624 kb
Host smart-f668daf3-5d26-45a1-84e2-8900fb3b173f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22233
00010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.2223300010
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.4149416694
Short name T535
Test name
Test status
Simulation time 10047220435 ps
CPU time 13.85 seconds
Started Jun 06 01:48:26 PM PDT 24
Finished Jun 06 01:48:41 PM PDT 24
Peak memory 205620 kb
Host smart-bc13ff87-7af0-4c84-8187-3f58f572c291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41494
16694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.4149416694
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.3466450421
Short name T111
Test name
Test status
Simulation time 10150532224 ps
CPU time 14.81 seconds
Started Jun 06 01:48:25 PM PDT 24
Finished Jun 06 01:48:42 PM PDT 24
Peak memory 205696 kb
Host smart-beaa3f72-31ea-4217-80fa-fdc43cdc9f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34664
50421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.3466450421
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.2159136459
Short name T856
Test name
Test status
Simulation time 10077848053 ps
CPU time 15.18 seconds
Started Jun 06 01:48:22 PM PDT 24
Finished Jun 06 01:48:38 PM PDT 24
Peak memory 205756 kb
Host smart-7b539f14-0e4b-45f8-8608-3e41cabaaa47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21591
36459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.2159136459
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.555744555
Short name T1367
Test name
Test status
Simulation time 10074922837 ps
CPU time 12.87 seconds
Started Jun 06 01:48:27 PM PDT 24
Finished Jun 06 01:48:41 PM PDT 24
Peak memory 205700 kb
Host smart-9c79e62a-6d79-4d5c-8c48-8bb1d19c3b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55574
4555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.555744555
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.644964070
Short name T536
Test name
Test status
Simulation time 10092583647 ps
CPU time 15.41 seconds
Started Jun 06 01:48:24 PM PDT 24
Finished Jun 06 01:48:41 PM PDT 24
Peak memory 205600 kb
Host smart-764c40e9-53d4-49be-9406-e6c77b38b2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64496
4070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.644964070
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.3438257830
Short name T827
Test name
Test status
Simulation time 10129989881 ps
CPU time 13.91 seconds
Started Jun 06 01:48:25 PM PDT 24
Finished Jun 06 01:48:40 PM PDT 24
Peak memory 205672 kb
Host smart-3dfa025a-4d03-4a58-8d8d-09f1e5836929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34382
57830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.3438257830
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_eop_single_bit_handling.3240728878
Short name T30
Test name
Test status
Simulation time 10088911428 ps
CPU time 14.41 seconds
Started Jun 06 01:48:24 PM PDT 24
Finished Jun 06 01:48:40 PM PDT 24
Peak memory 205728 kb
Host smart-523f31f9-9c13-4084-86b8-0d17f62a0274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32407
28878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_eop_single_bit_handling.3240728878
Directory /workspace/17.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.1325502102
Short name T1894
Test name
Test status
Simulation time 10042282780 ps
CPU time 12.65 seconds
Started Jun 06 01:48:33 PM PDT 24
Finished Jun 06 01:48:47 PM PDT 24
Peak memory 205628 kb
Host smart-610be234-48df-4007-8c3d-be35279384b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13255
02102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.1325502102
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.4220606186
Short name T1672
Test name
Test status
Simulation time 10058122944 ps
CPU time 14.91 seconds
Started Jun 06 01:48:25 PM PDT 24
Finished Jun 06 01:48:41 PM PDT 24
Peak memory 205612 kb
Host smart-0dd7ca40-b4f9-4339-b294-a6e447668b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42206
06186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.4220606186
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.2706737726
Short name T769
Test name
Test status
Simulation time 17556182903 ps
CPU time 31.48 seconds
Started Jun 06 01:48:24 PM PDT 24
Finished Jun 06 01:48:57 PM PDT 24
Peak memory 205680 kb
Host smart-9e4f35e8-f64c-4f83-ba76-4c55c516d4fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27067
37726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.2706737726
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.382461864
Short name T1569
Test name
Test status
Simulation time 10128546265 ps
CPU time 18.66 seconds
Started Jun 06 01:48:23 PM PDT 24
Finished Jun 06 01:48:42 PM PDT 24
Peak memory 205684 kb
Host smart-12f3a30d-0060-4706-8af0-667eccbed67a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38246
1864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.382461864
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.3390496377
Short name T417
Test name
Test status
Simulation time 10080408011 ps
CPU time 13.71 seconds
Started Jun 06 01:48:24 PM PDT 24
Finished Jun 06 01:48:38 PM PDT 24
Peak memory 205704 kb
Host smart-d1418d85-7259-4a1d-b2cb-7b141eaadbcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33904
96377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.3390496377
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.734886847
Short name T1789
Test name
Test status
Simulation time 10068690173 ps
CPU time 16.46 seconds
Started Jun 06 01:48:25 PM PDT 24
Finished Jun 06 01:48:43 PM PDT 24
Peak memory 205648 kb
Host smart-1f03ea35-751e-487c-9544-aba71f5428b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73488
6847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.734886847
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.295428089
Short name T614
Test name
Test status
Simulation time 10039195651 ps
CPU time 12.87 seconds
Started Jun 06 01:48:25 PM PDT 24
Finished Jun 06 01:48:40 PM PDT 24
Peak memory 205604 kb
Host smart-55dffa15-f717-4a92-89fe-c2a602c7f23f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29542
8089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.295428089
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.1420191968
Short name T1735
Test name
Test status
Simulation time 10082738143 ps
CPU time 13.87 seconds
Started Jun 06 01:48:27 PM PDT 24
Finished Jun 06 01:48:42 PM PDT 24
Peak memory 205656 kb
Host smart-33f7d7f5-0ff0-4428-8941-5718f3afb3c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14201
91968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1420191968
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3801946280
Short name T910
Test name
Test status
Simulation time 10058029794 ps
CPU time 14.34 seconds
Started Jun 06 01:48:23 PM PDT 24
Finished Jun 06 01:48:38 PM PDT 24
Peak memory 205960 kb
Host smart-df1b3417-5202-4ebf-b724-d0d6cd5dc597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38019
46280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3801946280
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3060630758
Short name T734
Test name
Test status
Simulation time 10093293886 ps
CPU time 14.4 seconds
Started Jun 06 01:48:15 PM PDT 24
Finished Jun 06 01:48:30 PM PDT 24
Peak memory 205616 kb
Host smart-717be392-efb1-4b80-8648-6aab46c1d751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30606
30758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3060630758
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2819254664
Short name T1355
Test name
Test status
Simulation time 10086443045 ps
CPU time 14.81 seconds
Started Jun 06 01:48:30 PM PDT 24
Finished Jun 06 01:48:46 PM PDT 24
Peak memory 205624 kb
Host smart-7fd01d30-9c15-40b8-b9c9-0e3326bfdc0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28192
54664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2819254664
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.1245389157
Short name T1650
Test name
Test status
Simulation time 10047607679 ps
CPU time 12.97 seconds
Started Jun 06 01:48:24 PM PDT 24
Finished Jun 06 01:48:38 PM PDT 24
Peak memory 205776 kb
Host smart-44c18f3f-a2f3-49b9-8330-712a8fadb365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12453
89157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.1245389157
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.3216545740
Short name T743
Test name
Test status
Simulation time 21594789340 ps
CPU time 339.21 seconds
Started Jun 06 01:48:25 PM PDT 24
Finished Jun 06 01:54:05 PM PDT 24
Peak memory 205612 kb
Host smart-cb215a38-a933-4973-95f4-8736f839814e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32165
45740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.3216545740
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.64563831
Short name T565
Test name
Test status
Simulation time 10157127432 ps
CPU time 15.54 seconds
Started Jun 06 01:48:26 PM PDT 24
Finished Jun 06 01:48:43 PM PDT 24
Peak memory 205712 kb
Host smart-f8879dea-2a8e-48e0-bd15-291e93e61d6c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=64563831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.64563831
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.100956733
Short name T980
Test name
Test status
Simulation time 10069623025 ps
CPU time 13.55 seconds
Started Jun 06 01:48:27 PM PDT 24
Finished Jun 06 01:48:42 PM PDT 24
Peak memory 205536 kb
Host smart-b094df37-49a3-4fb0-8972-304ada878704
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=100956733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.100956733
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.3863505218
Short name T513
Test name
Test status
Simulation time 10067112424 ps
CPU time 13.83 seconds
Started Jun 06 01:48:28 PM PDT 24
Finished Jun 06 01:48:43 PM PDT 24
Peak memory 205700 kb
Host smart-c49214b4-a561-4c38-816f-42116c0198f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38635
05218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.3863505218
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.2646403151
Short name T13
Test name
Test status
Simulation time 13965287354 ps
CPU time 17.86 seconds
Started Jun 06 01:48:24 PM PDT 24
Finished Jun 06 01:48:42 PM PDT 24
Peak memory 206012 kb
Host smart-4a551378-14e1-4dcc-9c04-a5abff74e87a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2646403151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.2646403151
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.1421854699
Short name T1836
Test name
Test status
Simulation time 23287340861 ps
CPU time 30.16 seconds
Started Jun 06 01:48:23 PM PDT 24
Finished Jun 06 01:48:54 PM PDT 24
Peak memory 205684 kb
Host smart-818cd28a-55f8-4a93-819e-a9299bb9d552
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1421854699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.1421854699
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.3380626250
Short name T1173
Test name
Test status
Simulation time 10079957515 ps
CPU time 14.25 seconds
Started Jun 06 01:48:28 PM PDT 24
Finished Jun 06 01:48:43 PM PDT 24
Peak memory 205616 kb
Host smart-9f568837-69c7-40b2-89bc-3c4b9bd9823f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33806
26250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.3380626250
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.3057314004
Short name T1568
Test name
Test status
Simulation time 10060160071 ps
CPU time 15.16 seconds
Started Jun 06 01:48:24 PM PDT 24
Finished Jun 06 01:48:41 PM PDT 24
Peak memory 205732 kb
Host smart-763faab3-ea63-4b67-a0b7-2b4fe1a52091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30573
14004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.3057314004
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.2419075085
Short name T174
Test name
Test status
Simulation time 10565542852 ps
CPU time 15.89 seconds
Started Jun 06 01:48:26 PM PDT 24
Finished Jun 06 01:48:43 PM PDT 24
Peak memory 205596 kb
Host smart-03db9bf0-5077-4f62-844b-88d1d322eb7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24190
75085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.2419075085
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.179640285
Short name T320
Test name
Test status
Simulation time 10062320453 ps
CPU time 13.47 seconds
Started Jun 06 01:48:26 PM PDT 24
Finished Jun 06 01:48:41 PM PDT 24
Peak memory 205596 kb
Host smart-af8f898c-abd4-4377-a34e-6428112b4e6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17964
0285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.179640285
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.2473973416
Short name T1673
Test name
Test status
Simulation time 10116367189 ps
CPU time 14.61 seconds
Started Jun 06 01:48:29 PM PDT 24
Finished Jun 06 01:48:44 PM PDT 24
Peak memory 205580 kb
Host smart-1d78a456-17b6-4e34-9f2c-4c874a428bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24739
73416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2473973416
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.1750718534
Short name T1040
Test name
Test status
Simulation time 10741106142 ps
CPU time 15.31 seconds
Started Jun 06 01:48:24 PM PDT 24
Finished Jun 06 01:48:40 PM PDT 24
Peak memory 205716 kb
Host smart-df9f8534-b636-44f5-98b8-143a89476507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17507
18534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.1750718534
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2195095701
Short name T642
Test name
Test status
Simulation time 10063629820 ps
CPU time 14.38 seconds
Started Jun 06 01:48:27 PM PDT 24
Finished Jun 06 01:48:43 PM PDT 24
Peak memory 205652 kb
Host smart-52825e8f-cd2c-4949-beda-80cc3e8617c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21950
95701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2195095701
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.2570297121
Short name T1848
Test name
Test status
Simulation time 10094242919 ps
CPU time 16 seconds
Started Jun 06 01:48:26 PM PDT 24
Finished Jun 06 01:48:43 PM PDT 24
Peak memory 205636 kb
Host smart-7f06e7f4-8652-4cbc-8678-f37a587b248c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25702
97121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.2570297121
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.2386317414
Short name T1309
Test name
Test status
Simulation time 10034827444 ps
CPU time 13.61 seconds
Started Jun 06 01:48:25 PM PDT 24
Finished Jun 06 01:48:40 PM PDT 24
Peak memory 205608 kb
Host smart-179dc2ef-9c5a-4873-8b1d-ef659b5a81a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23863
17414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.2386317414
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.706611630
Short name T2020
Test name
Test status
Simulation time 10122777869 ps
CPU time 13.38 seconds
Started Jun 06 01:48:29 PM PDT 24
Finished Jun 06 01:48:43 PM PDT 24
Peak memory 205712 kb
Host smart-a3ef5b99-3b0d-4c62-a876-94ac2b54b75c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70661
1630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.706611630
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.406243973
Short name T1343
Test name
Test status
Simulation time 10142486335 ps
CPU time 13.25 seconds
Started Jun 06 01:48:24 PM PDT 24
Finished Jun 06 01:48:39 PM PDT 24
Peak memory 205900 kb
Host smart-29a21823-d2d9-4a87-88e1-efc5235b9244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40624
3973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.406243973
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.2438109247
Short name T1152
Test name
Test status
Simulation time 13233974361 ps
CPU time 18 seconds
Started Jun 06 01:48:26 PM PDT 24
Finished Jun 06 01:48:45 PM PDT 24
Peak memory 205704 kb
Host smart-7d092cd2-c65a-4b94-a5a1-6f80cdb55b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24381
09247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.2438109247
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.423417187
Short name T1012
Test name
Test status
Simulation time 10173623638 ps
CPU time 12.88 seconds
Started Jun 06 01:48:28 PM PDT 24
Finished Jun 06 01:48:42 PM PDT 24
Peak memory 205704 kb
Host smart-81768b5d-2e43-4150-8426-9b4476394b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42341
7187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.423417187
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.3986109338
Short name T659
Test name
Test status
Simulation time 16556013864 ps
CPU time 71.65 seconds
Started Jun 06 01:48:26 PM PDT 24
Finished Jun 06 01:49:39 PM PDT 24
Peak memory 205752 kb
Host smart-17840828-d073-44a4-ba60-922fd9a32dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39861
09338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.3986109338
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2333037266
Short name T1317
Test name
Test status
Simulation time 10067118674 ps
CPU time 14.13 seconds
Started Jun 06 01:48:27 PM PDT 24
Finished Jun 06 01:48:43 PM PDT 24
Peak memory 205660 kb
Host smart-38eba52a-23ba-499a-a221-00bb0c4fc4f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23330
37266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2333037266
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.1998755679
Short name T1237
Test name
Test status
Simulation time 10076006978 ps
CPU time 16.52 seconds
Started Jun 06 01:48:25 PM PDT 24
Finished Jun 06 01:48:43 PM PDT 24
Peak memory 205728 kb
Host smart-d31b59e3-a2d4-48ac-8497-1e53dd3132cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19987
55679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1998755679
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.2091579614
Short name T898
Test name
Test status
Simulation time 10102448454 ps
CPU time 13.9 seconds
Started Jun 06 01:48:25 PM PDT 24
Finished Jun 06 01:48:40 PM PDT 24
Peak memory 205752 kb
Host smart-f6ab1994-f9c1-4fe2-a8e4-1c1752ffea89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20915
79614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.2091579614
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.872899601
Short name T1980
Test name
Test status
Simulation time 10066301056 ps
CPU time 16.09 seconds
Started Jun 06 01:48:27 PM PDT 24
Finished Jun 06 01:48:44 PM PDT 24
Peak memory 205748 kb
Host smart-c0ba6c44-a337-4bab-b348-559f33c27e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87289
9601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.872899601
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1067231697
Short name T1450
Test name
Test status
Simulation time 10065959575 ps
CPU time 15.19 seconds
Started Jun 06 01:48:26 PM PDT 24
Finished Jun 06 01:48:43 PM PDT 24
Peak memory 205640 kb
Host smart-f59881c3-8c6c-44e8-b267-91808df736a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10672
31697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1067231697
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1032196692
Short name T67
Test name
Test status
Simulation time 10054548376 ps
CPU time 14.59 seconds
Started Jun 06 01:48:27 PM PDT 24
Finished Jun 06 01:48:43 PM PDT 24
Peak memory 205632 kb
Host smart-35772dfc-6366-436e-8d2d-bebd53a4cb00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10321
96692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1032196692
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_eop_single_bit_handling.560784971
Short name T1278
Test name
Test status
Simulation time 10070967413 ps
CPU time 12.96 seconds
Started Jun 06 01:48:24 PM PDT 24
Finished Jun 06 01:48:38 PM PDT 24
Peak memory 205588 kb
Host smart-93abd212-6f15-45f7-8aeb-7fd53ad178ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56078
4971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_eop_single_bit_handling.560784971
Directory /workspace/18.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.1984030563
Short name T616
Test name
Test status
Simulation time 10075498890 ps
CPU time 13.67 seconds
Started Jun 06 01:48:27 PM PDT 24
Finished Jun 06 01:48:41 PM PDT 24
Peak memory 205608 kb
Host smart-5d8b5c01-04f9-4870-b0e5-4b0d6094cf7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19840
30563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.1984030563
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.4024176129
Short name T1403
Test name
Test status
Simulation time 10048745300 ps
CPU time 13 seconds
Started Jun 06 01:48:33 PM PDT 24
Finished Jun 06 01:48:47 PM PDT 24
Peak memory 205548 kb
Host smart-87efd8e7-5c26-40e1-8606-f763de067b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40241
76129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.4024176129
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.1763842247
Short name T1669
Test name
Test status
Simulation time 19111307880 ps
CPU time 39.62 seconds
Started Jun 06 01:48:27 PM PDT 24
Finished Jun 06 01:49:08 PM PDT 24
Peak memory 205660 kb
Host smart-d41bae20-a482-4e7a-957d-477da375c26d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17638
42247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.1763842247
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.1643039763
Short name T1593
Test name
Test status
Simulation time 10053143244 ps
CPU time 15.49 seconds
Started Jun 06 01:48:26 PM PDT 24
Finished Jun 06 01:48:43 PM PDT 24
Peak memory 205748 kb
Host smart-de48dc30-c3ef-4b4e-8f79-f2f5f912dad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16430
39763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1643039763
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.3453805520
Short name T1034
Test name
Test status
Simulation time 10241014452 ps
CPU time 16.26 seconds
Started Jun 06 01:48:27 PM PDT 24
Finished Jun 06 01:48:45 PM PDT 24
Peak memory 205768 kb
Host smart-ead30fa1-2799-494e-914c-4f3686cb7a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34538
05520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.3453805520
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.772751138
Short name T383
Test name
Test status
Simulation time 10090962781 ps
CPU time 14.36 seconds
Started Jun 06 01:48:31 PM PDT 24
Finished Jun 06 01:48:46 PM PDT 24
Peak memory 205584 kb
Host smart-d6ca904e-cb15-4876-b3b3-090b2c1a10fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77275
1138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.772751138
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.2775862238
Short name T65
Test name
Test status
Simulation time 10060824406 ps
CPU time 14.76 seconds
Started Jun 06 01:48:26 PM PDT 24
Finished Jun 06 01:48:42 PM PDT 24
Peak memory 205720 kb
Host smart-a328f6c0-7044-4fe3-8a20-ccc954462532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27758
62238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.2775862238
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.437958298
Short name T1087
Test name
Test status
Simulation time 10095349879 ps
CPU time 13.41 seconds
Started Jun 06 01:48:33 PM PDT 24
Finished Jun 06 01:48:47 PM PDT 24
Peak memory 205680 kb
Host smart-fff344b8-89f2-4758-8068-5d3f289600f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43795
8298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.437958298
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1124038447
Short name T1878
Test name
Test status
Simulation time 10059228911 ps
CPU time 15.18 seconds
Started Jun 06 01:48:33 PM PDT 24
Finished Jun 06 01:48:49 PM PDT 24
Peak memory 205488 kb
Host smart-3c68a722-6b15-46f0-8b8d-436c39c4db6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11240
38447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1124038447
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.4261524370
Short name T1106
Test name
Test status
Simulation time 10130272833 ps
CPU time 12.66 seconds
Started Jun 06 01:48:24 PM PDT 24
Finished Jun 06 01:48:38 PM PDT 24
Peak memory 205692 kb
Host smart-688cddeb-a518-4d65-b435-f82b804c0682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42615
24370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.4261524370
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.2192343306
Short name T1092
Test name
Test status
Simulation time 10045696787 ps
CPU time 13.56 seconds
Started Jun 06 01:48:27 PM PDT 24
Finished Jun 06 01:48:42 PM PDT 24
Peak memory 205652 kb
Host smart-a6090c58-b9c5-4c34-b173-9b7d7c9cb89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21923
43306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.2192343306
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.331757353
Short name T1698
Test name
Test status
Simulation time 10071634215 ps
CPU time 13.83 seconds
Started Jun 06 01:48:27 PM PDT 24
Finished Jun 06 01:48:42 PM PDT 24
Peak memory 205668 kb
Host smart-a4cc7627-649b-458c-9b37-ca5fa6fa8ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33175
7353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.331757353
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.865485971
Short name T631
Test name
Test status
Simulation time 25647323882 ps
CPU time 163.2 seconds
Started Jun 06 01:48:33 PM PDT 24
Finished Jun 06 01:51:17 PM PDT 24
Peak memory 205608 kb
Host smart-101e2a38-1e8a-472f-b1d3-eb674d125dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86548
5971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.865485971
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.1099715187
Short name T1543
Test name
Test status
Simulation time 10144241510 ps
CPU time 14.04 seconds
Started Jun 06 01:48:52 PM PDT 24
Finished Jun 06 01:49:09 PM PDT 24
Peak memory 205748 kb
Host smart-0b05dc4f-3746-4e76-9933-8a8d29843b72
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1099715187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.1099715187
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.1857541610
Short name T1643
Test name
Test status
Simulation time 10067308022 ps
CPU time 13.08 seconds
Started Jun 06 01:48:52 PM PDT 24
Finished Jun 06 01:49:08 PM PDT 24
Peak memory 205672 kb
Host smart-410552c6-9494-43a3-91af-a4b731f9b228
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1857541610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.1857541610
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.258897167
Short name T1525
Test name
Test status
Simulation time 10102754759 ps
CPU time 14.15 seconds
Started Jun 06 01:48:43 PM PDT 24
Finished Jun 06 01:48:58 PM PDT 24
Peak memory 205640 kb
Host smart-77e045bd-01f5-4f6b-859f-c7362973308e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25889
7167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.258897167
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.2203995358
Short name T604
Test name
Test status
Simulation time 14265985197 ps
CPU time 19.38 seconds
Started Jun 06 01:48:37 PM PDT 24
Finished Jun 06 01:48:57 PM PDT 24
Peak memory 205660 kb
Host smart-3944ebbf-c64e-4b97-93be-8d0789682ecd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2203995358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.2203995358
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.742837693
Short name T1376
Test name
Test status
Simulation time 23427927651 ps
CPU time 32.43 seconds
Started Jun 06 01:48:36 PM PDT 24
Finished Jun 06 01:49:09 PM PDT 24
Peak memory 205792 kb
Host smart-5202df73-12fa-4251-b8bc-618304772ff4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=742837693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.742837693
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.1697492023
Short name T240
Test name
Test status
Simulation time 10051306863 ps
CPU time 13.71 seconds
Started Jun 06 01:48:35 PM PDT 24
Finished Jun 06 01:48:49 PM PDT 24
Peak memory 205640 kb
Host smart-7cdac445-c56f-40dc-aebb-b42898f854f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16974
92023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.1697492023
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.28545249
Short name T185
Test name
Test status
Simulation time 11190964698 ps
CPU time 18.26 seconds
Started Jun 06 01:48:34 PM PDT 24
Finished Jun 06 01:48:53 PM PDT 24
Peak memory 205756 kb
Host smart-f7483d97-4d77-4864-ae9d-aaf6d6f45b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28545
249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.28545249
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.285520978
Short name T1556
Test name
Test status
Simulation time 10083569432 ps
CPU time 12.98 seconds
Started Jun 06 01:48:37 PM PDT 24
Finished Jun 06 01:48:51 PM PDT 24
Peak memory 205696 kb
Host smart-ae34d39e-7066-4e3b-984d-411a0a60dd88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28552
0978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.285520978
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.2805110083
Short name T1043
Test name
Test status
Simulation time 10061723858 ps
CPU time 13.36 seconds
Started Jun 06 01:48:36 PM PDT 24
Finished Jun 06 01:48:50 PM PDT 24
Peak memory 205744 kb
Host smart-e377d4ac-d1c9-4bf2-8733-ee345331d2da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28051
10083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2805110083
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.1367437857
Short name T787
Test name
Test status
Simulation time 10746588948 ps
CPU time 16.12 seconds
Started Jun 06 01:48:32 PM PDT 24
Finished Jun 06 01:48:49 PM PDT 24
Peak memory 205716 kb
Host smart-039e114c-02ac-4241-b2c4-b0cbab52761a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13674
37857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.1367437857
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.2205272196
Short name T1851
Test name
Test status
Simulation time 10245826256 ps
CPU time 16.56 seconds
Started Jun 06 01:48:33 PM PDT 24
Finished Jun 06 01:48:51 PM PDT 24
Peak memory 205744 kb
Host smart-86601de1-118b-4c34-9ee6-39fa0fb271dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22052
72196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2205272196
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.1502374585
Short name T1971
Test name
Test status
Simulation time 10126385840 ps
CPU time 16.09 seconds
Started Jun 06 01:48:40 PM PDT 24
Finished Jun 06 01:48:57 PM PDT 24
Peak memory 205720 kb
Host smart-d24c251c-848f-47c9-b54d-361c03b8e311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15023
74585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.1502374585
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.2228227702
Short name T584
Test name
Test status
Simulation time 10051979199 ps
CPU time 14.69 seconds
Started Jun 06 01:48:46 PM PDT 24
Finished Jun 06 01:49:02 PM PDT 24
Peak memory 205676 kb
Host smart-98eb3cc7-a49a-43f7-b7c3-a4b5a74f1466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22282
27702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.2228227702
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.3352992192
Short name T204
Test name
Test status
Simulation time 10108239610 ps
CPU time 14.04 seconds
Started Jun 06 01:48:36 PM PDT 24
Finished Jun 06 01:48:51 PM PDT 24
Peak memory 205916 kb
Host smart-e9310d52-a285-4656-9961-6fc2315e6f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33529
92192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.3352992192
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.2028571408
Short name T374
Test name
Test status
Simulation time 10115702605 ps
CPU time 13.68 seconds
Started Jun 06 01:48:34 PM PDT 24
Finished Jun 06 01:48:48 PM PDT 24
Peak memory 205640 kb
Host smart-af40441d-b8c3-4301-944c-677dba7590da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20285
71408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.2028571408
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.2363505406
Short name T1795
Test name
Test status
Simulation time 13278623415 ps
CPU time 17.37 seconds
Started Jun 06 01:48:32 PM PDT 24
Finished Jun 06 01:48:50 PM PDT 24
Peak memory 205656 kb
Host smart-4655c3b3-1669-492f-b790-fdb26540e8a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23635
05406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.2363505406
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1108185305
Short name T1540
Test name
Test status
Simulation time 10095956916 ps
CPU time 14.94 seconds
Started Jun 06 01:48:33 PM PDT 24
Finished Jun 06 01:48:49 PM PDT 24
Peak memory 205764 kb
Host smart-38dd795f-8c6b-49fe-9ecb-26196d2c56a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11081
85305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1108185305
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.2038658198
Short name T1432
Test name
Test status
Simulation time 17096126990 ps
CPU time 80.88 seconds
Started Jun 06 01:48:34 PM PDT 24
Finished Jun 06 01:49:56 PM PDT 24
Peak memory 205748 kb
Host smart-184f0e61-d90a-463f-a25c-0689bd16236e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20386
58198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.2038658198
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3211702888
Short name T1725
Test name
Test status
Simulation time 10057866382 ps
CPU time 15.48 seconds
Started Jun 06 01:48:33 PM PDT 24
Finished Jun 06 01:48:49 PM PDT 24
Peak memory 205776 kb
Host smart-8a235303-1e04-4099-8069-354413921460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32117
02888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3211702888
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.1360073599
Short name T664
Test name
Test status
Simulation time 10097621117 ps
CPU time 13.15 seconds
Started Jun 06 01:48:36 PM PDT 24
Finished Jun 06 01:48:50 PM PDT 24
Peak memory 206008 kb
Host smart-2cd73fae-c736-44ea-9a4b-943b67b29d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13600
73599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.1360073599
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.4127032207
Short name T1419
Test name
Test status
Simulation time 10060225730 ps
CPU time 14.11 seconds
Started Jun 06 01:48:34 PM PDT 24
Finished Jun 06 01:48:49 PM PDT 24
Peak memory 205776 kb
Host smart-49bbf7e1-a1f8-4fe2-87d5-f852d3c37bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41270
32207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.4127032207
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2390248205
Short name T1866
Test name
Test status
Simulation time 10051443198 ps
CPU time 15.69 seconds
Started Jun 06 01:48:34 PM PDT 24
Finished Jun 06 01:48:51 PM PDT 24
Peak memory 205748 kb
Host smart-5161f149-8cc7-47bf-ab78-f82e8aa21031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23902
48205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2390248205
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.411336169
Short name T141
Test name
Test status
Simulation time 10081137756 ps
CPU time 13.66 seconds
Started Jun 06 01:48:51 PM PDT 24
Finished Jun 06 01:49:07 PM PDT 24
Peak memory 205732 kb
Host smart-f033b62e-4aa5-4383-bd74-6794214946f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41133
6169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.411336169
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_eop_single_bit_handling.1828137460
Short name T206
Test name
Test status
Simulation time 10110396214 ps
CPU time 14.02 seconds
Started Jun 06 01:48:39 PM PDT 24
Finished Jun 06 01:48:53 PM PDT 24
Peak memory 205652 kb
Host smart-a1264a61-e14f-4a82-891a-36131d002168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18281
37460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_eop_single_bit_handling.1828137460
Directory /workspace/19.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.1475850441
Short name T572
Test name
Test status
Simulation time 10067568748 ps
CPU time 16.62 seconds
Started Jun 06 01:48:41 PM PDT 24
Finished Jun 06 01:48:59 PM PDT 24
Peak memory 205740 kb
Host smart-d573927c-a360-4c4d-9fb6-9961fa3a981e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14758
50441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.1475850441
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.147982166
Short name T626
Test name
Test status
Simulation time 10060786344 ps
CPU time 14.13 seconds
Started Jun 06 01:48:41 PM PDT 24
Finished Jun 06 01:48:56 PM PDT 24
Peak memory 205724 kb
Host smart-2729863f-75e6-4bfb-a02d-fcb2afbc599e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14798
2166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.147982166
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.608461399
Short name T182
Test name
Test status
Simulation time 31315291959 ps
CPU time 65.2 seconds
Started Jun 06 01:48:36 PM PDT 24
Finished Jun 06 01:49:42 PM PDT 24
Peak memory 205648 kb
Host smart-dd961bc1-b0e4-40bf-9f3d-d2e635c25d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60846
1399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.608461399
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.1120316316
Short name T1493
Test name
Test status
Simulation time 10077488808 ps
CPU time 13.18 seconds
Started Jun 06 01:48:34 PM PDT 24
Finished Jun 06 01:48:48 PM PDT 24
Peak memory 205704 kb
Host smart-96d6903f-e16f-471f-b99e-7d3ca318ce85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11203
16316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.1120316316
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1924735301
Short name T1776
Test name
Test status
Simulation time 10142595443 ps
CPU time 16.83 seconds
Started Jun 06 01:48:32 PM PDT 24
Finished Jun 06 01:48:49 PM PDT 24
Peak memory 205672 kb
Host smart-cee24cf5-db3f-4799-89f6-c201c35ba3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19247
35301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1924735301
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.3013508544
Short name T578
Test name
Test status
Simulation time 10077209901 ps
CPU time 14.24 seconds
Started Jun 06 01:48:34 PM PDT 24
Finished Jun 06 01:48:49 PM PDT 24
Peak memory 205656 kb
Host smart-45232142-907e-4f39-b290-f67f13c0f714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30135
08544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.3013508544
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.363720023
Short name T601
Test name
Test status
Simulation time 10104445766 ps
CPU time 14.38 seconds
Started Jun 06 01:48:32 PM PDT 24
Finished Jun 06 01:48:48 PM PDT 24
Peak memory 205700 kb
Host smart-1061e0b7-830e-4ac3-ae11-272ab3a638ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36372
0023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.363720023
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.3042590136
Short name T1976
Test name
Test status
Simulation time 10054240141 ps
CPU time 14.04 seconds
Started Jun 06 01:48:46 PM PDT 24
Finished Jun 06 01:49:01 PM PDT 24
Peak memory 205692 kb
Host smart-1919d4ed-d16a-490b-ab49-364842dc4743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30425
90136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.3042590136
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.2010145965
Short name T632
Test name
Test status
Simulation time 10055119482 ps
CPU time 12.98 seconds
Started Jun 06 01:48:32 PM PDT 24
Finished Jun 06 01:48:47 PM PDT 24
Peak memory 205632 kb
Host smart-fdb23682-8910-404b-b2d1-09e9e523bd0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20101
45965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.2010145965
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.4161557324
Short name T660
Test name
Test status
Simulation time 10104791082 ps
CPU time 15.65 seconds
Started Jun 06 01:48:32 PM PDT 24
Finished Jun 06 01:48:49 PM PDT 24
Peak memory 205708 kb
Host smart-dce38b30-63d6-43b5-b949-57e036a30a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41615
57324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.4161557324
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.388202053
Short name T1587
Test name
Test status
Simulation time 10073576080 ps
CPU time 14.22 seconds
Started Jun 06 01:48:37 PM PDT 24
Finished Jun 06 01:48:52 PM PDT 24
Peak memory 205688 kb
Host smart-7176dc31-103b-45b7-94b4-fc3475982774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38820
2053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.388202053
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3390462463
Short name T1581
Test name
Test status
Simulation time 10075644867 ps
CPU time 13.52 seconds
Started Jun 06 01:48:32 PM PDT 24
Finished Jun 06 01:48:47 PM PDT 24
Peak memory 205684 kb
Host smart-4acb6110-a2e3-4be2-adf1-c13ee05ea154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33904
62463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3390462463
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.1426493838
Short name T357
Test name
Test status
Simulation time 16312242166 ps
CPU time 189.83 seconds
Started Jun 06 01:48:33 PM PDT 24
Finished Jun 06 01:51:44 PM PDT 24
Peak memory 205608 kb
Host smart-3ad6bdb5-4537-49d3-83e0-b3fb9b4d457d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14264
93838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.1426493838
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.2951643139
Short name T948
Test name
Test status
Simulation time 10169859408 ps
CPU time 13.69 seconds
Started Jun 06 01:45:01 PM PDT 24
Finished Jun 06 01:45:15 PM PDT 24
Peak memory 205708 kb
Host smart-d9e2005a-95a7-42fa-bc7f-6b24a6b34944
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2951643139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.2951643139
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.3247148448
Short name T1637
Test name
Test status
Simulation time 10090100204 ps
CPU time 16 seconds
Started Jun 06 01:45:03 PM PDT 24
Finished Jun 06 01:45:20 PM PDT 24
Peak memory 205656 kb
Host smart-7fd11013-ca79-4f05-b891-ee6059927e8a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3247148448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.3247148448
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.4078850023
Short name T1671
Test name
Test status
Simulation time 10138713735 ps
CPU time 14.79 seconds
Started Jun 06 01:45:02 PM PDT 24
Finished Jun 06 01:45:18 PM PDT 24
Peak memory 205700 kb
Host smart-bd2d192b-f532-45ba-b445-7e48dccdbb74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40788
50023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.4078850023
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.4278717546
Short name T1295
Test name
Test status
Simulation time 13646701768 ps
CPU time 16.52 seconds
Started Jun 06 01:44:47 PM PDT 24
Finished Jun 06 01:45:04 PM PDT 24
Peak memory 205720 kb
Host smart-84f94bf6-47c7-4a1c-bf5e-12a8fd0716a9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4278717546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.4278717546
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.535606541
Short name T569
Test name
Test status
Simulation time 23273813268 ps
CPU time 26.12 seconds
Started Jun 06 01:44:44 PM PDT 24
Finished Jun 06 01:45:11 PM PDT 24
Peak memory 205768 kb
Host smart-50ffb719-7664-40e6-b8d5-bfb7b6388189
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=535606541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.535606541
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.3550693142
Short name T727
Test name
Test status
Simulation time 10056193373 ps
CPU time 13.66 seconds
Started Jun 06 01:44:46 PM PDT 24
Finished Jun 06 01:45:00 PM PDT 24
Peak memory 205636 kb
Host smart-7146f224-84de-4419-84e1-97532b338593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35506
93142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.3550693142
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.880610910
Short name T1413
Test name
Test status
Simulation time 11300915527 ps
CPU time 18.28 seconds
Started Jun 06 01:44:45 PM PDT 24
Finished Jun 06 01:45:04 PM PDT 24
Peak memory 205628 kb
Host smart-2be9d645-0fd0-4181-88ec-4fac111a1deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88061
0910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.880610910
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2565085407
Short name T346
Test name
Test status
Simulation time 10089700013 ps
CPU time 14.39 seconds
Started Jun 06 01:44:46 PM PDT 24
Finished Jun 06 01:45:01 PM PDT 24
Peak memory 205656 kb
Host smart-f82709ff-cac6-48cb-9a14-dd33fa783550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25650
85407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2565085407
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.2154192524
Short name T593
Test name
Test status
Simulation time 10055345646 ps
CPU time 17.81 seconds
Started Jun 06 01:44:46 PM PDT 24
Finished Jun 06 01:45:05 PM PDT 24
Peak memory 205576 kb
Host smart-b6be4131-6bde-42a5-88e8-823815b0c04d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21541
92524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.2154192524
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.771254088
Short name T667
Test name
Test status
Simulation time 10678335379 ps
CPU time 15.15 seconds
Started Jun 06 01:44:46 PM PDT 24
Finished Jun 06 01:45:02 PM PDT 24
Peak memory 205800 kb
Host smart-52cf57ed-1f76-4841-b2e7-17f4cec1aee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77125
4088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.771254088
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.1940705895
Short name T1167
Test name
Test status
Simulation time 10110442813 ps
CPU time 15.42 seconds
Started Jun 06 01:44:46 PM PDT 24
Finished Jun 06 01:45:03 PM PDT 24
Peak memory 205672 kb
Host smart-9829357f-d05f-4857-a0f6-66138c8c5fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19407
05895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.1940705895
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.1654918757
Short name T866
Test name
Test status
Simulation time 10060716955 ps
CPU time 14.65 seconds
Started Jun 06 01:45:01 PM PDT 24
Finished Jun 06 01:45:16 PM PDT 24
Peak memory 205632 kb
Host smart-d6c9f91d-f3c9-4c25-b1de-31fe2c143666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16549
18757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.1654918757
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.3907912981
Short name T1311
Test name
Test status
Simulation time 10063182947 ps
CPU time 14.79 seconds
Started Jun 06 01:45:02 PM PDT 24
Finished Jun 06 01:45:18 PM PDT 24
Peak memory 205676 kb
Host smart-aec335ac-5c8d-46c4-8b10-236f835ce05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39079
12981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.3907912981
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.1013594668
Short name T1085
Test name
Test status
Simulation time 10108850228 ps
CPU time 12.96 seconds
Started Jun 06 01:44:45 PM PDT 24
Finished Jun 06 01:44:59 PM PDT 24
Peak memory 205636 kb
Host smart-29fd25fb-0a96-4360-9351-0c53629bd9e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10135
94668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1013594668
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.1257567620
Short name T1541
Test name
Test status
Simulation time 10144024013 ps
CPU time 15.87 seconds
Started Jun 06 01:44:46 PM PDT 24
Finished Jun 06 01:45:02 PM PDT 24
Peak memory 205668 kb
Host smart-e3a803fd-f04c-42ab-b7eb-6bf7da4d0c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12575
67620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.1257567620
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.3908241283
Short name T598
Test name
Test status
Simulation time 13302807996 ps
CPU time 15.27 seconds
Started Jun 06 01:44:46 PM PDT 24
Finished Jun 06 01:45:02 PM PDT 24
Peak memory 205688 kb
Host smart-ded866b4-0be2-4158-bc0e-5f6ecf718e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39082
41283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.3908241283
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.2716604247
Short name T554
Test name
Test status
Simulation time 10119603943 ps
CPU time 13.87 seconds
Started Jun 06 01:44:45 PM PDT 24
Finished Jun 06 01:45:00 PM PDT 24
Peak memory 205688 kb
Host smart-9037cee6-2d81-4de3-b354-1208415a3d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27166
04247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2716604247
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.3700166528
Short name T1048
Test name
Test status
Simulation time 22757508227 ps
CPU time 147.62 seconds
Started Jun 06 01:44:54 PM PDT 24
Finished Jun 06 01:47:22 PM PDT 24
Peak memory 205700 kb
Host smart-30177b07-6f0c-4524-be64-08e4abd5ee4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37001
66528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.3700166528
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.2144305115
Short name T1970
Test name
Test status
Simulation time 10061342429 ps
CPU time 14.03 seconds
Started Jun 06 01:44:47 PM PDT 24
Finished Jun 06 01:45:02 PM PDT 24
Peak memory 205712 kb
Host smart-7930b190-20dc-4549-8f5f-2acd24971b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21443
05115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.2144305115
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.988428670
Short name T1852
Test name
Test status
Simulation time 10115560530 ps
CPU time 12.89 seconds
Started Jun 06 01:44:53 PM PDT 24
Finished Jun 06 01:45:06 PM PDT 24
Peak memory 205696 kb
Host smart-35578bdd-a93b-4641-b8e9-2d4337060cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98842
8670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.988428670
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.1626970598
Short name T461
Test name
Test status
Simulation time 10056137946 ps
CPU time 16.22 seconds
Started Jun 06 01:44:52 PM PDT 24
Finished Jun 06 01:45:09 PM PDT 24
Peak memory 205740 kb
Host smart-f993b271-b8ee-478e-9d8b-e793870cdf87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16269
70598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.1626970598
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.680069757
Short name T1260
Test name
Test status
Simulation time 10110453148 ps
CPU time 12.96 seconds
Started Jun 06 01:44:51 PM PDT 24
Finished Jun 06 01:45:04 PM PDT 24
Peak memory 205704 kb
Host smart-c13a442d-c615-443d-8d1d-4b3ae5f2a432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68006
9757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.680069757
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.4192249511
Short name T692
Test name
Test status
Simulation time 10046504325 ps
CPU time 15.2 seconds
Started Jun 06 01:44:53 PM PDT 24
Finished Jun 06 01:45:09 PM PDT 24
Peak memory 205744 kb
Host smart-3cc085bd-08c3-4c86-93a5-f538ff942021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41922
49511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.4192249511
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.704834596
Short name T1871
Test name
Test status
Simulation time 10049582831 ps
CPU time 14.27 seconds
Started Jun 06 01:45:03 PM PDT 24
Finished Jun 06 01:45:18 PM PDT 24
Peak memory 205664 kb
Host smart-5e80c1aa-a62e-4882-aef2-cf13818b400d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70483
4596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.704834596
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_eop_single_bit_handling.2965434230
Short name T1379
Test name
Test status
Simulation time 10084689654 ps
CPU time 13.53 seconds
Started Jun 06 01:45:01 PM PDT 24
Finished Jun 06 01:45:16 PM PDT 24
Peak memory 205748 kb
Host smart-b1a6f28b-513e-4ce7-a4e5-98f29847b30d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29654
34230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_eop_single_bit_handling.2965434230
Directory /workspace/2.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.2746854566
Short name T800
Test name
Test status
Simulation time 10050828487 ps
CPU time 15.56 seconds
Started Jun 06 01:45:01 PM PDT 24
Finished Jun 06 01:45:18 PM PDT 24
Peak memory 205788 kb
Host smart-8256a162-0b0e-4f62-9858-bcb8a1433898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27468
54566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.2746854566
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.1396947580
Short name T1634
Test name
Test status
Simulation time 10041046611 ps
CPU time 14.14 seconds
Started Jun 06 01:45:04 PM PDT 24
Finished Jun 06 01:45:19 PM PDT 24
Peak memory 205604 kb
Host smart-6d8dbd89-f289-46d0-836c-ecd0d09446f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13969
47580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.1396947580
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.298784613
Short name T1266
Test name
Test status
Simulation time 29442722464 ps
CPU time 59.02 seconds
Started Jun 06 01:44:54 PM PDT 24
Finished Jun 06 01:45:53 PM PDT 24
Peak memory 205680 kb
Host smart-0c3739e7-d250-4463-ab7f-ad2344bef5fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29878
4613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.298784613
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.4003268087
Short name T779
Test name
Test status
Simulation time 10097860383 ps
CPU time 14.4 seconds
Started Jun 06 01:44:55 PM PDT 24
Finished Jun 06 01:45:10 PM PDT 24
Peak memory 205720 kb
Host smart-778f601f-0788-4428-b022-aeb9fd8aad6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40032
68087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.4003268087
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.146175790
Short name T1849
Test name
Test status
Simulation time 10099469459 ps
CPU time 14.19 seconds
Started Jun 06 01:44:54 PM PDT 24
Finished Jun 06 01:45:09 PM PDT 24
Peak memory 205704 kb
Host smart-257a6183-925f-4011-b3ee-ccb48a6368b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14617
5790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.146175790
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.726931959
Short name T189
Test name
Test status
Simulation time 34976144954 ps
CPU time 183.7 seconds
Started Jun 06 01:44:52 PM PDT 24
Finished Jun 06 01:47:57 PM PDT 24
Peak memory 205740 kb
Host smart-ae12dbc8-548c-4354-badd-5ca645ec7a7d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=726931959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.726931959
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.3640312189
Short name T1530
Test name
Test status
Simulation time 25433500188 ps
CPU time 110.99 seconds
Started Jun 06 01:44:51 PM PDT 24
Finished Jun 06 01:46:43 PM PDT 24
Peak memory 205788 kb
Host smart-9bca77a1-e403-4623-af2c-7dd9885432b4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3640312189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.3640312189
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.578362356
Short name T1203
Test name
Test status
Simulation time 49352554354 ps
CPU time 363.65 seconds
Started Jun 06 01:44:53 PM PDT 24
Finished Jun 06 01:50:58 PM PDT 24
Peak memory 205780 kb
Host smart-ef0cb5b3-c850-4d6e-8b9d-d52eb2c97e00
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=578362356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.578362356
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.3026133856
Short name T1821
Test name
Test status
Simulation time 10086825651 ps
CPU time 14.42 seconds
Started Jun 06 01:44:53 PM PDT 24
Finished Jun 06 01:45:08 PM PDT 24
Peak memory 205592 kb
Host smart-2cbedd13-e9ee-4cc3-b5d0-283cc907297c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30261
33856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.3026133856
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.3504001544
Short name T1600
Test name
Test status
Simulation time 10089141949 ps
CPU time 13.58 seconds
Started Jun 06 01:44:54 PM PDT 24
Finished Jun 06 01:45:08 PM PDT 24
Peak memory 205748 kb
Host smart-5b4517eb-ab2b-43e7-b11e-ec262ca255fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35040
01544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.3504001544
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1653498580
Short name T191
Test name
Test status
Simulation time 336550167 ps
CPU time 1.21 seconds
Started Jun 06 01:45:01 PM PDT 24
Finished Jun 06 01:45:03 PM PDT 24
Peak memory 221740 kb
Host smart-febaaf8b-1c0e-4413-b5c1-4a1a34dd899f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1653498580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1653498580
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.1152499387
Short name T634
Test name
Test status
Simulation time 10062301563 ps
CPU time 13.07 seconds
Started Jun 06 01:45:03 PM PDT 24
Finished Jun 06 01:45:17 PM PDT 24
Peak memory 205612 kb
Host smart-3f21202c-c550-4846-a46b-2769d3acdb75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11524
99387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.1152499387
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.2201660144
Short name T1494
Test name
Test status
Simulation time 10062997123 ps
CPU time 14.08 seconds
Started Jun 06 01:44:51 PM PDT 24
Finished Jun 06 01:45:05 PM PDT 24
Peak memory 205716 kb
Host smart-658b42c5-10ec-4a64-aa54-375397312371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22016
60144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.2201660144
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.700965098
Short name T1448
Test name
Test status
Simulation time 10153187237 ps
CPU time 15.49 seconds
Started Jun 06 01:44:47 PM PDT 24
Finished Jun 06 01:45:03 PM PDT 24
Peak memory 205688 kb
Host smart-80d05e63-c3ae-47b6-8531-6a42c11e625a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70096
5098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.700965098
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.4183402455
Short name T345
Test name
Test status
Simulation time 10114734162 ps
CPU time 13.55 seconds
Started Jun 06 01:44:53 PM PDT 24
Finished Jun 06 01:45:08 PM PDT 24
Peak memory 205716 kb
Host smart-116fbd5a-ab69-498d-a547-4c5bd212d604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41834
02455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.4183402455
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.1745554590
Short name T752
Test name
Test status
Simulation time 10095667816 ps
CPU time 13.73 seconds
Started Jun 06 01:44:52 PM PDT 24
Finished Jun 06 01:45:07 PM PDT 24
Peak memory 205628 kb
Host smart-8d9444bc-699c-4b54-9fbf-5e0881e677f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17455
54590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.1745554590
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.1794031692
Short name T354
Test name
Test status
Simulation time 18406727209 ps
CPU time 71.99 seconds
Started Jun 06 01:44:54 PM PDT 24
Finished Jun 06 01:46:07 PM PDT 24
Peak memory 205708 kb
Host smart-c9009bfe-d179-4f92-a1af-60555853147d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17940
31692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.1794031692
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.3661305179
Short name T1242
Test name
Test status
Simulation time 23601440875 ps
CPU time 311.48 seconds
Started Jun 06 01:44:53 PM PDT 24
Finished Jun 06 01:50:05 PM PDT 24
Peak memory 205716 kb
Host smart-fced743c-1e24-400f-b469-abf7a7e7869c
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661305179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_
traffic.3661305179
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.3982594483
Short name T525
Test name
Test status
Simulation time 10144147616 ps
CPU time 16.18 seconds
Started Jun 06 01:48:51 PM PDT 24
Finished Jun 06 01:49:09 PM PDT 24
Peak memory 205768 kb
Host smart-74280803-a290-41a9-b4fd-b8d446e4133f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3982594483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.3982594483
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.4127006712
Short name T526
Test name
Test status
Simulation time 10147892000 ps
CPU time 13.62 seconds
Started Jun 06 01:48:54 PM PDT 24
Finished Jun 06 01:49:09 PM PDT 24
Peak memory 205632 kb
Host smart-bccbcc37-e131-417b-a029-e3924d632538
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4127006712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.4127006712
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.1778815591
Short name T1294
Test name
Test status
Simulation time 10127077986 ps
CPU time 12.87 seconds
Started Jun 06 01:48:52 PM PDT 24
Finished Jun 06 01:49:07 PM PDT 24
Peak memory 205744 kb
Host smart-22f125de-c196-420c-8ab9-a27b57982777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17788
15591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.1778815591
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.211147698
Short name T14
Test name
Test status
Simulation time 13603353021 ps
CPU time 16.09 seconds
Started Jun 06 01:48:52 PM PDT 24
Finished Jun 06 01:49:11 PM PDT 24
Peak memory 205696 kb
Host smart-db5edfb7-8ce9-418f-bdfa-21545f5a9582
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=211147698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.211147698
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.1504012952
Short name T1954
Test name
Test status
Simulation time 23249377715 ps
CPU time 26.96 seconds
Started Jun 06 01:48:41 PM PDT 24
Finished Jun 06 01:49:09 PM PDT 24
Peak memory 205732 kb
Host smart-e3ed133e-5843-426f-949b-ee6728d7c6c1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1504012952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.1504012952
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3046089508
Short name T326
Test name
Test status
Simulation time 10071706707 ps
CPU time 15.24 seconds
Started Jun 06 01:48:47 PM PDT 24
Finished Jun 06 01:49:04 PM PDT 24
Peak memory 205724 kb
Host smart-da60655e-8028-4f95-9216-ed55788fbba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30460
89508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3046089508
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.1031236252
Short name T643
Test name
Test status
Simulation time 10631683096 ps
CPU time 15.81 seconds
Started Jun 06 01:48:41 PM PDT 24
Finished Jun 06 01:48:58 PM PDT 24
Peak memory 205600 kb
Host smart-429cc861-8eae-486b-a90d-ab815f66c74a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10312
36252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.1031236252
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.2182392348
Short name T1218
Test name
Test status
Simulation time 10059783538 ps
CPU time 14.76 seconds
Started Jun 06 01:48:45 PM PDT 24
Finished Jun 06 01:49:00 PM PDT 24
Peak memory 205740 kb
Host smart-986e3624-8218-4bcb-99d7-0ee112729291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21823
92348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2182392348
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.1919712931
Short name T1665
Test name
Test status
Simulation time 10057117410 ps
CPU time 13.82 seconds
Started Jun 06 01:48:41 PM PDT 24
Finished Jun 06 01:48:56 PM PDT 24
Peak memory 205600 kb
Host smart-2a387401-4d5e-4306-8a11-a650af81ca83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19197
12931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1919712931
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.2174822396
Short name T2030
Test name
Test status
Simulation time 10776844740 ps
CPU time 18.29 seconds
Started Jun 06 01:48:44 PM PDT 24
Finished Jun 06 01:49:03 PM PDT 24
Peak memory 205780 kb
Host smart-fda8f9d1-e976-434d-9b6a-ee6750d073b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21748
22396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.2174822396
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.3911282490
Short name T995
Test name
Test status
Simulation time 10156592846 ps
CPU time 14.87 seconds
Started Jun 06 01:48:43 PM PDT 24
Finished Jun 06 01:48:59 PM PDT 24
Peak memory 205664 kb
Host smart-86f02d6e-86f5-486b-850e-09420af1b087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39112
82490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3911282490
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.12898421
Short name T1588
Test name
Test status
Simulation time 10120363730 ps
CPU time 13 seconds
Started Jun 06 01:48:55 PM PDT 24
Finished Jun 06 01:49:09 PM PDT 24
Peak memory 205664 kb
Host smart-3f3a9bc7-97ba-4982-a860-1be2a7185398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12898
421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.12898421
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.2724144599
Short name T935
Test name
Test status
Simulation time 10038881553 ps
CPU time 13.09 seconds
Started Jun 06 01:48:51 PM PDT 24
Finished Jun 06 01:49:07 PM PDT 24
Peak memory 205784 kb
Host smart-a5f9732a-e964-405b-bfd5-d6f29f82839b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27241
44599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.2724144599
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.1442904832
Short name T793
Test name
Test status
Simulation time 10111900590 ps
CPU time 13.29 seconds
Started Jun 06 01:48:40 PM PDT 24
Finished Jun 06 01:48:54 PM PDT 24
Peak memory 205764 kb
Host smart-0e590d19-07cb-46f7-9bd5-1b6bd131290d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14429
04832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.1442904832
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.4105567411
Short name T778
Test name
Test status
Simulation time 10115151121 ps
CPU time 16.96 seconds
Started Jun 06 01:48:52 PM PDT 24
Finished Jun 06 01:49:12 PM PDT 24
Peak memory 205604 kb
Host smart-22da592a-99c9-4b48-bb5a-ae4ba2676fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41055
67411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.4105567411
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.3305572980
Short name T1950
Test name
Test status
Simulation time 13158303621 ps
CPU time 18.67 seconds
Started Jun 06 01:48:40 PM PDT 24
Finished Jun 06 01:49:00 PM PDT 24
Peak memory 205712 kb
Host smart-c892a238-38eb-4479-a120-c22f547eacf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33055
72980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.3305572980
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.2840026018
Short name T1366
Test name
Test status
Simulation time 10122673120 ps
CPU time 14.52 seconds
Started Jun 06 01:48:44 PM PDT 24
Finished Jun 06 01:48:59 PM PDT 24
Peak memory 205680 kb
Host smart-659eebd3-1909-4eb7-9035-bd134aaa1cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28400
26018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2840026018
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.3164754498
Short name T1446
Test name
Test status
Simulation time 14066157123 ps
CPU time 131.23 seconds
Started Jun 06 01:48:47 PM PDT 24
Finished Jun 06 01:50:59 PM PDT 24
Peak memory 205648 kb
Host smart-9466a11d-009a-4a26-9ed7-dd7c5a11b292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31647
54498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.3164754498
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.2368684918
Short name T1310
Test name
Test status
Simulation time 10075656398 ps
CPU time 12.84 seconds
Started Jun 06 01:48:44 PM PDT 24
Finished Jun 06 01:48:58 PM PDT 24
Peak memory 205652 kb
Host smart-e0689a69-44ef-42d5-8b3c-b74403dcaabc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23686
84918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.2368684918
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.8936446
Short name T128
Test name
Test status
Simulation time 10096356789 ps
CPU time 15.26 seconds
Started Jun 06 01:48:42 PM PDT 24
Finished Jun 06 01:48:58 PM PDT 24
Peak memory 205704 kb
Host smart-e201206e-e908-4ce9-8e9d-c8cb8ec17d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89364
46 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.8936446
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.4213440736
Short name T1855
Test name
Test status
Simulation time 10064563090 ps
CPU time 13.36 seconds
Started Jun 06 01:48:55 PM PDT 24
Finished Jun 06 01:49:10 PM PDT 24
Peak memory 205700 kb
Host smart-082121f8-96b3-42c6-911c-f1678ad281f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42134
40736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.4213440736
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.4132632506
Short name T744
Test name
Test status
Simulation time 10085292819 ps
CPU time 15.43 seconds
Started Jun 06 01:48:53 PM PDT 24
Finished Jun 06 01:49:10 PM PDT 24
Peak memory 205676 kb
Host smart-6728862b-f89e-4c00-b405-772b974045bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41326
32506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.4132632506
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3235732835
Short name T1142
Test name
Test status
Simulation time 10124832495 ps
CPU time 14.54 seconds
Started Jun 06 01:48:52 PM PDT 24
Finished Jun 06 01:49:09 PM PDT 24
Peak memory 205728 kb
Host smart-ed9c7029-aab5-43f2-ab05-9ea9176be91c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32357
32835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3235732835
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.1503078339
Short name T2006
Test name
Test status
Simulation time 10049381522 ps
CPU time 15.63 seconds
Started Jun 06 01:48:52 PM PDT 24
Finished Jun 06 01:49:10 PM PDT 24
Peak memory 205648 kb
Host smart-cd859147-6b63-486e-888d-5a91c4487c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15030
78339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.1503078339
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_eop_single_bit_handling.2482268390
Short name T1709
Test name
Test status
Simulation time 10096478389 ps
CPU time 14.53 seconds
Started Jun 06 01:48:50 PM PDT 24
Finished Jun 06 01:49:06 PM PDT 24
Peak memory 205672 kb
Host smart-03a1975a-d8cd-4861-95b1-df80dafdf3ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24822
68390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_eop_single_bit_handling.2482268390
Directory /workspace/20.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.3906534484
Short name T1985
Test name
Test status
Simulation time 10046108026 ps
CPU time 13.32 seconds
Started Jun 06 01:48:51 PM PDT 24
Finished Jun 06 01:49:06 PM PDT 24
Peak memory 205716 kb
Host smart-0bfe5d39-2027-4eab-be30-c56d7e52f90a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39065
34484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.3906534484
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.3769007004
Short name T851
Test name
Test status
Simulation time 10079419680 ps
CPU time 13.2 seconds
Started Jun 06 01:48:51 PM PDT 24
Finished Jun 06 01:49:07 PM PDT 24
Peak memory 205736 kb
Host smart-7acaaec5-da1a-43b8-a070-631617f71185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37690
07004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.3769007004
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.1229814728
Short name T1186
Test name
Test status
Simulation time 24099054463 ps
CPU time 49 seconds
Started Jun 06 01:48:53 PM PDT 24
Finished Jun 06 01:49:44 PM PDT 24
Peak memory 205688 kb
Host smart-1da6cef1-2195-4a4a-bccf-f256010caa8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12298
14728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.1229814728
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.231630007
Short name T416
Test name
Test status
Simulation time 10119360577 ps
CPU time 15.15 seconds
Started Jun 06 01:48:50 PM PDT 24
Finished Jun 06 01:49:07 PM PDT 24
Peak memory 205712 kb
Host smart-920b40d3-7b87-48f5-b030-027961b10417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23163
0007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.231630007
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.2085190200
Short name T482
Test name
Test status
Simulation time 10105302583 ps
CPU time 13.47 seconds
Started Jun 06 01:48:49 PM PDT 24
Finished Jun 06 01:49:04 PM PDT 24
Peak memory 205648 kb
Host smart-82adffe2-9488-4ece-b10e-5e192712f126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20851
90200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.2085190200
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.3834519459
Short name T1786
Test name
Test status
Simulation time 10064994567 ps
CPU time 15.04 seconds
Started Jun 06 01:48:50 PM PDT 24
Finished Jun 06 01:49:07 PM PDT 24
Peak memory 205744 kb
Host smart-517aacbe-f40b-4b9f-bd89-fc69df6378a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38345
19459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.3834519459
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.3951975283
Short name T418
Test name
Test status
Simulation time 10045009069 ps
CPU time 13.37 seconds
Started Jun 06 01:48:51 PM PDT 24
Finished Jun 06 01:49:06 PM PDT 24
Peak memory 205744 kb
Host smart-ce7b2200-5d4c-49f6-a77d-ae750078ea17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39519
75283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.3951975283
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.9911135
Short name T1192
Test name
Test status
Simulation time 10061948767 ps
CPU time 14.17 seconds
Started Jun 06 01:48:50 PM PDT 24
Finished Jun 06 01:49:06 PM PDT 24
Peak memory 205724 kb
Host smart-a325d37f-d60e-4808-9b45-9dfe6ecf5051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99111
35 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.9911135
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.3041118291
Short name T1772
Test name
Test status
Simulation time 10058145061 ps
CPU time 13.05 seconds
Started Jun 06 01:48:51 PM PDT 24
Finished Jun 06 01:49:07 PM PDT 24
Peak memory 205552 kb
Host smart-b3dde8e8-5536-4f9c-96b4-bfce18460b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30411
18291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.3041118291
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1841573530
Short name T136
Test name
Test status
Simulation time 10170445532 ps
CPU time 14.97 seconds
Started Jun 06 01:48:43 PM PDT 24
Finished Jun 06 01:48:59 PM PDT 24
Peak memory 205704 kb
Host smart-c4288e64-1cee-428f-af34-40eb54ba9a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18415
73530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1841573530
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.864734980
Short name T748
Test name
Test status
Simulation time 10066357325 ps
CPU time 16.89 seconds
Started Jun 06 01:48:53 PM PDT 24
Finished Jun 06 01:49:12 PM PDT 24
Peak memory 205760 kb
Host smart-892f8c51-951c-474b-9ec2-58c9ba8f6f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86473
4980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.864734980
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.2685614759
Short name T1394
Test name
Test status
Simulation time 10075364866 ps
CPU time 14.85 seconds
Started Jun 06 01:48:50 PM PDT 24
Finished Jun 06 01:49:07 PM PDT 24
Peak memory 205720 kb
Host smart-98f4eab0-baba-42cb-ab79-052af0efdf79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26856
14759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.2685614759
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.368976393
Short name T1629
Test name
Test status
Simulation time 17148553819 ps
CPU time 216.04 seconds
Started Jun 06 01:48:52 PM PDT 24
Finished Jun 06 01:52:30 PM PDT 24
Peak memory 205664 kb
Host smart-2a2eaca5-40a8-4679-b855-ce438b8a4ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36897
6393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.368976393
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.1950780691
Short name T1416
Test name
Test status
Simulation time 10151918272 ps
CPU time 13.11 seconds
Started Jun 06 01:49:03 PM PDT 24
Finished Jun 06 01:49:17 PM PDT 24
Peak memory 205756 kb
Host smart-867027f8-fb23-47cd-a2b1-0b51d1d090b1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1950780691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.1950780691
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.2706629760
Short name T1700
Test name
Test status
Simulation time 10065975802 ps
CPU time 13.51 seconds
Started Jun 06 01:49:04 PM PDT 24
Finished Jun 06 01:49:18 PM PDT 24
Peak memory 205740 kb
Host smart-d5e52eba-c1b9-4de1-915b-0dceb19168b6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2706629760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.2706629760
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.4023050744
Short name T1036
Test name
Test status
Simulation time 10175624401 ps
CPU time 16.11 seconds
Started Jun 06 01:49:05 PM PDT 24
Finished Jun 06 01:49:22 PM PDT 24
Peak memory 205768 kb
Host smart-3b3d6e08-1b72-45c5-b6a4-20874818e2f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40230
50744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.4023050744
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.2115810179
Short name T1949
Test name
Test status
Simulation time 13346388443 ps
CPU time 16.75 seconds
Started Jun 06 01:48:52 PM PDT 24
Finished Jun 06 01:49:11 PM PDT 24
Peak memory 205760 kb
Host smart-2affdc72-fe43-4e17-8139-0120eda0cfd1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2115810179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.2115810179
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.3564762337
Short name T1231
Test name
Test status
Simulation time 23220564100 ps
CPU time 25.34 seconds
Started Jun 06 01:48:52 PM PDT 24
Finished Jun 06 01:49:19 PM PDT 24
Peak memory 205708 kb
Host smart-70f2418d-c3ff-4122-97e8-030494647310
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3564762337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.3564762337
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.1827397210
Short name T1591
Test name
Test status
Simulation time 10096759801 ps
CPU time 13.95 seconds
Started Jun 06 01:48:51 PM PDT 24
Finished Jun 06 01:49:07 PM PDT 24
Peak memory 205732 kb
Host smart-dcc0f138-9424-48fa-b72f-1000b1cc90f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18273
97210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.1827397210
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.3315879931
Short name T780
Test name
Test status
Simulation time 10290073990 ps
CPU time 17.99 seconds
Started Jun 06 01:48:51 PM PDT 24
Finished Jun 06 01:49:10 PM PDT 24
Peak memory 205700 kb
Host smart-3c2b083d-2e27-4f3e-833a-30056465f2b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33158
79931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.3315879931
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.3404532911
Short name T1623
Test name
Test status
Simulation time 10039880267 ps
CPU time 14.59 seconds
Started Jun 06 01:48:59 PM PDT 24
Finished Jun 06 01:49:15 PM PDT 24
Peak memory 205716 kb
Host smart-c41acf66-583d-4cae-89c4-47bdb2f9fd23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34045
32911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.3404532911
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.3248829714
Short name T373
Test name
Test status
Simulation time 10068126935 ps
CPU time 16.55 seconds
Started Jun 06 01:49:02 PM PDT 24
Finished Jun 06 01:49:19 PM PDT 24
Peak memory 205712 kb
Host smart-b19995cc-b587-4e01-966d-cc8c95f1bb0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32488
29714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.3248829714
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.690915432
Short name T385
Test name
Test status
Simulation time 10806966599 ps
CPU time 14.66 seconds
Started Jun 06 01:48:53 PM PDT 24
Finished Jun 06 01:49:09 PM PDT 24
Peak memory 205632 kb
Host smart-2b4322bb-2ac4-4c1e-afa5-f97f76e18277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69091
5432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.690915432
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.3859585404
Short name T537
Test name
Test status
Simulation time 10045411222 ps
CPU time 14.33 seconds
Started Jun 06 01:48:58 PM PDT 24
Finished Jun 06 01:49:13 PM PDT 24
Peak memory 205636 kb
Host smart-b4613e1d-18f7-449b-a3ce-cf6e0b1cf66d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38595
85404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.3859585404
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.137588806
Short name T1983
Test name
Test status
Simulation time 10143314921 ps
CPU time 13.94 seconds
Started Jun 06 01:49:05 PM PDT 24
Finished Jun 06 01:49:20 PM PDT 24
Peak memory 205784 kb
Host smart-3d73aa5b-07f6-4da1-95f4-3a2bfe2736a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13758
8806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.137588806
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.1610672241
Short name T1537
Test name
Test status
Simulation time 10040336659 ps
CPU time 15.32 seconds
Started Jun 06 01:49:04 PM PDT 24
Finished Jun 06 01:49:20 PM PDT 24
Peak memory 205656 kb
Host smart-2740f68c-7e5c-4dd4-b8af-cd4b1723ba6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16106
72241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.1610672241
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.2726837727
Short name T881
Test name
Test status
Simulation time 10095322505 ps
CPU time 14.7 seconds
Started Jun 06 01:49:01 PM PDT 24
Finished Jun 06 01:49:17 PM PDT 24
Peak memory 205696 kb
Host smart-b79ee59d-5563-412c-bf8d-e4903621401d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27268
37727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.2726837727
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.3919606751
Short name T1254
Test name
Test status
Simulation time 10102821960 ps
CPU time 15.56 seconds
Started Jun 06 01:49:02 PM PDT 24
Finished Jun 06 01:49:18 PM PDT 24
Peak memory 205684 kb
Host smart-fad07d07-45d0-47ca-9b59-33fd2bc79f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39196
06751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.3919606751
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.1140179428
Short name T424
Test name
Test status
Simulation time 13276382878 ps
CPU time 15.85 seconds
Started Jun 06 01:49:03 PM PDT 24
Finished Jun 06 01:49:20 PM PDT 24
Peak memory 205692 kb
Host smart-0e2f824e-42f3-47d5-b25b-ef7d0f1c573e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11401
79428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.1140179428
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2017272320
Short name T1552
Test name
Test status
Simulation time 10099073277 ps
CPU time 17.71 seconds
Started Jun 06 01:48:59 PM PDT 24
Finished Jun 06 01:49:18 PM PDT 24
Peak memory 205604 kb
Host smart-68add19a-c13c-434e-bf02-e6052c4c8df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20172
72320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2017272320
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.3908451842
Short name T688
Test name
Test status
Simulation time 24330290874 ps
CPU time 121.51 seconds
Started Jun 06 01:49:03 PM PDT 24
Finished Jun 06 01:51:05 PM PDT 24
Peak memory 205732 kb
Host smart-cb3d7111-e59d-463d-82b6-6f0f6924d405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39084
51842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.3908451842
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3252594028
Short name T765
Test name
Test status
Simulation time 10039200157 ps
CPU time 13.71 seconds
Started Jun 06 01:48:59 PM PDT 24
Finished Jun 06 01:49:14 PM PDT 24
Peak memory 205704 kb
Host smart-4613c168-9e7c-44ad-8c15-880b5e858e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32525
94028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3252594028
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.87171426
Short name T1929
Test name
Test status
Simulation time 10087879192 ps
CPU time 15.24 seconds
Started Jun 06 01:49:02 PM PDT 24
Finished Jun 06 01:49:18 PM PDT 24
Peak memory 205724 kb
Host smart-520528f7-abfc-4d1b-9043-536b1e15bdbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87171
426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.87171426
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.816483992
Short name T2026
Test name
Test status
Simulation time 10088198194 ps
CPU time 14.45 seconds
Started Jun 06 01:48:59 PM PDT 24
Finished Jun 06 01:49:15 PM PDT 24
Peak memory 205660 kb
Host smart-5b908c45-1ffb-4288-9b29-33888dfdfab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81648
3992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.816483992
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1629017035
Short name T952
Test name
Test status
Simulation time 10075234899 ps
CPU time 14.99 seconds
Started Jun 06 01:49:01 PM PDT 24
Finished Jun 06 01:49:17 PM PDT 24
Peak memory 205700 kb
Host smart-b3ee361e-3352-4e50-afef-24d7d7eec298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16290
17035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1629017035
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.2387945839
Short name T1898
Test name
Test status
Simulation time 10052407068 ps
CPU time 14.1 seconds
Started Jun 06 01:49:04 PM PDT 24
Finished Jun 06 01:49:19 PM PDT 24
Peak memory 205616 kb
Host smart-0a0c1c2e-7636-4f90-a294-1c9b2f3139a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23879
45839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.2387945839
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_eop_single_bit_handling.93091495
Short name T89
Test name
Test status
Simulation time 10052624679 ps
CPU time 13.63 seconds
Started Jun 06 01:48:59 PM PDT 24
Finished Jun 06 01:49:14 PM PDT 24
Peak memory 205656 kb
Host smart-283dc817-9808-4714-abff-7aa79c679948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93091
495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_eop_single_bit_handling.93091495
Directory /workspace/21.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.2883572832
Short name T1102
Test name
Test status
Simulation time 10039486126 ps
CPU time 13.12 seconds
Started Jun 06 01:49:01 PM PDT 24
Finished Jun 06 01:49:15 PM PDT 24
Peak memory 205776 kb
Host smart-ee8e95e6-77e5-4e8f-89c4-71bd3d29671a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28835
72832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.2883572832
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.1479861557
Short name T1903
Test name
Test status
Simulation time 10058252218 ps
CPU time 15.23 seconds
Started Jun 06 01:48:59 PM PDT 24
Finished Jun 06 01:49:15 PM PDT 24
Peak memory 205644 kb
Host smart-8c0bb108-d5f1-4828-b5ee-18b669a7c9b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14798
61557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.1479861557
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.749011058
Short name T437
Test name
Test status
Simulation time 27481941991 ps
CPU time 52.21 seconds
Started Jun 06 01:49:04 PM PDT 24
Finished Jun 06 01:49:56 PM PDT 24
Peak memory 205692 kb
Host smart-7177929f-6c71-4ab4-a48a-6b2b67786e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74901
1058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.749011058
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.2421263534
Short name T1813
Test name
Test status
Simulation time 10090266696 ps
CPU time 14.34 seconds
Started Jun 06 01:48:59 PM PDT 24
Finished Jun 06 01:49:14 PM PDT 24
Peak memory 205664 kb
Host smart-b09a4f2f-ce40-4fee-8ba7-b1e9f631a6c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24212
63534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.2421263534
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.164604931
Short name T803
Test name
Test status
Simulation time 10083748466 ps
CPU time 13.28 seconds
Started Jun 06 01:49:00 PM PDT 24
Finished Jun 06 01:49:14 PM PDT 24
Peak memory 205668 kb
Host smart-cc836b32-5a75-4fd7-a091-0cf167d113b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16460
4931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.164604931
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.2767512535
Short name T1038
Test name
Test status
Simulation time 10076104695 ps
CPU time 13.64 seconds
Started Jun 06 01:49:04 PM PDT 24
Finished Jun 06 01:49:18 PM PDT 24
Peak memory 205612 kb
Host smart-a67ac19b-3234-4e6d-be69-73127aff8494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27675
12535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.2767512535
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.2529660793
Short name T1774
Test name
Test status
Simulation time 10059806314 ps
CPU time 14.87 seconds
Started Jun 06 01:48:59 PM PDT 24
Finished Jun 06 01:49:15 PM PDT 24
Peak memory 205692 kb
Host smart-1d8ba057-bd37-457d-b7f0-43df7b06e906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25296
60793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.2529660793
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.3518700299
Short name T1667
Test name
Test status
Simulation time 10058388295 ps
CPU time 14.3 seconds
Started Jun 06 01:48:59 PM PDT 24
Finished Jun 06 01:49:14 PM PDT 24
Peak memory 205736 kb
Host smart-cbe926ed-ad01-4788-8e40-1cf29bb97268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35187
00299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.3518700299
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.174685971
Short name T695
Test name
Test status
Simulation time 10050482664 ps
CPU time 14.92 seconds
Started Jun 06 01:48:59 PM PDT 24
Finished Jun 06 01:49:15 PM PDT 24
Peak memory 205668 kb
Host smart-db489077-ecde-46a6-badb-10232f4082f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17468
5971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.174685971
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.2280936713
Short name T1452
Test name
Test status
Simulation time 10111523883 ps
CPU time 13.89 seconds
Started Jun 06 01:48:55 PM PDT 24
Finished Jun 06 01:49:10 PM PDT 24
Peak memory 205696 kb
Host smart-037f964b-e0ad-4f63-ac0e-c985d4084f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22809
36713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.2280936713
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.1901286352
Short name T1586
Test name
Test status
Simulation time 10075427278 ps
CPU time 16.3 seconds
Started Jun 06 01:49:00 PM PDT 24
Finished Jun 06 01:49:17 PM PDT 24
Peak memory 205692 kb
Host smart-689a0872-ccc8-4b87-b306-2cac253b9857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19012
86352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.1901286352
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.2242547362
Short name T711
Test name
Test status
Simulation time 10103569233 ps
CPU time 15.73 seconds
Started Jun 06 01:49:00 PM PDT 24
Finished Jun 06 01:49:16 PM PDT 24
Peak memory 205620 kb
Host smart-8436c720-fd53-4cb4-9707-3f06f521fe8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22425
47362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.2242547362
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.4151199252
Short name T551
Test name
Test status
Simulation time 23552583360 ps
CPU time 143.24 seconds
Started Jun 06 01:49:01 PM PDT 24
Finished Jun 06 01:51:25 PM PDT 24
Peak memory 205780 kb
Host smart-f796dbf7-8525-4276-a57a-a07f3077a4f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41511
99252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.4151199252
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.575570377
Short name T1347
Test name
Test status
Simulation time 10140242952 ps
CPU time 13.5 seconds
Started Jun 06 01:49:10 PM PDT 24
Finished Jun 06 01:49:24 PM PDT 24
Peak memory 205752 kb
Host smart-259ce8ed-19ce-4d72-bfc3-e7d71098a193
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=575570377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.575570377
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.3532162989
Short name T459
Test name
Test status
Simulation time 10054455531 ps
CPU time 14.4 seconds
Started Jun 06 01:49:11 PM PDT 24
Finished Jun 06 01:49:26 PM PDT 24
Peak memory 205764 kb
Host smart-d500d1bf-ab01-49c6-91f1-83abec0618c1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3532162989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.3532162989
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.62180731
Short name T844
Test name
Test status
Simulation time 10131456207 ps
CPU time 16.92 seconds
Started Jun 06 01:49:10 PM PDT 24
Finished Jun 06 01:49:28 PM PDT 24
Peak memory 205596 kb
Host smart-f3a66e79-dbff-4f62-bbf5-66c2139efc57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62180
731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.62180731
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.2908058743
Short name T950
Test name
Test status
Simulation time 13509586780 ps
CPU time 17.99 seconds
Started Jun 06 01:49:03 PM PDT 24
Finished Jun 06 01:49:22 PM PDT 24
Peak memory 205744 kb
Host smart-97781765-113f-4bf5-92d1-4e4f37f7cd9d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2908058743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.2908058743
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.955960651
Short name T1489
Test name
Test status
Simulation time 23387211345 ps
CPU time 30.34 seconds
Started Jun 06 01:49:01 PM PDT 24
Finished Jun 06 01:49:32 PM PDT 24
Peak memory 205700 kb
Host smart-d10fc1aa-c71f-433d-acea-5f2f902fcd6f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=955960651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.955960651
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3614582860
Short name T1631
Test name
Test status
Simulation time 10076851460 ps
CPU time 13.8 seconds
Started Jun 06 01:49:00 PM PDT 24
Finished Jun 06 01:49:15 PM PDT 24
Peak memory 205652 kb
Host smart-9d0bcbbe-6fcd-4143-a9eb-25b857c31a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36145
82860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3614582860
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.513619085
Short name T59
Test name
Test status
Simulation time 10124428029 ps
CPU time 13.22 seconds
Started Jun 06 01:49:24 PM PDT 24
Finished Jun 06 01:49:39 PM PDT 24
Peak memory 205740 kb
Host smart-8c113731-4962-4145-aab7-0b7af62e0b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51361
9085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.513619085
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.3402071088
Short name T1058
Test name
Test status
Simulation time 10973770240 ps
CPU time 16.06 seconds
Started Jun 06 01:49:00 PM PDT 24
Finished Jun 06 01:49:17 PM PDT 24
Peak memory 205732 kb
Host smart-422a70ae-0950-4afd-8821-45fcbfa7f91e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34020
71088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.3402071088
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.3634991553
Short name T1627
Test name
Test status
Simulation time 10077399151 ps
CPU time 12.19 seconds
Started Jun 06 01:49:09 PM PDT 24
Finished Jun 06 01:49:22 PM PDT 24
Peak memory 205712 kb
Host smart-216baf10-cfe5-487d-8f9f-dc44e83108b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36349
91553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.3634991553
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.933350391
Short name T924
Test name
Test status
Simulation time 10060021303 ps
CPU time 13.52 seconds
Started Jun 06 01:49:03 PM PDT 24
Finished Jun 06 01:49:17 PM PDT 24
Peak memory 205676 kb
Host smart-3b860152-0ef5-4ed4-a259-73db5c32e12a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93335
0391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.933350391
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.1504971454
Short name T1114
Test name
Test status
Simulation time 10777954668 ps
CPU time 14.91 seconds
Started Jun 06 01:49:00 PM PDT 24
Finished Jun 06 01:49:16 PM PDT 24
Peak memory 205740 kb
Host smart-e74e0db4-a0c1-4f01-99f7-9e8c55c0ac91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15049
71454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.1504971454
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.2720502094
Short name T945
Test name
Test status
Simulation time 10062395398 ps
CPU time 14.99 seconds
Started Jun 06 01:49:07 PM PDT 24
Finished Jun 06 01:49:23 PM PDT 24
Peak memory 205652 kb
Host smart-20717d80-028c-4f96-9163-e64c48b4b70a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27205
02094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.2720502094
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.2571001691
Short name T1622
Test name
Test status
Simulation time 10119503420 ps
CPU time 16.84 seconds
Started Jun 06 01:49:12 PM PDT 24
Finished Jun 06 01:49:30 PM PDT 24
Peak memory 205668 kb
Host smart-9a9c4753-b4c8-4fd0-8f46-66ffb7b3cff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25710
01691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.2571001691
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.1230405606
Short name T208
Test name
Test status
Simulation time 10081528858 ps
CPU time 13.46 seconds
Started Jun 06 01:49:14 PM PDT 24
Finished Jun 06 01:49:28 PM PDT 24
Peak memory 205652 kb
Host smart-78116154-27c1-42d5-9caa-e2202d334498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12304
05606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1230405606
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.2287223035
Short name T1073
Test name
Test status
Simulation time 10115889030 ps
CPU time 13.21 seconds
Started Jun 06 01:49:13 PM PDT 24
Finished Jun 06 01:49:27 PM PDT 24
Peak memory 205656 kb
Host smart-83aceec4-a9c2-4394-9f8e-ce88e97219f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22872
23035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.2287223035
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.4244238614
Short name T20
Test name
Test status
Simulation time 10139081243 ps
CPU time 13.86 seconds
Started Jun 06 01:49:09 PM PDT 24
Finished Jun 06 01:49:24 PM PDT 24
Peak memory 205692 kb
Host smart-b83f8c0c-6fff-48fb-888b-38d145b92e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42442
38614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.4244238614
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.2751568781
Short name T355
Test name
Test status
Simulation time 13227033318 ps
CPU time 18.4 seconds
Started Jun 06 01:49:10 PM PDT 24
Finished Jun 06 01:49:29 PM PDT 24
Peak memory 205704 kb
Host smart-b6db294f-e83b-473b-ad8f-41bc4abe9542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27515
68781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.2751568781
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3817195552
Short name T28
Test name
Test status
Simulation time 10085245022 ps
CPU time 15.36 seconds
Started Jun 06 01:49:11 PM PDT 24
Finished Jun 06 01:49:27 PM PDT 24
Peak memory 205680 kb
Host smart-f5b2e6ed-5be1-415d-92b7-b05c151f22ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38171
95552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3817195552
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.3003491570
Short name T981
Test name
Test status
Simulation time 15290866362 ps
CPU time 171.04 seconds
Started Jun 06 01:49:09 PM PDT 24
Finished Jun 06 01:52:00 PM PDT 24
Peak memory 205680 kb
Host smart-5bb8446f-8321-4c9b-854c-e0cfaf0e13dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30034
91570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.3003491570
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.4193838414
Short name T1785
Test name
Test status
Simulation time 10103254123 ps
CPU time 13.33 seconds
Started Jun 06 01:49:12 PM PDT 24
Finished Jun 06 01:49:27 PM PDT 24
Peak memory 205748 kb
Host smart-4f9b2da4-e9a8-43bb-b535-47005ecf023a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41938
38414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.4193838414
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.1777641102
Short name T1995
Test name
Test status
Simulation time 10063405036 ps
CPU time 14.8 seconds
Started Jun 06 01:49:09 PM PDT 24
Finished Jun 06 01:49:25 PM PDT 24
Peak memory 205676 kb
Host smart-62559000-e200-4518-b23f-d4953c6d6c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17776
41102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.1777641102
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.4202949161
Short name T307
Test name
Test status
Simulation time 10059594799 ps
CPU time 14.14 seconds
Started Jun 06 01:49:10 PM PDT 24
Finished Jun 06 01:49:25 PM PDT 24
Peak memory 205648 kb
Host smart-1a392e8e-ec40-4453-a6dd-eb42cfb67057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42029
49161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.4202949161
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.635616966
Short name T1546
Test name
Test status
Simulation time 10120778018 ps
CPU time 12.95 seconds
Started Jun 06 01:49:12 PM PDT 24
Finished Jun 06 01:49:25 PM PDT 24
Peak memory 205600 kb
Host smart-0205083e-d421-44fd-a1b7-c4e4d400294c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63561
6966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.635616966
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.81687498
Short name T1325
Test name
Test status
Simulation time 10073367216 ps
CPU time 13.84 seconds
Started Jun 06 01:49:10 PM PDT 24
Finished Jun 06 01:49:24 PM PDT 24
Peak memory 205632 kb
Host smart-847762e3-51d2-4784-a551-2320d44851ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81687
498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.81687498
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_eop_single_bit_handling.2230053699
Short name T1923
Test name
Test status
Simulation time 10041323939 ps
CPU time 12.72 seconds
Started Jun 06 01:49:12 PM PDT 24
Finished Jun 06 01:49:25 PM PDT 24
Peak memory 205672 kb
Host smart-d0f32da0-48a9-41a0-8f51-65481965759e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22300
53699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_eop_single_bit_handling.2230053699
Directory /workspace/22.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.1803973239
Short name T450
Test name
Test status
Simulation time 10049243893 ps
CPU time 13.02 seconds
Started Jun 06 01:49:11 PM PDT 24
Finished Jun 06 01:49:25 PM PDT 24
Peak memory 205716 kb
Host smart-d6ee15fe-9653-4f64-bc12-334f154c1550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18039
73239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.1803973239
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.4286287577
Short name T396
Test name
Test status
Simulation time 10061004370 ps
CPU time 12.92 seconds
Started Jun 06 01:49:09 PM PDT 24
Finished Jun 06 01:49:23 PM PDT 24
Peak memory 205768 kb
Host smart-ba4be743-fefd-424c-b8c0-31d6017b066f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42862
87577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.4286287577
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.2966252124
Short name T1596
Test name
Test status
Simulation time 10087782460 ps
CPU time 14.68 seconds
Started Jun 06 01:49:08 PM PDT 24
Finished Jun 06 01:49:23 PM PDT 24
Peak memory 205712 kb
Host smart-b579cf48-25c5-4887-9658-542d32aa6e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29662
52124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2966252124
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.4127672015
Short name T1247
Test name
Test status
Simulation time 10068427737 ps
CPU time 13.26 seconds
Started Jun 06 01:49:09 PM PDT 24
Finished Jun 06 01:49:23 PM PDT 24
Peak memory 205620 kb
Host smart-0f0c2c88-700f-4f0a-9c26-b0e973c90be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41276
72015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.4127672015
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.3356176277
Short name T818
Test name
Test status
Simulation time 10050557297 ps
CPU time 13.13 seconds
Started Jun 06 01:49:12 PM PDT 24
Finished Jun 06 01:49:26 PM PDT 24
Peak memory 205688 kb
Host smart-9124c448-ff0d-4d33-b8d3-3edeea26a155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33561
76277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.3356176277
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.3329677375
Short name T791
Test name
Test status
Simulation time 10037611487 ps
CPU time 13.65 seconds
Started Jun 06 01:49:11 PM PDT 24
Finished Jun 06 01:49:25 PM PDT 24
Peak memory 205648 kb
Host smart-fba7c886-f02b-495e-8f93-ebf31f464d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33296
77375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.3329677375
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.674007991
Short name T1989
Test name
Test status
Simulation time 10050500841 ps
CPU time 14.77 seconds
Started Jun 06 01:49:12 PM PDT 24
Finished Jun 06 01:49:28 PM PDT 24
Peak memory 205724 kb
Host smart-9d3d26c3-b381-4460-be2c-7a3dd9b497be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67400
7991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.674007991
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.2648701003
Short name T1982
Test name
Test status
Simulation time 10073285242 ps
CPU time 15.25 seconds
Started Jun 06 01:49:13 PM PDT 24
Finished Jun 06 01:49:29 PM PDT 24
Peak memory 205732 kb
Host smart-e71f1a95-3826-4446-a232-32c7b1c61525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26487
01003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.2648701003
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.1264140331
Short name T483
Test name
Test status
Simulation time 10094054349 ps
CPU time 14.49 seconds
Started Jun 06 01:49:11 PM PDT 24
Finished Jun 06 01:49:27 PM PDT 24
Peak memory 205620 kb
Host smart-d3be9a0a-09ac-4c33-b93d-b839bd2c6680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12641
40331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.1264140331
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.3881335212
Short name T875
Test name
Test status
Simulation time 10099641678 ps
CPU time 15.7 seconds
Started Jun 06 01:49:14 PM PDT 24
Finished Jun 06 01:49:31 PM PDT 24
Peak memory 205764 kb
Host smart-6b25f404-ae61-4dc7-9e69-5715c477f81f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38813
35212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.3881335212
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.3385508632
Short name T1742
Test name
Test status
Simulation time 21772283362 ps
CPU time 125.65 seconds
Started Jun 06 01:49:10 PM PDT 24
Finished Jun 06 01:51:16 PM PDT 24
Peak memory 205720 kb
Host smart-915aebaa-efc8-440b-a036-276ca557863a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33855
08632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.3385508632
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.3186203003
Short name T2008
Test name
Test status
Simulation time 10137726207 ps
CPU time 13.57 seconds
Started Jun 06 01:49:29 PM PDT 24
Finished Jun 06 01:49:44 PM PDT 24
Peak memory 205720 kb
Host smart-c93a4015-3b50-4824-903c-82ac8a8e104b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3186203003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.3186203003
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.2986217983
Short name T494
Test name
Test status
Simulation time 10061565924 ps
CPU time 15.11 seconds
Started Jun 06 01:49:30 PM PDT 24
Finished Jun 06 01:49:46 PM PDT 24
Peak memory 205744 kb
Host smart-c03e28fd-1382-4c1e-8d1d-42a2d24fde81
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2986217983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.2986217983
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.2649072810
Short name T926
Test name
Test status
Simulation time 10080414945 ps
CPU time 13.56 seconds
Started Jun 06 01:49:41 PM PDT 24
Finished Jun 06 01:49:55 PM PDT 24
Peak memory 205548 kb
Host smart-d82dfbd1-15cd-4ca1-b0d9-41523f2cf74f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26490
72810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.2649072810
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.3910409764
Short name T1253
Test name
Test status
Simulation time 14242895002 ps
CPU time 19.18 seconds
Started Jun 06 01:49:20 PM PDT 24
Finished Jun 06 01:49:40 PM PDT 24
Peak memory 206012 kb
Host smart-30fe8ca6-22ff-4792-8c6c-8fef16a5f279
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3910409764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.3910409764
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.1274601063
Short name T1723
Test name
Test status
Simulation time 23232199496 ps
CPU time 29.93 seconds
Started Jun 06 01:49:22 PM PDT 24
Finished Jun 06 01:49:53 PM PDT 24
Peak memory 205732 kb
Host smart-25b558fc-13ad-441b-934c-e1e42cff773c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1274601063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.1274601063
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.2855554331
Short name T1823
Test name
Test status
Simulation time 10055940061 ps
CPU time 13.73 seconds
Started Jun 06 01:49:20 PM PDT 24
Finished Jun 06 01:49:35 PM PDT 24
Peak memory 205728 kb
Host smart-2cece499-999a-4f0f-9bc0-628abb5c6d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28555
54331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2855554331
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.3032822395
Short name T58
Test name
Test status
Simulation time 10074334047 ps
CPU time 13.18 seconds
Started Jun 06 01:49:20 PM PDT 24
Finished Jun 06 01:49:34 PM PDT 24
Peak memory 205640 kb
Host smart-1bc5e8c2-49c2-4e8d-ade4-93305b278684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30328
22395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.3032822395
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.2443709964
Short name T1381
Test name
Test status
Simulation time 10556502944 ps
CPU time 14.89 seconds
Started Jun 06 01:49:20 PM PDT 24
Finished Jun 06 01:49:36 PM PDT 24
Peak memory 205772 kb
Host smart-a04d553e-35d1-4f30-8533-218bbbf5d8d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24437
09964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.2443709964
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.272040953
Short name T639
Test name
Test status
Simulation time 10043790005 ps
CPU time 15.67 seconds
Started Jun 06 01:49:21 PM PDT 24
Finished Jun 06 01:49:37 PM PDT 24
Peak memory 205532 kb
Host smart-1f553bcd-1936-47a9-9d72-35eae461b48c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27204
0953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.272040953
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.3955442412
Short name T2031
Test name
Test status
Simulation time 10072062634 ps
CPU time 14.6 seconds
Started Jun 06 01:49:19 PM PDT 24
Finished Jun 06 01:49:35 PM PDT 24
Peak memory 205624 kb
Host smart-4e755301-d34e-4b96-aa8d-0964e8bdc964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39554
42412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3955442412
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.1360323884
Short name T1143
Test name
Test status
Simulation time 10700435218 ps
CPU time 15.38 seconds
Started Jun 06 01:49:22 PM PDT 24
Finished Jun 06 01:49:39 PM PDT 24
Peak memory 205656 kb
Host smart-9658a9b1-7814-4550-8ff6-7f5c3132f710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13603
23884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.1360323884
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.1057743877
Short name T794
Test name
Test status
Simulation time 10186890188 ps
CPU time 14.89 seconds
Started Jun 06 01:49:21 PM PDT 24
Finished Jun 06 01:49:37 PM PDT 24
Peak memory 205748 kb
Host smart-0d119f31-b381-4559-9ef5-e270aa8d43be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10577
43877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.1057743877
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.1280636039
Short name T389
Test name
Test status
Simulation time 10110317927 ps
CPU time 12.73 seconds
Started Jun 06 01:49:29 PM PDT 24
Finished Jun 06 01:49:42 PM PDT 24
Peak memory 205708 kb
Host smart-96594f64-ad18-41c0-9bd5-1ce7fd523aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12806
36039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.1280636039
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.3437056568
Short name T80
Test name
Test status
Simulation time 10106377438 ps
CPU time 14.42 seconds
Started Jun 06 01:49:28 PM PDT 24
Finished Jun 06 01:49:43 PM PDT 24
Peak memory 205624 kb
Host smart-7e9085cd-34a7-458d-bf25-a132e02b051d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34370
56568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3437056568
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.3326785568
Short name T1752
Test name
Test status
Simulation time 10130406307 ps
CPU time 14.27 seconds
Started Jun 06 01:49:19 PM PDT 24
Finished Jun 06 01:49:34 PM PDT 24
Peak memory 205980 kb
Host smart-c04c1554-0d81-4276-b134-6d21d985da00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33267
85568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.3326785568
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.715687653
Short name T1165
Test name
Test status
Simulation time 10084660323 ps
CPU time 12.23 seconds
Started Jun 06 01:49:19 PM PDT 24
Finished Jun 06 01:49:32 PM PDT 24
Peak memory 205648 kb
Host smart-6649a0c1-9c03-4341-b2e7-fa5644db60a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71568
7653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.715687653
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.4002907982
Short name T1044
Test name
Test status
Simulation time 13204640382 ps
CPU time 16.46 seconds
Started Jun 06 01:49:22 PM PDT 24
Finished Jun 06 01:49:40 PM PDT 24
Peak memory 205744 kb
Host smart-1c0eff32-a591-4f90-be4b-264f20d241f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40029
07982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.4002907982
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2719104662
Short name T720
Test name
Test status
Simulation time 10097554982 ps
CPU time 13.11 seconds
Started Jun 06 01:49:21 PM PDT 24
Finished Jun 06 01:49:36 PM PDT 24
Peak memory 205760 kb
Host smart-29d7719f-c648-4002-9722-01f7f2cd280f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27191
04662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2719104662
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.3709598067
Short name T1128
Test name
Test status
Simulation time 14546599276 ps
CPU time 56.08 seconds
Started Jun 06 01:49:18 PM PDT 24
Finished Jun 06 01:50:15 PM PDT 24
Peak memory 205748 kb
Host smart-9fcb6326-beab-4442-8010-4638cba76db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37095
98067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.3709598067
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.627100007
Short name T704
Test name
Test status
Simulation time 10069038737 ps
CPU time 16.12 seconds
Started Jun 06 01:49:24 PM PDT 24
Finished Jun 06 01:49:41 PM PDT 24
Peak memory 205696 kb
Host smart-9c6ac3db-49d6-4eb1-90ac-a25a6e945e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62710
0007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.627100007
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.890961411
Short name T1472
Test name
Test status
Simulation time 10118490623 ps
CPU time 12.57 seconds
Started Jun 06 01:49:21 PM PDT 24
Finished Jun 06 01:49:34 PM PDT 24
Peak memory 205520 kb
Host smart-100346a7-624c-40df-a801-392987246b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89096
1411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.890961411
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.3939698880
Short name T1799
Test name
Test status
Simulation time 10136751797 ps
CPU time 16.98 seconds
Started Jun 06 01:49:24 PM PDT 24
Finished Jun 06 01:49:42 PM PDT 24
Peak memory 205644 kb
Host smart-fe1eaf01-2019-427e-a48f-89d9621c639c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39396
98880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.3939698880
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.831544889
Short name T602
Test name
Test status
Simulation time 10108951838 ps
CPU time 13 seconds
Started Jun 06 01:49:20 PM PDT 24
Finished Jun 06 01:49:34 PM PDT 24
Peak memory 205624 kb
Host smart-8c20d824-811b-4913-a75d-50679eecee9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83154
4889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.831544889
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.1580685031
Short name T2000
Test name
Test status
Simulation time 10072415751 ps
CPU time 14.51 seconds
Started Jun 06 01:49:21 PM PDT 24
Finished Jun 06 01:49:36 PM PDT 24
Peak memory 205764 kb
Host smart-a16da4d2-0cbd-4f20-8dad-fd0234e5eecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15806
85031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1580685031
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.1173449134
Short name T1132
Test name
Test status
Simulation time 10053969972 ps
CPU time 13.57 seconds
Started Jun 06 01:49:31 PM PDT 24
Finished Jun 06 01:49:46 PM PDT 24
Peak memory 205788 kb
Host smart-146d8ac1-ccf1-4c12-92b9-3b4b1e226a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11734
49134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.1173449134
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_eop_single_bit_handling.3835628738
Short name T712
Test name
Test status
Simulation time 10056697768 ps
CPU time 16.51 seconds
Started Jun 06 01:49:30 PM PDT 24
Finished Jun 06 01:49:48 PM PDT 24
Peak memory 205664 kb
Host smart-87b16a3a-5cd9-4535-a322-84600262f6b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38356
28738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_eop_single_bit_handling.3835628738
Directory /workspace/23.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.2066867443
Short name T1157
Test name
Test status
Simulation time 10040006110 ps
CPU time 17.15 seconds
Started Jun 06 01:49:31 PM PDT 24
Finished Jun 06 01:49:49 PM PDT 24
Peak memory 205744 kb
Host smart-3b39aadd-2ec2-415e-9f5c-40b103bc120a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20668
67443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.2066867443
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2264323640
Short name T1928
Test name
Test status
Simulation time 10036153897 ps
CPU time 13.74 seconds
Started Jun 06 01:49:30 PM PDT 24
Finished Jun 06 01:49:45 PM PDT 24
Peak memory 205616 kb
Host smart-dab530a6-03be-4b25-be1b-69de03e83660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22643
23640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2264323640
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.2900247699
Short name T172
Test name
Test status
Simulation time 31079101184 ps
CPU time 65.21 seconds
Started Jun 06 01:49:20 PM PDT 24
Finished Jun 06 01:50:26 PM PDT 24
Peak memory 205640 kb
Host smart-bbb46b21-5500-4c93-8e66-2009ed191c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29002
47699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.2900247699
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.935234827
Short name T1045
Test name
Test status
Simulation time 10134350854 ps
CPU time 13.53 seconds
Started Jun 06 01:49:19 PM PDT 24
Finished Jun 06 01:49:33 PM PDT 24
Peak memory 205660 kb
Host smart-c0360e27-05e1-43bb-8c11-ac46cf194b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93523
4827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.935234827
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.1448817830
Short name T1918
Test name
Test status
Simulation time 10069371969 ps
CPU time 14.46 seconds
Started Jun 06 01:49:27 PM PDT 24
Finished Jun 06 01:49:42 PM PDT 24
Peak memory 205688 kb
Host smart-d56b09a2-da54-4c08-a472-57aa1adb18bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14488
17830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1448817830
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.1682265208
Short name T325
Test name
Test status
Simulation time 10065883327 ps
CPU time 15.46 seconds
Started Jun 06 01:49:22 PM PDT 24
Finished Jun 06 01:49:39 PM PDT 24
Peak memory 205608 kb
Host smart-4e9c29e5-ca7e-4104-bcb6-e2b9c3860d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16822
65208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.1682265208
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.701394457
Short name T1933
Test name
Test status
Simulation time 10081508226 ps
CPU time 16.45 seconds
Started Jun 06 01:49:19 PM PDT 24
Finished Jun 06 01:49:37 PM PDT 24
Peak memory 205628 kb
Host smart-bd97313f-06e9-4184-8e2f-60e1bb59201f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70139
4457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.701394457
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.1368565338
Short name T850
Test name
Test status
Simulation time 10048347549 ps
CPU time 15.01 seconds
Started Jun 06 01:49:29 PM PDT 24
Finished Jun 06 01:49:45 PM PDT 24
Peak memory 205640 kb
Host smart-249aafb9-35a5-44ad-b545-8cf72635b5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13685
65338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1368565338
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2270688984
Short name T1133
Test name
Test status
Simulation time 10087108860 ps
CPU time 13.62 seconds
Started Jun 06 01:49:29 PM PDT 24
Finished Jun 06 01:49:43 PM PDT 24
Peak memory 205744 kb
Host smart-82b5555a-86be-4027-b252-ca8a95ffefee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22706
88984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2270688984
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.2879168770
Short name T1734
Test name
Test status
Simulation time 10153850253 ps
CPU time 15.17 seconds
Started Jun 06 01:49:17 PM PDT 24
Finished Jun 06 01:49:33 PM PDT 24
Peak memory 205732 kb
Host smart-a1f6390d-1936-45c0-a28e-9558cb57a87f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28791
68770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.2879168770
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3817719304
Short name T397
Test name
Test status
Simulation time 10060913236 ps
CPU time 14.3 seconds
Started Jun 06 01:49:27 PM PDT 24
Finished Jun 06 01:49:42 PM PDT 24
Peak memory 205636 kb
Host smart-86ddd943-c0c6-4c37-ab75-21d30a23f7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38177
19304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3817719304
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.3061576489
Short name T1401
Test name
Test status
Simulation time 10105917379 ps
CPU time 12.63 seconds
Started Jun 06 01:49:19 PM PDT 24
Finished Jun 06 01:49:33 PM PDT 24
Peak memory 205660 kb
Host smart-2f1efd70-5e1a-4389-8637-c85d0b9cc355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30615
76489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.3061576489
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.3560699563
Short name T842
Test name
Test status
Simulation time 20803707749 ps
CPU time 302.2 seconds
Started Jun 06 01:49:19 PM PDT 24
Finished Jun 06 01:54:22 PM PDT 24
Peak memory 205648 kb
Host smart-a443430e-f9a8-411c-ab80-a1b144a15616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35606
99563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.3560699563
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.2585680422
Short name T653
Test name
Test status
Simulation time 10140635054 ps
CPU time 13.11 seconds
Started Jun 06 01:49:31 PM PDT 24
Finished Jun 06 01:49:46 PM PDT 24
Peak memory 205720 kb
Host smart-65fae0f9-0558-4e13-bbf2-063dde0fb93c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2585680422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.2585680422
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.2955361858
Short name T1346
Test name
Test status
Simulation time 10057811619 ps
CPU time 13.31 seconds
Started Jun 06 01:49:31 PM PDT 24
Finished Jun 06 01:49:45 PM PDT 24
Peak memory 205624 kb
Host smart-1aea5f4b-2e5a-4bb4-974c-4714719673b7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2955361858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.2955361858
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.2811794318
Short name T268
Test name
Test status
Simulation time 10103153661 ps
CPU time 13.61 seconds
Started Jun 06 01:49:34 PM PDT 24
Finished Jun 06 01:49:48 PM PDT 24
Peak memory 205648 kb
Host smart-518e62bc-f026-4b4c-9ff8-8a94ba6e0a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28117
94318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.2811794318
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.874328256
Short name T1250
Test name
Test status
Simulation time 13998114298 ps
CPU time 16.78 seconds
Started Jun 06 01:49:31 PM PDT 24
Finished Jun 06 01:49:49 PM PDT 24
Peak memory 205704 kb
Host smart-3dd3e0cd-06cc-4de4-9e2e-97a13f2c63d2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=874328256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.874328256
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.1344088601
Short name T1845
Test name
Test status
Simulation time 23369826426 ps
CPU time 25.09 seconds
Started Jun 06 01:49:29 PM PDT 24
Finished Jun 06 01:49:55 PM PDT 24
Peak memory 205712 kb
Host smart-4aaa6a99-8881-4c66-a74e-d70960fbcb86
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1344088601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.1344088601
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2119853471
Short name T1492
Test name
Test status
Simulation time 10054059158 ps
CPU time 14.36 seconds
Started Jun 06 01:49:29 PM PDT 24
Finished Jun 06 01:49:44 PM PDT 24
Peak memory 205684 kb
Host smart-18db0846-8e3d-4a96-bbbb-d9db43e7b36b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21198
53471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2119853471
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.2585311827
Short name T1485
Test name
Test status
Simulation time 10735208063 ps
CPU time 15.27 seconds
Started Jun 06 01:49:30 PM PDT 24
Finished Jun 06 01:49:46 PM PDT 24
Peak memory 205684 kb
Host smart-972f62d6-7738-40a0-8768-2437c1ebfd2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25853
11827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.2585311827
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.3649781769
Short name T1440
Test name
Test status
Simulation time 10049078565 ps
CPU time 14.12 seconds
Started Jun 06 01:49:30 PM PDT 24
Finished Jun 06 01:49:45 PM PDT 24
Peak memory 205628 kb
Host smart-b9ff1352-0244-41ef-8444-067addea5e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36497
81769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.3649781769
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.3568034666
Short name T563
Test name
Test status
Simulation time 10051638630 ps
CPU time 16.07 seconds
Started Jun 06 01:49:33 PM PDT 24
Finished Jun 06 01:49:50 PM PDT 24
Peak memory 205680 kb
Host smart-3cc32df5-d860-41f5-8620-bbad21a5773c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35680
34666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.3568034666
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.202741528
Short name T1816
Test name
Test status
Simulation time 10096646561 ps
CPU time 16.06 seconds
Started Jun 06 01:49:29 PM PDT 24
Finished Jun 06 01:49:46 PM PDT 24
Peak memory 205660 kb
Host smart-aab58fd3-be2c-47ba-b085-24a1c15173b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20274
1528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.202741528
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.1521530794
Short name T1288
Test name
Test status
Simulation time 10066603593 ps
CPU time 13.39 seconds
Started Jun 06 01:49:32 PM PDT 24
Finished Jun 06 01:49:47 PM PDT 24
Peak memory 205716 kb
Host smart-e83e241a-cd1b-4fcb-93cd-7c881ccd4fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15215
30794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.1521530794
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.1650472041
Short name T773
Test name
Test status
Simulation time 10106787387 ps
CPU time 15.78 seconds
Started Jun 06 01:49:33 PM PDT 24
Finished Jun 06 01:49:50 PM PDT 24
Peak memory 205684 kb
Host smart-9b620dca-01eb-4563-8820-aeb7df0ea238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16504
72041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.1650472041
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.198562515
Short name T672
Test name
Test status
Simulation time 10138659630 ps
CPU time 15.43 seconds
Started Jun 06 01:49:29 PM PDT 24
Finished Jun 06 01:49:45 PM PDT 24
Peak memory 205724 kb
Host smart-8a18afef-b423-41a1-a446-db7f638ce2c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19856
2515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.198562515
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.453470094
Short name T1892
Test name
Test status
Simulation time 10141578241 ps
CPU time 14.19 seconds
Started Jun 06 01:49:32 PM PDT 24
Finished Jun 06 01:49:47 PM PDT 24
Peak memory 205684 kb
Host smart-a12e6b2b-d030-4445-8c82-6cde4078244e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45347
0094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.453470094
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.1551783588
Short name T1972
Test name
Test status
Simulation time 13190242061 ps
CPU time 16.3 seconds
Started Jun 06 01:49:31 PM PDT 24
Finished Jun 06 01:49:48 PM PDT 24
Peak memory 205784 kb
Host smart-418e66cb-ea7a-4b7f-9990-64f9f821653b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15517
83588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.1551783588
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.1850758376
Short name T925
Test name
Test status
Simulation time 10092617756 ps
CPU time 14.77 seconds
Started Jun 06 01:49:31 PM PDT 24
Finished Jun 06 01:49:47 PM PDT 24
Peak memory 205720 kb
Host smart-e080999e-0402-4605-be61-731fbb651e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18507
58376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.1850758376
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.3360123036
Short name T810
Test name
Test status
Simulation time 19064045278 ps
CPU time 97.3 seconds
Started Jun 06 01:49:33 PM PDT 24
Finished Jun 06 01:51:12 PM PDT 24
Peak memory 205700 kb
Host smart-394a19be-504e-4c89-a428-792488e39d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33601
23036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.3360123036
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2344448583
Short name T984
Test name
Test status
Simulation time 10075673700 ps
CPU time 13.22 seconds
Started Jun 06 01:49:31 PM PDT 24
Finished Jun 06 01:49:46 PM PDT 24
Peak memory 205628 kb
Host smart-173ffe5e-6cbd-47aa-9f8e-eb8c34b4f9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23444
48583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2344448583
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.985184649
Short name T121
Test name
Test status
Simulation time 10073614304 ps
CPU time 15.02 seconds
Started Jun 06 01:49:33 PM PDT 24
Finished Jun 06 01:49:49 PM PDT 24
Peak memory 205996 kb
Host smart-650fa748-da51-45a5-a741-1532d4230653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98518
4649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.985184649
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.3062597922
Short name T1341
Test name
Test status
Simulation time 10112189809 ps
CPU time 15.92 seconds
Started Jun 06 01:49:41 PM PDT 24
Finished Jun 06 01:49:57 PM PDT 24
Peak memory 205752 kb
Host smart-ca54990f-c393-4622-8624-69b12c0d0896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30625
97922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.3062597922
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.4162384659
Short name T1691
Test name
Test status
Simulation time 10143658782 ps
CPU time 12.73 seconds
Started Jun 06 01:49:31 PM PDT 24
Finished Jun 06 01:49:45 PM PDT 24
Peak memory 205744 kb
Host smart-dbb231c0-39d0-45af-88e7-b1b6110b6b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41623
84659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.4162384659
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.886074324
Short name T1480
Test name
Test status
Simulation time 10085805558 ps
CPU time 13.15 seconds
Started Jun 06 01:50:34 PM PDT 24
Finished Jun 06 01:50:49 PM PDT 24
Peak memory 205636 kb
Host smart-c68dbf15-dac1-46a0-8ce1-4eace0dcb697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88607
4324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.886074324
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.1133203287
Short name T149
Test name
Test status
Simulation time 10053787005 ps
CPU time 13.26 seconds
Started Jun 06 01:49:32 PM PDT 24
Finished Jun 06 01:49:46 PM PDT 24
Peak memory 205640 kb
Host smart-3bc7bf78-4bda-4df9-9d6b-f2205ba8775c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11332
03287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.1133203287
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_eop_single_bit_handling.2829844996
Short name T1639
Test name
Test status
Simulation time 10090601580 ps
CPU time 14.09 seconds
Started Jun 06 01:49:28 PM PDT 24
Finished Jun 06 01:49:43 PM PDT 24
Peak memory 205616 kb
Host smart-72603c3d-11ff-4f2b-bc69-f10c4af987fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28298
44996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_eop_single_bit_handling.2829844996
Directory /workspace/24.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.1030273467
Short name T71
Test name
Test status
Simulation time 10048218826 ps
CPU time 13.7 seconds
Started Jun 06 01:49:29 PM PDT 24
Finished Jun 06 01:49:44 PM PDT 24
Peak memory 205740 kb
Host smart-a65420f1-9ca5-45dd-9c21-17eee7f26ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10302
73467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.1030273467
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2023002462
Short name T1863
Test name
Test status
Simulation time 10035621322 ps
CPU time 13.92 seconds
Started Jun 06 01:49:30 PM PDT 24
Finished Jun 06 01:49:45 PM PDT 24
Peak memory 205652 kb
Host smart-fea28ac3-8844-4598-ba45-8ad097fdc681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20230
02462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2023002462
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2084689537
Short name T232
Test name
Test status
Simulation time 19636932997 ps
CPU time 39.28 seconds
Started Jun 06 01:49:29 PM PDT 24
Finished Jun 06 01:50:09 PM PDT 24
Peak memory 205604 kb
Host smart-1c20aa9b-e6ae-49eb-a775-54aad97d8751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20846
89537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2084689537
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1832503216
Short name T1827
Test name
Test status
Simulation time 10110028904 ps
CPU time 14.48 seconds
Started Jun 06 01:49:31 PM PDT 24
Finished Jun 06 01:49:47 PM PDT 24
Peak memory 205664 kb
Host smart-04e6aa1c-a74e-4a24-9c7b-cd1a7245d89a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18325
03216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1832503216
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.1187439795
Short name T1688
Test name
Test status
Simulation time 10096631363 ps
CPU time 14.34 seconds
Started Jun 06 01:49:30 PM PDT 24
Finished Jun 06 01:49:46 PM PDT 24
Peak memory 205768 kb
Host smart-45ea6e8c-697b-49f4-bc5e-cbe3b679e731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11874
39795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1187439795
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.577315037
Short name T814
Test name
Test status
Simulation time 10070926654 ps
CPU time 13.28 seconds
Started Jun 06 01:49:30 PM PDT 24
Finished Jun 06 01:49:44 PM PDT 24
Peak memory 205768 kb
Host smart-d4dd4eb3-903d-4102-acc4-e357797e2452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57731
5037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.577315037
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.1979767599
Short name T479
Test name
Test status
Simulation time 10045579163 ps
CPU time 14.14 seconds
Started Jun 06 01:49:30 PM PDT 24
Finished Jun 06 01:49:45 PM PDT 24
Peak memory 205696 kb
Host smart-3852f06e-a584-4033-94b3-8c84f116c882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19797
67599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.1979767599
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.3317766883
Short name T1249
Test name
Test status
Simulation time 10073269525 ps
CPU time 13.37 seconds
Started Jun 06 01:49:30 PM PDT 24
Finished Jun 06 01:49:44 PM PDT 24
Peak memory 205716 kb
Host smart-4c3e7b84-24e3-449d-b854-96f26b2d451e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33177
66883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.3317766883
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2980899200
Short name T519
Test name
Test status
Simulation time 10119852433 ps
CPU time 15.88 seconds
Started Jun 06 01:49:28 PM PDT 24
Finished Jun 06 01:49:45 PM PDT 24
Peak memory 205644 kb
Host smart-675197fa-5eb5-4db2-9bcb-088271603a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29808
99200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2980899200
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.1674879094
Short name T1573
Test name
Test status
Simulation time 10133211188 ps
CPU time 14.25 seconds
Started Jun 06 01:49:30 PM PDT 24
Finished Jun 06 01:49:46 PM PDT 24
Peak memory 205740 kb
Host smart-cb4bcc64-214c-4c1e-aa70-2b5ae8f35ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16748
79094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1674879094
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.2302598735
Short name T312
Test name
Test status
Simulation time 10096029997 ps
CPU time 13.9 seconds
Started Jun 06 01:49:30 PM PDT 24
Finished Jun 06 01:49:45 PM PDT 24
Peak memory 205724 kb
Host smart-83ee9c32-4ee0-45e7-997e-3e8fad14e52f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23025
98735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.2302598735
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.523501678
Short name T29
Test name
Test status
Simulation time 10077768342 ps
CPU time 13.93 seconds
Started Jun 06 01:49:31 PM PDT 24
Finished Jun 06 01:49:46 PM PDT 24
Peak memory 205584 kb
Host smart-abd6c80e-492a-49c7-b3c1-d3027e5ffd1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52350
1678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.523501678
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.231793207
Short name T1304
Test name
Test status
Simulation time 17030106891 ps
CPU time 214.11 seconds
Started Jun 06 01:49:31 PM PDT 24
Finished Jun 06 01:53:07 PM PDT 24
Peak memory 205616 kb
Host smart-f34a11e9-dcdc-4eb6-86a4-6bf53b8c0d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23179
3207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.231793207
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.929166009
Short name T1156
Test name
Test status
Simulation time 10170614388 ps
CPU time 16.15 seconds
Started Jun 06 01:49:47 PM PDT 24
Finished Jun 06 01:50:05 PM PDT 24
Peak memory 205656 kb
Host smart-e85ae681-8970-45b7-aabe-1048a9335630
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=929166009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.929166009
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.2167956142
Short name T1179
Test name
Test status
Simulation time 10055820955 ps
CPU time 14.41 seconds
Started Jun 06 01:49:40 PM PDT 24
Finished Jun 06 01:49:55 PM PDT 24
Peak memory 205684 kb
Host smart-badf9e2c-e1c9-40ac-9384-682ccd83a052
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2167956142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.2167956142
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.3864704670
Short name T38
Test name
Test status
Simulation time 10094247363 ps
CPU time 13.4 seconds
Started Jun 06 01:49:41 PM PDT 24
Finished Jun 06 01:49:55 PM PDT 24
Peak memory 205756 kb
Host smart-964f7fd8-2c65-4947-a9e0-9df9eb96296c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38647
04670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.3864704670
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.3831944093
Short name T618
Test name
Test status
Simulation time 13714027876 ps
CPU time 17.33 seconds
Started Jun 06 01:49:33 PM PDT 24
Finished Jun 06 01:49:52 PM PDT 24
Peak memory 205624 kb
Host smart-4730e8c7-22ab-4ec9-abe9-faf1e36edb9d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3831944093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.3831944093
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.1972385946
Short name T1901
Test name
Test status
Simulation time 23268141702 ps
CPU time 27.75 seconds
Started Jun 06 01:49:33 PM PDT 24
Finished Jun 06 01:50:01 PM PDT 24
Peak memory 205696 kb
Host smart-5a3fea13-e3c9-485c-9f6d-d0f20ebf652b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1972385946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.1972385946
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.2216078606
Short name T646
Test name
Test status
Simulation time 10104086754 ps
CPU time 13.05 seconds
Started Jun 06 01:49:33 PM PDT 24
Finished Jun 06 01:49:47 PM PDT 24
Peak memory 205644 kb
Host smart-17b2af38-15fa-4503-83f2-a245a2198167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22160
78606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2216078606
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.477435407
Short name T1507
Test name
Test status
Simulation time 10753534903 ps
CPU time 14.65 seconds
Started Jun 06 01:49:36 PM PDT 24
Finished Jun 06 01:49:52 PM PDT 24
Peak memory 205704 kb
Host smart-330a5dda-2b22-4064-a048-bbf18c0e4586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47743
5407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.477435407
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.2957315870
Short name T1095
Test name
Test status
Simulation time 10050680200 ps
CPU time 14.58 seconds
Started Jun 06 01:49:38 PM PDT 24
Finished Jun 06 01:49:54 PM PDT 24
Peak memory 205600 kb
Host smart-eb5e1aeb-5277-48a6-8033-65d5059891c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29573
15870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.2957315870
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.155736079
Short name T1754
Test name
Test status
Simulation time 10066542185 ps
CPU time 15.13 seconds
Started Jun 06 01:49:32 PM PDT 24
Finished Jun 06 01:49:48 PM PDT 24
Peak memory 205888 kb
Host smart-a8e65235-a40a-40dd-b04a-0bfcb89d42ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15573
6079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.155736079
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1375348355
Short name T2010
Test name
Test status
Simulation time 10771764276 ps
CPU time 16.56 seconds
Started Jun 06 01:49:31 PM PDT 24
Finished Jun 06 01:49:49 PM PDT 24
Peak memory 205772 kb
Host smart-bfdb2459-3332-4655-a75f-30f325916098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13753
48355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1375348355
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.3767200280
Short name T1333
Test name
Test status
Simulation time 10088501688 ps
CPU time 14.38 seconds
Started Jun 06 01:49:32 PM PDT 24
Finished Jun 06 01:49:47 PM PDT 24
Peak memory 205608 kb
Host smart-5bc7116c-1e8e-48a4-8b80-e07a55d7b890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37672
00280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.3767200280
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.2367640431
Short name T547
Test name
Test status
Simulation time 10055153590 ps
CPU time 15.14 seconds
Started Jun 06 01:49:38 PM PDT 24
Finished Jun 06 01:49:54 PM PDT 24
Peak memory 205648 kb
Host smart-4224fc82-860e-41af-a0fc-bcd275e0ff5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23676
40431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.2367640431
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1810912408
Short name T1577
Test name
Test status
Simulation time 10050931328 ps
CPU time 14.14 seconds
Started Jun 06 01:49:40 PM PDT 24
Finished Jun 06 01:49:55 PM PDT 24
Peak memory 205588 kb
Host smart-4667850e-4fea-4892-b6a4-448ce7fd6977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18109
12408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1810912408
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.2697705260
Short name T766
Test name
Test status
Simulation time 10131126052 ps
CPU time 14.23 seconds
Started Jun 06 01:49:37 PM PDT 24
Finished Jun 06 01:49:52 PM PDT 24
Peak memory 205708 kb
Host smart-8d591f4c-b1bc-4f70-b648-f2f5da37f0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26977
05260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.2697705260
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.3213446775
Short name T628
Test name
Test status
Simulation time 10105111661 ps
CPU time 14.25 seconds
Started Jun 06 01:49:33 PM PDT 24
Finished Jun 06 01:49:48 PM PDT 24
Peak memory 205968 kb
Host smart-9fba454d-5bbb-4522-b0c1-b65399cfafd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32134
46775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.3213446775
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.279985226
Short name T1769
Test name
Test status
Simulation time 13165973350 ps
CPU time 17.37 seconds
Started Jun 06 01:49:37 PM PDT 24
Finished Jun 06 01:49:55 PM PDT 24
Peak memory 205720 kb
Host smart-94ff7a87-4d85-477c-b992-a269d2ce790b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27998
5226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.279985226
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1804275447
Short name T476
Test name
Test status
Simulation time 10095145597 ps
CPU time 16.21 seconds
Started Jun 06 01:49:38 PM PDT 24
Finished Jun 06 01:49:55 PM PDT 24
Peak memory 205808 kb
Host smart-9ef1fbf3-4a83-4118-b5e3-a1452735bc06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18042
75447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1804275447
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.2925304746
Short name T135
Test name
Test status
Simulation time 15008563122 ps
CPU time 152.17 seconds
Started Jun 06 01:49:37 PM PDT 24
Finished Jun 06 01:52:10 PM PDT 24
Peak memory 205668 kb
Host smart-03bc3c98-03dc-40f0-b1eb-ed22ece96db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29253
04746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.2925304746
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2901351271
Short name T330
Test name
Test status
Simulation time 10046233314 ps
CPU time 13.5 seconds
Started Jun 06 01:49:40 PM PDT 24
Finished Jun 06 01:49:54 PM PDT 24
Peak memory 205748 kb
Host smart-68050f29-2cfe-4a82-8980-361c640c0d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29013
51271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2901351271
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.3044533936
Short name T114
Test name
Test status
Simulation time 10074700903 ps
CPU time 13.4 seconds
Started Jun 06 01:49:36 PM PDT 24
Finished Jun 06 01:49:51 PM PDT 24
Peak memory 205716 kb
Host smart-27a5be28-7cdf-4354-828f-f7098c0a3b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30445
33936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.3044533936
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.2679059829
Short name T1670
Test name
Test status
Simulation time 10085055540 ps
CPU time 15.52 seconds
Started Jun 06 01:49:39 PM PDT 24
Finished Jun 06 01:49:55 PM PDT 24
Peak memory 205624 kb
Host smart-116da7d0-62c2-43f4-8c75-477ce0cac71a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26790
59829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.2679059829
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3091304413
Short name T1439
Test name
Test status
Simulation time 10044941225 ps
CPU time 13.82 seconds
Started Jun 06 01:49:40 PM PDT 24
Finished Jun 06 01:49:55 PM PDT 24
Peak memory 205668 kb
Host smart-7eb15ac2-351b-42a1-9b09-0cd1befa778a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30913
04413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3091304413
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.366572163
Short name T1687
Test name
Test status
Simulation time 10093083835 ps
CPU time 13.7 seconds
Started Jun 06 01:49:47 PM PDT 24
Finished Jun 06 01:50:01 PM PDT 24
Peak memory 205664 kb
Host smart-a2247656-1b96-496f-bdc1-a0e3f6b67d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36657
2163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.366572163
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.402921763
Short name T1276
Test name
Test status
Simulation time 10097446784 ps
CPU time 13.27 seconds
Started Jun 06 01:49:38 PM PDT 24
Finished Jun 06 01:49:52 PM PDT 24
Peak memory 205632 kb
Host smart-fbc30b74-990c-44f0-934d-7bd7059c5837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40292
1763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.402921763
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_eop_single_bit_handling.1450147874
Short name T1407
Test name
Test status
Simulation time 10080491569 ps
CPU time 13.3 seconds
Started Jun 06 01:49:35 PM PDT 24
Finished Jun 06 01:49:49 PM PDT 24
Peak memory 205636 kb
Host smart-7960dc9b-a3ef-4036-8683-f2daecd1ec1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14501
47874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_eop_single_bit_handling.1450147874
Directory /workspace/25.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.2648425788
Short name T637
Test name
Test status
Simulation time 10049361455 ps
CPU time 14.29 seconds
Started Jun 06 01:49:43 PM PDT 24
Finished Jun 06 01:49:58 PM PDT 24
Peak memory 205620 kb
Host smart-0e46cb78-634f-47a7-889b-1e77fbbcd493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26484
25788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.2648425788
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.3111761671
Short name T998
Test name
Test status
Simulation time 10059893037 ps
CPU time 14.49 seconds
Started Jun 06 01:49:42 PM PDT 24
Finished Jun 06 01:49:57 PM PDT 24
Peak memory 205712 kb
Host smart-562df22e-570b-4365-89b1-0a19348b1544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31117
61671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.3111761671
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.4043948818
Short name T967
Test name
Test status
Simulation time 10071510341 ps
CPU time 14.09 seconds
Started Jun 06 01:49:47 PM PDT 24
Finished Jun 06 01:50:03 PM PDT 24
Peak memory 205688 kb
Host smart-f998a2a5-301d-436a-8fd1-e04b1f8f44b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40439
48818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.4043948818
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1124961325
Short name T611
Test name
Test status
Simulation time 10062637486 ps
CPU time 13.97 seconds
Started Jun 06 01:49:37 PM PDT 24
Finished Jun 06 01:49:52 PM PDT 24
Peak memory 205680 kb
Host smart-c26e67e8-e139-4c4e-b2ec-9aceaf3ebfe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11249
61325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1124961325
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.2925549884
Short name T1289
Test name
Test status
Simulation time 10080819856 ps
CPU time 14.88 seconds
Started Jun 06 01:49:44 PM PDT 24
Finished Jun 06 01:49:59 PM PDT 24
Peak memory 205764 kb
Host smart-0b4156f9-3577-4476-843a-e8555fb46a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29255
49884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.2925549884
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.3594773258
Short name T1240
Test name
Test status
Simulation time 10046716784 ps
CPU time 13.17 seconds
Started Jun 06 01:49:38 PM PDT 24
Finished Jun 06 01:49:52 PM PDT 24
Peak memory 205992 kb
Host smart-d91368ef-1398-4e9d-9dfb-a043985c6132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35947
73258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.3594773258
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.3554671504
Short name T953
Test name
Test status
Simulation time 10064755579 ps
CPU time 16.09 seconds
Started Jun 06 01:49:38 PM PDT 24
Finished Jun 06 01:49:55 PM PDT 24
Peak memory 205748 kb
Host smart-64b8a0e1-d090-4848-9fce-0a0e5d8e68bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35546
71504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.3554671504
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.671430443
Short name T570
Test name
Test status
Simulation time 10103698036 ps
CPU time 13.95 seconds
Started Jun 06 01:49:38 PM PDT 24
Finished Jun 06 01:49:53 PM PDT 24
Peak memory 205684 kb
Host smart-08fc07b1-3e8f-4e09-9947-4aa8123c4622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67143
0443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.671430443
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.3384555880
Short name T1177
Test name
Test status
Simulation time 10078827629 ps
CPU time 14.02 seconds
Started Jun 06 01:49:30 PM PDT 24
Finished Jun 06 01:49:45 PM PDT 24
Peak memory 205644 kb
Host smart-84cf6092-8dc8-4c9b-8234-7cebf361f263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33845
55880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.3384555880
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3643651513
Short name T1990
Test name
Test status
Simulation time 10076072517 ps
CPU time 13.86 seconds
Started Jun 06 01:49:37 PM PDT 24
Finished Jun 06 01:49:52 PM PDT 24
Peak memory 205656 kb
Host smart-622198af-d056-44bf-8273-26299c393b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36436
51513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3643651513
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.186690176
Short name T797
Test name
Test status
Simulation time 10083565523 ps
CPU time 15.45 seconds
Started Jun 06 01:49:45 PM PDT 24
Finished Jun 06 01:50:01 PM PDT 24
Peak memory 205720 kb
Host smart-422117f7-48a8-457b-a10f-dc4ee013d1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18669
0176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.186690176
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.3706854840
Short name T1117
Test name
Test status
Simulation time 24749536425 ps
CPU time 153.08 seconds
Started Jun 06 01:49:40 PM PDT 24
Finished Jun 06 01:52:13 PM PDT 24
Peak memory 205720 kb
Host smart-ca935958-d658-49cf-89bc-65b1ee139c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37068
54840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.3706854840
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.688929615
Short name T1677
Test name
Test status
Simulation time 10152346412 ps
CPU time 13.15 seconds
Started Jun 06 01:49:58 PM PDT 24
Finished Jun 06 01:50:12 PM PDT 24
Peak memory 205776 kb
Host smart-3347ac71-7a5e-45eb-bb41-8b19535d5522
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=688929615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.688929615
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.2142315068
Short name T1966
Test name
Test status
Simulation time 10047921408 ps
CPU time 13.19 seconds
Started Jun 06 01:49:53 PM PDT 24
Finished Jun 06 01:50:07 PM PDT 24
Peak memory 205632 kb
Host smart-261d0a47-f75f-453e-8e2f-813f58f9e865
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2142315068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.2142315068
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.2067507354
Short name T1105
Test name
Test status
Simulation time 10129851368 ps
CPU time 13.82 seconds
Started Jun 06 01:49:55 PM PDT 24
Finished Jun 06 01:50:10 PM PDT 24
Peak memory 205744 kb
Host smart-892d2b11-3710-45d9-b0ae-3ec14aa1e7b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20675
07354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.2067507354
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.411717787
Short name T1916
Test name
Test status
Simulation time 14093165256 ps
CPU time 17.04 seconds
Started Jun 06 01:49:39 PM PDT 24
Finished Jun 06 01:49:57 PM PDT 24
Peak memory 205612 kb
Host smart-ba98c435-026f-4042-8023-afe63c1fa319
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=411717787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.411717787
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.4278219192
Short name T50
Test name
Test status
Simulation time 23271483653 ps
CPU time 26.91 seconds
Started Jun 06 01:49:42 PM PDT 24
Finished Jun 06 01:50:09 PM PDT 24
Peak memory 205720 kb
Host smart-b491fc70-23e2-402d-b7d3-7892667b966b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4278219192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.4278219192
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.2531208898
Short name T1886
Test name
Test status
Simulation time 10103243748 ps
CPU time 15.45 seconds
Started Jun 06 01:49:40 PM PDT 24
Finished Jun 06 01:49:56 PM PDT 24
Peak memory 205764 kb
Host smart-cc2d540d-286d-4201-8b68-cb6996c577f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25312
08898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.2531208898
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.3313732064
Short name T1747
Test name
Test status
Simulation time 11191034686 ps
CPU time 15.82 seconds
Started Jun 06 01:49:38 PM PDT 24
Finished Jun 06 01:49:55 PM PDT 24
Peak memory 205680 kb
Host smart-44cbdc52-48d4-4e0a-aa88-a6cf2ec3dc34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33137
32064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.3313732064
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.2644243080
Short name T681
Test name
Test status
Simulation time 10052294051 ps
CPU time 12.69 seconds
Started Jun 06 01:49:47 PM PDT 24
Finished Jun 06 01:50:01 PM PDT 24
Peak memory 205732 kb
Host smart-90660451-957f-42d0-8dde-2a443726f026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26442
43080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2644243080
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.1039102940
Short name T24
Test name
Test status
Simulation time 10069256640 ps
CPU time 13.13 seconds
Started Jun 06 01:49:37 PM PDT 24
Finished Jun 06 01:49:50 PM PDT 24
Peak memory 205676 kb
Host smart-1784a979-477d-4fcf-9e27-c0568b8d9ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10391
02940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.1039102940
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.11123875
Short name T1146
Test name
Test status
Simulation time 10845822173 ps
CPU time 14.75 seconds
Started Jun 06 01:49:39 PM PDT 24
Finished Jun 06 01:49:55 PM PDT 24
Peak memory 205704 kb
Host smart-fed46c9c-d4b6-4f15-a61c-118a66ae1d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11123
875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.11123875
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.2961241954
Short name T1712
Test name
Test status
Simulation time 10096190410 ps
CPU time 15.59 seconds
Started Jun 06 01:49:42 PM PDT 24
Finished Jun 06 01:49:59 PM PDT 24
Peak memory 205664 kb
Host smart-34c91cd8-1485-42c9-840a-7d9735d15abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29612
41954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.2961241954
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.2175490601
Short name T1969
Test name
Test status
Simulation time 10136047155 ps
CPU time 14.15 seconds
Started Jun 06 01:49:45 PM PDT 24
Finished Jun 06 01:50:01 PM PDT 24
Peak memory 205748 kb
Host smart-c6e6d125-4b01-4f48-a364-416902db42bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21754
90601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.2175490601
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.207558538
Short name T977
Test name
Test status
Simulation time 10049807741 ps
CPU time 15.9 seconds
Started Jun 06 01:49:47 PM PDT 24
Finished Jun 06 01:50:04 PM PDT 24
Peak memory 205752 kb
Host smart-aa99a823-65d3-4b6f-9567-06cb69ec7a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20755
8538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.207558538
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.1656296950
Short name T1514
Test name
Test status
Simulation time 10072881098 ps
CPU time 13.81 seconds
Started Jun 06 01:49:40 PM PDT 24
Finished Jun 06 01:49:55 PM PDT 24
Peak memory 205644 kb
Host smart-a6de2045-ad4f-4a8f-b0c4-55bc2b693bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16562
96950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.1656296950
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.125981781
Short name T923
Test name
Test status
Simulation time 10080368527 ps
CPU time 14.57 seconds
Started Jun 06 01:49:36 PM PDT 24
Finished Jun 06 01:49:52 PM PDT 24
Peak memory 205632 kb
Host smart-15c0171d-f4f7-4690-b802-64e6e37acc85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12598
1781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.125981781
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.1840605850
Short name T1339
Test name
Test status
Simulation time 13155943366 ps
CPU time 15.59 seconds
Started Jun 06 01:49:47 PM PDT 24
Finished Jun 06 01:50:04 PM PDT 24
Peak memory 205728 kb
Host smart-f7939959-6d7b-4197-b90b-ca1c7abf68cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18406
05850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.1840605850
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3741614120
Short name T1009
Test name
Test status
Simulation time 10094159790 ps
CPU time 12.76 seconds
Started Jun 06 01:49:47 PM PDT 24
Finished Jun 06 01:50:01 PM PDT 24
Peak memory 205820 kb
Host smart-a6fe1e6e-42b1-4206-b2ab-e36b83cbe9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37416
14120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3741614120
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.3666257956
Short name T1028
Test name
Test status
Simulation time 16826222692 ps
CPU time 209.29 seconds
Started Jun 06 01:49:46 PM PDT 24
Finished Jun 06 01:53:16 PM PDT 24
Peak memory 205648 kb
Host smart-4efc2945-8969-469d-9f40-fbe3cd4c103f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36662
57956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.3666257956
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2019375852
Short name T589
Test name
Test status
Simulation time 10105995183 ps
CPU time 14.54 seconds
Started Jun 06 01:49:47 PM PDT 24
Finished Jun 06 01:50:03 PM PDT 24
Peak memory 205720 kb
Host smart-b4f07f82-3f35-4bdc-856f-f80d8c9bbe26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20193
75852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2019375852
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.4121088371
Short name T552
Test name
Test status
Simulation time 10058421089 ps
CPU time 13.7 seconds
Started Jun 06 01:49:44 PM PDT 24
Finished Jun 06 01:49:58 PM PDT 24
Peak memory 205748 kb
Host smart-3e9e3e9c-251d-4257-ba93-c30ba87c88d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41210
88371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.4121088371
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.4142804655
Short name T654
Test name
Test status
Simulation time 10094248323 ps
CPU time 14.28 seconds
Started Jun 06 01:49:45 PM PDT 24
Finished Jun 06 01:50:01 PM PDT 24
Peak memory 205640 kb
Host smart-cc1d14e9-0d47-42b2-9c93-61b590adf322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41428
04655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.4142804655
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1111953982
Short name T1498
Test name
Test status
Simulation time 10058019388 ps
CPU time 14 seconds
Started Jun 06 01:49:49 PM PDT 24
Finished Jun 06 01:50:04 PM PDT 24
Peak memory 205636 kb
Host smart-5741bc85-ef69-4ff6-b1b7-890f98ed2568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11119
53982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1111953982
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.3233245741
Short name T1285
Test name
Test status
Simulation time 10061685684 ps
CPU time 13.5 seconds
Started Jun 06 01:49:47 PM PDT 24
Finished Jun 06 01:50:02 PM PDT 24
Peak memory 205772 kb
Host smart-e76d93cc-3ce1-44ff-ac83-02213dcea6a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32332
45741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.3233245741
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_eop_single_bit_handling.2837485956
Short name T1578
Test name
Test status
Simulation time 10056183371 ps
CPU time 14.66 seconds
Started Jun 06 01:49:44 PM PDT 24
Finished Jun 06 01:50:00 PM PDT 24
Peak memory 205728 kb
Host smart-9c1f29d2-32b2-492d-b363-87bb49acf9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28374
85956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_eop_single_bit_handling.2837485956
Directory /workspace/26.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2881104903
Short name T1360
Test name
Test status
Simulation time 10045353794 ps
CPU time 13.39 seconds
Started Jun 06 01:49:49 PM PDT 24
Finished Jun 06 01:50:03 PM PDT 24
Peak memory 205620 kb
Host smart-2d9b648a-344f-4b02-8180-d7e09a276f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28811
04903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2881104903
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1085466738
Short name T42
Test name
Test status
Simulation time 10046865308 ps
CPU time 12.76 seconds
Started Jun 06 01:49:45 PM PDT 24
Finished Jun 06 01:49:59 PM PDT 24
Peak memory 205588 kb
Host smart-9bfba282-3b19-4145-8c89-84eb7189a662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10854
66738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1085466738
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.289340983
Short name T1423
Test name
Test status
Simulation time 21586651536 ps
CPU time 38.65 seconds
Started Jun 06 01:49:45 PM PDT 24
Finished Jun 06 01:50:25 PM PDT 24
Peak memory 205644 kb
Host smart-8ca4c30f-b2e8-4501-ad0b-15dbb1b1b64b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28934
0983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.289340983
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.2409905545
Short name T1500
Test name
Test status
Simulation time 10100719473 ps
CPU time 12.41 seconds
Started Jun 06 01:49:50 PM PDT 24
Finished Jun 06 01:50:03 PM PDT 24
Peak memory 205724 kb
Host smart-5176b22f-7307-412b-b382-aeef4191ccf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24099
05545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.2409905545
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.302294268
Short name T595
Test name
Test status
Simulation time 10087181337 ps
CPU time 14.53 seconds
Started Jun 06 01:49:49 PM PDT 24
Finished Jun 06 01:50:04 PM PDT 24
Peak memory 205784 kb
Host smart-27b9bf61-76da-4cb4-a58c-270768240c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30229
4268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.302294268
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.100360420
Short name T242
Test name
Test status
Simulation time 10075228261 ps
CPU time 13.88 seconds
Started Jun 06 01:50:02 PM PDT 24
Finished Jun 06 01:50:17 PM PDT 24
Peak memory 205624 kb
Host smart-b8283ebf-b99c-4932-9743-9a2d7574b150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10036
0420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.100360420
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.3156211339
Short name T996
Test name
Test status
Simulation time 10058501509 ps
CPU time 14.46 seconds
Started Jun 06 01:49:49 PM PDT 24
Finished Jun 06 01:50:04 PM PDT 24
Peak memory 205724 kb
Host smart-6de59bd6-e12f-414b-9adf-782b5e7dba32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31562
11339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.3156211339
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3876378425
Short name T162
Test name
Test status
Simulation time 10090256800 ps
CPU time 14.98 seconds
Started Jun 06 01:49:45 PM PDT 24
Finished Jun 06 01:50:02 PM PDT 24
Peak memory 205636 kb
Host smart-1dbf21da-e1e6-44c6-975c-002d00df61ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38763
78425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3876378425
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.1111433721
Short name T541
Test name
Test status
Simulation time 10068148513 ps
CPU time 15.89 seconds
Started Jun 06 01:49:46 PM PDT 24
Finished Jun 06 01:50:03 PM PDT 24
Peak memory 205688 kb
Host smart-592873b6-3b03-4eb5-b667-ad50bb29c578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11114
33721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.1111433721
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.161055525
Short name T994
Test name
Test status
Simulation time 10112822035 ps
CPU time 15.17 seconds
Started Jun 06 01:49:38 PM PDT 24
Finished Jun 06 01:49:53 PM PDT 24
Peak memory 205684 kb
Host smart-88d87bcd-af69-47de-b710-bdbab9e0610c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16105
5525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.161055525
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.2373107561
Short name T750
Test name
Test status
Simulation time 10126416294 ps
CPU time 14.08 seconds
Started Jun 06 01:49:48 PM PDT 24
Finished Jun 06 01:50:03 PM PDT 24
Peak memory 205668 kb
Host smart-983426a0-f1a7-45c1-bac7-ea4e859d47c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23731
07561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.2373107561
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.299984349
Short name T1606
Test name
Test status
Simulation time 10063734372 ps
CPU time 13.41 seconds
Started Jun 06 01:49:46 PM PDT 24
Finished Jun 06 01:50:00 PM PDT 24
Peak memory 205680 kb
Host smart-01dbf97b-4093-4edd-bf7b-09353de28482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29998
4349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.299984349
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.2112720003
Short name T1790
Test name
Test status
Simulation time 10176646309 ps
CPU time 14.27 seconds
Started Jun 06 01:50:03 PM PDT 24
Finished Jun 06 01:50:18 PM PDT 24
Peak memory 205708 kb
Host smart-6fe7ada0-8ed5-423f-b7c0-a9c44b20966e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2112720003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.2112720003
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.3269651647
Short name T1601
Test name
Test status
Simulation time 10086567535 ps
CPU time 13.41 seconds
Started Jun 06 01:50:03 PM PDT 24
Finished Jun 06 01:50:17 PM PDT 24
Peak memory 205712 kb
Host smart-cfe70f12-0d02-4687-ba90-abe47341b2a8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3269651647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.3269651647
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.1791765541
Short name T1547
Test name
Test status
Simulation time 10089452758 ps
CPU time 13.13 seconds
Started Jun 06 01:50:12 PM PDT 24
Finished Jun 06 01:50:26 PM PDT 24
Peak memory 205644 kb
Host smart-6ef3aae2-e292-4776-8337-8963e2fc1551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17917
65541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.1791765541
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.1235741264
Short name T1814
Test name
Test status
Simulation time 13527654887 ps
CPU time 17.68 seconds
Started Jun 06 01:49:57 PM PDT 24
Finished Jun 06 01:50:15 PM PDT 24
Peak memory 205764 kb
Host smart-5f04c8df-4482-4b93-96dc-22eaf3e36953
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1235741264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.1235741264
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.2625830571
Short name T1017
Test name
Test status
Simulation time 23253431690 ps
CPU time 24.94 seconds
Started Jun 06 01:49:55 PM PDT 24
Finished Jun 06 01:50:21 PM PDT 24
Peak memory 205628 kb
Host smart-13d55078-0a46-4b03-8d64-f06f71747138
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2625830571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.2625830571
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.1076915675
Short name T1663
Test name
Test status
Simulation time 10073617678 ps
CPU time 13.81 seconds
Started Jun 06 01:49:56 PM PDT 24
Finished Jun 06 01:50:10 PM PDT 24
Peak memory 205588 kb
Host smart-b36fea5e-ba87-4bed-af79-4e4484418cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10769
15675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.1076915675
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.2314032395
Short name T922
Test name
Test status
Simulation time 10077865565 ps
CPU time 13.51 seconds
Started Jun 06 01:49:57 PM PDT 24
Finished Jun 06 01:50:11 PM PDT 24
Peak memory 205724 kb
Host smart-95c53b91-3b21-470e-80b4-b0112218ca70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23140
32395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.2314032395
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.3606419038
Short name T1221
Test name
Test status
Simulation time 11225690571 ps
CPU time 16.44 seconds
Started Jun 06 01:49:58 PM PDT 24
Finished Jun 06 01:50:15 PM PDT 24
Peak memory 205628 kb
Host smart-f09fd3b9-4a80-438d-a63d-17f9c6e93b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36064
19038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.3606419038
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.1166147500
Short name T1905
Test name
Test status
Simulation time 10098870193 ps
CPU time 13.66 seconds
Started Jun 06 01:49:59 PM PDT 24
Finished Jun 06 01:50:14 PM PDT 24
Peak memory 205660 kb
Host smart-f9cb4e2e-cd23-47f4-b0e6-d52a4a3bfc7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11661
47500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.1166147500
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.326637247
Short name T1999
Test name
Test status
Simulation time 10060194572 ps
CPU time 14.1 seconds
Started Jun 06 01:49:55 PM PDT 24
Finished Jun 06 01:50:10 PM PDT 24
Peak memory 205660 kb
Host smart-9ecb2711-89b8-472e-bcd0-b346ca81c2fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32663
7247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.326637247
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.1687779622
Short name T561
Test name
Test status
Simulation time 10667178007 ps
CPU time 14.49 seconds
Started Jun 06 01:49:55 PM PDT 24
Finished Jun 06 01:50:11 PM PDT 24
Peak memory 205760 kb
Host smart-70a43659-fe14-4833-93fc-7dcac36d488c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16877
79622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.1687779622
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2057101208
Short name T1907
Test name
Test status
Simulation time 10095518176 ps
CPU time 16.95 seconds
Started Jun 06 01:49:54 PM PDT 24
Finished Jun 06 01:50:12 PM PDT 24
Peak memory 205588 kb
Host smart-c94861bf-f15d-4b3b-b4aa-d14d6825cffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20571
01208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2057101208
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.1695035657
Short name T1802
Test name
Test status
Simulation time 10104951315 ps
CPU time 14.2 seconds
Started Jun 06 01:50:03 PM PDT 24
Finished Jun 06 01:50:18 PM PDT 24
Peak memory 205668 kb
Host smart-ce4b17e7-9bb8-4b53-8235-7ea40da1d493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16950
35657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.1695035657
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.3020322325
Short name T899
Test name
Test status
Simulation time 10065690560 ps
CPU time 13.73 seconds
Started Jun 06 01:49:57 PM PDT 24
Finished Jun 06 01:50:12 PM PDT 24
Peak memory 205692 kb
Host smart-ec91ae5b-a74e-4491-8f3c-fb3c55725924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30203
22325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.3020322325
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.3814659597
Short name T1444
Test name
Test status
Simulation time 10108060092 ps
CPU time 14.93 seconds
Started Jun 06 01:49:57 PM PDT 24
Finished Jun 06 01:50:12 PM PDT 24
Peak memory 205600 kb
Host smart-fcf8ab75-480b-41f8-a4a9-6e4b6a30af18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38146
59597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3814659597
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.3340208547
Short name T436
Test name
Test status
Simulation time 10146542167 ps
CPU time 13.51 seconds
Started Jun 06 01:49:59 PM PDT 24
Finished Jun 06 01:50:13 PM PDT 24
Peak memory 205748 kb
Host smart-8cedbb33-cffb-44b5-b8d7-2631328a95b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33402
08547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.3340208547
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.2970657160
Short name T1796
Test name
Test status
Simulation time 13232517213 ps
CPU time 21.09 seconds
Started Jun 06 01:49:58 PM PDT 24
Finished Jun 06 01:50:20 PM PDT 24
Peak memory 205716 kb
Host smart-b0452626-0067-49db-9e09-683f630e461d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29706
57160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.2970657160
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2892266677
Short name T1934
Test name
Test status
Simulation time 10103052738 ps
CPU time 17.45 seconds
Started Jun 06 01:49:59 PM PDT 24
Finished Jun 06 01:50:18 PM PDT 24
Peak memory 205756 kb
Host smart-80c0b22b-f217-4042-b468-873ca8bd5128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28922
66677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2892266677
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.1623454219
Short name T1544
Test name
Test status
Simulation time 23328844375 ps
CPU time 361.86 seconds
Started Jun 06 01:49:58 PM PDT 24
Finished Jun 06 01:56:01 PM PDT 24
Peak memory 205664 kb
Host smart-6c9673b1-2046-41fd-b744-504f5b7a2918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16234
54219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.1623454219
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2705372612
Short name T1400
Test name
Test status
Simulation time 10047270850 ps
CPU time 13.69 seconds
Started Jun 06 01:49:56 PM PDT 24
Finished Jun 06 01:50:10 PM PDT 24
Peak memory 205724 kb
Host smart-9cfe14ac-8feb-4fbf-be03-a88f3206ec2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27053
72612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2705372612
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.3526949965
Short name T1771
Test name
Test status
Simulation time 10108676373 ps
CPU time 14.09 seconds
Started Jun 06 01:49:57 PM PDT 24
Finished Jun 06 01:50:12 PM PDT 24
Peak memory 205704 kb
Host smart-77d20076-6e93-4fed-9393-6dcda115de96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35269
49965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.3526949965
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.87337435
Short name T1233
Test name
Test status
Simulation time 10082339061 ps
CPU time 13.4 seconds
Started Jun 06 01:49:58 PM PDT 24
Finished Jun 06 01:50:12 PM PDT 24
Peak memory 205684 kb
Host smart-23c325bc-b68e-45d3-b324-698879073057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87337
435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.87337435
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1242537447
Short name T544
Test name
Test status
Simulation time 10111331398 ps
CPU time 13.84 seconds
Started Jun 06 01:50:00 PM PDT 24
Finished Jun 06 01:50:14 PM PDT 24
Peak memory 205664 kb
Host smart-bec7491f-5ced-412a-90e2-e6db77b84094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12425
37447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1242537447
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2054644576
Short name T1962
Test name
Test status
Simulation time 10082996246 ps
CPU time 16.4 seconds
Started Jun 06 01:49:58 PM PDT 24
Finished Jun 06 01:50:15 PM PDT 24
Peak memory 205696 kb
Host smart-f7c6acae-1a81-47aa-9773-3a20d0993df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20546
44576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2054644576
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.3695860445
Short name T161
Test name
Test status
Simulation time 10056561845 ps
CPU time 13.1 seconds
Started Jun 06 01:49:55 PM PDT 24
Finished Jun 06 01:50:09 PM PDT 24
Peak memory 205752 kb
Host smart-2fa74d62-ab29-4805-a1bd-55baa5139eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36958
60445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.3695860445
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_eop_single_bit_handling.4011393259
Short name T1409
Test name
Test status
Simulation time 10063954694 ps
CPU time 13.45 seconds
Started Jun 06 01:49:56 PM PDT 24
Finished Jun 06 01:50:10 PM PDT 24
Peak memory 205760 kb
Host smart-fcf1c4c6-5dfa-4533-86f3-5e302ec210c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40113
93259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_eop_single_bit_handling.4011393259
Directory /workspace/27.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.2698970374
Short name T45
Test name
Test status
Simulation time 10056876790 ps
CPU time 13.19 seconds
Started Jun 06 01:49:58 PM PDT 24
Finished Jun 06 01:50:12 PM PDT 24
Peak memory 205732 kb
Host smart-b5f4e437-ca6b-4211-93c5-d84c24cae8f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26989
70374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.2698970374
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.1977229171
Short name T1528
Test name
Test status
Simulation time 10110894712 ps
CPU time 14.32 seconds
Started Jun 06 01:49:54 PM PDT 24
Finished Jun 06 01:50:09 PM PDT 24
Peak memory 205600 kb
Host smart-52346856-f981-41df-b33b-42b0a2c1333a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19772
29171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.1977229171
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.1325681935
Short name T1697
Test name
Test status
Simulation time 29184816414 ps
CPU time 53.86 seconds
Started Jun 06 01:50:01 PM PDT 24
Finished Jun 06 01:50:56 PM PDT 24
Peak memory 205668 kb
Host smart-c08de5bb-f4cf-48b8-9f8a-6c36420db3ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13256
81935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.1325681935
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.2842293119
Short name T1258
Test name
Test status
Simulation time 10116535108 ps
CPU time 14.64 seconds
Started Jun 06 01:49:53 PM PDT 24
Finished Jun 06 01:50:09 PM PDT 24
Peak memory 205712 kb
Host smart-8e9061e0-3558-45f3-9fd8-6a35b7a2946a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28422
93119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.2842293119
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3960912737
Short name T1636
Test name
Test status
Simulation time 10133114043 ps
CPU time 15.58 seconds
Started Jun 06 01:49:55 PM PDT 24
Finished Jun 06 01:50:12 PM PDT 24
Peak memory 205612 kb
Host smart-bc8bc012-cb24-48fb-9bf3-d5a56d3c2d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39609
12737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3960912737
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.2406440514
Short name T1378
Test name
Test status
Simulation time 10116068351 ps
CPU time 13.96 seconds
Started Jun 06 01:49:58 PM PDT 24
Finished Jun 06 01:50:13 PM PDT 24
Peak memory 205772 kb
Host smart-23c9ca2d-7c45-483f-8170-44db30555e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24064
40514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.2406440514
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.2717661331
Short name T792
Test name
Test status
Simulation time 10090383360 ps
CPU time 14.88 seconds
Started Jun 06 01:49:55 PM PDT 24
Finished Jun 06 01:50:11 PM PDT 24
Peak memory 205600 kb
Host smart-bcfaad1d-0621-425e-a1f7-9b0811613808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27176
61331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.2717661331
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.1101270501
Short name T146
Test name
Test status
Simulation time 10073042168 ps
CPU time 13.39 seconds
Started Jun 06 01:49:58 PM PDT 24
Finished Jun 06 01:50:12 PM PDT 24
Peak memory 205672 kb
Host smart-01b772a3-539d-4010-9cc8-2092f9b7afe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11012
70501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1101270501
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1572197995
Short name T1959
Test name
Test status
Simulation time 10053280594 ps
CPU time 14.27 seconds
Started Jun 06 01:49:56 PM PDT 24
Finished Jun 06 01:50:11 PM PDT 24
Peak memory 205764 kb
Host smart-5f0ffbb7-aa7e-48eb-aaf2-80702b8ba644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15721
97995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1572197995
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.3616255342
Short name T656
Test name
Test status
Simulation time 10138531510 ps
CPU time 14.03 seconds
Started Jun 06 01:49:55 PM PDT 24
Finished Jun 06 01:50:10 PM PDT 24
Peak memory 205632 kb
Host smart-361a5aab-6f02-4e6e-939b-f0ff41b7d794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36162
55342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.3616255342
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.972209721
Short name T968
Test name
Test status
Simulation time 10096452752 ps
CPU time 13.87 seconds
Started Jun 06 01:49:58 PM PDT 24
Finished Jun 06 01:50:13 PM PDT 24
Peak memory 205676 kb
Host smart-58a9db72-cc4e-4a37-afdb-e8d7a5b7994b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97220
9721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.972209721
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.1354434583
Short name T1166
Test name
Test status
Simulation time 10085350885 ps
CPU time 13.11 seconds
Started Jun 06 01:49:56 PM PDT 24
Finished Jun 06 01:50:10 PM PDT 24
Peak memory 205672 kb
Host smart-6f75db63-e90c-4a42-a081-eda1c8017d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13544
34583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1354434583
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.1068863139
Short name T713
Test name
Test status
Simulation time 17606866087 ps
CPU time 81.3 seconds
Started Jun 06 01:49:54 PM PDT 24
Finished Jun 06 01:51:16 PM PDT 24
Peak memory 205744 kb
Host smart-8afa2fa5-b94f-4124-9106-3592ecc141c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10688
63139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.1068863139
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.3770251018
Short name T1847
Test name
Test status
Simulation time 10167045557 ps
CPU time 12.62 seconds
Started Jun 06 01:50:19 PM PDT 24
Finished Jun 06 01:50:32 PM PDT 24
Peak memory 205708 kb
Host smart-9e558ac3-d739-46f1-8a59-79cc3b4cd8ed
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3770251018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.3770251018
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.252456171
Short name T1464
Test name
Test status
Simulation time 10099749324 ps
CPU time 13.67 seconds
Started Jun 06 01:50:13 PM PDT 24
Finished Jun 06 01:50:28 PM PDT 24
Peak memory 205732 kb
Host smart-fc4683a1-8017-4208-afea-b298022df0e0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=252456171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.252456171
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.1466622156
Short name T1023
Test name
Test status
Simulation time 10175842410 ps
CPU time 13.17 seconds
Started Jun 06 01:50:12 PM PDT 24
Finished Jun 06 01:50:26 PM PDT 24
Peak memory 205612 kb
Host smart-6f45a72f-6dba-4daa-896a-808e13c2878f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14666
22156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.1466622156
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.915876929
Short name T1895
Test name
Test status
Simulation time 13635670563 ps
CPU time 16.42 seconds
Started Jun 06 01:50:02 PM PDT 24
Finished Jun 06 01:50:20 PM PDT 24
Peak memory 205688 kb
Host smart-e2e489f5-edce-48f5-af87-450cc9fa04a8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=915876929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.915876929
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.1494057362
Short name T582
Test name
Test status
Simulation time 23230093404 ps
CPU time 26.81 seconds
Started Jun 06 01:50:03 PM PDT 24
Finished Jun 06 01:50:30 PM PDT 24
Peak memory 205800 kb
Host smart-c118a2ac-004f-4ca4-b081-8be38433697b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1494057362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.1494057362
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.2864867848
Short name T269
Test name
Test status
Simulation time 10069637147 ps
CPU time 14.65 seconds
Started Jun 06 01:50:08 PM PDT 24
Finished Jun 06 01:50:23 PM PDT 24
Peak memory 205692 kb
Host smart-3beb95ba-b921-4981-95ea-9a3ba8a76c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28648
67848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.2864867848
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.742158636
Short name T1377
Test name
Test status
Simulation time 10594700609 ps
CPU time 14.53 seconds
Started Jun 06 01:50:05 PM PDT 24
Finished Jun 06 01:50:21 PM PDT 24
Peak memory 205672 kb
Host smart-35736dce-b7a3-4f6b-8080-721402af2c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74215
8636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.742158636
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.1699069765
Short name T1899
Test name
Test status
Simulation time 10052906351 ps
CPU time 14.96 seconds
Started Jun 06 01:50:03 PM PDT 24
Finished Jun 06 01:50:19 PM PDT 24
Peak memory 205652 kb
Host smart-106efa3e-47cb-4fc3-a98f-96595474e7a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16990
69765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.1699069765
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.1042012444
Short name T1638
Test name
Test status
Simulation time 10052321647 ps
CPU time 13.3 seconds
Started Jun 06 01:50:05 PM PDT 24
Finished Jun 06 01:50:19 PM PDT 24
Peak memory 205684 kb
Host smart-3ff43a66-27f1-4b86-961e-13309347fa8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10420
12444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.1042012444
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.3911970275
Short name T486
Test name
Test status
Simulation time 10935561566 ps
CPU time 14.36 seconds
Started Jun 06 01:50:02 PM PDT 24
Finished Jun 06 01:50:17 PM PDT 24
Peak memory 205708 kb
Host smart-750a8bb9-c361-4f39-b201-d824633db0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39119
70275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.3911970275
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2847524439
Short name T1094
Test name
Test status
Simulation time 10243060063 ps
CPU time 13.68 seconds
Started Jun 06 01:50:06 PM PDT 24
Finished Jun 06 01:50:21 PM PDT 24
Peak memory 205728 kb
Host smart-c8ca14aa-ba31-41f2-8c85-b14b69cbe766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28475
24439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2847524439
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.997323878
Short name T1682
Test name
Test status
Simulation time 10138723574 ps
CPU time 13.27 seconds
Started Jun 06 01:50:07 PM PDT 24
Finished Jun 06 01:50:21 PM PDT 24
Peak memory 205660 kb
Host smart-92c62a5e-2e8c-4c26-809c-ee2b12c39fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99732
3878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.997323878
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.4252089346
Short name T1405
Test name
Test status
Simulation time 10059604566 ps
CPU time 12.98 seconds
Started Jun 06 01:50:07 PM PDT 24
Finished Jun 06 01:50:21 PM PDT 24
Peak memory 205572 kb
Host smart-adec98e2-7aa2-4e02-b1cc-346398c5ac13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42520
89346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.4252089346
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.2623206830
Short name T91
Test name
Test status
Simulation time 10096900441 ps
CPU time 15.64 seconds
Started Jun 06 01:50:11 PM PDT 24
Finished Jun 06 01:50:28 PM PDT 24
Peak memory 205648 kb
Host smart-b75deb85-ff33-4b00-ab53-8c5f9d95bd36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26232
06830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.2623206830
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.3392030806
Short name T1571
Test name
Test status
Simulation time 10125946557 ps
CPU time 13.12 seconds
Started Jun 06 01:50:06 PM PDT 24
Finished Jun 06 01:50:20 PM PDT 24
Peak memory 205612 kb
Host smart-1c3d7330-04f2-40e5-8358-46debaa6b145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33920
30806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.3392030806
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.2946827921
Short name T1031
Test name
Test status
Simulation time 13183535035 ps
CPU time 18.58 seconds
Started Jun 06 01:50:06 PM PDT 24
Finished Jun 06 01:50:25 PM PDT 24
Peak memory 205772 kb
Host smart-76980040-7144-4de9-a8f9-8c5d742ee3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29468
27921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.2946827921
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.4231808717
Short name T658
Test name
Test status
Simulation time 10092604607 ps
CPU time 17.47 seconds
Started Jun 06 01:50:04 PM PDT 24
Finished Jun 06 01:50:22 PM PDT 24
Peak memory 205672 kb
Host smart-20a85767-442d-4adf-8da8-455de3f83ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42318
08717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.4231808717
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.2994544907
Short name T1107
Test name
Test status
Simulation time 21048620153 ps
CPU time 319.71 seconds
Started Jun 06 01:50:02 PM PDT 24
Finished Jun 06 01:55:23 PM PDT 24
Peak memory 205628 kb
Host smart-f325d28f-cdef-4e73-be92-da107c7aed73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29945
44907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.2994544907
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1434408596
Short name T1021
Test name
Test status
Simulation time 10047539569 ps
CPU time 15.15 seconds
Started Jun 06 01:50:03 PM PDT 24
Finished Jun 06 01:50:19 PM PDT 24
Peak memory 205704 kb
Host smart-180af925-6856-413b-b5e8-b2fcb1a801c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14344
08596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1434408596
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.943972393
Short name T117
Test name
Test status
Simulation time 10092319743 ps
CPU time 15.58 seconds
Started Jun 06 01:50:03 PM PDT 24
Finished Jun 06 01:50:19 PM PDT 24
Peak memory 205648 kb
Host smart-bd3118a3-c32d-45a7-93e0-879d5e116764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94397
2393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.943972393
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.576014878
Short name T943
Test name
Test status
Simulation time 10064334287 ps
CPU time 13.59 seconds
Started Jun 06 01:50:04 PM PDT 24
Finished Jun 06 01:50:18 PM PDT 24
Peak memory 205792 kb
Host smart-a75e6e73-2c60-4bef-804c-dec066340e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57601
4878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.576014878
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3914172624
Short name T438
Test name
Test status
Simulation time 10092417803 ps
CPU time 13.75 seconds
Started Jun 06 01:50:07 PM PDT 24
Finished Jun 06 01:50:21 PM PDT 24
Peak memory 205740 kb
Host smart-4ed73680-9dcc-452c-a867-cae6d77b683a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39141
72624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3914172624
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2647117090
Short name T1220
Test name
Test status
Simulation time 10070693233 ps
CPU time 12.53 seconds
Started Jun 06 01:50:08 PM PDT 24
Finished Jun 06 01:50:21 PM PDT 24
Peak memory 205612 kb
Host smart-fc3520dd-19f1-4028-838b-65a005c03aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26471
17090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2647117090
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1179844123
Short name T137
Test name
Test status
Simulation time 10077578884 ps
CPU time 13.29 seconds
Started Jun 06 01:50:04 PM PDT 24
Finished Jun 06 01:50:18 PM PDT 24
Peak memory 205676 kb
Host smart-0b9c2caf-74dd-40d6-8c18-a732ce9b114b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11798
44123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1179844123
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_eop_single_bit_handling.2812511614
Short name T1029
Test name
Test status
Simulation time 10082148267 ps
CPU time 14.45 seconds
Started Jun 06 01:50:08 PM PDT 24
Finished Jun 06 01:50:23 PM PDT 24
Peak memory 205772 kb
Host smart-c8c38ced-1f52-45eb-b9c7-2d380bed6fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28125
11614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_eop_single_bit_handling.2812511614
Directory /workspace/28.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.2348845053
Short name T873
Test name
Test status
Simulation time 10069968348 ps
CPU time 13.37 seconds
Started Jun 06 01:50:08 PM PDT 24
Finished Jun 06 01:50:22 PM PDT 24
Peak memory 205716 kb
Host smart-510d85a6-c9f9-43ce-b921-b7fc5db50e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23488
45053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.2348845053
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.3930123019
Short name T1701
Test name
Test status
Simulation time 10037370549 ps
CPU time 13.21 seconds
Started Jun 06 01:50:12 PM PDT 24
Finished Jun 06 01:50:26 PM PDT 24
Peak memory 205568 kb
Host smart-93383e09-5983-4801-86d9-3062c4dc01b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39301
23019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.3930123019
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.4223379386
Short name T1865
Test name
Test status
Simulation time 25618149187 ps
CPU time 50.27 seconds
Started Jun 06 01:50:06 PM PDT 24
Finished Jun 06 01:50:57 PM PDT 24
Peak memory 205664 kb
Host smart-a6a31cd9-8b5f-40fa-9ded-957f18f57ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42233
79386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.4223379386
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.3091485037
Short name T1363
Test name
Test status
Simulation time 10067948580 ps
CPU time 15.52 seconds
Started Jun 06 01:50:04 PM PDT 24
Finished Jun 06 01:50:20 PM PDT 24
Peak memory 205728 kb
Host smart-110e8cd6-0912-4abe-a9a0-8376b171aced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30914
85037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.3091485037
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.3307711940
Short name T1181
Test name
Test status
Simulation time 10092675547 ps
CPU time 13.48 seconds
Started Jun 06 01:50:07 PM PDT 24
Finished Jun 06 01:50:21 PM PDT 24
Peak memory 205684 kb
Host smart-b5ae3ac2-c7c9-4cdb-b036-2151d3631fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33077
11940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.3307711940
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.243479784
Short name T1327
Test name
Test status
Simulation time 10150533776 ps
CPU time 14.31 seconds
Started Jun 06 01:50:12 PM PDT 24
Finished Jun 06 01:50:28 PM PDT 24
Peak memory 205552 kb
Host smart-82f4512c-1c93-4a6b-9ade-a38fbcb1f5f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24347
9784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.243479784
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.3204135546
Short name T1702
Test name
Test status
Simulation time 10046349481 ps
CPU time 12.6 seconds
Started Jun 06 01:50:06 PM PDT 24
Finished Jun 06 01:50:20 PM PDT 24
Peak memory 205764 kb
Host smart-5ae73a53-90f8-4420-bf6a-eff648abe443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32041
35546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.3204135546
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.534020387
Short name T862
Test name
Test status
Simulation time 10049647292 ps
CPU time 12.92 seconds
Started Jun 06 01:50:07 PM PDT 24
Finished Jun 06 01:50:20 PM PDT 24
Peak memory 205684 kb
Host smart-311695c1-a476-4181-b8a7-8ccea8842be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53402
0387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.534020387
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.33941184
Short name T1748
Test name
Test status
Simulation time 10061119385 ps
CPU time 13.43 seconds
Started Jun 06 01:50:07 PM PDT 24
Finished Jun 06 01:50:21 PM PDT 24
Peak memory 205656 kb
Host smart-79e0fb23-d409-48a3-9c42-f33a3a97b267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33941
184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.33941184
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.1100680910
Short name T1731
Test name
Test status
Simulation time 10147841763 ps
CPU time 15.79 seconds
Started Jun 06 01:50:07 PM PDT 24
Finished Jun 06 01:50:23 PM PDT 24
Peak memory 205768 kb
Host smart-8b92c557-d46d-4600-a4ae-fb625bbb2b00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11006
80910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.1100680910
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.2787496094
Short name T1946
Test name
Test status
Simulation time 10062333413 ps
CPU time 13.83 seconds
Started Jun 06 01:50:07 PM PDT 24
Finished Jun 06 01:50:22 PM PDT 24
Peak memory 205672 kb
Host smart-474dead8-af28-41a1-ac0a-2d768ef5a8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27874
96094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.2787496094
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.2154341337
Short name T663
Test name
Test status
Simulation time 10098663304 ps
CPU time 14.4 seconds
Started Jun 06 01:50:02 PM PDT 24
Finished Jun 06 01:50:17 PM PDT 24
Peak memory 205744 kb
Host smart-7a3dca85-8735-4427-81c4-83180e99bde9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21543
41337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2154341337
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.131404630
Short name T1436
Test name
Test status
Simulation time 21268285241 ps
CPU time 340.35 seconds
Started Jun 06 01:50:04 PM PDT 24
Finished Jun 06 01:55:45 PM PDT 24
Peak memory 205648 kb
Host smart-5af6f88c-4f7d-4206-81a0-1fbb2e64a78d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13140
4630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.131404630
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.3337913875
Short name T388
Test name
Test status
Simulation time 10153617795 ps
CPU time 14.25 seconds
Started Jun 06 01:50:25 PM PDT 24
Finished Jun 06 01:50:41 PM PDT 24
Peak memory 205776 kb
Host smart-41823cbe-2b60-463d-9729-ed113899b59b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3337913875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.3337913875
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.2024012460
Short name T1047
Test name
Test status
Simulation time 10053821058 ps
CPU time 14.94 seconds
Started Jun 06 01:50:24 PM PDT 24
Finished Jun 06 01:50:40 PM PDT 24
Peak memory 205616 kb
Host smart-b5743da1-8383-42d1-9b31-590f25d5fadf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2024012460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.2024012460
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.2711929254
Short name T1872
Test name
Test status
Simulation time 10120421309 ps
CPU time 15.58 seconds
Started Jun 06 01:50:26 PM PDT 24
Finished Jun 06 01:50:42 PM PDT 24
Peak memory 205668 kb
Host smart-adb1777f-b885-42d9-9b75-c532d14e30c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27119
29254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.2711929254
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1825588401
Short name T452
Test name
Test status
Simulation time 13719436197 ps
CPU time 16.89 seconds
Started Jun 06 01:50:12 PM PDT 24
Finished Jun 06 01:50:30 PM PDT 24
Peak memory 205776 kb
Host smart-fdc6b733-0a2e-4d22-b79d-3a17751f10a2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1825588401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.1825588401
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.1757823163
Short name T1227
Test name
Test status
Simulation time 23228330142 ps
CPU time 25.43 seconds
Started Jun 06 01:50:13 PM PDT 24
Finished Jun 06 01:50:39 PM PDT 24
Peak memory 205732 kb
Host smart-3ac71441-d58a-44a3-b869-0e0f11738e7e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1757823163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.1757823163
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.3225480435
Short name T1876
Test name
Test status
Simulation time 10050214460 ps
CPU time 13.68 seconds
Started Jun 06 01:50:16 PM PDT 24
Finished Jun 06 01:50:31 PM PDT 24
Peak memory 205768 kb
Host smart-d34cb0bf-a120-4aa2-bb1b-821ab829b172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32254
80435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.3225480435
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.3248424768
Short name T1213
Test name
Test status
Simulation time 11245245455 ps
CPU time 15.89 seconds
Started Jun 06 01:50:15 PM PDT 24
Finished Jun 06 01:50:32 PM PDT 24
Peak memory 205652 kb
Host smart-5e7644ad-869f-47be-bd4b-97a1f825148f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32484
24768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.3248424768
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_enable.3710650451
Short name T555
Test name
Test status
Simulation time 10066084887 ps
CPU time 13.44 seconds
Started Jun 06 01:50:12 PM PDT 24
Finished Jun 06 01:50:26 PM PDT 24
Peak memory 205648 kb
Host smart-8f3dc23f-7c58-4a65-9a63-d8b1a9e86ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37106
50451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3710650451
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.656510947
Short name T1955
Test name
Test status
Simulation time 10796062202 ps
CPU time 14.74 seconds
Started Jun 06 01:50:16 PM PDT 24
Finished Jun 06 01:50:31 PM PDT 24
Peak memory 205636 kb
Host smart-2c8f20d6-1848-4f07-9cae-05764858ac47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65651
0947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.656510947
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2884537829
Short name T728
Test name
Test status
Simulation time 10165422263 ps
CPU time 14.78 seconds
Started Jun 06 01:50:12 PM PDT 24
Finished Jun 06 01:50:27 PM PDT 24
Peak memory 205716 kb
Host smart-fa1f3018-37f2-4b80-9bd1-8f68b345c43c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28845
37829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2884537829
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.4266684595
Short name T423
Test name
Test status
Simulation time 10153558181 ps
CPU time 15.94 seconds
Started Jun 06 01:50:23 PM PDT 24
Finished Jun 06 01:50:40 PM PDT 24
Peak memory 205704 kb
Host smart-18b9cbae-1764-4a09-8e0e-770a2108c01c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42666
84595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.4266684595
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.194081167
Short name T805
Test name
Test status
Simulation time 10068310560 ps
CPU time 13.81 seconds
Started Jun 06 01:50:24 PM PDT 24
Finished Jun 06 01:50:39 PM PDT 24
Peak memory 205728 kb
Host smart-27b7bd11-2fd3-44ce-8d98-89ab66b3b498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19408
1167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.194081167
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.259568795
Short name T608
Test name
Test status
Simulation time 10063252813 ps
CPU time 16.27 seconds
Started Jun 06 01:50:16 PM PDT 24
Finished Jun 06 01:50:33 PM PDT 24
Peak memory 205764 kb
Host smart-4216c1ae-4073-4d99-89a3-5688c3edf1f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25956
8795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.259568795
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.1569919265
Short name T1417
Test name
Test status
Simulation time 10160894988 ps
CPU time 15.94 seconds
Started Jun 06 01:50:16 PM PDT 24
Finished Jun 06 01:50:32 PM PDT 24
Peak memory 205700 kb
Host smart-f1c95af2-0d6c-4ac6-8606-1b09629a3d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15699
19265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.1569919265
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.2338055286
Short name T1940
Test name
Test status
Simulation time 13235029806 ps
CPU time 15.51 seconds
Started Jun 06 01:50:16 PM PDT 24
Finished Jun 06 01:50:32 PM PDT 24
Peak memory 205672 kb
Host smart-c3ed213f-bcc3-4a1a-b6ce-766ef61b97e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23380
55286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.2338055286
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2512614949
Short name T982
Test name
Test status
Simulation time 10110631156 ps
CPU time 13.28 seconds
Started Jun 06 01:50:13 PM PDT 24
Finished Jun 06 01:50:27 PM PDT 24
Peak memory 205900 kb
Host smart-f69462d5-e25f-4a6f-9da4-2dcee5c6aacb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25126
14949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2512614949
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.3406361885
Short name T1779
Test name
Test status
Simulation time 23926593007 ps
CPU time 406.2 seconds
Started Jun 06 01:50:16 PM PDT 24
Finished Jun 06 01:57:03 PM PDT 24
Peak memory 205672 kb
Host smart-d447c882-5d29-40ef-ab6d-658d54fdeefd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34063
61885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.3406361885
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.1803695348
Short name T377
Test name
Test status
Simulation time 10062387614 ps
CPU time 13.29 seconds
Started Jun 06 01:50:14 PM PDT 24
Finished Jun 06 01:50:28 PM PDT 24
Peak memory 205648 kb
Host smart-bfbcb104-ffa7-41d4-ab11-b52b7f0cf815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18036
95348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.1803695348
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.1630397658
Short name T129
Test name
Test status
Simulation time 10134339309 ps
CPU time 14.41 seconds
Started Jun 06 01:50:16 PM PDT 24
Finished Jun 06 01:50:31 PM PDT 24
Peak memory 205784 kb
Host smart-df20e5a4-da72-4198-9ff4-42c8dca61d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16303
97658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1630397658
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.2909278943
Short name T991
Test name
Test status
Simulation time 10081777391 ps
CPU time 15.69 seconds
Started Jun 06 01:50:17 PM PDT 24
Finished Jun 06 01:50:34 PM PDT 24
Peak memory 205712 kb
Host smart-ec9aec3e-ce89-4000-ad42-a4e5dc5f8d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29092
78943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.2909278943
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.210130907
Short name T1206
Test name
Test status
Simulation time 10093876231 ps
CPU time 13.78 seconds
Started Jun 06 01:50:14 PM PDT 24
Finished Jun 06 01:50:28 PM PDT 24
Peak memory 205660 kb
Host smart-04e5bfc8-2f5b-4f49-9d7b-5cd96414f60d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21013
0907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.210130907
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3054135374
Short name T1084
Test name
Test status
Simulation time 10073957310 ps
CPU time 13.88 seconds
Started Jun 06 01:50:11 PM PDT 24
Finished Jun 06 01:50:26 PM PDT 24
Peak memory 205628 kb
Host smart-c33f9f5d-4fdd-40cb-a248-7484a544d924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30541
35374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3054135374
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.1149394594
Short name T1630
Test name
Test status
Simulation time 10110701213 ps
CPU time 13.63 seconds
Started Jun 06 01:50:23 PM PDT 24
Finished Jun 06 01:50:37 PM PDT 24
Peak memory 205656 kb
Host smart-14e1f7ea-8b05-4201-a849-5199d110aa82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11493
94594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.1149394594
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_eop_single_bit_handling.2960740249
Short name T1729
Test name
Test status
Simulation time 10069944328 ps
CPU time 13.24 seconds
Started Jun 06 01:50:26 PM PDT 24
Finished Jun 06 01:50:40 PM PDT 24
Peak memory 205692 kb
Host smart-179e1870-f2bb-477f-aec5-d22d95ea50d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29607
40249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_eop_single_bit_handling.2960740249
Directory /workspace/29.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.1650726825
Short name T46
Test name
Test status
Simulation time 10038064498 ps
CPU time 12.57 seconds
Started Jun 06 01:50:23 PM PDT 24
Finished Jun 06 01:50:37 PM PDT 24
Peak memory 205636 kb
Host smart-0c5eac70-762c-48eb-a759-3aa9d304c4f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16507
26825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.1650726825
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.764648202
Short name T835
Test name
Test status
Simulation time 10103892458 ps
CPU time 13.07 seconds
Started Jun 06 01:50:22 PM PDT 24
Finished Jun 06 01:50:36 PM PDT 24
Peak memory 205668 kb
Host smart-3e351b8f-afd5-44e7-93bf-e88b77465ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76464
8202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.764648202
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2313645156
Short name T1424
Test name
Test status
Simulation time 17982932707 ps
CPU time 31.21 seconds
Started Jun 06 01:50:13 PM PDT 24
Finished Jun 06 01:50:45 PM PDT 24
Peak memory 205624 kb
Host smart-97901c04-e56a-488c-9837-c346dd6418df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23136
45156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2313645156
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.2163249087
Short name T347
Test name
Test status
Simulation time 10136989328 ps
CPU time 14.56 seconds
Started Jun 06 01:50:16 PM PDT 24
Finished Jun 06 01:50:31 PM PDT 24
Peak memory 205648 kb
Host smart-c336e7c6-1684-4439-b051-cc59bfe59307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21632
49087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.2163249087
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.850436097
Short name T1421
Test name
Test status
Simulation time 10137486322 ps
CPU time 14.1 seconds
Started Jun 06 01:50:12 PM PDT 24
Finished Jun 06 01:50:27 PM PDT 24
Peak memory 205724 kb
Host smart-c8718d16-af3e-47f6-befd-60081789042b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85043
6097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.850436097
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.180101896
Short name T891
Test name
Test status
Simulation time 10039442777 ps
CPU time 12.4 seconds
Started Jun 06 01:50:27 PM PDT 24
Finished Jun 06 01:50:40 PM PDT 24
Peak memory 205772 kb
Host smart-c692ebbc-6e8d-43b2-96df-47125f4cb1a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18010
1896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.180101896
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.3724856994
Short name T1801
Test name
Test status
Simulation time 10059462870 ps
CPU time 16.35 seconds
Started Jun 06 01:50:24 PM PDT 24
Finished Jun 06 01:50:41 PM PDT 24
Peak memory 205728 kb
Host smart-faeb951f-d205-4ec6-96cd-ba5dc3cf8964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37248
56994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.3724856994
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3547909744
Short name T1187
Test name
Test status
Simulation time 10069791461 ps
CPU time 14.34 seconds
Started Jun 06 01:50:27 PM PDT 24
Finished Jun 06 01:50:42 PM PDT 24
Peak memory 205772 kb
Host smart-e0074083-d471-4c82-9a72-d94b7e4ed387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35479
09744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3547909744
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.3419872410
Short name T1080
Test name
Test status
Simulation time 10111710553 ps
CPU time 13.8 seconds
Started Jun 06 01:50:15 PM PDT 24
Finished Jun 06 01:50:29 PM PDT 24
Peak memory 205712 kb
Host smart-abb18fa2-fdcb-4654-b2cd-dfa9debc6bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34198
72410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.3419872410
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.2115361339
Short name T272
Test name
Test status
Simulation time 10120920108 ps
CPU time 15.52 seconds
Started Jun 06 01:50:24 PM PDT 24
Finished Jun 06 01:50:40 PM PDT 24
Peak memory 205760 kb
Host smart-15d875ba-232e-4243-83d4-c4d59b1dd3fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21153
61339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.2115361339
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.2991387000
Short name T1109
Test name
Test status
Simulation time 10089116603 ps
CPU time 13.38 seconds
Started Jun 06 01:50:15 PM PDT 24
Finished Jun 06 01:50:29 PM PDT 24
Peak memory 205764 kb
Host smart-fb18fb1e-5e23-4038-9e12-cda4b8fa08af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29913
87000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2991387000
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.3278331163
Short name T633
Test name
Test status
Simulation time 22142252981 ps
CPU time 337.1 seconds
Started Jun 06 01:50:30 PM PDT 24
Finished Jun 06 01:56:08 PM PDT 24
Peak memory 205640 kb
Host smart-ac07b4b6-22a0-45a0-b6e9-631e7d562a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32783
31163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.3278331163
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.2470798282
Short name T318
Test name
Test status
Simulation time 10159319824 ps
CPU time 13.5 seconds
Started Jun 06 01:45:21 PM PDT 24
Finished Jun 06 01:45:35 PM PDT 24
Peak memory 205636 kb
Host smart-22e288cb-a7d3-48d2-8726-ba544ebf85ab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2470798282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.2470798282
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.626138761
Short name T267
Test name
Test status
Simulation time 10066146674 ps
CPU time 13.11 seconds
Started Jun 06 01:45:21 PM PDT 24
Finished Jun 06 01:45:35 PM PDT 24
Peak memory 205572 kb
Host smart-a78c5564-7cdb-44b5-b00b-fccfbef2fbab
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=626138761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.626138761
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.2681871079
Short name T1617
Test name
Test status
Simulation time 10104365802 ps
CPU time 13.2 seconds
Started Jun 06 01:45:19 PM PDT 24
Finished Jun 06 01:45:33 PM PDT 24
Peak memory 205576 kb
Host smart-e0dd21ad-416e-4599-947f-7d6ea6ecfed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26818
71079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.2681871079
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.3470910654
Short name T1324
Test name
Test status
Simulation time 13494473965 ps
CPU time 18.7 seconds
Started Jun 06 01:45:00 PM PDT 24
Finished Jun 06 01:45:20 PM PDT 24
Peak memory 205728 kb
Host smart-061ad854-bc12-4969-a48c-c982ba1c9028
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3470910654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.3470910654
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.1459431354
Short name T1011
Test name
Test status
Simulation time 23222140973 ps
CPU time 28.87 seconds
Started Jun 06 01:45:02 PM PDT 24
Finished Jun 06 01:45:32 PM PDT 24
Peak memory 205672 kb
Host smart-3954086b-a83c-4d3f-a3ad-8e9350d20292
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1459431354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.1459431354
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.579408996
Short name T1840
Test name
Test status
Simulation time 10052477015 ps
CPU time 15.44 seconds
Started Jun 06 01:45:04 PM PDT 24
Finished Jun 06 01:45:20 PM PDT 24
Peak memory 205736 kb
Host smart-30945283-f9bb-43ec-89bb-4d1816f01894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57940
8996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.579408996
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.3461647721
Short name T954
Test name
Test status
Simulation time 11074280777 ps
CPU time 14.83 seconds
Started Jun 06 01:45:03 PM PDT 24
Finished Jun 06 01:45:19 PM PDT 24
Peak memory 205692 kb
Host smart-10809189-5f18-43bf-b1ea-511356a565f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34616
47721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.3461647721
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.3161821734
Short name T1410
Test name
Test status
Simulation time 10066388921 ps
CPU time 13.04 seconds
Started Jun 06 01:45:03 PM PDT 24
Finished Jun 06 01:45:17 PM PDT 24
Peak memory 205576 kb
Host smart-859337e4-857c-4da3-abf3-04d2a2d01072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31618
21734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.3161821734
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.827649961
Short name T770
Test name
Test status
Simulation time 10065160337 ps
CPU time 14.24 seconds
Started Jun 06 01:45:01 PM PDT 24
Finished Jun 06 01:45:17 PM PDT 24
Peak memory 205684 kb
Host smart-ab34286a-359c-4a9c-ac0d-eec683ee47c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82764
9961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.827649961
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.2905574015
Short name T944
Test name
Test status
Simulation time 10727477937 ps
CPU time 14.94 seconds
Started Jun 06 01:45:02 PM PDT 24
Finished Jun 06 01:45:18 PM PDT 24
Peak memory 205712 kb
Host smart-4468ad9f-bf05-446e-83d8-44c5f0040a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29055
74015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.2905574015
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.2080144609
Short name T1775
Test name
Test status
Simulation time 10107383430 ps
CPU time 17.66 seconds
Started Jun 06 01:45:01 PM PDT 24
Finished Jun 06 01:45:20 PM PDT 24
Peak memory 205684 kb
Host smart-ddfd3ae1-d745-4e94-ba54-eca6bac45784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20801
44609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.2080144609
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.3729564346
Short name T1411
Test name
Test status
Simulation time 10072757418 ps
CPU time 13.64 seconds
Started Jun 06 01:45:21 PM PDT 24
Finished Jun 06 01:45:35 PM PDT 24
Peak memory 205648 kb
Host smart-a8a25ecd-ef04-4aa2-8ac4-c685d372327c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37295
64346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.3729564346
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.2307788752
Short name T673
Test name
Test status
Simulation time 10067578158 ps
CPU time 13.36 seconds
Started Jun 06 01:45:09 PM PDT 24
Finished Jun 06 01:45:23 PM PDT 24
Peak memory 205760 kb
Host smart-f818c759-c433-40f8-a546-d54593cc1863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23077
88752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2307788752
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.3516950773
Short name T51
Test name
Test status
Simulation time 10104835148 ps
CPU time 12.78 seconds
Started Jun 06 01:45:03 PM PDT 24
Finished Jun 06 01:45:17 PM PDT 24
Peak memory 205740 kb
Host smart-17e3d882-d8cc-4057-960b-ba5d86cd2560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35169
50773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.3516950773
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.3157869382
Short name T812
Test name
Test status
Simulation time 10074030355 ps
CPU time 16.45 seconds
Started Jun 06 01:45:01 PM PDT 24
Finished Jun 06 01:45:19 PM PDT 24
Peak memory 205756 kb
Host smart-b6d7138b-c255-42b5-bbce-91a13f8d85db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31578
69382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.3157869382
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.1631948851
Short name T443
Test name
Test status
Simulation time 13268202250 ps
CPU time 17.99 seconds
Started Jun 06 01:45:02 PM PDT 24
Finished Jun 06 01:45:21 PM PDT 24
Peak memory 205712 kb
Host smart-b1467a4a-af76-43d6-b767-f55c038de4f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16319
48851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.1631948851
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.2232566221
Short name T747
Test name
Test status
Simulation time 10122779463 ps
CPU time 14.12 seconds
Started Jun 06 01:45:01 PM PDT 24
Finished Jun 06 01:45:16 PM PDT 24
Peak memory 205588 kb
Host smart-be0047bb-8583-4284-b2be-3368864b77f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22325
66221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.2232566221
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.3875603365
Short name T1201
Test name
Test status
Simulation time 15466489475 ps
CPU time 169.01 seconds
Started Jun 06 01:45:03 PM PDT 24
Finished Jun 06 01:47:53 PM PDT 24
Peak memory 205576 kb
Host smart-469628ae-d2e4-42b3-9d7d-7ee1fa21dce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38756
03365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.3875603365
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.743967314
Short name T1755
Test name
Test status
Simulation time 10077247143 ps
CPU time 14.5 seconds
Started Jun 06 01:45:01 PM PDT 24
Finished Jun 06 01:45:16 PM PDT 24
Peak memory 205728 kb
Host smart-48a6decb-6eb2-4a92-af2e-ba65118035c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74396
7314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.743967314
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.1822737917
Short name T1937
Test name
Test status
Simulation time 10084301236 ps
CPU time 16.14 seconds
Started Jun 06 01:45:11 PM PDT 24
Finished Jun 06 01:45:28 PM PDT 24
Peak memory 205680 kb
Host smart-29f19cf7-3759-4d6b-b41a-967c9e54a74d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18227
37917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.1822737917
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.3783406916
Short name T802
Test name
Test status
Simulation time 10069072312 ps
CPU time 13.66 seconds
Started Jun 06 01:45:11 PM PDT 24
Finished Jun 06 01:45:25 PM PDT 24
Peak memory 205644 kb
Host smart-e7d063ed-e738-4daf-b865-6679f2eae1d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37834
06916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.3783406916
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3873296559
Short name T1427
Test name
Test status
Simulation time 10074375038 ps
CPU time 13.49 seconds
Started Jun 06 01:45:11 PM PDT 24
Finished Jun 06 01:45:26 PM PDT 24
Peak memory 205720 kb
Host smart-b2113e97-374d-438c-a4ae-1c545e0cfaac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38732
96559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3873296559
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.1385043429
Short name T837
Test name
Test status
Simulation time 10065085577 ps
CPU time 14.41 seconds
Started Jun 06 01:45:11 PM PDT 24
Finished Jun 06 01:45:26 PM PDT 24
Peak memory 205732 kb
Host smart-eb94995e-d63c-4492-9eac-878d4ecbe82d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13850
43429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.1385043429
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.4048307002
Short name T790
Test name
Test status
Simulation time 10055161308 ps
CPU time 13.98 seconds
Started Jun 06 01:45:14 PM PDT 24
Finished Jun 06 01:45:30 PM PDT 24
Peak memory 205768 kb
Host smart-f48e05ee-0764-405b-bb3e-41b9f256e078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40483
07002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.4048307002
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_eop_single_bit_handling.1725658019
Short name T1461
Test name
Test status
Simulation time 10077176334 ps
CPU time 14.17 seconds
Started Jun 06 01:45:11 PM PDT 24
Finished Jun 06 01:45:26 PM PDT 24
Peak memory 205748 kb
Host smart-1b74ad39-acef-4fb6-ba36-3c079b80a54e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17256
58019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_eop_single_bit_handling.1725658019
Directory /workspace/3.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2760214612
Short name T942
Test name
Test status
Simulation time 10045870512 ps
CPU time 18.27 seconds
Started Jun 06 01:45:09 PM PDT 24
Finished Jun 06 01:45:28 PM PDT 24
Peak memory 205688 kb
Host smart-99ea74e9-aff7-43fd-9cbb-2ea87a5fb033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27602
14612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2760214612
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.1090152572
Short name T1061
Test name
Test status
Simulation time 29585062623 ps
CPU time 58.57 seconds
Started Jun 06 01:45:14 PM PDT 24
Finished Jun 06 01:46:14 PM PDT 24
Peak memory 205712 kb
Host smart-b34f6c83-2827-4f98-a587-afca43d6bb2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10901
52572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.1090152572
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.415996120
Short name T1784
Test name
Test status
Simulation time 10071412078 ps
CPU time 15.25 seconds
Started Jun 06 01:45:09 PM PDT 24
Finished Jun 06 01:45:25 PM PDT 24
Peak memory 205668 kb
Host smart-316912f3-fff8-45c3-97c2-6a73c5b00166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41599
6120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.415996120
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.867158526
Short name T1506
Test name
Test status
Simulation time 10048363297 ps
CPU time 14.94 seconds
Started Jun 06 01:45:11 PM PDT 24
Finished Jun 06 01:45:27 PM PDT 24
Peak memory 205604 kb
Host smart-66d4544b-964a-4025-955a-10d5c788f8fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86715
8526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.867158526
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.119459105
Short name T1122
Test name
Test status
Simulation time 21572541118 ps
CPU time 126.37 seconds
Started Jun 06 01:45:11 PM PDT 24
Finished Jun 06 01:47:19 PM PDT 24
Peak memory 205772 kb
Host smart-f018c2f2-976e-4021-8fef-2aabcd77a961
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=119459105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.119459105
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.4083617000
Short name T1066
Test name
Test status
Simulation time 28607350932 ps
CPU time 151.88 seconds
Started Jun 06 01:45:19 PM PDT 24
Finished Jun 06 01:47:52 PM PDT 24
Peak memory 205784 kb
Host smart-cf8e78a4-9508-42de-84db-de3c6e41c22c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4083617000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.4083617000
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.2586047709
Short name T596
Test name
Test status
Simulation time 49016397092 ps
CPU time 1026.24 seconds
Started Jun 06 01:45:10 PM PDT 24
Finished Jun 06 02:02:17 PM PDT 24
Peak memory 205704 kb
Host smart-c0b0395b-f51d-40eb-b9b3-5fb2ee30b177
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2586047709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2586047709
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.911124534
Short name T2007
Test name
Test status
Simulation time 10081133509 ps
CPU time 13.15 seconds
Started Jun 06 01:45:09 PM PDT 24
Finished Jun 06 01:45:23 PM PDT 24
Peak memory 205688 kb
Host smart-5051c4b6-dc6d-4ae7-9e9d-6643c017bdcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91112
4534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.911124534
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.1859365350
Short name T64
Test name
Test status
Simulation time 10117896788 ps
CPU time 13.38 seconds
Started Jun 06 01:45:12 PM PDT 24
Finished Jun 06 01:45:26 PM PDT 24
Peak memory 205740 kb
Host smart-0775cba7-3e19-4031-85a8-878c5c7b8266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18593
65350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.1859365350
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.4106285653
Short name T199
Test name
Test status
Simulation time 578924643 ps
CPU time 1.48 seconds
Started Jun 06 01:45:21 PM PDT 24
Finished Jun 06 01:45:24 PM PDT 24
Peak memory 222768 kb
Host smart-1b6bd2ee-1eb9-47cd-9385-792d53efc7de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4106285653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.4106285653
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.3735380754
Short name T876
Test name
Test status
Simulation time 10122414634 ps
CPU time 13.28 seconds
Started Jun 06 01:45:09 PM PDT 24
Finished Jun 06 01:45:23 PM PDT 24
Peak memory 205592 kb
Host smart-f0372d21-ad48-40d5-9c4b-1c1895f5f1d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37353
80754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.3735380754
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2561305331
Short name T1039
Test name
Test status
Simulation time 10060689837 ps
CPU time 13.71 seconds
Started Jun 06 01:45:10 PM PDT 24
Finished Jun 06 01:45:25 PM PDT 24
Peak memory 205724 kb
Host smart-3ee90afa-19f7-49ca-b973-cf89b3632af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25613
05331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2561305331
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.196718720
Short name T1679
Test name
Test status
Simulation time 10138810734 ps
CPU time 14.06 seconds
Started Jun 06 01:45:02 PM PDT 24
Finished Jun 06 01:45:17 PM PDT 24
Peak memory 205748 kb
Host smart-4ddc477d-92b9-439b-a47b-bea86a7024a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19671
8720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.196718720
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.1608805597
Short name T380
Test name
Test status
Simulation time 10070434005 ps
CPU time 12.96 seconds
Started Jun 06 01:45:11 PM PDT 24
Finished Jun 06 01:45:24 PM PDT 24
Peak memory 205680 kb
Host smart-30ceb15f-c25c-46c5-823a-7016fbbfca94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16088
05597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.1608805597
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2933830112
Short name T314
Test name
Test status
Simulation time 10111631763 ps
CPU time 14.28 seconds
Started Jun 06 01:45:11 PM PDT 24
Finished Jun 06 01:45:26 PM PDT 24
Peak memory 205724 kb
Host smart-16e77664-9d16-45ed-a0e8-538d98e651eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29338
30112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2933830112
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.452739849
Short name T585
Test name
Test status
Simulation time 16933375702 ps
CPU time 65.24 seconds
Started Jun 06 01:45:10 PM PDT 24
Finished Jun 06 01:46:16 PM PDT 24
Peak memory 205724 kb
Host smart-19532e26-9acb-4556-8c22-40aca8976d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45273
9849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.452739849
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.680454390
Short name T167
Test name
Test status
Simulation time 20683849748 ps
CPU time 108.64 seconds
Started Jun 06 01:45:11 PM PDT 24
Finished Jun 06 01:47:00 PM PDT 24
Peak memory 205688 kb
Host smart-f38a40c5-6b29-46b3-8300-76538fb38112
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680454390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bu
s_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_t
raffic.680454390
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.3241913799
Short name T344
Test name
Test status
Simulation time 10159651097 ps
CPU time 17.06 seconds
Started Jun 06 01:50:36 PM PDT 24
Finished Jun 06 01:50:54 PM PDT 24
Peak memory 205712 kb
Host smart-4db97154-e3f2-4ec2-8ae9-6488d29bcf70
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3241913799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.3241913799
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.2622347278
Short name T1153
Test name
Test status
Simulation time 10066846100 ps
CPU time 16.44 seconds
Started Jun 06 01:50:34 PM PDT 24
Finished Jun 06 01:50:51 PM PDT 24
Peak memory 205628 kb
Host smart-f68262d6-2d07-4870-9257-f52c17689cb5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2622347278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.2622347278
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.362582134
Short name T1425
Test name
Test status
Simulation time 10097703792 ps
CPU time 13.88 seconds
Started Jun 06 01:50:43 PM PDT 24
Finished Jun 06 01:50:58 PM PDT 24
Peak memory 205672 kb
Host smart-d661f92b-2982-4901-8f33-9a9a84018eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36258
2134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.362582134
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.2273241192
Short name T1121
Test name
Test status
Simulation time 13463214802 ps
CPU time 15.61 seconds
Started Jun 06 01:50:26 PM PDT 24
Finished Jun 06 01:50:42 PM PDT 24
Peak memory 205752 kb
Host smart-a3692306-3956-4d4b-853b-46e4eaa43bb0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2273241192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.2273241192
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.1203113451
Short name T1930
Test name
Test status
Simulation time 23308455690 ps
CPU time 28.71 seconds
Started Jun 06 01:50:25 PM PDT 24
Finished Jun 06 01:50:54 PM PDT 24
Peak memory 205724 kb
Host smart-8aa2ec71-bc8e-47e4-a64b-0ef4171e3bfa
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1203113451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.1203113451
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.4084105953
Short name T817
Test name
Test status
Simulation time 10083556505 ps
CPU time 13.22 seconds
Started Jun 06 01:50:23 PM PDT 24
Finished Jun 06 01:50:38 PM PDT 24
Peak memory 205608 kb
Host smart-6bd8ec76-7d58-4bae-bbe4-b51f1fb7889d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40841
05953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.4084105953
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.2758212184
Short name T1751
Test name
Test status
Simulation time 11052034837 ps
CPU time 17.17 seconds
Started Jun 06 01:50:22 PM PDT 24
Finished Jun 06 01:50:40 PM PDT 24
Peak memory 205660 kb
Host smart-b25c2536-a35b-46c0-97ed-0cfe4f48292a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27582
12184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.2758212184
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.1743213624
Short name T1991
Test name
Test status
Simulation time 10052665514 ps
CPU time 13.34 seconds
Started Jun 06 01:50:36 PM PDT 24
Finished Jun 06 01:50:50 PM PDT 24
Peak memory 205696 kb
Host smart-2c6ffbaf-3170-4d44-9296-bf48aacdc9e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17432
13624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.1743213624
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.1537141087
Short name T1856
Test name
Test status
Simulation time 10079398232 ps
CPU time 15.61 seconds
Started Jun 06 01:50:24 PM PDT 24
Finished Jun 06 01:50:40 PM PDT 24
Peak memory 205684 kb
Host smart-d3345eba-a85c-486b-86a9-afe59dbd1ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15371
41087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.1537141087
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.1676123800
Short name T907
Test name
Test status
Simulation time 10791396919 ps
CPU time 14.9 seconds
Started Jun 06 01:50:28 PM PDT 24
Finished Jun 06 01:50:43 PM PDT 24
Peak memory 205652 kb
Host smart-c309e579-a622-4381-a786-2e60eaf36da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16761
23800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.1676123800
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3379241581
Short name T1778
Test name
Test status
Simulation time 10100791604 ps
CPU time 14.24 seconds
Started Jun 06 01:50:25 PM PDT 24
Finished Jun 06 01:50:41 PM PDT 24
Peak memory 205612 kb
Host smart-c604d400-d001-4360-b908-eb1c7aa7794e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33792
41581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3379241581
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.2963391825
Short name T855
Test name
Test status
Simulation time 10108015806 ps
CPU time 13.67 seconds
Started Jun 06 01:50:34 PM PDT 24
Finished Jun 06 01:50:49 PM PDT 24
Peak memory 205616 kb
Host smart-df25d2cb-3efb-4e7e-8950-f3a1f3b8e85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29633
91825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.2963391825
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.3406946855
Short name T472
Test name
Test status
Simulation time 10134060296 ps
CPU time 13.63 seconds
Started Jun 06 01:50:34 PM PDT 24
Finished Jun 06 01:50:49 PM PDT 24
Peak memory 205692 kb
Host smart-24e47637-acce-4a6c-8bdf-b77ebdfa40a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34069
46855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.3406946855
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.658140319
Short name T990
Test name
Test status
Simulation time 10113561238 ps
CPU time 14.72 seconds
Started Jun 06 01:50:23 PM PDT 24
Finished Jun 06 01:50:39 PM PDT 24
Peak memory 205764 kb
Host smart-86443898-0957-49aa-819b-040a5cf0e23b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65814
0319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.658140319
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.3124029644
Short name T1169
Test name
Test status
Simulation time 10081145463 ps
CPU time 13.75 seconds
Started Jun 06 01:50:25 PM PDT 24
Finished Jun 06 01:50:39 PM PDT 24
Peak memory 205888 kb
Host smart-95b87dfa-7974-42c2-ae43-9141780d19b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31240
29644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.3124029644
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.4026663946
Short name T492
Test name
Test status
Simulation time 13228218262 ps
CPU time 16.49 seconds
Started Jun 06 01:50:37 PM PDT 24
Finished Jun 06 01:50:55 PM PDT 24
Peak memory 205668 kb
Host smart-544cdbf0-1e3f-405b-8322-ae1f97d974cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40266
63946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.4026663946
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3874597318
Short name T1275
Test name
Test status
Simulation time 10091405460 ps
CPU time 13.14 seconds
Started Jun 06 01:50:37 PM PDT 24
Finished Jun 06 01:50:51 PM PDT 24
Peak memory 205620 kb
Host smart-12d40a24-1eb4-4ff2-a6f9-be586eeb5c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38745
97318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3874597318
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.141526529
Short name T1185
Test name
Test status
Simulation time 15719956594 ps
CPU time 54.94 seconds
Started Jun 06 01:50:36 PM PDT 24
Finished Jun 06 01:51:33 PM PDT 24
Peak memory 205688 kb
Host smart-d7169a26-e124-47c6-9eae-75b67bbf8d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14152
6529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.141526529
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.4005645808
Short name T1303
Test name
Test status
Simulation time 10043933317 ps
CPU time 16.06 seconds
Started Jun 06 01:50:36 PM PDT 24
Finished Jun 06 01:50:54 PM PDT 24
Peak memory 205728 kb
Host smart-d755f6b3-a0fb-4b3f-85eb-7632713df0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40056
45808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.4005645808
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2095161788
Short name T1757
Test name
Test status
Simulation time 10109700056 ps
CPU time 14.18 seconds
Started Jun 06 01:50:35 PM PDT 24
Finished Jun 06 01:50:50 PM PDT 24
Peak memory 205680 kb
Host smart-f66a909f-4366-4a7c-9d63-a968d6efb739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20951
61788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2095161788
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3234143695
Short name T1529
Test name
Test status
Simulation time 10090273269 ps
CPU time 13.35 seconds
Started Jun 06 01:50:36 PM PDT 24
Finished Jun 06 01:50:51 PM PDT 24
Peak memory 205732 kb
Host smart-577c4053-15d1-432c-9832-e46ed3c990e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32341
43695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3234143695
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.1444757228
Short name T845
Test name
Test status
Simulation time 10081250924 ps
CPU time 16.83 seconds
Started Jun 06 01:50:35 PM PDT 24
Finished Jun 06 01:50:53 PM PDT 24
Peak memory 205740 kb
Host smart-f0bdc76f-1854-42bd-a48d-d2ca0dc4d14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14447
57228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.1444757228
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1107890341
Short name T466
Test name
Test status
Simulation time 10071522450 ps
CPU time 13.74 seconds
Started Jun 06 01:50:41 PM PDT 24
Finished Jun 06 01:50:55 PM PDT 24
Peak memory 205696 kb
Host smart-271c262d-230a-4df1-9c82-7a97ab2aa00e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11078
90341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1107890341
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.1824079616
Short name T139
Test name
Test status
Simulation time 10099089678 ps
CPU time 15.15 seconds
Started Jun 06 01:50:38 PM PDT 24
Finished Jun 06 01:50:54 PM PDT 24
Peak memory 206008 kb
Host smart-fe1d4824-f9c3-4d42-bc83-ac1302fe8553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18240
79616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.1824079616
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_eop_single_bit_handling.3428309263
Short name T636
Test name
Test status
Simulation time 10053838141 ps
CPU time 14.25 seconds
Started Jun 06 01:50:40 PM PDT 24
Finished Jun 06 01:50:55 PM PDT 24
Peak memory 205748 kb
Host smart-2319f84d-ceef-43de-87c6-8156665d389c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34283
09263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_eop_single_bit_handling.3428309263
Directory /workspace/30.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.531769993
Short name T322
Test name
Test status
Simulation time 10046647668 ps
CPU time 13.62 seconds
Started Jun 06 01:50:33 PM PDT 24
Finished Jun 06 01:50:47 PM PDT 24
Peak memory 205696 kb
Host smart-5deb8d5d-af50-44dc-840a-34bdb69ab0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53176
9993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.531769993
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2285559979
Short name T44
Test name
Test status
Simulation time 10040461784 ps
CPU time 15.02 seconds
Started Jun 06 01:50:37 PM PDT 24
Finished Jun 06 01:50:54 PM PDT 24
Peak memory 205712 kb
Host smart-6967d466-27f5-40a3-80c0-0afea946efdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22855
59979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2285559979
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.2250048908
Short name T1831
Test name
Test status
Simulation time 20093459698 ps
CPU time 40.9 seconds
Started Jun 06 01:50:33 PM PDT 24
Finished Jun 06 01:51:15 PM PDT 24
Peak memory 205632 kb
Host smart-ef12cc06-e4b8-4d18-a507-a2fbb056abf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22500
48908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.2250048908
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.2016762979
Short name T430
Test name
Test status
Simulation time 10055877852 ps
CPU time 15.7 seconds
Started Jun 06 01:50:34 PM PDT 24
Finished Jun 06 01:50:51 PM PDT 24
Peak memory 205596 kb
Host smart-96dd516e-fd6d-4961-84dd-04fc760656f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20167
62979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.2016762979
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.137076453
Short name T1864
Test name
Test status
Simulation time 10130152297 ps
CPU time 14.12 seconds
Started Jun 06 01:50:36 PM PDT 24
Finished Jun 06 01:50:52 PM PDT 24
Peak memory 205672 kb
Host smart-9ff4d586-f02c-4f47-b9c4-5c999a29730f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13707
6453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.137076453
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.3248038310
Short name T1642
Test name
Test status
Simulation time 10086403461 ps
CPU time 12.86 seconds
Started Jun 06 01:50:39 PM PDT 24
Finished Jun 06 01:50:53 PM PDT 24
Peak memory 205712 kb
Host smart-d9ddada4-b0ae-4953-81a1-95b19517150a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32480
38310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.3248038310
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.1043181760
Short name T960
Test name
Test status
Simulation time 10057057023 ps
CPU time 14.79 seconds
Started Jun 06 01:50:38 PM PDT 24
Finished Jun 06 01:50:54 PM PDT 24
Peak memory 205856 kb
Host smart-cb9aa1c0-9d2a-49a7-b543-13bc6b5c7a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10431
81760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.1043181760
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.3874657291
Short name T1060
Test name
Test status
Simulation time 10053722693 ps
CPU time 15.87 seconds
Started Jun 06 01:50:34 PM PDT 24
Finished Jun 06 01:50:51 PM PDT 24
Peak memory 205712 kb
Host smart-25c28a33-0684-4aa2-8a70-f4937eb53f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38746
57291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.3874657291
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3686517030
Short name T1523
Test name
Test status
Simulation time 10103344352 ps
CPU time 13.99 seconds
Started Jun 06 01:50:35 PM PDT 24
Finished Jun 06 01:50:50 PM PDT 24
Peak memory 205704 kb
Host smart-65c30052-1067-4e09-9af5-917e3cf21120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36865
17030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3686517030
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3863886300
Short name T1644
Test name
Test status
Simulation time 10158236775 ps
CPU time 13.52 seconds
Started Jun 06 01:50:23 PM PDT 24
Finished Jun 06 01:50:38 PM PDT 24
Peak memory 205716 kb
Host smart-cb0b41fb-6195-4f77-b57e-ade133e083ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38638
86300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3863886300
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.3604254706
Short name T560
Test name
Test status
Simulation time 10085923885 ps
CPU time 17.24 seconds
Started Jun 06 01:50:34 PM PDT 24
Finished Jun 06 01:50:52 PM PDT 24
Peak memory 205736 kb
Host smart-8b926bf5-32c4-4c6f-b8d7-f568ec965904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36042
54706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3604254706
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.3527188284
Short name T1927
Test name
Test status
Simulation time 10062255505 ps
CPU time 14.7 seconds
Started Jun 06 01:50:43 PM PDT 24
Finished Jun 06 01:50:58 PM PDT 24
Peak memory 205712 kb
Host smart-1ace9460-8921-45ad-80c3-ec26426b7f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35271
88284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.3527188284
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.334839172
Short name T1981
Test name
Test status
Simulation time 24300632309 ps
CPU time 425.59 seconds
Started Jun 06 01:50:37 PM PDT 24
Finished Jun 06 01:57:44 PM PDT 24
Peak memory 205648 kb
Host smart-fcbb0043-d6a9-4c45-b7d9-a3af8bd9328c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33483
9172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.334839172
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.845941373
Short name T957
Test name
Test status
Simulation time 10208310088 ps
CPU time 13.82 seconds
Started Jun 06 01:50:37 PM PDT 24
Finished Jun 06 01:50:52 PM PDT 24
Peak memory 205720 kb
Host smart-0801c1a9-12f8-4f93-826f-763f597ccfbe
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=845941373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.845941373
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.4030300711
Short name T941
Test name
Test status
Simulation time 10073449493 ps
CPU time 15.54 seconds
Started Jun 06 01:50:34 PM PDT 24
Finished Jun 06 01:50:51 PM PDT 24
Peak memory 205764 kb
Host smart-a84ad41e-48ef-4a67-a149-9bf6a2696048
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4030300711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.4030300711
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.2243706454
Short name T333
Test name
Test status
Simulation time 10106113560 ps
CPU time 15.17 seconds
Started Jun 06 01:50:37 PM PDT 24
Finished Jun 06 01:50:53 PM PDT 24
Peak memory 205620 kb
Host smart-1e3902cb-2590-4535-95ee-51fe7f3345af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22437
06454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.2243706454
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.1921795300
Short name T1064
Test name
Test status
Simulation time 13898748527 ps
CPU time 17.43 seconds
Started Jun 06 01:50:41 PM PDT 24
Finished Jun 06 01:50:59 PM PDT 24
Peak memory 205668 kb
Host smart-1dd843d4-74d7-4590-af0f-740bb20c08ec
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1921795300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.1921795300
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.2076387407
Short name T1926
Test name
Test status
Simulation time 23294246775 ps
CPU time 30.86 seconds
Started Jun 06 01:50:39 PM PDT 24
Finished Jun 06 01:51:11 PM PDT 24
Peak memory 205764 kb
Host smart-915a5ba8-25a9-425e-a443-86d371dfa889
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2076387407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.2076387407
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.3865952151
Short name T1286
Test name
Test status
Simulation time 10051109574 ps
CPU time 14.06 seconds
Started Jun 06 01:50:35 PM PDT 24
Finished Jun 06 01:50:50 PM PDT 24
Peak memory 205728 kb
Host smart-590ecfc9-ca25-4811-a7c0-fbeac624c36b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38659
52151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.3865952151
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.3740230720
Short name T216
Test name
Test status
Simulation time 10083010087 ps
CPU time 13.39 seconds
Started Jun 06 01:50:34 PM PDT 24
Finished Jun 06 01:50:48 PM PDT 24
Peak memory 205964 kb
Host smart-8546af93-0847-42ec-8924-05d7aaf64c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37402
30720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.3740230720
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.174829244
Short name T1159
Test name
Test status
Simulation time 10187901147 ps
CPU time 13.14 seconds
Started Jun 06 01:50:34 PM PDT 24
Finished Jun 06 01:50:49 PM PDT 24
Peak memory 205748 kb
Host smart-cccf0028-9815-48b0-b8c1-e4a2fbeb2782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17482
9244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.174829244
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.1740839096
Short name T543
Test name
Test status
Simulation time 10043635224 ps
CPU time 14.05 seconds
Started Jun 06 01:50:37 PM PDT 24
Finished Jun 06 01:50:52 PM PDT 24
Peak memory 205712 kb
Host smart-95991715-8e5e-47f8-8ac8-4e4704531168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17408
39096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.1740839096
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.1237134319
Short name T985
Test name
Test status
Simulation time 10047378416 ps
CPU time 13.48 seconds
Started Jun 06 01:50:39 PM PDT 24
Finished Jun 06 01:50:54 PM PDT 24
Peak memory 205644 kb
Host smart-fe94a5ff-6c4c-4ff1-862c-b492c461cc94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12371
34319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.1237134319
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.4279730253
Short name T889
Test name
Test status
Simulation time 10880205394 ps
CPU time 14.87 seconds
Started Jun 06 01:50:35 PM PDT 24
Finished Jun 06 01:50:51 PM PDT 24
Peak memory 205700 kb
Host smart-545f87a8-cac1-4562-8ea5-d2cd09ba5e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42797
30253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.4279730253
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.578212160
Short name T1597
Test name
Test status
Simulation time 10187267661 ps
CPU time 14.79 seconds
Started Jun 06 01:50:38 PM PDT 24
Finished Jun 06 01:50:54 PM PDT 24
Peak memory 205744 kb
Host smart-cc24e63d-2895-4b6c-b793-d2494db161d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57821
2160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.578212160
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.2467602821
Short name T675
Test name
Test status
Simulation time 10136873291 ps
CPU time 14.85 seconds
Started Jun 06 01:50:37 PM PDT 24
Finished Jun 06 01:50:53 PM PDT 24
Peak memory 205600 kb
Host smart-74f2f01b-ecaa-4f30-8dc0-ec4c4d635ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24676
02821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.2467602821
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.1190642733
Short name T509
Test name
Test status
Simulation time 10036944650 ps
CPU time 12.6 seconds
Started Jun 06 01:50:36 PM PDT 24
Finished Jun 06 01:50:49 PM PDT 24
Peak memory 205288 kb
Host smart-30b021c5-2df6-4b60-9ce9-2ecde5ccd379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11906
42733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.1190642733
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.3616931862
Short name T478
Test name
Test status
Simulation time 10130017215 ps
CPU time 13.99 seconds
Started Jun 06 01:50:35 PM PDT 24
Finished Jun 06 01:50:50 PM PDT 24
Peak memory 205692 kb
Host smart-1d5d36f8-9cc4-4c78-ba14-66f69cbd015d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36169
31862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.3616931862
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.4057977453
Short name T649
Test name
Test status
Simulation time 10149403114 ps
CPU time 14.62 seconds
Started Jun 06 01:50:37 PM PDT 24
Finished Jun 06 01:50:52 PM PDT 24
Peak memory 205736 kb
Host smart-356db80f-3c0f-4b62-a575-753dabf95e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40579
77453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.4057977453
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.3118529946
Short name T1147
Test name
Test status
Simulation time 13235258637 ps
CPU time 16.96 seconds
Started Jun 06 01:50:40 PM PDT 24
Finished Jun 06 01:50:57 PM PDT 24
Peak memory 205684 kb
Host smart-1019b69a-d073-478f-90af-59227441bd5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31185
29946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.3118529946
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.4166401199
Short name T498
Test name
Test status
Simulation time 10111541061 ps
CPU time 14.72 seconds
Started Jun 06 01:50:43 PM PDT 24
Finished Jun 06 01:50:58 PM PDT 24
Peak memory 205696 kb
Host smart-9419f605-5396-49b4-9e4c-23b519167ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41664
01199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.4166401199
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.499319205
Short name T1057
Test name
Test status
Simulation time 23003742244 ps
CPU time 386.42 seconds
Started Jun 06 01:50:34 PM PDT 24
Finished Jun 06 01:57:02 PM PDT 24
Peak memory 205720 kb
Host smart-672477c1-95b1-439d-9449-7492408bcd3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49931
9205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.499319205
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.361084776
Short name T1689
Test name
Test status
Simulation time 10062943228 ps
CPU time 15.71 seconds
Started Jun 06 01:50:36 PM PDT 24
Finished Jun 06 01:50:52 PM PDT 24
Peak memory 205664 kb
Host smart-c8deccf1-20d9-4a62-9c9d-6a76552718ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36108
4776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.361084776
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.10741511
Short name T126
Test name
Test status
Simulation time 10103575927 ps
CPU time 13.66 seconds
Started Jun 06 01:50:38 PM PDT 24
Finished Jun 06 01:50:53 PM PDT 24
Peak memory 205724 kb
Host smart-fc4c553d-793d-4272-9df8-a5b751087b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10741
511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.10741511
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.3779656141
Short name T1081
Test name
Test status
Simulation time 10097998993 ps
CPU time 13.6 seconds
Started Jun 06 01:50:35 PM PDT 24
Finished Jun 06 01:50:49 PM PDT 24
Peak memory 205728 kb
Host smart-ec76e339-03a2-40df-8893-070603d99957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37796
56141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.3779656141
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.2202340099
Short name T1300
Test name
Test status
Simulation time 10085349128 ps
CPU time 15.74 seconds
Started Jun 06 01:50:42 PM PDT 24
Finished Jun 06 01:50:59 PM PDT 24
Peak memory 205660 kb
Host smart-b5cc22cc-a78a-4289-8017-b12be3f48f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22023
40099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.2202340099
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.913584506
Short name T1475
Test name
Test status
Simulation time 10063449921 ps
CPU time 13.2 seconds
Started Jun 06 01:50:36 PM PDT 24
Finished Jun 06 01:50:50 PM PDT 24
Peak memory 205668 kb
Host smart-5e3660ae-6aea-44fc-86bb-fa800d469251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91358
4506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.913584506
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.4242259628
Short name T1615
Test name
Test status
Simulation time 10063190351 ps
CPU time 15.77 seconds
Started Jun 06 01:50:34 PM PDT 24
Finished Jun 06 01:50:51 PM PDT 24
Peak memory 205716 kb
Host smart-df40eefc-5e7f-4e5b-82a0-b5b6ae897b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42422
59628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.4242259628
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_eop_single_bit_handling.1456615250
Short name T1550
Test name
Test status
Simulation time 10106545505 ps
CPU time 14.05 seconds
Started Jun 06 01:50:35 PM PDT 24
Finished Jun 06 01:50:51 PM PDT 24
Peak memory 205752 kb
Host smart-f430827b-f89a-40b6-907d-baf1c6706db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14566
15250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_eop_single_bit_handling.1456615250
Directory /workspace/31.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.2572217368
Short name T445
Test name
Test status
Simulation time 10051381617 ps
CPU time 14.21 seconds
Started Jun 06 01:50:35 PM PDT 24
Finished Jun 06 01:50:50 PM PDT 24
Peak memory 205616 kb
Host smart-c9f5009d-5168-4158-b627-b9c649ca333e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25722
17368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.2572217368
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.1405386489
Short name T600
Test name
Test status
Simulation time 10072816086 ps
CPU time 13.96 seconds
Started Jun 06 01:50:34 PM PDT 24
Finished Jun 06 01:50:49 PM PDT 24
Peak memory 205728 kb
Host smart-35f51d1c-bf1a-4962-9c8a-d24ea505c2b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14053
86489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.1405386489
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.457773652
Short name T183
Test name
Test status
Simulation time 18355658268 ps
CPU time 30.21 seconds
Started Jun 06 01:50:33 PM PDT 24
Finished Jun 06 01:51:04 PM PDT 24
Peak memory 205640 kb
Host smart-d1a46fad-9765-4f00-b217-56887792dd7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45777
3652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.457773652
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.3468978319
Short name T1835
Test name
Test status
Simulation time 10069819246 ps
CPU time 13.13 seconds
Started Jun 06 01:50:36 PM PDT 24
Finished Jun 06 01:50:50 PM PDT 24
Peak memory 205732 kb
Host smart-3e548a7f-7be6-401b-8b41-5d55e990c1e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34689
78319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.3468978319
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.4193054731
Short name T603
Test name
Test status
Simulation time 10132421540 ps
CPU time 13.81 seconds
Started Jun 06 01:50:33 PM PDT 24
Finished Jun 06 01:50:48 PM PDT 24
Peak memory 205604 kb
Host smart-1c684bd6-0912-40d8-a041-1c47a1a65979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41930
54731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.4193054731
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.862977703
Short name T1364
Test name
Test status
Simulation time 10048317574 ps
CPU time 14.83 seconds
Started Jun 06 01:50:36 PM PDT 24
Finished Jun 06 01:50:52 PM PDT 24
Peak memory 205568 kb
Host smart-a3fdcad2-81ed-4204-8aca-16f065a9fe2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86297
7703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.862977703
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.3858546668
Short name T976
Test name
Test status
Simulation time 10047408287 ps
CPU time 13.48 seconds
Started Jun 06 01:50:34 PM PDT 24
Finished Jun 06 01:50:48 PM PDT 24
Peak memory 205712 kb
Host smart-941ffdfc-b02f-449e-bcf5-c29b20f2082e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38585
46668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.3858546668
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.3664664805
Short name T1372
Test name
Test status
Simulation time 10125213422 ps
CPU time 14.87 seconds
Started Jun 06 01:50:34 PM PDT 24
Finished Jun 06 01:50:50 PM PDT 24
Peak memory 205672 kb
Host smart-bc466063-02f2-4276-86c2-6dce1156bb26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36646
64805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.3664664805
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.77056777
Short name T557
Test name
Test status
Simulation time 10049243928 ps
CPU time 15.3 seconds
Started Jun 06 01:50:35 PM PDT 24
Finished Jun 06 01:50:51 PM PDT 24
Peak memory 205640 kb
Host smart-135b03bc-00a2-4686-bda6-b922a443f5c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77056
777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.77056777
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.2940891479
Short name T781
Test name
Test status
Simulation time 10129846651 ps
CPU time 13.28 seconds
Started Jun 06 01:50:35 PM PDT 24
Finished Jun 06 01:50:50 PM PDT 24
Peak memory 205736 kb
Host smart-402db6b2-2fd4-4ada-95a6-0e14ac843ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29408
91479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2940891479
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.3374766883
Short name T539
Test name
Test status
Simulation time 10124032444 ps
CPU time 12.83 seconds
Started Jun 06 01:50:35 PM PDT 24
Finished Jun 06 01:50:49 PM PDT 24
Peak memory 205640 kb
Host smart-04b47bdb-1bc3-44be-be88-44727b179a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33747
66883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.3374766883
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1896037187
Short name T1565
Test name
Test status
Simulation time 10076546709 ps
CPU time 14.65 seconds
Started Jun 06 01:50:35 PM PDT 24
Finished Jun 06 01:50:51 PM PDT 24
Peak memory 205672 kb
Host smart-3745c175-d9e7-4e06-8356-e59165f73bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18960
37187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1896037187
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.1672369769
Short name T1466
Test name
Test status
Simulation time 17157214771 ps
CPU time 83.37 seconds
Started Jun 06 01:50:36 PM PDT 24
Finished Jun 06 01:52:01 PM PDT 24
Peak memory 205680 kb
Host smart-a966c9a8-2969-41e6-911c-6b791a9458b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16723
69769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.1672369769
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.189445532
Short name T415
Test name
Test status
Simulation time 10145715162 ps
CPU time 15.78 seconds
Started Jun 06 01:50:48 PM PDT 24
Finished Jun 06 01:51:05 PM PDT 24
Peak memory 205720 kb
Host smart-76fc9244-3888-408d-a1e7-78639ff17823
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=189445532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.189445532
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.3519460970
Short name T761
Test name
Test status
Simulation time 10068878689 ps
CPU time 12.64 seconds
Started Jun 06 01:50:43 PM PDT 24
Finished Jun 06 01:50:56 PM PDT 24
Peak memory 205644 kb
Host smart-e514de87-e35e-49bd-a9c4-3ba5a5171e6e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3519460970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.3519460970
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.777508465
Short name T718
Test name
Test status
Simulation time 10153112829 ps
CPU time 14.34 seconds
Started Jun 06 01:50:47 PM PDT 24
Finished Jun 06 01:51:02 PM PDT 24
Peak memory 205724 kb
Host smart-d2621c6f-4f3e-4212-ab95-44908ca1a262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77750
8465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.777508465
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.690262254
Short name T205
Test name
Test status
Simulation time 14255770086 ps
CPU time 19.43 seconds
Started Jun 06 01:50:36 PM PDT 24
Finished Jun 06 01:50:56 PM PDT 24
Peak memory 205376 kb
Host smart-6cd0088c-cff6-45a0-a2df-75b9affd945b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=690262254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.690262254
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3372586857
Short name T1567
Test name
Test status
Simulation time 23338616786 ps
CPU time 26.8 seconds
Started Jun 06 01:50:39 PM PDT 24
Finished Jun 06 01:51:07 PM PDT 24
Peak memory 205736 kb
Host smart-cd0241f6-1a8c-4996-98d8-cb6c19cc858d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3372586857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3372586857
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.1837290805
Short name T1487
Test name
Test status
Simulation time 10065774577 ps
CPU time 14.27 seconds
Started Jun 06 01:50:43 PM PDT 24
Finished Jun 06 01:50:59 PM PDT 24
Peak memory 205716 kb
Host smart-5d54d6d6-14f1-4664-b95f-0012da9be7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18372
90805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.1837290805
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1343910684
Short name T72
Test name
Test status
Simulation time 10620169526 ps
CPU time 14.16 seconds
Started Jun 06 01:50:42 PM PDT 24
Finished Jun 06 01:50:57 PM PDT 24
Peak memory 205592 kb
Host smart-1d359848-9e58-468c-a960-790a50a1e21e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13439
10684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1343910684
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.254239266
Short name T394
Test name
Test status
Simulation time 10069005258 ps
CPU time 14.72 seconds
Started Jun 06 01:50:44 PM PDT 24
Finished Jun 06 01:51:00 PM PDT 24
Peak memory 205688 kb
Host smart-1c1bde38-dd72-4b29-83a1-68d32efd4999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25423
9266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.254239266
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2928498596
Short name T1932
Test name
Test status
Simulation time 10083926742 ps
CPU time 13.61 seconds
Started Jun 06 01:50:47 PM PDT 24
Finished Jun 06 01:51:01 PM PDT 24
Peak memory 205564 kb
Host smart-113cd563-684c-4388-8aac-45035b1834ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29284
98596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2928498596
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.3391706509
Short name T1674
Test name
Test status
Simulation time 10709749696 ps
CPU time 13.92 seconds
Started Jun 06 01:50:48 PM PDT 24
Finished Jun 06 01:51:03 PM PDT 24
Peak memory 205656 kb
Host smart-fd901679-9fa2-4470-a814-54c116b59cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33917
06509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.3391706509
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.2729793332
Short name T774
Test name
Test status
Simulation time 10224326331 ps
CPU time 13.82 seconds
Started Jun 06 01:50:45 PM PDT 24
Finished Jun 06 01:50:59 PM PDT 24
Peak memory 205720 kb
Host smart-06afb254-6924-415d-9e31-250baca17487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27297
93332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.2729793332
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.48139015
Short name T1414
Test name
Test status
Simulation time 10103376731 ps
CPU time 15.08 seconds
Started Jun 06 01:50:47 PM PDT 24
Finished Jun 06 01:51:04 PM PDT 24
Peak memory 205748 kb
Host smart-9972804d-043c-4542-9a25-b3d43cc63f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48139
015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.48139015
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.2548676224
Short name T1676
Test name
Test status
Simulation time 10101900793 ps
CPU time 13.62 seconds
Started Jun 06 01:50:48 PM PDT 24
Finished Jun 06 01:51:03 PM PDT 24
Peak memory 205720 kb
Host smart-8024bc9f-0949-4cf9-a91f-20e04c0c8b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25486
76224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.2548676224
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.4233472373
Short name T1108
Test name
Test status
Simulation time 10081465238 ps
CPU time 13.92 seconds
Started Jun 06 01:50:43 PM PDT 24
Finished Jun 06 01:50:57 PM PDT 24
Peak memory 205728 kb
Host smart-6360416f-1e2b-4fe1-b972-4c77ba908189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42334
72373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.4233472373
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.1695522849
Short name T690
Test name
Test status
Simulation time 10140365446 ps
CPU time 13.68 seconds
Started Jun 06 01:50:47 PM PDT 24
Finished Jun 06 01:51:01 PM PDT 24
Peak memory 205724 kb
Host smart-062a6868-0061-46ad-9261-ad1f2eebf5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16955
22849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1695522849
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.3946245337
Short name T878
Test name
Test status
Simulation time 13234961755 ps
CPU time 16.33 seconds
Started Jun 06 01:50:47 PM PDT 24
Finished Jun 06 01:51:04 PM PDT 24
Peak memory 205644 kb
Host smart-27e7eb0e-dca6-4874-8cae-6dd8ade50606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39462
45337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.3946245337
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1755376871
Short name T1538
Test name
Test status
Simulation time 10091416316 ps
CPU time 13.59 seconds
Started Jun 06 01:50:45 PM PDT 24
Finished Jun 06 01:50:59 PM PDT 24
Peak memory 205632 kb
Host smart-448624ba-6652-4f6d-a960-e646806dd320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17553
76871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1755376871
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.1252340974
Short name T1477
Test name
Test status
Simulation time 15509781020 ps
CPU time 69.73 seconds
Started Jun 06 01:50:48 PM PDT 24
Finished Jun 06 01:51:59 PM PDT 24
Peak memory 205720 kb
Host smart-05ab0570-ab08-4d4d-812f-58477b9acbcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12523
40974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.1252340974
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1163135841
Short name T1522
Test name
Test status
Simulation time 10037440021 ps
CPU time 15.27 seconds
Started Jun 06 01:50:42 PM PDT 24
Finished Jun 06 01:50:58 PM PDT 24
Peak memory 205672 kb
Host smart-b816d967-e799-45b7-b78e-e1dde12748f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11631
35841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1163135841
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.3438591076
Short name T116
Test name
Test status
Simulation time 10095490104 ps
CPU time 14.04 seconds
Started Jun 06 01:50:45 PM PDT 24
Finished Jun 06 01:51:00 PM PDT 24
Peak memory 205640 kb
Host smart-b86389ea-9195-4733-a64b-6ee6ad218a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34385
91076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3438591076
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.720027109
Short name T1205
Test name
Test status
Simulation time 10130247545 ps
CPU time 14.12 seconds
Started Jun 06 01:50:45 PM PDT 24
Finished Jun 06 01:51:00 PM PDT 24
Peak memory 205620 kb
Host smart-56f660c8-b53f-4542-a13f-db973e81b7fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72002
7109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.720027109
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.4060569849
Short name T34
Test name
Test status
Simulation time 10077828762 ps
CPU time 12.93 seconds
Started Jun 06 01:50:44 PM PDT 24
Finished Jun 06 01:50:58 PM PDT 24
Peak memory 205672 kb
Host smart-807e3b23-fd2d-4d53-a37f-bbccffddad77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40605
69849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.4060569849
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.2896954048
Short name T516
Test name
Test status
Simulation time 10093185598 ps
CPU time 15.01 seconds
Started Jun 06 01:50:49 PM PDT 24
Finished Jun 06 01:51:05 PM PDT 24
Peak memory 205668 kb
Host smart-3076aa34-47a1-4b8b-a441-a4bb682f98b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28969
54048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.2896954048
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.1171742323
Short name T1803
Test name
Test status
Simulation time 10047731371 ps
CPU time 13.07 seconds
Started Jun 06 01:50:43 PM PDT 24
Finished Jun 06 01:50:57 PM PDT 24
Peak memory 205676 kb
Host smart-9c8ec7a8-8f48-4cd2-91a4-4e3dba92f7d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11717
42323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.1171742323
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_eop_single_bit_handling.2055619989
Short name T241
Test name
Test status
Simulation time 10079397453 ps
CPU time 13.33 seconds
Started Jun 06 01:50:47 PM PDT 24
Finished Jun 06 01:51:01 PM PDT 24
Peak memory 205492 kb
Host smart-aad87d04-111f-4c87-95f7-ff4bfeff17b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20556
19989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_eop_single_bit_handling.2055619989
Directory /workspace/32.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.2768193356
Short name T999
Test name
Test status
Simulation time 10041595796 ps
CPU time 13.03 seconds
Started Jun 06 01:50:48 PM PDT 24
Finished Jun 06 01:51:02 PM PDT 24
Peak memory 205776 kb
Host smart-2ad7a934-95b9-4bdf-a96b-ef290e43a9b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27681
93356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.2768193356
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.2462446827
Short name T1913
Test name
Test status
Simulation time 10036745972 ps
CPU time 13.13 seconds
Started Jun 06 01:50:46 PM PDT 24
Finished Jun 06 01:51:00 PM PDT 24
Peak memory 205696 kb
Host smart-72cc56de-03b9-4e1c-be1d-e1c9734fd39e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24624
46827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.2462446827
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1544247656
Short name T274
Test name
Test status
Simulation time 15972406342 ps
CPU time 26.97 seconds
Started Jun 06 01:50:45 PM PDT 24
Finished Jun 06 01:51:13 PM PDT 24
Peak memory 205692 kb
Host smart-ba8df0b3-47a4-4e0e-9c06-732d04a98a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15442
47656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1544247656
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.1526329480
Short name T1765
Test name
Test status
Simulation time 10073173332 ps
CPU time 13.33 seconds
Started Jun 06 01:50:49 PM PDT 24
Finished Jun 06 01:51:03 PM PDT 24
Peak memory 205540 kb
Host smart-04529441-84bc-4223-bfa6-e63952b90c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15263
29480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.1526329480
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3812207505
Short name T398
Test name
Test status
Simulation time 10126782779 ps
CPU time 13.45 seconds
Started Jun 06 01:50:44 PM PDT 24
Finished Jun 06 01:50:58 PM PDT 24
Peak memory 205628 kb
Host smart-70c14025-0865-4f4f-b6fd-b9d910846433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38122
07505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3812207505
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.3136936841
Short name T1442
Test name
Test status
Simulation time 10130294505 ps
CPU time 15.01 seconds
Started Jun 06 01:50:43 PM PDT 24
Finished Jun 06 01:50:59 PM PDT 24
Peak memory 205700 kb
Host smart-a4b36699-7268-4e8d-be8d-76ee180d96e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31369
36841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.3136936841
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.2284293210
Short name T965
Test name
Test status
Simulation time 10045864628 ps
CPU time 13.48 seconds
Started Jun 06 01:50:47 PM PDT 24
Finished Jun 06 01:51:02 PM PDT 24
Peak memory 205724 kb
Host smart-18255e16-f916-47af-9667-88b4fbee3150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22842
93210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.2284293210
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.3084989609
Short name T1857
Test name
Test status
Simulation time 10081252138 ps
CPU time 13.23 seconds
Started Jun 06 01:50:47 PM PDT 24
Finished Jun 06 01:51:01 PM PDT 24
Peak memory 205488 kb
Host smart-faafa8e0-ff54-471d-8c8b-128cb4940f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30849
89609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3084989609
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2997177204
Short name T1014
Test name
Test status
Simulation time 10050176568 ps
CPU time 13.66 seconds
Started Jun 06 01:50:47 PM PDT 24
Finished Jun 06 01:51:02 PM PDT 24
Peak memory 205600 kb
Host smart-55389575-da62-4f68-9070-6139caa90de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29971
77204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2997177204
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1571537491
Short name T819
Test name
Test status
Simulation time 10117763121 ps
CPU time 13.67 seconds
Started Jun 06 01:50:40 PM PDT 24
Finished Jun 06 01:50:54 PM PDT 24
Peak memory 205648 kb
Host smart-c79bd2e8-5a32-455b-a664-731898b78e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15715
37491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1571537491
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1970916029
Short name T1965
Test name
Test status
Simulation time 10070708579 ps
CPU time 13.72 seconds
Started Jun 06 01:50:45 PM PDT 24
Finished Jun 06 01:50:59 PM PDT 24
Peak memory 205748 kb
Host smart-1afb77bb-56f0-4758-a462-56d68cdb63e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19709
16029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1970916029
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.459526332
Short name T372
Test name
Test status
Simulation time 10065172526 ps
CPU time 14.72 seconds
Started Jun 06 01:50:44 PM PDT 24
Finished Jun 06 01:51:00 PM PDT 24
Peak memory 205584 kb
Host smart-c56a1093-616a-4374-b796-62e52db7985b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45952
6332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.459526332
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.2289065963
Short name T407
Test name
Test status
Simulation time 16522687247 ps
CPU time 199.52 seconds
Started Jun 06 01:50:43 PM PDT 24
Finished Jun 06 01:54:04 PM PDT 24
Peak memory 205668 kb
Host smart-f054a31a-fd3f-4ca6-a44f-52ad4c086b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22890
65963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.2289065963
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.928884918
Short name T392
Test name
Test status
Simulation time 10144504340 ps
CPU time 13.37 seconds
Started Jun 06 01:50:55 PM PDT 24
Finished Jun 06 01:51:10 PM PDT 24
Peak memory 205780 kb
Host smart-e09f7d2b-34d9-4a48-bc9f-5525802eab24
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=928884918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.928884918
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.234228429
Short name T341
Test name
Test status
Simulation time 10050517095 ps
CPU time 14.56 seconds
Started Jun 06 01:50:52 PM PDT 24
Finished Jun 06 01:51:08 PM PDT 24
Peak memory 205664 kb
Host smart-d5e5b4ae-a0a1-4957-8464-4b3cea9fd748
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=234228429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.234228429
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.308950151
Short name T1202
Test name
Test status
Simulation time 10080229890 ps
CPU time 15.47 seconds
Started Jun 06 01:51:02 PM PDT 24
Finished Jun 06 01:51:19 PM PDT 24
Peak memory 205648 kb
Host smart-42f24368-c10b-4c49-a5de-93910ee88f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30895
0151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.308950151
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.4099872036
Short name T464
Test name
Test status
Simulation time 13448333883 ps
CPU time 16.8 seconds
Started Jun 06 01:50:46 PM PDT 24
Finished Jun 06 01:51:04 PM PDT 24
Peak memory 205740 kb
Host smart-366fa126-92f3-4ddc-8bb4-ef81536c9eff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4099872036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.4099872036
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.4158248817
Short name T706
Test name
Test status
Simulation time 23250820179 ps
CPU time 24.73 seconds
Started Jun 06 01:50:47 PM PDT 24
Finished Jun 06 01:51:13 PM PDT 24
Peak memory 205724 kb
Host smart-d430c7b1-b77d-474e-bdce-0f9fef8d3026
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4158248817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.4158248817
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.2734551017
Short name T740
Test name
Test status
Simulation time 10101844672 ps
CPU time 13.97 seconds
Started Jun 06 01:50:43 PM PDT 24
Finished Jun 06 01:50:58 PM PDT 24
Peak memory 205704 kb
Host smart-b145e023-0ea6-4bb3-b37d-b131e7ea5d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27345
51017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.2734551017
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.2891042461
Short name T1992
Test name
Test status
Simulation time 10079698322 ps
CPU time 12.97 seconds
Started Jun 06 01:50:46 PM PDT 24
Finished Jun 06 01:51:00 PM PDT 24
Peak memory 205744 kb
Host smart-4bb69cbe-b76b-47a5-83bb-0ac9ecc5b59f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28910
42461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.2891042461
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.2856705483
Short name T1270
Test name
Test status
Simulation time 10659870421 ps
CPU time 16.78 seconds
Started Jun 06 01:50:48 PM PDT 24
Finished Jun 06 01:51:06 PM PDT 24
Peak memory 205668 kb
Host smart-33cc93a3-87dc-40ac-9de1-c00eb0cebdbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28567
05483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.2856705483
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.49370168
Short name T1274
Test name
Test status
Simulation time 10073864556 ps
CPU time 16.56 seconds
Started Jun 06 01:51:02 PM PDT 24
Finished Jun 06 01:51:19 PM PDT 24
Peak memory 205736 kb
Host smart-3a3cca11-d041-4c1c-b531-8cc19c58c461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49370
168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.49370168
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.391389928
Short name T854
Test name
Test status
Simulation time 10104822578 ps
CPU time 12.85 seconds
Started Jun 06 01:50:45 PM PDT 24
Finished Jun 06 01:50:59 PM PDT 24
Peak memory 205764 kb
Host smart-d142256b-e26b-46e7-bf71-2f0a687cd844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39138
9928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.391389928
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.1532635909
Short name T545
Test name
Test status
Simulation time 10711292159 ps
CPU time 16.92 seconds
Started Jun 06 01:50:47 PM PDT 24
Finished Jun 06 01:51:05 PM PDT 24
Peak memory 205728 kb
Host smart-3136cf05-1ba3-4f36-82c4-33be7db6645f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15326
35909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.1532635909
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.909724606
Short name T1699
Test name
Test status
Simulation time 10096338607 ps
CPU time 13.8 seconds
Started Jun 06 01:50:43 PM PDT 24
Finished Jun 06 01:50:58 PM PDT 24
Peak memory 205768 kb
Host smart-1188c0a9-8f46-4d5a-8589-b6158f7b0944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90972
4606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.909724606
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.4267630000
Short name T1640
Test name
Test status
Simulation time 10098262326 ps
CPU time 14.1 seconds
Started Jun 06 01:50:53 PM PDT 24
Finished Jun 06 01:51:08 PM PDT 24
Peak memory 205612 kb
Host smart-dc19ae04-c26d-4071-a160-069f73547fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42676
30000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.4267630000
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.1550254435
Short name T1549
Test name
Test status
Simulation time 10043924975 ps
CPU time 12.85 seconds
Started Jun 06 01:51:08 PM PDT 24
Finished Jun 06 01:51:22 PM PDT 24
Peak memory 205676 kb
Host smart-ec4d6691-c9e4-4de2-999b-76914ceeba4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15502
54435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1550254435
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.4072125119
Short name T368
Test name
Test status
Simulation time 10132738692 ps
CPU time 17.03 seconds
Started Jun 06 01:50:46 PM PDT 24
Finished Jun 06 01:51:04 PM PDT 24
Peak memory 205692 kb
Host smart-1774f3c3-b9aa-4a96-bb3e-f419bce5bfd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40721
25119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.4072125119
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.949031094
Short name T319
Test name
Test status
Simulation time 10119242817 ps
CPU time 15.61 seconds
Started Jun 06 01:50:53 PM PDT 24
Finished Jun 06 01:51:09 PM PDT 24
Peak memory 205744 kb
Host smart-6e0ea4e0-53b4-4482-871b-a4b3059cea3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94903
1094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.949031094
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.1452875943
Short name T1703
Test name
Test status
Simulation time 13192854988 ps
CPU time 16.08 seconds
Started Jun 06 01:50:58 PM PDT 24
Finished Jun 06 01:51:15 PM PDT 24
Peak memory 205668 kb
Host smart-2dfc7eba-f3ae-40d9-9c71-4758425c0069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14528
75943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.1452875943
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3106886244
Short name T758
Test name
Test status
Simulation time 10087389952 ps
CPU time 14.61 seconds
Started Jun 06 01:51:01 PM PDT 24
Finished Jun 06 01:51:16 PM PDT 24
Peak memory 205652 kb
Host smart-6f99e3f9-b24d-4fe8-8078-874dbc017a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31068
86244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3106886244
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.1790760559
Short name T1808
Test name
Test status
Simulation time 18086837514 ps
CPU time 246.42 seconds
Started Jun 06 01:50:52 PM PDT 24
Finished Jun 06 01:54:59 PM PDT 24
Peak memory 205652 kb
Host smart-87e5b29f-1684-4199-a7d2-1fb416727e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17907
60559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.1790760559
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.1945987432
Short name T1953
Test name
Test status
Simulation time 10070231136 ps
CPU time 14.66 seconds
Started Jun 06 01:51:05 PM PDT 24
Finished Jun 06 01:51:21 PM PDT 24
Peak memory 205748 kb
Host smart-3c9408e1-4a9b-486d-ac67-6328f93699a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19459
87432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.1945987432
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.662069822
Short name T115
Test name
Test status
Simulation time 10128816416 ps
CPU time 15.5 seconds
Started Jun 06 01:51:00 PM PDT 24
Finished Jun 06 01:51:16 PM PDT 24
Peak memory 205760 kb
Host smart-35fdfffb-65f6-4688-942f-4126e61400e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66206
9822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.662069822
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.4203175572
Short name T88
Test name
Test status
Simulation time 10070697069 ps
CPU time 13.88 seconds
Started Jun 06 01:51:08 PM PDT 24
Finished Jun 06 01:51:23 PM PDT 24
Peak memory 205672 kb
Host smart-8e9a294c-da5b-4c86-8bf6-13f2742393bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42031
75572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.4203175572
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3023035431
Short name T920
Test name
Test status
Simulation time 10082501744 ps
CPU time 15.91 seconds
Started Jun 06 01:51:00 PM PDT 24
Finished Jun 06 01:51:17 PM PDT 24
Peak memory 205664 kb
Host smart-90d7d742-3b0b-4059-b36a-fafbaeeadbf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30230
35431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3023035431
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.1718969634
Short name T1349
Test name
Test status
Simulation time 10085337669 ps
CPU time 13.81 seconds
Started Jun 06 01:51:02 PM PDT 24
Finished Jun 06 01:51:17 PM PDT 24
Peak memory 205696 kb
Host smart-b34fa2b8-67d6-4d20-84d0-14444a929506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17189
69634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.1718969634
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.815641427
Short name T1728
Test name
Test status
Simulation time 10056971194 ps
CPU time 13.39 seconds
Started Jun 06 01:51:01 PM PDT 24
Finished Jun 06 01:51:15 PM PDT 24
Peak memory 205676 kb
Host smart-199ff040-43ef-45f7-b175-20493bde75bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81564
1427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.815641427
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_eop_single_bit_handling.1391293084
Short name T1662
Test name
Test status
Simulation time 10068113226 ps
CPU time 13.73 seconds
Started Jun 06 01:51:01 PM PDT 24
Finished Jun 06 01:51:15 PM PDT 24
Peak memory 205744 kb
Host smart-3f82e289-f319-4842-b990-ae4f61023ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13912
93084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_eop_single_bit_handling.1391293084
Directory /workspace/33.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.871139740
Short name T1481
Test name
Test status
Simulation time 10048131206 ps
CPU time 13.07 seconds
Started Jun 06 01:51:05 PM PDT 24
Finished Jun 06 01:51:19 PM PDT 24
Peak memory 205716 kb
Host smart-347c5a97-dcbb-41fe-9e1b-5b180f68c948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87113
9740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.871139740
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1149605468
Short name T25
Test name
Test status
Simulation time 10044494255 ps
CPU time 13.52 seconds
Started Jun 06 01:51:02 PM PDT 24
Finished Jun 06 01:51:16 PM PDT 24
Peak memory 205648 kb
Host smart-c023922b-a6b7-4b13-ad21-aa66eb82161d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11496
05468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1149605468
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.913045069
Short name T245
Test name
Test status
Simulation time 32804619559 ps
CPU time 66.23 seconds
Started Jun 06 01:51:01 PM PDT 24
Finished Jun 06 01:52:08 PM PDT 24
Peak memory 205684 kb
Host smart-db12cf2d-aabb-4889-a767-66e41fb9f6ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91304
5069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.913045069
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.4174910514
Short name T1193
Test name
Test status
Simulation time 10050397218 ps
CPU time 14.36 seconds
Started Jun 06 01:50:59 PM PDT 24
Finished Jun 06 01:51:14 PM PDT 24
Peak memory 205660 kb
Host smart-70267a43-c92e-4bdb-b131-1ec4adc95e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41749
10514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.4174910514
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2179438410
Short name T39
Test name
Test status
Simulation time 10083584321 ps
CPU time 13.47 seconds
Started Jun 06 01:51:01 PM PDT 24
Finished Jun 06 01:51:15 PM PDT 24
Peak memory 205728 kb
Host smart-b7f431ed-d4c8-4f3a-ad7d-6894e84d75e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21794
38410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2179438410
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.3202982615
Short name T1230
Test name
Test status
Simulation time 10071019868 ps
CPU time 15.37 seconds
Started Jun 06 01:51:01 PM PDT 24
Finished Jun 06 01:51:17 PM PDT 24
Peak memory 205764 kb
Host smart-79bf505f-64c0-4726-a972-67771d569754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32029
82615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.3202982615
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.2607372076
Short name T63
Test name
Test status
Simulation time 10062292947 ps
CPU time 13.58 seconds
Started Jun 06 01:50:52 PM PDT 24
Finished Jun 06 01:51:06 PM PDT 24
Peak memory 205724 kb
Host smart-683fdd23-716e-437e-809c-fd836df91720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26073
72076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.2607372076
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.3032919137
Short name T1386
Test name
Test status
Simulation time 10062365739 ps
CPU time 14.4 seconds
Started Jun 06 01:50:53 PM PDT 24
Finished Jun 06 01:51:08 PM PDT 24
Peak memory 205688 kb
Host smart-477bf803-f890-4ef7-9593-99973c1a3069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30329
19137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.3032919137
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3989724204
Short name T1792
Test name
Test status
Simulation time 10083898365 ps
CPU time 13.42 seconds
Started Jun 06 01:50:52 PM PDT 24
Finished Jun 06 01:51:07 PM PDT 24
Peak memory 205632 kb
Host smart-62e14a6f-cb8c-42f9-9efb-96c00c0914e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39897
24204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3989724204
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.3687902628
Short name T989
Test name
Test status
Simulation time 10107653003 ps
CPU time 14.52 seconds
Started Jun 06 01:50:42 PM PDT 24
Finished Jun 06 01:50:57 PM PDT 24
Peak memory 205756 kb
Host smart-a1491864-4e2d-4ea4-b065-46312bf1d97a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36879
02628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3687902628
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.3369892373
Short name T824
Test name
Test status
Simulation time 10131987637 ps
CPU time 13.98 seconds
Started Jun 06 01:50:52 PM PDT 24
Finished Jun 06 01:51:07 PM PDT 24
Peak memory 205728 kb
Host smart-938b35c9-32bc-4c15-8d91-cb362dd4e9b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33698
92373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.3369892373
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.456064835
Short name T972
Test name
Test status
Simulation time 22675244846 ps
CPU time 99.94 seconds
Started Jun 06 01:51:05 PM PDT 24
Finished Jun 06 01:52:46 PM PDT 24
Peak memory 205744 kb
Host smart-8a93e970-f046-46c7-bf4e-30df122e74e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45606
4835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.456064835
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.3594546237
Short name T1070
Test name
Test status
Simulation time 10171081488 ps
CPU time 13.62 seconds
Started Jun 06 01:51:03 PM PDT 24
Finished Jun 06 01:51:18 PM PDT 24
Peak memory 205688 kb
Host smart-25f84c3b-8089-4bea-b421-61c7c9037bba
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3594546237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.3594546237
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.3822577615
Short name T693
Test name
Test status
Simulation time 10059859115 ps
CPU time 14.55 seconds
Started Jun 06 01:51:04 PM PDT 24
Finished Jun 06 01:51:20 PM PDT 24
Peak memory 205604 kb
Host smart-c5259083-b52b-4dc8-80d6-b9eb8dab8496
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3822577615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.3822577615
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.3693181534
Short name T1051
Test name
Test status
Simulation time 10078218307 ps
CPU time 15.62 seconds
Started Jun 06 01:51:03 PM PDT 24
Finished Jun 06 01:51:20 PM PDT 24
Peak memory 205600 kb
Host smart-3f7ba107-00ae-41e4-9c8a-0edf73df26c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36931
81534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.3693181534
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.1515780249
Short name T1398
Test name
Test status
Simulation time 13696440124 ps
CPU time 17.65 seconds
Started Jun 06 01:51:00 PM PDT 24
Finished Jun 06 01:51:18 PM PDT 24
Peak memory 205720 kb
Host smart-3d80c102-b507-4b28-b98b-13e07b8b69a1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1515780249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.1515780249
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.504966517
Short name T2016
Test name
Test status
Simulation time 23258606176 ps
CPU time 32.17 seconds
Started Jun 06 01:51:05 PM PDT 24
Finished Jun 06 01:51:39 PM PDT 24
Peak memory 205744 kb
Host smart-bb56f3ed-97ec-4eb8-bdbd-484b21729e4d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=504966517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.504966517
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.214797910
Short name T470
Test name
Test status
Simulation time 10051696111 ps
CPU time 12.31 seconds
Started Jun 06 01:51:05 PM PDT 24
Finished Jun 06 01:51:19 PM PDT 24
Peak memory 205768 kb
Host smart-911125db-22e7-403b-b465-2fb0559fdebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21479
7910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.214797910
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.2407322749
Short name T74
Test name
Test status
Simulation time 11073426908 ps
CPU time 14.52 seconds
Started Jun 06 01:51:06 PM PDT 24
Finished Jun 06 01:51:21 PM PDT 24
Peak memory 205708 kb
Host smart-8014f137-2323-4859-919a-0b2683d683d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24073
22749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.2407322749
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.795742319
Short name T843
Test name
Test status
Simulation time 10053958576 ps
CPU time 13.37 seconds
Started Jun 06 01:51:03 PM PDT 24
Finished Jun 06 01:51:18 PM PDT 24
Peak memory 205636 kb
Host smart-d914811d-3049-4232-9838-b8ad2c038e1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79574
2319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.795742319
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.3935483596
Short name T1838
Test name
Test status
Simulation time 10051151741 ps
CPU time 12.8 seconds
Started Jun 06 01:51:03 PM PDT 24
Finished Jun 06 01:51:17 PM PDT 24
Peak memory 205592 kb
Host smart-3529c403-cdce-4c30-9bd6-6509b5cf3b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39354
83596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.3935483596
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.1670868344
Short name T2028
Test name
Test status
Simulation time 10806447534 ps
CPU time 15.37 seconds
Started Jun 06 01:51:07 PM PDT 24
Finished Jun 06 01:51:23 PM PDT 24
Peak memory 205632 kb
Host smart-210756eb-88cd-4878-8e11-547443739470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16708
68344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.1670868344
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2387674471
Short name T1659
Test name
Test status
Simulation time 10172325827 ps
CPU time 14.3 seconds
Started Jun 06 01:51:03 PM PDT 24
Finished Jun 06 01:51:18 PM PDT 24
Peak memory 205668 kb
Host smart-10c2f8ef-8776-4020-9bb6-a6d0255fb391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23876
74471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2387674471
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.2104534090
Short name T586
Test name
Test status
Simulation time 10118745067 ps
CPU time 13.42 seconds
Started Jun 06 01:51:04 PM PDT 24
Finished Jun 06 01:51:19 PM PDT 24
Peak memory 205648 kb
Host smart-41adf762-a5e5-4613-8dad-a6dc2b6ec8b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21045
34090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.2104534090
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.36406771
Short name T1759
Test name
Test status
Simulation time 10054768390 ps
CPU time 12.74 seconds
Started Jun 06 01:51:06 PM PDT 24
Finished Jun 06 01:51:20 PM PDT 24
Peak memory 205688 kb
Host smart-440f303a-2b42-4860-baac-0e18d592686d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36406
771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.36406771
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2203984959
Short name T1140
Test name
Test status
Simulation time 10049248526 ps
CPU time 12.86 seconds
Started Jun 06 01:51:01 PM PDT 24
Finished Jun 06 01:51:15 PM PDT 24
Peak memory 205716 kb
Host smart-73655d88-66b0-4faf-bbc7-1b4078b89f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22039
84959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2203984959
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.2363268577
Short name T1881
Test name
Test status
Simulation time 10144028417 ps
CPU time 14.51 seconds
Started Jun 06 01:51:01 PM PDT 24
Finished Jun 06 01:51:17 PM PDT 24
Peak memory 205760 kb
Host smart-bdca6ecc-4971-4c70-b82f-0b3389ebd2a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23632
68577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.2363268577
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.2769176605
Short name T733
Test name
Test status
Simulation time 13221091800 ps
CPU time 15.73 seconds
Started Jun 06 01:51:03 PM PDT 24
Finished Jun 06 01:51:19 PM PDT 24
Peak memory 205824 kb
Host smart-ada07cde-b8ac-40b9-a82c-11c7426f1782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27691
76605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.2769176605
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1077428439
Short name T1178
Test name
Test status
Simulation time 10104801572 ps
CPU time 13.96 seconds
Started Jun 06 01:51:04 PM PDT 24
Finished Jun 06 01:51:20 PM PDT 24
Peak memory 205808 kb
Host smart-2d61ea63-309e-4a89-b246-74295def0a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10774
28439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1077428439
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.1647437790
Short name T1155
Test name
Test status
Simulation time 14621225016 ps
CPU time 45.88 seconds
Started Jun 06 01:51:06 PM PDT 24
Finished Jun 06 01:51:53 PM PDT 24
Peak memory 205712 kb
Host smart-470727fc-4968-4f26-b400-f1306d521391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16474
37790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.1647437790
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.4118030747
Short name T1842
Test name
Test status
Simulation time 10060214871 ps
CPU time 13.94 seconds
Started Jun 06 01:51:05 PM PDT 24
Finished Jun 06 01:51:20 PM PDT 24
Peak memory 205740 kb
Host smart-08127263-d8c6-4542-976b-6150160f6e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41180
30747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.4118030747
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.3417352674
Short name T517
Test name
Test status
Simulation time 10095440455 ps
CPU time 12.96 seconds
Started Jun 06 01:51:06 PM PDT 24
Finished Jun 06 01:51:20 PM PDT 24
Peak memory 205652 kb
Host smart-c96bab94-aafd-44dd-8ce0-f9ddfeb4a039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34173
52674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.3417352674
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.1100221956
Short name T599
Test name
Test status
Simulation time 10066487067 ps
CPU time 12.28 seconds
Started Jun 06 01:51:04 PM PDT 24
Finished Jun 06 01:51:17 PM PDT 24
Peak memory 205696 kb
Host smart-18974d12-3c53-470c-8f2d-ecd78b5c3424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11002
21956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.1100221956
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.3271689912
Short name T1321
Test name
Test status
Simulation time 10058493043 ps
CPU time 15.9 seconds
Started Jun 06 01:51:05 PM PDT 24
Finished Jun 06 01:51:22 PM PDT 24
Peak memory 205692 kb
Host smart-c1e78ecb-95a3-49bc-a14d-0e6089401f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32716
89912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3271689912
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2702185241
Short name T408
Test name
Test status
Simulation time 10107586505 ps
CPU time 16.72 seconds
Started Jun 06 01:51:08 PM PDT 24
Finished Jun 06 01:51:25 PM PDT 24
Peak memory 205684 kb
Host smart-bd3802d4-c258-4305-9450-23ab74406efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27021
85241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2702185241
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2994618372
Short name T1708
Test name
Test status
Simulation time 10089012363 ps
CPU time 13.02 seconds
Started Jun 06 01:51:01 PM PDT 24
Finished Jun 06 01:51:15 PM PDT 24
Peak memory 205748 kb
Host smart-6eb5fce8-dcad-4726-8a0e-e56b44c6370b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29946
18372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2994618372
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_eop_single_bit_handling.3071628436
Short name T1732
Test name
Test status
Simulation time 10058602696 ps
CPU time 13.81 seconds
Started Jun 06 01:51:04 PM PDT 24
Finished Jun 06 01:51:19 PM PDT 24
Peak memory 205672 kb
Host smart-834f276f-1c28-40c9-975e-4a9a60897de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30716
28436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_eop_single_bit_handling.3071628436
Directory /workspace/34.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.4204719702
Short name T1978
Test name
Test status
Simulation time 10044888250 ps
CPU time 12.94 seconds
Started Jun 06 01:51:06 PM PDT 24
Finished Jun 06 01:51:20 PM PDT 24
Peak memory 205552 kb
Host smart-a1adbd96-f1da-499e-9c50-3607f295d2cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42047
19702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.4204719702
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.1843405631
Short name T1880
Test name
Test status
Simulation time 10040582378 ps
CPU time 14.61 seconds
Started Jun 06 01:51:07 PM PDT 24
Finished Jun 06 01:51:22 PM PDT 24
Peak memory 205624 kb
Host smart-9e599907-d65d-4ed9-aea2-aac43b424156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18434
05631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.1843405631
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.2889097406
Short name T2021
Test name
Test status
Simulation time 19457570132 ps
CPU time 33.18 seconds
Started Jun 06 01:51:04 PM PDT 24
Finished Jun 06 01:51:39 PM PDT 24
Peak memory 205676 kb
Host smart-481e2948-cc60-426a-b3ff-46dc25674dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28890
97406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.2889097406
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.3914441927
Short name T1743
Test name
Test status
Simulation time 10083669211 ps
CPU time 12.5 seconds
Started Jun 06 01:51:04 PM PDT 24
Finished Jun 06 01:51:17 PM PDT 24
Peak memory 205708 kb
Host smart-69cd53b0-9377-4712-8b3a-30052c1f1e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39144
41927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.3914441927
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.3376928829
Short name T590
Test name
Test status
Simulation time 10078523356 ps
CPU time 13.82 seconds
Started Jun 06 01:51:05 PM PDT 24
Finished Jun 06 01:51:21 PM PDT 24
Peak memory 205748 kb
Host smart-0a386eb4-bfbf-44b6-8f6e-4770b8a4d035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33769
28829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.3376928829
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.1691766114
Short name T1282
Test name
Test status
Simulation time 10080152845 ps
CPU time 14.83 seconds
Started Jun 06 01:51:06 PM PDT 24
Finished Jun 06 01:51:22 PM PDT 24
Peak memory 205748 kb
Host smart-62d5fd23-dfc9-4b9c-8f88-1ddb2ca88f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16917
66114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.1691766114
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.2233219560
Short name T1163
Test name
Test status
Simulation time 10062621374 ps
CPU time 14.84 seconds
Started Jun 06 01:51:05 PM PDT 24
Finished Jun 06 01:51:21 PM PDT 24
Peak memory 205704 kb
Host smart-c09cef4a-30bf-422c-9831-c410b70d8489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22332
19560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.2233219560
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.1033714771
Short name T1893
Test name
Test status
Simulation time 10042573569 ps
CPU time 13.33 seconds
Started Jun 06 01:51:00 PM PDT 24
Finished Jun 06 01:51:14 PM PDT 24
Peak memory 205736 kb
Host smart-876f0741-3e9e-4387-b526-43d4722bfff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10337
14771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.1033714771
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.3265204885
Short name T1443
Test name
Test status
Simulation time 10084426360 ps
CPU time 12.95 seconds
Started Jun 06 01:51:03 PM PDT 24
Finished Jun 06 01:51:17 PM PDT 24
Peak memory 205648 kb
Host smart-42ac4dc4-3978-43ac-a22a-198ab1c4d25f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32652
04885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.3265204885
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.4170089163
Short name T1078
Test name
Test status
Simulation time 10149775455 ps
CPU time 14.48 seconds
Started Jun 06 01:51:02 PM PDT 24
Finished Jun 06 01:51:17 PM PDT 24
Peak memory 205616 kb
Host smart-8f4f6153-748c-4b40-80d6-e39c5afbf104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41700
89163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.4170089163
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.1356198823
Short name T1469
Test name
Test status
Simulation time 10092390335 ps
CPU time 15.14 seconds
Started Jun 06 01:51:03 PM PDT 24
Finished Jun 06 01:51:19 PM PDT 24
Peak memory 205704 kb
Host smart-4d1a70b0-a24e-4010-add6-2b95d2de3923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13561
98823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.1356198823
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.3422824858
Short name T883
Test name
Test status
Simulation time 10074472167 ps
CPU time 13.08 seconds
Started Jun 06 01:51:06 PM PDT 24
Finished Jun 06 01:51:21 PM PDT 24
Peak memory 205516 kb
Host smart-abc7570c-e393-4bd1-87a6-cd05500a9b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34228
24858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.3422824858
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.3565569092
Short name T647
Test name
Test status
Simulation time 23401196329 ps
CPU time 139.71 seconds
Started Jun 06 01:51:03 PM PDT 24
Finished Jun 06 01:53:25 PM PDT 24
Peak memory 205676 kb
Host smart-be05ec37-bc01-4614-a853-34e7f6071810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35655
69092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.3565569092
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.2296916807
Short name T1973
Test name
Test status
Simulation time 10146168412 ps
CPU time 15.53 seconds
Started Jun 06 01:51:12 PM PDT 24
Finished Jun 06 01:51:28 PM PDT 24
Peak memory 205744 kb
Host smart-c1f8084c-0741-4a19-8a7d-a72e59f96461
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2296916807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.2296916807
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.582566459
Short name T308
Test name
Test status
Simulation time 10079780839 ps
CPU time 13.48 seconds
Started Jun 06 01:51:12 PM PDT 24
Finished Jun 06 01:51:26 PM PDT 24
Peak memory 205724 kb
Host smart-52b8f5fc-c92f-4c5c-a50d-9cb888c91dc2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=582566459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.582566459
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.1293566317
Short name T1675
Test name
Test status
Simulation time 10096003299 ps
CPU time 13.16 seconds
Started Jun 06 01:51:26 PM PDT 24
Finished Jun 06 01:51:40 PM PDT 24
Peak memory 205564 kb
Host smart-8c7124e8-5b80-4a3e-b20c-d269cba4aeb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12935
66317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.1293566317
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.3060459821
Short name T829
Test name
Test status
Simulation time 13303881931 ps
CPU time 17.99 seconds
Started Jun 06 01:51:06 PM PDT 24
Finished Jun 06 01:51:25 PM PDT 24
Peak memory 205660 kb
Host smart-60410bd1-7422-41bf-b42e-9b46bc9a4abb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3060459821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.3060459821
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.3800412337
Short name T652
Test name
Test status
Simulation time 23311191512 ps
CPU time 25.94 seconds
Started Jun 06 01:51:03 PM PDT 24
Finished Jun 06 01:51:30 PM PDT 24
Peak memory 205628 kb
Host smart-283eda9e-0f7b-4de3-9eb1-718c92f58841
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3800412337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.3800412337
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.3720082886
Short name T903
Test name
Test status
Simulation time 10085784779 ps
CPU time 13.37 seconds
Started Jun 06 01:51:07 PM PDT 24
Finished Jun 06 01:51:22 PM PDT 24
Peak memory 205692 kb
Host smart-bd0a5ecb-868b-4e19-96a9-aaaa6851a499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37200
82886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.3720082886
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.2824053437
Short name T1194
Test name
Test status
Simulation time 10043273266 ps
CPU time 13.47 seconds
Started Jun 06 01:51:07 PM PDT 24
Finished Jun 06 01:51:21 PM PDT 24
Peak memory 205772 kb
Host smart-7550486a-b2e2-4b40-8e12-52d499f40452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28240
53437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.2824053437
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.3160450064
Short name T1889
Test name
Test status
Simulation time 10752468072 ps
CPU time 15.27 seconds
Started Jun 06 01:51:07 PM PDT 24
Finished Jun 06 01:51:23 PM PDT 24
Peak memory 205756 kb
Host smart-ba3eca4d-14e8-48db-b80e-46a4457ebdda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31604
50064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.3160450064
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.1649241809
Short name T428
Test name
Test status
Simulation time 10038256874 ps
CPU time 13.22 seconds
Started Jun 06 01:51:26 PM PDT 24
Finished Jun 06 01:51:40 PM PDT 24
Peak memory 205568 kb
Host smart-b2cd19b0-fd9b-47df-bb82-b7acc8d7f791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16492
41809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.1649241809
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.3421684238
Short name T1806
Test name
Test status
Simulation time 10058555559 ps
CPU time 14.49 seconds
Started Jun 06 01:51:04 PM PDT 24
Finished Jun 06 01:51:19 PM PDT 24
Peak memory 205624 kb
Host smart-cde942ba-0e70-4cf1-8e19-eacef6fc5b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34216
84238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.3421684238
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.1227002960
Short name T1678
Test name
Test status
Simulation time 10690160881 ps
CPU time 17.59 seconds
Started Jun 06 01:51:06 PM PDT 24
Finished Jun 06 01:51:24 PM PDT 24
Peak memory 205696 kb
Host smart-1ab5d585-8c70-43df-9922-38126873111e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12270
02960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.1227002960
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1476476004
Short name T1348
Test name
Test status
Simulation time 10084806743 ps
CPU time 14.62 seconds
Started Jun 06 01:51:04 PM PDT 24
Finished Jun 06 01:51:20 PM PDT 24
Peak memory 205596 kb
Host smart-a07882f0-e2e9-480a-8fcb-40a01cb79c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14764
76004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1476476004
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.3477532409
Short name T1564
Test name
Test status
Simulation time 10156881349 ps
CPU time 13.89 seconds
Started Jun 06 01:51:10 PM PDT 24
Finished Jun 06 01:51:24 PM PDT 24
Peak memory 205692 kb
Host smart-b5ac077a-e4eb-4d4b-aae6-29eb31ab24de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34775
32409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.3477532409
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.2046467962
Short name T710
Test name
Test status
Simulation time 10043934245 ps
CPU time 14.16 seconds
Started Jun 06 01:51:11 PM PDT 24
Finished Jun 06 01:51:26 PM PDT 24
Peak memory 205612 kb
Host smart-11813bd5-ffca-4d36-a10e-8d577276e0b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20464
67962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.2046467962
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3679746987
Short name T2023
Test name
Test status
Simulation time 10111443531 ps
CPU time 13.2 seconds
Started Jun 06 01:51:06 PM PDT 24
Finished Jun 06 01:51:20 PM PDT 24
Peak memory 205732 kb
Host smart-3fa5bb74-c255-4577-a1bc-f5072b3ab849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36797
46987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3679746987
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.2744384216
Short name T1072
Test name
Test status
Simulation time 10125251965 ps
CPU time 13.13 seconds
Started Jun 06 01:51:06 PM PDT 24
Finished Jun 06 01:51:20 PM PDT 24
Peak memory 205764 kb
Host smart-81408185-b887-400d-810b-3a7b2092043d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27443
84216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.2744384216
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.4294172654
Short name T939
Test name
Test status
Simulation time 13174105833 ps
CPU time 16.78 seconds
Started Jun 06 01:51:06 PM PDT 24
Finished Jun 06 01:51:24 PM PDT 24
Peak memory 205656 kb
Host smart-130ae3ea-960e-42bc-8828-0d5c7ac5f335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42941
72654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.4294172654
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.462292086
Short name T530
Test name
Test status
Simulation time 10093724556 ps
CPU time 13.16 seconds
Started Jun 06 01:51:12 PM PDT 24
Finished Jun 06 01:51:25 PM PDT 24
Peak memory 205740 kb
Host smart-10b7836a-a607-4114-89e2-37ccad11c625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46229
2086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.462292086
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.3417112774
Short name T1733
Test name
Test status
Simulation time 25215744714 ps
CPU time 160.2 seconds
Started Jun 06 01:51:10 PM PDT 24
Finished Jun 06 01:53:51 PM PDT 24
Peak memory 205664 kb
Host smart-6c556f02-7562-4853-97ff-774d584a7866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34171
12774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.3417112774
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.3686893595
Short name T1445
Test name
Test status
Simulation time 10084335453 ps
CPU time 13.28 seconds
Started Jun 06 01:51:11 PM PDT 24
Finished Jun 06 01:51:25 PM PDT 24
Peak memory 205724 kb
Host smart-0ff02f7e-3e61-4bac-97c6-b680586ac214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36868
93595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.3686893595
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.475509125
Short name T122
Test name
Test status
Simulation time 10080187151 ps
CPU time 14.13 seconds
Started Jun 06 01:51:12 PM PDT 24
Finished Jun 06 01:51:27 PM PDT 24
Peak memory 205652 kb
Host smart-b1dbecc1-a16d-4f9b-9784-37127bbbd266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47550
9125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.475509125
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.1175228877
Short name T650
Test name
Test status
Simulation time 10069830453 ps
CPU time 12.58 seconds
Started Jun 06 01:51:19 PM PDT 24
Finished Jun 06 01:51:33 PM PDT 24
Peak memory 205680 kb
Host smart-34a9819d-f18a-42a6-8fb9-5c36997251a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11752
28877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.1175228877
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.452820934
Short name T1345
Test name
Test status
Simulation time 10087439717 ps
CPU time 15.49 seconds
Started Jun 06 01:51:19 PM PDT 24
Finished Jun 06 01:51:35 PM PDT 24
Peak memory 205732 kb
Host smart-456cb2eb-796b-4419-ae33-677681d7c50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45282
0934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.452820934
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3175092053
Short name T455
Test name
Test status
Simulation time 10057298400 ps
CPU time 14.51 seconds
Started Jun 06 01:51:12 PM PDT 24
Finished Jun 06 01:51:28 PM PDT 24
Peak memory 205636 kb
Host smart-f2506f86-8d4d-4cf8-bfff-8ea8f33c7a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31750
92053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3175092053
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.957867957
Short name T613
Test name
Test status
Simulation time 10137645824 ps
CPU time 14.05 seconds
Started Jun 06 01:51:11 PM PDT 24
Finished Jun 06 01:51:26 PM PDT 24
Peak memory 205688 kb
Host smart-4de903e5-a0a8-4c1d-852c-6e18297eefaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95786
7957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.957867957
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_eop_single_bit_handling.2938862462
Short name T1091
Test name
Test status
Simulation time 10080270106 ps
CPU time 13.18 seconds
Started Jun 06 01:51:14 PM PDT 24
Finished Jun 06 01:51:27 PM PDT 24
Peak memory 205740 kb
Host smart-80bee00c-b4af-4189-8315-78f2807750d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29388
62462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_eop_single_bit_handling.2938862462
Directory /workspace/35.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.1277779653
Short name T587
Test name
Test status
Simulation time 10051580084 ps
CPU time 14.06 seconds
Started Jun 06 01:51:14 PM PDT 24
Finished Jun 06 01:51:29 PM PDT 24
Peak memory 205732 kb
Host smart-83f8fc22-4adb-49e4-812e-1b08fdc0a7e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12777
79653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.1277779653
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.4154340401
Short name T1075
Test name
Test status
Simulation time 10048903503 ps
CPU time 15.84 seconds
Started Jun 06 01:51:19 PM PDT 24
Finished Jun 06 01:51:36 PM PDT 24
Peak memory 205552 kb
Host smart-6027ff74-40df-46d5-b42e-7fa00f270248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41543
40401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.4154340401
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.2509127224
Short name T1130
Test name
Test status
Simulation time 16298337548 ps
CPU time 27.82 seconds
Started Jun 06 01:51:10 PM PDT 24
Finished Jun 06 01:51:38 PM PDT 24
Peak memory 205632 kb
Host smart-ffc9687f-3bff-4984-a1dc-9e3f3dae564a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25091
27224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.2509127224
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.2339632542
Short name T1033
Test name
Test status
Simulation time 10057643503 ps
CPU time 13.41 seconds
Started Jun 06 01:51:09 PM PDT 24
Finished Jun 06 01:51:23 PM PDT 24
Peak memory 205628 kb
Host smart-f8851e04-7f76-4db5-ab66-60ea4765864d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23396
32542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.2339632542
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2459099145
Short name T795
Test name
Test status
Simulation time 10122718504 ps
CPU time 15.26 seconds
Started Jun 06 01:51:08 PM PDT 24
Finished Jun 06 01:51:24 PM PDT 24
Peak memory 205724 kb
Host smart-227c0450-2053-4604-b8cd-7685a360fb49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24590
99145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2459099145
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.3725455084
Short name T1176
Test name
Test status
Simulation time 10076158054 ps
CPU time 13.42 seconds
Started Jun 06 01:51:18 PM PDT 24
Finished Jun 06 01:51:33 PM PDT 24
Peak memory 205768 kb
Host smart-f78b31b2-3808-43a7-addc-3949d36314e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37254
55084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.3725455084
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.272450808
Short name T1551
Test name
Test status
Simulation time 10053910485 ps
CPU time 13.9 seconds
Started Jun 06 01:51:18 PM PDT 24
Finished Jun 06 01:51:33 PM PDT 24
Peak memory 205700 kb
Host smart-749c08e4-3669-4241-b28f-c330e5dc519a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27245
0808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.272450808
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.162539174
Short name T1519
Test name
Test status
Simulation time 10060115846 ps
CPU time 16.51 seconds
Started Jun 06 01:51:12 PM PDT 24
Finished Jun 06 01:51:29 PM PDT 24
Peak memory 205736 kb
Host smart-1430c073-0509-4944-a294-de6d4758e252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16253
9174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.162539174
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2708656539
Short name T1172
Test name
Test status
Simulation time 10099414486 ps
CPU time 13.65 seconds
Started Jun 06 01:51:12 PM PDT 24
Finished Jun 06 01:51:27 PM PDT 24
Peak memory 205692 kb
Host smart-ee26772d-b614-410d-b0fe-0509c65913f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27086
56539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2708656539
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.1325057713
Short name T1397
Test name
Test status
Simulation time 10137321220 ps
CPU time 17.23 seconds
Started Jun 06 01:51:06 PM PDT 24
Finished Jun 06 01:51:25 PM PDT 24
Peak memory 205684 kb
Host smart-255aa9a7-1edd-4d24-9d93-6c7d11918c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13250
57713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.1325057713
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.1724528448
Short name T1462
Test name
Test status
Simulation time 10064451710 ps
CPU time 13.12 seconds
Started Jun 06 01:51:18 PM PDT 24
Finished Jun 06 01:51:33 PM PDT 24
Peak memory 205736 kb
Host smart-8bbd585c-c719-45e4-a6f2-9feea4c09699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17245
28448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.1724528448
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.2279102751
Short name T987
Test name
Test status
Simulation time 10070915971 ps
CPU time 14.14 seconds
Started Jun 06 01:51:11 PM PDT 24
Finished Jun 06 01:51:26 PM PDT 24
Peak memory 205768 kb
Host smart-6fe9c6d8-791f-4aa8-9212-77f42618c29d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22791
02751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.2279102751
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.2781715300
Short name T1174
Test name
Test status
Simulation time 15228412931 ps
CPU time 60.97 seconds
Started Jun 06 01:51:24 PM PDT 24
Finished Jun 06 01:52:26 PM PDT 24
Peak memory 205680 kb
Host smart-95d3e23e-6f7b-4bff-a35d-daf9c248d9d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27817
15300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.2781715300
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.32298620
Short name T1354
Test name
Test status
Simulation time 10142716000 ps
CPU time 13.63 seconds
Started Jun 06 01:51:32 PM PDT 24
Finished Jun 06 01:51:47 PM PDT 24
Peak memory 205740 kb
Host smart-1f1127e2-5268-4a63-985d-14e4b3469333
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=32298620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.32298620
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.2436755489
Short name T813
Test name
Test status
Simulation time 10076163657 ps
CPU time 14.34 seconds
Started Jun 06 01:51:30 PM PDT 24
Finished Jun 06 01:51:45 PM PDT 24
Peak memory 205620 kb
Host smart-35894fe5-e53f-4ee2-88af-898f5383fd4b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2436755489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.2436755489
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.3636331789
Short name T732
Test name
Test status
Simulation time 10109634566 ps
CPU time 13.01 seconds
Started Jun 06 01:51:28 PM PDT 24
Finished Jun 06 01:51:42 PM PDT 24
Peak memory 205564 kb
Host smart-52d6e4b1-be9e-4974-9700-73e6446cbbad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36363
31789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.3636331789
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.2758581900
Short name T1952
Test name
Test status
Simulation time 14299073556 ps
CPU time 17.09 seconds
Started Jun 06 01:51:08 PM PDT 24
Finished Jun 06 01:51:26 PM PDT 24
Peak memory 205724 kb
Host smart-8adf2da7-3cbb-41ea-9549-6f0dcfc43112
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2758581900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.2758581900
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.3746428392
Short name T932
Test name
Test status
Simulation time 23258926638 ps
CPU time 23.49 seconds
Started Jun 06 01:51:24 PM PDT 24
Finished Jun 06 01:51:48 PM PDT 24
Peak memory 205680 kb
Host smart-adc9939d-a5db-4f28-a6c3-2e947d85b3db
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3746428392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.3746428392
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.2358284620
Short name T1420
Test name
Test status
Simulation time 10048236436 ps
CPU time 14.75 seconds
Started Jun 06 01:51:10 PM PDT 24
Finished Jun 06 01:51:26 PM PDT 24
Peak memory 205996 kb
Host smart-8dde2fef-7940-4af7-a35c-34aa52e3c9c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23582
84620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.2358284620
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.3434964898
Short name T170
Test name
Test status
Simulation time 10912478260 ps
CPU time 14.58 seconds
Started Jun 06 01:51:25 PM PDT 24
Finished Jun 06 01:51:40 PM PDT 24
Peak memory 205604 kb
Host smart-0627fe56-c70d-4734-8386-fe035bfc7c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34349
64898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.3434964898
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.1334767750
Short name T1518
Test name
Test status
Simulation time 10083714420 ps
CPU time 13.3 seconds
Started Jun 06 01:51:18 PM PDT 24
Finished Jun 06 01:51:32 PM PDT 24
Peak memory 205780 kb
Host smart-28ae7605-7b3d-4f03-837a-f6db96c8ff42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13347
67750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.1334767750
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.3803313030
Short name T1473
Test name
Test status
Simulation time 10061161383 ps
CPU time 13.28 seconds
Started Jun 06 01:51:20 PM PDT 24
Finished Jun 06 01:51:34 PM PDT 24
Peak memory 205644 kb
Host smart-ffe8429e-fe87-46e7-a238-c08c907e92f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38033
13030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3803313030
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.2935936157
Short name T1788
Test name
Test status
Simulation time 10775155845 ps
CPU time 14.53 seconds
Started Jun 06 01:51:26 PM PDT 24
Finished Jun 06 01:51:41 PM PDT 24
Peak memory 205604 kb
Host smart-84d5da08-cde8-4fee-86ee-112fc90a5ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29359
36157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.2935936157
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.184040008
Short name T93
Test name
Test status
Simulation time 10109836137 ps
CPU time 15.98 seconds
Started Jun 06 01:51:21 PM PDT 24
Finished Jun 06 01:51:38 PM PDT 24
Peak memory 205660 kb
Host smart-ee62e3cc-7759-4a54-a3da-f6dce68e9bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18404
0008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.184040008
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.1363200538
Short name T702
Test name
Test status
Simulation time 10145609848 ps
CPU time 13.93 seconds
Started Jun 06 01:51:19 PM PDT 24
Finished Jun 06 01:51:35 PM PDT 24
Peak memory 205608 kb
Host smart-b2d4ef02-61b1-4079-b846-5da44cd17bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13632
00538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.1363200538
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.877127734
Short name T1429
Test name
Test status
Simulation time 10128951071 ps
CPU time 14.82 seconds
Started Jun 06 01:51:17 PM PDT 24
Finished Jun 06 01:51:33 PM PDT 24
Peak memory 205688 kb
Host smart-d971db30-db69-437d-aa58-a17d280efdac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87712
7734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.877127734
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.3026951520
Short name T1730
Test name
Test status
Simulation time 10070438687 ps
CPU time 14.57 seconds
Started Jun 06 01:51:18 PM PDT 24
Finished Jun 06 01:51:34 PM PDT 24
Peak memory 205768 kb
Host smart-0174029f-2298-4a6f-831e-a9c6d9268983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30269
51520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.3026951520
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.1198817709
Short name T1873
Test name
Test status
Simulation time 10091815746 ps
CPU time 13.18 seconds
Started Jun 06 01:51:21 PM PDT 24
Finished Jun 06 01:51:35 PM PDT 24
Peak memory 205716 kb
Host smart-19e80e6b-0f73-439c-927e-c6fa20620e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11988
17709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.1198817709
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.1009242578
Short name T971
Test name
Test status
Simulation time 13256999427 ps
CPU time 19.93 seconds
Started Jun 06 01:51:18 PM PDT 24
Finished Jun 06 01:51:39 PM PDT 24
Peak memory 205716 kb
Host smart-19f76b5c-b29f-41ef-83a0-76e60bf64d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10092
42578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.1009242578
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.4134296309
Short name T776
Test name
Test status
Simulation time 10095153085 ps
CPU time 13.26 seconds
Started Jun 06 01:51:19 PM PDT 24
Finished Jun 06 01:51:34 PM PDT 24
Peak memory 205748 kb
Host smart-df754b6e-b4e9-4c13-a198-9018ba314413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41342
96309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.4134296309
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.314714664
Short name T771
Test name
Test status
Simulation time 20473493515 ps
CPU time 116.15 seconds
Started Jun 06 01:51:20 PM PDT 24
Finished Jun 06 01:53:17 PM PDT 24
Peak memory 205696 kb
Host smart-b0fafc45-0b74-4878-acdb-c6b1ea4aac48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31471
4664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.314714664
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3073456142
Short name T666
Test name
Test status
Simulation time 10049662581 ps
CPU time 14.72 seconds
Started Jun 06 01:51:20 PM PDT 24
Finished Jun 06 01:51:36 PM PDT 24
Peak memory 205764 kb
Host smart-dec1b128-ed01-4f23-88c4-8abffac9b263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30734
56142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3073456142
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.2650810324
Short name T125
Test name
Test status
Simulation time 10141298802 ps
CPU time 16.31 seconds
Started Jun 06 01:51:26 PM PDT 24
Finished Jun 06 01:51:43 PM PDT 24
Peak memory 205644 kb
Host smart-64c59c4f-6b9b-4930-880f-294a20f8fc78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26508
10324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.2650810324
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3371338771
Short name T961
Test name
Test status
Simulation time 10169358540 ps
CPU time 16.65 seconds
Started Jun 06 01:51:26 PM PDT 24
Finished Jun 06 01:51:44 PM PDT 24
Peak memory 205680 kb
Host smart-06749377-8659-473c-86bb-9d0345ac5ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33713
38771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3371338771
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.2567730525
Short name T1979
Test name
Test status
Simulation time 10050136859 ps
CPU time 15.08 seconds
Started Jun 06 01:51:23 PM PDT 24
Finished Jun 06 01:51:39 PM PDT 24
Peak memory 205764 kb
Host smart-3caa4fae-5e38-4dba-b141-fe607e3d3967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25677
30525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.2567730525
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1230115858
Short name T1234
Test name
Test status
Simulation time 10169261203 ps
CPU time 14.37 seconds
Started Jun 06 01:51:20 PM PDT 24
Finished Jun 06 01:51:36 PM PDT 24
Peak memory 205620 kb
Host smart-f834665c-8d5c-45d1-b999-5fd8f9eea63d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12301
15858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1230115858
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.1456074004
Short name T588
Test name
Test status
Simulation time 10061967102 ps
CPU time 13.81 seconds
Started Jun 06 01:51:21 PM PDT 24
Finished Jun 06 01:51:35 PM PDT 24
Peak memory 205672 kb
Host smart-a86816aa-daab-4759-b99d-c0a7d416a5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14560
74004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1456074004
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_eop_single_bit_handling.618915379
Short name T786
Test name
Test status
Simulation time 10106634337 ps
CPU time 14.96 seconds
Started Jun 06 01:51:25 PM PDT 24
Finished Jun 06 01:51:41 PM PDT 24
Peak memory 205728 kb
Host smart-13a64d73-8148-43fa-a514-636260cad7c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61891
5379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_eop_single_bit_handling.618915379
Directory /workspace/36.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.1232005107
Short name T507
Test name
Test status
Simulation time 10049023747 ps
CPU time 14.11 seconds
Started Jun 06 01:51:23 PM PDT 24
Finished Jun 06 01:51:38 PM PDT 24
Peak memory 206008 kb
Host smart-0dfe8ec2-3d87-4519-b172-10bd4288167e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12320
05107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.1232005107
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.911587588
Short name T27
Test name
Test status
Simulation time 10060160191 ps
CPU time 13.81 seconds
Started Jun 06 01:51:19 PM PDT 24
Finished Jun 06 01:51:34 PM PDT 24
Peak memory 205640 kb
Host smart-200f9f1e-75c8-4819-92ec-1566928b377e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91158
7588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.911587588
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3890086391
Short name T244
Test name
Test status
Simulation time 27132216853 ps
CPU time 55.23 seconds
Started Jun 06 01:51:19 PM PDT 24
Finished Jun 06 01:52:15 PM PDT 24
Peak memory 205632 kb
Host smart-cca8e81d-3ed2-4f75-984b-1a23c67ecfad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38900
86391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3890086391
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.553510345
Short name T857
Test name
Test status
Simulation time 10065666082 ps
CPU time 14.05 seconds
Started Jun 06 01:51:23 PM PDT 24
Finished Jun 06 01:51:37 PM PDT 24
Peak memory 206012 kb
Host smart-c5f72ece-f190-47cc-a348-d8bccd61a9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55351
0345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.553510345
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.2561735716
Short name T1605
Test name
Test status
Simulation time 10090589526 ps
CPU time 13.07 seconds
Started Jun 06 01:51:17 PM PDT 24
Finished Jun 06 01:51:32 PM PDT 24
Peak memory 205772 kb
Host smart-3db03186-6b81-4c69-946d-69c5026cf88d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25617
35716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.2561735716
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.113239327
Short name T657
Test name
Test status
Simulation time 10085643555 ps
CPU time 13.21 seconds
Started Jun 06 01:51:20 PM PDT 24
Finished Jun 06 01:51:35 PM PDT 24
Peak memory 205648 kb
Host smart-3a7f4e08-e9cc-4f48-b561-6e7d1d604835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11323
9327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.113239327
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.1877370347
Short name T1745
Test name
Test status
Simulation time 10043803603 ps
CPU time 13.39 seconds
Started Jun 06 01:51:21 PM PDT 24
Finished Jun 06 01:51:35 PM PDT 24
Peak memory 205720 kb
Host smart-9bb29343-653b-4daa-87a5-04660a783548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18773
70347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.1877370347
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.631467956
Short name T520
Test name
Test status
Simulation time 10049442826 ps
CPU time 13.27 seconds
Started Jun 06 01:51:22 PM PDT 24
Finished Jun 06 01:51:36 PM PDT 24
Peak memory 205752 kb
Host smart-c899d375-8796-4419-8148-fbf9b560427d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63146
7956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.631467956
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.75087392
Short name T884
Test name
Test status
Simulation time 10057652237 ps
CPU time 15.73 seconds
Started Jun 06 01:51:23 PM PDT 24
Finished Jun 06 01:51:40 PM PDT 24
Peak memory 205660 kb
Host smart-31488744-6a1f-4570-bbb5-631095fb9f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75087
392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.75087392
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.759069240
Short name T2022
Test name
Test status
Simulation time 10131806462 ps
CPU time 13.1 seconds
Started Jun 06 01:51:26 PM PDT 24
Finished Jun 06 01:51:40 PM PDT 24
Peak memory 205596 kb
Host smart-9b7741eb-efc9-4e95-ba5a-28dacff18255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75906
9240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.759069240
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.359982903
Short name T331
Test name
Test status
Simulation time 10076552303 ps
CPU time 13.5 seconds
Started Jun 06 01:51:18 PM PDT 24
Finished Jun 06 01:51:33 PM PDT 24
Peak memory 205724 kb
Host smart-60d74347-9bda-4da9-9926-f7ed2eb9e76a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35998
2903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.359982903
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.3600228226
Short name T1054
Test name
Test status
Simulation time 10054212884 ps
CPU time 13.48 seconds
Started Jun 06 01:51:22 PM PDT 24
Finished Jun 06 01:51:36 PM PDT 24
Peak memory 205704 kb
Host smart-65a48fc9-0218-479a-9432-eecc36c92b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36002
28226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.3600228226
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.2609804841
Short name T237
Test name
Test status
Simulation time 15564545556 ps
CPU time 52.34 seconds
Started Jun 06 01:51:17 PM PDT 24
Finished Jun 06 01:52:10 PM PDT 24
Peak memory 205752 kb
Host smart-f191bb4d-a092-40d4-a5e1-e24c62df839e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26098
04841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.2609804841
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.1556201322
Short name T393
Test name
Test status
Simulation time 10141171743 ps
CPU time 17.8 seconds
Started Jun 06 01:51:41 PM PDT 24
Finished Jun 06 01:52:01 PM PDT 24
Peak memory 205640 kb
Host smart-9b4f64b3-38f5-432e-bcbc-fd70cd1caaee
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1556201322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.1556201322
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.659675683
Short name T1616
Test name
Test status
Simulation time 10071511145 ps
CPU time 14.7 seconds
Started Jun 06 01:51:38 PM PDT 24
Finished Jun 06 01:51:54 PM PDT 24
Peak memory 205772 kb
Host smart-e6636159-9c5d-4296-a288-a12f640bbbc2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=659675683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.659675683
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.3375735098
Short name T1284
Test name
Test status
Simulation time 10128333824 ps
CPU time 13.95 seconds
Started Jun 06 01:51:42 PM PDT 24
Finished Jun 06 01:51:58 PM PDT 24
Peak memory 205284 kb
Host smart-e049b9a2-b3da-4fca-9dcd-f1f0d578ba12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33757
35098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.3375735098
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.2776485417
Short name T606
Test name
Test status
Simulation time 14121115179 ps
CPU time 18.24 seconds
Started Jun 06 01:51:35 PM PDT 24
Finished Jun 06 01:51:53 PM PDT 24
Peak memory 205716 kb
Host smart-bf275e11-0bef-4da2-8f82-d08cff3b4a52
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2776485417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.2776485417
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.3926841263
Short name T1531
Test name
Test status
Simulation time 23258943256 ps
CPU time 24.9 seconds
Started Jun 06 01:51:30 PM PDT 24
Finished Jun 06 01:51:56 PM PDT 24
Peak memory 205600 kb
Host smart-ea0b15c6-c2df-4f4e-9d12-633c1b8bfc75
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3926841263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.3926841263
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3824589496
Short name T1212
Test name
Test status
Simulation time 10102229326 ps
CPU time 13.37 seconds
Started Jun 06 01:51:30 PM PDT 24
Finished Jun 06 01:51:44 PM PDT 24
Peak memory 205996 kb
Host smart-33ece929-a8cf-474f-911f-377d59fd8605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38245
89496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3824589496
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.3750376584
Short name T1656
Test name
Test status
Simulation time 10196415024 ps
CPU time 14.71 seconds
Started Jun 06 01:51:29 PM PDT 24
Finished Jun 06 01:51:44 PM PDT 24
Peak memory 205660 kb
Host smart-88d35970-90ea-4a35-a6d4-b02bc1228466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37503
76584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.3750376584
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.3728193523
Short name T956
Test name
Test status
Simulation time 10045548582 ps
CPU time 16.06 seconds
Started Jun 06 01:51:29 PM PDT 24
Finished Jun 06 01:51:46 PM PDT 24
Peak memory 205664 kb
Host smart-c1f20362-c684-4ed8-a0bb-587576526320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37281
93523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.3728193523
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.992666166
Short name T698
Test name
Test status
Simulation time 10105563940 ps
CPU time 14.13 seconds
Started Jun 06 01:51:33 PM PDT 24
Finished Jun 06 01:51:48 PM PDT 24
Peak memory 205680 kb
Host smart-abc72ee9-3656-4f0c-8f35-76574b792241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99266
6166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.992666166
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.3509151883
Short name T521
Test name
Test status
Simulation time 10799220673 ps
CPU time 15.12 seconds
Started Jun 06 01:51:32 PM PDT 24
Finished Jun 06 01:51:48 PM PDT 24
Peak memory 205696 kb
Host smart-57e3a754-0e72-40da-9f71-d0395cd9d735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35091
51883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.3509151883
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.970042303
Short name T1713
Test name
Test status
Simulation time 10069898700 ps
CPU time 13.48 seconds
Started Jun 06 01:51:34 PM PDT 24
Finished Jun 06 01:51:48 PM PDT 24
Peak memory 205644 kb
Host smart-38287ed5-d601-4a51-9d01-ba951ccd3128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97004
2303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.970042303
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.721450534
Short name T940
Test name
Test status
Simulation time 10104315375 ps
CPU time 13.05 seconds
Started Jun 06 01:51:43 PM PDT 24
Finished Jun 06 01:51:59 PM PDT 24
Peak memory 205784 kb
Host smart-96bf040b-9bc3-40c2-b030-7cc1f32ccecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72145
0534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.721450534
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.2993118748
Short name T1329
Test name
Test status
Simulation time 10061087190 ps
CPU time 12.5 seconds
Started Jun 06 01:51:47 PM PDT 24
Finished Jun 06 01:52:01 PM PDT 24
Peak memory 205728 kb
Host smart-50eb331f-03f4-4cc8-87bc-4c05434cc9f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29931
18748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.2993118748
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.2777564868
Short name T524
Test name
Test status
Simulation time 10064776122 ps
CPU time 14.54 seconds
Started Jun 06 01:51:31 PM PDT 24
Finished Jun 06 01:51:46 PM PDT 24
Peak memory 205692 kb
Host smart-8e6a5ad1-e4f7-4adf-8187-61bd5c169751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27775
64868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.2777564868
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.885834523
Short name T1144
Test name
Test status
Simulation time 10152874696 ps
CPU time 13.34 seconds
Started Jun 06 01:51:35 PM PDT 24
Finished Jun 06 01:51:48 PM PDT 24
Peak memory 205652 kb
Host smart-db3bbe3b-041f-4366-b4b4-abb2466c4dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88583
4523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.885834523
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.1598954068
Short name T433
Test name
Test status
Simulation time 13282434083 ps
CPU time 19.97 seconds
Started Jun 06 01:51:30 PM PDT 24
Finished Jun 06 01:51:50 PM PDT 24
Peak memory 205652 kb
Host smart-47998285-128e-481f-a97d-05927b4651de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15989
54068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.1598954068
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.3576609908
Short name T1516
Test name
Test status
Simulation time 10119026225 ps
CPU time 13.37 seconds
Started Jun 06 01:51:31 PM PDT 24
Finished Jun 06 01:51:45 PM PDT 24
Peak memory 205680 kb
Host smart-9a8281dd-d58d-4e0d-9d3b-e32d266c5a0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35766
09908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.3576609908
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.3565992335
Short name T351
Test name
Test status
Simulation time 23277441220 ps
CPU time 134.18 seconds
Started Jun 06 01:51:30 PM PDT 24
Finished Jun 06 01:53:45 PM PDT 24
Peak memory 205704 kb
Host smart-c6f28f55-784f-4b58-bbfe-3098c5417bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35659
92335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.3565992335
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.1005394694
Short name T1196
Test name
Test status
Simulation time 10035600624 ps
CPU time 14.23 seconds
Started Jun 06 01:51:32 PM PDT 24
Finished Jun 06 01:51:47 PM PDT 24
Peak memory 205696 kb
Host smart-6f9cc8a9-5981-4cb4-99b5-f6d469e0dd5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10053
94694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.1005394694
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.4284560629
Short name T118
Test name
Test status
Simulation time 10136534341 ps
CPU time 14.56 seconds
Started Jun 06 01:51:44 PM PDT 24
Finished Jun 06 01:52:01 PM PDT 24
Peak memory 205616 kb
Host smart-1496e15d-00ad-4c12-ae72-1488d8d307c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42845
60629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.4284560629
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.1760043493
Short name T2001
Test name
Test status
Simulation time 10073743983 ps
CPU time 16.38 seconds
Started Jun 06 01:51:40 PM PDT 24
Finished Jun 06 01:51:58 PM PDT 24
Peak memory 205732 kb
Host smart-d768b4bb-7fcc-4401-86cb-3a10e24169bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17600
43493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.1760043493
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.4164477943
Short name T566
Test name
Test status
Simulation time 10067874291 ps
CPU time 14.49 seconds
Started Jun 06 01:51:39 PM PDT 24
Finished Jun 06 01:51:55 PM PDT 24
Peak memory 205556 kb
Host smart-5bebee2c-ee47-4006-8ed7-014e46f50dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41644
77943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.4164477943
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.517578151
Short name T410
Test name
Test status
Simulation time 10116008408 ps
CPU time 12.93 seconds
Started Jun 06 01:51:38 PM PDT 24
Finished Jun 06 01:51:52 PM PDT 24
Peak memory 205640 kb
Host smart-8ab3c008-5a9f-4a6b-af9b-e7236c672020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51757
8151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.517578151
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.3078454739
Short name T144
Test name
Test status
Simulation time 10050112828 ps
CPU time 13.18 seconds
Started Jun 06 01:51:37 PM PDT 24
Finished Jun 06 01:51:51 PM PDT 24
Peak memory 205788 kb
Host smart-6d9ee3cc-5f5e-4e71-b155-e4f17c513fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30784
54739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.3078454739
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_eop_single_bit_handling.3567460097
Short name T1719
Test name
Test status
Simulation time 10075686082 ps
CPU time 12.73 seconds
Started Jun 06 01:51:40 PM PDT 24
Finished Jun 06 01:51:54 PM PDT 24
Peak memory 205716 kb
Host smart-a72d3866-5f78-4ea9-a9f3-2d0d0eb86c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35674
60097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_eop_single_bit_handling.3567460097
Directory /workspace/37.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.72605185
Short name T1707
Test name
Test status
Simulation time 10042395666 ps
CPU time 14.6 seconds
Started Jun 06 01:51:44 PM PDT 24
Finished Jun 06 01:52:01 PM PDT 24
Peak memory 205660 kb
Host smart-e0d3db5b-32df-497a-9093-4c2e373b73fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72605
185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.72605185
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.995926311
Short name T1154
Test name
Test status
Simulation time 10037923584 ps
CPU time 13.39 seconds
Started Jun 06 01:51:47 PM PDT 24
Finished Jun 06 01:52:02 PM PDT 24
Peak memory 205616 kb
Host smart-d57136a3-f2ab-4f57-884b-0b585abb25f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99592
6311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.995926311
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.4223235986
Short name T100
Test name
Test status
Simulation time 32450581766 ps
CPU time 74.49 seconds
Started Jun 06 01:51:39 PM PDT 24
Finished Jun 06 01:52:55 PM PDT 24
Peak memory 205664 kb
Host smart-9669ea16-97ca-4eff-9dfa-c0b176a85382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42232
35986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.4223235986
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.2227324606
Short name T53
Test name
Test status
Simulation time 10086264370 ps
CPU time 13.81 seconds
Started Jun 06 01:51:48 PM PDT 24
Finished Jun 06 01:52:03 PM PDT 24
Peak memory 205744 kb
Host smart-f199277c-e184-4367-ba15-6e6ca2d864a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22273
24606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2227324606
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1992343205
Short name T1119
Test name
Test status
Simulation time 10114156130 ps
CPU time 15.2 seconds
Started Jun 06 01:51:42 PM PDT 24
Finished Jun 06 01:52:00 PM PDT 24
Peak memory 205484 kb
Host smart-0d67a211-6454-4867-8560-1e831122795e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19923
43205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1992343205
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.749292010
Short name T719
Test name
Test status
Simulation time 10093171349 ps
CPU time 13.46 seconds
Started Jun 06 01:51:39 PM PDT 24
Finished Jun 06 01:51:54 PM PDT 24
Peak memory 205852 kb
Host smart-14fa638b-0721-4a5e-9a03-7f66e30749e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74929
2010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.749292010
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.3826015655
Short name T1787
Test name
Test status
Simulation time 10134176279 ps
CPU time 12.98 seconds
Started Jun 06 01:51:42 PM PDT 24
Finished Jun 06 01:51:57 PM PDT 24
Peak memory 205736 kb
Host smart-1bb91e64-1311-4d99-9368-fdafe10dec8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38260
15655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.3826015655
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.3844603217
Short name T145
Test name
Test status
Simulation time 10070782940 ps
CPU time 12.33 seconds
Started Jun 06 01:51:42 PM PDT 24
Finished Jun 06 01:51:57 PM PDT 24
Peak memory 205752 kb
Host smart-c65bbf8e-9f5b-4252-a080-8e5dbd23921e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38446
03217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.3844603217
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2484199590
Short name T703
Test name
Test status
Simulation time 10096587263 ps
CPU time 14.55 seconds
Started Jun 06 01:51:41 PM PDT 24
Finished Jun 06 01:51:57 PM PDT 24
Peak memory 205612 kb
Host smart-d2c6262a-db69-46dd-98f7-10e43ad7cd70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24841
99590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2484199590
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.4166239293
Short name T147
Test name
Test status
Simulation time 10093841432 ps
CPU time 14.62 seconds
Started Jun 06 01:51:33 PM PDT 24
Finished Jun 06 01:51:49 PM PDT 24
Peak memory 205728 kb
Host smart-cdb0a1eb-5bdb-47c7-9eb0-8a7be0405ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41662
39293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.4166239293
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.3573153090
Short name T439
Test name
Test status
Simulation time 10061478136 ps
CPU time 14.71 seconds
Started Jun 06 01:51:39 PM PDT 24
Finished Jun 06 01:51:55 PM PDT 24
Peak memory 205720 kb
Host smart-3fd5aff7-133d-4cfc-92ed-5a60934365b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35731
53090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.3573153090
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.3788064156
Short name T1833
Test name
Test status
Simulation time 10084547891 ps
CPU time 14.93 seconds
Started Jun 06 01:51:40 PM PDT 24
Finished Jun 06 01:51:56 PM PDT 24
Peak memory 205636 kb
Host smart-7e592dd1-dc93-4c69-b4de-7fa00d8a36f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37880
64156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.3788064156
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.746609463
Short name T1666
Test name
Test status
Simulation time 19802574491 ps
CPU time 278.78 seconds
Started Jun 06 01:51:48 PM PDT 24
Finished Jun 06 01:56:28 PM PDT 24
Peak memory 205632 kb
Host smart-1b3fae7b-a217-4070-a8d3-92d2da5decde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74660
9463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.746609463
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.317016161
Short name T1584
Test name
Test status
Simulation time 10166037605 ps
CPU time 12.94 seconds
Started Jun 06 01:51:44 PM PDT 24
Finished Jun 06 01:51:59 PM PDT 24
Peak memory 205664 kb
Host smart-ff214511-acd6-44b8-9b68-c3c1ea76ec50
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=317016161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.317016161
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.1663105845
Short name T1726
Test name
Test status
Simulation time 10083013769 ps
CPU time 13.71 seconds
Started Jun 06 01:51:42 PM PDT 24
Finished Jun 06 01:51:58 PM PDT 24
Peak memory 205732 kb
Host smart-6dcec1d2-13ec-4042-a127-acd9a49e0fb0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1663105845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.1663105845
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.510860445
Short name T1053
Test name
Test status
Simulation time 10086708490 ps
CPU time 15.38 seconds
Started Jun 06 01:51:44 PM PDT 24
Finished Jun 06 01:52:02 PM PDT 24
Peak memory 205744 kb
Host smart-32db39b5-0388-4232-82e3-de85e0f76af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51086
0445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.510860445
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.694004542
Short name T11
Test name
Test status
Simulation time 13505842581 ps
CPU time 19.98 seconds
Started Jun 06 01:51:47 PM PDT 24
Finished Jun 06 01:52:09 PM PDT 24
Peak memory 205776 kb
Host smart-e76ab4f1-969a-4965-bed0-2978a1a84b01
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=694004542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.694004542
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.3281295103
Short name T10
Test name
Test status
Simulation time 23221466158 ps
CPU time 31.52 seconds
Started Jun 06 01:51:40 PM PDT 24
Finished Jun 06 01:52:13 PM PDT 24
Peak memory 205692 kb
Host smart-c03549a4-fb6f-4f75-9067-cb8b4ef27b28
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3281295103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.3281295103
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.1515922654
Short name T1059
Test name
Test status
Simulation time 10093983208 ps
CPU time 13.22 seconds
Started Jun 06 01:51:44 PM PDT 24
Finished Jun 06 01:51:59 PM PDT 24
Peak memory 205652 kb
Host smart-a8b77dc5-d57d-4661-9ebf-df5cabd69359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15159
22654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.1515922654
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.415376178
Short name T1089
Test name
Test status
Simulation time 11155909455 ps
CPU time 17.83 seconds
Started Jun 06 01:51:43 PM PDT 24
Finished Jun 06 01:52:04 PM PDT 24
Peak memory 205660 kb
Host smart-4a86f22d-ec6a-4a74-a667-3d52e87f92a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41537
6178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.415376178
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.3710206799
Short name T892
Test name
Test status
Simulation time 10068037907 ps
CPU time 15.54 seconds
Started Jun 06 01:51:40 PM PDT 24
Finished Jun 06 01:51:57 PM PDT 24
Peak memory 205692 kb
Host smart-3c36a619-4504-44dd-9283-a6503892e8d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37102
06799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.3710206799
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.2526085025
Short name T340
Test name
Test status
Simulation time 10069935020 ps
CPU time 14.8 seconds
Started Jun 06 01:51:42 PM PDT 24
Finished Jun 06 01:51:58 PM PDT 24
Peak memory 205632 kb
Host smart-c5d7c6e0-88ca-4854-9740-9044cabc16de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25260
85025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.2526085025
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.2033129796
Short name T1750
Test name
Test status
Simulation time 10848741595 ps
CPU time 17.53 seconds
Started Jun 06 01:51:41 PM PDT 24
Finished Jun 06 01:52:00 PM PDT 24
Peak memory 205660 kb
Host smart-d55a5c05-47fe-4a51-994e-7551cb9f7087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20331
29796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.2033129796
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2893554010
Short name T474
Test name
Test status
Simulation time 10160174576 ps
CPU time 17.01 seconds
Started Jun 06 01:51:40 PM PDT 24
Finished Jun 06 01:51:59 PM PDT 24
Peak memory 205692 kb
Host smart-32fbb45a-c501-4b16-87be-420a9a88f216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28935
54010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2893554010
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.3720846821
Short name T1299
Test name
Test status
Simulation time 10117196647 ps
CPU time 14.26 seconds
Started Jun 06 01:51:44 PM PDT 24
Finished Jun 06 01:52:00 PM PDT 24
Peak memory 205720 kb
Host smart-badd6331-2a96-49a5-a7e2-6ce7ccec2bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37208
46821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.3720846821
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.1494783913
Short name T823
Test name
Test status
Simulation time 10054188801 ps
CPU time 13.65 seconds
Started Jun 06 01:51:42 PM PDT 24
Finished Jun 06 01:51:57 PM PDT 24
Peak memory 205996 kb
Host smart-4df926cb-1d13-408c-90e2-cee119db3b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14947
83913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1494783913
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1655714951
Short name T651
Test name
Test status
Simulation time 10148611341 ps
CPU time 14.01 seconds
Started Jun 06 01:51:42 PM PDT 24
Finished Jun 06 01:51:58 PM PDT 24
Peak memory 205672 kb
Host smart-75d93e54-93c0-46ae-9518-6c96e48330ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16557
14951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1655714951
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.2848350952
Short name T1654
Test name
Test status
Simulation time 10092329773 ps
CPU time 14.24 seconds
Started Jun 06 01:51:41 PM PDT 24
Finished Jun 06 01:51:57 PM PDT 24
Peak memory 205740 kb
Host smart-93f7739d-2afe-40e2-bd93-cd3ea7dcc506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28483
50952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.2848350952
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.336047689
Short name T1353
Test name
Test status
Simulation time 13216125972 ps
CPU time 15.69 seconds
Started Jun 06 01:51:39 PM PDT 24
Finished Jun 06 01:51:56 PM PDT 24
Peak memory 205696 kb
Host smart-efb5ccb6-b742-4da2-8eb3-2a4310e401e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33604
7689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.336047689
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3169301168
Short name T1824
Test name
Test status
Simulation time 10140277076 ps
CPU time 13.5 seconds
Started Jun 06 01:51:46 PM PDT 24
Finished Jun 06 01:52:02 PM PDT 24
Peak memory 205640 kb
Host smart-e6c0a777-b51b-4d8d-a947-ee26a586ac5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31693
01168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3169301168
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.2682494047
Short name T403
Test name
Test status
Simulation time 24079773887 ps
CPU time 141.47 seconds
Started Jun 06 01:51:43 PM PDT 24
Finished Jun 06 01:54:07 PM PDT 24
Peak memory 205788 kb
Host smart-4c55e076-8196-4b8f-b12a-b89a6c45ef22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26824
94047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.2682494047
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3966716987
Short name T594
Test name
Test status
Simulation time 10040091338 ps
CPU time 15.23 seconds
Started Jun 06 01:51:40 PM PDT 24
Finished Jun 06 01:51:57 PM PDT 24
Peak memory 205708 kb
Host smart-d181bd7e-59c6-482d-885a-dab98d32c99c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39667
16987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3966716987
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.564093503
Short name T1925
Test name
Test status
Simulation time 10079204968 ps
CPU time 15.23 seconds
Started Jun 06 01:51:42 PM PDT 24
Finished Jun 06 01:51:59 PM PDT 24
Peak memory 205752 kb
Host smart-acd0beed-fe02-4677-8d4b-22d48295e51d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56409
3503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.564093503
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.2040606512
Short name T462
Test name
Test status
Simulation time 10138602586 ps
CPU time 14.89 seconds
Started Jun 06 01:51:44 PM PDT 24
Finished Jun 06 01:52:01 PM PDT 24
Peak memory 205648 kb
Host smart-e0b218f2-cbee-4d64-8bde-fc5e61afcfd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20406
06512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.2040606512
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.948474314
Short name T1695
Test name
Test status
Simulation time 10092449460 ps
CPU time 12.43 seconds
Started Jun 06 01:51:43 PM PDT 24
Finished Jun 06 01:51:58 PM PDT 24
Peak memory 205672 kb
Host smart-bd46cc7e-e44f-44ef-bcfb-6f979c2383e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94847
4314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.948474314
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.2855480229
Short name T266
Test name
Test status
Simulation time 10102288671 ps
CPU time 16.45 seconds
Started Jun 06 01:51:45 PM PDT 24
Finished Jun 06 01:52:03 PM PDT 24
Peak memory 205748 kb
Host smart-592dd6df-7d4a-40dd-b13f-b93a4a4522b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28554
80229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.2855480229
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.2153691142
Short name T164
Test name
Test status
Simulation time 10054983909 ps
CPU time 14.67 seconds
Started Jun 06 01:51:44 PM PDT 24
Finished Jun 06 01:52:01 PM PDT 24
Peak memory 205688 kb
Host smart-b5b607a2-41a5-4fe1-b652-b4dae9ae40b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21536
91142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.2153691142
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_eop_single_bit_handling.1437228120
Short name T395
Test name
Test status
Simulation time 10083392961 ps
CPU time 14.25 seconds
Started Jun 06 01:51:40 PM PDT 24
Finished Jun 06 01:51:56 PM PDT 24
Peak memory 205700 kb
Host smart-47cc0785-827c-4204-ae00-915cbecb79b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14372
28120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_eop_single_bit_handling.1437228120
Directory /workspace/38.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.1444853510
Short name T334
Test name
Test status
Simulation time 10048572347 ps
CPU time 15.5 seconds
Started Jun 06 01:51:46 PM PDT 24
Finished Jun 06 01:52:04 PM PDT 24
Peak memory 205756 kb
Host smart-d51a4979-509a-419a-8b58-4c00c2badd39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14448
53510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.1444853510
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.2835745355
Short name T1298
Test name
Test status
Simulation time 10035815457 ps
CPU time 13.88 seconds
Started Jun 06 01:51:43 PM PDT 24
Finished Jun 06 01:51:58 PM PDT 24
Peak memory 205724 kb
Host smart-758db4f0-abdc-46b4-89a1-3b5bb96f1f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28357
45355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.2835745355
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.2148825988
Short name T815
Test name
Test status
Simulation time 26695911946 ps
CPU time 49.36 seconds
Started Jun 06 01:51:41 PM PDT 24
Finished Jun 06 01:52:31 PM PDT 24
Peak memory 205632 kb
Host smart-2584ca13-1c0e-48f1-9b23-b77129fd8145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21488
25988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.2148825988
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.857248609
Short name T1582
Test name
Test status
Simulation time 10074471769 ps
CPU time 14.85 seconds
Started Jun 06 01:51:46 PM PDT 24
Finished Jun 06 01:52:03 PM PDT 24
Peak memory 205660 kb
Host smart-54482ca7-ba43-43a8-b0f6-55879ef8e158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85724
8609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.857248609
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.2441292828
Short name T1197
Test name
Test status
Simulation time 10108979393 ps
CPU time 13.5 seconds
Started Jun 06 01:51:42 PM PDT 24
Finished Jun 06 01:51:57 PM PDT 24
Peak memory 205696 kb
Host smart-9c362bf3-de5f-4040-a17f-660fc16c0cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24412
92828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.2441292828
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.126332970
Short name T1264
Test name
Test status
Simulation time 10068541731 ps
CPU time 13.17 seconds
Started Jun 06 01:51:41 PM PDT 24
Finished Jun 06 01:51:55 PM PDT 24
Peak memory 205728 kb
Host smart-a14abca8-4e58-46d6-9dfe-d036a0db89cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12633
2970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.126332970
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.3854882711
Short name T970
Test name
Test status
Simulation time 10051422486 ps
CPU time 14.71 seconds
Started Jun 06 01:51:41 PM PDT 24
Finished Jun 06 01:51:57 PM PDT 24
Peak memory 205616 kb
Host smart-0b8872f8-9659-47c1-ac93-ef1c85f6f43f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38548
82711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.3854882711
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.1889293259
Short name T1331
Test name
Test status
Simulation time 10059060901 ps
CPU time 15.73 seconds
Started Jun 06 01:51:43 PM PDT 24
Finished Jun 06 01:52:01 PM PDT 24
Peak memory 205660 kb
Host smart-4aa131d0-8059-41e3-9dcf-77dd1ee39798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18892
93259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.1889293259
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2982412568
Short name T1412
Test name
Test status
Simulation time 10056900510 ps
CPU time 12.43 seconds
Started Jun 06 01:51:47 PM PDT 24
Finished Jun 06 01:52:01 PM PDT 24
Peak memory 205660 kb
Host smart-e425793a-9d74-476d-a28c-8e3a25f84076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29824
12568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2982412568
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.639919198
Short name T1115
Test name
Test status
Simulation time 10116106408 ps
CPU time 14.66 seconds
Started Jun 06 01:51:41 PM PDT 24
Finished Jun 06 01:51:57 PM PDT 24
Peak memory 205604 kb
Host smart-30b7e8a4-9ccd-4af1-9238-df38bc69308b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63991
9198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.639919198
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.568428545
Short name T1433
Test name
Test status
Simulation time 10055813204 ps
CPU time 13.2 seconds
Started Jun 06 01:51:43 PM PDT 24
Finished Jun 06 01:51:59 PM PDT 24
Peak memory 205728 kb
Host smart-4d2671b4-2945-4a31-89b5-892e82e1fa6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56842
8545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.568428545
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.2645334619
Short name T893
Test name
Test status
Simulation time 10059965864 ps
CPU time 14.28 seconds
Started Jun 06 01:51:39 PM PDT 24
Finished Jun 06 01:51:54 PM PDT 24
Peak memory 205644 kb
Host smart-dd7b7080-fe0c-4ccb-8e6a-c6cdcf4ce07a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26453
34619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.2645334619
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.3077549871
Short name T202
Test name
Test status
Simulation time 14798023881 ps
CPU time 57.85 seconds
Started Jun 06 01:51:43 PM PDT 24
Finished Jun 06 01:52:44 PM PDT 24
Peak memory 205744 kb
Host smart-591968af-7f2a-426a-8435-b7fdbdfb7622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30775
49871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.3077549871
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.3421839107
Short name T2009
Test name
Test status
Simulation time 10148696401 ps
CPU time 12.77 seconds
Started Jun 06 01:51:50 PM PDT 24
Finished Jun 06 01:52:04 PM PDT 24
Peak memory 205624 kb
Host smart-5922d32b-21e3-4d67-b621-e4d659b490c5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3421839107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.3421839107
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.1613949656
Short name T1453
Test name
Test status
Simulation time 10052246987 ps
CPU time 13.98 seconds
Started Jun 06 01:51:47 PM PDT 24
Finished Jun 06 01:52:02 PM PDT 24
Peak memory 205692 kb
Host smart-c58a4f62-2ee9-4e15-9070-20a4d8d1631b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1613949656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.1613949656
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.847567172
Short name T1149
Test name
Test status
Simulation time 10092689177 ps
CPU time 13.38 seconds
Started Jun 06 01:51:52 PM PDT 24
Finished Jun 06 01:52:07 PM PDT 24
Peak memory 205644 kb
Host smart-aa75ff6d-e359-428d-a531-e83c25238c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84756
7172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.847567172
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.2716417002
Short name T1369
Test name
Test status
Simulation time 13418976532 ps
CPU time 15.71 seconds
Started Jun 06 01:51:44 PM PDT 24
Finished Jun 06 01:52:02 PM PDT 24
Peak memory 205768 kb
Host smart-880b6345-192d-4415-9c17-ad7813cb7da3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2716417002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.2716417002
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.3056317267
Short name T1396
Test name
Test status
Simulation time 23333604299 ps
CPU time 25.4 seconds
Started Jun 06 01:51:43 PM PDT 24
Finished Jun 06 01:52:10 PM PDT 24
Peak memory 205616 kb
Host smart-01107bbf-0792-4d45-b9ac-e7e627e560ed
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3056317267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.3056317267
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.2490216907
Short name T338
Test name
Test status
Simulation time 10050709498 ps
CPU time 12.57 seconds
Started Jun 06 01:51:42 PM PDT 24
Finished Jun 06 01:51:57 PM PDT 24
Peak memory 205668 kb
Host smart-276669c0-9fbe-4cbe-b04f-4a556ae6f488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24902
16907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.2490216907
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.1689857042
Short name T1647
Test name
Test status
Simulation time 11221579087 ps
CPU time 15.18 seconds
Started Jun 06 01:51:45 PM PDT 24
Finished Jun 06 01:52:02 PM PDT 24
Peak memory 205644 kb
Host smart-0f1365ae-5ba2-476a-b650-e3ad10884eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16898
57042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.1689857042
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.3018570550
Short name T23
Test name
Test status
Simulation time 10055499785 ps
CPU time 13.07 seconds
Started Jun 06 01:51:42 PM PDT 24
Finished Jun 06 01:51:57 PM PDT 24
Peak memory 205676 kb
Host smart-481f9cb4-1df2-41ad-bc8e-e00ba5fcf570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30185
70550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.3018570550
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.2452764585
Short name T1118
Test name
Test status
Simulation time 10064480767 ps
CPU time 13.44 seconds
Started Jun 06 01:51:44 PM PDT 24
Finished Jun 06 01:51:59 PM PDT 24
Peak memory 205628 kb
Host smart-9c4dc870-cf2c-465b-8ed1-9fa0197e8c3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24527
64585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.2452764585
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.1019791175
Short name T1921
Test name
Test status
Simulation time 10843203362 ps
CPU time 17.72 seconds
Started Jun 06 01:51:43 PM PDT 24
Finished Jun 06 01:52:03 PM PDT 24
Peak memory 205756 kb
Host smart-88adb434-3428-408f-a914-7cbfbcbd1275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10197
91175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.1019791175
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3594989777
Short name T399
Test name
Test status
Simulation time 10202607896 ps
CPU time 16.85 seconds
Started Jun 06 01:51:43 PM PDT 24
Finished Jun 06 01:52:03 PM PDT 24
Peak memory 205748 kb
Host smart-2641e5dd-e5ba-4449-aa51-93f6f0757abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35949
89777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3594989777
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.3375403080
Short name T531
Test name
Test status
Simulation time 10140726095 ps
CPU time 13.74 seconds
Started Jun 06 01:51:49 PM PDT 24
Finished Jun 06 01:52:04 PM PDT 24
Peak memory 205720 kb
Host smart-1459d207-2f90-4ac1-815a-5c96dcf9024f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33754
03080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.3375403080
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1178625153
Short name T1922
Test name
Test status
Simulation time 10042730557 ps
CPU time 15.61 seconds
Started Jun 06 01:51:49 PM PDT 24
Finished Jun 06 01:52:06 PM PDT 24
Peak memory 205400 kb
Host smart-1bc8c660-66fc-4a5c-8c75-2ae1e9ebca90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11786
25153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1178625153
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.758855813
Short name T1123
Test name
Test status
Simulation time 10074507857 ps
CPU time 14.75 seconds
Started Jun 06 01:51:42 PM PDT 24
Finished Jun 06 01:51:58 PM PDT 24
Peak memory 205704 kb
Host smart-c4b8226c-32f8-4fa5-86f7-be834b1f965b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75885
5813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.758855813
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.2005064499
Short name T894
Test name
Test status
Simulation time 10123704894 ps
CPU time 13.44 seconds
Started Jun 06 01:51:42 PM PDT 24
Finished Jun 06 01:51:58 PM PDT 24
Peak memory 205756 kb
Host smart-86b0a357-2ac5-41be-82e0-4e1b0b8bb8fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20050
64499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.2005064499
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.1457723311
Short name T661
Test name
Test status
Simulation time 13184209791 ps
CPU time 15.84 seconds
Started Jun 06 01:51:45 PM PDT 24
Finished Jun 06 01:52:03 PM PDT 24
Peak memory 205348 kb
Host smart-c01049cf-ef7b-4a7c-83e4-2ed9aefaf501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14577
23311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.1457723311
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.4201539948
Short name T1483
Test name
Test status
Simulation time 10145759088 ps
CPU time 16.13 seconds
Started Jun 06 01:51:41 PM PDT 24
Finished Jun 06 01:51:59 PM PDT 24
Peak memory 205748 kb
Host smart-63ef99ef-39cb-4896-b467-37f546ea6286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42015
39948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.4201539948
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.2124853844
Short name T353
Test name
Test status
Simulation time 22002227312 ps
CPU time 341.24 seconds
Started Jun 06 01:51:43 PM PDT 24
Finished Jun 06 01:57:26 PM PDT 24
Peak memory 205488 kb
Host smart-a287d264-f458-4199-ac2c-240bbb764efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21248
53844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.2124853844
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1649983741
Short name T270
Test name
Test status
Simulation time 10113750079 ps
CPU time 15.91 seconds
Started Jun 06 01:51:43 PM PDT 24
Finished Jun 06 01:52:01 PM PDT 24
Peak memory 205564 kb
Host smart-e83fd432-f884-4e53-a303-5af991a9e324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16499
83741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1649983741
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1992947793
Short name T119
Test name
Test status
Simulation time 10115438334 ps
CPU time 12.84 seconds
Started Jun 06 01:51:50 PM PDT 24
Finished Jun 06 01:52:04 PM PDT 24
Peak memory 205688 kb
Host smart-d6821f56-052c-4815-8627-e73c87b4d3c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19929
47793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1992947793
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.2069299723
Short name T868
Test name
Test status
Simulation time 10085612155 ps
CPU time 14.56 seconds
Started Jun 06 01:51:46 PM PDT 24
Finished Jun 06 01:52:03 PM PDT 24
Peak memory 205764 kb
Host smart-bf4d4cfa-ec28-44c3-8431-af13e75539c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20692
99723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.2069299723
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1761340097
Short name T329
Test name
Test status
Simulation time 10096096745 ps
CPU time 14.06 seconds
Started Jun 06 01:51:45 PM PDT 24
Finished Jun 06 01:52:01 PM PDT 24
Peak memory 205460 kb
Host smart-c1ee4093-18f7-4c99-a95f-cc85173288a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17613
40097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1761340097
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.2540159718
Short name T1301
Test name
Test status
Simulation time 10071460861 ps
CPU time 16.25 seconds
Started Jun 06 01:51:51 PM PDT 24
Finished Jun 06 01:52:08 PM PDT 24
Peak memory 205764 kb
Host smart-3eafbe99-c5c3-4875-ade5-7ae6c233c099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25401
59718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.2540159718
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.2424247279
Short name T1945
Test name
Test status
Simulation time 10057056093 ps
CPU time 14.25 seconds
Started Jun 06 01:51:52 PM PDT 24
Finished Jun 06 01:52:07 PM PDT 24
Peak memory 205696 kb
Host smart-0891366e-e25e-4e00-a5fa-5d1b519b6ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24242
47279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.2424247279
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_eop_single_bit_handling.1229708852
Short name T921
Test name
Test status
Simulation time 10090280094 ps
CPU time 13.36 seconds
Started Jun 06 01:51:49 PM PDT 24
Finished Jun 06 01:52:03 PM PDT 24
Peak memory 205640 kb
Host smart-20bb0e5b-d6c0-4944-8041-15dc264ac505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12297
08852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_eop_single_bit_handling.1229708852
Directory /workspace/39.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2598312642
Short name T201
Test name
Test status
Simulation time 10114920967 ps
CPU time 13.45 seconds
Started Jun 06 01:51:48 PM PDT 24
Finished Jun 06 01:52:03 PM PDT 24
Peak memory 205640 kb
Host smart-f244327f-1ab3-47d9-b618-9a1b1079131e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25983
12642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.2598312642
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1332533543
Short name T1065
Test name
Test status
Simulation time 10042328117 ps
CPU time 13.61 seconds
Started Jun 06 01:51:48 PM PDT 24
Finished Jun 06 01:52:03 PM PDT 24
Peak memory 205720 kb
Host smart-93b36f6a-5599-4eff-9097-1691d0267539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13325
33543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1332533543
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.1205276003
Short name T1215
Test name
Test status
Simulation time 20158059490 ps
CPU time 36.44 seconds
Started Jun 06 01:51:54 PM PDT 24
Finished Jun 06 01:52:32 PM PDT 24
Peak memory 205640 kb
Host smart-3be8a461-1131-44f3-8787-aa1a66ae83c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12052
76003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.1205276003
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.3335855149
Short name T1914
Test name
Test status
Simulation time 10075740767 ps
CPU time 13.28 seconds
Started Jun 06 01:51:48 PM PDT 24
Finished Jun 06 01:52:02 PM PDT 24
Peak memory 205664 kb
Host smart-005c96ba-3e4d-4620-8527-853ab3a979b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33358
55149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.3335855149
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.3098380314
Short name T619
Test name
Test status
Simulation time 10131802883 ps
CPU time 13.39 seconds
Started Jun 06 01:51:49 PM PDT 24
Finished Jun 06 01:52:04 PM PDT 24
Peak memory 205728 kb
Host smart-ff966105-3c14-4d19-a493-6f22e16b1e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30983
80314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.3098380314
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.3190927216
Short name T371
Test name
Test status
Simulation time 10065813011 ps
CPU time 13.32 seconds
Started Jun 06 01:51:49 PM PDT 24
Finished Jun 06 01:52:04 PM PDT 24
Peak memory 205720 kb
Host smart-82a62e99-399e-46d7-9421-36a11df9c673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31909
27216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.3190927216
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.3024247508
Short name T1184
Test name
Test status
Simulation time 10041851187 ps
CPU time 13.68 seconds
Started Jun 06 01:51:53 PM PDT 24
Finished Jun 06 01:52:08 PM PDT 24
Peak memory 205592 kb
Host smart-dd7fd279-4141-435b-9942-5cfcd9b2f6a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30242
47508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.3024247508
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.4049650883
Short name T1939
Test name
Test status
Simulation time 10077116461 ps
CPU time 14.25 seconds
Started Jun 06 01:52:01 PM PDT 24
Finished Jun 06 01:52:16 PM PDT 24
Peak memory 205676 kb
Host smart-095ccf7f-5747-4ab1-b757-1a4c44a138f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40496
50883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.4049650883
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1415077175
Short name T1974
Test name
Test status
Simulation time 10076081716 ps
CPU time 14.02 seconds
Started Jun 06 01:51:49 PM PDT 24
Finished Jun 06 01:52:04 PM PDT 24
Peak memory 205644 kb
Host smart-b3458d8c-f598-495c-aae5-9db3dc4f1ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14150
77175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1415077175
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.4187119221
Short name T1986
Test name
Test status
Simulation time 10152227699 ps
CPU time 14 seconds
Started Jun 06 01:51:53 PM PDT 24
Finished Jun 06 01:52:08 PM PDT 24
Peak memory 205720 kb
Host smart-8b2ed8ca-1a27-4f25-ac1e-f49c6ad0730d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41871
19221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.4187119221
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.1614603328
Short name T809
Test name
Test status
Simulation time 10048819344 ps
CPU time 15.58 seconds
Started Jun 06 01:51:48 PM PDT 24
Finished Jun 06 01:52:05 PM PDT 24
Peak memory 205696 kb
Host smart-18b4143f-1ad3-4aae-aacb-2f5f3e331459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16146
03328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.1614603328
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.2360124993
Short name T369
Test name
Test status
Simulation time 10077915562 ps
CPU time 13.07 seconds
Started Jun 06 01:51:50 PM PDT 24
Finished Jun 06 01:52:04 PM PDT 24
Peak memory 205708 kb
Host smart-55b4aff3-190c-47f8-a7a5-ea4dbbcc88da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23601
24993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.2360124993
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.1146918863
Short name T760
Test name
Test status
Simulation time 15220122280 ps
CPU time 60.58 seconds
Started Jun 06 01:51:55 PM PDT 24
Finished Jun 06 01:52:57 PM PDT 24
Peak memory 205704 kb
Host smart-dfe0d04c-e43c-45c6-8522-ed7d3a6a7449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11469
18863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.1146918863
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.3659188666
Short name T880
Test name
Test status
Simulation time 10138810352 ps
CPU time 16.68 seconds
Started Jun 06 01:45:33 PM PDT 24
Finished Jun 06 01:45:51 PM PDT 24
Peak memory 205732 kb
Host smart-96b6c894-fc05-45e5-a80d-3dc2edb95df2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3659188666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.3659188666
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.2621069375
Short name T1957
Test name
Test status
Simulation time 10054401786 ps
CPU time 15.17 seconds
Started Jun 06 01:45:32 PM PDT 24
Finished Jun 06 01:45:48 PM PDT 24
Peak memory 205564 kb
Host smart-2009a567-90ce-460c-bee5-667fe920cf1f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2621069375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.2621069375
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.982539784
Short name T1861
Test name
Test status
Simulation time 10161923900 ps
CPU time 16.47 seconds
Started Jun 06 01:45:30 PM PDT 24
Finished Jun 06 01:45:47 PM PDT 24
Peak memory 205900 kb
Host smart-29075880-300e-47a2-bc5c-27d5a980356d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98253
9784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.982539784
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.1560019876
Short name T1944
Test name
Test status
Simulation time 13650109872 ps
CPU time 17.56 seconds
Started Jun 06 01:45:19 PM PDT 24
Finished Jun 06 01:45:38 PM PDT 24
Peak memory 205728 kb
Host smart-ccbdc000-76d2-4793-ada4-78c54ef820b4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1560019876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.1560019876
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.619105090
Short name T1467
Test name
Test status
Simulation time 10149277178 ps
CPU time 15.4 seconds
Started Jun 06 01:45:22 PM PDT 24
Finished Jun 06 01:45:38 PM PDT 24
Peak memory 205884 kb
Host smart-4be506b0-2443-43aa-84ea-904f62870013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61910
5090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.619105090
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.262255646
Short name T173
Test name
Test status
Simulation time 11237043434 ps
CPU time 14.79 seconds
Started Jun 06 01:45:20 PM PDT 24
Finished Jun 06 01:45:36 PM PDT 24
Peak memory 205664 kb
Host smart-2ee8301d-4956-441e-83d0-e0dcbb648453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26225
5646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.262255646
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.2356505184
Short name T1997
Test name
Test status
Simulation time 10036062860 ps
CPU time 14.04 seconds
Started Jun 06 01:45:19 PM PDT 24
Finished Jun 06 01:45:34 PM PDT 24
Peak memory 205592 kb
Host smart-49a15f89-2785-4895-b5b8-09bc102ebcbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23565
05184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.2356505184
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.2910111873
Short name T1888
Test name
Test status
Simulation time 10127182604 ps
CPU time 13.06 seconds
Started Jun 06 01:45:21 PM PDT 24
Finished Jun 06 01:45:35 PM PDT 24
Peak memory 205608 kb
Host smart-01ffdf8e-45df-4190-b6fb-d87d1d4d5cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29101
11873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.2910111873
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.485214895
Short name T1226
Test name
Test status
Simulation time 10910226465 ps
CPU time 14.73 seconds
Started Jun 06 01:45:21 PM PDT 24
Finished Jun 06 01:45:37 PM PDT 24
Peak memory 205644 kb
Host smart-97bdc677-c565-40ce-9eb9-a89da0ced87f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48521
4895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.485214895
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.4026933964
Short name T627
Test name
Test status
Simulation time 10077646708 ps
CPU time 14 seconds
Started Jun 06 01:45:22 PM PDT 24
Finished Jun 06 01:45:37 PM PDT 24
Peak memory 205632 kb
Host smart-22a45a8c-f517-4de3-b9cf-f93e07a79aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40269
33964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.4026933964
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.4129671714
Short name T1766
Test name
Test status
Simulation time 10142712124 ps
CPU time 14.47 seconds
Started Jun 06 01:45:32 PM PDT 24
Finished Jun 06 01:45:47 PM PDT 24
Peak memory 205644 kb
Host smart-5cc97094-c05d-4550-93d6-854fec92a1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41296
71714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.4129671714
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.1540575883
Short name T1867
Test name
Test status
Simulation time 10055803725 ps
CPU time 13.13 seconds
Started Jun 06 01:45:30 PM PDT 24
Finished Jun 06 01:45:44 PM PDT 24
Peak memory 205632 kb
Host smart-9c65c812-72cf-4bfb-8c64-5c0dff46e12c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15405
75883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.1540575883
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1485826815
Short name T1994
Test name
Test status
Simulation time 10157728890 ps
CPU time 13.27 seconds
Started Jun 06 01:45:22 PM PDT 24
Finished Jun 06 01:45:36 PM PDT 24
Peak memory 205768 kb
Host smart-4415c843-d23e-4e7d-9bed-0b64a6b07c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14858
26815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1485826815
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.2812507504
Short name T836
Test name
Test status
Simulation time 10121407775 ps
CPU time 14.49 seconds
Started Jun 06 01:45:23 PM PDT 24
Finished Jun 06 01:45:38 PM PDT 24
Peak memory 205936 kb
Host smart-32ce3996-88a0-4248-a720-77263dc1047a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28125
07504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.2812507504
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.547274921
Short name T352
Test name
Test status
Simulation time 13207471912 ps
CPU time 15.25 seconds
Started Jun 06 01:45:21 PM PDT 24
Finished Jun 06 01:45:37 PM PDT 24
Peak memory 205724 kb
Host smart-9ab02e00-273f-4670-9878-6d998a07bd5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54727
4921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.547274921
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.1872924140
Short name T1884
Test name
Test status
Simulation time 10090306695 ps
CPU time 15.33 seconds
Started Jun 06 01:45:21 PM PDT 24
Finished Jun 06 01:45:37 PM PDT 24
Peak memory 205648 kb
Host smart-992fec96-5d0a-4da0-88f0-3de03aa66152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18729
24140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.1872924140
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.636554771
Short name T1882
Test name
Test status
Simulation time 22921817972 ps
CPU time 139.27 seconds
Started Jun 06 01:45:19 PM PDT 24
Finished Jun 06 01:47:39 PM PDT 24
Peak memory 205708 kb
Host smart-48cdd4cb-97fc-4d81-95ea-a51e3358a370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63655
4771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.636554771
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.605308909
Short name T304
Test name
Test status
Simulation time 10086526076 ps
CPU time 12.69 seconds
Started Jun 06 01:45:20 PM PDT 24
Finished Jun 06 01:45:33 PM PDT 24
Peak memory 205760 kb
Host smart-595cefe5-1b36-47a9-b20e-381808eec4f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60530
8909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.605308909
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.2248114227
Short name T130
Test name
Test status
Simulation time 10114929291 ps
CPU time 15.86 seconds
Started Jun 06 01:45:21 PM PDT 24
Finished Jun 06 01:45:38 PM PDT 24
Peak memory 205656 kb
Host smart-bee7b8e9-7660-4ea9-afc6-0067cae53d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22481
14227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.2248114227
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.1202161547
Short name T1135
Test name
Test status
Simulation time 10072565342 ps
CPU time 15.99 seconds
Started Jun 06 01:45:21 PM PDT 24
Finished Jun 06 01:45:38 PM PDT 24
Peak memory 205756 kb
Host smart-e081f48a-eaf4-429c-968d-f47e76e27443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12021
61547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.1202161547
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.3508227614
Short name T499
Test name
Test status
Simulation time 10062323098 ps
CPU time 13.03 seconds
Started Jun 06 01:45:21 PM PDT 24
Finished Jun 06 01:45:35 PM PDT 24
Peak memory 205668 kb
Host smart-f45d9679-ac4a-47ab-830a-9b0eb05b7b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35082
27614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.3508227614
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.860296066
Short name T56
Test name
Test status
Simulation time 10070017451 ps
CPU time 13.94 seconds
Started Jun 06 01:45:32 PM PDT 24
Finished Jun 06 01:45:47 PM PDT 24
Peak memory 205544 kb
Host smart-d96cf1a0-37af-4bbb-9ceb-09db7cb44762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86029
6066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.860296066
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1932142402
Short name T1532
Test name
Test status
Simulation time 10053384715 ps
CPU time 14.39 seconds
Started Jun 06 01:45:32 PM PDT 24
Finished Jun 06 01:45:47 PM PDT 24
Peak memory 205736 kb
Host smart-957d3aaa-3473-4e4b-b055-b6d04ee8ca7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19321
42402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1932142402
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_eop_single_bit_handling.2962981103
Short name T490
Test name
Test status
Simulation time 10146824293 ps
CPU time 13.83 seconds
Started Jun 06 01:45:35 PM PDT 24
Finished Jun 06 01:45:49 PM PDT 24
Peak memory 205660 kb
Host smart-d9febb87-cb2b-49fc-a544-f1c1cc48f6d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29629
81103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_eop_single_bit_handling.2962981103
Directory /workspace/4.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.540998786
Short name T798
Test name
Test status
Simulation time 10053043053 ps
CPU time 17.2 seconds
Started Jun 06 01:45:30 PM PDT 24
Finished Jun 06 01:45:48 PM PDT 24
Peak memory 205700 kb
Host smart-dc5bb198-6966-4568-b908-05ace7f23ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54099
8786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.540998786
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.1405051984
Short name T1265
Test name
Test status
Simulation time 10061630634 ps
CPU time 14.52 seconds
Started Jun 06 01:45:32 PM PDT 24
Finished Jun 06 01:45:47 PM PDT 24
Peak memory 205700 kb
Host smart-319c4d43-09fe-4e1c-ac38-7df714f9a857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14050
51984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.1405051984
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3024072682
Short name T1832
Test name
Test status
Simulation time 19180849099 ps
CPU time 38.7 seconds
Started Jun 06 01:45:30 PM PDT 24
Finished Jun 06 01:46:09 PM PDT 24
Peak memory 205652 kb
Host smart-de6ed70e-cad6-4764-b069-8efe1ef1b3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30240
72682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3024072682
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.2993879251
Short name T895
Test name
Test status
Simulation time 10090037680 ps
CPU time 14.33 seconds
Started Jun 06 01:45:33 PM PDT 24
Finished Jun 06 01:45:48 PM PDT 24
Peak memory 205760 kb
Host smart-3fb1958b-9881-41ba-ad26-74f0868b4fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29938
79251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.2993879251
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2554943681
Short name T785
Test name
Test status
Simulation time 10177211680 ps
CPU time 14.03 seconds
Started Jun 06 01:45:31 PM PDT 24
Finished Jun 06 01:45:46 PM PDT 24
Peak memory 205688 kb
Host smart-62b9bf04-ec8d-4f6d-a876-03d18d83afe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25549
43681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2554943681
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.4040817657
Short name T188
Test name
Test status
Simulation time 32774981424 ps
CPU time 200.01 seconds
Started Jun 06 01:45:30 PM PDT 24
Finished Jun 06 01:48:52 PM PDT 24
Peak memory 205732 kb
Host smart-7dc7cfc6-5548-4f8f-ba6c-e374786e526a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4040817657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.4040817657
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.3997294525
Short name T179
Test name
Test status
Simulation time 24923737374 ps
CPU time 433.51 seconds
Started Jun 06 01:45:35 PM PDT 24
Finished Jun 06 01:52:49 PM PDT 24
Peak memory 205772 kb
Host smart-6b059157-e2b7-46e3-ab15-747b916b5c02
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3997294525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.3997294525
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.2251011650
Short name T1486
Test name
Test status
Simulation time 25667360047 ps
CPU time 341.18 seconds
Started Jun 06 01:45:30 PM PDT 24
Finished Jun 06 01:51:12 PM PDT 24
Peak memory 205776 kb
Host smart-84b1e266-8464-448a-b7fe-5291ff9f0233
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2251011650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.2251011650
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.713992155
Short name T1625
Test name
Test status
Simulation time 10091309903 ps
CPU time 14.43 seconds
Started Jun 06 01:45:31 PM PDT 24
Finished Jun 06 01:45:46 PM PDT 24
Peak memory 205636 kb
Host smart-0a5c10e5-49b5-4b9a-a249-197b99eb107e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71399
2155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.713992155
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.2746049642
Short name T811
Test name
Test status
Simulation time 10040780020 ps
CPU time 14.43 seconds
Started Jun 06 01:45:30 PM PDT 24
Finished Jun 06 01:45:46 PM PDT 24
Peak memory 205596 kb
Host smart-3408c81a-8ff8-44f2-a234-d7d2d9b3ebb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27460
49642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.2746049642
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.653279886
Short name T200
Test name
Test status
Simulation time 340499777 ps
CPU time 1.16 seconds
Started Jun 06 01:45:32 PM PDT 24
Finished Jun 06 01:45:34 PM PDT 24
Peak memory 221684 kb
Host smart-3cf1206f-aee7-4695-b455-09926fa266d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=653279886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.653279886
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.1193024015
Short name T2025
Test name
Test status
Simulation time 10116615455 ps
CPU time 14.16 seconds
Started Jun 06 01:45:32 PM PDT 24
Finished Jun 06 01:45:47 PM PDT 24
Peak memory 205716 kb
Host smart-41077cad-7dbc-48b2-a274-ef9409760d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11930
24015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.1193024015
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.1531559271
Short name T2005
Test name
Test status
Simulation time 10086351902 ps
CPU time 13.95 seconds
Started Jun 06 01:45:32 PM PDT 24
Finished Jun 06 01:45:47 PM PDT 24
Peak memory 205648 kb
Host smart-2ea0c81c-663f-4456-b4c2-fd008cc96a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15315
59271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.1531559271
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.303026238
Short name T140
Test name
Test status
Simulation time 10123269301 ps
CPU time 13.88 seconds
Started Jun 06 01:45:22 PM PDT 24
Finished Jun 06 01:45:37 PM PDT 24
Peak memory 205964 kb
Host smart-f06bb787-b33e-43e0-8a21-5ed44238c9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30302
6238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.303026238
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.1664435292
Short name T542
Test name
Test status
Simulation time 10089715374 ps
CPU time 13.71 seconds
Started Jun 06 01:45:32 PM PDT 24
Finished Jun 06 01:45:46 PM PDT 24
Peak memory 205728 kb
Host smart-6eb57dfd-9c23-4223-a13c-85cbda9d4f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16644
35292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.1664435292
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.1946243828
Short name T303
Test name
Test status
Simulation time 10054947746 ps
CPU time 13.86 seconds
Started Jun 06 01:45:31 PM PDT 24
Finished Jun 06 01:45:46 PM PDT 24
Peak memory 205664 kb
Host smart-84f16cbf-4616-451a-b3d2-3e537fca5b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19462
43828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1946243828
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.1870887202
Short name T988
Test name
Test status
Simulation time 14246553752 ps
CPU time 138.01 seconds
Started Jun 06 01:45:31 PM PDT 24
Finished Jun 06 01:47:50 PM PDT 24
Peak memory 205704 kb
Host smart-ec8e8fc2-43de-4e7c-bbe7-4d9fcd1f9081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18708
87202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.1870887202
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.2390459358
Short name T597
Test name
Test status
Simulation time 41752145709 ps
CPU time 209.59 seconds
Started Jun 06 01:45:33 PM PDT 24
Finished Jun 06 01:49:04 PM PDT 24
Peak memory 205760 kb
Host smart-ab831acf-812f-4113-9e3e-849878355eeb
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390459358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_
traffic.2390459358
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.364069943
Short name T1912
Test name
Test status
Simulation time 10146813326 ps
CPU time 14.9 seconds
Started Jun 06 01:51:59 PM PDT 24
Finished Jun 06 01:52:15 PM PDT 24
Peak memory 205684 kb
Host smart-1af903c5-4bbb-4bb8-a84e-1a31cacb842c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=364069943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.364069943
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.146822484
Short name T1384
Test name
Test status
Simulation time 10049726550 ps
CPU time 13.53 seconds
Started Jun 06 01:52:01 PM PDT 24
Finished Jun 06 01:52:16 PM PDT 24
Peak memory 205636 kb
Host smart-7c62e22d-1583-46cf-9798-cdfb6702d418
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=146822484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.146822484
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.1199146589
Short name T1834
Test name
Test status
Simulation time 10084466105 ps
CPU time 15.01 seconds
Started Jun 06 01:51:58 PM PDT 24
Finished Jun 06 01:52:14 PM PDT 24
Peak memory 205620 kb
Host smart-5ad51c96-4e05-489e-9f27-b2f977d6b510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11991
46589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.1199146589
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.1947557049
Short name T934
Test name
Test status
Simulation time 13596491445 ps
CPU time 19.45 seconds
Started Jun 06 01:51:50 PM PDT 24
Finished Jun 06 01:52:11 PM PDT 24
Peak memory 205700 kb
Host smart-c09b4559-0cf1-4972-a738-d4d80cef30ed
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1947557049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.1947557049
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.565745069
Short name T1684
Test name
Test status
Simulation time 23261562945 ps
CPU time 25.99 seconds
Started Jun 06 01:51:48 PM PDT 24
Finished Jun 06 01:52:15 PM PDT 24
Peak memory 205780 kb
Host smart-5279cef7-bcd9-4b28-9434-d262105dd366
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=565745069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.565745069
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.3920499085
Short name T1098
Test name
Test status
Simulation time 10079589116 ps
CPU time 13.71 seconds
Started Jun 06 01:51:50 PM PDT 24
Finished Jun 06 01:52:05 PM PDT 24
Peak memory 205596 kb
Host smart-f8dd24f9-a57f-4a34-bcb8-8d1d17dc3960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39204
99085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.3920499085
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.1484997890
Short name T767
Test name
Test status
Simulation time 10043006830 ps
CPU time 15.36 seconds
Started Jun 06 01:51:50 PM PDT 24
Finished Jun 06 01:52:07 PM PDT 24
Peak memory 205676 kb
Host smart-0ce61dd6-fbf6-4091-9ea5-0d09b9c99097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14849
97890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.1484997890
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.398388986
Short name T559
Test name
Test status
Simulation time 10189107664 ps
CPU time 14.35 seconds
Started Jun 06 01:51:53 PM PDT 24
Finished Jun 06 01:52:09 PM PDT 24
Peak memory 205684 kb
Host smart-aeff2a64-3b54-4b70-aa28-2d5c58785e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39838
8986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.398388986
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.2821078944
Short name T697
Test name
Test status
Simulation time 10059361879 ps
CPU time 13.37 seconds
Started Jun 06 01:51:52 PM PDT 24
Finished Jun 06 01:52:07 PM PDT 24
Peak memory 205724 kb
Host smart-290b69af-76ef-47de-ab72-3aaf5f44b825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28210
78944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.2821078944
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.4078132493
Short name T1161
Test name
Test status
Simulation time 10117938073 ps
CPU time 13.76 seconds
Started Jun 06 01:51:49 PM PDT 24
Finished Jun 06 01:52:04 PM PDT 24
Peak memory 205604 kb
Host smart-2807c1fa-bca7-4950-9e72-57a48b515f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40781
32493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.4078132493
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.1054061533
Short name T806
Test name
Test status
Simulation time 10760257685 ps
CPU time 15.97 seconds
Started Jun 06 01:51:47 PM PDT 24
Finished Jun 06 01:52:05 PM PDT 24
Peak memory 205656 kb
Host smart-d6527bde-b74d-4214-a99f-9055f4846b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10540
61533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.1054061533
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.1672490560
Short name T1093
Test name
Test status
Simulation time 10200739387 ps
CPU time 14.75 seconds
Started Jun 06 01:51:54 PM PDT 24
Finished Jun 06 01:52:10 PM PDT 24
Peak memory 205684 kb
Host smart-770aa756-ce2e-4769-81ba-f18cedde65c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16724
90560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1672490560
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.1825470883
Short name T1223
Test name
Test status
Simulation time 10104161166 ps
CPU time 13.82 seconds
Started Jun 06 01:51:57 PM PDT 24
Finished Jun 06 01:52:12 PM PDT 24
Peak memory 205580 kb
Host smart-d608458f-c440-4677-b79a-fce4a601113e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18254
70883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.1825470883
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.3765473056
Short name T548
Test name
Test status
Simulation time 10043815919 ps
CPU time 14.75 seconds
Started Jun 06 01:51:58 PM PDT 24
Finished Jun 06 01:52:14 PM PDT 24
Peak memory 205712 kb
Host smart-d0e20996-1a09-402c-be37-323c4ea050f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37654
73056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.3765473056
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1191391528
Short name T1067
Test name
Test status
Simulation time 10139837642 ps
CPU time 15.79 seconds
Started Jun 06 01:51:51 PM PDT 24
Finished Jun 06 01:52:08 PM PDT 24
Peak memory 205764 kb
Host smart-77eaa4ab-a34d-4260-8826-41365b1a11cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11913
91528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1191391528
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.1698662651
Short name T1768
Test name
Test status
Simulation time 10063450557 ps
CPU time 14.45 seconds
Started Jun 06 01:51:49 PM PDT 24
Finished Jun 06 01:52:05 PM PDT 24
Peak memory 205704 kb
Host smart-8ac1148d-6b77-49dd-96d2-5e656e3e4931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16986
62651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.1698662651
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.1414595017
Short name T1705
Test name
Test status
Simulation time 13195016195 ps
CPU time 15.62 seconds
Started Jun 06 01:51:55 PM PDT 24
Finished Jun 06 01:52:12 PM PDT 24
Peak memory 205680 kb
Host smart-bcbd7a61-d57b-4fd0-85f3-a5293dd0dccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14145
95017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.1414595017
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.1090137044
Short name T1019
Test name
Test status
Simulation time 10114716658 ps
CPU time 13.46 seconds
Started Jun 06 01:51:50 PM PDT 24
Finished Jun 06 01:52:05 PM PDT 24
Peak memory 205620 kb
Host smart-e4686209-e8b4-4590-92cc-02f2a8ae602a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10901
37044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1090137044
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.1701735574
Short name T753
Test name
Test status
Simulation time 15277930796 ps
CPU time 155.75 seconds
Started Jun 06 01:51:52 PM PDT 24
Finished Jun 06 01:54:29 PM PDT 24
Peak memory 205648 kb
Host smart-09eccc0b-b318-4816-bfdf-52d2e6714ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17017
35574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.1701735574
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3822771844
Short name T865
Test name
Test status
Simulation time 10056847367 ps
CPU time 13.3 seconds
Started Jun 06 01:51:53 PM PDT 24
Finished Jun 06 01:52:07 PM PDT 24
Peak memory 205652 kb
Host smart-10018f7f-9ad0-4d0b-ba4d-3aece06a3a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38227
71844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3822771844
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.31177431
Short name T738
Test name
Test status
Simulation time 10098354006 ps
CPU time 17.34 seconds
Started Jun 06 01:51:49 PM PDT 24
Finished Jun 06 01:52:08 PM PDT 24
Peak memory 205364 kb
Host smart-3409226b-5037-4c04-8a83-d8fe15ca56e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31177
431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.31177431
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.3039292180
Short name T87
Test name
Test status
Simulation time 10101977652 ps
CPU time 12.32 seconds
Started Jun 06 01:51:55 PM PDT 24
Finished Jun 06 01:52:09 PM PDT 24
Peak memory 205768 kb
Host smart-7e607f2a-71d9-4368-86e0-18ccd020fef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30392
92180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.3039292180
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2388548586
Short name T1783
Test name
Test status
Simulation time 10084188358 ps
CPU time 14.44 seconds
Started Jun 06 01:51:52 PM PDT 24
Finished Jun 06 01:52:08 PM PDT 24
Peak memory 205648 kb
Host smart-9d5ff242-b9cb-4380-9e96-9653960a8e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23885
48586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2388548586
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.608791467
Short name T1030
Test name
Test status
Simulation time 10061387701 ps
CPU time 12.74 seconds
Started Jun 06 01:51:55 PM PDT 24
Finished Jun 06 01:52:09 PM PDT 24
Peak memory 205736 kb
Host smart-265059a9-c8a2-4ea9-a0a4-dc324d2581bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60879
1467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.608791467
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.575861941
Short name T897
Test name
Test status
Simulation time 10052265936 ps
CPU time 14.86 seconds
Started Jun 06 01:52:01 PM PDT 24
Finished Jun 06 01:52:17 PM PDT 24
Peak memory 205768 kb
Host smart-7821c3e1-8702-41ab-bd31-52ec17a57b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57586
1941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.575861941
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_eop_single_bit_handling.818939002
Short name T832
Test name
Test status
Simulation time 10066511725 ps
CPU time 14.27 seconds
Started Jun 06 01:51:57 PM PDT 24
Finished Jun 06 01:52:12 PM PDT 24
Peak memory 205736 kb
Host smart-d5401c75-112e-4c3e-914d-f00f12764f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81893
9002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_eop_single_bit_handling.818939002
Directory /workspace/40.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2977354249
Short name T382
Test name
Test status
Simulation time 10043097411 ps
CPU time 13.57 seconds
Started Jun 06 01:51:57 PM PDT 24
Finished Jun 06 01:52:12 PM PDT 24
Peak memory 205636 kb
Host smart-edc73aaa-fdd5-4d65-9135-66f451377aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29773
54249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2977354249
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.2535949665
Short name T1180
Test name
Test status
Simulation time 10091813304 ps
CPU time 13.24 seconds
Started Jun 06 01:51:59 PM PDT 24
Finished Jun 06 01:52:13 PM PDT 24
Peak memory 205564 kb
Host smart-ec4d2569-358a-4cba-abab-ea16287d4c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25359
49665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.2535949665
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.2259304889
Short name T612
Test name
Test status
Simulation time 32665172027 ps
CPU time 70.94 seconds
Started Jun 06 01:51:52 PM PDT 24
Finished Jun 06 01:53:05 PM PDT 24
Peak memory 205680 kb
Host smart-dc6bdb59-1f4a-47f8-88f9-1a1e72cf3dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22593
04889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.2259304889
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2312502295
Short name T1069
Test name
Test status
Simulation time 10124937775 ps
CPU time 13.14 seconds
Started Jun 06 01:51:55 PM PDT 24
Finished Jun 06 01:52:10 PM PDT 24
Peak memory 205768 kb
Host smart-c99eab04-db0b-41f5-ac63-2b8f53c19448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23125
02295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2312502295
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.2474205485
Short name T629
Test name
Test status
Simulation time 10174278529 ps
CPU time 13.41 seconds
Started Jun 06 01:51:52 PM PDT 24
Finished Jun 06 01:52:07 PM PDT 24
Peak memory 205636 kb
Host smart-72ff8eaa-7f0a-4c29-ac31-5afa10070c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24742
05485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2474205485
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.2936476009
Short name T311
Test name
Test status
Simulation time 10059221304 ps
CPU time 12.98 seconds
Started Jun 06 01:51:59 PM PDT 24
Finished Jun 06 01:52:14 PM PDT 24
Peak memory 205736 kb
Host smart-e03155c3-042b-4f51-87f3-cc66f27bebff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29364
76009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.2936476009
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.2392169560
Short name T1082
Test name
Test status
Simulation time 10093844197 ps
CPU time 14.68 seconds
Started Jun 06 01:51:56 PM PDT 24
Finished Jun 06 01:52:12 PM PDT 24
Peak memory 205636 kb
Host smart-14063916-6e46-458a-8796-434de7bea380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23921
69560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.2392169560
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.3059664946
Short name T142
Test name
Test status
Simulation time 10070357686 ps
CPU time 12.99 seconds
Started Jun 06 01:51:56 PM PDT 24
Finished Jun 06 01:52:10 PM PDT 24
Peak memory 205704 kb
Host smart-50b0c7ae-a683-46e5-8c86-a4d8cc1fae84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30596
64946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.3059664946
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.3146164098
Short name T671
Test name
Test status
Simulation time 10050364250 ps
CPU time 13.36 seconds
Started Jun 06 01:52:01 PM PDT 24
Finished Jun 06 01:52:15 PM PDT 24
Peak memory 205680 kb
Host smart-a631e7d3-f428-47e5-b4ac-acb74385c925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31461
64098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.3146164098
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2750009504
Short name T1633
Test name
Test status
Simulation time 10131122415 ps
CPU time 14.83 seconds
Started Jun 06 01:51:50 PM PDT 24
Finished Jun 06 01:52:06 PM PDT 24
Peak memory 205696 kb
Host smart-3579d990-49c0-4d1d-a9fa-05e744e7f7af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27500
09504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2750009504
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.346943897
Short name T725
Test name
Test status
Simulation time 10098383697 ps
CPU time 12.76 seconds
Started Jun 06 01:51:58 PM PDT 24
Finished Jun 06 01:52:12 PM PDT 24
Peak memory 205648 kb
Host smart-21ff98c2-68d4-40c2-b422-128f30ad5ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34694
3897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.346943897
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1425198318
Short name T1753
Test name
Test status
Simulation time 10085261907 ps
CPU time 13.03 seconds
Started Jun 06 01:52:01 PM PDT 24
Finished Jun 06 01:52:15 PM PDT 24
Peak memory 205716 kb
Host smart-c63385de-b4f0-475d-94ce-40de85faf8d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14251
98318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1425198318
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.1739356158
Short name T1594
Test name
Test status
Simulation time 21975542957 ps
CPU time 132.92 seconds
Started Jun 06 01:52:02 PM PDT 24
Finished Jun 06 01:54:16 PM PDT 24
Peak memory 205740 kb
Host smart-1b5e95ee-54c1-4ae9-92bf-b2b3f95d94fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17393
56158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.1739356158
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.3260232469
Short name T1344
Test name
Test status
Simulation time 10154799658 ps
CPU time 13.03 seconds
Started Jun 06 01:52:20 PM PDT 24
Finished Jun 06 01:52:33 PM PDT 24
Peak memory 205720 kb
Host smart-5e6cab19-428a-41ed-962f-88151d565b95
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3260232469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.3260232469
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.1357052634
Short name T309
Test name
Test status
Simulation time 10051134883 ps
CPU time 13.49 seconds
Started Jun 06 01:52:05 PM PDT 24
Finished Jun 06 01:52:19 PM PDT 24
Peak memory 205620 kb
Host smart-f6ca934a-0683-43b6-b95c-54eea54a6f55
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1357052634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.1357052634
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.1911703757
Short name T858
Test name
Test status
Simulation time 10176376832 ps
CPU time 14.1 seconds
Started Jun 06 01:52:07 PM PDT 24
Finished Jun 06 01:52:22 PM PDT 24
Peak memory 205708 kb
Host smart-38ddbd2d-bc9f-4da8-8f2c-8fc39afebdc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19117
03757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.1911703757
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.3639868383
Short name T1533
Test name
Test status
Simulation time 14283558620 ps
CPU time 17.3 seconds
Started Jun 06 01:52:00 PM PDT 24
Finished Jun 06 01:52:18 PM PDT 24
Peak memory 205740 kb
Host smart-d6f4186f-c01b-4ad3-a403-3daa3c860550
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3639868383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.3639868383
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.3092227266
Short name T1696
Test name
Test status
Simulation time 23248841568 ps
CPU time 22.81 seconds
Started Jun 06 01:51:59 PM PDT 24
Finished Jun 06 01:52:23 PM PDT 24
Peak memory 205728 kb
Host smart-c8be04a2-4b36-4856-ba08-f77db830e158
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3092227266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.3092227266
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1041852412
Short name T1943
Test name
Test status
Simulation time 10063658356 ps
CPU time 15.15 seconds
Started Jun 06 01:51:56 PM PDT 24
Finished Jun 06 01:52:13 PM PDT 24
Peak memory 205632 kb
Host smart-6dfbdeb0-6119-4a6f-bce9-22dc65f711d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10418
52412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1041852412
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.1257665742
Short name T177
Test name
Test status
Simulation time 10768415671 ps
CPU time 15.42 seconds
Started Jun 06 01:52:01 PM PDT 24
Finished Jun 06 01:52:17 PM PDT 24
Peak memory 205712 kb
Host smart-cd748e42-483b-4cd9-a754-92eb43a9ecc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12576
65742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.1257665742
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.1422192043
Short name T1
Test name
Test status
Simulation time 10061611884 ps
CPU time 13.25 seconds
Started Jun 06 01:52:06 PM PDT 24
Finished Jun 06 01:52:20 PM PDT 24
Peak memory 205664 kb
Host smart-867bbd89-58e0-4c7f-be26-0957813a2c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14221
92043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.1422192043
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.694940655
Short name T1478
Test name
Test status
Simulation time 10052898674 ps
CPU time 16.63 seconds
Started Jun 06 01:52:00 PM PDT 24
Finished Jun 06 01:52:18 PM PDT 24
Peak memory 205660 kb
Host smart-969b5c84-9401-4205-ae80-912664dcf901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69494
0655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.694940655
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.3315418813
Short name T680
Test name
Test status
Simulation time 10609151735 ps
CPU time 15.31 seconds
Started Jun 06 01:51:56 PM PDT 24
Finished Jun 06 01:52:13 PM PDT 24
Peak memory 205608 kb
Host smart-8860b2ae-7c10-4f2b-9d31-82676b556ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33154
18813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.3315418813
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3332905944
Short name T1603
Test name
Test status
Simulation time 10081596396 ps
CPU time 16.22 seconds
Started Jun 06 01:51:59 PM PDT 24
Finished Jun 06 01:52:17 PM PDT 24
Peak memory 205604 kb
Host smart-0ea5e76e-ff08-4191-8e3e-d4b859107ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33329
05944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3332905944
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.983000865
Short name T721
Test name
Test status
Simulation time 10081096446 ps
CPU time 14.88 seconds
Started Jun 06 01:52:05 PM PDT 24
Finished Jun 06 01:52:21 PM PDT 24
Peak memory 205656 kb
Host smart-e88efad5-ee2c-4791-8497-7119a8893ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98300
0865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.983000865
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2516171733
Short name T1252
Test name
Test status
Simulation time 10054042724 ps
CPU time 13.23 seconds
Started Jun 06 01:52:14 PM PDT 24
Finished Jun 06 01:52:28 PM PDT 24
Peak memory 205748 kb
Host smart-70f0e899-4e19-4c61-82e7-00b83bd4780f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25161
71733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2516171733
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.1652445624
Short name T1434
Test name
Test status
Simulation time 10094025151 ps
CPU time 14.18 seconds
Started Jun 06 01:52:02 PM PDT 24
Finished Jun 06 01:52:17 PM PDT 24
Peak memory 205764 kb
Host smart-49462c4f-0cb1-4e51-825b-f62476ccc686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16524
45624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1652445624
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.1447357554
Short name T1915
Test name
Test status
Simulation time 10066470371 ps
CPU time 13.61 seconds
Started Jun 06 01:51:55 PM PDT 24
Finished Jun 06 01:52:10 PM PDT 24
Peak memory 205656 kb
Host smart-e3d6afe6-e54d-4635-926d-5d1cdcab965a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14473
57554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.1447357554
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.172175323
Short name T508
Test name
Test status
Simulation time 13243992766 ps
CPU time 18.31 seconds
Started Jun 06 01:51:58 PM PDT 24
Finished Jun 06 01:52:18 PM PDT 24
Peak memory 205672 kb
Host smart-7c8816fd-c7a6-4e00-aac7-abdd073061db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17217
5323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.172175323
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.2735269722
Short name T1145
Test name
Test status
Simulation time 10092342592 ps
CPU time 13.7 seconds
Started Jun 06 01:52:07 PM PDT 24
Finished Jun 06 01:52:22 PM PDT 24
Peak memory 206016 kb
Host smart-195d9971-d466-4037-a58d-8ae747c078df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27352
69722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.2735269722
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.680603151
Short name T1454
Test name
Test status
Simulation time 15560687872 ps
CPU time 49.69 seconds
Started Jun 06 01:52:08 PM PDT 24
Finished Jun 06 01:52:59 PM PDT 24
Peak memory 205700 kb
Host smart-eaacaad8-7a53-47cb-9b76-13291b7aaf49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68060
3151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.680603151
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.2440416551
Short name T1316
Test name
Test status
Simulation time 10047414479 ps
CPU time 13.11 seconds
Started Jun 06 01:52:10 PM PDT 24
Finished Jun 06 01:52:24 PM PDT 24
Peak memory 205680 kb
Host smart-9b6b11c6-7567-4d80-952e-cd6a6910da06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24404
16551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.2440416551
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.1791935907
Short name T2
Test name
Test status
Simulation time 10116924141 ps
CPU time 14.22 seconds
Started Jun 06 01:52:31 PM PDT 24
Finished Jun 06 01:52:46 PM PDT 24
Peak memory 205676 kb
Host smart-3670bc87-fba1-4104-9230-295c9fa3dd45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17919
35907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1791935907
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.750160824
Short name T434
Test name
Test status
Simulation time 10091267634 ps
CPU time 15.95 seconds
Started Jun 06 01:52:11 PM PDT 24
Finished Jun 06 01:52:28 PM PDT 24
Peak memory 205716 kb
Host smart-1566dbb8-5343-4887-bd42-f1f5452b3fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75016
0824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.750160824
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.4072270489
Short name T431
Test name
Test status
Simulation time 10078489174 ps
CPU time 13.68 seconds
Started Jun 06 01:52:07 PM PDT 24
Finished Jun 06 01:52:22 PM PDT 24
Peak memory 205680 kb
Host smart-ac651b67-408a-48a3-82c6-a34933f6a79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40722
70489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.4072270489
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3933971803
Short name T1189
Test name
Test status
Simulation time 10081253874 ps
CPU time 15.54 seconds
Started Jun 06 01:52:10 PM PDT 24
Finished Jun 06 01:52:27 PM PDT 24
Peak memory 205736 kb
Host smart-3889c15c-4b7b-4005-a914-7d6c7806aa96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39339
71803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3933971803
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.206731944
Short name T154
Test name
Test status
Simulation time 10057668597 ps
CPU time 15.02 seconds
Started Jun 06 01:52:10 PM PDT 24
Finished Jun 06 01:52:26 PM PDT 24
Peak memory 205632 kb
Host smart-723f45a1-767b-40bb-bd4f-4f1df438044e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20673
1944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.206731944
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_eop_single_bit_handling.1815655137
Short name T1896
Test name
Test status
Simulation time 10057815786 ps
CPU time 13.94 seconds
Started Jun 06 01:52:07 PM PDT 24
Finished Jun 06 01:52:22 PM PDT 24
Peak memory 205660 kb
Host smart-c3f74354-bed2-4092-824d-efef53d3db4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18156
55137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_eop_single_bit_handling.1815655137
Directory /workspace/41.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.1611887550
Short name T979
Test name
Test status
Simulation time 10045533283 ps
CPU time 12.91 seconds
Started Jun 06 01:52:10 PM PDT 24
Finished Jun 06 01:52:24 PM PDT 24
Peak memory 205640 kb
Host smart-b45f8b25-bc43-4b8c-9b5e-487c9f16f15e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16118
87550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.1611887550
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.818259676
Short name T676
Test name
Test status
Simulation time 10048948582 ps
CPU time 13.08 seconds
Started Jun 06 01:52:06 PM PDT 24
Finished Jun 06 01:52:20 PM PDT 24
Peak memory 205628 kb
Host smart-63f2eb31-6853-47f7-a9a8-34f87751bb6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81825
9676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.818259676
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1694948633
Short name T497
Test name
Test status
Simulation time 26055165752 ps
CPU time 52.73 seconds
Started Jun 06 01:52:07 PM PDT 24
Finished Jun 06 01:53:01 PM PDT 24
Peak memory 205652 kb
Host smart-d95442b2-4090-499d-addf-1def6336535a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16949
48633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1694948633
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.803936970
Short name T533
Test name
Test status
Simulation time 10089860673 ps
CPU time 14.43 seconds
Started Jun 06 01:52:09 PM PDT 24
Finished Jun 06 01:52:24 PM PDT 24
Peak memory 205676 kb
Host smart-9ea918e3-46fe-472d-bcb2-f5884480c850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80393
6970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.803936970
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.1973844924
Short name T1828
Test name
Test status
Simulation time 10144793222 ps
CPU time 13.97 seconds
Started Jun 06 01:52:08 PM PDT 24
Finished Jun 06 01:52:23 PM PDT 24
Peak memory 205692 kb
Host smart-12073a6e-beee-48a5-b0e4-591a095e5d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19738
44924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.1973844924
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.1773936079
Short name T678
Test name
Test status
Simulation time 10061674499 ps
CPU time 14.96 seconds
Started Jun 06 01:52:04 PM PDT 24
Finished Jun 06 01:52:19 PM PDT 24
Peak memory 205752 kb
Host smart-b62640cc-449b-415f-9ab6-d035f3c51f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17739
36079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.1773936079
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.3594977814
Short name T1711
Test name
Test status
Simulation time 10044249422 ps
CPU time 14.26 seconds
Started Jun 06 01:52:11 PM PDT 24
Finished Jun 06 01:52:26 PM PDT 24
Peak memory 205696 kb
Host smart-8b79d580-baea-4f76-872f-886c0a067bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35949
77814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.3594977814
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.767996023
Short name T1313
Test name
Test status
Simulation time 10092391382 ps
CPU time 13.59 seconds
Started Jun 06 01:52:08 PM PDT 24
Finished Jun 06 01:52:22 PM PDT 24
Peak memory 205708 kb
Host smart-b6d261e1-059b-4a84-a632-110a2751be65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76799
6023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.767996023
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.2043516880
Short name T75
Test name
Test status
Simulation time 10066639119 ps
CPU time 13.16 seconds
Started Jun 06 01:52:07 PM PDT 24
Finished Jun 06 01:52:21 PM PDT 24
Peak memory 205704 kb
Host smart-cbcca725-b23f-445f-b909-59b8b464a209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20435
16880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.2043516880
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.869065157
Short name T816
Test name
Test status
Simulation time 10125666174 ps
CPU time 13.18 seconds
Started Jun 06 01:51:58 PM PDT 24
Finished Jun 06 01:52:13 PM PDT 24
Peak memory 205632 kb
Host smart-a05dd167-422b-4b17-b832-6ee373b9abee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86906
5157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.869065157
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.1332537229
Short name T510
Test name
Test status
Simulation time 10058152260 ps
CPU time 12.86 seconds
Started Jun 06 01:52:09 PM PDT 24
Finished Jun 06 01:52:23 PM PDT 24
Peak memory 205672 kb
Host smart-a0efc244-65d2-445e-aa4e-4c3f463631c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13325
37229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.1332537229
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.1454711056
Short name T564
Test name
Test status
Simulation time 10096790043 ps
CPU time 17.29 seconds
Started Jun 06 01:52:08 PM PDT 24
Finished Jun 06 01:52:26 PM PDT 24
Peak memory 205680 kb
Host smart-a31e8158-de7c-4fbd-b7ce-ea23f55dbd31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14547
11056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.1454711056
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.3048710145
Short name T1408
Test name
Test status
Simulation time 21372409555 ps
CPU time 92.41 seconds
Started Jun 06 01:52:11 PM PDT 24
Finished Jun 06 01:53:44 PM PDT 24
Peak memory 205732 kb
Host smart-2ab88e90-e4e2-4b11-bc94-e0218aef19fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30487
10145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.3048710145
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.3783848813
Short name T1243
Test name
Test status
Simulation time 10140749272 ps
CPU time 15.98 seconds
Started Jun 06 01:52:14 PM PDT 24
Finished Jun 06 01:52:31 PM PDT 24
Peak memory 205704 kb
Host smart-5eb15a1f-1e05-483d-9a27-d474fc57540f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3783848813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.3783848813
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.3246834246
Short name T1924
Test name
Test status
Simulation time 10072390634 ps
CPU time 17.03 seconds
Started Jun 06 01:52:31 PM PDT 24
Finished Jun 06 01:52:49 PM PDT 24
Peak memory 205692 kb
Host smart-76d4522f-592a-4771-a3ba-d1468fb7a4ba
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3246834246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.3246834246
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.2544802549
Short name T1798
Test name
Test status
Simulation time 10135290204 ps
CPU time 13.2 seconds
Started Jun 06 01:52:10 PM PDT 24
Finished Jun 06 01:52:24 PM PDT 24
Peak memory 205696 kb
Host smart-3601719f-6320-42f0-ac09-e68734639dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25448
02549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.2544802549
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.2718428661
Short name T739
Test name
Test status
Simulation time 13972283227 ps
CPU time 17.62 seconds
Started Jun 06 01:52:04 PM PDT 24
Finished Jun 06 01:52:22 PM PDT 24
Peak memory 205736 kb
Host smart-b9444246-aaf7-4dcb-933b-fbca992914d2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2718428661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.2718428661
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.3050642352
Short name T701
Test name
Test status
Simulation time 23323862320 ps
CPU time 25.2 seconds
Started Jun 06 01:52:12 PM PDT 24
Finished Jun 06 01:52:38 PM PDT 24
Peak memory 205656 kb
Host smart-b14f29b0-39dd-491b-823e-f09a75dfa9d9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3050642352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3050642352
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.3449110178
Short name T1374
Test name
Test status
Simulation time 10059016611 ps
CPU time 12.79 seconds
Started Jun 06 01:52:10 PM PDT 24
Finished Jun 06 01:52:24 PM PDT 24
Peak memory 205688 kb
Host smart-95ea719a-e36c-4c77-822e-7c6e45828b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34491
10178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3449110178
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.3594829249
Short name T1168
Test name
Test status
Simulation time 10845890345 ps
CPU time 14.03 seconds
Started Jun 06 01:52:07 PM PDT 24
Finished Jun 06 01:52:21 PM PDT 24
Peak memory 205640 kb
Host smart-a59e622e-5022-4dae-89d0-8839cd0f2009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35948
29249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.3594829249
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.3780084698
Short name T419
Test name
Test status
Simulation time 10062078516 ps
CPU time 13.01 seconds
Started Jun 06 01:52:10 PM PDT 24
Finished Jun 06 01:52:24 PM PDT 24
Peak memory 205624 kb
Host smart-004a95d2-6834-428d-8115-8cc7dd7c87c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37800
84698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.3780084698
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.1066570492
Short name T1720
Test name
Test status
Simulation time 10053499854 ps
CPU time 13.9 seconds
Started Jun 06 01:52:10 PM PDT 24
Finished Jun 06 01:52:25 PM PDT 24
Peak memory 205680 kb
Host smart-b48a7fd5-9a67-429f-9a15-e0ede506984e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10665
70492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1066570492
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.3586670959
Short name T1008
Test name
Test status
Simulation time 10636359852 ps
CPU time 14.91 seconds
Started Jun 06 01:52:05 PM PDT 24
Finished Jun 06 01:52:20 PM PDT 24
Peak memory 205740 kb
Host smart-331945dd-4ce3-42ce-ba03-5a71e35491c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35866
70959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.3586670959
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.314739815
Short name T1111
Test name
Test status
Simulation time 10137921879 ps
CPU time 14.45 seconds
Started Jun 06 01:52:09 PM PDT 24
Finished Jun 06 01:52:24 PM PDT 24
Peak memory 205736 kb
Host smart-60f31730-3c55-418f-be2d-f96b0856b659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31473
9815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.314739815
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.486131531
Short name T1217
Test name
Test status
Simulation time 10092399740 ps
CPU time 14.11 seconds
Started Jun 06 01:52:10 PM PDT 24
Finished Jun 06 01:52:25 PM PDT 24
Peak memory 205760 kb
Host smart-fabee227-e390-458b-b15f-2987af190e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48613
1531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.486131531
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.2262956888
Short name T662
Test name
Test status
Simulation time 10057530442 ps
CPU time 14.22 seconds
Started Jun 06 01:52:07 PM PDT 24
Finished Jun 06 01:52:22 PM PDT 24
Peak memory 205668 kb
Host smart-31eb4a45-e206-457b-a900-baf2fafff973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22629
56888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2262956888
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1287410735
Short name T514
Test name
Test status
Simulation time 10109002935 ps
CPU time 13.06 seconds
Started Jun 06 01:52:14 PM PDT 24
Finished Jun 06 01:52:28 PM PDT 24
Peak memory 205780 kb
Host smart-7f4687aa-0046-457a-a46a-ac6a894e687b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12874
10735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1287410735
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.1267304623
Short name T495
Test name
Test status
Simulation time 10061426333 ps
CPU time 16.07 seconds
Started Jun 06 01:52:17 PM PDT 24
Finished Jun 06 01:52:34 PM PDT 24
Peak memory 205728 kb
Host smart-c0fdd3fa-2298-4b2c-bf12-1092f718a0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12673
04623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.1267304623
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1975843263
Short name T694
Test name
Test status
Simulation time 13229721325 ps
CPU time 19.36 seconds
Started Jun 06 01:52:07 PM PDT 24
Finished Jun 06 01:52:27 PM PDT 24
Peak memory 205680 kb
Host smart-711a30f4-0928-40fc-895e-f7077ef31084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19758
43263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1975843263
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.221410480
Short name T209
Test name
Test status
Simulation time 10115334358 ps
CPU time 14.29 seconds
Started Jun 06 01:52:12 PM PDT 24
Finished Jun 06 01:52:27 PM PDT 24
Peak memory 205748 kb
Host smart-07ea915f-a536-4621-8dd4-a764746c7459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22141
0480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.221410480
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.3769690288
Short name T1496
Test name
Test status
Simulation time 24216034197 ps
CPU time 143.32 seconds
Started Jun 06 01:52:08 PM PDT 24
Finished Jun 06 01:54:32 PM PDT 24
Peak memory 205768 kb
Host smart-c74d6c2b-f758-4e93-ab22-e8adef4375d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37696
90288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.3769690288
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.4000124744
Short name T1993
Test name
Test status
Simulation time 10050104372 ps
CPU time 14.11 seconds
Started Jun 06 01:52:10 PM PDT 24
Finished Jun 06 01:52:25 PM PDT 24
Peak memory 205696 kb
Host smart-f5d65862-4e8d-47a1-94f5-6d5e823298de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40001
24744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.4000124744
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.1651090438
Short name T404
Test name
Test status
Simulation time 10118226905 ps
CPU time 13.38 seconds
Started Jun 06 01:52:12 PM PDT 24
Finished Jun 06 01:52:26 PM PDT 24
Peak memory 205400 kb
Host smart-b636866e-479c-4516-b681-bdc68ce7fa14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16510
90438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1651090438
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.2898897882
Short name T1037
Test name
Test status
Simulation time 10092267305 ps
CPU time 13.37 seconds
Started Jun 06 01:52:09 PM PDT 24
Finished Jun 06 01:52:24 PM PDT 24
Peak memory 205628 kb
Host smart-a034bc68-b72e-4f7b-950e-03df46068843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28988
97882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.2898897882
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.2475831892
Short name T751
Test name
Test status
Simulation time 10064771889 ps
CPU time 14.3 seconds
Started Jun 06 01:52:12 PM PDT 24
Finished Jun 06 01:52:27 PM PDT 24
Peak memory 205612 kb
Host smart-bd312881-40fb-4a35-ad1a-074d42728bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24758
31892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.2475831892
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.2864553899
Short name T1520
Test name
Test status
Simulation time 10058297293 ps
CPU time 13.44 seconds
Started Jun 06 01:52:07 PM PDT 24
Finished Jun 06 01:52:22 PM PDT 24
Peak memory 205652 kb
Host smart-34f2469c-ad24-4716-99a5-1be8aed09bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28645
53899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2864553899
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3847018458
Short name T1399
Test name
Test status
Simulation time 10104552784 ps
CPU time 13.36 seconds
Started Jun 06 01:52:09 PM PDT 24
Finished Jun 06 01:52:24 PM PDT 24
Peak memory 205576 kb
Host smart-9e2af570-fa3d-4fa3-b42e-99db1710178f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38470
18458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3847018458
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_eop_single_bit_handling.3048853658
Short name T453
Test name
Test status
Simulation time 10062696586 ps
CPU time 13.44 seconds
Started Jun 06 01:52:17 PM PDT 24
Finished Jun 06 01:52:32 PM PDT 24
Peak memory 205620 kb
Host smart-1548f973-f8a4-4be1-9a5f-8bd4b8ccdda3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30488
53658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_eop_single_bit_handling.3048853658
Directory /workspace/42.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.906172119
Short name T1853
Test name
Test status
Simulation time 10087367608 ps
CPU time 13.64 seconds
Started Jun 06 01:52:08 PM PDT 24
Finished Jun 06 01:52:23 PM PDT 24
Peak memory 205656 kb
Host smart-e1c27143-c983-46b1-899f-e85066d86285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90617
2119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.906172119
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.3427374828
Short name T1645
Test name
Test status
Simulation time 10055455040 ps
CPU time 13.79 seconds
Started Jun 06 01:52:06 PM PDT 24
Finished Jun 06 01:52:21 PM PDT 24
Peak memory 205696 kb
Host smart-36ada22e-0fd8-4d20-bd01-872da6d8b00a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34273
74828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.3427374828
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.4189780616
Short name T1879
Test name
Test status
Simulation time 29841782134 ps
CPU time 53.65 seconds
Started Jun 06 01:52:20 PM PDT 24
Finished Jun 06 01:53:14 PM PDT 24
Peak memory 205700 kb
Host smart-39a156c5-f573-4aef-9b6f-28d27de6ae3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41897
80616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.4189780616
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.1558167620
Short name T709
Test name
Test status
Simulation time 10063007521 ps
CPU time 13.03 seconds
Started Jun 06 01:52:14 PM PDT 24
Finished Jun 06 01:52:28 PM PDT 24
Peak memory 205668 kb
Host smart-6d50fb52-b785-4bbd-8fef-5df142d76056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15581
67620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.1558167620
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2110687999
Short name T529
Test name
Test status
Simulation time 10140071650 ps
CPU time 16.34 seconds
Started Jun 06 01:52:17 PM PDT 24
Finished Jun 06 01:52:34 PM PDT 24
Peak memory 205728 kb
Host smart-54f0c114-641d-492d-ad09-f04c56882460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21106
87999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2110687999
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.1003815176
Short name T1874
Test name
Test status
Simulation time 10084407961 ps
CPU time 12.76 seconds
Started Jun 06 01:52:20 PM PDT 24
Finished Jun 06 01:52:33 PM PDT 24
Peak memory 205704 kb
Host smart-cfbcccbd-9bf1-4aca-b8a6-64d96e1c8fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10038
15176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.1003815176
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1405898110
Short name T1652
Test name
Test status
Simulation time 10044157102 ps
CPU time 13.54 seconds
Started Jun 06 01:52:09 PM PDT 24
Finished Jun 06 01:52:24 PM PDT 24
Peak memory 205628 kb
Host smart-578b379c-e635-43cd-8c39-4af56f69155b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14058
98110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1405898110
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.2827396658
Short name T163
Test name
Test status
Simulation time 10056744647 ps
CPU time 15.16 seconds
Started Jun 06 01:52:04 PM PDT 24
Finished Jun 06 01:52:20 PM PDT 24
Peak memory 205756 kb
Host smart-f879e04c-2dd5-4f55-a45e-dfd3c6469e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28273
96658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.2827396658
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.3112463546
Short name T54
Test name
Test status
Simulation time 10095401057 ps
CPU time 12.45 seconds
Started Jun 06 01:52:08 PM PDT 24
Finished Jun 06 01:52:21 PM PDT 24
Peak memory 205720 kb
Host smart-6ac9df45-1bc4-435a-8f55-1b4a3b54e84f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31124
63546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.3112463546
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.3597017745
Short name T1330
Test name
Test status
Simulation time 10144002322 ps
CPU time 12.86 seconds
Started Jun 06 01:52:09 PM PDT 24
Finished Jun 06 01:52:23 PM PDT 24
Peak memory 205724 kb
Host smart-08889b9c-a90f-4c1e-8ddd-bbd09711556b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35970
17745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3597017745
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.3558421443
Short name T1499
Test name
Test status
Simulation time 10110697686 ps
CPU time 15.09 seconds
Started Jun 06 01:52:12 PM PDT 24
Finished Jun 06 01:52:28 PM PDT 24
Peak memory 205732 kb
Host smart-6e033052-af05-4dcf-be07-76fe06caf9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35584
21443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.3558421443
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.19628451
Short name T1209
Test name
Test status
Simulation time 10082445259 ps
CPU time 15.89 seconds
Started Jun 06 01:52:07 PM PDT 24
Finished Jun 06 01:52:25 PM PDT 24
Peak memory 205788 kb
Host smart-0b663414-fbed-4561-b7ea-8bdff4dad25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19628
451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.19628451
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.2706959399
Short name T1984
Test name
Test status
Simulation time 17939846422 ps
CPU time 92.34 seconds
Started Jun 06 01:52:06 PM PDT 24
Finished Jun 06 01:53:39 PM PDT 24
Peak memory 205780 kb
Host smart-2c2fff62-90c4-4599-b4b4-f5d5e2bce2dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27069
59399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.2706959399
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.3144438141
Short name T305
Test name
Test status
Simulation time 10145711380 ps
CPU time 14.63 seconds
Started Jun 06 01:52:24 PM PDT 24
Finished Jun 06 01:52:39 PM PDT 24
Peak memory 205648 kb
Host smart-b7baaed7-4a04-4a5f-9ebf-bb047847c2ab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3144438141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.3144438141
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.3949122678
Short name T1482
Test name
Test status
Simulation time 10064275328 ps
CPU time 14.17 seconds
Started Jun 06 01:52:24 PM PDT 24
Finished Jun 06 01:52:39 PM PDT 24
Peak memory 205936 kb
Host smart-0f0ec577-0ca2-4549-8a78-77db43f010e5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3949122678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.3949122678
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.3816717852
Short name T852
Test name
Test status
Simulation time 10200127670 ps
CPU time 12.9 seconds
Started Jun 06 01:52:32 PM PDT 24
Finished Jun 06 01:52:46 PM PDT 24
Peak memory 205648 kb
Host smart-9c81f07e-a744-4c9a-a94d-e03f1c245d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38167
17852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.3816717852
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.3391817582
Short name T1716
Test name
Test status
Simulation time 14011878986 ps
CPU time 20.56 seconds
Started Jun 06 01:52:18 PM PDT 24
Finished Jun 06 01:52:40 PM PDT 24
Peak memory 205668 kb
Host smart-d80a8221-09d5-4d60-bace-401991347177
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3391817582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.3391817582
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.1448633143
Short name T1259
Test name
Test status
Simulation time 23364709357 ps
CPU time 24.4 seconds
Started Jun 06 01:52:20 PM PDT 24
Finished Jun 06 01:52:45 PM PDT 24
Peak memory 205752 kb
Host smart-7ceb006c-863b-4680-accf-13ac6448e209
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1448633143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.1448633143
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.940907649
Short name T18
Test name
Test status
Simulation time 10058194518 ps
CPU time 13.28 seconds
Started Jun 06 01:52:17 PM PDT 24
Finished Jun 06 01:52:31 PM PDT 24
Peak memory 205768 kb
Host smart-7f5c710f-c9ee-4a1d-851b-12b97af397e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94090
7649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.940907649
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.531840572
Short name T169
Test name
Test status
Simulation time 11077501586 ps
CPU time 14.48 seconds
Started Jun 06 01:52:14 PM PDT 24
Finished Jun 06 01:52:29 PM PDT 24
Peak memory 205708 kb
Host smart-4395fb17-b351-404f-bca2-1235396ce2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53184
0572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.531840572
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.3949892333
Short name T997
Test name
Test status
Simulation time 10047360244 ps
CPU time 13.49 seconds
Started Jun 06 01:52:12 PM PDT 24
Finished Jun 06 01:52:27 PM PDT 24
Peak memory 205696 kb
Host smart-487d05fc-87fa-4156-aab1-d4ae5b2066b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39498
92333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.3949892333
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.606392648
Short name T1112
Test name
Test status
Simulation time 10064878832 ps
CPU time 12.45 seconds
Started Jun 06 01:52:13 PM PDT 24
Finished Jun 06 01:52:26 PM PDT 24
Peak memory 205708 kb
Host smart-d50a7e3b-93e2-4a55-adbf-468126e4905f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60639
2648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.606392648
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.4251493148
Short name T375
Test name
Test status
Simulation time 10882300599 ps
CPU time 14.7 seconds
Started Jun 06 01:52:20 PM PDT 24
Finished Jun 06 01:52:36 PM PDT 24
Peak memory 205780 kb
Host smart-50c94a9b-e3c4-4649-8f03-a577e589d7aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42514
93148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.4251493148
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.263290002
Short name T796
Test name
Test status
Simulation time 10147152601 ps
CPU time 16.61 seconds
Started Jun 06 01:52:14 PM PDT 24
Finished Jun 06 01:52:31 PM PDT 24
Peak memory 205640 kb
Host smart-28a78d6c-5c02-4abb-be3d-8b87fdaac0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26329
0002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.263290002
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.3201176417
Short name T905
Test name
Test status
Simulation time 10135527196 ps
CPU time 13.32 seconds
Started Jun 06 01:52:23 PM PDT 24
Finished Jun 06 01:52:36 PM PDT 24
Peak memory 205604 kb
Host smart-06bd958e-d530-4a4f-be0b-b84e21441e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32011
76417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.3201176417
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.3483852334
Short name T959
Test name
Test status
Simulation time 10041954420 ps
CPU time 12.95 seconds
Started Jun 06 01:52:31 PM PDT 24
Finished Jun 06 01:52:44 PM PDT 24
Peak memory 205600 kb
Host smart-be2310af-99f4-420d-a235-5f6a1df09444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34838
52334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.3483852334
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.558000118
Short name T342
Test name
Test status
Simulation time 10141887817 ps
CPU time 14.85 seconds
Started Jun 06 01:52:13 PM PDT 24
Finished Jun 06 01:52:29 PM PDT 24
Peak memory 205636 kb
Host smart-1f4ccded-fa0c-4b0e-94c0-4c58cb098f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55800
0118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.558000118
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.2996506660
Short name T951
Test name
Test status
Simulation time 10168852958 ps
CPU time 13.67 seconds
Started Jun 06 01:52:13 PM PDT 24
Finished Jun 06 01:52:27 PM PDT 24
Peak memory 205736 kb
Host smart-232aeb52-5e2e-4a93-9650-1ec7931468eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29965
06660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.2996506660
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.409507154
Short name T1947
Test name
Test status
Simulation time 13196230468 ps
CPU time 16.61 seconds
Started Jun 06 01:52:14 PM PDT 24
Finished Jun 06 01:52:31 PM PDT 24
Peak memory 205600 kb
Host smart-1d027885-a395-4e21-8d33-dcaa3a75b2d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40950
7154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.409507154
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2179411120
Short name T962
Test name
Test status
Simulation time 10083430376 ps
CPU time 14.52 seconds
Started Jun 06 01:52:11 PM PDT 24
Finished Jun 06 01:52:27 PM PDT 24
Peak memory 205580 kb
Host smart-7dce8895-3066-4861-b2e5-b5aae46bb3a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21794
11120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2179411120
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.3583609330
Short name T1661
Test name
Test status
Simulation time 17522359107 ps
CPU time 88.67 seconds
Started Jun 06 01:52:14 PM PDT 24
Finished Jun 06 01:53:43 PM PDT 24
Peak memory 205816 kb
Host smart-b345d2a6-8993-4a93-a713-c1470008b757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35836
09330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.3583609330
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.156914947
Short name T838
Test name
Test status
Simulation time 10048054166 ps
CPU time 13.99 seconds
Started Jun 06 01:52:17 PM PDT 24
Finished Jun 06 01:52:32 PM PDT 24
Peak memory 205736 kb
Host smart-2d9bbdd9-070c-494e-9126-6369334f1db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15691
4947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.156914947
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.2619932303
Short name T1714
Test name
Test status
Simulation time 10128603767 ps
CPU time 13.32 seconds
Started Jun 06 01:52:19 PM PDT 24
Finished Jun 06 01:52:33 PM PDT 24
Peak memory 205620 kb
Host smart-9815a546-9693-4fdb-aea5-f78ed22bedca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26199
32303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2619932303
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.1894753157
Short name T1963
Test name
Test status
Simulation time 10149322550 ps
CPU time 14.9 seconds
Started Jun 06 01:52:17 PM PDT 24
Finished Jun 06 01:52:33 PM PDT 24
Peak memory 205736 kb
Host smart-304910fb-7965-4c92-97d7-f07a83e1383e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18947
53157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.1894753157
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.3364451169
Short name T1681
Test name
Test status
Simulation time 10051505795 ps
CPU time 15.99 seconds
Started Jun 06 01:52:32 PM PDT 24
Finished Jun 06 01:52:49 PM PDT 24
Peak memory 205672 kb
Host smart-74268c16-a405-4798-aa07-a56a7a69b303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33644
51169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.3364451169
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.1759731173
Short name T1737
Test name
Test status
Simulation time 10094113563 ps
CPU time 13.11 seconds
Started Jun 06 01:52:18 PM PDT 24
Finished Jun 06 01:52:32 PM PDT 24
Peak memory 205728 kb
Host smart-2c80270c-5c35-474e-a7b4-54604ac1105b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17597
31173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.1759731173
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.2688997221
Short name T160
Test name
Test status
Simulation time 10063200297 ps
CPU time 14.97 seconds
Started Jun 06 01:52:23 PM PDT 24
Finished Jun 06 01:52:39 PM PDT 24
Peak memory 205660 kb
Host smart-37827356-ebd1-4c92-942b-2f48e0ed7e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26889
97221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.2688997221
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_eop_single_bit_handling.1613479266
Short name T1839
Test name
Test status
Simulation time 10083809928 ps
CPU time 14.47 seconds
Started Jun 06 01:52:31 PM PDT 24
Finished Jun 06 01:52:46 PM PDT 24
Peak memory 205752 kb
Host smart-4395ba28-9834-4e78-8270-adf073ab0fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16134
79266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_eop_single_bit_handling.1613479266
Directory /workspace/43.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.2618486763
Short name T84
Test name
Test status
Simulation time 10050714493 ps
CPU time 16.18 seconds
Started Jun 06 01:52:20 PM PDT 24
Finished Jun 06 01:52:37 PM PDT 24
Peak memory 205764 kb
Host smart-82dd137b-c3f9-4f0f-ad81-dcf2482d28ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26184
86763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.2618486763
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.3915810591
Short name T1869
Test name
Test status
Simulation time 10039160983 ps
CPU time 13.17 seconds
Started Jun 06 01:52:22 PM PDT 24
Finished Jun 06 01:52:36 PM PDT 24
Peak memory 205644 kb
Host smart-b8b677be-3b8f-4058-b88e-7fd5a4e66bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39158
10591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.3915810591
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.1612510706
Short name T1471
Test name
Test status
Simulation time 20293345005 ps
CPU time 37.18 seconds
Started Jun 06 01:52:13 PM PDT 24
Finished Jun 06 01:52:51 PM PDT 24
Peak memory 205676 kb
Host smart-b555df97-37ae-4429-bc76-2f9c1133a4c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16125
10706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.1612510706
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.891492982
Short name T1560
Test name
Test status
Simulation time 10133315497 ps
CPU time 13.65 seconds
Started Jun 06 01:52:20 PM PDT 24
Finished Jun 06 01:52:34 PM PDT 24
Peak memory 205740 kb
Host smart-9d97f93f-c0de-4b6f-b7c3-4e71e25367f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89149
2982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.891492982
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3728801584
Short name T737
Test name
Test status
Simulation time 10148928566 ps
CPU time 17.56 seconds
Started Jun 06 01:52:30 PM PDT 24
Finished Jun 06 01:52:48 PM PDT 24
Peak memory 205564 kb
Host smart-d05988ab-bc22-4cbb-8e1f-a3ce04fd1d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37288
01584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3728801584
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.950913471
Short name T756
Test name
Test status
Simulation time 10141109601 ps
CPU time 13.1 seconds
Started Jun 06 01:52:13 PM PDT 24
Finished Jun 06 01:52:26 PM PDT 24
Peak memory 205652 kb
Host smart-7c948602-bce4-4483-82d9-9cbb9133798c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95091
3471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.950913471
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.3029576020
Short name T938
Test name
Test status
Simulation time 10045601244 ps
CPU time 16.51 seconds
Started Jun 06 01:52:14 PM PDT 24
Finished Jun 06 01:52:31 PM PDT 24
Peak memory 205736 kb
Host smart-ed363ff7-e607-401a-ae99-fde997590b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30295
76020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.3029576020
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.826793083
Short name T1006
Test name
Test status
Simulation time 10100687539 ps
CPU time 15.19 seconds
Started Jun 06 01:52:24 PM PDT 24
Finished Jun 06 01:52:40 PM PDT 24
Peak memory 205612 kb
Host smart-ea5e8ade-5170-4d0d-b6e4-e3adb79f2e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82679
3083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.826793083
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.1376543109
Short name T607
Test name
Test status
Simulation time 10057598075 ps
CPU time 12.98 seconds
Started Jun 06 01:52:14 PM PDT 24
Finished Jun 06 01:52:28 PM PDT 24
Peak memory 205720 kb
Host smart-4300599e-10bc-4523-9ba2-1cbb3d949734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13765
43109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.1376543109
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.2777923053
Short name T1219
Test name
Test status
Simulation time 10120548619 ps
CPU time 15.8 seconds
Started Jun 06 01:52:15 PM PDT 24
Finished Jun 06 01:52:31 PM PDT 24
Peak memory 205640 kb
Host smart-f7095f37-436d-4a1e-9f8f-55b5326b775d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27779
23053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2777923053
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.2643528521
Short name T411
Test name
Test status
Simulation time 10054399611 ps
CPU time 15.98 seconds
Started Jun 06 01:52:19 PM PDT 24
Finished Jun 06 01:52:36 PM PDT 24
Peak memory 205732 kb
Host smart-47782fec-f649-40f6-bec2-7ca6370f8bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26435
28521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.2643528521
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.145857962
Short name T1063
Test name
Test status
Simulation time 10084504414 ps
CPU time 14.16 seconds
Started Jun 06 01:52:19 PM PDT 24
Finished Jun 06 01:52:34 PM PDT 24
Peak memory 205708 kb
Host smart-ccc44de8-d2ab-4f38-a251-37deb2e8748c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14585
7962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.145857962
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.201169670
Short name T1890
Test name
Test status
Simulation time 13798083477 ps
CPU time 49.05 seconds
Started Jun 06 01:52:19 PM PDT 24
Finished Jun 06 01:53:09 PM PDT 24
Peak memory 205728 kb
Host smart-ce946098-1e7a-4e90-97b4-969b2599dd81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20116
9670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.201169670
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.482743961
Short name T1998
Test name
Test status
Simulation time 10181494220 ps
CPU time 13.58 seconds
Started Jun 06 01:52:49 PM PDT 24
Finished Jun 06 01:53:04 PM PDT 24
Peak memory 205740 kb
Host smart-75bf89f1-e43b-432f-a29d-aeb7e9c2bfba
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=482743961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.482743961
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.1544726402
Short name T668
Test name
Test status
Simulation time 10053210720 ps
CPU time 14.07 seconds
Started Jun 06 01:52:50 PM PDT 24
Finished Jun 06 01:53:06 PM PDT 24
Peak memory 205644 kb
Host smart-0a0cbcd5-cfd2-496b-b982-9982e851b226
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1544726402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.1544726402
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.811003612
Short name T782
Test name
Test status
Simulation time 10107281645 ps
CPU time 14.01 seconds
Started Jun 06 01:52:38 PM PDT 24
Finished Jun 06 01:52:52 PM PDT 24
Peak memory 205712 kb
Host smart-bb96ba84-8470-4449-982b-6514ee2bbc64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81100
3612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.811003612
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.46587350
Short name T15
Test name
Test status
Simulation time 13764230450 ps
CPU time 21.33 seconds
Started Jun 06 01:52:32 PM PDT 24
Finished Jun 06 01:52:54 PM PDT 24
Peak memory 205728 kb
Host smart-b067738c-981b-495e-8c94-63236e97fde5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=46587350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.46587350
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.1039209686
Short name T457
Test name
Test status
Simulation time 23323079494 ps
CPU time 25.34 seconds
Started Jun 06 01:52:22 PM PDT 24
Finished Jun 06 01:52:49 PM PDT 24
Peak memory 205616 kb
Host smart-0ace9ef9-6ef4-48c5-a036-c1a03ad6dcf6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1039209686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.1039209686
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.3863875361
Short name T1975
Test name
Test status
Simulation time 10080917500 ps
CPU time 14.53 seconds
Started Jun 06 01:52:27 PM PDT 24
Finished Jun 06 01:52:42 PM PDT 24
Peak memory 205732 kb
Host smart-36fd15ed-0ed0-4879-b138-4e6b8678a727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38638
75361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3863875361
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.2643660202
Short name T648
Test name
Test status
Simulation time 11446750312 ps
CPU time 16.32 seconds
Started Jun 06 01:52:23 PM PDT 24
Finished Jun 06 01:52:40 PM PDT 24
Peak memory 205628 kb
Host smart-50e6ab7e-0de2-490f-8113-f63c7d6885b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26436
60202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.2643660202
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.1316352855
Short name T523
Test name
Test status
Simulation time 10043792689 ps
CPU time 15.47 seconds
Started Jun 06 01:52:34 PM PDT 24
Finished Jun 06 01:52:50 PM PDT 24
Peak memory 205588 kb
Host smart-14d854e9-a88f-4db2-be09-b8d6487cdfd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13163
52855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.1316352855
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.420568012
Short name T386
Test name
Test status
Simulation time 10056772302 ps
CPU time 13.26 seconds
Started Jun 06 01:52:23 PM PDT 24
Finished Jun 06 01:52:37 PM PDT 24
Peak memory 205720 kb
Host smart-6daf389d-037a-4668-b373-c5b250d99c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42056
8012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.420568012
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.931040492
Short name T1263
Test name
Test status
Simulation time 10899088345 ps
CPU time 15.34 seconds
Started Jun 06 01:52:32 PM PDT 24
Finished Jun 06 01:52:48 PM PDT 24
Peak memory 205696 kb
Host smart-ba3f61eb-36cd-446a-b1fa-92aec3a742c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93104
0492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.931040492
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.1611202697
Short name T1504
Test name
Test status
Simulation time 10186308101 ps
CPU time 14.36 seconds
Started Jun 06 01:52:24 PM PDT 24
Finished Jun 06 01:52:39 PM PDT 24
Peak memory 205716 kb
Host smart-e55f17e6-885c-4213-b58d-86dc243f98e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16112
02697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.1611202697
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.3222776028
Short name T78
Test name
Test status
Simulation time 10063417264 ps
CPU time 13.54 seconds
Started Jun 06 01:52:39 PM PDT 24
Finished Jun 06 01:52:53 PM PDT 24
Peak memory 205716 kb
Host smart-bc0bfff5-ea22-425a-9fb2-0d7b309179f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32227
76028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3222776028
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.486972649
Short name T1782
Test name
Test status
Simulation time 10113095247 ps
CPU time 12.84 seconds
Started Jun 06 01:52:35 PM PDT 24
Finished Jun 06 01:52:48 PM PDT 24
Peak memory 205676 kb
Host smart-1502861e-9cec-46e8-98fa-773a4cd5d183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48697
2649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.486972649
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.2775542454
Short name T784
Test name
Test status
Simulation time 10129167575 ps
CPU time 14.32 seconds
Started Jun 06 01:52:36 PM PDT 24
Finished Jun 06 01:52:51 PM PDT 24
Peak memory 205712 kb
Host smart-d511ff3a-ac87-407c-93d7-bb3f48038bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27755
42454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2775542454
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.4049001198
Short name T1208
Test name
Test status
Simulation time 10106181718 ps
CPU time 13.7 seconds
Started Jun 06 01:52:35 PM PDT 24
Finished Jun 06 01:52:50 PM PDT 24
Peak memory 205668 kb
Host smart-5223cd42-857b-418d-b02a-9895ebeaa826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40490
01198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.4049001198
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.872943391
Short name T1032
Test name
Test status
Simulation time 13215824096 ps
CPU time 20.06 seconds
Started Jun 06 01:52:38 PM PDT 24
Finished Jun 06 01:52:59 PM PDT 24
Peak memory 205732 kb
Host smart-4670f92a-c0ec-456e-a7a2-d77d806a0b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87294
3391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.872943391
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.3623719919
Short name T783
Test name
Test status
Simulation time 10132151789 ps
CPU time 13.21 seconds
Started Jun 06 01:52:39 PM PDT 24
Finished Jun 06 01:52:53 PM PDT 24
Peak memory 205792 kb
Host smart-d5e3359e-e297-4e45-953a-d0dc11bc8cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36237
19919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.3623719919
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.1279424542
Short name T1170
Test name
Test status
Simulation time 23903703129 ps
CPU time 112.75 seconds
Started Jun 06 01:52:35 PM PDT 24
Finished Jun 06 01:54:29 PM PDT 24
Peak memory 205680 kb
Host smart-2dc68fc3-096e-4ed2-8f7c-fe104438fb9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12794
24542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.1279424542
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.620490348
Short name T918
Test name
Test status
Simulation time 10055377608 ps
CPU time 12.99 seconds
Started Jun 06 01:52:37 PM PDT 24
Finished Jun 06 01:52:51 PM PDT 24
Peak memory 205656 kb
Host smart-d34611d6-b474-47f3-b6b4-df1705bd7ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62049
0348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.620490348
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.1756638542
Short name T1210
Test name
Test status
Simulation time 10181062394 ps
CPU time 15.3 seconds
Started Jun 06 01:52:37 PM PDT 24
Finished Jun 06 01:52:53 PM PDT 24
Peak memory 205708 kb
Host smart-1150e7a0-3d71-49f8-abd5-9e5a0505446d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17566
38542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.1756638542
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.3433995323
Short name T1479
Test name
Test status
Simulation time 10093521228 ps
CPU time 15.19 seconds
Started Jun 06 01:52:40 PM PDT 24
Finished Jun 06 01:52:55 PM PDT 24
Peak memory 205720 kb
Host smart-4b0ab83f-3790-4e03-b893-abe1e1ead1af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34339
95323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.3433995323
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3494565771
Short name T302
Test name
Test status
Simulation time 10078633898 ps
CPU time 13.4 seconds
Started Jun 06 01:52:40 PM PDT 24
Finished Jun 06 01:52:54 PM PDT 24
Peak memory 205700 kb
Host smart-627b3c6d-dba9-4213-85a6-51dca8fb6e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34945
65771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3494565771
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.1103016550
Short name T730
Test name
Test status
Simulation time 10137722917 ps
CPU time 12.88 seconds
Started Jun 06 01:52:35 PM PDT 24
Finished Jun 06 01:52:49 PM PDT 24
Peak memory 205672 kb
Host smart-555d15c5-f6a4-475c-8c76-803863a9b1db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11030
16550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.1103016550
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.2189266533
Short name T1749
Test name
Test status
Simulation time 10048170518 ps
CPU time 13.31 seconds
Started Jun 06 01:52:39 PM PDT 24
Finished Jun 06 01:52:53 PM PDT 24
Peak memory 205748 kb
Host smart-3c0351c1-24b7-4292-bbd3-210d8981976e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21892
66533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.2189266533
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_eop_single_bit_handling.2259383660
Short name T493
Test name
Test status
Simulation time 10058016722 ps
CPU time 15.3 seconds
Started Jun 06 01:52:37 PM PDT 24
Finished Jun 06 01:52:53 PM PDT 24
Peak memory 205696 kb
Host smart-69e39162-ea04-41a4-bbc3-fbc7e5ec53a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22593
83660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_eop_single_bit_handling.2259383660
Directory /workspace/44.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1378337700
Short name T1897
Test name
Test status
Simulation time 10045813877 ps
CPU time 14.99 seconds
Started Jun 06 01:52:37 PM PDT 24
Finished Jun 06 01:52:53 PM PDT 24
Peak memory 205712 kb
Host smart-f0725576-e332-4c9b-a805-f85ee0825779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13783
37700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1378337700
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.1027421582
Short name T1512
Test name
Test status
Simulation time 10038347734 ps
CPU time 13.51 seconds
Started Jun 06 01:52:36 PM PDT 24
Finished Jun 06 01:52:50 PM PDT 24
Peak memory 205660 kb
Host smart-35b10626-4e20-42a1-ac57-34cc24d4561a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10274
21582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.1027421582
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.1381060342
Short name T273
Test name
Test status
Simulation time 23326919548 ps
CPU time 40.73 seconds
Started Jun 06 01:52:36 PM PDT 24
Finished Jun 06 01:53:17 PM PDT 24
Peak memory 205652 kb
Host smart-d6fc62da-ac4f-4973-a508-f2dd9b539762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13810
60342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.1381060342
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.2763199084
Short name T425
Test name
Test status
Simulation time 10083072446 ps
CPU time 13.14 seconds
Started Jun 06 01:52:42 PM PDT 24
Finished Jun 06 01:52:55 PM PDT 24
Peak memory 205720 kb
Host smart-f247637b-3213-43d6-b12b-a91d488568fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27631
99084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.2763199084
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1076066855
Short name T1287
Test name
Test status
Simulation time 10107569356 ps
CPU time 14.16 seconds
Started Jun 06 01:52:42 PM PDT 24
Finished Jun 06 01:52:57 PM PDT 24
Peak memory 205736 kb
Host smart-c2e327ce-6fbf-4a65-8bb3-7c43f814416c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10760
66855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1076066855
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.2526393373
Short name T919
Test name
Test status
Simulation time 10046806747 ps
CPU time 15.78 seconds
Started Jun 06 01:52:35 PM PDT 24
Finished Jun 06 01:52:52 PM PDT 24
Peak memory 205628 kb
Host smart-af82683b-302a-4370-837f-7fddad22ccce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25263
93373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.2526393373
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.2677232982
Short name T1602
Test name
Test status
Simulation time 10123965601 ps
CPU time 14.18 seconds
Started Jun 06 01:52:35 PM PDT 24
Finished Jun 06 01:52:50 PM PDT 24
Peak memory 205752 kb
Host smart-20b24e44-6528-4d13-903f-c2ebe0b06318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26772
32982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.2677232982
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.2297938169
Short name T143
Test name
Test status
Simulation time 10059840334 ps
CPU time 14.05 seconds
Started Jun 06 01:52:39 PM PDT 24
Finished Jun 06 01:52:54 PM PDT 24
Peak memory 205712 kb
Host smart-90ee4b40-7b79-4fa0-8060-c0b2a32081fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22979
38169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2297938169
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.4264773588
Short name T1074
Test name
Test status
Simulation time 10049879670 ps
CPU time 16.77 seconds
Started Jun 06 01:52:51 PM PDT 24
Finished Jun 06 01:53:09 PM PDT 24
Peak memory 205672 kb
Host smart-ee741420-7c57-4c58-9132-7287841394ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42647
73588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.4264773588
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.1494053649
Short name T1365
Test name
Test status
Simulation time 10107319814 ps
CPU time 14.75 seconds
Started Jun 06 01:52:32 PM PDT 24
Finished Jun 06 01:52:48 PM PDT 24
Peak memory 205740 kb
Host smart-c6a5675d-b055-48f1-adcb-c2ef4a0a8dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14940
53649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1494053649
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.4127057775
Short name T1137
Test name
Test status
Simulation time 10146417067 ps
CPU time 14.88 seconds
Started Jun 06 01:52:40 PM PDT 24
Finished Jun 06 01:52:56 PM PDT 24
Peak memory 205772 kb
Host smart-86602586-6ba2-4dc7-94f4-60a7f1cc9ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41270
57775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.4127057775
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.2469082291
Short name T239
Test name
Test status
Simulation time 10059357855 ps
CPU time 16.91 seconds
Started Jun 06 01:52:39 PM PDT 24
Finished Jun 06 01:52:56 PM PDT 24
Peak memory 205720 kb
Host smart-4507fe78-dc24-4212-bdc3-98967ce35b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24690
82291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.2469082291
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.2637642276
Short name T446
Test name
Test status
Simulation time 23937076965 ps
CPU time 400.64 seconds
Started Jun 06 01:52:37 PM PDT 24
Finished Jun 06 01:59:18 PM PDT 24
Peak memory 205612 kb
Host smart-e8dc5770-c86e-4df4-9922-eb98e2a32b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26376
42276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.2637642276
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.536805642
Short name T1646
Test name
Test status
Simulation time 10168290811 ps
CPU time 14.92 seconds
Started Jun 06 01:52:51 PM PDT 24
Finished Jun 06 01:53:08 PM PDT 24
Peak memory 205672 kb
Host smart-7213bf9f-e7f5-4794-9055-7eb484b979ba
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=536805642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.536805642
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.2198092157
Short name T2019
Test name
Test status
Simulation time 10080734797 ps
CPU time 14.11 seconds
Started Jun 06 01:52:53 PM PDT 24
Finished Jun 06 01:53:09 PM PDT 24
Peak memory 205536 kb
Host smart-09634757-8ff4-4bbb-b001-d5739574c6d7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2198092157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.2198092157
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.708579399
Short name T1794
Test name
Test status
Simulation time 10168943177 ps
CPU time 12.65 seconds
Started Jun 06 01:52:58 PM PDT 24
Finished Jun 06 01:53:12 PM PDT 24
Peak memory 205736 kb
Host smart-c6de5ae1-51f2-48d3-b74d-34efd8a23833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70857
9399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.708579399
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.1882434033
Short name T1877
Test name
Test status
Simulation time 14142866083 ps
CPU time 17.85 seconds
Started Jun 06 01:52:46 PM PDT 24
Finished Jun 06 01:53:04 PM PDT 24
Peak memory 205696 kb
Host smart-75368a13-2e0d-413f-ba1f-5e15cf27ced2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1882434033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.1882434033
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.3559002106
Short name T213
Test name
Test status
Simulation time 23233481448 ps
CPU time 28.67 seconds
Started Jun 06 01:52:45 PM PDT 24
Finished Jun 06 01:53:15 PM PDT 24
Peak memory 205628 kb
Host smart-00a0348a-3ca2-44ec-9e79-9c3b31468754
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3559002106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.3559002106
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.2358923154
Short name T1844
Test name
Test status
Simulation time 10093434738 ps
CPU time 13.58 seconds
Started Jun 06 01:52:53 PM PDT 24
Finished Jun 06 01:53:08 PM PDT 24
Peak memory 205772 kb
Host smart-5289ca73-8ae0-4166-8ff7-f66aceea9bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23589
23154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.2358923154
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.2943653537
Short name T1548
Test name
Test status
Simulation time 10104152476 ps
CPU time 14.71 seconds
Started Jun 06 01:52:45 PM PDT 24
Finished Jun 06 01:53:00 PM PDT 24
Peak memory 205624 kb
Host smart-7384569b-2e3f-466a-afc5-8fe927ca89ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29436
53537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.2943653537
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.86041084
Short name T324
Test name
Test status
Simulation time 10071023133 ps
CPU time 13.31 seconds
Started Jun 06 01:52:50 PM PDT 24
Finished Jun 06 01:53:05 PM PDT 24
Peak memory 205592 kb
Host smart-fa65d352-a3b5-47a9-8a32-39e7db9755d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86041
084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.86041084
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.4200984514
Short name T860
Test name
Test status
Simulation time 10838403820 ps
CPU time 15.04 seconds
Started Jun 06 01:52:50 PM PDT 24
Finished Jun 06 01:53:06 PM PDT 24
Peak memory 205668 kb
Host smart-527be519-5767-4df3-99fb-dbbcea01f039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42009
84514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.4200984514
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.3329944406
Short name T95
Test name
Test status
Simulation time 10266256862 ps
CPU time 14.71 seconds
Started Jun 06 01:52:51 PM PDT 24
Finished Jun 06 01:53:07 PM PDT 24
Peak memory 205736 kb
Host smart-5af2410a-8794-4093-b51b-4310be8ae579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33299
44406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.3329944406
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.2249556994
Short name T1290
Test name
Test status
Simulation time 10120191217 ps
CPU time 13.51 seconds
Started Jun 06 01:52:51 PM PDT 24
Finished Jun 06 01:53:05 PM PDT 24
Peak memory 205716 kb
Host smart-c8de38ae-41db-41c1-bad0-563a77e44b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22495
56994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.2249556994
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1195808421
Short name T1497
Test name
Test status
Simulation time 10052651922 ps
CPU time 13.79 seconds
Started Jun 06 01:52:51 PM PDT 24
Finished Jun 06 01:53:07 PM PDT 24
Peak memory 205736 kb
Host smart-b1c0f333-898b-4df2-a94d-5ced9aa4f4c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11958
08421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1195808421
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.1542649477
Short name T1373
Test name
Test status
Simulation time 10077211635 ps
CPU time 15.91 seconds
Started Jun 06 01:52:52 PM PDT 24
Finished Jun 06 01:53:09 PM PDT 24
Peak memory 205696 kb
Host smart-1e636496-b471-4bdb-9679-4281451af7cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15426
49477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.1542649477
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.2558859676
Short name T1216
Test name
Test status
Simulation time 10185892822 ps
CPU time 14.66 seconds
Started Jun 06 01:52:47 PM PDT 24
Finished Jun 06 01:53:02 PM PDT 24
Peak memory 205704 kb
Host smart-8d386292-2144-4a57-a70e-11358dddd93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25588
59676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.2558859676
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.578010122
Short name T447
Test name
Test status
Simulation time 13223805589 ps
CPU time 19.04 seconds
Started Jun 06 01:52:47 PM PDT 24
Finished Jun 06 01:53:07 PM PDT 24
Peak memory 205740 kb
Host smart-8e8df508-952d-4ec3-a6ea-c29de6f841e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57801
0122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.578010122
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.3677836045
Short name T1843
Test name
Test status
Simulation time 10099958060 ps
CPU time 15.56 seconds
Started Jun 06 01:52:50 PM PDT 24
Finished Jun 06 01:53:06 PM PDT 24
Peak memory 205732 kb
Host smart-7b833763-19a2-4e6e-bac7-28e543f7c36b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36778
36045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.3677836045
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.4223559018
Short name T5
Test name
Test status
Simulation time 23854954854 ps
CPU time 111.24 seconds
Started Jun 06 01:52:50 PM PDT 24
Finished Jun 06 01:54:42 PM PDT 24
Peak memory 205716 kb
Host smart-58c5a867-4996-4ac5-849b-3aa5c0f4ba74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42235
59018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.4223559018
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.1273118402
Short name T2012
Test name
Test status
Simulation time 10060897033 ps
CPU time 13.71 seconds
Started Jun 06 01:52:47 PM PDT 24
Finished Jun 06 01:53:01 PM PDT 24
Peak memory 205684 kb
Host smart-8782bdd7-4a4f-4f10-99dc-e7161142b4cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12731
18402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.1273118402
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2447141273
Short name T1910
Test name
Test status
Simulation time 10157115947 ps
CPU time 15.24 seconds
Started Jun 06 01:52:46 PM PDT 24
Finished Jun 06 01:53:02 PM PDT 24
Peak memory 205568 kb
Host smart-16e65266-9825-498d-ba87-4d5fd1a80522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24471
41273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2447141273
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.336276858
Short name T1820
Test name
Test status
Simulation time 10119259753 ps
CPU time 14.74 seconds
Started Jun 06 01:52:56 PM PDT 24
Finished Jun 06 01:53:11 PM PDT 24
Peak memory 205704 kb
Host smart-bc2c6127-4f7f-458c-8d51-9ced43a75a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33627
6858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.336276858
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.3974765841
Short name T687
Test name
Test status
Simulation time 10056896832 ps
CPU time 15.57 seconds
Started Jun 06 01:52:58 PM PDT 24
Finished Jun 06 01:53:14 PM PDT 24
Peak memory 205672 kb
Host smart-7f5790ad-0b63-4d36-97fe-2672d4579ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39747
65841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.3974765841
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.656805219
Short name T1052
Test name
Test status
Simulation time 10083438818 ps
CPU time 13.31 seconds
Started Jun 06 01:52:52 PM PDT 24
Finished Jun 06 01:53:06 PM PDT 24
Peak memory 205656 kb
Host smart-6a0b4800-f3ed-461a-bae3-dc23541c7185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65680
5219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.656805219
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1790104870
Short name T1727
Test name
Test status
Simulation time 10047496273 ps
CPU time 14.04 seconds
Started Jun 06 01:52:45 PM PDT 24
Finished Jun 06 01:52:59 PM PDT 24
Peak memory 205600 kb
Host smart-d7a2e38f-6bde-4931-808e-ce8156147731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17901
04870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1790104870
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_eop_single_bit_handling.1443116866
Short name T886
Test name
Test status
Simulation time 10067550989 ps
CPU time 12.96 seconds
Started Jun 06 01:52:50 PM PDT 24
Finished Jun 06 01:53:04 PM PDT 24
Peak memory 205692 kb
Host smart-d6b7e4fc-0157-4644-91fb-a7beaa2b1040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14431
16866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_eop_single_bit_handling.1443116866
Directory /workspace/45.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.490196575
Short name T839
Test name
Test status
Simulation time 10043908612 ps
CPU time 14.19 seconds
Started Jun 06 01:52:45 PM PDT 24
Finished Jun 06 01:53:00 PM PDT 24
Peak memory 205648 kb
Host smart-72cb4ed5-2424-40f8-9292-842751c0c480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49019
6575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.490196575
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.1045087933
Short name T43
Test name
Test status
Simulation time 10035642237 ps
CPU time 14.61 seconds
Started Jun 06 01:52:52 PM PDT 24
Finished Jun 06 01:53:08 PM PDT 24
Peak memory 205676 kb
Host smart-eec6d87a-2509-4056-b1cf-bb7199d16f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10450
87933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.1045087933
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.52173772
Short name T1777
Test name
Test status
Simulation time 16568718699 ps
CPU time 31.17 seconds
Started Jun 06 01:52:46 PM PDT 24
Finished Jun 06 01:53:18 PM PDT 24
Peak memory 205620 kb
Host smart-28483700-2fc7-4a9c-b692-9f876b98c7c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52173
772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.52173772
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.1601629669
Short name T1120
Test name
Test status
Simulation time 10153325754 ps
CPU time 13.22 seconds
Started Jun 06 01:52:55 PM PDT 24
Finished Jun 06 01:53:09 PM PDT 24
Peak memory 205660 kb
Host smart-85dc60aa-73c5-448e-ac1c-ad0bf458c5ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16016
29669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.1601629669
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.3412926272
Short name T401
Test name
Test status
Simulation time 10131199390 ps
CPU time 12.9 seconds
Started Jun 06 01:52:53 PM PDT 24
Finished Jun 06 01:53:07 PM PDT 24
Peak memory 205484 kb
Host smart-b657dcdd-a8c2-4ea6-8f8b-7eeb8c584d95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34129
26272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.3412926272
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.1315051429
Short name T313
Test name
Test status
Simulation time 10072891355 ps
CPU time 13.14 seconds
Started Jun 06 01:52:46 PM PDT 24
Finished Jun 06 01:53:00 PM PDT 24
Peak memory 205764 kb
Host smart-b0545ce6-2e15-447e-baff-10b1533b739a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13150
51429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.1315051429
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.748068496
Short name T1257
Test name
Test status
Simulation time 10043007089 ps
CPU time 16.69 seconds
Started Jun 06 01:52:44 PM PDT 24
Finished Jun 06 01:53:01 PM PDT 24
Peak memory 205728 kb
Host smart-c2062183-0563-437f-8fcc-52fb8a379282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74806
8496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.748068496
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.1665027934
Short name T1812
Test name
Test status
Simulation time 10064112332 ps
CPU time 15.11 seconds
Started Jun 06 01:52:58 PM PDT 24
Finished Jun 06 01:53:14 PM PDT 24
Peak memory 205720 kb
Host smart-ae83f9cd-95fe-4815-a015-e2699775fb67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16650
27934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.1665027934
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3462356625
Short name T670
Test name
Test status
Simulation time 10057320894 ps
CPU time 13.22 seconds
Started Jun 06 01:52:46 PM PDT 24
Finished Jun 06 01:53:00 PM PDT 24
Peak memory 205708 kb
Host smart-f9da7ede-f173-467b-a7f6-4b26211b8b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34623
56625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3462356625
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3632666484
Short name T1431
Test name
Test status
Simulation time 10187859552 ps
CPU time 14.63 seconds
Started Jun 06 01:52:48 PM PDT 24
Finished Jun 06 01:53:04 PM PDT 24
Peak memory 205692 kb
Host smart-d8f9f28f-434a-435a-8a8c-518d78e9f9b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36326
66484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3632666484
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.3444191342
Short name T1335
Test name
Test status
Simulation time 10075742097 ps
CPU time 16.93 seconds
Started Jun 06 01:52:51 PM PDT 24
Finished Jun 06 01:53:10 PM PDT 24
Peak memory 205668 kb
Host smart-6bfa6375-1b3a-458c-beaa-7c8e884a5035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34441
91342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.3444191342
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.231959705
Short name T1536
Test name
Test status
Simulation time 10075136623 ps
CPU time 14.82 seconds
Started Jun 06 01:52:55 PM PDT 24
Finished Jun 06 01:53:11 PM PDT 24
Peak memory 205744 kb
Host smart-5f69ba08-0f1f-43c9-8905-7db6fb27c482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23195
9705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.231959705
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.1770974083
Short name T1293
Test name
Test status
Simulation time 24246623624 ps
CPU time 151.91 seconds
Started Jun 06 01:52:56 PM PDT 24
Finished Jun 06 01:55:29 PM PDT 24
Peak memory 205724 kb
Host smart-e91ecaa4-bcfa-4ed2-9735-5abbee7fc962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17709
74083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.1770974083
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.2642107254
Short name T350
Test name
Test status
Simulation time 10162184861 ps
CPU time 14.79 seconds
Started Jun 06 01:52:55 PM PDT 24
Finished Jun 06 01:53:11 PM PDT 24
Peak memory 205772 kb
Host smart-802b20e6-febb-4a60-889f-d2cb08a83119
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2642107254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.2642107254
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.1108062021
Short name T947
Test name
Test status
Simulation time 10060466982 ps
CPU time 16.39 seconds
Started Jun 06 01:52:56 PM PDT 24
Finished Jun 06 01:53:13 PM PDT 24
Peak memory 205740 kb
Host smart-a1758456-8a68-465c-bc05-76e7694d825c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1108062021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.1108062021
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.3747287055
Short name T332
Test name
Test status
Simulation time 10103642953 ps
CPU time 12.95 seconds
Started Jun 06 01:52:53 PM PDT 24
Finished Jun 06 01:53:07 PM PDT 24
Peak memory 205588 kb
Host smart-0659a69d-2070-4406-90dc-c50f2800ea93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37472
87055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.3747287055
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.3962498871
Short name T9
Test name
Test status
Simulation time 13925701988 ps
CPU time 17.64 seconds
Started Jun 06 01:52:51 PM PDT 24
Finished Jun 06 01:53:10 PM PDT 24
Peak memory 205628 kb
Host smart-b745baeb-8af3-47e3-bd54-a0bf9c25214a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3962498871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.3962498871
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.1014981455
Short name T874
Test name
Test status
Simulation time 23347715174 ps
CPU time 26.6 seconds
Started Jun 06 01:52:46 PM PDT 24
Finished Jun 06 01:53:14 PM PDT 24
Peak memory 205624 kb
Host smart-98265dae-79d2-4592-9f84-2f09b7c1af1f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1014981455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.1014981455
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.251744828
Short name T775
Test name
Test status
Simulation time 10052597158 ps
CPU time 14.47 seconds
Started Jun 06 01:52:44 PM PDT 24
Finished Jun 06 01:52:59 PM PDT 24
Peak memory 205736 kb
Host smart-23f94080-9ff2-4e2c-ba8a-ea4c65e46457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25174
4828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.251744828
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.872100583
Short name T60
Test name
Test status
Simulation time 10072884446 ps
CPU time 16.74 seconds
Started Jun 06 01:52:44 PM PDT 24
Finished Jun 06 01:53:02 PM PDT 24
Peak memory 205756 kb
Host smart-7a9a9783-021f-4b24-ae41-74d2227e609a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87210
0583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.872100583
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.3114555618
Short name T1632
Test name
Test status
Simulation time 10528199328 ps
CPU time 14.12 seconds
Started Jun 06 01:52:44 PM PDT 24
Finished Jun 06 01:52:59 PM PDT 24
Peak memory 205772 kb
Host smart-697e13df-8867-4c57-8c8a-1e3e008c5578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31145
55618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.3114555618
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.94998900
Short name T1390
Test name
Test status
Simulation time 10079303939 ps
CPU time 13.12 seconds
Started Jun 06 01:52:45 PM PDT 24
Finished Jun 06 01:52:59 PM PDT 24
Peak memory 205732 kb
Host smart-953314f0-1443-4119-bcd7-b2809490c8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94998
900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.94998900
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.2708851266
Short name T512
Test name
Test status
Simulation time 10064801003 ps
CPU time 15.96 seconds
Started Jun 06 01:52:49 PM PDT 24
Finished Jun 06 01:53:05 PM PDT 24
Peak memory 205608 kb
Host smart-b2095092-a41d-472a-b486-0da9041613c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27088
51266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2708851266
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.2371411047
Short name T1116
Test name
Test status
Simulation time 10816278971 ps
CPU time 14.88 seconds
Started Jun 06 01:52:58 PM PDT 24
Finished Jun 06 01:53:14 PM PDT 24
Peak memory 205732 kb
Host smart-37a2bf3f-c6a5-4f87-9856-8a280da8c574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23714
11047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.2371411047
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.319644893
Short name T1455
Test name
Test status
Simulation time 10257331559 ps
CPU time 14.74 seconds
Started Jun 06 01:52:53 PM PDT 24
Finished Jun 06 01:53:09 PM PDT 24
Peak memory 205708 kb
Host smart-f58e3bdc-b267-4815-b64e-da386dd721f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31964
4893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.319644893
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.3111171561
Short name T831
Test name
Test status
Simulation time 10147284144 ps
CPU time 14.33 seconds
Started Jun 06 01:52:52 PM PDT 24
Finished Jun 06 01:53:08 PM PDT 24
Peak memory 205788 kb
Host smart-50b57f35-f27b-43cf-a5e1-0a58574fd7f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31111
71561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3111171561
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.2353630609
Short name T625
Test name
Test status
Simulation time 10037387815 ps
CPU time 16.96 seconds
Started Jun 06 01:52:54 PM PDT 24
Finished Jun 06 01:53:12 PM PDT 24
Peak memory 205664 kb
Host smart-1a72331f-50bc-4b04-9e92-dd447279f93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23536
30609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.2353630609
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.3214387431
Short name T440
Test name
Test status
Simulation time 10139712283 ps
CPU time 14.03 seconds
Started Jun 06 01:52:55 PM PDT 24
Finished Jun 06 01:53:10 PM PDT 24
Peak memory 205700 kb
Host smart-cb694f35-6961-4f24-83cf-adeccb75890a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32143
87431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.3214387431
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.2520615358
Short name T754
Test name
Test status
Simulation time 10136134293 ps
CPU time 13.27 seconds
Started Jun 06 01:52:55 PM PDT 24
Finished Jun 06 01:53:10 PM PDT 24
Peak memory 205752 kb
Host smart-9f365f09-0209-4f6f-a710-ab55181d76a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25206
15358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.2520615358
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.1412413467
Short name T1624
Test name
Test status
Simulation time 13232205824 ps
CPU time 17.77 seconds
Started Jun 06 01:52:49 PM PDT 24
Finished Jun 06 01:53:08 PM PDT 24
Peak memory 205728 kb
Host smart-d712d05b-cdc2-403c-87ed-936a743744f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14124
13467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.1412413467
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2477392840
Short name T1825
Test name
Test status
Simulation time 10117883925 ps
CPU time 12.59 seconds
Started Jun 06 01:52:45 PM PDT 24
Finished Jun 06 01:52:59 PM PDT 24
Peak memory 205592 kb
Host smart-e7930b80-8a7f-432a-8b08-885969e4c5ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24773
92840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2477392840
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.2435995001
Short name T705
Test name
Test status
Simulation time 21082900417 ps
CPU time 90.06 seconds
Started Jun 06 01:52:52 PM PDT 24
Finished Jun 06 01:54:24 PM PDT 24
Peak memory 205708 kb
Host smart-aabafa1a-498c-4860-9275-6b605c6dad2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24359
95001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.2435995001
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.1033932345
Short name T1251
Test name
Test status
Simulation time 10052650734 ps
CPU time 13.6 seconds
Started Jun 06 01:52:54 PM PDT 24
Finished Jun 06 01:53:08 PM PDT 24
Peak memory 205628 kb
Host smart-1c94c0d3-2af9-4d33-a086-8e3e8e05989c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10339
32345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.1033932345
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.4044948890
Short name T102
Test name
Test status
Simulation time 10102328219 ps
CPU time 13.47 seconds
Started Jun 06 01:52:52 PM PDT 24
Finished Jun 06 01:53:07 PM PDT 24
Peak memory 205732 kb
Host smart-60f9b0bf-5937-4c06-b5e9-d64d2e96b172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40449
48890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.4044948890
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.1147441300
Short name T577
Test name
Test status
Simulation time 10084812281 ps
CPU time 13.55 seconds
Started Jun 06 01:52:49 PM PDT 24
Finished Jun 06 01:53:03 PM PDT 24
Peak memory 205648 kb
Host smart-f3ad57b1-280f-48fd-b58b-3fa3e5cb0b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11474
41300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.1147441300
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.1758130044
Short name T1160
Test name
Test status
Simulation time 10095743813 ps
CPU time 13.58 seconds
Started Jun 06 01:52:54 PM PDT 24
Finished Jun 06 01:53:09 PM PDT 24
Peak memory 205724 kb
Host smart-a93617a8-efc6-45d1-9620-7f5f0aaca32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17581
30044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.1758130044
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1011672412
Short name T390
Test name
Test status
Simulation time 10066975207 ps
CPU time 16.43 seconds
Started Jun 06 01:52:46 PM PDT 24
Finished Jun 06 01:53:03 PM PDT 24
Peak memory 205716 kb
Host smart-be18c9f3-e5c4-4f6f-b380-dc4b5e614dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10116
72412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1011672412
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1125618037
Short name T159
Test name
Test status
Simulation time 10043898045 ps
CPU time 14.11 seconds
Started Jun 06 01:52:57 PM PDT 24
Finished Jun 06 01:53:12 PM PDT 24
Peak memory 205680 kb
Host smart-4f6b56f4-d032-423f-aead-13ba51786e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11256
18037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1125618037
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_eop_single_bit_handling.836052120
Short name T1917
Test name
Test status
Simulation time 10063275377 ps
CPU time 12.77 seconds
Started Jun 06 01:52:56 PM PDT 24
Finished Jun 06 01:53:09 PM PDT 24
Peak memory 205724 kb
Host smart-e37b49c6-6b06-4f37-888d-921c5c279bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83605
2120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_eop_single_bit_handling.836052120
Directory /workspace/46.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.2923824094
Short name T1083
Test name
Test status
Simulation time 10049899439 ps
CPU time 13.48 seconds
Started Jun 06 01:52:50 PM PDT 24
Finished Jun 06 01:53:04 PM PDT 24
Peak memory 205656 kb
Host smart-59a4f81e-5510-4294-aafa-9d5914c05e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29238
24094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.2923824094
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3628239143
Short name T1004
Test name
Test status
Simulation time 10035108576 ps
CPU time 13.17 seconds
Started Jun 06 01:52:59 PM PDT 24
Finished Jun 06 01:53:13 PM PDT 24
Peak memory 205636 kb
Host smart-e1a2a113-ce81-4d4a-9ee8-04183650cbcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36282
39143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3628239143
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.1916320527
Short name T98
Test name
Test status
Simulation time 32555366163 ps
CPU time 69.13 seconds
Started Jun 06 01:52:50 PM PDT 24
Finished Jun 06 01:54:01 PM PDT 24
Peak memory 205664 kb
Host smart-27e4dc92-4d4c-42c9-a677-fc5efc8505fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19163
20527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.1916320527
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.1429965224
Short name T475
Test name
Test status
Simulation time 10055418090 ps
CPU time 16.85 seconds
Started Jun 06 01:52:53 PM PDT 24
Finished Jun 06 01:53:11 PM PDT 24
Peak memory 205728 kb
Host smart-8c52eb6f-544d-4079-96d9-52155e9a166f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14299
65224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.1429965224
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.4026111897
Short name T1692
Test name
Test status
Simulation time 10121137246 ps
CPU time 13.5 seconds
Started Jun 06 01:52:50 PM PDT 24
Finished Jun 06 01:53:04 PM PDT 24
Peak memory 205616 kb
Host smart-7a288c6a-61ec-4a6e-8e5b-119198fb355b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40261
11897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.4026111897
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.3956910324
Short name T1314
Test name
Test status
Simulation time 10081523705 ps
CPU time 13.28 seconds
Started Jun 06 01:52:53 PM PDT 24
Finished Jun 06 01:53:08 PM PDT 24
Peak memory 205640 kb
Host smart-df25f08c-286e-4d53-9b44-9bbc84b9d20f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39569
10324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.3956910324
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.314568358
Short name T724
Test name
Test status
Simulation time 10045762734 ps
CPU time 15.21 seconds
Started Jun 06 01:52:54 PM PDT 24
Finished Jun 06 01:53:11 PM PDT 24
Peak memory 205644 kb
Host smart-9b3ba9df-aa03-4fd8-8445-88d24131bdf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31456
8358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.314568358
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.3240988974
Short name T152
Test name
Test status
Simulation time 10080389056 ps
CPU time 14.85 seconds
Started Jun 06 01:52:59 PM PDT 24
Finished Jun 06 01:53:15 PM PDT 24
Peak memory 205688 kb
Host smart-23e6a25e-0857-4174-9cd0-0615ee27ca7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32409
88974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.3240988974
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.446965611
Short name T1139
Test name
Test status
Simulation time 10055709944 ps
CPU time 14.81 seconds
Started Jun 06 01:52:51 PM PDT 24
Finished Jun 06 01:53:07 PM PDT 24
Peak memory 205728 kb
Host smart-6bd0a382-ae1a-44c5-8bce-ff7fe11e2901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44696
5611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.446965611
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3441810457
Short name T1296
Test name
Test status
Simulation time 10102049149 ps
CPU time 13.65 seconds
Started Jun 06 01:52:55 PM PDT 24
Finished Jun 06 01:53:10 PM PDT 24
Peak memory 205664 kb
Host smart-37541f84-4918-44c9-a7a6-733594292f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34418
10457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3441810457
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.2892181044
Short name T1628
Test name
Test status
Simulation time 10127254493 ps
CPU time 15.54 seconds
Started Jun 06 01:52:45 PM PDT 24
Finished Jun 06 01:53:01 PM PDT 24
Peak memory 205712 kb
Host smart-099a2082-fe22-4547-a2f7-09fed366cf15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28921
81044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.2892181044
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2833021934
Short name T861
Test name
Test status
Simulation time 10078461830 ps
CPU time 14.56 seconds
Started Jun 06 01:52:46 PM PDT 24
Finished Jun 06 01:53:01 PM PDT 24
Peak memory 205676 kb
Host smart-5984dc16-5148-4a31-bd2b-fcb9cea41962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28330
21934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2833021934
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.527905196
Short name T1668
Test name
Test status
Simulation time 14351845746 ps
CPU time 53.47 seconds
Started Jun 06 01:52:53 PM PDT 24
Finished Jun 06 01:53:48 PM PDT 24
Peak memory 205716 kb
Host smart-c25cb24f-fa98-4d77-b3d2-d8fedfa2a79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52790
5196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.527905196
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.3186012098
Short name T825
Test name
Test status
Simulation time 10152643277 ps
CPU time 13.25 seconds
Started Jun 06 01:52:58 PM PDT 24
Finished Jun 06 01:53:12 PM PDT 24
Peak memory 205732 kb
Host smart-0d62b0dc-3535-4924-a578-adb3c0c33f8a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3186012098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.3186012098
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.3133960009
Short name T1126
Test name
Test status
Simulation time 10065507823 ps
CPU time 13.64 seconds
Started Jun 06 01:53:01 PM PDT 24
Finished Jun 06 01:53:15 PM PDT 24
Peak memory 205620 kb
Host smart-bd2384d5-2549-4e61-b4ac-339f84d38e13
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3133960009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.3133960009
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.397521964
Short name T1175
Test name
Test status
Simulation time 10143504356 ps
CPU time 15.32 seconds
Started Jun 06 01:53:00 PM PDT 24
Finished Jun 06 01:53:16 PM PDT 24
Peak memory 205688 kb
Host smart-46ad7b44-f4c5-43e7-8e7f-37b511c75be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39752
1964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.397521964
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.165205336
Short name T1704
Test name
Test status
Simulation time 13436650467 ps
CPU time 16.67 seconds
Started Jun 06 01:52:56 PM PDT 24
Finished Jun 06 01:53:13 PM PDT 24
Peak memory 205648 kb
Host smart-504bddb3-af65-486c-8624-727b36fc5bc4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=165205336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.165205336
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.4173976075
Short name T8
Test name
Test status
Simulation time 23237575834 ps
CPU time 24.95 seconds
Started Jun 06 01:52:52 PM PDT 24
Finished Jun 06 01:53:18 PM PDT 24
Peak memory 205696 kb
Host smart-1c493f2f-3952-4ee6-9ff3-844669fef21f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4173976075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.4173976075
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2641167221
Short name T983
Test name
Test status
Simulation time 10071478244 ps
CPU time 13.29 seconds
Started Jun 06 01:52:52 PM PDT 24
Finished Jun 06 01:53:06 PM PDT 24
Peak memory 205704 kb
Host smart-95413302-114e-44e3-90ac-8fed65a94aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26411
67221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2641167221
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.4138245136
Short name T1941
Test name
Test status
Simulation time 10802180652 ps
CPU time 15.74 seconds
Started Jun 06 01:52:55 PM PDT 24
Finished Jun 06 01:53:12 PM PDT 24
Peak memory 205648 kb
Host smart-66c28803-22ac-4922-b55d-c74dcc6918c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41382
45136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.4138245136
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.785803550
Short name T1198
Test name
Test status
Simulation time 10059291398 ps
CPU time 12.92 seconds
Started Jun 06 01:53:00 PM PDT 24
Finished Jun 06 01:53:14 PM PDT 24
Peak memory 205636 kb
Host smart-d1b2e774-38e9-48cd-986d-928533b20680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78580
3550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.785803550
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.3701859290
Short name T1891
Test name
Test status
Simulation time 10079375425 ps
CPU time 13.78 seconds
Started Jun 06 01:52:55 PM PDT 24
Finished Jun 06 01:53:09 PM PDT 24
Peak memory 205676 kb
Host smart-b68b32f8-cd8f-490c-a5c7-bdbaae629563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37018
59290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3701859290
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.2874375427
Short name T503
Test name
Test status
Simulation time 10876463945 ps
CPU time 14.85 seconds
Started Jun 06 01:52:55 PM PDT 24
Finished Jun 06 01:53:11 PM PDT 24
Peak memory 205764 kb
Host smart-380e4701-f775-41ba-82d6-8cf0c454cba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28743
75427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.2874375427
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.1684378616
Short name T491
Test name
Test status
Simulation time 10294290312 ps
CPU time 15.9 seconds
Started Jun 06 01:52:54 PM PDT 24
Finished Jun 06 01:53:11 PM PDT 24
Peak memory 205680 kb
Host smart-18a7b6ac-9e65-4e94-8c71-b4dbd91375f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16843
78616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.1684378616
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.3012488379
Short name T77
Test name
Test status
Simulation time 10138895627 ps
CPU time 14.95 seconds
Started Jun 06 01:52:58 PM PDT 24
Finished Jun 06 01:53:15 PM PDT 24
Peak memory 205604 kb
Host smart-c06f424d-60a0-4b0e-b192-35f811c69328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30124
88379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.3012488379
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.3198147753
Short name T830
Test name
Test status
Simulation time 10039871383 ps
CPU time 12.81 seconds
Started Jun 06 01:53:00 PM PDT 24
Finished Jun 06 01:53:14 PM PDT 24
Peak memory 205672 kb
Host smart-97acdbd2-2298-496f-99fb-77f6a8e168d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31981
47753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.3198147753
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.204705277
Short name T553
Test name
Test status
Simulation time 10131800111 ps
CPU time 15.88 seconds
Started Jun 06 01:52:56 PM PDT 24
Finished Jun 06 01:53:13 PM PDT 24
Peak memory 205756 kb
Host smart-6d3fdd4e-133c-4024-b937-64daa9db0cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20470
5277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.204705277
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.1915532698
Short name T1693
Test name
Test status
Simulation time 10137513291 ps
CPU time 14.06 seconds
Started Jun 06 01:52:54 PM PDT 24
Finished Jun 06 01:53:10 PM PDT 24
Peak memory 205684 kb
Host smart-bd982565-c5e0-426e-8352-db4b4ed73503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19155
32698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.1915532698
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.2716546250
Short name T700
Test name
Test status
Simulation time 13167491676 ps
CPU time 19.27 seconds
Started Jun 06 01:52:53 PM PDT 24
Finished Jun 06 01:53:14 PM PDT 24
Peak memory 205668 kb
Host smart-a88fb96f-df4e-46e8-9f7d-303fddbec6d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27165
46250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.2716546250
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.2293829577
Short name T1909
Test name
Test status
Simulation time 10096101584 ps
CPU time 14.12 seconds
Started Jun 06 01:52:58 PM PDT 24
Finished Jun 06 01:53:13 PM PDT 24
Peak memory 205660 kb
Host smart-b4ac5b8f-e4e0-4a63-9a3c-8afcd2d9128a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22938
29577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.2293829577
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.768315877
Short name T1340
Test name
Test status
Simulation time 23532151399 ps
CPU time 113.09 seconds
Started Jun 06 01:53:00 PM PDT 24
Finished Jun 06 01:54:54 PM PDT 24
Peak memory 205776 kb
Host smart-b6f73cea-e75b-47b3-9b20-18cbe659fdad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76831
5877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.768315877
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.2573154691
Short name T1271
Test name
Test status
Simulation time 10050503401 ps
CPU time 13.85 seconds
Started Jun 06 01:52:57 PM PDT 24
Finished Jun 06 01:53:12 PM PDT 24
Peak memory 205720 kb
Host smart-78b13109-1e8c-41b1-b60f-8896af93bb23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25731
54691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.2573154691
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.1898100004
Short name T108
Test name
Test status
Simulation time 10084502705 ps
CPU time 12.52 seconds
Started Jun 06 01:52:58 PM PDT 24
Finished Jun 06 01:53:12 PM PDT 24
Peak memory 205668 kb
Host smart-b51d919c-bc93-498a-ab18-f9b6c88d4c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18981
00004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.1898100004
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.2491236741
Short name T429
Test name
Test status
Simulation time 10065489745 ps
CPU time 16.14 seconds
Started Jun 06 01:52:58 PM PDT 24
Finished Jun 06 01:53:15 PM PDT 24
Peak memory 205668 kb
Host smart-70a8e406-6ffb-41b3-afd8-40c391d2a15c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24912
36741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.2491236741
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.2083913911
Short name T2014
Test name
Test status
Simulation time 10079902080 ps
CPU time 14.62 seconds
Started Jun 06 01:52:57 PM PDT 24
Finished Jun 06 01:53:12 PM PDT 24
Peak memory 205764 kb
Host smart-506e3fa3-9872-44c2-99fe-2c41942bcfde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20839
13911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.2083913911
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3115485236
Short name T1797
Test name
Test status
Simulation time 10060429561 ps
CPU time 14.68 seconds
Started Jun 06 01:52:58 PM PDT 24
Finished Jun 06 01:53:14 PM PDT 24
Peak memory 205756 kb
Host smart-3c811658-81da-4748-8b95-e26f1a768d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31154
85236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3115485236
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.1253508742
Short name T992
Test name
Test status
Simulation time 10054625728 ps
CPU time 13.66 seconds
Started Jun 06 01:52:57 PM PDT 24
Finished Jun 06 01:53:12 PM PDT 24
Peak memory 205652 kb
Host smart-d68a7e9a-763f-415c-a2aa-4467fddfd3cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12535
08742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.1253508742
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_eop_single_bit_handling.570263875
Short name T913
Test name
Test status
Simulation time 10073229563 ps
CPU time 12.66 seconds
Started Jun 06 01:52:58 PM PDT 24
Finished Jun 06 01:53:11 PM PDT 24
Peak memory 205640 kb
Host smart-14c989a2-e233-495b-947e-ab0aeca2cba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57026
3875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_eop_single_bit_handling.570263875
Directory /workspace/47.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.1192231232
Short name T689
Test name
Test status
Simulation time 10042789925 ps
CPU time 15.92 seconds
Started Jun 06 01:52:57 PM PDT 24
Finished Jun 06 01:53:14 PM PDT 24
Peak memory 205740 kb
Host smart-a3891a6c-c9de-4f7e-ab11-0e85ef39b0f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11922
31232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.1192231232
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.11247399
Short name T1607
Test name
Test status
Simulation time 10032334664 ps
CPU time 14.26 seconds
Started Jun 06 01:52:59 PM PDT 24
Finished Jun 06 01:53:14 PM PDT 24
Peak memory 205716 kb
Host smart-b9aa33ba-419c-4960-919f-11342dc84762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11247
399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.11247399
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2768230237
Short name T96
Test name
Test status
Simulation time 27665783522 ps
CPU time 55.37 seconds
Started Jun 06 01:52:59 PM PDT 24
Finished Jun 06 01:53:56 PM PDT 24
Peak memory 205672 kb
Host smart-15425fdd-d538-431f-8632-1ef29c49050a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27682
30237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2768230237
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1547646635
Short name T458
Test name
Test status
Simulation time 10057649963 ps
CPU time 16.44 seconds
Started Jun 06 01:53:01 PM PDT 24
Finished Jun 06 01:53:18 PM PDT 24
Peak memory 205652 kb
Host smart-2d84a948-446e-439a-a501-ec1a648322ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15476
46635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1547646635
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.1822475955
Short name T1756
Test name
Test status
Simulation time 10123862047 ps
CPU time 14.73 seconds
Started Jun 06 01:52:53 PM PDT 24
Finished Jun 06 01:53:09 PM PDT 24
Peak memory 205748 kb
Host smart-1b2c05fc-aaa2-4a08-a0dd-3ba275ffa8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18224
75955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.1822475955
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.1538768551
Short name T986
Test name
Test status
Simulation time 10085932279 ps
CPU time 13.43 seconds
Started Jun 06 01:52:58 PM PDT 24
Finished Jun 06 01:53:13 PM PDT 24
Peak memory 205664 kb
Host smart-e0427b36-3740-4df6-ae6d-d2c0d656cd62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15387
68551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.1538768551
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.856699977
Short name T1610
Test name
Test status
Simulation time 10044268102 ps
CPU time 14.14 seconds
Started Jun 06 01:52:57 PM PDT 24
Finished Jun 06 01:53:12 PM PDT 24
Peak memory 205640 kb
Host smart-a7d58523-7f64-4d7e-9f1d-dd5f808e9c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85669
9977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.856699977
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.4131123975
Short name T1510
Test name
Test status
Simulation time 10062905527 ps
CPU time 12.79 seconds
Started Jun 06 01:52:57 PM PDT 24
Finished Jun 06 01:53:11 PM PDT 24
Peak memory 205648 kb
Host smart-de97d440-5879-49db-a316-e9f38cdc9e85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41311
23975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.4131123975
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.3538361319
Short name T974
Test name
Test status
Simulation time 10047364231 ps
CPU time 13.71 seconds
Started Jun 06 01:52:57 PM PDT 24
Finished Jun 06 01:53:12 PM PDT 24
Peak memory 205612 kb
Host smart-fc4abeed-1cf4-42d3-ac35-31f2742b0102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35383
61319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.3538361319
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.4149580265
Short name T1262
Test name
Test status
Simulation time 10143608911 ps
CPU time 14.62 seconds
Started Jun 06 01:52:59 PM PDT 24
Finished Jun 06 01:53:15 PM PDT 24
Peak memory 205716 kb
Host smart-b0366120-f1ac-4fcb-b2fa-82e9d0e8328d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41495
80265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.4149580265
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.1282572886
Short name T132
Test name
Test status
Simulation time 10070842204 ps
CPU time 16.89 seconds
Started Jun 06 01:52:55 PM PDT 24
Finished Jun 06 01:53:13 PM PDT 24
Peak memory 205684 kb
Host smart-95f5ce13-7f35-47d1-b265-dcb299ebc033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12825
72886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.1282572886
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2188499583
Short name T33
Test name
Test status
Simulation time 10101940909 ps
CPU time 14.32 seconds
Started Jun 06 01:52:59 PM PDT 24
Finished Jun 06 01:53:14 PM PDT 24
Peak memory 205716 kb
Host smart-a0f8d6d7-fe8a-443d-924b-855683e2e7f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21884
99583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2188499583
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.1463561504
Short name T1718
Test name
Test status
Simulation time 14737936156 ps
CPU time 50.24 seconds
Started Jun 06 01:52:58 PM PDT 24
Finished Jun 06 01:53:49 PM PDT 24
Peak memory 205764 kb
Host smart-7a637491-9a1d-4d7a-b5c3-5999aa3e419f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14635
61504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.1463561504
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.3918985578
Short name T1068
Test name
Test status
Simulation time 10139731599 ps
CPU time 15.09 seconds
Started Jun 06 01:53:08 PM PDT 24
Finished Jun 06 01:53:24 PM PDT 24
Peak memory 205668 kb
Host smart-91acceaf-12bb-45f1-9f85-7f9ee12902cb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3918985578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.3918985578
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.3171059632
Short name T427
Test name
Test status
Simulation time 10063644447 ps
CPU time 13.9 seconds
Started Jun 06 01:53:08 PM PDT 24
Finished Jun 06 01:53:23 PM PDT 24
Peak memory 205748 kb
Host smart-cebea627-b102-4007-9579-ecd46e1d7cc2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3171059632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.3171059632
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.3699732494
Short name T348
Test name
Test status
Simulation time 10057309608 ps
CPU time 13.72 seconds
Started Jun 06 01:53:04 PM PDT 24
Finished Jun 06 01:53:19 PM PDT 24
Peak memory 205688 kb
Host smart-b5515f6a-d76e-453a-a69f-76808b4c8e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36997
32494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.3699732494
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.1057351328
Short name T887
Test name
Test status
Simulation time 13790316083 ps
CPU time 17.79 seconds
Started Jun 06 01:53:00 PM PDT 24
Finished Jun 06 01:53:19 PM PDT 24
Peak memory 205680 kb
Host smart-a25e588c-3a29-4149-b49a-82b3d276d1e4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1057351328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.1057351328
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.2131245896
Short name T532
Test name
Test status
Simulation time 23265264127 ps
CPU time 27.08 seconds
Started Jun 06 01:52:57 PM PDT 24
Finished Jun 06 01:53:25 PM PDT 24
Peak memory 205752 kb
Host smart-32ecf067-531c-46cb-9a67-5c50cf37bb11
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2131245896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.2131245896
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.2844895648
Short name T442
Test name
Test status
Simulation time 10060276883 ps
CPU time 13.62 seconds
Started Jun 06 01:53:00 PM PDT 24
Finished Jun 06 01:53:14 PM PDT 24
Peak memory 205684 kb
Host smart-e9e382e2-71bb-4c62-ad51-8f9a58972660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28448
95648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.2844895648
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.129310846
Short name T1404
Test name
Test status
Simulation time 10277053321 ps
CPU time 13.33 seconds
Started Jun 06 01:52:54 PM PDT 24
Finished Jun 06 01:53:08 PM PDT 24
Peak memory 205628 kb
Host smart-ffc131e8-7e53-4f20-8055-6828f49713e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12931
0846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.129310846
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.4067236500
Short name T489
Test name
Test status
Simulation time 10042482948 ps
CPU time 12.69 seconds
Started Jun 06 01:52:52 PM PDT 24
Finished Jun 06 01:53:06 PM PDT 24
Peak memory 205648 kb
Host smart-bfbcca78-14b4-4ffd-aade-60de52e394b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40672
36500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.4067236500
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.4136971243
Short name T1451
Test name
Test status
Simulation time 10055665697 ps
CPU time 13.34 seconds
Started Jun 06 01:52:56 PM PDT 24
Finished Jun 06 01:53:10 PM PDT 24
Peak memory 205980 kb
Host smart-989fca16-54bf-4752-9271-d1457466e85d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41369
71243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.4136971243
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.1904150653
Short name T963
Test name
Test status
Simulation time 10616091212 ps
CPU time 14.37 seconds
Started Jun 06 01:52:56 PM PDT 24
Finished Jun 06 01:53:11 PM PDT 24
Peak memory 206004 kb
Host smart-96053368-24fd-4055-a900-c9f924630171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19041
50653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.1904150653
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3776009013
Short name T973
Test name
Test status
Simulation time 10071010524 ps
CPU time 14.27 seconds
Started Jun 06 01:52:56 PM PDT 24
Finished Jun 06 01:53:11 PM PDT 24
Peak memory 205880 kb
Host smart-5e90d9aa-825d-45d3-85a2-cc2df0a823b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37760
09013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3776009013
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.1777435040
Short name T1558
Test name
Test status
Simulation time 10151384593 ps
CPU time 14.97 seconds
Started Jun 06 01:53:05 PM PDT 24
Finished Jun 06 01:53:21 PM PDT 24
Peak memory 205648 kb
Host smart-3b924f44-12d5-4584-bc13-a585b0f98fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17774
35040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.1777435040
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1645822102
Short name T644
Test name
Test status
Simulation time 10055147192 ps
CPU time 12.99 seconds
Started Jun 06 01:53:04 PM PDT 24
Finished Jun 06 01:53:18 PM PDT 24
Peak memory 205716 kb
Host smart-0cddbb4f-d996-4505-96a2-a5d33e18f0a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16458
22102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1645822102
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.4099651288
Short name T546
Test name
Test status
Simulation time 10147782107 ps
CPU time 14.54 seconds
Started Jun 06 01:53:00 PM PDT 24
Finished Jun 06 01:53:15 PM PDT 24
Peak memory 205652 kb
Host smart-85c7d7d4-dcce-4d23-a0c1-a5107fe699ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40996
51288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.4099651288
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.2487936763
Short name T1539
Test name
Test status
Simulation time 10164810432 ps
CPU time 17.14 seconds
Started Jun 06 01:52:56 PM PDT 24
Finished Jun 06 01:53:14 PM PDT 24
Peak memory 205856 kb
Host smart-ef0e5bee-95a7-4667-9f56-c3e0a5e61da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24879
36763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.2487936763
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.447107067
Short name T869
Test name
Test status
Simulation time 13174745957 ps
CPU time 16.62 seconds
Started Jun 06 01:52:59 PM PDT 24
Finished Jun 06 01:53:16 PM PDT 24
Peak memory 205580 kb
Host smart-c8813e11-e811-48df-a045-84ee62286e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44710
7067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.447107067
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.127734980
Short name T833
Test name
Test status
Simulation time 10098522820 ps
CPU time 13.29 seconds
Started Jun 06 01:52:59 PM PDT 24
Finished Jun 06 01:53:14 PM PDT 24
Peak memory 205612 kb
Host smart-2322636b-b1a3-40fd-af7c-6db3c12779f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12773
4980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.127734980
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.486447046
Short name T729
Test name
Test status
Simulation time 18505781967 ps
CPU time 244.66 seconds
Started Jun 06 01:53:03 PM PDT 24
Finished Jun 06 01:57:09 PM PDT 24
Peak memory 205676 kb
Host smart-2b238cd0-a386-40b6-80d7-bca6c1d9bea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48644
7046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.486447046
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2861964975
Short name T409
Test name
Test status
Simulation time 10073999047 ps
CPU time 13.03 seconds
Started Jun 06 01:53:01 PM PDT 24
Finished Jun 06 01:53:15 PM PDT 24
Peak memory 205576 kb
Host smart-9e4625e0-93ad-4b29-84ea-3f792b7a9509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28619
64975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2861964975
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.2729852011
Short name T107
Test name
Test status
Simulation time 10176014022 ps
CPU time 13.09 seconds
Started Jun 06 01:53:02 PM PDT 24
Finished Jun 06 01:53:16 PM PDT 24
Peak memory 205784 kb
Host smart-9b3524e4-888f-4075-8ec1-9f1984e231bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27298
52011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.2729852011
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.220946114
Short name T1393
Test name
Test status
Simulation time 10091832628 ps
CPU time 13.65 seconds
Started Jun 06 01:53:07 PM PDT 24
Finished Jun 06 01:53:22 PM PDT 24
Peak memory 205704 kb
Host smart-35a8c7b8-18e2-4331-bfb7-b9165c18ad1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22094
6114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.220946114
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.2209435531
Short name T772
Test name
Test status
Simulation time 10105768206 ps
CPU time 13.73 seconds
Started Jun 06 01:53:05 PM PDT 24
Finished Jun 06 01:53:20 PM PDT 24
Peak memory 205676 kb
Host smart-94e162ce-6a1c-439a-afcd-fbf031b1a99c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22094
35531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.2209435531
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1695183428
Short name T1503
Test name
Test status
Simulation time 10089066659 ps
CPU time 13.31 seconds
Started Jun 06 01:53:03 PM PDT 24
Finished Jun 06 01:53:17 PM PDT 24
Peak memory 205712 kb
Host smart-7bb1f90c-d8a6-4817-bdf8-83b86a66a7be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16951
83428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1695183428
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.1653323833
Short name T2027
Test name
Test status
Simulation time 10078368001 ps
CPU time 12.48 seconds
Started Jun 06 01:53:03 PM PDT 24
Finished Jun 06 01:53:16 PM PDT 24
Peak memory 205648 kb
Host smart-8edec624-1d11-401c-8e46-b087c4a28809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16533
23833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.1653323833
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_eop_single_bit_handling.3443831481
Short name T707
Test name
Test status
Simulation time 10080412610 ps
CPU time 12.72 seconds
Started Jun 06 01:53:01 PM PDT 24
Finished Jun 06 01:53:14 PM PDT 24
Peak memory 205684 kb
Host smart-216f0039-937e-4440-a270-67680fbb7e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34438
31481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_eop_single_bit_handling.3443831481
Directory /workspace/48.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.1442858211
Short name T1382
Test name
Test status
Simulation time 10047878194 ps
CPU time 14.89 seconds
Started Jun 06 01:53:01 PM PDT 24
Finished Jun 06 01:53:17 PM PDT 24
Peak memory 205700 kb
Host smart-142030cc-4844-4348-9580-4391544c08be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14428
58211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.1442858211
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.323527156
Short name T41
Test name
Test status
Simulation time 10049347978 ps
CPU time 14.08 seconds
Started Jun 06 01:53:08 PM PDT 24
Finished Jun 06 01:53:23 PM PDT 24
Peak memory 205648 kb
Host smart-1fda24c3-7694-4702-8007-1a34c2d4a602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32352
7156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.323527156
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.3901995770
Short name T1810
Test name
Test status
Simulation time 23263379938 ps
CPU time 40.59 seconds
Started Jun 06 01:53:02 PM PDT 24
Finished Jun 06 01:53:43 PM PDT 24
Peak memory 205616 kb
Host smart-940666da-9cc8-4592-a521-2ca4046c7993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39019
95770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.3901995770
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2590094381
Short name T630
Test name
Test status
Simulation time 10083064164 ps
CPU time 17.09 seconds
Started Jun 06 01:53:02 PM PDT 24
Finished Jun 06 01:53:20 PM PDT 24
Peak memory 205916 kb
Host smart-9c0768e7-af40-4150-87cc-c7919179c39f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25900
94381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2590094381
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.1796587250
Short name T504
Test name
Test status
Simulation time 10116311940 ps
CPU time 13.69 seconds
Started Jun 06 01:53:02 PM PDT 24
Finished Jun 06 01:53:16 PM PDT 24
Peak memory 205616 kb
Host smart-b78d06f7-556f-4d7d-aba0-238c30443291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17965
87250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.1796587250
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.3632879509
Short name T914
Test name
Test status
Simulation time 10084232789 ps
CPU time 16.25 seconds
Started Jun 06 01:53:03 PM PDT 24
Finished Jun 06 01:53:20 PM PDT 24
Peak memory 205640 kb
Host smart-9dc6db72-619e-4b8c-9187-46424b1dca89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36328
79509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.3632879509
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.1635115762
Short name T1357
Test name
Test status
Simulation time 10071687242 ps
CPU time 15.55 seconds
Started Jun 06 01:53:07 PM PDT 24
Finished Jun 06 01:53:23 PM PDT 24
Peak memory 205612 kb
Host smart-9f39358a-8b6d-4c5e-bd24-aaaa5488de10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16351
15762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.1635115762
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.1454430222
Short name T1322
Test name
Test status
Simulation time 10051551661 ps
CPU time 13.06 seconds
Started Jun 06 01:53:07 PM PDT 24
Finished Jun 06 01:53:21 PM PDT 24
Peak memory 205616 kb
Host smart-c20ed79b-2632-499f-84b8-4633a9ee5744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14544
30222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.1454430222
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2980763533
Short name T1361
Test name
Test status
Simulation time 10068006454 ps
CPU time 13.6 seconds
Started Jun 06 01:53:10 PM PDT 24
Finished Jun 06 01:53:25 PM PDT 24
Peak memory 205700 kb
Host smart-3dae9d30-52e7-4440-8b69-8d1fda67a1a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29807
63533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2980763533
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.709646882
Short name T2017
Test name
Test status
Simulation time 10171373840 ps
CPU time 17.03 seconds
Started Jun 06 01:52:59 PM PDT 24
Finished Jun 06 01:53:17 PM PDT 24
Peak memory 205600 kb
Host smart-e718f240-e4ce-494a-81d4-74699642966b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70964
6882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.709646882
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.204074978
Short name T1706
Test name
Test status
Simulation time 10088370859 ps
CPU time 12.95 seconds
Started Jun 06 01:53:01 PM PDT 24
Finished Jun 06 01:53:15 PM PDT 24
Peak memory 205668 kb
Host smart-5da9806d-2c21-4f7b-841b-3642a8a86cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20407
4978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.204074978
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.3135738844
Short name T1062
Test name
Test status
Simulation time 10060140188 ps
CPU time 13.48 seconds
Started Jun 06 01:53:00 PM PDT 24
Finished Jun 06 01:53:15 PM PDT 24
Peak memory 205756 kb
Host smart-a38d3dd7-3add-44dc-9e3c-ecf219fd5e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31357
38844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.3135738844
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.2737588309
Short name T1619
Test name
Test status
Simulation time 15229049878 ps
CPU time 47.38 seconds
Started Jun 06 01:53:03 PM PDT 24
Finished Jun 06 01:53:51 PM PDT 24
Peak memory 205676 kb
Host smart-311aa52a-4945-491a-a30a-c6259fed1c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27375
88309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.2737588309
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.2570664371
Short name T405
Test name
Test status
Simulation time 10146264196 ps
CPU time 13.32 seconds
Started Jun 06 01:53:19 PM PDT 24
Finished Jun 06 01:53:34 PM PDT 24
Peak memory 205680 kb
Host smart-770082e1-2873-465c-ad83-8c6bba34d528
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2570664371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.2570664371
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.1443121235
Short name T1996
Test name
Test status
Simulation time 10059815920 ps
CPU time 14.12 seconds
Started Jun 06 01:53:14 PM PDT 24
Finished Jun 06 01:53:30 PM PDT 24
Peak memory 205672 kb
Host smart-6bfa8535-83b0-4dcc-8360-310a5b9b781a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1443121235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.1443121235
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.2685930407
Short name T617
Test name
Test status
Simulation time 10105755966 ps
CPU time 15.61 seconds
Started Jun 06 01:53:09 PM PDT 24
Finished Jun 06 01:53:25 PM PDT 24
Peak memory 205716 kb
Host smart-d1f85b4c-fd58-4d15-81d4-b841e81ec007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26859
30407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.2685930407
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.2181812390
Short name T1508
Test name
Test status
Simulation time 13499990189 ps
CPU time 16.79 seconds
Started Jun 06 01:53:04 PM PDT 24
Finished Jun 06 01:53:22 PM PDT 24
Peak memory 205744 kb
Host smart-f09a261a-5e4b-411a-80b3-e8e75070a35d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2181812390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.2181812390
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.1652574839
Short name T1071
Test name
Test status
Simulation time 23313417774 ps
CPU time 25.12 seconds
Started Jun 06 01:53:04 PM PDT 24
Finished Jun 06 01:53:30 PM PDT 24
Peak memory 205708 kb
Host smart-d6876f0c-4821-47b0-bb5f-b20b52b0fc59
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1652574839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.1652574839
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3004662437
Short name T1521
Test name
Test status
Simulation time 10053125139 ps
CPU time 14.74 seconds
Started Jun 06 01:53:05 PM PDT 24
Finished Jun 06 01:53:20 PM PDT 24
Peak memory 205592 kb
Host smart-8fd0e41c-1efc-49a1-bed9-45d1e69c65a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30046
62437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3004662437
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.273147168
Short name T1566
Test name
Test status
Simulation time 10437397530 ps
CPU time 13.72 seconds
Started Jun 06 01:53:08 PM PDT 24
Finished Jun 06 01:53:22 PM PDT 24
Peak memory 205644 kb
Host smart-6d29cfd1-603f-4331-a86e-cded520cd4a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27314
7168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.273147168
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_enable.3748609076
Short name T1392
Test name
Test status
Simulation time 10056999655 ps
CPU time 13.03 seconds
Started Jun 06 01:53:06 PM PDT 24
Finished Jun 06 01:53:20 PM PDT 24
Peak memory 205612 kb
Host smart-b9c657f6-085c-4093-96b4-6dd8c0641939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37486
09076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.3748609076
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.1386000404
Short name T917
Test name
Test status
Simulation time 10769745920 ps
CPU time 16.15 seconds
Started Jun 06 01:53:07 PM PDT 24
Finished Jun 06 01:53:24 PM PDT 24
Peak memory 205688 kb
Host smart-3d38d408-dc7b-4b9b-9f58-1edef9f33360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13860
00404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.1386000404
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.2746282168
Short name T1022
Test name
Test status
Simulation time 10176641220 ps
CPU time 13.73 seconds
Started Jun 06 01:53:05 PM PDT 24
Finished Jun 06 01:53:19 PM PDT 24
Peak memory 205696 kb
Host smart-cdef1ef0-4c92-4449-a42f-166d969d8a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27462
82168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.2746282168
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1389378196
Short name T1158
Test name
Test status
Simulation time 10138046858 ps
CPU time 13.08 seconds
Started Jun 06 01:53:11 PM PDT 24
Finished Jun 06 01:53:26 PM PDT 24
Peak memory 205740 kb
Host smart-b52d2503-a475-4ff1-92a5-9482c724fe0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13893
78196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1389378196
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.3435448403
Short name T391
Test name
Test status
Simulation time 10040652624 ps
CPU time 14.52 seconds
Started Jun 06 01:53:13 PM PDT 24
Finished Jun 06 01:53:29 PM PDT 24
Peak memory 205696 kb
Host smart-5477646a-75de-4ce6-b882-b1d21efa1e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34354
48403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.3435448403
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.1883877344
Short name T1555
Test name
Test status
Simulation time 10146639246 ps
CPU time 14.96 seconds
Started Jun 06 01:53:07 PM PDT 24
Finished Jun 06 01:53:23 PM PDT 24
Peak memory 205696 kb
Host smart-5108182f-725e-4ec2-815a-f292f3be8787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18838
77344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.1883877344
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.4005430123
Short name T361
Test name
Test status
Simulation time 10130462345 ps
CPU time 17.29 seconds
Started Jun 06 01:53:07 PM PDT 24
Finished Jun 06 01:53:25 PM PDT 24
Peak memory 205736 kb
Host smart-94c0ea81-0909-4254-ab02-21383a8a32dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40054
30123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.4005430123
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.3903051214
Short name T243
Test name
Test status
Simulation time 13229742814 ps
CPU time 17.62 seconds
Started Jun 06 01:53:01 PM PDT 24
Finished Jun 06 01:53:19 PM PDT 24
Peak memory 205744 kb
Host smart-78fc6509-51cc-409a-8c6f-981645898de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39030
51214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.3903051214
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3728729937
Short name T511
Test name
Test status
Simulation time 10100726821 ps
CPU time 12.86 seconds
Started Jun 06 01:53:08 PM PDT 24
Finished Jun 06 01:53:21 PM PDT 24
Peak memory 205716 kb
Host smart-64ed31a0-a6ab-44e2-8078-494ea6585506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37287
29937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3728729937
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.2872784229
Short name T789
Test name
Test status
Simulation time 16177432237 ps
CPU time 77.4 seconds
Started Jun 06 01:53:12 PM PDT 24
Finished Jun 06 01:54:30 PM PDT 24
Peak memory 205712 kb
Host smart-43b3db3c-8873-4a5a-989a-36818797d646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28727
84229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.2872784229
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1205150128
Short name T271
Test name
Test status
Simulation time 10055143295 ps
CPU time 15.21 seconds
Started Jun 06 01:53:16 PM PDT 24
Finished Jun 06 01:53:32 PM PDT 24
Peak memory 205776 kb
Host smart-9cfe0800-c409-455c-9ced-ddffcef986db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12051
50128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1205150128
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2235033044
Short name T1653
Test name
Test status
Simulation time 10076290757 ps
CPU time 15.05 seconds
Started Jun 06 01:53:09 PM PDT 24
Finished Jun 06 01:53:25 PM PDT 24
Peak memory 205760 kb
Host smart-3790ba68-9c5e-4c71-b247-abe7c042655b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22350
33044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2235033044
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.2297044677
Short name T620
Test name
Test status
Simulation time 10077500461 ps
CPU time 13.87 seconds
Started Jun 06 01:53:14 PM PDT 24
Finished Jun 06 01:53:30 PM PDT 24
Peak memory 205684 kb
Host smart-ab21ddf2-d80e-4d35-a04a-ce656d41cde1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22970
44677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.2297044677
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.2875540277
Short name T1359
Test name
Test status
Simulation time 10070058708 ps
CPU time 12.63 seconds
Started Jun 06 01:53:14 PM PDT 24
Finished Jun 06 01:53:29 PM PDT 24
Peak memory 205720 kb
Host smart-fd098d7c-317f-43c4-8079-9eba1f9c14d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28755
40277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.2875540277
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1098448887
Short name T1435
Test name
Test status
Simulation time 10077667128 ps
CPU time 13.68 seconds
Started Jun 06 01:53:11 PM PDT 24
Finished Jun 06 01:53:26 PM PDT 24
Peak memory 205640 kb
Host smart-1671b651-a329-440f-8564-bd36ae1732b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10984
48887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1098448887
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.2849436734
Short name T853
Test name
Test status
Simulation time 10058762231 ps
CPU time 15.27 seconds
Started Jun 06 01:53:14 PM PDT 24
Finished Jun 06 01:53:31 PM PDT 24
Peak memory 205676 kb
Host smart-92623509-a8e5-42e6-8675-90121db995ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28494
36734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.2849436734
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_eop_single_bit_handling.2861024582
Short name T635
Test name
Test status
Simulation time 10082503217 ps
CPU time 13.93 seconds
Started Jun 06 01:53:12 PM PDT 24
Finished Jun 06 01:53:27 PM PDT 24
Peak memory 205620 kb
Host smart-2760f38b-1cc6-4ed6-926a-048c0e687a8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28610
24582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_eop_single_bit_handling.2861024582
Directory /workspace/49.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.2048933861
Short name T1488
Test name
Test status
Simulation time 10049737603 ps
CPU time 13.67 seconds
Started Jun 06 01:53:14 PM PDT 24
Finished Jun 06 01:53:29 PM PDT 24
Peak memory 205672 kb
Host smart-ba3e5def-234c-4d2d-93c3-eb085f83285a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20489
33861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.2048933861
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.4246969871
Short name T444
Test name
Test status
Simulation time 10043958976 ps
CPU time 14.33 seconds
Started Jun 06 01:53:13 PM PDT 24
Finished Jun 06 01:53:29 PM PDT 24
Peak memory 205716 kb
Host smart-3d125eda-94c8-42aa-992b-42aeb50bf1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42469
69871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.4246969871
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.1208413842
Short name T1005
Test name
Test status
Simulation time 29906211498 ps
CPU time 58.34 seconds
Started Jun 06 01:53:16 PM PDT 24
Finished Jun 06 01:54:16 PM PDT 24
Peak memory 205688 kb
Host smart-3e0b5bf5-07b7-4d02-a58b-3f3f8a72384e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12084
13842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.1208413842
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.2235092883
Short name T448
Test name
Test status
Simulation time 10147737813 ps
CPU time 13.49 seconds
Started Jun 06 01:53:15 PM PDT 24
Finished Jun 06 01:53:30 PM PDT 24
Peak memory 205728 kb
Host smart-8a01a940-7ae1-440e-93ec-a578cb26d17b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22350
92883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.2235092883
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.225371732
Short name T1307
Test name
Test status
Simulation time 10094230701 ps
CPU time 15.62 seconds
Started Jun 06 01:53:17 PM PDT 24
Finished Jun 06 01:53:34 PM PDT 24
Peak memory 205728 kb
Host smart-bb535d95-5feb-49dd-9a6a-09783410cd3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22537
1732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.225371732
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.4186369749
Short name T777
Test name
Test status
Simulation time 10130344229 ps
CPU time 13.62 seconds
Started Jun 06 01:53:09 PM PDT 24
Finished Jun 06 01:53:24 PM PDT 24
Peak memory 205732 kb
Host smart-c4efe209-6a3d-430a-9c95-58f0e52f1afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41863
69749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.4186369749
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.3514114794
Short name T1171
Test name
Test status
Simulation time 10072029474 ps
CPU time 16.58 seconds
Started Jun 06 01:53:13 PM PDT 24
Finished Jun 06 01:53:31 PM PDT 24
Peak memory 205700 kb
Host smart-b3cdd458-1d42-4345-bc9e-a14afb913827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35141
14794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.3514114794
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.2220889624
Short name T1113
Test name
Test status
Simulation time 10052416035 ps
CPU time 13 seconds
Started Jun 06 01:53:11 PM PDT 24
Finished Jun 06 01:53:25 PM PDT 24
Peak memory 205632 kb
Host smart-80154382-5e08-4677-a6f7-078975030914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22208
89624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.2220889624
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.861326685
Short name T882
Test name
Test status
Simulation time 10060336110 ps
CPU time 12.54 seconds
Started Jun 06 01:53:13 PM PDT 24
Finished Jun 06 01:53:27 PM PDT 24
Peak memory 205648 kb
Host smart-aa6611c2-5653-4608-b2f7-920afcf22aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86132
6685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.861326685
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3431686142
Short name T157
Test name
Test status
Simulation time 10129821042 ps
CPU time 14.37 seconds
Started Jun 06 01:53:04 PM PDT 24
Finished Jun 06 01:53:20 PM PDT 24
Peak memory 205716 kb
Host smart-92e3c67f-01ea-4d7d-aafb-66ce58ae3957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34316
86142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3431686142
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.3975976625
Short name T1211
Test name
Test status
Simulation time 10159719446 ps
CPU time 14.04 seconds
Started Jun 06 01:53:15 PM PDT 24
Finished Jun 06 01:53:30 PM PDT 24
Peak memory 205680 kb
Host smart-82a072e6-3f91-49e1-90f1-2a59dd4de9c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39759
76625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.3975976625
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.3938275348
Short name T1534
Test name
Test status
Simulation time 10062185317 ps
CPU time 13.66 seconds
Started Jun 06 01:53:20 PM PDT 24
Finished Jun 06 01:53:35 PM PDT 24
Peak memory 205720 kb
Host smart-3d7d30ff-a838-4f86-a048-c994141a0750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39382
75348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.3938275348
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.2811418039
Short name T928
Test name
Test status
Simulation time 19043634860 ps
CPU time 95.87 seconds
Started Jun 06 01:53:14 PM PDT 24
Finished Jun 06 01:54:52 PM PDT 24
Peak memory 205716 kb
Host smart-62be2fcc-c732-4488-a07f-06a08cd480b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28114
18039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.2811418039
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.1216496390
Short name T1387
Test name
Test status
Simulation time 10161362602 ps
CPU time 13.32 seconds
Started Jun 06 01:45:49 PM PDT 24
Finished Jun 06 01:46:04 PM PDT 24
Peak memory 205716 kb
Host smart-ed1b709f-9aff-43b7-991e-aa0413582d0a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1216496390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.1216496390
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.1004746627
Short name T615
Test name
Test status
Simulation time 10072342919 ps
CPU time 15.25 seconds
Started Jun 06 01:45:51 PM PDT 24
Finished Jun 06 01:46:08 PM PDT 24
Peak memory 205708 kb
Host smart-965d429f-5b66-45db-8703-0e4ab6dac455
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1004746627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.1004746627
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.1265041238
Short name T1182
Test name
Test status
Simulation time 10159855492 ps
CPU time 13.9 seconds
Started Jun 06 01:45:50 PM PDT 24
Finished Jun 06 01:46:06 PM PDT 24
Peak memory 205644 kb
Host smart-10b45fd0-ecd1-408c-8752-69ed7c949725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12650
41238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.1265041238
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.3734916367
Short name T6
Test name
Test status
Simulation time 13996774088 ps
CPU time 21.99 seconds
Started Jun 06 01:45:40 PM PDT 24
Finished Jun 06 01:46:02 PM PDT 24
Peak memory 205644 kb
Host smart-140fd5eb-1ab1-45df-8133-4fcc3b96df7c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3734916367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.3734916367
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.387343232
Short name T978
Test name
Test status
Simulation time 23287403815 ps
CPU time 28.42 seconds
Started Jun 06 01:45:41 PM PDT 24
Finished Jun 06 01:46:10 PM PDT 24
Peak memory 205756 kb
Host smart-1cbace87-c93e-49d2-82a4-68aaa89769f3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=387343232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.387343232
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.3892568564
Short name T1280
Test name
Test status
Simulation time 10054383107 ps
CPU time 17.66 seconds
Started Jun 06 01:45:42 PM PDT 24
Finished Jun 06 01:46:00 PM PDT 24
Peak memory 205696 kb
Host smart-c795c760-cd05-4d80-8591-10c556c481a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38925
68564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.3892568564
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.721005414
Short name T722
Test name
Test status
Simulation time 10044614540 ps
CPU time 15.69 seconds
Started Jun 06 01:45:44 PM PDT 24
Finished Jun 06 01:46:00 PM PDT 24
Peak memory 205792 kb
Host smart-9d575291-ad93-4fa7-88ac-f45f2b21e247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72100
5414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.721005414
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.2822930676
Short name T1590
Test name
Test status
Simulation time 10775614508 ps
CPU time 15.64 seconds
Started Jun 06 01:45:42 PM PDT 24
Finished Jun 06 01:45:58 PM PDT 24
Peak memory 205596 kb
Host smart-df4b6644-06d7-4bc0-b630-27c993ea2076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28229
30676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.2822930676
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.1053170071
Short name T581
Test name
Test status
Simulation time 10062664811 ps
CPU time 14.19 seconds
Started Jun 06 01:45:41 PM PDT 24
Finished Jun 06 01:45:56 PM PDT 24
Peak memory 205772 kb
Host smart-3ad17553-70a6-4860-a99e-aad16b00879a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10531
70071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.1053170071
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.3425644770
Short name T1204
Test name
Test status
Simulation time 10057343944 ps
CPU time 13.18 seconds
Started Jun 06 01:45:40 PM PDT 24
Finished Jun 06 01:45:54 PM PDT 24
Peak memory 205628 kb
Host smart-5b731d51-1c6c-4556-a4ff-2201305d225b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34256
44770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.3425644770
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.1006101785
Short name T715
Test name
Test status
Simulation time 10851850994 ps
CPU time 17.48 seconds
Started Jun 06 01:45:42 PM PDT 24
Finished Jun 06 01:46:00 PM PDT 24
Peak memory 206000 kb
Host smart-c6ab0f2b-afe1-4988-9986-53657100c639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10061
01785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.1006101785
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.547830527
Short name T1721
Test name
Test status
Simulation time 10201004716 ps
CPU time 14.45 seconds
Started Jun 06 01:45:39 PM PDT 24
Finished Jun 06 01:45:54 PM PDT 24
Peak memory 205708 kb
Host smart-db2da9dc-4d7a-41de-8ea6-3e665aec6fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54783
0527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.547830527
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.2323401018
Short name T1281
Test name
Test status
Simulation time 10156463988 ps
CPU time 15.04 seconds
Started Jun 06 01:45:50 PM PDT 24
Finished Jun 06 01:46:07 PM PDT 24
Peak memory 205672 kb
Host smart-04aa8737-8897-4e2d-bb78-b1d7bc56ad9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23234
01018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.2323401018
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1770300201
Short name T993
Test name
Test status
Simulation time 10053355436 ps
CPU time 13.93 seconds
Started Jun 06 01:45:39 PM PDT 24
Finished Jun 06 01:45:54 PM PDT 24
Peak memory 205732 kb
Host smart-43c87778-6fb0-4007-86ff-db7309abdb05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17703
00201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1770300201
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.1368462307
Short name T655
Test name
Test status
Simulation time 10124747460 ps
CPU time 15.61 seconds
Started Jun 06 01:45:42 PM PDT 24
Finished Jun 06 01:45:58 PM PDT 24
Peak memory 205600 kb
Host smart-cb7c1ef5-4752-473b-9f76-c1e0d8bb7601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13684
62307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.1368462307
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.3906516390
Short name T591
Test name
Test status
Simulation time 13171333121 ps
CPU time 17.88 seconds
Started Jun 06 01:45:42 PM PDT 24
Finished Jun 06 01:46:01 PM PDT 24
Peak memory 205680 kb
Host smart-d4a9c354-5954-43f3-b2a6-00f91f769db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39065
16390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.3906516390
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.2314813060
Short name T481
Test name
Test status
Simulation time 10102229353 ps
CPU time 14.71 seconds
Started Jun 06 01:45:42 PM PDT 24
Finished Jun 06 01:45:57 PM PDT 24
Peak memory 205604 kb
Host smart-c0411dc6-194c-4977-8355-ff55a2487081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23148
13060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.2314813060
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.3495817368
Short name T1026
Test name
Test status
Simulation time 23178743994 ps
CPU time 387.29 seconds
Started Jun 06 01:45:39 PM PDT 24
Finished Jun 06 01:52:07 PM PDT 24
Peak memory 205640 kb
Host smart-9559d6ec-04d9-4e93-8506-1ed021a268b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34958
17368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.3495817368
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1499506380
Short name T682
Test name
Test status
Simulation time 10041728645 ps
CPU time 17.22 seconds
Started Jun 06 01:45:40 PM PDT 24
Finished Jun 06 01:45:58 PM PDT 24
Peak memory 205652 kb
Host smart-db3df694-0d40-4ee7-ac4a-4a7b32b0e829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14995
06380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1499506380
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.403816204
Short name T109
Test name
Test status
Simulation time 10093019872 ps
CPU time 13.32 seconds
Started Jun 06 01:45:40 PM PDT 24
Finished Jun 06 01:45:54 PM PDT 24
Peak memory 205728 kb
Host smart-9cfd6602-c429-463e-94df-7f87dbbaa1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40381
6204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.403816204
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.2126563798
Short name T1337
Test name
Test status
Simulation time 10050447758 ps
CPU time 13.15 seconds
Started Jun 06 01:45:41 PM PDT 24
Finished Jun 06 01:45:55 PM PDT 24
Peak memory 205652 kb
Host smart-8262668b-0fb6-4197-a2f9-40d11bdcadb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21265
63798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.2126563798
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.4039973911
Short name T1592
Test name
Test status
Simulation time 10064083653 ps
CPU time 14.97 seconds
Started Jun 06 01:45:41 PM PDT 24
Finished Jun 06 01:45:57 PM PDT 24
Peak memory 205748 kb
Host smart-db146fb3-884d-4bec-b817-4436acdc9cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40399
73911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.4039973911
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2060247625
Short name T1391
Test name
Test status
Simulation time 10141948008 ps
CPU time 13.14 seconds
Started Jun 06 01:45:39 PM PDT 24
Finished Jun 06 01:45:53 PM PDT 24
Peak memory 205680 kb
Host smart-504064d5-e39d-485c-99ee-f8d5dedf03cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20602
47625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2060247625
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.260326738
Short name T153
Test name
Test status
Simulation time 10058886666 ps
CPU time 13.77 seconds
Started Jun 06 01:45:46 PM PDT 24
Finished Jun 06 01:46:01 PM PDT 24
Peak memory 205756 kb
Host smart-71d4ba8b-d2f3-44ab-808b-898d0e969f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26032
6738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.260326738
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_eop_single_bit_handling.1116311422
Short name T1055
Test name
Test status
Simulation time 10079008907 ps
CPU time 17.2 seconds
Started Jun 06 01:45:50 PM PDT 24
Finished Jun 06 01:46:09 PM PDT 24
Peak memory 205704 kb
Host smart-778399e4-a89e-4a3f-920c-e4cfce163c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11163
11422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_eop_single_bit_handling.1116311422
Directory /workspace/5.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.2102976597
Short name T1850
Test name
Test status
Simulation time 10040794530 ps
CPU time 13.8 seconds
Started Jun 06 01:45:50 PM PDT 24
Finished Jun 06 01:46:05 PM PDT 24
Peak memory 205644 kb
Host smart-a91f7cb0-f914-4f90-bcc9-1e2a205d78e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21029
76597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.2102976597
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.615174487
Short name T1447
Test name
Test status
Simulation time 10034170146 ps
CPU time 15.65 seconds
Started Jun 06 01:45:50 PM PDT 24
Finished Jun 06 01:46:07 PM PDT 24
Peak memory 205672 kb
Host smart-fa27050f-c0d7-445c-a73f-86e7a87d8361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61517
4487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.615174487
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.1328548230
Short name T1570
Test name
Test status
Simulation time 30762029355 ps
CPU time 55.6 seconds
Started Jun 06 01:45:49 PM PDT 24
Finished Jun 06 01:46:45 PM PDT 24
Peak memory 205604 kb
Host smart-e06eacd5-b2a3-4de8-8c17-5316edd1072b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13285
48230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.1328548230
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2350759761
Short name T460
Test name
Test status
Simulation time 10092771456 ps
CPU time 16.61 seconds
Started Jun 06 01:45:49 PM PDT 24
Finished Jun 06 01:46:07 PM PDT 24
Peak memory 205700 kb
Host smart-a74bd73c-3a57-4e72-b621-cf9f2d52cdd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23507
59761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2350759761
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.819448345
Short name T484
Test name
Test status
Simulation time 10121256929 ps
CPU time 14.65 seconds
Started Jun 06 01:45:53 PM PDT 24
Finished Jun 06 01:46:08 PM PDT 24
Peak memory 205732 kb
Host smart-0cd055af-1200-41b1-9cdc-f0cae5e509bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81944
8345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.819448345
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.4219137209
Short name T1338
Test name
Test status
Simulation time 28866291035 ps
CPU time 147.31 seconds
Started Jun 06 01:45:51 PM PDT 24
Finished Jun 06 01:48:19 PM PDT 24
Peak memory 205728 kb
Host smart-4f80255a-d865-43e4-a75d-c6156d91a119
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4219137209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.4219137209
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.3544425267
Short name T1096
Test name
Test status
Simulation time 24542298362 ps
CPU time 323.24 seconds
Started Jun 06 01:45:49 PM PDT 24
Finished Jun 06 01:51:14 PM PDT 24
Peak memory 205732 kb
Host smart-cc691a88-649c-4a5e-8f23-40f16562707e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3544425267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.3544425267
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.3470302728
Short name T36
Test name
Test status
Simulation time 42166391192 ps
CPU time 796.44 seconds
Started Jun 06 01:45:49 PM PDT 24
Finished Jun 06 01:59:07 PM PDT 24
Peak memory 205744 kb
Host smart-fbcbc091-bd34-4d2f-981f-274aa41b85f4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3470302728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.3470302728
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.18292539
Short name T236
Test name
Test status
Simulation time 10071850897 ps
CPU time 15.39 seconds
Started Jun 06 01:45:50 PM PDT 24
Finished Jun 06 01:46:07 PM PDT 24
Peak memory 205668 kb
Host smart-07bbe37f-9405-4940-b173-41f85706aac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18292
539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.18292539
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.935420119
Short name T1222
Test name
Test status
Simulation time 10042757298 ps
CPU time 15.2 seconds
Started Jun 06 01:45:47 PM PDT 24
Finished Jun 06 01:46:04 PM PDT 24
Peak memory 205700 kb
Host smart-c2c7aab8-33e6-44b3-ab54-3a8c6ef3063b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93542
0119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.935420119
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.2541120300
Short name T1858
Test name
Test status
Simulation time 10045548822 ps
CPU time 14.61 seconds
Started Jun 06 01:45:54 PM PDT 24
Finished Jun 06 01:46:09 PM PDT 24
Peak memory 205732 kb
Host smart-2f2fb44c-f8b3-49ed-b78d-84e77ded9a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25411
20300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.2541120300
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1524953596
Short name T1524
Test name
Test status
Simulation time 10049503110 ps
CPU time 13.98 seconds
Started Jun 06 01:45:51 PM PDT 24
Finished Jun 06 01:46:06 PM PDT 24
Peak memory 205668 kb
Host smart-6c9e38f6-2f44-49d2-af69-a39072e2aa5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15249
53596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1524953596
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.150276762
Short name T155
Test name
Test status
Simulation time 10129205894 ps
CPU time 13.76 seconds
Started Jun 06 01:45:41 PM PDT 24
Finished Jun 06 01:45:55 PM PDT 24
Peak memory 205760 kb
Host smart-ff7470f7-189a-488a-92c5-dfa6ebe9efb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15027
6762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.150276762
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.448881416
Short name T1302
Test name
Test status
Simulation time 10067772395 ps
CPU time 15.25 seconds
Started Jun 06 01:45:51 PM PDT 24
Finished Jun 06 01:46:08 PM PDT 24
Peak memory 205628 kb
Host smart-45238863-8e3f-45bd-bcaa-18eced270b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44888
1416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.448881416
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.1081839924
Short name T1079
Test name
Test status
Simulation time 10067225333 ps
CPU time 14 seconds
Started Jun 06 01:45:47 PM PDT 24
Finished Jun 06 01:46:02 PM PDT 24
Peak memory 205600 kb
Host smart-423adda6-71be-4456-9769-cf60c7fe4435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10818
39924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.1081839924
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.3798820191
Short name T1232
Test name
Test status
Simulation time 23308839825 ps
CPU time 143.59 seconds
Started Jun 06 01:45:48 PM PDT 24
Finished Jun 06 01:48:13 PM PDT 24
Peak memory 205696 kb
Host smart-24ffdd8b-f727-4910-b75a-1699e95aafc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37988
20191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.3798820191
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.717082113
Short name T1811
Test name
Test status
Simulation time 10150642384 ps
CPU time 13.73 seconds
Started Jun 06 01:46:13 PM PDT 24
Finished Jun 06 01:46:29 PM PDT 24
Peak memory 205668 kb
Host smart-03f862c5-2b33-4648-a947-9b0abdadf2c0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=717082113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.717082113
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.2953292246
Short name T1328
Test name
Test status
Simulation time 10067372511 ps
CPU time 13.09 seconds
Started Jun 06 01:46:08 PM PDT 24
Finished Jun 06 01:46:23 PM PDT 24
Peak memory 205568 kb
Host smart-40001f7f-728e-4dea-9860-648f7375018c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2953292246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.2953292246
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.1300190224
Short name T1225
Test name
Test status
Simulation time 10110305716 ps
CPU time 16.1 seconds
Started Jun 06 01:46:12 PM PDT 24
Finished Jun 06 01:46:30 PM PDT 24
Peak memory 205724 kb
Host smart-85b015b0-249e-41da-96ec-892fd18a7b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13001
90224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.1300190224
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.3297960461
Short name T1826
Test name
Test status
Simulation time 14100212654 ps
CPU time 17.68 seconds
Started Jun 06 01:45:48 PM PDT 24
Finished Jun 06 01:46:06 PM PDT 24
Peak memory 205732 kb
Host smart-0acbe9c6-76e5-4168-8da5-f1d14fb2e7db
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3297960461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.3297960461
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.555625332
Short name T1007
Test name
Test status
Simulation time 23314963545 ps
CPU time 24.52 seconds
Started Jun 06 01:45:48 PM PDT 24
Finished Jun 06 01:46:14 PM PDT 24
Peak memory 205780 kb
Host smart-37ce75c9-ca2a-49ab-abef-3b9a90a28918
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=555625332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.555625332
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.1980789218
Short name T1609
Test name
Test status
Simulation time 10085787651 ps
CPU time 13.11 seconds
Started Jun 06 01:45:53 PM PDT 24
Finished Jun 06 01:46:07 PM PDT 24
Peak memory 205760 kb
Host smart-b3c5d132-e12a-4408-8b82-6530323ecdd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19807
89218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1980789218
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.3695449854
Short name T19
Test name
Test status
Simulation time 11023519131 ps
CPU time 17.37 seconds
Started Jun 06 01:45:47 PM PDT 24
Finished Jun 06 01:46:05 PM PDT 24
Peak memory 205708 kb
Host smart-bb710abf-bccf-4fbe-aef8-5fcce96911a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36954
49854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.3695449854
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.498216628
Short name T1056
Test name
Test status
Simulation time 10060906257 ps
CPU time 15.07 seconds
Started Jun 06 01:45:59 PM PDT 24
Finished Jun 06 01:46:15 PM PDT 24
Peak memory 205752 kb
Host smart-def619d7-31f0-4fbc-b51c-022ec297cd7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49821
6628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.498216628
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.3965821882
Short name T402
Test name
Test status
Simulation time 10059905795 ps
CPU time 16.42 seconds
Started Jun 06 01:46:01 PM PDT 24
Finished Jun 06 01:46:18 PM PDT 24
Peak memory 205616 kb
Host smart-4adc9e7b-f19a-4a9a-9bbe-4e9dbab7b929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39658
21882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3965821882
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.3352876128
Short name T1010
Test name
Test status
Simulation time 10783841284 ps
CPU time 14.47 seconds
Started Jun 06 01:45:52 PM PDT 24
Finished Jun 06 01:46:07 PM PDT 24
Peak memory 205632 kb
Host smart-2b3966f3-3dec-4bcc-9fd1-056a685b453c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33528
76128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.3352876128
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3350713731
Short name T435
Test name
Test status
Simulation time 10069084043 ps
CPU time 17.1 seconds
Started Jun 06 01:46:01 PM PDT 24
Finished Jun 06 01:46:19 PM PDT 24
Peak memory 205600 kb
Host smart-60b68f5f-decc-4468-89a7-80353c2a5200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33507
13731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3350713731
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.709673315
Short name T1739
Test name
Test status
Simulation time 10142675020 ps
CPU time 14.18 seconds
Started Jun 06 01:46:11 PM PDT 24
Finished Jun 06 01:46:27 PM PDT 24
Peak memory 205752 kb
Host smart-c2966f36-0bc9-4ab0-ba9c-4ff7b7543863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70967
3315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.709673315
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.702592246
Short name T1476
Test name
Test status
Simulation time 10039521716 ps
CPU time 13.5 seconds
Started Jun 06 01:46:10 PM PDT 24
Finished Jun 06 01:46:26 PM PDT 24
Peak memory 205736 kb
Host smart-ef890e89-365f-4645-abdf-9fc7858dbe49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70259
2246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.702592246
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.3559907311
Short name T912
Test name
Test status
Simulation time 10176963969 ps
CPU time 15.09 seconds
Started Jun 06 01:46:03 PM PDT 24
Finished Jun 06 01:46:19 PM PDT 24
Peak memory 205736 kb
Host smart-0a3f9694-97ac-4c5e-a199-c932aa6fb2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35599
07311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.3559907311
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.2790842124
Short name T1648
Test name
Test status
Simulation time 10126950244 ps
CPU time 13.22 seconds
Started Jun 06 01:46:00 PM PDT 24
Finished Jun 06 01:46:14 PM PDT 24
Peak memory 205704 kb
Host smart-2b46bd99-822e-4c68-b80a-152d1478f0ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27908
42124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.2790842124
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.1352444702
Short name T1936
Test name
Test status
Simulation time 13219743102 ps
CPU time 16.37 seconds
Started Jun 06 01:46:22 PM PDT 24
Finished Jun 06 01:46:39 PM PDT 24
Peak memory 205716 kb
Host smart-30fd4683-05e1-4dd9-b301-7a06850ffe15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13524
44702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.1352444702
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.3350747055
Short name T343
Test name
Test status
Simulation time 10125993209 ps
CPU time 15.14 seconds
Started Jun 06 01:46:00 PM PDT 24
Finished Jun 06 01:46:16 PM PDT 24
Peak memory 205644 kb
Host smart-c20d3840-5d12-430a-b9f3-f56420bcdeca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33507
47055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.3350747055
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.3125146043
Short name T1495
Test name
Test status
Simulation time 20154904723 ps
CPU time 301.08 seconds
Started Jun 06 01:45:59 PM PDT 24
Finished Jun 06 01:51:01 PM PDT 24
Peak memory 205652 kb
Host smart-0861fe82-a009-4bc9-a87a-92df08cbb870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31251
46043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.3125146043
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.996847234
Short name T1326
Test name
Test status
Simulation time 10078496061 ps
CPU time 13.19 seconds
Started Jun 06 01:45:59 PM PDT 24
Finished Jun 06 01:46:13 PM PDT 24
Peak memory 205600 kb
Host smart-4a0adfb1-fb2e-44c8-840a-7eb3ae0a027e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99684
7234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.996847234
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2580500917
Short name T1764
Test name
Test status
Simulation time 10131877535 ps
CPU time 13.53 seconds
Started Jun 06 01:46:01 PM PDT 24
Finished Jun 06 01:46:15 PM PDT 24
Peak memory 205712 kb
Host smart-c1c8c1a1-61fa-4774-a321-63b3c3c50742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25805
00917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2580500917
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.3150771056
Short name T86
Test name
Test status
Simulation time 10098810954 ps
CPU time 14.12 seconds
Started Jun 06 01:46:01 PM PDT 24
Finished Jun 06 01:46:16 PM PDT 24
Peak memory 205692 kb
Host smart-2a4b248c-a0d8-44c3-9007-a69bdcab1f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31507
71056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.3150771056
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.653950980
Short name T1016
Test name
Test status
Simulation time 10107036358 ps
CPU time 14.37 seconds
Started Jun 06 01:45:59 PM PDT 24
Finished Jun 06 01:46:14 PM PDT 24
Peak memory 205708 kb
Host smart-469d6bf1-2ee1-489a-b78b-c4a3c91350fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65395
0980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.653950980
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.427910568
Short name T1267
Test name
Test status
Simulation time 10067938146 ps
CPU time 15.09 seconds
Started Jun 06 01:46:01 PM PDT 24
Finished Jun 06 01:46:18 PM PDT 24
Peak memory 205752 kb
Host smart-908c5594-c458-4390-82c9-ae5e6d9c91cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42791
0568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.427910568
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.3802573327
Short name T22
Test name
Test status
Simulation time 10059482359 ps
CPU time 15.82 seconds
Started Jun 06 01:46:13 PM PDT 24
Finished Jun 06 01:46:30 PM PDT 24
Peak memory 205732 kb
Host smart-adbe9d14-0d8b-4756-8224-92b30ae701f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38025
73327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.3802573327
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_eop_single_bit_handling.4114658057
Short name T1515
Test name
Test status
Simulation time 10068381021 ps
CPU time 14.71 seconds
Started Jun 06 01:46:10 PM PDT 24
Finished Jun 06 01:46:26 PM PDT 24
Peak memory 205720 kb
Host smart-c5448e7f-db4b-413e-8c68-da4d6c26aac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41146
58057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_eop_single_bit_handling.4114658057
Directory /workspace/6.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.1107488438
Short name T828
Test name
Test status
Simulation time 10078484505 ps
CPU time 13.41 seconds
Started Jun 06 01:46:11 PM PDT 24
Finished Jun 06 01:46:26 PM PDT 24
Peak memory 205620 kb
Host smart-65e4e4a7-4bb8-4b55-93d3-96544de8141c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11074
88438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.1107488438
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.983743219
Short name T1956
Test name
Test status
Simulation time 10077288183 ps
CPU time 13.24 seconds
Started Jun 06 01:46:10 PM PDT 24
Finished Jun 06 01:46:25 PM PDT 24
Peak memory 205584 kb
Host smart-9b99e79c-af89-4969-a9f1-3b3ef49d34c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98374
3219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.983743219
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.2662451007
Short name T1148
Test name
Test status
Simulation time 18645571224 ps
CPU time 30.2 seconds
Started Jun 06 01:46:03 PM PDT 24
Finished Jun 06 01:46:34 PM PDT 24
Peak memory 205688 kb
Host smart-49de5664-5d5b-4d59-b12c-408f69f441b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26624
51007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.2662451007
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.1136279845
Short name T821
Test name
Test status
Simulation time 10058945464 ps
CPU time 13.47 seconds
Started Jun 06 01:45:59 PM PDT 24
Finished Jun 06 01:46:13 PM PDT 24
Peak memory 205728 kb
Host smart-2ce59977-2c65-4029-8816-204dc1e99111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11362
79845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1136279845
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.3732300345
Short name T592
Test name
Test status
Simulation time 10131966151 ps
CPU time 14.86 seconds
Started Jun 06 01:45:58 PM PDT 24
Finished Jun 06 01:46:13 PM PDT 24
Peak memory 205724 kb
Host smart-65161249-56bb-43f1-a3c0-16b365599826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37323
00345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.3732300345
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.1404070488
Short name T181
Test name
Test status
Simulation time 25975161103 ps
CPU time 355.61 seconds
Started Jun 06 01:45:59 PM PDT 24
Finished Jun 06 01:51:56 PM PDT 24
Peak memory 205788 kb
Host smart-f3a5e0ba-9eb0-4c88-abe7-124b9b9f5bb2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1404070488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.1404070488
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.3942086434
Short name T691
Test name
Test status
Simulation time 28441718565 ps
CPU time 120.24 seconds
Started Jun 06 01:46:01 PM PDT 24
Finished Jun 06 01:48:02 PM PDT 24
Peak memory 205704 kb
Host smart-fdaa162f-a3dc-415d-a781-3098b98fd066
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3942086434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.3942086434
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.1434094743
Short name T1911
Test name
Test status
Simulation time 32139107674 ps
CPU time 510.23 seconds
Started Jun 06 01:45:59 PM PDT 24
Finished Jun 06 01:54:31 PM PDT 24
Peak memory 205740 kb
Host smart-a251cffc-1035-4563-aae2-943f66fb4d3a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1434094743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.1434094743
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.2729074783
Short name T736
Test name
Test status
Simulation time 10084809351 ps
CPU time 13.96 seconds
Started Jun 06 01:45:59 PM PDT 24
Finished Jun 06 01:46:14 PM PDT 24
Peak memory 205768 kb
Host smart-ebf6a427-0957-492d-ae4f-a7151ff0f88a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27290
74783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.2729074783
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.2252228290
Short name T1460
Test name
Test status
Simulation time 10043651387 ps
CPU time 14.6 seconds
Started Jun 06 01:45:59 PM PDT 24
Finished Jun 06 01:46:14 PM PDT 24
Peak memory 205668 kb
Host smart-f340a2c4-1006-4421-baf5-29ad94988766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22522
28290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.2252228290
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.2888176853
Short name T76
Test name
Test status
Simulation time 10066372868 ps
CPU time 13.05 seconds
Started Jun 06 01:46:09 PM PDT 24
Finished Jun 06 01:46:24 PM PDT 24
Peak memory 205640 kb
Host smart-cd954569-cff5-4ddd-a76e-2d26a58eaeae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28881
76853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.2888176853
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.2158144403
Short name T207
Test name
Test status
Simulation time 10093951044 ps
CPU time 15.11 seconds
Started Jun 06 01:45:59 PM PDT 24
Finished Jun 06 01:46:15 PM PDT 24
Peak memory 205704 kb
Host smart-d201b208-ebdb-41e1-ba93-1e5ab2f3b4f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21581
44403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.2158144403
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1443740436
Short name T1599
Test name
Test status
Simulation time 10168271742 ps
CPU time 13.13 seconds
Started Jun 06 01:45:48 PM PDT 24
Finished Jun 06 01:46:03 PM PDT 24
Peak memory 205668 kb
Host smart-46096124-4482-4658-9900-ff2b12593e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14437
40436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1443740436
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.2524520438
Short name T579
Test name
Test status
Simulation time 10090882540 ps
CPU time 13.39 seconds
Started Jun 06 01:46:03 PM PDT 24
Finished Jun 06 01:46:17 PM PDT 24
Peak memory 205672 kb
Host smart-1202aab3-8fc9-422c-8dd1-e07c3fb1845a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25245
20438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.2524520438
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.1901766084
Short name T931
Test name
Test status
Simulation time 10101139248 ps
CPU time 13.59 seconds
Started Jun 06 01:45:58 PM PDT 24
Finished Jun 06 01:46:13 PM PDT 24
Peak memory 205680 kb
Host smart-72f31188-6cd6-4c5f-a3a4-8c62c2bab883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19017
66084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.1901766084
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.793123847
Short name T1389
Test name
Test status
Simulation time 15535820027 ps
CPU time 167.49 seconds
Started Jun 06 01:46:00 PM PDT 24
Finished Jun 06 01:48:48 PM PDT 24
Peak memory 205704 kb
Host smart-2c3d0ace-4dbb-4f96-9e64-88597f074dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79312
3847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.793123847
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.1614030210
Short name T1621
Test name
Test status
Simulation time 10144936187 ps
CPU time 14.48 seconds
Started Jun 06 01:46:21 PM PDT 24
Finished Jun 06 01:46:36 PM PDT 24
Peak memory 205616 kb
Host smart-d2e458ad-abc8-476d-af81-9312d57b7eb5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1614030210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.1614030210
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.1942268110
Short name T788
Test name
Test status
Simulation time 10053277444 ps
CPU time 15.55 seconds
Started Jun 06 01:46:21 PM PDT 24
Finished Jun 06 01:46:37 PM PDT 24
Peak memory 205664 kb
Host smart-01f21e89-123c-40f3-a61d-7411bf680bf8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1942268110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.1942268110
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.3370042263
Short name T870
Test name
Test status
Simulation time 10158849694 ps
CPU time 14.57 seconds
Started Jun 06 01:46:22 PM PDT 24
Finished Jun 06 01:46:37 PM PDT 24
Peak memory 205724 kb
Host smart-56180a13-9045-49ea-9541-59dc25d522e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33700
42263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.3370042263
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.1924995612
Short name T467
Test name
Test status
Simulation time 14340846493 ps
CPU time 17.52 seconds
Started Jun 06 01:46:11 PM PDT 24
Finished Jun 06 01:46:30 PM PDT 24
Peak memory 205760 kb
Host smart-21e9e4b4-9c79-4a4d-bb51-9a327dfc3f19
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1924995612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.1924995612
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.3090458154
Short name T1680
Test name
Test status
Simulation time 23330142508 ps
CPU time 24.2 seconds
Started Jun 06 01:46:10 PM PDT 24
Finished Jun 06 01:46:36 PM PDT 24
Peak memory 205728 kb
Host smart-cb90ec39-9108-44f4-a60f-d24bc25a9d14
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3090458154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.3090458154
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.388100624
Short name T1101
Test name
Test status
Simulation time 10058607692 ps
CPU time 13.68 seconds
Started Jun 06 01:46:10 PM PDT 24
Finished Jun 06 01:46:25 PM PDT 24
Peak memory 205764 kb
Host smart-e6821ac4-8b59-42b2-9d8f-076469554ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38810
0624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.388100624
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.3987423963
Short name T1256
Test name
Test status
Simulation time 10846122528 ps
CPU time 13.57 seconds
Started Jun 06 01:46:14 PM PDT 24
Finished Jun 06 01:46:29 PM PDT 24
Peak memory 205684 kb
Host smart-8680f2b0-12f6-480b-a945-bf491cb90ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39874
23963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.3987423963
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.2173870732
Short name T1350
Test name
Test status
Simulation time 10095727438 ps
CPU time 12.88 seconds
Started Jun 06 01:46:11 PM PDT 24
Finished Jun 06 01:46:26 PM PDT 24
Peak memory 205712 kb
Host smart-4dbde1f7-117e-425a-b3d8-a37710b224cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21738
70732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.2173870732
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.3273896888
Short name T1099
Test name
Test status
Simulation time 10054099057 ps
CPU time 14 seconds
Started Jun 06 01:46:09 PM PDT 24
Finished Jun 06 01:46:25 PM PDT 24
Peak memory 205724 kb
Host smart-e53bd551-0d27-4a0f-98b5-6aa0f75688c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32738
96888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3273896888
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.1781963343
Short name T1770
Test name
Test status
Simulation time 10808254508 ps
CPU time 14 seconds
Started Jun 06 01:46:15 PM PDT 24
Finished Jun 06 01:46:30 PM PDT 24
Peak memory 205628 kb
Host smart-f70ce0a6-c779-4456-8a72-3c79a83549ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17819
63343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.1781963343
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.4050972543
Short name T94
Test name
Test status
Simulation time 10202888816 ps
CPU time 15.22 seconds
Started Jun 06 01:46:10 PM PDT 24
Finished Jun 06 01:46:27 PM PDT 24
Peak memory 205692 kb
Host smart-7903b364-83f5-4f58-9a88-dd004fbcd932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40509
72543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.4050972543
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.23327553
Short name T1013
Test name
Test status
Simulation time 10177009479 ps
CPU time 14.24 seconds
Started Jun 06 01:46:24 PM PDT 24
Finished Jun 06 01:46:39 PM PDT 24
Peak memory 205640 kb
Host smart-ade77c05-f062-4be1-a1d2-24bbf4d162e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23327
553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.23327553
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3350832497
Short name T1162
Test name
Test status
Simulation time 10043096851 ps
CPU time 13.99 seconds
Started Jun 06 01:46:18 PM PDT 24
Finished Jun 06 01:46:33 PM PDT 24
Peak memory 205700 kb
Host smart-5e201ba9-447f-47d0-87d2-18a420b240c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33508
32497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3350832497
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.2354180501
Short name T1781
Test name
Test status
Simulation time 10117543019 ps
CPU time 16.22 seconds
Started Jun 06 01:46:11 PM PDT 24
Finished Jun 06 01:46:28 PM PDT 24
Peak memory 205664 kb
Host smart-caf06699-b460-43bc-a7e2-42b17bbeb582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23541
80501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2354180501
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.1870957584
Short name T381
Test name
Test status
Simulation time 10117732955 ps
CPU time 12.86 seconds
Started Jun 06 01:46:14 PM PDT 24
Finished Jun 06 01:46:28 PM PDT 24
Peak memory 205588 kb
Host smart-db4ae70b-a12e-4207-a320-a5b8c3b2c7c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18709
57584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.1870957584
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.2797315087
Short name T414
Test name
Test status
Simulation time 13297002610 ps
CPU time 17.29 seconds
Started Jun 06 01:46:10 PM PDT 24
Finished Jun 06 01:46:28 PM PDT 24
Peak memory 205704 kb
Host smart-d615ba2a-d78e-4fc6-b54f-fa59782c6c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27973
15087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.2797315087
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.134562287
Short name T888
Test name
Test status
Simulation time 10092111384 ps
CPU time 14.14 seconds
Started Jun 06 01:46:09 PM PDT 24
Finished Jun 06 01:46:25 PM PDT 24
Peak memory 205764 kb
Host smart-26ef2e85-2d51-4405-a9d7-6d23ed9c516b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13456
2287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.134562287
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.3588810885
Short name T583
Test name
Test status
Simulation time 16890647985 ps
CPU time 205.25 seconds
Started Jun 06 01:46:13 PM PDT 24
Finished Jun 06 01:49:40 PM PDT 24
Peak memory 205648 kb
Host smart-99174cb1-0620-437c-8aad-282da6283c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35888
10885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.3588810885
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.475986865
Short name T1164
Test name
Test status
Simulation time 10061378105 ps
CPU time 14.43 seconds
Started Jun 06 01:46:11 PM PDT 24
Finished Jun 06 01:46:27 PM PDT 24
Peak memory 205784 kb
Host smart-5368686c-f66f-439c-8e78-d7273b808861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47598
6865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.475986865
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3404822643
Short name T1125
Test name
Test status
Simulation time 10095045895 ps
CPU time 12.68 seconds
Started Jun 06 01:46:12 PM PDT 24
Finished Jun 06 01:46:27 PM PDT 24
Peak memory 205796 kb
Host smart-d461893b-8ab6-4a1c-914c-c95beed01a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34048
22643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3404822643
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.2941100333
Short name T1362
Test name
Test status
Simulation time 10052916184 ps
CPU time 14.16 seconds
Started Jun 06 01:46:11 PM PDT 24
Finished Jun 06 01:46:27 PM PDT 24
Peak memory 205636 kb
Host smart-1b54006d-2a00-46a7-b558-7a750fba4ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29411
00333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.2941100333
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2588422984
Short name T562
Test name
Test status
Simulation time 10098902893 ps
CPU time 13.21 seconds
Started Jun 06 01:46:15 PM PDT 24
Finished Jun 06 01:46:29 PM PDT 24
Peak memory 205764 kb
Host smart-8abea29f-ad80-4b4a-9637-cc53a12c024a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25884
22984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2588422984
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.3464675387
Short name T1724
Test name
Test status
Simulation time 10084456037 ps
CPU time 13.79 seconds
Started Jun 06 01:46:10 PM PDT 24
Finished Jun 06 01:46:26 PM PDT 24
Peak memory 205708 kb
Host smart-df69075a-1110-4acf-a2a1-7f818a677e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34646
75387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.3464675387
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.374205114
Short name T915
Test name
Test status
Simulation time 10048385780 ps
CPU time 15.19 seconds
Started Jun 06 01:46:19 PM PDT 24
Finished Jun 06 01:46:35 PM PDT 24
Peak memory 205636 kb
Host smart-810304a1-d15a-4195-b0f7-4b5f41ee4b00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37420
5114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.374205114
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_eop_single_bit_handling.3297642755
Short name T683
Test name
Test status
Simulation time 10084757412 ps
CPU time 17.09 seconds
Started Jun 06 01:46:18 PM PDT 24
Finished Jun 06 01:46:37 PM PDT 24
Peak memory 205664 kb
Host smart-6cb21215-f6e8-403f-bfc9-2c2c0f999883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32976
42755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_eop_single_bit_handling.3297642755
Directory /workspace/7.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.1972162026
Short name T975
Test name
Test status
Simulation time 10052725698 ps
CPU time 14.77 seconds
Started Jun 06 01:46:22 PM PDT 24
Finished Jun 06 01:46:37 PM PDT 24
Peak memory 205736 kb
Host smart-b8f5f64b-4b3c-4e95-8a06-44d3f45b40a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19721
62026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.1972162026
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.1340864970
Short name T1351
Test name
Test status
Simulation time 10031002659 ps
CPU time 12.52 seconds
Started Jun 06 01:46:24 PM PDT 24
Finished Jun 06 01:46:37 PM PDT 24
Peak memory 205720 kb
Host smart-37287c09-1a76-4811-9fa2-bc3b264fda64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13408
64970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.1340864970
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.2923611569
Short name T645
Test name
Test status
Simulation time 22804195009 ps
CPU time 38.77 seconds
Started Jun 06 01:46:08 PM PDT 24
Finished Jun 06 01:46:49 PM PDT 24
Peak memory 205664 kb
Host smart-90311ddc-441d-45c9-be56-9cc56866314d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29236
11569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.2923611569
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.2450517463
Short name T1649
Test name
Test status
Simulation time 10086695236 ps
CPU time 13.5 seconds
Started Jun 06 01:46:09 PM PDT 24
Finished Jun 06 01:46:24 PM PDT 24
Peak memory 205616 kb
Host smart-edfa3294-b34f-4d50-b5b0-398a0cc66e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24505
17463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.2450517463
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.136664131
Short name T506
Test name
Test status
Simulation time 10121723195 ps
CPU time 13.77 seconds
Started Jun 06 01:46:08 PM PDT 24
Finished Jun 06 01:46:24 PM PDT 24
Peak memory 205688 kb
Host smart-f93bf5dd-e7bd-48b0-9adf-a8fe2fc430e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13666
4131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.136664131
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.3502955863
Short name T178
Test name
Test status
Simulation time 27543932654 ps
CPU time 118.98 seconds
Started Jun 06 01:46:11 PM PDT 24
Finished Jun 06 01:48:12 PM PDT 24
Peak memory 205668 kb
Host smart-640faf45-10a4-49b5-ac1a-9c775569efb7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3502955863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.3502955863
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.1401540616
Short name T1760
Test name
Test status
Simulation time 22575382768 ps
CPU time 86.78 seconds
Started Jun 06 01:46:12 PM PDT 24
Finished Jun 06 01:47:40 PM PDT 24
Peak memory 205724 kb
Host smart-63ca47d3-e256-46c8-9c73-67d92b2864f7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1401540616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.1401540616
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.2934254335
Short name T1626
Test name
Test status
Simulation time 10056506806 ps
CPU time 13.56 seconds
Started Jun 06 01:46:18 PM PDT 24
Finished Jun 06 01:46:32 PM PDT 24
Peak memory 205728 kb
Host smart-7325febb-fb9f-40f6-bec3-0683e6176ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29342
54335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.2934254335
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.2021182619
Short name T1717
Test name
Test status
Simulation time 10070791845 ps
CPU time 13.34 seconds
Started Jun 06 01:46:24 PM PDT 24
Finished Jun 06 01:46:38 PM PDT 24
Peak memory 205676 kb
Host smart-8443738f-b2b3-47b6-8547-9acf15865287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20211
82619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.2021182619
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.4220436306
Short name T1342
Test name
Test status
Simulation time 10059848000 ps
CPU time 16.55 seconds
Started Jun 06 01:46:19 PM PDT 24
Finished Jun 06 01:46:36 PM PDT 24
Peak memory 205760 kb
Host smart-c37ef127-0cca-48ca-8ba1-bb99dd941f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42204
36306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.4220436306
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.989916998
Short name T85
Test name
Test status
Simulation time 10052056725 ps
CPU time 12.81 seconds
Started Jun 06 01:46:22 PM PDT 24
Finished Jun 06 01:46:36 PM PDT 24
Peak memory 205636 kb
Host smart-87fd11ad-11c0-4c5f-b423-84f09287d5ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98991
6998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.989916998
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.4105042431
Short name T801
Test name
Test status
Simulation time 10114609713 ps
CPU time 14.81 seconds
Started Jun 06 01:46:09 PM PDT 24
Finished Jun 06 01:46:25 PM PDT 24
Peak memory 205764 kb
Host smart-590a5ac1-5d01-4eea-967f-6293a2fccc71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41050
42431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.4105042431
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.3797898996
Short name T1968
Test name
Test status
Simulation time 10052963513 ps
CPU time 12.45 seconds
Started Jun 06 01:46:19 PM PDT 24
Finished Jun 06 01:46:32 PM PDT 24
Peak memory 205720 kb
Host smart-f5c1ae0b-07f4-4f2b-b0a9-439b05a83679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37978
98996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.3797898996
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.2546228350
Short name T92
Test name
Test status
Simulation time 10073014296 ps
CPU time 13.73 seconds
Started Jun 06 01:46:21 PM PDT 24
Finished Jun 06 01:46:35 PM PDT 24
Peak memory 205736 kb
Host smart-147c99c5-05ac-4af3-abc4-bd02254ba5f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25462
28350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.2546228350
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.3610043789
Short name T847
Test name
Test status
Simulation time 16376941130 ps
CPU time 192.72 seconds
Started Jun 06 01:46:20 PM PDT 24
Finished Jun 06 01:49:34 PM PDT 24
Peak memory 205688 kb
Host smart-bedd35a6-7e9e-404a-bb8e-4bbaf003c02f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36100
43789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.3610043789
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.3750593052
Short name T1255
Test name
Test status
Simulation time 10184695291 ps
CPU time 14.52 seconds
Started Jun 06 01:46:27 PM PDT 24
Finished Jun 06 01:46:43 PM PDT 24
Peak memory 205688 kb
Host smart-a005f1ab-b2de-4b7f-8d08-f8dcd2146a58
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3750593052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.3750593052
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.3762622466
Short name T1246
Test name
Test status
Simulation time 10094727173 ps
CPU time 13.61 seconds
Started Jun 06 01:46:26 PM PDT 24
Finished Jun 06 01:46:40 PM PDT 24
Peak memory 205724 kb
Host smart-e809cc94-b356-49b7-9052-0bcb8e3a6cb6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3762622466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.3762622466
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.1218077146
Short name T1685
Test name
Test status
Simulation time 10117143079 ps
CPU time 16.27 seconds
Started Jun 06 01:46:26 PM PDT 24
Finished Jun 06 01:46:43 PM PDT 24
Peak memory 205700 kb
Host smart-1353ff1a-7b97-486f-a751-98ab355f19f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12180
77146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.1218077146
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.2565700538
Short name T12
Test name
Test status
Simulation time 14004281706 ps
CPU time 17.02 seconds
Started Jun 06 01:46:21 PM PDT 24
Finished Jun 06 01:46:39 PM PDT 24
Peak memory 205716 kb
Host smart-3d6bc226-6f9c-4d95-a60f-4b0eb7268a7f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2565700538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.2565700538
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.3109594070
Short name T901
Test name
Test status
Simulation time 23325370351 ps
CPU time 28.4 seconds
Started Jun 06 01:46:19 PM PDT 24
Finished Jun 06 01:46:48 PM PDT 24
Peak memory 205696 kb
Host smart-43b85762-47ae-4b54-91bd-bb2ce2923dc8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3109594070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.3109594070
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1233435501
Short name T714
Test name
Test status
Simulation time 10043653745 ps
CPU time 14.79 seconds
Started Jun 06 01:46:19 PM PDT 24
Finished Jun 06 01:46:35 PM PDT 24
Peak memory 205760 kb
Host smart-4bcee4a4-172c-4f38-8e6b-4c89ba9077d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12334
35501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1233435501
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.2415935134
Short name T69
Test name
Test status
Simulation time 10533330256 ps
CPU time 16.81 seconds
Started Jun 06 01:46:22 PM PDT 24
Finished Jun 06 01:46:40 PM PDT 24
Peak memory 205704 kb
Host smart-b578241c-4478-4a15-962f-b4f52c26358e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24159
35134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.2415935134
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.104166424
Short name T1804
Test name
Test status
Simulation time 10088328649 ps
CPU time 16.12 seconds
Started Jun 06 01:46:21 PM PDT 24
Finished Jun 06 01:46:37 PM PDT 24
Peak memory 205732 kb
Host smart-0d808c09-8ffb-4c3e-82fe-3857977c78db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10416
6424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.104166424
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.3786659497
Short name T716
Test name
Test status
Simulation time 10056199566 ps
CPU time 13.28 seconds
Started Jun 06 01:46:19 PM PDT 24
Finished Jun 06 01:46:33 PM PDT 24
Peak memory 205632 kb
Host smart-5e6371e2-a011-4513-8846-8d8769d3ae6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37866
59497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3786659497
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.3768879943
Short name T1585
Test name
Test status
Simulation time 10658504213 ps
CPU time 14.89 seconds
Started Jun 06 01:46:16 PM PDT 24
Finished Jun 06 01:46:32 PM PDT 24
Peak memory 205712 kb
Host smart-82716461-ab10-48f8-bc48-7f23130ff763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37688
79943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.3768879943
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.413793709
Short name T1818
Test name
Test status
Simulation time 10064894425 ps
CPU time 13.95 seconds
Started Jun 06 01:46:22 PM PDT 24
Finished Jun 06 01:46:37 PM PDT 24
Peak memory 205600 kb
Host smart-f23c1951-c941-4f81-a23e-f5f528e8f06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41379
3709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.413793709
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.432184472
Short name T79
Test name
Test status
Simulation time 10183839823 ps
CPU time 15.79 seconds
Started Jun 06 01:46:27 PM PDT 24
Finished Jun 06 01:46:44 PM PDT 24
Peak memory 205664 kb
Host smart-44c9acd9-bb8f-4e99-bced-b097b1fc532c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43218
4472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.432184472
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1721852342
Short name T1308
Test name
Test status
Simulation time 10073731406 ps
CPU time 15.47 seconds
Started Jun 06 01:46:28 PM PDT 24
Finished Jun 06 01:46:45 PM PDT 24
Peak memory 205752 kb
Host smart-20f69e5e-1adf-4996-ae67-c36418b4c563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17218
52342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1721852342
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.2617824635
Short name T538
Test name
Test status
Simulation time 10124147035 ps
CPU time 14.39 seconds
Started Jun 06 01:46:21 PM PDT 24
Finished Jun 06 01:46:37 PM PDT 24
Peak memory 205644 kb
Host smart-7621b1be-47bb-420f-8cb7-99c938cf4604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26178
24635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.2617824635
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.628825411
Short name T1595
Test name
Test status
Simulation time 10216407947 ps
CPU time 15.98 seconds
Started Jun 06 01:46:19 PM PDT 24
Finished Jun 06 01:46:36 PM PDT 24
Peak memory 205612 kb
Host smart-bb0d8c55-057f-4a7a-b052-93fc49a01329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62882
5411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.628825411
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.981633789
Short name T2024
Test name
Test status
Simulation time 13230296615 ps
CPU time 16.98 seconds
Started Jun 06 01:46:20 PM PDT 24
Finished Jun 06 01:46:38 PM PDT 24
Peak memory 206012 kb
Host smart-729c2d41-f547-4913-9b33-89475d1d718d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98163
3789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.981633789
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.2146233345
Short name T1150
Test name
Test status
Simulation time 10091641237 ps
CPU time 14.67 seconds
Started Jun 06 01:46:19 PM PDT 24
Finished Jun 06 01:46:35 PM PDT 24
Peak memory 205712 kb
Host smart-a88e2956-da1a-440d-b060-276ddb6efdfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21462
33345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2146233345
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.2634067542
Short name T1306
Test name
Test status
Simulation time 14636137419 ps
CPU time 45.61 seconds
Started Jun 06 01:46:20 PM PDT 24
Finished Jun 06 01:47:06 PM PDT 24
Peak memory 205704 kb
Host smart-1d47d33f-419a-4da2-875e-15b4e2718034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26340
67542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.2634067542
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1582550276
Short name T1305
Test name
Test status
Simulation time 10092021013 ps
CPU time 16.48 seconds
Started Jun 06 01:46:20 PM PDT 24
Finished Jun 06 01:46:37 PM PDT 24
Peak memory 206008 kb
Host smart-bc8d38d5-d226-48ba-a0c8-67766e4c997d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15825
50276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1582550276
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.728031196
Short name T1904
Test name
Test status
Simulation time 10110575789 ps
CPU time 14.72 seconds
Started Jun 06 01:46:20 PM PDT 24
Finished Jun 06 01:46:36 PM PDT 24
Peak memory 205572 kb
Host smart-8d753487-8d32-46c4-883e-532f98c9e464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72803
1196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.728031196
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.4205076336
Short name T2029
Test name
Test status
Simulation time 10132623160 ps
CPU time 14.46 seconds
Started Jun 06 01:46:22 PM PDT 24
Finished Jun 06 01:46:37 PM PDT 24
Peak memory 205688 kb
Host smart-afe4d5de-5643-4b3c-bfe4-99824371244f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42050
76336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.4205076336
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.1753556996
Short name T367
Test name
Test status
Simulation time 10067178579 ps
CPU time 12.96 seconds
Started Jun 06 01:46:27 PM PDT 24
Finished Jun 06 01:46:40 PM PDT 24
Peak memory 205628 kb
Host smart-f8d3c344-9d22-4d6e-8d16-d2b5cdb97883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17535
56996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1753556996
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.2981787113
Short name T1906
Test name
Test status
Simulation time 10069272259 ps
CPU time 13.75 seconds
Started Jun 06 01:46:30 PM PDT 24
Finished Jun 06 01:46:44 PM PDT 24
Peak memory 205724 kb
Host smart-84943ad2-7d70-4aaa-be94-470e673f535a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29817
87113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.2981787113
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.3042165235
Short name T148
Test name
Test status
Simulation time 10062037779 ps
CPU time 16.63 seconds
Started Jun 06 01:46:24 PM PDT 24
Finished Jun 06 01:46:42 PM PDT 24
Peak memory 205704 kb
Host smart-284c40c0-414e-440e-a8d3-245c85d840b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30421
65235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3042165235
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_eop_single_bit_handling.807136181
Short name T669
Test name
Test status
Simulation time 10101271920 ps
CPU time 15.25 seconds
Started Jun 06 01:46:28 PM PDT 24
Finished Jun 06 01:46:44 PM PDT 24
Peak memory 205908 kb
Host smart-9029da11-6ade-42bf-82ee-d71c32a2740f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80713
6181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_eop_single_bit_handling.807136181
Directory /workspace/8.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.404737889
Short name T1809
Test name
Test status
Simulation time 10050683864 ps
CPU time 13.52 seconds
Started Jun 06 01:46:28 PM PDT 24
Finished Jun 06 01:46:43 PM PDT 24
Peak memory 205716 kb
Host smart-4a837686-831b-4dcf-9f4f-655d505643fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40473
7889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.404737889
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3254737511
Short name T463
Test name
Test status
Simulation time 10069898631 ps
CPU time 13.32 seconds
Started Jun 06 01:46:27 PM PDT 24
Finished Jun 06 01:46:42 PM PDT 24
Peak memory 205660 kb
Host smart-b321d282-622c-4f53-b3c6-736c1acb664d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32547
37511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3254737511
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.1417675471
Short name T166
Test name
Test status
Simulation time 17887062134 ps
CPU time 32.23 seconds
Started Jun 06 01:46:26 PM PDT 24
Finished Jun 06 01:46:58 PM PDT 24
Peak memory 205660 kb
Host smart-4b1aec7c-6fe7-47c9-839b-2df5c670a52e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14176
75471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.1417675471
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.1116801601
Short name T451
Test name
Test status
Simulation time 10077274509 ps
CPU time 15.4 seconds
Started Jun 06 01:46:27 PM PDT 24
Finished Jun 06 01:46:43 PM PDT 24
Peak memory 205700 kb
Host smart-28cf696f-73c8-459a-9a3a-1dede8106cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11168
01601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.1116801601
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3670193979
Short name T1611
Test name
Test status
Simulation time 10132984837 ps
CPU time 13.34 seconds
Started Jun 06 01:46:27 PM PDT 24
Finished Jun 06 01:46:41 PM PDT 24
Peak memory 205728 kb
Host smart-8d8215bc-ceb0-43d8-9801-70ef01e3e128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36701
93979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3670193979
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.3420760892
Short name T186
Test name
Test status
Simulation time 45867944297 ps
CPU time 865.69 seconds
Started Jun 06 01:46:24 PM PDT 24
Finished Jun 06 02:00:51 PM PDT 24
Peak memory 205776 kb
Host smart-405eb3e7-28c8-4b15-b0a9-59baee53aec7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3420760892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.3420760892
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.1665837445
Short name T580
Test name
Test status
Simulation time 31033579935 ps
CPU time 169.9 seconds
Started Jun 06 01:46:26 PM PDT 24
Finished Jun 06 01:49:16 PM PDT 24
Peak memory 205712 kb
Host smart-73b1e39f-2b34-4f92-9bc6-88a04ae913e1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1665837445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.1665837445
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.2068760209
Short name T1127
Test name
Test status
Simulation time 33991358518 ps
CPU time 590 seconds
Started Jun 06 01:46:26 PM PDT 24
Finished Jun 06 01:56:17 PM PDT 24
Peak memory 205748 kb
Host smart-81b354b4-363c-4d11-9fc2-228c36b5c566
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2068760209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.2068760209
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.220252920
Short name T846
Test name
Test status
Simulation time 10073881475 ps
CPU time 16.03 seconds
Started Jun 06 01:46:28 PM PDT 24
Finished Jun 06 01:46:45 PM PDT 24
Peak memory 205960 kb
Host smart-c23459bc-0848-4464-842c-ccce5461c084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22025
2920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.220252920
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.2061247215
Short name T1449
Test name
Test status
Simulation time 10035678679 ps
CPU time 14.88 seconds
Started Jun 06 01:46:25 PM PDT 24
Finished Jun 06 01:46:41 PM PDT 24
Peak memory 205616 kb
Host smart-5bc3c1e4-ed2a-42ab-8ea6-5d698cd69d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20612
47215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.2061247215
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.3820535343
Short name T165
Test name
Test status
Simulation time 10069741763 ps
CPU time 15.27 seconds
Started Jun 06 01:46:28 PM PDT 24
Finished Jun 06 01:46:44 PM PDT 24
Peak memory 205700 kb
Host smart-91bf12f0-9df3-42b9-899f-98895832cbef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38205
35343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.3820535343
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2175484162
Short name T1273
Test name
Test status
Simulation time 10052885463 ps
CPU time 12.54 seconds
Started Jun 06 01:46:30 PM PDT 24
Finished Jun 06 01:46:43 PM PDT 24
Peak memory 205640 kb
Host smart-0e312544-8164-45a6-9f68-36c902eb4ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21754
84162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2175484162
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.4198494512
Short name T949
Test name
Test status
Simulation time 10146068033 ps
CPU time 13.84 seconds
Started Jun 06 01:46:20 PM PDT 24
Finished Jun 06 01:46:35 PM PDT 24
Peak memory 205660 kb
Host smart-49cbf6c8-f030-4e67-bcf6-b0ac00e1949c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41984
94512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.4198494512
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.3005721925
Short name T306
Test name
Test status
Simulation time 10110933912 ps
CPU time 13.1 seconds
Started Jun 06 01:46:27 PM PDT 24
Finished Jun 06 01:46:41 PM PDT 24
Peak memory 205708 kb
Host smart-80ee8b54-1a13-4259-ba4c-6b6f659fe50d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30057
21925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.3005721925
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.1634889621
Short name T412
Test name
Test status
Simulation time 10093184724 ps
CPU time 12.61 seconds
Started Jun 06 01:46:24 PM PDT 24
Finished Jun 06 01:46:38 PM PDT 24
Peak memory 205592 kb
Host smart-88bd532d-dfa0-4dc6-8766-d707d40fbce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16348
89621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.1634889621
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.2151166304
Short name T1283
Test name
Test status
Simulation time 22216411132 ps
CPU time 95.81 seconds
Started Jun 06 01:46:27 PM PDT 24
Finished Jun 06 01:48:03 PM PDT 24
Peak memory 205720 kb
Host smart-883755b0-e51d-4a99-9d60-b26e03cf57ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21511
66304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.2151166304
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.3419748367
Short name T1422
Test name
Test status
Simulation time 10195934996 ps
CPU time 13.57 seconds
Started Jun 06 01:46:44 PM PDT 24
Finished Jun 06 01:46:58 PM PDT 24
Peak memory 205612 kb
Host smart-74a46602-1092-4896-b4ea-be9a26e27fe3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3419748367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.3419748367
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.756983801
Short name T1660
Test name
Test status
Simulation time 10069678394 ps
CPU time 13.25 seconds
Started Jun 06 01:46:44 PM PDT 24
Finished Jun 06 01:46:58 PM PDT 24
Peak memory 205700 kb
Host smart-50c410b3-602a-4cda-a25a-844b707f055a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=756983801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.756983801
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.392049422
Short name T37
Test name
Test status
Simulation time 10111566435 ps
CPU time 16.02 seconds
Started Jun 06 01:46:45 PM PDT 24
Finished Jun 06 01:47:02 PM PDT 24
Peak memory 205752 kb
Host smart-2ac8cc74-849b-43ca-b1ce-02e9aedf9e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39204
9422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.392049422
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.2585955132
Short name T1920
Test name
Test status
Simulation time 14439520808 ps
CPU time 18.06 seconds
Started Jun 06 01:46:33 PM PDT 24
Finished Jun 06 01:46:52 PM PDT 24
Peak memory 205680 kb
Host smart-56869b45-cef2-48ec-9a09-fe6de0a9ea61
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2585955132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.2585955132
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.3600424325
Short name T1129
Test name
Test status
Simulation time 23296093788 ps
CPU time 32.15 seconds
Started Jun 06 01:46:38 PM PDT 24
Finished Jun 06 01:47:11 PM PDT 24
Peak memory 205776 kb
Host smart-ff94afc3-0a5f-4b98-ba1e-cb6faf1142a3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3600424325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.3600424325
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2217936782
Short name T1319
Test name
Test status
Simulation time 10068143586 ps
CPU time 13.36 seconds
Started Jun 06 01:46:35 PM PDT 24
Finished Jun 06 01:46:49 PM PDT 24
Peak memory 205652 kb
Host smart-849dae23-88bf-4a2e-8537-16ebcd3d9479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22179
36782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2217936782
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.1674278262
Short name T61
Test name
Test status
Simulation time 10085109191 ps
CPU time 12.51 seconds
Started Jun 06 01:46:37 PM PDT 24
Finished Jun 06 01:46:50 PM PDT 24
Peak memory 205752 kb
Host smart-e3a4434d-1656-47f9-a072-050c477b8fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16742
78262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.1674278262
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.3178984805
Short name T2013
Test name
Test status
Simulation time 10616757677 ps
CPU time 14.36 seconds
Started Jun 06 01:46:38 PM PDT 24
Finished Jun 06 01:46:53 PM PDT 24
Peak memory 205668 kb
Host smart-70ec1548-2b18-49f9-91e2-5a9ac776e9af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31789
84805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.3178984805
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.1351895386
Short name T755
Test name
Test status
Simulation time 10031061834 ps
CPU time 13.43 seconds
Started Jun 06 01:46:36 PM PDT 24
Finished Jun 06 01:46:51 PM PDT 24
Peak memory 205628 kb
Host smart-fb2d3d5a-506a-4638-bafa-5b200060a3a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13518
95386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1351895386
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.3142393664
Short name T1315
Test name
Test status
Simulation time 10064120517 ps
CPU time 13.01 seconds
Started Jun 06 01:46:37 PM PDT 24
Finished Jun 06 01:46:51 PM PDT 24
Peak memory 205644 kb
Host smart-5544df31-9735-46bb-b4b7-dcc56fafba77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31423
93664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.3142393664
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.3206517219
Short name T2004
Test name
Test status
Simulation time 10647692528 ps
CPU time 14.86 seconds
Started Jun 06 01:46:44 PM PDT 24
Finished Jun 06 01:47:00 PM PDT 24
Peak memory 205696 kb
Host smart-e105e9a2-96db-4a5b-baf2-b8bd701e9069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32065
17219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.3206517219
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1822912060
Short name T1292
Test name
Test status
Simulation time 10234956809 ps
CPU time 14.55 seconds
Started Jun 06 01:46:37 PM PDT 24
Finished Jun 06 01:46:52 PM PDT 24
Peak memory 205732 kb
Host smart-40bfc99d-5cc4-4064-a7a4-845b49264c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18229
12060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1822912060
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.737221901
Short name T841
Test name
Test status
Simulation time 10137557134 ps
CPU time 13.19 seconds
Started Jun 06 01:46:52 PM PDT 24
Finished Jun 06 01:47:06 PM PDT 24
Peak memory 205796 kb
Host smart-cce2d774-2765-4edf-8551-5211b6d47e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73722
1901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.737221901
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.2340920532
Short name T1527
Test name
Test status
Simulation time 10054604295 ps
CPU time 13.68 seconds
Started Jun 06 01:46:51 PM PDT 24
Finished Jun 06 01:47:06 PM PDT 24
Peak memory 205688 kb
Host smart-57c290c8-74f2-425b-9aab-85f2d4a6dee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23409
20532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.2340920532
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3189504476
Short name T420
Test name
Test status
Simulation time 10105445866 ps
CPU time 13.64 seconds
Started Jun 06 01:46:35 PM PDT 24
Finished Jun 06 01:46:50 PM PDT 24
Peak memory 205600 kb
Host smart-64b45eaf-61a3-43be-8efb-d35afcb3d9ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31895
04476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3189504476
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.4249448045
Short name T55
Test name
Test status
Simulation time 10154988140 ps
CPU time 13.24 seconds
Started Jun 06 01:46:36 PM PDT 24
Finished Jun 06 01:46:50 PM PDT 24
Peak memory 205764 kb
Host smart-7ee7fe8d-f552-4f1e-b669-9fac404c9663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42494
48045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.4249448045
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.105011148
Short name T1110
Test name
Test status
Simulation time 13221575881 ps
CPU time 16.77 seconds
Started Jun 06 01:46:38 PM PDT 24
Finished Jun 06 01:46:55 PM PDT 24
Peak memory 205632 kb
Host smart-d14398ab-1495-4bd0-b3d0-5d32585ca745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10501
1148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.105011148
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3937973615
Short name T400
Test name
Test status
Simulation time 10089517199 ps
CPU time 13.22 seconds
Started Jun 06 01:46:35 PM PDT 24
Finished Jun 06 01:46:49 PM PDT 24
Peak memory 205604 kb
Host smart-3483a960-1448-42d4-85b6-4b092ea96055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39379
73615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3937973615
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.902811422
Short name T1380
Test name
Test status
Simulation time 14861234563 ps
CPU time 56.44 seconds
Started Jun 06 01:46:36 PM PDT 24
Finished Jun 06 01:47:34 PM PDT 24
Peak memory 205724 kb
Host smart-d4b84ed5-6051-4955-ab97-5cf221c0f4cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90281
1422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.902811422
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3857812886
Short name T1388
Test name
Test status
Simulation time 10146632046 ps
CPU time 15.89 seconds
Started Jun 06 01:46:35 PM PDT 24
Finished Jun 06 01:46:52 PM PDT 24
Peak memory 205724 kb
Host smart-b50b3826-b30e-4003-aa0e-69e55597d7a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38578
12886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3857812886
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1562996743
Short name T101
Test name
Test status
Simulation time 10105711114 ps
CPU time 13.18 seconds
Started Jun 06 01:46:35 PM PDT 24
Finished Jun 06 01:46:49 PM PDT 24
Peak memory 205672 kb
Host smart-ca13a175-55fc-4fe4-8d24-1fdbfb553adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15629
96743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1562996743
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.1804610337
Short name T1722
Test name
Test status
Simulation time 10056662791 ps
CPU time 13.95 seconds
Started Jun 06 01:46:35 PM PDT 24
Finished Jun 06 01:46:50 PM PDT 24
Peak memory 205672 kb
Host smart-6586e963-0099-41d5-8fa7-c1eccbf76979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18046
10337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.1804610337
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.1040983919
Short name T1138
Test name
Test status
Simulation time 10092576603 ps
CPU time 12.88 seconds
Started Jun 06 01:46:36 PM PDT 24
Finished Jun 06 01:46:50 PM PDT 24
Peak memory 205764 kb
Host smart-d2888208-e0a7-4e74-8a6c-970852cbbe6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10409
83919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.1040983919
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.1038803556
Short name T1960
Test name
Test status
Simulation time 10069708264 ps
CPU time 16.11 seconds
Started Jun 06 01:46:34 PM PDT 24
Finished Jun 06 01:46:51 PM PDT 24
Peak memory 205772 kb
Host smart-8bee3abd-bbd2-4456-a962-df0ba82644cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10388
03556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.1038803556
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.1018008964
Short name T1297
Test name
Test status
Simulation time 10065015109 ps
CPU time 13.47 seconds
Started Jun 06 01:46:47 PM PDT 24
Finished Jun 06 01:47:01 PM PDT 24
Peak memory 205776 kb
Host smart-41f8c1f6-574a-46cf-95ab-30da284274e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10180
08964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.1018008964
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_eop_single_bit_handling.2464777164
Short name T1958
Test name
Test status
Simulation time 10103367449 ps
CPU time 15.52 seconds
Started Jun 06 01:46:45 PM PDT 24
Finished Jun 06 01:47:01 PM PDT 24
Peak memory 205720 kb
Host smart-4c1666a9-7235-4a96-bd99-30ac3a64d30a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24647
77164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_eop_single_bit_handling.2464777164
Directory /workspace/9.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.158725974
Short name T82
Test name
Test status
Simulation time 10096980749 ps
CPU time 13.78 seconds
Started Jun 06 01:46:43 PM PDT 24
Finished Jun 06 01:46:58 PM PDT 24
Peak memory 205736 kb
Host smart-89142d26-0e13-42df-a376-060666d6a7ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15872
5974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.158725974
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.223048832
Short name T1441
Test name
Test status
Simulation time 10054185718 ps
CPU time 16.04 seconds
Started Jun 06 01:46:44 PM PDT 24
Finished Jun 06 01:47:01 PM PDT 24
Peak memory 205632 kb
Host smart-a4308412-9e06-41a3-a9ee-b2141100c5d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22304
8832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.223048832
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.3982418853
Short name T1371
Test name
Test status
Simulation time 25038619740 ps
CPU time 45.66 seconds
Started Jun 06 01:46:45 PM PDT 24
Finished Jun 06 01:47:31 PM PDT 24
Peak memory 205672 kb
Host smart-19f43d5e-b08a-454a-abe3-694f45fe3bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39824
18853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.3982418853
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.2909886646
Short name T807
Test name
Test status
Simulation time 10078743120 ps
CPU time 13 seconds
Started Jun 06 01:46:45 PM PDT 24
Finished Jun 06 01:46:59 PM PDT 24
Peak memory 205728 kb
Host smart-83120441-36d6-4ddb-85b2-8c8f82850517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29098
86646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.2909886646
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.1841267751
Short name T1791
Test name
Test status
Simulation time 10069098881 ps
CPU time 15.14 seconds
Started Jun 06 01:46:45 PM PDT 24
Finished Jun 06 01:47:01 PM PDT 24
Peak memory 206012 kb
Host smart-0ab35ad8-244f-4dea-8f06-069ce7b28bfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18412
67751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1841267751
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.1175723486
Short name T168
Test name
Test status
Simulation time 17465848476 ps
CPU time 61.78 seconds
Started Jun 06 01:46:47 PM PDT 24
Finished Jun 06 01:47:49 PM PDT 24
Peak memory 205760 kb
Host smart-c688282c-283a-426e-a5dd-60ff093f3621
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1175723486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.1175723486
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.547033647
Short name T360
Test name
Test status
Simulation time 25830957956 ps
CPU time 104.89 seconds
Started Jun 06 01:46:44 PM PDT 24
Finished Jun 06 01:48:31 PM PDT 24
Peak memory 205716 kb
Host smart-31880d2c-30b6-4907-8338-4428428d4d4d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=547033647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.547033647
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.1343398787
Short name T723
Test name
Test status
Simulation time 39366071729 ps
CPU time 246.26 seconds
Started Jun 06 01:46:45 PM PDT 24
Finished Jun 06 01:50:52 PM PDT 24
Peak memory 205784 kb
Host smart-72ad4911-ca44-43e6-8bd8-e577f93153a7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1343398787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.1343398787
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.3316136835
Short name T1641
Test name
Test status
Simulation time 10095306748 ps
CPU time 13.38 seconds
Started Jun 06 01:46:44 PM PDT 24
Finished Jun 06 01:46:58 PM PDT 24
Peak memory 205712 kb
Host smart-b065dc3e-a8a9-4bcf-9363-9807c1f90e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33161
36835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.3316136835
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.3813486469
Short name T576
Test name
Test status
Simulation time 10050816964 ps
CPU time 13.1 seconds
Started Jun 06 01:46:51 PM PDT 24
Finished Jun 06 01:47:05 PM PDT 24
Peak memory 205752 kb
Host smart-56464586-63f6-4013-b46f-af798e39e157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38134
86469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.3813486469
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.339368397
Short name T1291
Test name
Test status
Simulation time 10078783084 ps
CPU time 15.33 seconds
Started Jun 06 01:46:45 PM PDT 24
Finished Jun 06 01:47:01 PM PDT 24
Peak memory 205692 kb
Host smart-7b9972c2-fafd-42e7-96e0-a79d39888d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33936
8397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.339368397
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.12217873
Short name T762
Test name
Test status
Simulation time 10053658441 ps
CPU time 13.89 seconds
Started Jun 06 01:46:45 PM PDT 24
Finished Jun 06 01:47:00 PM PDT 24
Peak memory 205692 kb
Host smart-f88d14f6-6b3c-408b-a1ae-e6be611fed62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12217
873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.12217873
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.3374548795
Short name T1951
Test name
Test status
Simulation time 10128702969 ps
CPU time 13.16 seconds
Started Jun 06 01:46:27 PM PDT 24
Finished Jun 06 01:46:41 PM PDT 24
Peak memory 205656 kb
Host smart-8e7b51ca-9fb2-4dee-ac16-d12f61365660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33745
48795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.3374548795
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.2298802924
Short name T362
Test name
Test status
Simulation time 10081694634 ps
CPU time 13.44 seconds
Started Jun 06 01:46:52 PM PDT 24
Finished Jun 06 01:47:06 PM PDT 24
Peak memory 205704 kb
Host smart-9caa4f70-5f11-4ff4-867e-ac92e22411d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22988
02924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2298802924
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.2134453777
Short name T759
Test name
Test status
Simulation time 10088426795 ps
CPU time 14.48 seconds
Started Jun 06 01:46:47 PM PDT 24
Finished Jun 06 01:47:01 PM PDT 24
Peak memory 205752 kb
Host smart-442ae851-0a81-4010-85b4-21f4d04b6ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21344
53777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.2134453777
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.912393336
Short name T1457
Test name
Test status
Simulation time 21889262625 ps
CPU time 125.58 seconds
Started Jun 06 01:46:46 PM PDT 24
Finished Jun 06 01:48:52 PM PDT 24
Peak memory 205724 kb
Host smart-ee7419bd-eed1-4d8b-8d15-f4fe908b7aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91239
3336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.912393336
Directory /workspace/9.usbdev_streaming_out/latest
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