Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	28475	1		T1	3		T2	3		T3	4
all_values[1]	28475	1		T1	3		T2	3		T3	4
all_values[2]	28475	1		T1	3		T2	3		T3	4
all_values[3]	28475	1		T1	3		T2	3		T3	4
all_values[4]	28475	1		T1	3		T2	3		T3	4
all_values[5]	28475	1		T1	3		T2	3		T3	4
all_values[6]	28475	1		T1	3		T2	3		T3	4
all_values[7]	28475	1		T1	3		T2	3		T3	4
all_values[8]	28475	1		T1	3		T2	3		T3	4
all_values[9]	28475	1		T1	3		T2	3		T3	4
all_values[10]	28475	1		T1	3		T2	3		T3	4
all_values[11]	28475	1		T1	3		T2	3		T3	4
all_values[12]	28475	1		T1	3		T2	3		T3	4
all_values[13]	28475	1		T1	3		T2	3		T3	4
all_values[14]	28475	1		T1	3		T2	3		T3	4
all_values[15]	28475	1		T1	3		T2	3		T3	4
all_values[16]	28475	1		T1	3		T2	3		T3	4
all_values[17]	28475	1		T1	3		T2	3		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	506433	1		T1	51		T2	51		T3	72
auto[1]	6117	1		T1	3		T2	3		T34	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	507538	1		T1	54		T2	54		T3	72
auto[1]	5012	1		T91	134		T92	126		T93	72

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	27463	1		T1	3		T2	3		T3	4
all_values[0]	auto[0]	auto[1]	140	1		T91	6		T92	3		T93	3
all_values[0]	auto[1]	auto[0]	734	1		T34	3		T19	3		T50	4
all_values[0]	auto[1]	auto[1]	138	1		T91	2		T92	5		T93	1
all_values[1]	auto[0]	auto[0]	26027	1		T3	4		T28	6		T34	3
all_values[1]	auto[0]	auto[1]	127	1		T91	6		T92	2		T193	6
all_values[1]	auto[1]	auto[0]	2174	1		T1	3		T2	3		T7	4
all_values[1]	auto[1]	auto[1]	147	1		T91	2		T92	5		T93	4
all_values[2]	auto[0]	auto[0]	28077	1		T1	3		T2	3		T3	4
all_values[2]	auto[0]	auto[1]	132	1		T92	3		T193	3		T194	5
all_values[2]	auto[1]	auto[0]	130	1		T17	2		T44	2		T45	2
all_values[2]	auto[1]	auto[1]	136	1		T91	8		T92	5		T93	3
all_values[3]	auto[0]	auto[0]	28164	1		T1	3		T2	3		T3	4
all_values[3]	auto[0]	auto[1]	141	1		T91	3		T92	2		T93	5
all_values[3]	auto[1]	auto[0]	31	1		T92	2		T261	2		T260	1
all_values[3]	auto[1]	auto[1]	139	1		T91	5		T92	3		T193	6
all_values[4]	auto[0]	auto[0]	28169	1		T1	3		T2	3		T3	4
all_values[4]	auto[0]	auto[1]	135	1		T92	1		T93	4		T193	8
all_values[4]	auto[1]	auto[0]	16	1		T91	1		T92	1		T93	1
all_values[4]	auto[1]	auto[1]	155	1		T91	7		T92	4		T194	3
all_values[5]	auto[0]	auto[0]	28184	1		T1	3		T2	3		T3	4
all_values[5]	auto[0]	auto[1]	111	1		T92	2		T93	5		T193	1
all_values[5]	auto[1]	auto[0]	28	1		T91	1		T92	1		T195	1
all_values[5]	auto[1]	auto[1]	152	1		T91	6		T92	4		T193	6
all_values[6]	auto[0]	auto[0]	28183	1		T1	3		T2	3		T3	4
all_values[6]	auto[0]	auto[1]	116	1		T91	1		T92	1		T93	1
all_values[6]	auto[1]	auto[0]	25	1		T195	3		T260	1		T262	1
all_values[6]	auto[1]	auto[1]	151	1		T91	7		T92	6		T93	3
all_values[7]	auto[0]	auto[0]	28175	1		T1	3		T2	3		T3	4
all_values[7]	auto[0]	auto[1]	123	1		T91	6		T92	2		T93	2
all_values[7]	auto[1]	auto[0]	23	1		T194	3		T195	1		T261	2
all_values[7]	auto[1]	auto[1]	154	1		T91	2		T92	6		T93	3
all_values[8]	auto[0]	auto[0]	28171	1		T1	3		T2	3		T3	4
all_values[8]	auto[0]	auto[1]	138	1		T91	1		T92	3		T93	1
all_values[8]	auto[1]	auto[0]	30	1		T92	1		T193	1		T194	2
all_values[8]	auto[1]	auto[1]	136	1		T91	7		T92	3		T93	4
all_values[9]	auto[0]	auto[0]	28162	1		T1	3		T2	3		T3	4
all_values[9]	auto[0]	auto[1]	135	1		T91	1		T92	2		T93	3
all_values[9]	auto[1]	auto[0]	20	1		T91	1		T193	2		T261	1
all_values[9]	auto[1]	auto[1]	158	1		T91	5		T92	6		T193	5
all_values[10]	auto[0]	auto[0]	28165	1		T1	3		T2	3		T3	4
all_values[10]	auto[0]	auto[1]	146	1		T91	5		T92	4		T93	2
all_values[10]	auto[1]	auto[0]	25	1		T263	2		T264	2		T262	2
all_values[10]	auto[1]	auto[1]	139	1		T91	3		T92	4		T93	3
all_values[11]	auto[0]	auto[0]	28067	1		T1	3		T2	3		T3	4
all_values[11]	auto[0]	auto[1]	141	1		T91	2		T92	2		T193	7
all_values[11]	auto[1]	auto[0]	141	1		T48	2		T49	2		T62	2
all_values[11]	auto[1]	auto[1]	126	1		T91	6		T92	6		T193	1
all_values[12]	auto[0]	auto[0]	28174	1		T1	3		T2	3		T3	4
all_values[12]	auto[0]	auto[1]	162	1		T91	8		T92	1		T93	4
all_values[12]	auto[1]	auto[0]	18	1		T265	2		T266	2		T267	2
all_values[12]	auto[1]	auto[1]	121	1		T92	7		T93	1		T193	4
all_values[13]	auto[0]	auto[0]	28166	1		T1	3		T2	3		T3	4
all_values[13]	auto[0]	auto[1]	135	1		T91	5		T92	3		T93	1
all_values[13]	auto[1]	auto[0]	28	1		T92	3		T93	1		T194	1
all_values[13]	auto[1]	auto[1]	146	1		T91	3		T92	1		T93	3
all_values[14]	auto[0]	auto[0]	28162	1		T1	3		T2	3		T3	4
all_values[14]	auto[0]	auto[1]	148	1		T91	6		T92	5		T93	1
all_values[14]	auto[1]	auto[0]	19	1		T261	2		T264	2		T268	1
all_values[14]	auto[1]	auto[1]	146	1		T91	2		T92	3		T93	4
all_values[15]	auto[0]	auto[0]	28163	1		T1	3		T2	3		T3	4
all_values[15]	auto[0]	auto[1]	135	1		T91	1		T92	1		T93	3
all_values[15]	auto[1]	auto[0]	18	1		T195	2		T262	1		T269	1
all_values[15]	auto[1]	auto[1]	159	1		T91	7		T92	7		T93	1
all_values[16]	auto[0]	auto[0]	28170	1		T1	3		T2	3		T3	4
all_values[16]	auto[0]	auto[1]	143	1		T91	4		T92	2		T93	3
all_values[16]	auto[1]	auto[0]	29	1		T91	1		T93	2		T195	1
all_values[16]	auto[1]	auto[1]	133	1		T91	3		T92	6		T193	4
all_values[17]	auto[0]	auto[0]	28176	1		T1	3		T2	3		T3	4
all_values[17]	auto[0]	auto[1]	107	1		T91	3		T93	4		T194	6
all_values[17]	auto[1]	auto[0]	31	1		T91	2		T92	1		T263	1
all_values[17]	auto[1]	auto[1]	161	1		T91	1		T92	6		T193	8