Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	28475	1		T1	3		T2	3		T3	4
all_pins[1]	28475	1		T1	3		T2	3		T3	4
all_pins[2]	28475	1		T1	3		T2	3		T3	4
all_pins[3]	28475	1		T1	3		T2	3		T3	4
all_pins[4]	28475	1		T1	3		T2	3		T3	4
all_pins[5]	28475	1		T1	3		T2	3		T3	4
all_pins[6]	28475	1		T1	3		T2	3		T3	4
all_pins[7]	28475	1		T1	3		T2	3		T3	4
all_pins[8]	28475	1		T1	3		T2	3		T3	4
all_pins[9]	28475	1		T1	3		T2	3		T3	4
all_pins[10]	28475	1		T1	3		T2	3		T3	4
all_pins[11]	28475	1		T1	3		T2	3		T3	4
all_pins[12]	28475	1		T1	3		T2	3		T3	4
all_pins[13]	28475	1		T1	3		T2	3		T3	4
all_pins[14]	28475	1		T1	3		T2	3		T3	4
all_pins[15]	28475	1		T1	3		T2	3		T3	4
all_pins[16]	28475	1		T1	3		T2	3		T3	4
all_pins[17]	28475	1		T1	3		T2	3		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	510005	1		T1	53		T2	53		T3	72
values[0x1]	2545	1		T1	1		T2	1		T7	1
transitions[0x0=>0x1]	2237	1		T1	1		T2	1		T7	1
transitions[0x1=>0x0]	2250	1		T1	1		T2	1		T7	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	28312	1		T1	3		T2	3		T3	4
all_pins[0]	values[0x1]	163	1		T50	1		T270	1		T271	1
all_pins[0]	transitions[0x0=>0x1]	148	1		T50	1		T270	1		T271	1
all_pins[0]	transitions[0x1=>0x0]	1190	1		T1	1		T2	1		T7	1
all_pins[1]	values[0x0]	27270	1		T1	2		T2	2		T3	4
all_pins[1]	values[0x1]	1205	1		T1	1		T2	1		T7	1
all_pins[1]	transitions[0x0=>0x1]	1191	1		T1	1		T2	1		T7	1
all_pins[1]	transitions[0x1=>0x0]	99	1		T17	1		T44	1		T45	1
all_pins[2]	values[0x0]	28362	1		T1	3		T2	3		T3	4
all_pins[2]	values[0x1]	113	1		T17	1		T44	1		T45	1
all_pins[2]	transitions[0x0=>0x1]	102	1		T17	1		T44	1		T45	1
all_pins[2]	transitions[0x1=>0x0]	62	1		T91	2		T193	4		T194	2
all_pins[3]	values[0x0]	28402	1		T1	3		T2	3		T3	4
all_pins[3]	values[0x1]	73	1		T91	3		T193	4		T194	2
all_pins[3]	transitions[0x0=>0x1]	54	1		T91	1		T193	4		T194	2
all_pins[3]	transitions[0x1=>0x0]	49	1		T91	1		T92	2		T195	2
all_pins[4]	values[0x0]	28407	1		T1	3		T2	3		T3	4
all_pins[4]	values[0x1]	68	1		T91	3		T92	2		T195	2
all_pins[4]	transitions[0x0=>0x1]	46	1		T92	2		T195	1		T261	1
all_pins[4]	transitions[0x1=>0x0]	54	1		T91	1		T193	1		T261	3
all_pins[5]	values[0x0]	28399	1		T1	3		T2	3		T3	4
all_pins[5]	values[0x1]	76	1		T91	4		T193	1		T195	1
all_pins[5]	transitions[0x0=>0x1]	53	1		T91	2		T193	1		T195	1
all_pins[5]	transitions[0x1=>0x0]	53	1		T92	2		T93	2		T193	1
all_pins[6]	values[0x0]	28399	1		T1	3		T2	3		T3	4
all_pins[6]	values[0x1]	76	1		T91	2		T92	2		T93	2
all_pins[6]	transitions[0x0=>0x1]	56	1		T91	2		T92	2		T93	1
all_pins[6]	transitions[0x1=>0x0]	40	1		T91	1		T92	1		T193	1
all_pins[7]	values[0x0]	28415	1		T1	3		T2	3		T3	4
all_pins[7]	values[0x1]	60	1		T91	1		T92	1		T93	1
all_pins[7]	transitions[0x0=>0x1]	50	1		T92	1		T93	1		T193	2
all_pins[7]	transitions[0x1=>0x0]	34	1		T91	2		T92	1		T194	1
all_pins[8]	values[0x0]	28431	1		T1	3		T2	3		T3	4
all_pins[8]	values[0x1]	44	1		T91	3		T92	1		T194	1
all_pins[8]	transitions[0x0=>0x1]	31	1		T91	3		T92	1		T261	2
all_pins[8]	transitions[0x1=>0x0]	57	1		T92	1		T193	4		T194	1
all_pins[9]	values[0x0]	28405	1		T1	3		T2	3		T3	4
all_pins[9]	values[0x1]	70	1		T92	1		T193	4		T194	2
all_pins[9]	transitions[0x0=>0x1]	51	1		T193	3		T194	2		T195	2
all_pins[9]	transitions[0x1=>0x0]	48	1		T91	1		T92	3		T194	1
all_pins[10]	values[0x0]	28408	1		T1	3		T2	3		T3	4
all_pins[10]	values[0x1]	67	1		T91	1		T92	4		T193	1
all_pins[10]	transitions[0x0=>0x1]	52	1		T92	2		T193	1		T194	1
all_pins[10]	transitions[0x1=>0x0]	98	1		T48	1		T49	1		T62	1
all_pins[11]	values[0x0]	28362	1		T1	3		T2	3		T3	4
all_pins[11]	values[0x1]	113	1		T48	1		T49	1		T62	1
all_pins[11]	transitions[0x0=>0x1]	102	1		T48	1		T49	1		T62	1
all_pins[11]	transitions[0x1=>0x0]	51	1		T92	2		T93	1		T195	1
all_pins[12]	values[0x0]	28413	1		T1	3		T2	3		T3	4
all_pins[12]	values[0x1]	62	1		T92	6		T93	1		T195	2
all_pins[12]	transitions[0x0=>0x1]	47	1		T92	5		T93	1		T195	2
all_pins[12]	transitions[0x1=>0x0]	55	1		T91	3		T93	2		T193	6
all_pins[13]	values[0x0]	28405	1		T1	3		T2	3		T3	4
all_pins[13]	values[0x1]	70	1		T91	3		T92	1		T93	2
all_pins[13]	transitions[0x0=>0x1]	48	1		T91	2		T92	1		T193	5
all_pins[13]	transitions[0x1=>0x0]	49	1		T92	3		T193	1		T194	2
all_pins[14]	values[0x0]	28404	1		T1	3		T2	3		T3	4
all_pins[14]	values[0x1]	71	1		T91	1		T92	3		T93	2
all_pins[14]	transitions[0x0=>0x1]	50	1		T92	2		T93	2		T193	2
all_pins[14]	transitions[0x1=>0x0]	62	1		T91	4		T92	2		T93	1
all_pins[15]	values[0x0]	28392	1		T1	3		T2	3		T3	4
all_pins[15]	values[0x1]	83	1		T91	5		T92	3		T93	1
all_pins[15]	transitions[0x0=>0x1]	69	1		T91	5		T92	1		T93	1
all_pins[15]	transitions[0x1=>0x0]	53	1		T92	2		T193	3		T194	3
all_pins[16]	values[0x0]	28408	1		T1	3		T2	3		T3	4
all_pins[16]	values[0x1]	67	1		T92	4		T193	4		T194	3
all_pins[16]	transitions[0x0=>0x1]	51	1		T92	3		T193	2		T194	3
all_pins[16]	transitions[0x1=>0x0]	48	1		T91	1		T92	1		T193	1
all_pins[17]	values[0x0]	28411	1		T1	3		T2	3		T3	4
all_pins[17]	values[0x1]	64	1		T91	1		T92	2		T193	3
all_pins[17]	transitions[0x0=>0x1]	36	1		T91	1		T92	2		T193	1
all_pins[17]	transitions[0x1=>0x0]	148	1		T50	1		T270	1		T271	1