Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1		T91	7		T92	7		T93	4
all_values[1]	284	1		T91	7		T92	7		T93	4
all_values[2]	284	1		T91	7		T92	7		T93	4
all_values[3]	284	1		T91	7		T92	7		T93	4
all_values[4]	284	1		T91	7		T92	7		T93	4
all_values[5]	284	1		T91	7		T92	7		T93	4
all_values[6]	284	1		T91	7		T92	7		T93	4
all_values[7]	284	1		T91	7		T92	7		T93	4
all_values[8]	284	1		T91	7		T92	7		T93	4
all_values[9]	284	1		T91	7		T92	7		T93	4
all_values[10]	284	1		T91	7		T92	7		T93	4
all_values[11]	284	1		T91	7		T92	7		T93	4
all_values[12]	284	1		T91	7		T92	7		T93	4
all_values[13]	284	1		T91	7		T92	7		T93	4
all_values[14]	284	1		T91	7		T92	7		T93	4
all_values[15]	284	1		T91	7		T92	7		T93	4
all_values[16]	284	1		T91	7		T92	7		T93	4
all_values[17]	284	1		T91	7		T92	7		T93	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2815	1		T91	69		T92	46		T93	47
auto[1]	2297	1		T91	57		T92	80		T93	25

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	940	1		T91	10		T92	18		T93	17
auto[1]	4172	1		T91	116		T92	108		T93	55

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3044	1		T91	69		T92	78		T93	48
auto[1]	2068	1		T91	57		T92	48		T93	24

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	30	1		T93	1		T194	1		T261	1
all_values[0]	auto[0]	auto[0]	auto[1]	61	1		T91	2		T92	1		T93	1
all_values[0]	auto[0]	auto[1]	auto[0]	22	1		T261	1		T263	1		T262	1
all_values[0]	auto[0]	auto[1]	auto[1]	50	1		T91	1		T92	1		T193	1
all_values[0]	auto[1]	auto[0]	auto[1]	64	1		T91	2		T92	4		T93	1
all_values[0]	auto[1]	auto[1]	auto[1]	57	1		T91	2		T92	1		T93	1
all_values[1]	auto[0]	auto[0]	auto[0]	30	1		T93	1		T195	2		T261	1
all_values[1]	auto[0]	auto[0]	auto[1]	55	1		T91	3		T92	1		T193	3
all_values[1]	auto[0]	auto[1]	auto[0]	25	1		T92	1		T261	1		T260	3
all_values[1]	auto[0]	auto[1]	auto[1]	64	1		T91	2		T92	3		T93	2
all_values[1]	auto[1]	auto[0]	auto[1]	62	1		T91	2		T92	1		T193	1
all_values[1]	auto[1]	auto[1]	auto[1]	48	1		T92	1		T93	1		T194	1
all_values[2]	auto[0]	auto[0]	auto[0]	37	1		T93	2		T193	2		T195	1
all_values[2]	auto[0]	auto[0]	auto[1]	54	1		T92	2		T193	1		T194	2
all_values[2]	auto[0]	auto[1]	auto[0]	24	1		T193	1		T194	1		T260	1
all_values[2]	auto[0]	auto[1]	auto[1]	56	1		T91	3		T92	2		T93	1
all_values[2]	auto[1]	auto[0]	auto[1]	60	1		T91	1		T92	1		T194	2
all_values[2]	auto[1]	auto[1]	auto[1]	53	1		T91	3		T92	2		T93	1
all_values[3]	auto[0]	auto[0]	auto[0]	32	1		T195	2		T261	2		T260	2
all_values[3]	auto[0]	auto[0]	auto[1]	60	1		T91	2		T92	2		T93	1
all_values[3]	auto[0]	auto[1]	auto[0]	20	1		T92	3		T261	1		T262	2
all_values[3]	auto[0]	auto[1]	auto[1]	58	1		T91	2		T92	1		T193	2
all_values[3]	auto[1]	auto[0]	auto[1]	63	1		T91	3		T92	1		T93	3
all_values[3]	auto[1]	auto[1]	auto[1]	51	1		T193	1		T261	2		T263	4
all_values[4]	auto[0]	auto[0]	auto[0]	31	1		T91	1		T92	3		T93	1
all_values[4]	auto[0]	auto[0]	auto[1]	61	1		T93	2		T193	5		T194	2
all_values[4]	auto[0]	auto[1]	auto[0]	12	1		T194	1		T260	2		T269	2
all_values[4]	auto[0]	auto[1]	auto[1]	67	1		T91	3		T92	2		T194	1
all_values[4]	auto[1]	auto[0]	auto[1]	68	1		T92	1		T93	1		T193	2
all_values[4]	auto[1]	auto[1]	auto[1]	45	1		T91	3		T92	1		T194	2
all_values[5]	auto[0]	auto[0]	auto[0]	51	1		T91	2		T92	1		T193	1
all_values[5]	auto[0]	auto[0]	auto[1]	50	1		T92	2		T93	2		T193	1
all_values[5]	auto[0]	auto[1]	auto[0]	16	1		T92	1		T195	1		T261	1
all_values[5]	auto[0]	auto[1]	auto[1]	61	1		T91	1		T92	2		T193	3
all_values[5]	auto[1]	auto[0]	auto[1]	55	1		T92	1		T93	2		T193	1
all_values[5]	auto[1]	auto[1]	auto[1]	51	1		T91	4		T193	1		T195	2
all_values[6]	auto[0]	auto[0]	auto[0]	50	1		T92	1		T93	1		T195	3
all_values[6]	auto[0]	auto[0]	auto[1]	41	1		T92	1		T193	3		T261	1
all_values[6]	auto[0]	auto[1]	auto[0]	12	1		T195	1		T260	1		T269	2
all_values[6]	auto[0]	auto[1]	auto[1]	67	1		T91	2		T92	2		T93	2
all_values[6]	auto[1]	auto[0]	auto[1]	62	1		T91	2		T93	1		T193	1
all_values[6]	auto[1]	auto[1]	auto[1]	52	1		T91	3		T92	3		T194	1
all_values[7]	auto[0]	auto[0]	auto[0]	40	1		T194	3		T261	2		T263	2
all_values[7]	auto[0]	auto[0]	auto[1]	53	1		T91	4		T92	1		T193	1
all_values[7]	auto[0]	auto[1]	auto[0]	13	1		T194	4		T195	1		T261	1
all_values[7]	auto[0]	auto[1]	auto[1]	57	1		T92	4		T93	1		T193	3
all_values[7]	auto[1]	auto[0]	auto[1]	71	1		T91	2		T92	1		T93	2
all_values[7]	auto[1]	auto[1]	auto[1]	50	1		T91	1		T92	1		T93	1
all_values[8]	auto[0]	auto[0]	auto[0]	39	1		T92	1		T193	1		T264	1
all_values[8]	auto[0]	auto[0]	auto[1]	64	1		T92	1		T193	2		T195	1
all_values[8]	auto[0]	auto[1]	auto[0]	17	1		T92	1		T193	1		T194	2
all_values[8]	auto[0]	auto[1]	auto[1]	64	1		T91	3		T92	2		T93	3
all_values[8]	auto[1]	auto[0]	auto[1]	60	1		T91	3		T93	1		T193	2
all_values[8]	auto[1]	auto[1]	auto[1]	40	1		T91	1		T92	2		T194	2
all_values[9]	auto[0]	auto[0]	auto[0]	23	1		T91	2		T93	2		T193	1
all_values[9]	auto[0]	auto[0]	auto[1]	58	1		T92	3		T93	1		T194	2
all_values[9]	auto[0]	auto[1]	auto[0]	15	1		T193	2		T261	1		T260	1
all_values[9]	auto[0]	auto[1]	auto[1]	56	1		T91	2		T92	2		T193	2
all_values[9]	auto[1]	auto[0]	auto[1]	73	1		T91	2		T92	1		T93	1
all_values[9]	auto[1]	auto[1]	auto[1]	59	1		T91	1		T92	1		T193	2
all_values[10]	auto[0]	auto[0]	auto[0]	33	1		T194	1		T263	1		T264	4
all_values[10]	auto[0]	auto[0]	auto[1]	66	1		T91	4		T92	2		T93	1
all_values[10]	auto[0]	auto[1]	auto[0]	14	1		T263	2		T262	1		T265	2
all_values[10]	auto[0]	auto[1]	auto[1]	54	1		T92	2		T93	2		T194	2
all_values[10]	auto[1]	auto[0]	auto[1]	64	1		T91	1		T92	1		T93	1
all_values[10]	auto[1]	auto[1]	auto[1]	53	1		T91	2		T92	2		T193	1
all_values[11]	auto[0]	auto[0]	auto[0]	33	1		T93	1		T272	2		T273	1
all_values[11]	auto[0]	auto[0]	auto[1]	57	1		T91	3		T193	4		T194	1
all_values[11]	auto[0]	auto[1]	auto[0]	29	1		T93	3		T260	1		T273	1
all_values[11]	auto[0]	auto[1]	auto[1]	55	1		T91	3		T92	3		T194	2
all_values[11]	auto[1]	auto[0]	auto[1]	67	1		T91	1		T92	1		T193	2
all_values[11]	auto[1]	auto[1]	auto[1]	43	1		T92	3		T193	1		T194	1
all_values[12]	auto[0]	auto[0]	auto[0]	37	1		T193	1		T194	1		T261	1
all_values[12]	auto[0]	auto[0]	auto[1]	69	1		T91	3		T93	3		T193	1
all_values[12]	auto[0]	auto[1]	auto[0]	12	1		T265	2		T266	1		T267	2
all_values[12]	auto[0]	auto[1]	auto[1]	49	1		T92	3		T193	1		T195	1
all_values[12]	auto[1]	auto[0]	auto[1]	72	1		T91	4		T93	1		T193	3
all_values[12]	auto[1]	auto[1]	auto[1]	45	1		T92	4		T193	1		T194	1
all_values[13]	auto[0]	auto[0]	auto[0]	30	1		T92	2		T93	1		T195	4
all_values[13]	auto[0]	auto[0]	auto[1]	52	1		T91	1		T92	1		T194	2
all_values[13]	auto[0]	auto[1]	auto[0]	19	1		T92	2		T194	1		T260	2
all_values[13]	auto[0]	auto[1]	auto[1]	68	1		T91	3		T93	2		T193	2
all_values[13]	auto[1]	auto[0]	auto[1]	64	1		T91	2		T93	1		T193	3
all_values[13]	auto[1]	auto[1]	auto[1]	51	1		T91	1		T92	2		T193	2
all_values[14]	auto[0]	auto[0]	auto[0]	27	1		T194	1		T261	1		T264	1
all_values[14]	auto[0]	auto[0]	auto[1]	61	1		T91	4		T92	2		T193	2
all_values[14]	auto[0]	auto[1]	auto[0]	11	1		T261	1		T264	1		T274	1
all_values[14]	auto[0]	auto[1]	auto[1]	58	1		T92	1		T93	2		T194	2
all_values[14]	auto[1]	auto[0]	auto[1]	68	1		T91	2		T92	2		T93	1
all_values[14]	auto[1]	auto[1]	auto[1]	59	1		T91	1		T92	2		T93	1
all_values[15]	auto[0]	auto[0]	auto[0]	29	1		T93	1		T263	2		T262	1
all_values[15]	auto[0]	auto[0]	auto[1]	60	1		T91	1		T93	2		T193	1
all_values[15]	auto[0]	auto[1]	auto[0]	10	1		T195	2		T269	2		T275	1
all_values[15]	auto[0]	auto[1]	auto[1]	57	1		T91	2		T92	5		T193	4
all_values[15]	auto[1]	auto[0]	auto[1]	60	1		T91	2		T193	2		T194	1
all_values[15]	auto[1]	auto[1]	auto[1]	68	1		T91	2		T92	2		T93	1
all_values[16]	auto[0]	auto[0]	auto[0]	38	1		T91	1		T93	1		T261	2
all_values[16]	auto[0]	auto[0]	auto[1]	68	1		T91	1		T92	2		T93	1
all_values[16]	auto[0]	auto[1]	auto[0]	18	1		T93	1		T195	1		T263	1
all_values[16]	auto[0]	auto[1]	auto[1]	59	1		T91	2		T92	1		T193	2
all_values[16]	auto[1]	auto[0]	auto[1]	63	1		T91	1		T92	1		T93	1
all_values[16]	auto[1]	auto[1]	auto[1]	38	1		T91	2		T92	3		T193	1
all_values[17]	auto[0]	auto[0]	auto[0]	41	1		T91	3		T92	1		T93	1
all_values[17]	auto[0]	auto[0]	auto[1]	40	1		T91	1		T93	2		T194	1
all_values[17]	auto[0]	auto[1]	auto[0]	20	1		T91	1		T92	1		T263	1
all_values[17]	auto[0]	auto[1]	auto[1]	74	1		T91	1		T92	3		T193	4
all_values[17]	auto[1]	auto[0]	auto[1]	58	1		T91	1		T93	1		T193	1
all_values[17]	auto[1]	auto[1]	auto[1]	51	1		T92	2		T193	2		T194	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal