Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.41 97.48 92.28 97.86 68.75 95.77 98.17 96.58


Total test records in report: 2137
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T273 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3768775298 Jun 07 08:32:27 PM PDT 24 Jun 07 08:32:34 PM PDT 24 38566090 ps
T210 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2469705568 Jun 07 08:32:19 PM PDT 24 Jun 07 08:32:32 PM PDT 24 898197313 ps
T241 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.249304854 Jun 07 08:32:25 PM PDT 24 Jun 07 08:32:46 PM PDT 24 1992158118 ps
T226 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.983176787 Jun 07 08:32:28 PM PDT 24 Jun 07 08:32:37 PM PDT 24 148152160 ps
T242 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3339937070 Jun 07 08:32:29 PM PDT 24 Jun 07 08:32:39 PM PDT 24 204919800 ps
T227 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.753775294 Jun 07 08:32:21 PM PDT 24 Jun 07 08:32:32 PM PDT 24 525938355 ps
T269 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.796361132 Jun 07 08:32:30 PM PDT 24 Jun 07 08:32:41 PM PDT 24 69941563 ps
T2035 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.301428258 Jun 07 08:32:35 PM PDT 24 Jun 07 08:32:51 PM PDT 24 41962738 ps
T266 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.270804277 Jun 07 08:32:31 PM PDT 24 Jun 07 08:32:43 PM PDT 24 68027263 ps
T221 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3939851108 Jun 07 08:32:31 PM PDT 24 Jun 07 08:32:43 PM PDT 24 88916314 ps
T247 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1202692136 Jun 07 08:32:30 PM PDT 24 Jun 07 08:32:39 PM PDT 24 82339007 ps
T2036 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1792539275 Jun 07 08:32:16 PM PDT 24 Jun 07 08:32:25 PM PDT 24 30701526 ps
T2037 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3253231644 Jun 07 08:32:27 PM PDT 24 Jun 07 08:32:36 PM PDT 24 59797127 ps
T2038 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.14986043 Jun 07 08:32:26 PM PDT 24 Jun 07 08:32:36 PM PDT 24 312593716 ps
T2039 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.4105848679 Jun 07 08:32:22 PM PDT 24 Jun 07 08:32:31 PM PDT 24 95418875 ps
T280 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1684300133 Jun 07 08:32:30 PM PDT 24 Jun 07 08:32:45 PM PDT 24 864485125 ps
T2040 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.205746535 Jun 07 08:32:27 PM PDT 24 Jun 07 08:32:38 PM PDT 24 94383066 ps
T2041 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.86365004 Jun 07 08:32:23 PM PDT 24 Jun 07 08:32:32 PM PDT 24 95445794 ps
T217 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.4154117196 Jun 07 08:32:28 PM PDT 24 Jun 07 08:32:39 PM PDT 24 291675350 ps
T243 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1758657915 Jun 07 08:32:27 PM PDT 24 Jun 07 08:32:39 PM PDT 24 915800047 ps
T275 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1986598835 Jun 07 08:32:26 PM PDT 24 Jun 07 08:32:34 PM PDT 24 53035635 ps
T2042 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.678954235 Jun 07 08:32:25 PM PDT 24 Jun 07 08:32:33 PM PDT 24 79128903 ps
T2043 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3836944711 Jun 07 08:32:34 PM PDT 24 Jun 07 08:32:46 PM PDT 24 159958449 ps
T268 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1782841498 Jun 07 08:32:32 PM PDT 24 Jun 07 08:32:43 PM PDT 24 76574176 ps
T2044 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1800143943 Jun 07 08:32:39 PM PDT 24 Jun 07 08:32:50 PM PDT 24 50306924 ps
T220 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3235269590 Jun 07 08:32:32 PM PDT 24 Jun 07 08:32:44 PM PDT 24 50843897 ps
T2045 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2971269268 Jun 07 08:32:23 PM PDT 24 Jun 07 08:32:31 PM PDT 24 74402575 ps
T2046 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2287279826 Jun 07 08:32:20 PM PDT 24 Jun 07 08:32:28 PM PDT 24 72959461 ps
T2047 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1247314182 Jun 07 08:32:32 PM PDT 24 Jun 07 08:32:43 PM PDT 24 39178638 ps
T244 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1032713768 Jun 07 08:32:27 PM PDT 24 Jun 07 08:32:35 PM PDT 24 66674445 ps
T2048 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1052191281 Jun 07 08:32:29 PM PDT 24 Jun 07 08:32:38 PM PDT 24 120206644 ps
T2049 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1528512364 Jun 07 08:32:20 PM PDT 24 Jun 07 08:32:32 PM PDT 24 185922183 ps
T279 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3766267149 Jun 07 08:32:28 PM PDT 24 Jun 07 08:32:39 PM PDT 24 347756713 ps
T282 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2108240821 Jun 07 08:32:30 PM PDT 24 Jun 07 08:32:44 PM PDT 24 1035200633 ps
T2050 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3443157064 Jun 07 08:32:28 PM PDT 24 Jun 07 08:32:36 PM PDT 24 65227924 ps
T2051 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1648006277 Jun 07 08:32:28 PM PDT 24 Jun 07 08:32:37 PM PDT 24 40406008 ps
T2052 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.884413968 Jun 07 08:32:34 PM PDT 24 Jun 07 08:32:47 PM PDT 24 117215097 ps
T2053 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.12004621 Jun 07 08:32:22 PM PDT 24 Jun 07 08:32:30 PM PDT 24 101626472 ps
T276 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3638486920 Jun 07 08:32:28 PM PDT 24 Jun 07 08:32:48 PM PDT 24 2147326169 ps
T267 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.4003219380 Jun 07 08:32:29 PM PDT 24 Jun 07 08:32:39 PM PDT 24 58072694 ps
T2054 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1675503493 Jun 07 08:32:30 PM PDT 24 Jun 07 08:32:41 PM PDT 24 156968820 ps
T245 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2419060077 Jun 07 08:32:26 PM PDT 24 Jun 07 08:32:34 PM PDT 24 49890603 ps
T246 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1811660527 Jun 07 08:32:31 PM PDT 24 Jun 07 08:32:42 PM PDT 24 81828363 ps
T274 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.642293533 Jun 07 08:32:32 PM PDT 24 Jun 07 08:32:44 PM PDT 24 46431777 ps
T2055 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3586413614 Jun 07 08:32:30 PM PDT 24 Jun 07 08:32:51 PM PDT 24 40623916 ps
T2056 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.327962699 Jun 07 08:32:39 PM PDT 24 Jun 07 08:32:51 PM PDT 24 106817230 ps
T2057 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.217720687 Jun 07 08:32:37 PM PDT 24 Jun 07 08:32:49 PM PDT 24 39913584 ps
T258 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3012693624 Jun 07 08:32:30 PM PDT 24 Jun 07 08:32:41 PM PDT 24 197857206 ps
T249 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.24974190 Jun 07 08:32:28 PM PDT 24 Jun 07 08:32:37 PM PDT 24 100832681 ps
T2058 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1058187546 Jun 07 08:32:28 PM PDT 24 Jun 07 08:32:37 PM PDT 24 70950921 ps
T2059 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2345161982 Jun 07 08:32:36 PM PDT 24 Jun 07 08:32:47 PM PDT 24 45118299 ps
T222 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3974915151 Jun 07 08:32:25 PM PDT 24 Jun 07 08:32:34 PM PDT 24 181193901 ps
T259 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2865582567 Jun 07 08:32:30 PM PDT 24 Jun 07 08:32:44 PM PDT 24 1097941338 ps
T2060 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1174529368 Jun 07 08:32:36 PM PDT 24 Jun 07 08:32:51 PM PDT 24 39725323 ps
T2061 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.4061253861 Jun 07 08:32:11 PM PDT 24 Jun 07 08:32:22 PM PDT 24 71878190 ps
T2062 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4203931326 Jun 07 08:32:25 PM PDT 24 Jun 07 08:32:33 PM PDT 24 133731940 ps
T2063 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3675513792 Jun 07 08:32:26 PM PDT 24 Jun 07 08:32:38 PM PDT 24 360881720 ps
T2064 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1940316898 Jun 07 08:32:31 PM PDT 24 Jun 07 08:32:41 PM PDT 24 46909715 ps
T2065 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1294804531 Jun 07 08:32:28 PM PDT 24 Jun 07 08:32:41 PM PDT 24 727480744 ps
T2066 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2574733576 Jun 07 08:32:28 PM PDT 24 Jun 07 08:32:40 PM PDT 24 262269751 ps
T2067 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2191221429 Jun 07 08:32:21 PM PDT 24 Jun 07 08:32:30 PM PDT 24 138761443 ps
T2068 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3526369459 Jun 07 08:32:37 PM PDT 24 Jun 07 08:32:48 PM PDT 24 46815133 ps
T2069 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2280601166 Jun 07 08:32:28 PM PDT 24 Jun 07 08:32:37 PM PDT 24 173526043 ps
T2070 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2667392551 Jun 07 08:32:19 PM PDT 24 Jun 07 08:32:28 PM PDT 24 99038749 ps
T248 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.4227779259 Jun 07 08:32:26 PM PDT 24 Jun 07 08:32:35 PM PDT 24 75719979 ps
T2071 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2026512184 Jun 07 08:32:28 PM PDT 24 Jun 07 08:32:38 PM PDT 24 306849393 ps
T2072 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2827143635 Jun 07 08:32:30 PM PDT 24 Jun 07 08:32:42 PM PDT 24 99816078 ps
T2073 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.634925759 Jun 07 08:32:28 PM PDT 24 Jun 07 08:32:37 PM PDT 24 123265541 ps
T2074 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.683736624 Jun 07 08:32:29 PM PDT 24 Jun 07 08:32:41 PM PDT 24 267555034 ps
T2075 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1139279759 Jun 07 08:32:28 PM PDT 24 Jun 07 08:32:38 PM PDT 24 83906866 ps
T2076 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4236361382 Jun 07 08:32:30 PM PDT 24 Jun 07 08:32:40 PM PDT 24 36675933 ps
T2077 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.770635960 Jun 07 08:32:30 PM PDT 24 Jun 07 08:32:39 PM PDT 24 39365626 ps
T2078 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3973343783 Jun 07 08:32:28 PM PDT 24 Jun 07 08:32:37 PM PDT 24 158700844 ps
T2079 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2232705835 Jun 07 08:32:20 PM PDT 24 Jun 07 08:32:31 PM PDT 24 316669095 ps
T2080 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1053221902 Jun 07 08:32:22 PM PDT 24 Jun 07 08:32:30 PM PDT 24 81958409 ps
T250 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2102959755 Jun 07 08:32:33 PM PDT 24 Jun 07 08:32:45 PM PDT 24 47764761 ps
T2081 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2208140877 Jun 07 08:32:32 PM PDT 24 Jun 07 08:32:44 PM PDT 24 114694253 ps
T2082 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1497652986 Jun 07 08:32:30 PM PDT 24 Jun 07 08:32:39 PM PDT 24 143123970 ps
T281 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2220029892 Jun 07 08:32:33 PM PDT 24 Jun 07 08:32:46 PM PDT 24 313173136 ps
T2083 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1644442681 Jun 07 08:32:29 PM PDT 24 Jun 07 08:32:39 PM PDT 24 154597334 ps
T2084 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1081094809 Jun 07 08:32:21 PM PDT 24 Jun 07 08:32:30 PM PDT 24 92465662 ps
T2085 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2303012234 Jun 07 08:32:32 PM PDT 24 Jun 07 08:32:43 PM PDT 24 55966041 ps
T2086 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3873742496 Jun 07 08:32:34 PM PDT 24 Jun 07 08:32:47 PM PDT 24 163099820 ps
T2087 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2466564033 Jun 07 08:32:32 PM PDT 24 Jun 07 08:32:44 PM PDT 24 94388460 ps
T2088 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.4044682904 Jun 07 08:32:36 PM PDT 24 Jun 07 08:32:47 PM PDT 24 38964098 ps
T2089 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1816475938 Jun 07 08:32:32 PM PDT 24 Jun 07 08:32:43 PM PDT 24 40461111 ps
T2090 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3065830931 Jun 07 08:32:36 PM PDT 24 Jun 07 08:32:47 PM PDT 24 53519551 ps
T2091 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1861889476 Jun 07 08:32:25 PM PDT 24 Jun 07 08:32:33 PM PDT 24 87886095 ps
T2092 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.575646444 Jun 07 08:32:29 PM PDT 24 Jun 07 08:32:39 PM PDT 24 292074654 ps
T2093 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.486533276 Jun 07 08:32:24 PM PDT 24 Jun 07 08:32:32 PM PDT 24 138676436 ps
T2094 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1449997741 Jun 07 08:32:34 PM PDT 24 Jun 07 08:32:50 PM PDT 24 53768906 ps
T2095 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1935480990 Jun 07 08:32:30 PM PDT 24 Jun 07 08:32:40 PM PDT 24 104401213 ps
T278 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.789489165 Jun 07 08:32:28 PM PDT 24 Jun 07 08:32:49 PM PDT 24 619996133 ps
T2096 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3222095910 Jun 07 08:32:23 PM PDT 24 Jun 07 08:32:31 PM PDT 24 49677802 ps
T2097 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2782642494 Jun 07 08:32:23 PM PDT 24 Jun 07 08:32:32 PM PDT 24 173118268 ps
T2098 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3794541410 Jun 07 08:32:27 PM PDT 24 Jun 07 08:32:36 PM PDT 24 184642878 ps
T2099 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.187528656 Jun 07 08:32:20 PM PDT 24 Jun 07 08:32:29 PM PDT 24 59697981 ps
T2100 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.775085628 Jun 07 08:32:32 PM PDT 24 Jun 07 08:32:45 PM PDT 24 73485053 ps
T277 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2861284147 Jun 07 08:32:18 PM PDT 24 Jun 07 08:32:33 PM PDT 24 2305484430 ps
T2101 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2792699126 Jun 07 08:32:19 PM PDT 24 Jun 07 08:32:29 PM PDT 24 166282372 ps
T2102 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2196306074 Jun 07 08:32:28 PM PDT 24 Jun 07 08:32:37 PM PDT 24 220873715 ps
T2103 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2741595802 Jun 07 08:32:29 PM PDT 24 Jun 07 08:32:39 PM PDT 24 150985347 ps
T2104 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.613653234 Jun 07 08:32:26 PM PDT 24 Jun 07 08:32:35 PM PDT 24 99316141 ps
T2105 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2438050774 Jun 07 08:33:00 PM PDT 24 Jun 07 08:33:04 PM PDT 24 42550830 ps
T2106 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2740594684 Jun 07 08:32:26 PM PDT 24 Jun 07 08:32:37 PM PDT 24 730586276 ps
T2107 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.194861898 Jun 07 08:32:35 PM PDT 24 Jun 07 08:32:49 PM PDT 24 486923291 ps
T2108 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3399698761 Jun 07 08:33:02 PM PDT 24 Jun 07 08:33:06 PM PDT 24 48313411 ps
T283 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1521048170 Jun 07 08:32:29 PM PDT 24 Jun 07 08:32:42 PM PDT 24 843504634 ps
T2109 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2841838370 Jun 07 08:32:24 PM PDT 24 Jun 07 08:32:33 PM PDT 24 73459629 ps
T2110 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1818735108 Jun 07 08:32:28 PM PDT 24 Jun 07 08:32:40 PM PDT 24 306764976 ps
T2111 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2562869046 Jun 07 08:32:30 PM PDT 24 Jun 07 08:32:39 PM PDT 24 56552042 ps
T2112 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.4045433583 Jun 07 08:32:33 PM PDT 24 Jun 07 08:32:44 PM PDT 24 64880229 ps
T2113 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1219454184 Jun 07 08:32:17 PM PDT 24 Jun 07 08:32:26 PM PDT 24 93103563 ps
T2114 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3910900460 Jun 07 08:32:21 PM PDT 24 Jun 07 08:32:29 PM PDT 24 81885574 ps
T2115 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2745255270 Jun 07 08:32:26 PM PDT 24 Jun 07 08:32:35 PM PDT 24 153405939 ps
T2116 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.34249268 Jun 07 08:32:17 PM PDT 24 Jun 07 08:32:29 PM PDT 24 484677663 ps
T2117 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2705283318 Jun 07 08:32:29 PM PDT 24 Jun 07 08:32:39 PM PDT 24 58445646 ps
T2118 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.4161304411 Jun 07 08:32:21 PM PDT 24 Jun 07 08:32:33 PM PDT 24 373651263 ps
T2119 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2385036888 Jun 07 08:32:26 PM PDT 24 Jun 07 08:32:35 PM PDT 24 102234156 ps
T2120 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2789335812 Jun 07 08:32:28 PM PDT 24 Jun 07 08:32:37 PM PDT 24 147681317 ps
T2121 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3452106570 Jun 07 08:32:31 PM PDT 24 Jun 07 08:32:44 PM PDT 24 115116594 ps
T2122 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.583806233 Jun 07 08:32:25 PM PDT 24 Jun 07 08:32:35 PM PDT 24 410869616 ps
T2123 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1185626719 Jun 07 08:32:15 PM PDT 24 Jun 07 08:32:28 PM PDT 24 1142989666 ps
T2124 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1249297186 Jun 07 08:32:37 PM PDT 24 Jun 07 08:32:48 PM PDT 24 63310735 ps
T2125 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1531973997 Jun 07 08:32:35 PM PDT 24 Jun 07 08:32:47 PM PDT 24 43292899 ps
T2126 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1322076357 Jun 07 08:32:34 PM PDT 24 Jun 07 08:32:45 PM PDT 24 38854415 ps
T2127 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3211480542 Jun 07 08:32:17 PM PDT 24 Jun 07 08:32:35 PM PDT 24 918849426 ps
T2128 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1603357094 Jun 07 08:32:25 PM PDT 24 Jun 07 08:32:40 PM PDT 24 72739071 ps
T2129 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2786190896 Jun 07 08:32:30 PM PDT 24 Jun 07 08:32:40 PM PDT 24 32811074 ps
T2130 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.777725309 Jun 07 08:32:21 PM PDT 24 Jun 07 08:32:31 PM PDT 24 112148696 ps
T2131 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.258730736 Jun 07 08:32:29 PM PDT 24 Jun 07 08:32:39 PM PDT 24 57112056 ps
T2132 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1199251045 Jun 07 08:32:24 PM PDT 24 Jun 07 08:32:33 PM PDT 24 186506458 ps
T2133 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3253705847 Jun 07 08:32:30 PM PDT 24 Jun 07 08:32:40 PM PDT 24 84113550 ps
T2134 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3084027038 Jun 07 08:32:37 PM PDT 24 Jun 07 08:32:48 PM PDT 24 39149741 ps
T2135 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3583831602 Jun 07 08:32:30 PM PDT 24 Jun 07 08:32:40 PM PDT 24 78999693 ps
T2136 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2971700376 Jun 07 08:32:31 PM PDT 24 Jun 07 08:32:43 PM PDT 24 126627653 ps
T2137 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1520756328 Jun 07 08:32:30 PM PDT 24 Jun 07 08:32:40 PM PDT 24 66156469 ps

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.2628367586
Short name T7
Test name
Test status
Simulation time 13574245369 ps
CPU time 17.33 seconds
Started Jun 07 08:46:57 PM PDT 24
Finished Jun 07 08:47:18 PM PDT 24
Peak memory 205796 kb
Host smart-f6097a09-f585-425b-b1cb-c8e7aa77274d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2628367586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.2628367586
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.920099521
Short name T261
Test name
Test status
Simulation time 57586463 ps
CPU time 0.69 seconds
Started Jun 07 08:32:31 PM PDT 24
Finished Jun 07 08:32:41 PM PDT 24
Peak memory 204656 kb
Host smart-dc3ff718-3bc0-49e0-abcb-52a043f80010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=920099521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.920099521
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/default/18.usbdev_smoke.4131865840
Short name T19
Test name
Test status
Simulation time 10092084423 ps
CPU time 14.05 seconds
Started Jun 07 08:44:26 PM PDT 24
Finished Jun 07 08:44:43 PM PDT 24
Peak memory 205848 kb
Host smart-a156c3ec-3996-4e78-a5f1-fcb2672703f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41318
65840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.4131865840
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.492446268
Short name T32
Test name
Test status
Simulation time 30747330422 ps
CPU time 56.93 seconds
Started Jun 07 08:41:53 PM PDT 24
Finished Jun 07 08:42:52 PM PDT 24
Peak memory 205788 kb
Host smart-23b842a7-8262-469f-8635-e59a87892b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49244
6268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.492446268
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3529401746
Short name T192
Test name
Test status
Simulation time 719482187 ps
CPU time 5.18 seconds
Started Jun 07 08:32:26 PM PDT 24
Finished Jun 07 08:32:38 PM PDT 24
Peak memory 204948 kb
Host smart-2f2e3e4f-a27c-46ac-b03f-1a84f8ccf826
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3529401746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3529401746
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.2687445286
Short name T35
Test name
Test status
Simulation time 10067183788 ps
CPU time 13.66 seconds
Started Jun 07 08:44:23 PM PDT 24
Finished Jun 07 08:44:39 PM PDT 24
Peak memory 205896 kb
Host smart-a666f364-63b4-4f77-952e-261db036f101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26874
45286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.2687445286
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.2007652996
Short name T16
Test name
Test status
Simulation time 23293714508 ps
CPU time 24.79 seconds
Started Jun 07 08:42:49 PM PDT 24
Finished Jun 07 08:43:17 PM PDT 24
Peak memory 205804 kb
Host smart-e89a0aed-8cb9-4f78-a666-0d7ba2dd22f3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2007652996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.2007652996
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3854313386
Short name T223
Test name
Test status
Simulation time 164349893 ps
CPU time 1.76 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:38 PM PDT 24
Peak memory 217176 kb
Host smart-985e4976-e9c8-4ed6-8064-9992116f3a2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854313386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.3854313386
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1902867471
Short name T92
Test name
Test status
Simulation time 91170934 ps
CPU time 0.72 seconds
Started Jun 07 08:32:27 PM PDT 24
Finished Jun 07 08:32:36 PM PDT 24
Peak memory 204688 kb
Host smart-7bc1b2c4-cf4e-4620-9aaa-dd40c3e0fd4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1902867471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1902867471
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.4242237589
Short name T72
Test name
Test status
Simulation time 10153468621 ps
CPU time 13.59 seconds
Started Jun 07 08:44:44 PM PDT 24
Finished Jun 07 08:45:00 PM PDT 24
Peak memory 205880 kb
Host smart-ac584a9b-5991-48bb-adb4-7c654632a4d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42422
37589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.4242237589
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.1813619334
Short name T44
Test name
Test status
Simulation time 10111611861 ps
CPU time 12.8 seconds
Started Jun 07 08:46:52 PM PDT 24
Finished Jun 07 08:47:09 PM PDT 24
Peak memory 205800 kb
Host smart-90357a86-1968-459a-9f1d-b13b2012e132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18136
19334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.1813619334
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.2951107536
Short name T70
Test name
Test status
Simulation time 10074755918 ps
CPU time 15.37 seconds
Started Jun 07 08:47:53 PM PDT 24
Finished Jun 07 08:48:15 PM PDT 24
Peak memory 205868 kb
Host smart-b6f92850-a18b-4512-9745-cceb474b6810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29511
07536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.2951107536
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.4007443730
Short name T113
Test name
Test status
Simulation time 10126893513 ps
CPU time 13.07 seconds
Started Jun 07 08:44:29 PM PDT 24
Finished Jun 07 08:44:46 PM PDT 24
Peak memory 205852 kb
Host smart-0d9ff0b2-ecc2-4aab-a661-d4df6676d9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40074
43730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.4007443730
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.38358534
Short name T26
Test name
Test status
Simulation time 10066646153 ps
CPU time 13.1 seconds
Started Jun 07 08:43:12 PM PDT 24
Finished Jun 07 08:43:27 PM PDT 24
Peak memory 205836 kb
Host smart-e5a4cad3-0b5e-47e2-8d7b-cec20c95c7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38358
534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.38358534
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.1447065851
Short name T54
Test name
Test status
Simulation time 10516095590 ps
CPU time 15.02 seconds
Started Jun 07 08:43:51 PM PDT 24
Finished Jun 07 08:44:08 PM PDT 24
Peak memory 205704 kb
Host smart-c6c21526-1cc6-4c13-a084-0b85115c1594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14470
65851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.1447065851
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.3545785673
Short name T56
Test name
Test status
Simulation time 10056371093 ps
CPU time 12.95 seconds
Started Jun 07 08:46:41 PM PDT 24
Finished Jun 07 08:46:59 PM PDT 24
Peak memory 205820 kb
Host smart-8bb628fe-2ead-49d7-a73f-860937857ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35457
85673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.3545785673
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.3425469700
Short name T197
Test name
Test status
Simulation time 479510210 ps
CPU time 1.3 seconds
Started Jun 07 08:40:28 PM PDT 24
Finished Jun 07 08:40:31 PM PDT 24
Peak memory 222996 kb
Host smart-9e1eacaf-edf8-4046-85e8-d8264cb01f46
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3425469700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3425469700
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.2124415710
Short name T181
Test name
Test status
Simulation time 10211688265 ps
CPU time 13.43 seconds
Started Jun 07 08:40:36 PM PDT 24
Finished Jun 07 08:40:51 PM PDT 24
Peak memory 205880 kb
Host smart-61920299-ca25-4c48-bb4c-1568e9300910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21244
15710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2124415710
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.430035441
Short name T262
Test name
Test status
Simulation time 48268310 ps
CPU time 0.65 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:41 PM PDT 24
Peak memory 204628 kb
Host smart-4dcad6f4-3b2a-4689-8cf6-207b93235b04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=430035441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.430035441
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.988384795
Short name T238
Test name
Test status
Simulation time 92888284 ps
CPU time 0.85 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:41 PM PDT 24
Peak memory 204728 kb
Host smart-b62d369e-15ed-4f83-9fc2-c34dd2cf390b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=988384795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.988384795
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.4003219380
Short name T267
Test name
Test status
Simulation time 58072694 ps
CPU time 0.66 seconds
Started Jun 07 08:32:29 PM PDT 24
Finished Jun 07 08:32:39 PM PDT 24
Peak memory 204520 kb
Host smart-bc7bdb5a-683c-4c9e-a7af-b105eba57884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4003219380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.4003219380
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.1676905975
Short name T62
Test name
Test status
Simulation time 10071379362 ps
CPU time 14.46 seconds
Started Jun 07 08:45:00 PM PDT 24
Finished Jun 07 08:45:17 PM PDT 24
Peak memory 205912 kb
Host smart-03a7b70a-2739-44c4-b940-9bbe26ad2342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16769
05975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.1676905975
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3596278932
Short name T218
Test name
Test status
Simulation time 118051372 ps
CPU time 2.88 seconds
Started Jun 07 08:32:24 PM PDT 24
Finished Jun 07 08:32:34 PM PDT 24
Peak memory 220756 kb
Host smart-1491916c-09fb-489e-b383-3358635914a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3596278932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3596278932
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.789489165
Short name T278
Test name
Test status
Simulation time 619996133 ps
CPU time 4.61 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:49 PM PDT 24
Peak memory 204940 kb
Host smart-d6c1843c-172f-47eb-b67a-1181cad77d1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=789489165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.789489165
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.2362896070
Short name T160
Test name
Test status
Simulation time 18617799512 ps
CPU time 229.35 seconds
Started Jun 07 08:40:46 PM PDT 24
Finished Jun 07 08:44:36 PM PDT 24
Peak memory 205864 kb
Host smart-ca636ea6-bea7-4cdf-99b2-135a77519b71
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2362896070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2362896070
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1986598835
Short name T275
Test name
Test status
Simulation time 53035635 ps
CPU time 0.68 seconds
Started Jun 07 08:32:26 PM PDT 24
Finished Jun 07 08:32:34 PM PDT 24
Peak memory 204648 kb
Host smart-5d663389-74d9-4bbb-90d8-57c7bca269dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1986598835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1986598835
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/default/1.usbdev_enable.3000051575
Short name T270
Test name
Test status
Simulation time 10054918383 ps
CPU time 12.68 seconds
Started Jun 07 08:40:33 PM PDT 24
Finished Jun 07 08:40:47 PM PDT 24
Peak memory 205752 kb
Host smart-7d878374-bb46-4575-b3f2-3b1de58ccfe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30000
51575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3000051575
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3766267149
Short name T279
Test name
Test status
Simulation time 347756713 ps
CPU time 2.42 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:39 PM PDT 24
Peak memory 204900 kb
Host smart-cc0967de-d581-4507-bb85-0aa37016e1a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3766267149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3766267149
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.2676731211
Short name T162
Test name
Test status
Simulation time 16111672722 ps
CPU time 46.32 seconds
Started Jun 07 08:41:24 PM PDT 24
Finished Jun 07 08:42:14 PM PDT 24
Peak memory 205816 kb
Host smart-73b74a3f-74d8-47c9-91ea-45c15ff0dd69
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676731211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_
traffic.2676731211
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.1883562918
Short name T206
Test name
Test status
Simulation time 5115896550 ps
CPU time 31.03 seconds
Started Jun 07 08:40:01 PM PDT 24
Finished Jun 07 08:40:33 PM PDT 24
Peak memory 205772 kb
Host smart-0b92902b-e8e1-4a8d-9ead-89ddcf761e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18835
62918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.1883562918
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2861284147
Short name T277
Test name
Test status
Simulation time 2305484430 ps
CPU time 6.74 seconds
Started Jun 07 08:32:18 PM PDT 24
Finished Jun 07 08:32:33 PM PDT 24
Peak memory 205100 kb
Host smart-e9f2e722-c6bd-4122-802b-4cf4ffeea4bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2861284147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2861284147
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2469705568
Short name T210
Test name
Test status
Simulation time 898197313 ps
CPU time 4.95 seconds
Started Jun 07 08:32:19 PM PDT 24
Finished Jun 07 08:32:32 PM PDT 24
Peak memory 204948 kb
Host smart-78f51e75-b543-4636-b2ac-4f9fc00d762a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2469705568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.2469705568
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.2989897482
Short name T355
Test name
Test status
Simulation time 10813831707 ps
CPU time 15.77 seconds
Started Jun 07 08:44:35 PM PDT 24
Finished Jun 07 08:44:54 PM PDT 24
Peak memory 205800 kb
Host smart-a065d44d-b971-4902-b186-568a3ec76133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29898
97482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.2989897482
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.256593716
Short name T158
Test name
Test status
Simulation time 31282531353 ps
CPU time 53.87 seconds
Started Jun 07 08:45:29 PM PDT 24
Finished Jun 07 08:46:27 PM PDT 24
Peak memory 205760 kb
Host smart-86220267-9a8e-4363-a54b-1c41ec0f700d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25659
3716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.256593716
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.3636956480
Short name T175
Test name
Test status
Simulation time 29354378005 ps
CPU time 555.34 seconds
Started Jun 07 08:42:14 PM PDT 24
Finished Jun 07 08:51:31 PM PDT 24
Peak memory 205908 kb
Host smart-eccb2133-9b20-43b2-89df-223181a4a852
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3636956480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.3636956480
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.3151674391
Short name T214
Test name
Test status
Simulation time 10073548138 ps
CPU time 12.27 seconds
Started Jun 07 08:40:28 PM PDT 24
Finished Jun 07 08:40:42 PM PDT 24
Peak memory 205884 kb
Host smart-a0478afa-e04a-41d1-948d-3521bfc9e891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31516
74391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.3151674391
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3004186219
Short name T207
Test name
Test status
Simulation time 93866389 ps
CPU time 2.61 seconds
Started Jun 07 08:32:22 PM PDT 24
Finished Jun 07 08:32:31 PM PDT 24
Peak memory 220744 kb
Host smart-49166439-5f01-419e-9eff-0317edffca6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3004186219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3004186219
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.3901295342
Short name T63
Test name
Test status
Simulation time 10057132916 ps
CPU time 15.15 seconds
Started Jun 07 08:40:51 PM PDT 24
Finished Jun 07 08:41:08 PM PDT 24
Peak memory 205752 kb
Host smart-292d08be-2843-4d2a-92c5-3c18dbd7fb26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39012
95342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.3901295342
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.3397619418
Short name T288
Test name
Test status
Simulation time 10111292629 ps
CPU time 12.99 seconds
Started Jun 07 08:40:51 PM PDT 24
Finished Jun 07 08:41:06 PM PDT 24
Peak memory 205832 kb
Host smart-a47432b5-38f2-4579-9b9a-9ff0ee8a27dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33976
19418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.3397619418
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.1201766531
Short name T725
Test name
Test status
Simulation time 10046012663 ps
CPU time 14.74 seconds
Started Jun 07 08:40:18 PM PDT 24
Finished Jun 07 08:40:34 PM PDT 24
Peak memory 205876 kb
Host smart-70f4ec61-0876-400a-b148-424e338478ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12017
66531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.1201766531
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.4234171184
Short name T389
Test name
Test status
Simulation time 10059703687 ps
CPU time 13.49 seconds
Started Jun 07 08:40:28 PM PDT 24
Finished Jun 07 08:40:43 PM PDT 24
Peak memory 205740 kb
Host smart-58255c78-2aa9-411d-a72f-7de370701671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42341
71184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.4234171184
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.158544468
Short name T168
Test name
Test status
Simulation time 19917289697 ps
CPU time 274.74 seconds
Started Jun 07 08:40:41 PM PDT 24
Finished Jun 07 08:45:17 PM PDT 24
Peak memory 205768 kb
Host smart-2f30530b-be1c-4a0f-bc79-3fb394e1a6dd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=158544468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.158544468
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.3824718791
Short name T921
Test name
Test status
Simulation time 10081923039 ps
CPU time 13.4 seconds
Started Jun 07 08:43:13 PM PDT 24
Finished Jun 07 08:43:29 PM PDT 24
Peak memory 205784 kb
Host smart-2537c4b3-b4a4-4842-a181-69e44dab4553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38247
18791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.3824718791
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3646580963
Short name T1161
Test name
Test status
Simulation time 10079193621 ps
CPU time 13.67 seconds
Started Jun 07 08:43:16 PM PDT 24
Finished Jun 07 08:43:32 PM PDT 24
Peak memory 205844 kb
Host smart-4e815f7e-3fd0-4056-a0bf-3ea5c236b264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36465
80963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3646580963
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.3612359744
Short name T1477
Test name
Test status
Simulation time 10046272026 ps
CPU time 13.9 seconds
Started Jun 07 08:43:22 PM PDT 24
Finished Jun 07 08:43:38 PM PDT 24
Peak memory 205732 kb
Host smart-55b78132-4d2d-4074-a69c-4f5c499a5a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36123
59744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.3612359744
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.1582748950
Short name T38
Test name
Test status
Simulation time 10107230164 ps
CPU time 13.28 seconds
Started Jun 07 08:43:40 PM PDT 24
Finished Jun 07 08:43:56 PM PDT 24
Peak memory 205812 kb
Host smart-e0edf4d9-54d7-407b-b2f5-1711ca567f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15827
48950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.1582748950
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.1706392031
Short name T145
Test name
Test status
Simulation time 10050481719 ps
CPU time 13.71 seconds
Started Jun 07 08:43:41 PM PDT 24
Finished Jun 07 08:43:57 PM PDT 24
Peak memory 205856 kb
Host smart-876ceb8a-2ece-4892-8933-bd99f742ba69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17063
92031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.1706392031
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_smoke.2970805339
Short name T516
Test name
Test status
Simulation time 10097550778 ps
CPU time 14.98 seconds
Started Jun 07 08:44:05 PM PDT 24
Finished Jun 07 08:44:22 PM PDT 24
Peak memory 205824 kb
Host smart-b883f7a9-4530-45ab-9d6b-15062b1e7aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29708
05339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2970805339
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.2381640578
Short name T136
Test name
Test status
Simulation time 10052450533 ps
CPU time 13.2 seconds
Started Jun 07 08:44:38 PM PDT 24
Finished Jun 07 08:44:54 PM PDT 24
Peak memory 205700 kb
Host smart-65226ddb-502d-4d1b-b83f-6483568bc6f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23816
40578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.2381640578
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.1488752139
Short name T724
Test name
Test status
Simulation time 10061416199 ps
CPU time 13.07 seconds
Started Jun 07 08:44:42 PM PDT 24
Finished Jun 07 08:44:58 PM PDT 24
Peak memory 205824 kb
Host smart-d63ed89d-0b12-4200-95f4-231d238a7211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14887
52139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.1488752139
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.2943978321
Short name T139
Test name
Test status
Simulation time 10063254131 ps
CPU time 15.31 seconds
Started Jun 07 08:45:23 PM PDT 24
Finished Jun 07 08:45:41 PM PDT 24
Peak memory 205828 kb
Host smart-6a088247-6d98-48ca-b4ea-b3a2e0e6d024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29439
78321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.2943978321
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.3415039763
Short name T174
Test name
Test status
Simulation time 10521039259 ps
CPU time 14.38 seconds
Started Jun 07 08:46:23 PM PDT 24
Finished Jun 07 08:46:43 PM PDT 24
Peak memory 205840 kb
Host smart-ce4e032c-a614-4cc6-bdf5-0cc0de4d4f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34150
39763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.3415039763
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.2406583905
Short name T170
Test name
Test status
Simulation time 10773254742 ps
CPU time 14.62 seconds
Started Jun 07 08:47:23 PM PDT 24
Finished Jun 07 08:47:40 PM PDT 24
Peak memory 205696 kb
Host smart-c4522cc0-52a1-4557-b7c3-d5af3b62ac34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24065
83905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.2406583905
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.3284309698
Short name T57
Test name
Test status
Simulation time 10112175948 ps
CPU time 13.56 seconds
Started Jun 07 08:47:38 PM PDT 24
Finished Jun 07 08:47:57 PM PDT 24
Peak memory 205812 kb
Host smart-64766557-b2dc-43d6-b55d-ee11944f414c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32843
09698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.3284309698
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.438006243
Short name T907
Test name
Test status
Simulation time 10075622704 ps
CPU time 12.99 seconds
Started Jun 07 08:40:08 PM PDT 24
Finished Jun 07 08:40:22 PM PDT 24
Peak memory 205840 kb
Host smart-5cf7b29d-02d1-44f1-96e2-e7ef77b2e34b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43800
6243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.438006243
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.2828021913
Short name T1611
Test name
Test status
Simulation time 10099301641 ps
CPU time 13.52 seconds
Started Jun 07 08:40:38 PM PDT 24
Finished Jun 07 08:40:52 PM PDT 24
Peak memory 205720 kb
Host smart-035289d9-49cd-496c-bb09-bd990cbc7c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28280
21913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.2828021913
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.3400738411
Short name T98
Test name
Test status
Simulation time 10111160606 ps
CPU time 15.48 seconds
Started Jun 07 08:43:13 PM PDT 24
Finished Jun 07 08:43:30 PM PDT 24
Peak memory 205820 kb
Host smart-1f1135c7-5396-4868-85d2-c34b9f250710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34007
38411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.3400738411
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.1700788979
Short name T108
Test name
Test status
Simulation time 10148027462 ps
CPU time 12.81 seconds
Started Jun 07 08:43:29 PM PDT 24
Finished Jun 07 08:43:43 PM PDT 24
Peak memory 205928 kb
Host smart-bf26af18-23d5-4ebd-9724-693bbfe096df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17007
88979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1700788979
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3312517543
Short name T104
Test name
Test status
Simulation time 10099998011 ps
CPU time 16.15 seconds
Started Jun 07 08:43:32 PM PDT 24
Finished Jun 07 08:43:51 PM PDT 24
Peak memory 205860 kb
Host smart-665bafd5-8ef8-409d-9fe7-12c9c6c176dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33125
17543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3312517543
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.3031905303
Short name T212
Test name
Test status
Simulation time 10056547640 ps
CPU time 12.68 seconds
Started Jun 07 08:43:44 PM PDT 24
Finished Jun 07 08:43:58 PM PDT 24
Peak memory 205768 kb
Host smart-07c63c74-7365-49dd-ad89-8822a8d197ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30319
05303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.3031905303
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1785879246
Short name T101
Test name
Test status
Simulation time 10054121699 ps
CPU time 13.59 seconds
Started Jun 07 08:43:59 PM PDT 24
Finished Jun 07 08:44:14 PM PDT 24
Peak memory 205884 kb
Host smart-bbdbdb2f-3cfe-457f-8c84-66bef0f9513d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17858
79246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1785879246
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.2668449865
Short name T2015
Test name
Test status
Simulation time 10106145924 ps
CPU time 13.74 seconds
Started Jun 07 08:44:21 PM PDT 24
Finished Jun 07 08:44:38 PM PDT 24
Peak memory 205844 kb
Host smart-1e1b6827-8e00-4825-986c-f47ae0f5309d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26684
49865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.2668449865
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2056843787
Short name T118
Test name
Test status
Simulation time 10138957415 ps
CPU time 13.07 seconds
Started Jun 07 08:44:35 PM PDT 24
Finished Jun 07 08:44:51 PM PDT 24
Peak memory 205844 kb
Host smart-8b83160a-aabd-44ec-b13c-462ccb5aece5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20568
43787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2056843787
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2477186098
Short name T120
Test name
Test status
Simulation time 10108740013 ps
CPU time 13.34 seconds
Started Jun 07 08:46:06 PM PDT 24
Finished Jun 07 08:46:23 PM PDT 24
Peak memory 205800 kb
Host smart-08c1ae73-e46c-4b8a-a442-6a079af12832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24771
86098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2477186098
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.3560506790
Short name T88
Test name
Test status
Simulation time 10122884905 ps
CPU time 13.56 seconds
Started Jun 07 08:46:21 PM PDT 24
Finished Jun 07 08:46:37 PM PDT 24
Peak memory 205820 kb
Host smart-1039ef77-928f-47a9-b882-ad11862302b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35605
06790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3560506790
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.1500551239
Short name T112
Test name
Test status
Simulation time 10055793199 ps
CPU time 12.57 seconds
Started Jun 07 08:47:39 PM PDT 24
Finished Jun 07 08:47:58 PM PDT 24
Peak memory 205776 kb
Host smart-e1881e4e-1c62-4a90-bc99-a052641862b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15005
51239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1500551239
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2232705835
Short name T2079
Test name
Test status
Simulation time 316669095 ps
CPU time 3.67 seconds
Started Jun 07 08:32:20 PM PDT 24
Finished Jun 07 08:32:31 PM PDT 24
Peak memory 205004 kb
Host smart-4649ed25-9a59-47be-9e49-0ec5618131ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2232705835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2232705835
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3211480542
Short name T2127
Test name
Test status
Simulation time 918849426 ps
CPU time 9.65 seconds
Started Jun 07 08:32:17 PM PDT 24
Finished Jun 07 08:32:35 PM PDT 24
Peak memory 205032 kb
Host smart-17e2e165-b5f6-4c89-acb0-1cb8d0e86321
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3211480542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3211480542
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1032713768
Short name T244
Test name
Test status
Simulation time 66674445 ps
CPU time 0.83 seconds
Started Jun 07 08:32:27 PM PDT 24
Finished Jun 07 08:32:35 PM PDT 24
Peak memory 204716 kb
Host smart-0880a930-1b4c-4ba3-a91d-448e7b8d13ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1032713768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1032713768
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1058187546
Short name T2058
Test name
Test status
Simulation time 70950921 ps
CPU time 1.44 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:37 PM PDT 24
Peak memory 213192 kb
Host smart-854506ae-0f37-41c8-877f-04ee4b8fe122
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058187546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.1058187546
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1219454184
Short name T2113
Test name
Test status
Simulation time 93103563 ps
CPU time 0.97 seconds
Started Jun 07 08:32:17 PM PDT 24
Finished Jun 07 08:32:26 PM PDT 24
Peak memory 205064 kb
Host smart-b9bff83d-bab3-4e12-b949-44ce07541e67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1219454184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1219454184
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1861889476
Short name T2091
Test name
Test status
Simulation time 87886095 ps
CPU time 0.69 seconds
Started Jun 07 08:32:25 PM PDT 24
Finished Jun 07 08:32:33 PM PDT 24
Peak memory 204652 kb
Host smart-0bc3eac6-6df3-4638-8959-7eb4996e2739
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1861889476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1861889476
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2792699126
Short name T2101
Test name
Test status
Simulation time 166282372 ps
CPU time 2.34 seconds
Started Jun 07 08:32:19 PM PDT 24
Finished Jun 07 08:32:29 PM PDT 24
Peak memory 213236 kb
Host smart-6ba9fac7-7093-43c8-8c8f-a9c52844278f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2792699126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2792699126
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1528512364
Short name T2049
Test name
Test status
Simulation time 185922183 ps
CPU time 3.75 seconds
Started Jun 07 08:32:20 PM PDT 24
Finished Jun 07 08:32:32 PM PDT 24
Peak memory 205004 kb
Host smart-8150d947-3faa-400c-98fd-28d3ffad6214
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1528512364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1528512364
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.486533276
Short name T2093
Test name
Test status
Simulation time 138676436 ps
CPU time 1.12 seconds
Started Jun 07 08:32:24 PM PDT 24
Finished Jun 07 08:32:32 PM PDT 24
Peak memory 204864 kb
Host smart-1859fd67-4e5c-46a2-b500-c32e3f47f676
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=486533276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.486533276
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3974915151
Short name T222
Test name
Test status
Simulation time 181193901 ps
CPU time 2.3 seconds
Started Jun 07 08:32:25 PM PDT 24
Finished Jun 07 08:32:34 PM PDT 24
Peak memory 220700 kb
Host smart-b9000ef3-4c60-4947-af60-29197a668851
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3974915151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3974915151
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1081094809
Short name T2084
Test name
Test status
Simulation time 92465662 ps
CPU time 1.97 seconds
Started Jun 07 08:32:21 PM PDT 24
Finished Jun 07 08:32:30 PM PDT 24
Peak memory 205048 kb
Host smart-fba89bc8-cf2f-4809-b609-cb8b3af5af75
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1081094809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1081094809
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.4161304411
Short name T2118
Test name
Test status
Simulation time 373651263 ps
CPU time 4.5 seconds
Started Jun 07 08:32:21 PM PDT 24
Finished Jun 07 08:32:33 PM PDT 24
Peak memory 204964 kb
Host smart-8f987757-69d9-4903-9ca4-45b9d3f35890
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4161304411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.4161304411
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.4061253861
Short name T2061
Test name
Test status
Simulation time 71878190 ps
CPU time 0.81 seconds
Started Jun 07 08:32:11 PM PDT 24
Finished Jun 07 08:32:22 PM PDT 24
Peak memory 204748 kb
Host smart-35934f94-dc28-4c11-b502-9afa5b4762ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4061253861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.4061253861
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.14986043
Short name T2038
Test name
Test status
Simulation time 312593716 ps
CPU time 2.19 seconds
Started Jun 07 08:32:26 PM PDT 24
Finished Jun 07 08:32:36 PM PDT 24
Peak memory 213256 kb
Host smart-d0d0b35f-2c07-4972-859b-a5fbf6aef34f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14986043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_
csr_mem_rw_with_rand_reset.14986043
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.187528656
Short name T2099
Test name
Test status
Simulation time 59697981 ps
CPU time 0.82 seconds
Started Jun 07 08:32:20 PM PDT 24
Finished Jun 07 08:32:29 PM PDT 24
Peak memory 204760 kb
Host smart-453c0977-052a-41f2-bd2b-fb58cfe88b89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=187528656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.187528656
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2287279826
Short name T2046
Test name
Test status
Simulation time 72959461 ps
CPU time 0.73 seconds
Started Jun 07 08:32:20 PM PDT 24
Finished Jun 07 08:32:28 PM PDT 24
Peak memory 204660 kb
Host smart-9d7d29ca-fcef-4efe-88fe-199fe1488845
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2287279826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2287279826
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.24974190
Short name T249
Test name
Test status
Simulation time 100832681 ps
CPU time 1.47 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:37 PM PDT 24
Peak memory 213168 kb
Host smart-35c8b939-4e02-4f1a-bc7d-dd86b3535a83
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=24974190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.24974190
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.4105848679
Short name T2039
Test name
Test status
Simulation time 95418875 ps
CPU time 2.3 seconds
Started Jun 07 08:32:22 PM PDT 24
Finished Jun 07 08:32:31 PM PDT 24
Peak memory 205000 kb
Host smart-66659541-3589-4a85-8940-ef791b8fe488
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4105848679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.4105848679
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2191221429
Short name T2067
Test name
Test status
Simulation time 138761443 ps
CPU time 1.12 seconds
Started Jun 07 08:32:21 PM PDT 24
Finished Jun 07 08:32:30 PM PDT 24
Peak memory 204984 kb
Host smart-6480eb14-2700-400c-9950-1074a9a47fcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2191221429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2191221429
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.777725309
Short name T2130
Test name
Test status
Simulation time 112148696 ps
CPU time 3.06 seconds
Started Jun 07 08:32:21 PM PDT 24
Finished Jun 07 08:32:31 PM PDT 24
Peak memory 220728 kb
Host smart-8a22e7e2-59fb-4249-abe9-b270d05d9e5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=777725309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.777725309
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1675503493
Short name T2054
Test name
Test status
Simulation time 156968820 ps
CPU time 2.34 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:41 PM PDT 24
Peak memory 213128 kb
Host smart-c0c716bf-d932-4c6e-afa5-b1e3f1950ed7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675503493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.1675503493
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1449997741
Short name T2094
Test name
Test status
Simulation time 53768906 ps
CPU time 0.7 seconds
Started Jun 07 08:32:34 PM PDT 24
Finished Jun 07 08:32:50 PM PDT 24
Peak memory 204668 kb
Host smart-9b78e714-d2f8-4e12-a8bf-474a725cbad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1449997741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1449997741
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3973343783
Short name T2078
Test name
Test status
Simulation time 158700844 ps
CPU time 1.62 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:37 PM PDT 24
Peak memory 204944 kb
Host smart-b4800673-45ca-45d5-b4e9-3e5637147d4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3973343783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.3973343783
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3253705847
Short name T2133
Test name
Test status
Simulation time 84113550 ps
CPU time 1.73 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:40 PM PDT 24
Peak memory 216308 kb
Host smart-63d87336-eecb-4710-83e7-1fe6282007d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253705847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.3253705847
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.691702890
Short name T239
Test name
Test status
Simulation time 137777660 ps
CPU time 1.03 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:40 PM PDT 24
Peak memory 204996 kb
Host smart-fe5784da-2c32-4383-917b-ba1fbecaa276
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=691702890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.691702890
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3444226597
Short name T260
Test name
Test status
Simulation time 89745655 ps
CPU time 0.73 seconds
Started Jun 07 08:32:29 PM PDT 24
Finished Jun 07 08:32:38 PM PDT 24
Peak memory 204628 kb
Host smart-06fa0de1-1997-476a-b497-8c0f02df5265
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3444226597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3444226597
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2466564033
Short name T2087
Test name
Test status
Simulation time 94388460 ps
CPU time 1.1 seconds
Started Jun 07 08:32:32 PM PDT 24
Finished Jun 07 08:32:44 PM PDT 24
Peak memory 204908 kb
Host smart-ab030f9b-60b6-49ce-9147-46d9fcf50c47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2466564033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.2466564033
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3873742496
Short name T2086
Test name
Test status
Simulation time 163099820 ps
CPU time 2.43 seconds
Started Jun 07 08:32:34 PM PDT 24
Finished Jun 07 08:32:47 PM PDT 24
Peak memory 205000 kb
Host smart-64c72606-bf78-4760-a2f7-728fbc2bde56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3873742496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3873742496
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.194861898
Short name T2107
Test name
Test status
Simulation time 486923291 ps
CPU time 3.12 seconds
Started Jun 07 08:32:35 PM PDT 24
Finished Jun 07 08:32:49 PM PDT 24
Peak memory 204948 kb
Host smart-2a549259-8f14-440c-a2e0-22670b0a5c05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=194861898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.194861898
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1935480990
Short name T2095
Test name
Test status
Simulation time 104401213 ps
CPU time 1.32 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:40 PM PDT 24
Peak memory 213104 kb
Host smart-1e75fcb4-fd66-4f58-b587-b1e7aad36bc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935480990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.1935480990
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1940316898
Short name T2064
Test name
Test status
Simulation time 46909715 ps
CPU time 0.77 seconds
Started Jun 07 08:32:31 PM PDT 24
Finished Jun 07 08:32:41 PM PDT 24
Peak memory 204688 kb
Host smart-7e95d787-488f-4d1d-b257-8ff6b924bd88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1940316898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1940316898
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1052191281
Short name T2048
Test name
Test status
Simulation time 120206644 ps
CPU time 0.75 seconds
Started Jun 07 08:32:29 PM PDT 24
Finished Jun 07 08:32:38 PM PDT 24
Peak memory 204664 kb
Host smart-22d4729e-333d-4fae-9f90-dad4557d4170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1052191281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1052191281
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3583831602
Short name T2135
Test name
Test status
Simulation time 78999693 ps
CPU time 1.11 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:40 PM PDT 24
Peak memory 204944 kb
Host smart-33923210-beb2-4440-9758-2a1aaf8e7e32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3583831602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3583831602
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2574733576
Short name T2066
Test name
Test status
Simulation time 262269751 ps
CPU time 3.3 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:40 PM PDT 24
Peak memory 220720 kb
Host smart-0f56a504-055e-4532-b518-05cbf46f98d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2574733576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2574733576
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1684300133
Short name T280
Test name
Test status
Simulation time 864485125 ps
CPU time 4.95 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:45 PM PDT 24
Peak memory 204896 kb
Host smart-b049931e-414a-4f71-a4ea-fa73563f224b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1684300133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1684300133
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.327962699
Short name T2056
Test name
Test status
Simulation time 106817230 ps
CPU time 2.16 seconds
Started Jun 07 08:32:39 PM PDT 24
Finished Jun 07 08:32:51 PM PDT 24
Peak memory 213192 kb
Host smart-15463953-a2fe-4ef6-bf81-c2d7e0f3aecc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327962699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbde
v_csr_mem_rw_with_rand_reset.327962699
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3665647974
Short name T255
Test name
Test status
Simulation time 141893066 ps
CPU time 1.12 seconds
Started Jun 07 08:32:29 PM PDT 24
Finished Jun 07 08:32:38 PM PDT 24
Peak memory 204964 kb
Host smart-0a19d7a8-6d4b-4987-84d7-4a6b09d26afe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3665647974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3665647974
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1497652986
Short name T2082
Test name
Test status
Simulation time 143123970 ps
CPU time 1.1 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:39 PM PDT 24
Peak memory 204920 kb
Host smart-97262ffb-c565-4bf7-a023-3b783602dfb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1497652986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1497652986
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3939851108
Short name T221
Test name
Test status
Simulation time 88916314 ps
CPU time 1.83 seconds
Started Jun 07 08:32:31 PM PDT 24
Finished Jun 07 08:32:43 PM PDT 24
Peak memory 220796 kb
Host smart-626d8f56-df72-4746-9fcf-36fd4fb5ba78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3939851108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3939851108
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2108240821
Short name T282
Test name
Test status
Simulation time 1035200633 ps
CPU time 5.22 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:44 PM PDT 24
Peak memory 204932 kb
Host smart-c411d4c8-d452-4cbc-90ab-f34e79d945fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2108240821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.2108240821
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3253231644
Short name T2037
Test name
Test status
Simulation time 59797127 ps
CPU time 1.47 seconds
Started Jun 07 08:32:27 PM PDT 24
Finished Jun 07 08:32:36 PM PDT 24
Peak memory 213188 kb
Host smart-40c2b06c-b411-453a-bb42-39abbb7a4157
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253231644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.3253231644
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4236361382
Short name T2076
Test name
Test status
Simulation time 36675933 ps
CPU time 0.75 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:40 PM PDT 24
Peak memory 204716 kb
Host smart-8a0a2df0-0457-4d7f-962f-0fb39450f2ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4236361382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.4236361382
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3768775298
Short name T273
Test name
Test status
Simulation time 38566090 ps
CPU time 0.66 seconds
Started Jun 07 08:32:27 PM PDT 24
Finished Jun 07 08:32:34 PM PDT 24
Peak memory 204608 kb
Host smart-a1005233-6848-4ab0-89b5-f44eb96c7e14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3768775298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3768775298
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2196306074
Short name T2102
Test name
Test status
Simulation time 220873715 ps
CPU time 1.25 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:37 PM PDT 24
Peak memory 205044 kb
Host smart-b1ac059a-b763-49f5-af64-038423e576db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2196306074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2196306074
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.4154117196
Short name T217
Test name
Test status
Simulation time 291675350 ps
CPU time 2.82 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:39 PM PDT 24
Peak memory 220588 kb
Host smart-340c4a24-5533-4b0c-a14e-45a96d84e160
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4154117196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.4154117196
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2782642494
Short name T2097
Test name
Test status
Simulation time 173118268 ps
CPU time 1.35 seconds
Started Jun 07 08:32:23 PM PDT 24
Finished Jun 07 08:32:32 PM PDT 24
Peak memory 213172 kb
Host smart-7817f199-d16d-4302-a52e-b80f969f25a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782642494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.2782642494
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1811660527
Short name T246
Test name
Test status
Simulation time 81828363 ps
CPU time 1.02 seconds
Started Jun 07 08:32:31 PM PDT 24
Finished Jun 07 08:32:42 PM PDT 24
Peak memory 204912 kb
Host smart-4b7a0887-7218-41d3-84ec-f980cd10a099
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1811660527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1811660527
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1648006277
Short name T2051
Test name
Test status
Simulation time 40406008 ps
CPU time 0.7 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:37 PM PDT 24
Peak memory 204652 kb
Host smart-dfd06fe7-0909-4ad4-9ee7-99b851d760b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1648006277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1648006277
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3836944711
Short name T2043
Test name
Test status
Simulation time 159958449 ps
CPU time 1.71 seconds
Started Jun 07 08:32:34 PM PDT 24
Finished Jun 07 08:32:46 PM PDT 24
Peak memory 204864 kb
Host smart-14d843fe-dea9-4a98-a2f5-e4762fd24145
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3836944711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3836944711
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2827143635
Short name T2072
Test name
Test status
Simulation time 99816078 ps
CPU time 2.38 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:42 PM PDT 24
Peak memory 220652 kb
Host smart-8f20e538-c9ae-4f69-a6d8-14bfafbb3917
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2827143635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2827143635
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1521048170
Short name T283
Test name
Test status
Simulation time 843504634 ps
CPU time 4.68 seconds
Started Jun 07 08:32:29 PM PDT 24
Finished Jun 07 08:32:42 PM PDT 24
Peak memory 204988 kb
Host smart-27d96a28-4e0d-4250-b0c8-96161179eeed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1521048170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1521048170
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.613653234
Short name T2104
Test name
Test status
Simulation time 99316141 ps
CPU time 1.36 seconds
Started Jun 07 08:32:26 PM PDT 24
Finished Jun 07 08:32:35 PM PDT 24
Peak memory 213172 kb
Host smart-95a907c5-38b7-4b48-9887-103def6cfd07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613653234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde
v_csr_mem_rw_with_rand_reset.613653234
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2102959755
Short name T250
Test name
Test status
Simulation time 47764761 ps
CPU time 0.97 seconds
Started Jun 07 08:32:33 PM PDT 24
Finished Jun 07 08:32:45 PM PDT 24
Peak memory 204900 kb
Host smart-2bbcde79-dba8-483b-a300-0e85ae3d5024
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2102959755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2102959755
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3792285640
Short name T263
Test name
Test status
Simulation time 84214075 ps
CPU time 0.71 seconds
Started Jun 07 08:32:27 PM PDT 24
Finished Jun 07 08:32:36 PM PDT 24
Peak memory 204660 kb
Host smart-a619e79e-ced4-485d-b8ab-17a304652687
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3792285640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.3792285640
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3012693624
Short name T258
Test name
Test status
Simulation time 197857206 ps
CPU time 1.68 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:41 PM PDT 24
Peak memory 204968 kb
Host smart-ff29a887-1f6c-45d3-9ab1-4946ae6d8ded
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3012693624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3012693624
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3235269590
Short name T220
Test name
Test status
Simulation time 50843897 ps
CPU time 1.16 seconds
Started Jun 07 08:32:32 PM PDT 24
Finished Jun 07 08:32:44 PM PDT 24
Peak memory 204964 kb
Host smart-ca336b9e-8d56-47f6-a071-a7ab29b20c48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3235269590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3235269590
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2284707552
Short name T230
Test name
Test status
Simulation time 259225380 ps
CPU time 2.43 seconds
Started Jun 07 08:32:31 PM PDT 24
Finished Jun 07 08:32:43 PM PDT 24
Peak memory 204888 kb
Host smart-dd806ae8-5595-412f-9863-f8282022e0f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2284707552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.2284707552
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.983176787
Short name T226
Test name
Test status
Simulation time 148152160 ps
CPU time 1.33 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:37 PM PDT 24
Peak memory 213136 kb
Host smart-b43efaec-0db3-4db6-9412-a3a14ead4931
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983176787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbde
v_csr_mem_rw_with_rand_reset.983176787
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4007368486
Short name T253
Test name
Test status
Simulation time 78423900 ps
CPU time 0.86 seconds
Started Jun 07 08:32:29 PM PDT 24
Finished Jun 07 08:32:41 PM PDT 24
Peak memory 204736 kb
Host smart-7b539b25-922e-4b9a-b084-102bc37e77da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4007368486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.4007368486
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1816475938
Short name T2089
Test name
Test status
Simulation time 40461111 ps
CPU time 0.65 seconds
Started Jun 07 08:32:32 PM PDT 24
Finished Jun 07 08:32:43 PM PDT 24
Peak memory 204636 kb
Host smart-05453f90-771f-4a78-80df-bc8b4dec07a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1816475938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1816475938
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2789335812
Short name T2120
Test name
Test status
Simulation time 147681317 ps
CPU time 1.19 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:37 PM PDT 24
Peak memory 204948 kb
Host smart-51ae2ec3-1b1c-4821-b484-787525009f75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2789335812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2789335812
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.775085628
Short name T2100
Test name
Test status
Simulation time 73485053 ps
CPU time 1.95 seconds
Started Jun 07 08:32:32 PM PDT 24
Finished Jun 07 08:32:45 PM PDT 24
Peak memory 205060 kb
Host smart-81954c63-f557-471a-a196-dd70917695d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=775085628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.775085628
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3638486920
Short name T276
Test name
Test status
Simulation time 2147326169 ps
CPU time 6.25 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:48 PM PDT 24
Peak memory 204988 kb
Host smart-f84113c3-53bd-4702-a8fb-ea97b165156e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3638486920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3638486920
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3399698761
Short name T2108
Test name
Test status
Simulation time 48313411 ps
CPU time 0.78 seconds
Started Jun 07 08:33:02 PM PDT 24
Finished Jun 07 08:33:06 PM PDT 24
Peak memory 204728 kb
Host smart-db628301-7097-44f8-888d-4d79e102c119
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3399698761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3399698761
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.770635960
Short name T2077
Test name
Test status
Simulation time 39365626 ps
CPU time 0.66 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:39 PM PDT 24
Peak memory 204544 kb
Host smart-1681fa7f-52cc-481f-9bcd-03ad790f4be6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=770635960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.770635960
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2825093868
Short name T254
Test name
Test status
Simulation time 326931059 ps
CPU time 1.73 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:41 PM PDT 24
Peak memory 204872 kb
Host smart-aa9bf150-573e-4419-ada3-89a7924ec242
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2825093868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2825093868
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.683736624
Short name T2074
Test name
Test status
Simulation time 267555034 ps
CPU time 2.78 seconds
Started Jun 07 08:32:29 PM PDT 24
Finished Jun 07 08:32:41 PM PDT 24
Peak memory 220676 kb
Host smart-77d33440-71c5-4d96-92a2-cd0f985ceb56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=683736624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.683736624
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2220029892
Short name T281
Test name
Test status
Simulation time 313173136 ps
CPU time 2.24 seconds
Started Jun 07 08:32:33 PM PDT 24
Finished Jun 07 08:32:46 PM PDT 24
Peak memory 204984 kb
Host smart-4fd2bd33-66e9-4eb7-b122-6eeabd235ba1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2220029892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2220029892
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2562745373
Short name T224
Test name
Test status
Simulation time 97014238 ps
CPU time 1.38 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:40 PM PDT 24
Peak memory 214640 kb
Host smart-bd7d4492-f3c6-4ddd-b49f-1c30d68d4bbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562745373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.2562745373
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2602896866
Short name T240
Test name
Test status
Simulation time 86754454 ps
CPU time 1.05 seconds
Started Jun 07 08:32:32 PM PDT 24
Finished Jun 07 08:32:43 PM PDT 24
Peak memory 204944 kb
Host smart-583036bd-860a-4704-822f-2e09d3c6e194
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2602896866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2602896866
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2243816333
Short name T93
Test name
Test status
Simulation time 71502835 ps
CPU time 0.7 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:41 PM PDT 24
Peak memory 204660 kb
Host smart-e54d50b1-a8b7-4d05-bd09-4cfc3ff56b7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2243816333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2243816333
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.884413968
Short name T2052
Test name
Test status
Simulation time 117215097 ps
CPU time 1.22 seconds
Started Jun 07 08:32:34 PM PDT 24
Finished Jun 07 08:32:47 PM PDT 24
Peak memory 204924 kb
Host smart-60bd2c09-2a3b-4e83-8fa1-cf97b5a7ad87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=884413968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.884413968
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.4147842267
Short name T208
Test name
Test status
Simulation time 151466631 ps
CPU time 3.89 seconds
Started Jun 07 08:32:27 PM PDT 24
Finished Jun 07 08:32:43 PM PDT 24
Peak memory 221004 kb
Host smart-5fe349ad-86f3-4e2c-aa7d-711626592724
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4147842267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.4147842267
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2865582567
Short name T259
Test name
Test status
Simulation time 1097941338 ps
CPU time 5.01 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:44 PM PDT 24
Peak memory 204960 kb
Host smart-da10e630-6949-4e8c-883a-e7e39b503c66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2865582567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2865582567
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3339937070
Short name T242
Test name
Test status
Simulation time 204919800 ps
CPU time 2.21 seconds
Started Jun 07 08:32:29 PM PDT 24
Finished Jun 07 08:32:39 PM PDT 24
Peak memory 204956 kb
Host smart-a44f246d-8008-4538-8261-caca19993163
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3339937070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3339937070
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.249304854
Short name T241
Test name
Test status
Simulation time 1992158118 ps
CPU time 13.35 seconds
Started Jun 07 08:32:25 PM PDT 24
Finished Jun 07 08:32:46 PM PDT 24
Peak memory 205004 kb
Host smart-bcc0e523-0a96-499e-af23-3f5bc238cf79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=249304854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.249304854
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.4270782955
Short name T2034
Test name
Test status
Simulation time 86968830 ps
CPU time 0.99 seconds
Started Jun 07 08:32:19 PM PDT 24
Finished Jun 07 08:32:28 PM PDT 24
Peak memory 204728 kb
Host smart-0b3507f4-44de-477b-a197-223584247bfc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4270782955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.4270782955
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3910900460
Short name T2114
Test name
Test status
Simulation time 81885574 ps
CPU time 1.1 seconds
Started Jun 07 08:32:21 PM PDT 24
Finished Jun 07 08:32:29 PM PDT 24
Peak memory 213184 kb
Host smart-8b858ea4-848d-4e43-99be-6893e619f21f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910900460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3910900460
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2745255270
Short name T2115
Test name
Test status
Simulation time 153405939 ps
CPU time 0.9 seconds
Started Jun 07 08:32:26 PM PDT 24
Finished Jun 07 08:32:35 PM PDT 24
Peak memory 204704 kb
Host smart-7a568ebf-625f-4af0-8ce1-cfc8f7c7baaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2745255270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2745255270
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1792539275
Short name T2036
Test name
Test status
Simulation time 30701526 ps
CPU time 0.65 seconds
Started Jun 07 08:32:16 PM PDT 24
Finished Jun 07 08:32:25 PM PDT 24
Peak memory 204636 kb
Host smart-d21f8b54-22b2-4a51-92be-4139e4670024
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1792539275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.1792539275
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3794541410
Short name T2098
Test name
Test status
Simulation time 184642878 ps
CPU time 2.24 seconds
Started Jun 07 08:32:27 PM PDT 24
Finished Jun 07 08:32:36 PM PDT 24
Peak memory 213204 kb
Host smart-d5059e79-5aa5-48a6-9c8a-3c15618af31b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3794541410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3794541410
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1294804531
Short name T2065
Test name
Test status
Simulation time 727480744 ps
CPU time 4.68 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:41 PM PDT 24
Peak memory 204884 kb
Host smart-f05f6406-0c3b-420a-bc41-34f8c352f2d3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1294804531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1294804531
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2667392551
Short name T2070
Test name
Test status
Simulation time 99038749 ps
CPU time 1.13 seconds
Started Jun 07 08:32:19 PM PDT 24
Finished Jun 07 08:32:28 PM PDT 24
Peak memory 205032 kb
Host smart-33d6b9ab-5321-4e70-933a-d403d765570c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2667392551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2667392551
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1603357094
Short name T2128
Test name
Test status
Simulation time 72739071 ps
CPU time 1.68 seconds
Started Jun 07 08:32:25 PM PDT 24
Finished Jun 07 08:32:40 PM PDT 24
Peak memory 205000 kb
Host smart-cb44c197-94db-4dbb-b89d-0af382de2992
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1603357094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1603357094
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1185626719
Short name T2123
Test name
Test status
Simulation time 1142989666 ps
CPU time 3.96 seconds
Started Jun 07 08:32:15 PM PDT 24
Finished Jun 07 08:32:28 PM PDT 24
Peak memory 205040 kb
Host smart-bd5701ef-ad72-4c9a-973e-1121feff8bef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1185626719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1185626719
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1739019429
Short name T272
Test name
Test status
Simulation time 48005259 ps
CPU time 0.69 seconds
Started Jun 07 08:32:33 PM PDT 24
Finished Jun 07 08:32:44 PM PDT 24
Peak memory 204616 kb
Host smart-0d01665c-7349-463c-b051-5a841d6b8b79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1739019429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1739019429
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2786190896
Short name T2129
Test name
Test status
Simulation time 32811074 ps
CPU time 0.61 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:40 PM PDT 24
Peak memory 204636 kb
Host smart-fc698d0a-bad7-46db-8b4f-01e8e4b43a23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2786190896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2786190896
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1247314182
Short name T2047
Test name
Test status
Simulation time 39178638 ps
CPU time 0.65 seconds
Started Jun 07 08:32:32 PM PDT 24
Finished Jun 07 08:32:43 PM PDT 24
Peak memory 204616 kb
Host smart-33f1ceea-ed47-4b3d-9147-7523fc0d03ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1247314182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1247314182
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3228664595
Short name T265
Test name
Test status
Simulation time 47296574 ps
CPU time 0.67 seconds
Started Jun 07 08:32:36 PM PDT 24
Finished Jun 07 08:32:47 PM PDT 24
Peak memory 204660 kb
Host smart-37c87e46-d783-42e6-9348-4c6d4d35ef09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3228664595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3228664595
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.270804277
Short name T266
Test name
Test status
Simulation time 68027263 ps
CPU time 0.79 seconds
Started Jun 07 08:32:31 PM PDT 24
Finished Jun 07 08:32:43 PM PDT 24
Peak memory 204616 kb
Host smart-5b0735ba-626d-4efe-992a-171c95c02e06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=270804277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.270804277
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1174529368
Short name T2060
Test name
Test status
Simulation time 39725323 ps
CPU time 0.64 seconds
Started Jun 07 08:32:36 PM PDT 24
Finished Jun 07 08:32:51 PM PDT 24
Peak memory 204660 kb
Host smart-994bcb93-43d7-40f7-b059-a149cbe5d9ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1174529368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.1174529368
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2705283318
Short name T2117
Test name
Test status
Simulation time 58445646 ps
CPU time 0.69 seconds
Started Jun 07 08:32:29 PM PDT 24
Finished Jun 07 08:32:39 PM PDT 24
Peak memory 204612 kb
Host smart-7b13f525-650e-4ff8-a206-db7b0dded9a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2705283318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2705283318
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.4227779259
Short name T248
Test name
Test status
Simulation time 75719979 ps
CPU time 2 seconds
Started Jun 07 08:32:26 PM PDT 24
Finished Jun 07 08:32:35 PM PDT 24
Peak memory 204960 kb
Host smart-a2526aff-e425-421d-b461-6bfaf2cf4807
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4227779259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.4227779259
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1758657915
Short name T243
Test name
Test status
Simulation time 915800047 ps
CPU time 5.11 seconds
Started Jun 07 08:32:27 PM PDT 24
Finished Jun 07 08:32:39 PM PDT 24
Peak memory 204968 kb
Host smart-b464cfda-d1db-4363-a5f6-f9ee3f8cda51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1758657915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1758657915
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2385036888
Short name T2119
Test name
Test status
Simulation time 102234156 ps
CPU time 0.95 seconds
Started Jun 07 08:32:26 PM PDT 24
Finished Jun 07 08:32:35 PM PDT 24
Peak memory 204704 kb
Host smart-5bbddda0-08ad-4cbe-961b-b5f6b8a318d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2385036888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2385036888
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.575646444
Short name T2092
Test name
Test status
Simulation time 292074654 ps
CPU time 2.05 seconds
Started Jun 07 08:32:29 PM PDT 24
Finished Jun 07 08:32:39 PM PDT 24
Peak memory 221312 kb
Host smart-b7a72993-7cd5-40a8-aa75-211b90fe6a34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575646444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev
_csr_mem_rw_with_rand_reset.575646444
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2562869046
Short name T2111
Test name
Test status
Simulation time 56552042 ps
CPU time 0.79 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:39 PM PDT 24
Peak memory 204696 kb
Host smart-5a684c90-9f0f-415c-9249-996c38ccfb1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2562869046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2562869046
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.258730736
Short name T2131
Test name
Test status
Simulation time 57112056 ps
CPU time 0.69 seconds
Started Jun 07 08:32:29 PM PDT 24
Finished Jun 07 08:32:39 PM PDT 24
Peak memory 204628 kb
Host smart-b55caf95-504f-4db8-9000-c753c0d49667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=258730736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.258730736
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2741595802
Short name T2103
Test name
Test status
Simulation time 150985347 ps
CPU time 1.48 seconds
Started Jun 07 08:32:29 PM PDT 24
Finished Jun 07 08:32:39 PM PDT 24
Peak memory 204916 kb
Host smart-056a242a-71b6-4a62-b8da-bb21574a260e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2741595802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2741595802
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.634925759
Short name T2073
Test name
Test status
Simulation time 123265541 ps
CPU time 2.27 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:37 PM PDT 24
Peak memory 204900 kb
Host smart-c69a6417-613a-4a38-a788-a0257087e364
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=634925759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.634925759
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4203931326
Short name T2062
Test name
Test status
Simulation time 133731940 ps
CPU time 1.1 seconds
Started Jun 07 08:32:25 PM PDT 24
Finished Jun 07 08:32:33 PM PDT 24
Peak memory 205024 kb
Host smart-3c17ebc0-00f5-4753-a37c-2191583bb843
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4203931326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.4203931326
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1434738462
Short name T189
Test name
Test status
Simulation time 97768310 ps
CPU time 2.35 seconds
Started Jun 07 08:32:26 PM PDT 24
Finished Jun 07 08:32:35 PM PDT 24
Peak memory 205052 kb
Host smart-39610294-8084-48e1-92fc-b6db959086bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1434738462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1434738462
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2740594684
Short name T2106
Test name
Test status
Simulation time 730586276 ps
CPU time 4.49 seconds
Started Jun 07 08:32:26 PM PDT 24
Finished Jun 07 08:32:37 PM PDT 24
Peak memory 204912 kb
Host smart-b3a9c2ff-0a23-4ec0-8b93-125086ca8c8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2740594684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2740594684
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.4045433583
Short name T2112
Test name
Test status
Simulation time 64880229 ps
CPU time 0.75 seconds
Started Jun 07 08:32:33 PM PDT 24
Finished Jun 07 08:32:44 PM PDT 24
Peak memory 204660 kb
Host smart-5370e6f9-65d3-4c27-b9a4-348286cc56b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4045433583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.4045433583
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1531973997
Short name T2125
Test name
Test status
Simulation time 43292899 ps
CPU time 0.66 seconds
Started Jun 07 08:32:35 PM PDT 24
Finished Jun 07 08:32:47 PM PDT 24
Peak memory 204608 kb
Host smart-8aeb7b5d-4bc0-45ae-9ee9-f1a24deb1ca3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1531973997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.1531973997
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.217720687
Short name T2057
Test name
Test status
Simulation time 39913584 ps
CPU time 0.7 seconds
Started Jun 07 08:32:37 PM PDT 24
Finished Jun 07 08:32:49 PM PDT 24
Peak memory 204680 kb
Host smart-4d3824c3-0167-4480-a8a0-b0230cc0e058
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=217720687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.217720687
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2438050774
Short name T2105
Test name
Test status
Simulation time 42550830 ps
CPU time 0.63 seconds
Started Jun 07 08:33:00 PM PDT 24
Finished Jun 07 08:33:04 PM PDT 24
Peak memory 204648 kb
Host smart-a82fd26f-e008-4a17-b1dc-d5e12b0d05e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2438050774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2438050774
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3586413614
Short name T2055
Test name
Test status
Simulation time 40623916 ps
CPU time 0.67 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:51 PM PDT 24
Peak memory 204728 kb
Host smart-ac76f895-ca8c-4d1e-8ac2-b50c61a730bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3586413614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3586413614
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.642293533
Short name T274
Test name
Test status
Simulation time 46431777 ps
CPU time 0.65 seconds
Started Jun 07 08:32:32 PM PDT 24
Finished Jun 07 08:32:44 PM PDT 24
Peak memory 204668 kb
Host smart-493c04d9-02c9-40e8-958b-391a882fe380
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=642293533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.642293533
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3526369459
Short name T2068
Test name
Test status
Simulation time 46815133 ps
CPU time 0.69 seconds
Started Jun 07 08:32:37 PM PDT 24
Finished Jun 07 08:32:48 PM PDT 24
Peak memory 204624 kb
Host smart-04a19872-8979-4d8c-b64e-f76673c2c625
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3526369459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3526369459
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1520756328
Short name T2137
Test name
Test status
Simulation time 66156469 ps
CPU time 0.68 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:40 PM PDT 24
Peak memory 204664 kb
Host smart-4c31eefc-d0c1-4f6a-bf05-f4f9c6421c9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1520756328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1520756328
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2345161982
Short name T2059
Test name
Test status
Simulation time 45118299 ps
CPU time 0.66 seconds
Started Jun 07 08:32:36 PM PDT 24
Finished Jun 07 08:32:47 PM PDT 24
Peak memory 204628 kb
Host smart-f4e6bc61-243b-43fa-9295-8c544da410b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2345161982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2345161982
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3060258571
Short name T195
Test name
Test status
Simulation time 38638509 ps
CPU time 0.69 seconds
Started Jun 07 08:32:37 PM PDT 24
Finished Jun 07 08:32:49 PM PDT 24
Peak memory 204636 kb
Host smart-1c12f30e-d22f-444a-bcb6-290c9d879667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3060258571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3060258571
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2813996552
Short name T219
Test name
Test status
Simulation time 164537895 ps
CPU time 2.24 seconds
Started Jun 07 08:32:29 PM PDT 24
Finished Jun 07 08:32:39 PM PDT 24
Peak memory 205000 kb
Host smart-ce551daa-9c84-4bf0-9cb9-4f52e9b48087
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2813996552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2813996552
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3675513792
Short name T2063
Test name
Test status
Simulation time 360881720 ps
CPU time 3.97 seconds
Started Jun 07 08:32:26 PM PDT 24
Finished Jun 07 08:32:38 PM PDT 24
Peak memory 204828 kb
Host smart-fa6d0d86-996d-47bb-ac91-415942582f84
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3675513792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3675513792
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2971269268
Short name T2045
Test name
Test status
Simulation time 74402575 ps
CPU time 0.8 seconds
Started Jun 07 08:32:23 PM PDT 24
Finished Jun 07 08:32:31 PM PDT 24
Peak memory 204704 kb
Host smart-9b82f1be-28f6-475b-80a8-c7117f908f25
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2971269268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2971269268
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2026512184
Short name T2071
Test name
Test status
Simulation time 306849393 ps
CPU time 2.28 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:38 PM PDT 24
Peak memory 213196 kb
Host smart-fc65ab55-bbc9-4ffb-b526-0eb093527df2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026512184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.2026512184
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.4010548031
Short name T237
Test name
Test status
Simulation time 59443753 ps
CPU time 0.88 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:37 PM PDT 24
Peak memory 204780 kb
Host smart-9f6cb2f1-3e59-4e76-9563-65a27de81010
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4010548031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.4010548031
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.796361132
Short name T269
Test name
Test status
Simulation time 69941563 ps
CPU time 0.69 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:41 PM PDT 24
Peak memory 204680 kb
Host smart-80c5c201-a2f0-44a0-8e4b-65be1ccc232d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=796361132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.796361132
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2208140877
Short name T2081
Test name
Test status
Simulation time 114694253 ps
CPU time 1.45 seconds
Started Jun 07 08:32:32 PM PDT 24
Finished Jun 07 08:32:44 PM PDT 24
Peak memory 213148 kb
Host smart-c01c5a5e-e159-4bf5-af10-adec039db991
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2208140877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2208140877
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.34249268
Short name T2116
Test name
Test status
Simulation time 484677663 ps
CPU time 4.46 seconds
Started Jun 07 08:32:17 PM PDT 24
Finished Jun 07 08:32:29 PM PDT 24
Peak memory 204960 kb
Host smart-be18ee12-41ad-40a7-a4dd-8fdeca25d89c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=34249268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.34249268
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3222095910
Short name T2096
Test name
Test status
Simulation time 49677802 ps
CPU time 0.95 seconds
Started Jun 07 08:32:23 PM PDT 24
Finished Jun 07 08:32:31 PM PDT 24
Peak memory 205000 kb
Host smart-e501190f-f77e-4dff-a814-5200443465c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3222095910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3222095910
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1644442681
Short name T2083
Test name
Test status
Simulation time 154597334 ps
CPU time 1.72 seconds
Started Jun 07 08:32:29 PM PDT 24
Finished Jun 07 08:32:39 PM PDT 24
Peak memory 205044 kb
Host smart-d4a64a80-6f8d-46cf-9da4-c3db5ef1f33b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1644442681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1644442681
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1303734507
Short name T229
Test name
Test status
Simulation time 1200422364 ps
CPU time 3.31 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:42 PM PDT 24
Peak memory 205024 kb
Host smart-bd734adb-983c-43e7-8bfd-3702b9d3f6a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1303734507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1303734507
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3084027038
Short name T2134
Test name
Test status
Simulation time 39149741 ps
CPU time 0.68 seconds
Started Jun 07 08:32:37 PM PDT 24
Finished Jun 07 08:32:48 PM PDT 24
Peak memory 204652 kb
Host smart-754f8d7c-f354-4b3d-96f4-be902fab2a1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3084027038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3084027038
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2971700376
Short name T2136
Test name
Test status
Simulation time 126627653 ps
CPU time 0.75 seconds
Started Jun 07 08:32:31 PM PDT 24
Finished Jun 07 08:32:43 PM PDT 24
Peak memory 204692 kb
Host smart-ec685834-fb76-401f-b9e0-e28c328cffdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2971700376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2971700376
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1800143943
Short name T2044
Test name
Test status
Simulation time 50306924 ps
CPU time 0.68 seconds
Started Jun 07 08:32:39 PM PDT 24
Finished Jun 07 08:32:50 PM PDT 24
Peak memory 204712 kb
Host smart-c33fe742-7290-4691-b484-edf9909e26cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1800143943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1800143943
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.4213861904
Short name T194
Test name
Test status
Simulation time 31381059 ps
CPU time 0.66 seconds
Started Jun 07 08:32:34 PM PDT 24
Finished Jun 07 08:32:45 PM PDT 24
Peak memory 204656 kb
Host smart-56884898-c324-4e56-85cf-6aba810c42da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4213861904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.4213861904
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3065830931
Short name T2090
Test name
Test status
Simulation time 53519551 ps
CPU time 0.66 seconds
Started Jun 07 08:32:36 PM PDT 24
Finished Jun 07 08:32:47 PM PDT 24
Peak memory 204660 kb
Host smart-2fa5d573-370f-4654-8acf-fae4e63037d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3065830931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3065830931
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1782841498
Short name T268
Test name
Test status
Simulation time 76574176 ps
CPU time 0.7 seconds
Started Jun 07 08:32:32 PM PDT 24
Finished Jun 07 08:32:43 PM PDT 24
Peak memory 204676 kb
Host smart-87a0a3ce-7804-4885-ab11-c37285a055f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1782841498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1782841498
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.301428258
Short name T2035
Test name
Test status
Simulation time 41962738 ps
CPU time 0.69 seconds
Started Jun 07 08:32:35 PM PDT 24
Finished Jun 07 08:32:51 PM PDT 24
Peak memory 204660 kb
Host smart-220d85a4-625f-439a-8d42-0559841d5c86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=301428258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.301428258
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1322076357
Short name T2126
Test name
Test status
Simulation time 38854415 ps
CPU time 0.68 seconds
Started Jun 07 08:32:34 PM PDT 24
Finished Jun 07 08:32:45 PM PDT 24
Peak memory 204668 kb
Host smart-a2a9eb26-3a23-464b-8162-fa9d7030e40d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1322076357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1322076357
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.4044682904
Short name T2088
Test name
Test status
Simulation time 38964098 ps
CPU time 0.66 seconds
Started Jun 07 08:32:36 PM PDT 24
Finished Jun 07 08:32:47 PM PDT 24
Peak memory 204660 kb
Host smart-6fd96c04-6211-44b2-bcc4-1c80c2360dd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4044682904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.4044682904
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1249297186
Short name T2124
Test name
Test status
Simulation time 63310735 ps
CPU time 0.67 seconds
Started Jun 07 08:32:37 PM PDT 24
Finished Jun 07 08:32:48 PM PDT 24
Peak memory 204660 kb
Host smart-e853e94c-4219-436c-b49d-34ac77f59779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1249297186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.1249297186
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.353508777
Short name T225
Test name
Test status
Simulation time 58010969 ps
CPU time 1.17 seconds
Started Jun 07 08:32:29 PM PDT 24
Finished Jun 07 08:32:39 PM PDT 24
Peak memory 213228 kb
Host smart-cee71a70-942c-42ea-bf96-3375879c76be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353508777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.353508777
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1202692136
Short name T247
Test name
Test status
Simulation time 82339007 ps
CPU time 1.02 seconds
Started Jun 07 08:32:30 PM PDT 24
Finished Jun 07 08:32:39 PM PDT 24
Peak memory 204952 kb
Host smart-91ebb3a6-08f3-4f36-98f2-d802f4533027
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1202692136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1202692136
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1292532904
Short name T209
Test name
Test status
Simulation time 122290739 ps
CPU time 1.11 seconds
Started Jun 07 08:32:25 PM PDT 24
Finished Jun 07 08:32:33 PM PDT 24
Peak memory 204932 kb
Host smart-69984866-e85b-4ddd-be50-05d0c1549dcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1292532904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1292532904
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1818735108
Short name T2110
Test name
Test status
Simulation time 306764976 ps
CPU time 3.43 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:40 PM PDT 24
Peak memory 220828 kb
Host smart-8075d1fb-7f54-4f1f-947f-928b60a35c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1818735108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1818735108
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3808540853
Short name T191
Test name
Test status
Simulation time 307510255 ps
CPU time 2.58 seconds
Started Jun 07 08:32:26 PM PDT 24
Finished Jun 07 08:32:35 PM PDT 24
Peak memory 204872 kb
Host smart-a23425f3-03a7-4009-aba6-34f4f2be94d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3808540853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3808540853
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2292352478
Short name T228
Test name
Test status
Simulation time 80550177 ps
CPU time 1.71 seconds
Started Jun 07 08:32:27 PM PDT 24
Finished Jun 07 08:32:37 PM PDT 24
Peak memory 213156 kb
Host smart-2eff8d89-d177-4036-934a-644de23610cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292352478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.2292352478
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1053221902
Short name T2080
Test name
Test status
Simulation time 81958409 ps
CPU time 1.01 seconds
Started Jun 07 08:32:22 PM PDT 24
Finished Jun 07 08:32:30 PM PDT 24
Peak memory 204944 kb
Host smart-056f3e81-ac31-40f7-bf68-a35289d25423
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1053221902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1053221902
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1967600464
Short name T193
Test name
Test status
Simulation time 40423160 ps
CPU time 0.7 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:37 PM PDT 24
Peak memory 204660 kb
Host smart-96eb1a32-4a7c-49de-9e10-6d58a3ecaf91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1967600464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1967600464
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.12004621
Short name T2053
Test name
Test status
Simulation time 101626472 ps
CPU time 1.07 seconds
Started Jun 07 08:32:22 PM PDT 24
Finished Jun 07 08:32:30 PM PDT 24
Peak memory 204848 kb
Host smart-86eb7e88-aa8c-4c01-80cc-3448e6762e23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=12004621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.12004621
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1139279759
Short name T2075
Test name
Test status
Simulation time 83906866 ps
CPU time 2.27 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:38 PM PDT 24
Peak memory 204920 kb
Host smart-3081274c-ffcd-4927-b44e-73ad1bfbb762
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1139279759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1139279759
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.205746535
Short name T2040
Test name
Test status
Simulation time 94383066 ps
CPU time 2.36 seconds
Started Jun 07 08:32:27 PM PDT 24
Finished Jun 07 08:32:38 PM PDT 24
Peak memory 213236 kb
Host smart-43db7b33-e152-4a7b-bd4b-9af01a5cb231
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205746535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev
_csr_mem_rw_with_rand_reset.205746535
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2303012234
Short name T2085
Test name
Test status
Simulation time 55966041 ps
CPU time 0.82 seconds
Started Jun 07 08:32:32 PM PDT 24
Finished Jun 07 08:32:43 PM PDT 24
Peak memory 204828 kb
Host smart-169980d7-3b28-4943-ae87-e7428fafe485
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2303012234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2303012234
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3443157064
Short name T2050
Test name
Test status
Simulation time 65227924 ps
CPU time 0.67 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:36 PM PDT 24
Peak memory 204680 kb
Host smart-438ddc0e-cb52-4c8c-ab17-75a50bd92017
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3443157064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3443157064
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2280601166
Short name T2069
Test name
Test status
Simulation time 173526043 ps
CPU time 1.21 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:37 PM PDT 24
Peak memory 204940 kb
Host smart-83819b2f-9336-4b96-88d4-2bb920d55f11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2280601166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2280601166
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.583806233
Short name T2122
Test name
Test status
Simulation time 410869616 ps
CPU time 2.63 seconds
Started Jun 07 08:32:25 PM PDT 24
Finished Jun 07 08:32:35 PM PDT 24
Peak memory 204940 kb
Host smart-8b07f918-480c-498f-9196-e02af2923bf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=583806233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.583806233
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.678954235
Short name T2042
Test name
Test status
Simulation time 79128903 ps
CPU time 1.82 seconds
Started Jun 07 08:32:25 PM PDT 24
Finished Jun 07 08:32:33 PM PDT 24
Peak memory 213188 kb
Host smart-98a7acac-11d5-468d-a378-f8caab8cf2f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678954235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev
_csr_mem_rw_with_rand_reset.678954235
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2419060077
Short name T245
Test name
Test status
Simulation time 49890603 ps
CPU time 0.81 seconds
Started Jun 07 08:32:26 PM PDT 24
Finished Jun 07 08:32:34 PM PDT 24
Peak memory 204708 kb
Host smart-eecde4ff-f2d7-43c6-a5a3-d3c59f873f0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2419060077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2419060077
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2283322919
Short name T264
Test name
Test status
Simulation time 72861188 ps
CPU time 0.7 seconds
Started Jun 07 08:32:21 PM PDT 24
Finished Jun 07 08:32:29 PM PDT 24
Peak memory 204588 kb
Host smart-2f9eb2d0-0de6-4473-b0f5-7d27cd218532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2283322919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2283322919
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2012513843
Short name T251
Test name
Test status
Simulation time 73816552 ps
CPU time 1.04 seconds
Started Jun 07 08:32:28 PM PDT 24
Finished Jun 07 08:32:38 PM PDT 24
Peak memory 204984 kb
Host smart-266bf91f-29fb-4ec1-a1c6-c3f3db644db8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2012513843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.2012513843
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2841838370
Short name T2109
Test name
Test status
Simulation time 73459629 ps
CPU time 1.55 seconds
Started Jun 07 08:32:24 PM PDT 24
Finished Jun 07 08:32:33 PM PDT 24
Peak memory 204964 kb
Host smart-4a0314e3-78cd-4560-befd-a467faae18fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2841838370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2841838370
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3596765296
Short name T190
Test name
Test status
Simulation time 438706134 ps
CPU time 2.8 seconds
Started Jun 07 08:32:24 PM PDT 24
Finished Jun 07 08:32:33 PM PDT 24
Peak memory 204996 kb
Host smart-6602749b-7ce4-4c7b-ad70-f5e76aafd285
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3596765296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3596765296
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.86365004
Short name T2041
Test name
Test status
Simulation time 95445794 ps
CPU time 2.12 seconds
Started Jun 07 08:32:23 PM PDT 24
Finished Jun 07 08:32:32 PM PDT 24
Peak memory 213200 kb
Host smart-5a0ca20f-91e4-40cd-abad-fbbfc9eb207f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86365004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_
csr_mem_rw_with_rand_reset.86365004
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1301255616
Short name T252
Test name
Test status
Simulation time 54683013 ps
CPU time 0.76 seconds
Started Jun 07 08:32:31 PM PDT 24
Finished Jun 07 08:32:43 PM PDT 24
Peak memory 204696 kb
Host smart-e8214f84-09d4-4d9f-bd23-81f7f57f5a29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1301255616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1301255616
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1931375913
Short name T91
Test name
Test status
Simulation time 43703945 ps
CPU time 0.67 seconds
Started Jun 07 08:32:25 PM PDT 24
Finished Jun 07 08:32:32 PM PDT 24
Peak memory 204640 kb
Host smart-4ce5a434-acfa-48f4-90c6-f4259dc6fe82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1931375913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1931375913
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1199251045
Short name T2132
Test name
Test status
Simulation time 186506458 ps
CPU time 1.37 seconds
Started Jun 07 08:32:24 PM PDT 24
Finished Jun 07 08:32:33 PM PDT 24
Peak memory 205004 kb
Host smart-0f2e9410-9c7c-42d8-b260-0e13641f590b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1199251045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1199251045
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3452106570
Short name T2121
Test name
Test status
Simulation time 115116594 ps
CPU time 3.27 seconds
Started Jun 07 08:32:31 PM PDT 24
Finished Jun 07 08:32:44 PM PDT 24
Peak memory 205028 kb
Host smart-6106da87-cae6-4cc1-8cd9-9231ea8f7098
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3452106570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3452106570
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.753775294
Short name T227
Test name
Test status
Simulation time 525938355 ps
CPU time 4.12 seconds
Started Jun 07 08:32:21 PM PDT 24
Finished Jun 07 08:32:32 PM PDT 24
Peak memory 204980 kb
Host smart-24ba4b99-b84f-4457-8026-ce8117726926
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=753775294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.753775294
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.4169561899
Short name T311
Test name
Test status
Simulation time 10157771616 ps
CPU time 14.32 seconds
Started Jun 07 08:40:28 PM PDT 24
Finished Jun 07 08:40:44 PM PDT 24
Peak memory 205772 kb
Host smart-e8be2263-e9d7-41d8-b4b6-707e784efdc3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4169561899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.4169561899
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.2558064628
Short name T406
Test name
Test status
Simulation time 10110141490 ps
CPU time 12.41 seconds
Started Jun 07 08:40:22 PM PDT 24
Finished Jun 07 08:40:35 PM PDT 24
Peak memory 205760 kb
Host smart-a2a16705-7523-46ad-959d-195094074e47
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2558064628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.2558064628
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.1213748662
Short name T1550
Test name
Test status
Simulation time 10160612312 ps
CPU time 15.79 seconds
Started Jun 07 08:40:29 PM PDT 24
Finished Jun 07 08:40:46 PM PDT 24
Peak memory 205776 kb
Host smart-c7c4180c-84fa-4f6e-9fdb-22be1f475f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12137
48662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.1213748662
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.4220560850
Short name T1165
Test name
Test status
Simulation time 14160898496 ps
CPU time 18.16 seconds
Started Jun 07 08:40:02 PM PDT 24
Finished Jun 07 08:40:21 PM PDT 24
Peak memory 205888 kb
Host smart-109c95c1-9292-46dd-91dc-6df33bb803a0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4220560850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.4220560850
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.3271668788
Short name T1782
Test name
Test status
Simulation time 23224604173 ps
CPU time 25.43 seconds
Started Jun 07 08:40:00 PM PDT 24
Finished Jun 07 08:40:26 PM PDT 24
Peak memory 205936 kb
Host smart-e62e448c-1c66-44ca-b780-4e5c89c82d17
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3271668788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.3271668788
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.3453339301
Short name T1740
Test name
Test status
Simulation time 10062341665 ps
CPU time 12.93 seconds
Started Jun 07 08:40:00 PM PDT 24
Finished Jun 07 08:40:14 PM PDT 24
Peak memory 205880 kb
Host smart-60bed144-9d65-43a9-abb5-3e7f6a8e21d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34533
39301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.3453339301
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.206206496
Short name T66
Test name
Test status
Simulation time 10972137053 ps
CPU time 14.44 seconds
Started Jun 07 08:40:00 PM PDT 24
Finished Jun 07 08:40:16 PM PDT 24
Peak memory 205816 kb
Host smart-b0376090-9622-424d-9d2f-666916800dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20620
6496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.206206496
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.40404100
Short name T505
Test name
Test status
Simulation time 10049751221 ps
CPU time 12.75 seconds
Started Jun 07 08:40:07 PM PDT 24
Finished Jun 07 08:40:20 PM PDT 24
Peak memory 205748 kb
Host smart-3f647c92-f462-44fb-9e17-790b510ec78c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40404
100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.40404100
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.3335704713
Short name T947
Test name
Test status
Simulation time 10055798863 ps
CPU time 14.47 seconds
Started Jun 07 08:40:01 PM PDT 24
Finished Jun 07 08:40:17 PM PDT 24
Peak memory 205764 kb
Host smart-d54ba1c5-e69e-41ec-97b7-b0d624bc6ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33357
04713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.3335704713
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.3448338558
Short name T86
Test name
Test status
Simulation time 10813763824 ps
CPU time 14.65 seconds
Started Jun 07 08:40:02 PM PDT 24
Finished Jun 07 08:40:18 PM PDT 24
Peak memory 205704 kb
Host smart-a94594a0-96a5-4a3b-a178-36f372f0328a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34483
38558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3448338558
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.451537518
Short name T647
Test name
Test status
Simulation time 10093995959 ps
CPU time 14.96 seconds
Started Jun 07 08:40:07 PM PDT 24
Finished Jun 07 08:40:23 PM PDT 24
Peak memory 205768 kb
Host smart-9da9177e-da01-4ca4-8591-e69078378af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45153
7518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.451537518
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.2731523547
Short name T723
Test name
Test status
Simulation time 10159933930 ps
CPU time 12.86 seconds
Started Jun 07 08:40:27 PM PDT 24
Finished Jun 07 08:40:41 PM PDT 24
Peak memory 205944 kb
Host smart-5b64099f-ac53-4e1e-a381-a390db40fd7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27315
23547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.2731523547
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.3593272924
Short name T74
Test name
Test status
Simulation time 10034761523 ps
CPU time 14.62 seconds
Started Jun 07 08:40:26 PM PDT 24
Finished Jun 07 08:40:42 PM PDT 24
Peak memory 205776 kb
Host smart-a5103305-6150-49f2-890e-0fc00982ff5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35932
72924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.3593272924
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.3930385141
Short name T1214
Test name
Test status
Simulation time 10071568115 ps
CPU time 13.17 seconds
Started Jun 07 08:40:07 PM PDT 24
Finished Jun 07 08:40:22 PM PDT 24
Peak memory 205840 kb
Host smart-eb65c582-c9af-4656-bf8d-c1a70fd71f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39303
85141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.3930385141
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.2332382697
Short name T1945
Test name
Test status
Simulation time 10122472690 ps
CPU time 12.87 seconds
Started Jun 07 08:40:07 PM PDT 24
Finished Jun 07 08:40:20 PM PDT 24
Peak memory 205812 kb
Host smart-10fd3f24-f87d-44d9-bdab-df6ce9390eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23323
82697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.2332382697
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.500213702
Short name T1583
Test name
Test status
Simulation time 13214735579 ps
CPU time 16.48 seconds
Started Jun 07 08:40:08 PM PDT 24
Finished Jun 07 08:40:25 PM PDT 24
Peak memory 205852 kb
Host smart-060aca1c-9215-4c85-ae30-c3f4fc4c31e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50021
3702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.500213702
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.3739361966
Short name T502
Test name
Test status
Simulation time 10105122590 ps
CPU time 12.65 seconds
Started Jun 07 08:40:10 PM PDT 24
Finished Jun 07 08:40:24 PM PDT 24
Peak memory 205936 kb
Host smart-09deb8ad-7b66-4cc6-801d-128e2c35cfc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37393
61966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3739361966
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.4229981198
Short name T375
Test name
Test status
Simulation time 24567716793 ps
CPU time 402.5 seconds
Started Jun 07 08:40:10 PM PDT 24
Finished Jun 07 08:46:53 PM PDT 24
Peak memory 205848 kb
Host smart-b26664b5-1f10-4800-9d48-83c213c704e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42299
81198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.4229981198
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1120234766
Short name T687
Test name
Test status
Simulation time 10049053712 ps
CPU time 13.51 seconds
Started Jun 07 08:40:08 PM PDT 24
Finished Jun 07 08:40:22 PM PDT 24
Peak memory 205860 kb
Host smart-00a5a191-5921-4ce9-9a69-1e8df82513d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11202
34766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1120234766
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.2578832317
Short name T347
Test name
Test status
Simulation time 10057736806 ps
CPU time 12.73 seconds
Started Jun 07 08:40:07 PM PDT 24
Finished Jun 07 08:40:20 PM PDT 24
Peak memory 205800 kb
Host smart-c022066a-bf05-4ee9-89c2-48984a27a738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25788
32317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.2578832317
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.712662628
Short name T994
Test name
Test status
Simulation time 10101055322 ps
CPU time 12.02 seconds
Started Jun 07 08:40:10 PM PDT 24
Finished Jun 07 08:40:23 PM PDT 24
Peak memory 205844 kb
Host smart-dbf0fdf2-de2b-468b-a74c-c2cb2c4318db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71266
2628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.712662628
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.1508178934
Short name T327
Test name
Test status
Simulation time 10118898182 ps
CPU time 12.24 seconds
Started Jun 07 08:40:08 PM PDT 24
Finished Jun 07 08:40:21 PM PDT 24
Peak memory 205768 kb
Host smart-6dd4f3bf-a3cc-4263-a9ff-981f08caf5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15081
78934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.1508178934
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.1165029340
Short name T817
Test name
Test status
Simulation time 10075499679 ps
CPU time 13.99 seconds
Started Jun 07 08:40:28 PM PDT 24
Finished Jun 07 08:40:44 PM PDT 24
Peak memory 205852 kb
Host smart-34a5bb01-0e00-4c82-aaa1-1f67ca10eb31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11650
29340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.1165029340
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.642491808
Short name T39
Test name
Test status
Simulation time 10045551376 ps
CPU time 12.87 seconds
Started Jun 07 08:40:27 PM PDT 24
Finished Jun 07 08:40:42 PM PDT 24
Peak memory 205820 kb
Host smart-37b44b2e-6083-4d81-8dad-42f46c58f6e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64249
1808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.642491808
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.2865946750
Short name T216
Test name
Test status
Simulation time 19479515269 ps
CPU time 30.96 seconds
Started Jun 07 08:40:08 PM PDT 24
Finished Jun 07 08:40:40 PM PDT 24
Peak memory 205816 kb
Host smart-ebfa65cc-7884-4f66-8a2a-eb94425a91a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28659
46750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.2865946750
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.2977675104
Short name T2019
Test name
Test status
Simulation time 10059165983 ps
CPU time 15.24 seconds
Started Jun 07 08:40:08 PM PDT 24
Finished Jun 07 08:40:24 PM PDT 24
Peak memory 205788 kb
Host smart-aa40e47b-0a28-4254-805d-6d881b26b39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29776
75104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.2977675104
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1848194227
Short name T387
Test name
Test status
Simulation time 10105204155 ps
CPU time 12.88 seconds
Started Jun 07 08:40:07 PM PDT 24
Finished Jun 07 08:40:21 PM PDT 24
Peak memory 205940 kb
Host smart-94df8287-9feb-4bf1-8ef0-0b3fbbc2fd78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18481
94227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1848194227
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.4279757428
Short name T1868
Test name
Test status
Simulation time 36972318612 ps
CPU time 644.1 seconds
Started Jun 07 08:40:18 PM PDT 24
Finished Jun 07 08:51:03 PM PDT 24
Peak memory 205876 kb
Host smart-f8fc553a-a558-4b30-bd9c-ad8e3c681d4a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4279757428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.4279757428
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.3186167912
Short name T1934
Test name
Test status
Simulation time 15944442895 ps
CPU time 147.44 seconds
Started Jun 07 08:40:19 PM PDT 24
Finished Jun 07 08:42:48 PM PDT 24
Peak memory 205796 kb
Host smart-b1d6f503-d22f-49f0-ae84-f7d806e8941d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3186167912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.3186167912
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.1516690833
Short name T1483
Test name
Test status
Simulation time 23763864523 ps
CPU time 109.29 seconds
Started Jun 07 08:40:17 PM PDT 24
Finished Jun 07 08:42:07 PM PDT 24
Peak memory 205812 kb
Host smart-64564b3a-dd8d-4e64-99b0-5320f79ce7f7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1516690833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.1516690833
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.270119631
Short name T987
Test name
Test status
Simulation time 10147832475 ps
CPU time 13.53 seconds
Started Jun 07 08:40:16 PM PDT 24
Finished Jun 07 08:40:30 PM PDT 24
Peak memory 205884 kb
Host smart-95c69457-ffaa-4b5c-b8ac-5fcc94c7b751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27011
9631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.270119631
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.1272049199
Short name T1555
Test name
Test status
Simulation time 10039150769 ps
CPU time 12.75 seconds
Started Jun 07 08:40:27 PM PDT 24
Finished Jun 07 08:40:42 PM PDT 24
Peak memory 205800 kb
Host smart-f844836d-3847-42d5-a666-68d16aa44399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12720
49199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.1272049199
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.4077397303
Short name T1982
Test name
Test status
Simulation time 10045432867 ps
CPU time 12.42 seconds
Started Jun 07 08:40:27 PM PDT 24
Finished Jun 07 08:40:41 PM PDT 24
Peak memory 205736 kb
Host smart-9077edbe-24af-4c10-abd9-7c4a1ede8fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40773
97303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.4077397303
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_smoke.2931420670
Short name T1480
Test name
Test status
Simulation time 10102171808 ps
CPU time 15.1 seconds
Started Jun 07 08:40:02 PM PDT 24
Finished Jun 07 08:40:18 PM PDT 24
Peak memory 205708 kb
Host smart-a9f9384f-0a1d-439c-858e-caa728178ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29314
20670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.2931420670
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.3383092619
Short name T1853
Test name
Test status
Simulation time 10081485806 ps
CPU time 13.63 seconds
Started Jun 07 08:40:21 PM PDT 24
Finished Jun 07 08:40:35 PM PDT 24
Peak memory 205892 kb
Host smart-45231f11-fbfb-4990-bb3b-09742f1be846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33830
92619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.3383092619
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.622487093
Short name T781
Test name
Test status
Simulation time 10089403392 ps
CPU time 13.37 seconds
Started Jun 07 08:40:16 PM PDT 24
Finished Jun 07 08:40:30 PM PDT 24
Peak memory 205768 kb
Host smart-d26eb038-f70d-4844-a8ec-032bee770af2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62248
7093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.622487093
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.1948437781
Short name T1964
Test name
Test status
Simulation time 19546136572 ps
CPU time 103.32 seconds
Started Jun 07 08:40:18 PM PDT 24
Finished Jun 07 08:42:02 PM PDT 24
Peak memory 205940 kb
Host smart-bcfd7db8-f71f-4472-bbe3-ad3a53241c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19484
37781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.1948437781
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.31908540
Short name T1284
Test name
Test status
Simulation time 25127927069 ps
CPU time 141.01 seconds
Started Jun 07 08:40:18 PM PDT 24
Finished Jun 07 08:42:40 PM PDT 24
Peak memory 205852 kb
Host smart-fce362ce-84d3-40b1-875e-b769af1b390f
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31908540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus
_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_tr
affic.31908540
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.1131606445
Short name T1454
Test name
Test status
Simulation time 10137269489 ps
CPU time 12.71 seconds
Started Jun 07 08:40:55 PM PDT 24
Finished Jun 07 08:41:08 PM PDT 24
Peak memory 205804 kb
Host smart-0e661d03-c4cb-4a45-b060-ba4d31333791
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1131606445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.1131606445
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.2917519888
Short name T692
Test name
Test status
Simulation time 10084651866 ps
CPU time 12.79 seconds
Started Jun 07 08:40:52 PM PDT 24
Finished Jun 07 08:41:06 PM PDT 24
Peak memory 205784 kb
Host smart-6eaec25e-4efb-4adc-ae40-f4fd086280ad
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2917519888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.2917519888
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.3901065432
Short name T1997
Test name
Test status
Simulation time 10084656172 ps
CPU time 13.21 seconds
Started Jun 07 08:40:54 PM PDT 24
Finished Jun 07 08:41:09 PM PDT 24
Peak memory 205776 kb
Host smart-f9179035-893d-408d-aaf2-59272789e30a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39010
65432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.3901065432
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.3956764469
Short name T467
Test name
Test status
Simulation time 13408036224 ps
CPU time 15.87 seconds
Started Jun 07 08:40:27 PM PDT 24
Finished Jun 07 08:40:44 PM PDT 24
Peak memory 205752 kb
Host smart-4412532c-f8b7-4c65-83f6-897b28e2a20e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3956764469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.3956764469
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.1393951598
Short name T46
Test name
Test status
Simulation time 23375617949 ps
CPU time 27.35 seconds
Started Jun 07 08:40:27 PM PDT 24
Finished Jun 07 08:40:56 PM PDT 24
Peak memory 205820 kb
Host smart-24a5c80b-e214-492c-a411-7af6d668e503
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1393951598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.1393951598
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1703468637
Short name T1745
Test name
Test status
Simulation time 10052581598 ps
CPU time 12.95 seconds
Started Jun 07 08:40:26 PM PDT 24
Finished Jun 07 08:40:40 PM PDT 24
Peak memory 205724 kb
Host smart-5a4dc01f-93a1-48e2-85ba-c6ee87e2cd6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17034
68637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1703468637
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.3757884733
Short name T1887
Test name
Test status
Simulation time 10339175326 ps
CPU time 14.28 seconds
Started Jun 07 08:40:28 PM PDT 24
Finished Jun 07 08:40:44 PM PDT 24
Peak memory 205760 kb
Host smart-d9498c12-d023-463d-a4ae-d40b9dab2b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37578
84733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.3757884733
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.4279421792
Short name T869
Test name
Test status
Simulation time 10045135348 ps
CPU time 12.64 seconds
Started Jun 07 08:40:40 PM PDT 24
Finished Jun 07 08:40:53 PM PDT 24
Peak memory 205772 kb
Host smart-c31e78ee-5413-411b-ad63-0c103f154e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42794
21792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.4279421792
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.743380962
Short name T564
Test name
Test status
Simulation time 10750370120 ps
CPU time 14.63 seconds
Started Jun 07 08:40:34 PM PDT 24
Finished Jun 07 08:40:50 PM PDT 24
Peak memory 205868 kb
Host smart-64a8e6d5-a7ab-4197-b801-f3eb49a09646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74338
0962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.743380962
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.232009036
Short name T1616
Test name
Test status
Simulation time 10155275335 ps
CPU time 12.98 seconds
Started Jun 07 08:40:52 PM PDT 24
Finished Jun 07 08:41:07 PM PDT 24
Peak memory 205740 kb
Host smart-3add6345-982c-4f15-a012-4eff53d42ae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23200
9036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.232009036
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.971438547
Short name T1739
Test name
Test status
Simulation time 10091325922 ps
CPU time 13.01 seconds
Started Jun 07 08:40:52 PM PDT 24
Finished Jun 07 08:41:06 PM PDT 24
Peak memory 205968 kb
Host smart-9fbfcc15-9d07-4d3c-97b9-3477daff2818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97143
8547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.971438547
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.56408760
Short name T18
Test name
Test status
Simulation time 10093268920 ps
CPU time 13.24 seconds
Started Jun 07 08:40:34 PM PDT 24
Finished Jun 07 08:40:48 PM PDT 24
Peak memory 205876 kb
Host smart-efa1ad96-444a-4d06-b27d-8eb6e7b67051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56408
760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.56408760
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.1584071083
Short name T1937
Test name
Test status
Simulation time 10150960301 ps
CPU time 13.34 seconds
Started Jun 07 08:40:35 PM PDT 24
Finished Jun 07 08:40:50 PM PDT 24
Peak memory 205828 kb
Host smart-8b12fe25-dc9f-478a-8e53-0aeaae7f38aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15840
71083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.1584071083
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.476472110
Short name T1063
Test name
Test status
Simulation time 13167320696 ps
CPU time 18.88 seconds
Started Jun 07 08:40:36 PM PDT 24
Finished Jun 07 08:40:56 PM PDT 24
Peak memory 205824 kb
Host smart-511ab95a-9092-4ae6-935a-dc11da9933c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47647
2110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.476472110
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.1213444954
Short name T693
Test name
Test status
Simulation time 10107484395 ps
CPU time 12.78 seconds
Started Jun 07 08:40:34 PM PDT 24
Finished Jun 07 08:40:49 PM PDT 24
Peak memory 205884 kb
Host smart-1c9f604d-d7ad-4a04-acc3-f2ea6f61e937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12134
44954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.1213444954
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.916785499
Short name T843
Test name
Test status
Simulation time 19665921068 ps
CPU time 80.18 seconds
Started Jun 07 08:40:37 PM PDT 24
Finished Jun 07 08:41:58 PM PDT 24
Peak memory 205852 kb
Host smart-3c50405f-a365-4b53-897e-4d42bd9485ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91678
5499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.916785499
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.3271407049
Short name T1035
Test name
Test status
Simulation time 10081421400 ps
CPU time 13.08 seconds
Started Jun 07 08:40:34 PM PDT 24
Finished Jun 07 08:40:48 PM PDT 24
Peak memory 205852 kb
Host smart-d0bc50df-aacb-4e1d-8276-cdcee2c617ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32714
07049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.3271407049
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.87993691
Short name T846
Test name
Test status
Simulation time 10062009516 ps
CPU time 13.61 seconds
Started Jun 07 08:40:38 PM PDT 24
Finished Jun 07 08:40:53 PM PDT 24
Peak memory 205832 kb
Host smart-ee93791b-f494-42d7-9034-116619bfa473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87993
691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.87993691
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.4086415123
Short name T1675
Test name
Test status
Simulation time 10051583083 ps
CPU time 14.37 seconds
Started Jun 07 08:40:39 PM PDT 24
Finished Jun 07 08:40:54 PM PDT 24
Peak memory 205732 kb
Host smart-fbb79169-ce37-4738-9020-5190499d7ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40864
15123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.4086415123
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3651651358
Short name T415
Test name
Test status
Simulation time 10097273703 ps
CPU time 12.43 seconds
Started Jun 07 08:40:39 PM PDT 24
Finished Jun 07 08:40:52 PM PDT 24
Peak memory 205812 kb
Host smart-086a52c9-e48d-464f-800f-756bab0a0d5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36516
51358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3651651358
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.1116145402
Short name T657
Test name
Test status
Simulation time 10050768614 ps
CPU time 14.44 seconds
Started Jun 07 08:40:50 PM PDT 24
Finished Jun 07 08:41:06 PM PDT 24
Peak memory 205876 kb
Host smart-c277e1dc-afd6-4921-bb02-ee9186ce85b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11161
45402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.1116145402
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_eop_single_bit_handling.175576171
Short name T539
Test name
Test status
Simulation time 10102703287 ps
CPU time 13.04 seconds
Started Jun 07 08:40:51 PM PDT 24
Finished Jun 07 08:41:06 PM PDT 24
Peak memory 205852 kb
Host smart-30b2e08d-39c9-437a-bf2b-1c3b68cc3f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17557
6171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_eop_single_bit_handling.175576171
Directory /workspace/1.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.1527528382
Short name T185
Test name
Test status
Simulation time 10050873091 ps
CPU time 13.39 seconds
Started Jun 07 08:40:51 PM PDT 24
Finished Jun 07 08:41:06 PM PDT 24
Peak memory 205820 kb
Host smart-8cc896cd-ed66-410b-a3be-43947a074df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15275
28382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.1527528382
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1587409822
Short name T573
Test name
Test status
Simulation time 10048487654 ps
CPU time 12.81 seconds
Started Jun 07 08:40:52 PM PDT 24
Finished Jun 07 08:41:07 PM PDT 24
Peak memory 205760 kb
Host smart-7b9c960d-d318-4681-890e-af31d9ea1b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15874
09822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1587409822
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.1509664927
Short name T2002
Test name
Test status
Simulation time 27855121801 ps
CPU time 55.52 seconds
Started Jun 07 08:40:39 PM PDT 24
Finished Jun 07 08:41:36 PM PDT 24
Peak memory 205824 kb
Host smart-f4f79911-ba44-4ea3-bb3e-6b07d3d94a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15096
64927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.1509664927
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.553154959
Short name T1018
Test name
Test status
Simulation time 10052624830 ps
CPU time 14.67 seconds
Started Jun 07 08:40:38 PM PDT 24
Finished Jun 07 08:40:53 PM PDT 24
Peak memory 205780 kb
Host smart-a4f1d498-1549-4f61-976c-16c293b20bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55315
4959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.553154959
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.4046237355
Short name T1705
Test name
Test status
Simulation time 10072788197 ps
CPU time 15.93 seconds
Started Jun 07 08:40:41 PM PDT 24
Finished Jun 07 08:40:58 PM PDT 24
Peak memory 205772 kb
Host smart-784ace13-aa0c-4fc3-87f5-95509c5abc4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40462
37355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.4046237355
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.1294625124
Short name T1867
Test name
Test status
Simulation time 17696580416 ps
CPU time 127.98 seconds
Started Jun 07 08:40:44 PM PDT 24
Finished Jun 07 08:42:53 PM PDT 24
Peak memory 205880 kb
Host smart-efdedd71-650d-49cd-b820-1abe670c207b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1294625124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.1294625124
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.1728165761
Short name T508
Test name
Test status
Simulation time 10083908377 ps
CPU time 13.29 seconds
Started Jun 07 08:40:45 PM PDT 24
Finished Jun 07 08:40:59 PM PDT 24
Peak memory 205848 kb
Host smart-6c2ee023-e115-41c6-80cc-a3ef50ce6c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17281
65761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.1728165761
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.2265404003
Short name T525
Test name
Test status
Simulation time 10053701729 ps
CPU time 13.14 seconds
Started Jun 07 08:40:51 PM PDT 24
Finished Jun 07 08:41:05 PM PDT 24
Peak memory 205856 kb
Host smart-06fd957a-781f-43a2-a19b-c6e449a446c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22654
04003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.2265404003
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.4033694721
Short name T187
Test name
Test status
Simulation time 394205801 ps
CPU time 1.19 seconds
Started Jun 07 08:40:59 PM PDT 24
Finished Jun 07 08:41:02 PM PDT 24
Peak memory 221804 kb
Host smart-5b18f052-763a-43b0-8c9a-8c173b54bba1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4033694721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.4033694721
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3157124194
Short name T1549
Test name
Test status
Simulation time 10111217385 ps
CPU time 12.94 seconds
Started Jun 07 08:40:52 PM PDT 24
Finished Jun 07 08:41:07 PM PDT 24
Peak memory 205836 kb
Host smart-7bc322b9-73c1-4a28-b744-4f909cadcdd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31571
24194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3157124194
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.1144053779
Short name T1371
Test name
Test status
Simulation time 10114433563 ps
CPU time 14.5 seconds
Started Jun 07 08:40:27 PM PDT 24
Finished Jun 07 08:40:43 PM PDT 24
Peak memory 205716 kb
Host smart-7aeb3428-5fa0-4f46-a24c-04b05259f189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11440
53779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.1144053779
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.676861123
Short name T21
Test name
Test status
Simulation time 10079014028 ps
CPU time 12.96 seconds
Started Jun 07 08:40:46 PM PDT 24
Finished Jun 07 08:41:00 PM PDT 24
Peak memory 205848 kb
Host smart-8e5b3b18-457e-4dc8-8976-acb054a18ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67686
1123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.676861123
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.3691089739
Short name T790
Test name
Test status
Simulation time 21064731991 ps
CPU time 314.79 seconds
Started Jun 07 08:40:44 PM PDT 24
Finished Jun 07 08:46:00 PM PDT 24
Peak memory 205788 kb
Host smart-03b16d14-e633-4717-bcd8-f249a368af48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36910
89739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.3691089739
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.3510139235
Short name T1864
Test name
Test status
Simulation time 36605718028 ps
CPU time 231.16 seconds
Started Jun 07 08:40:49 PM PDT 24
Finished Jun 07 08:44:41 PM PDT 24
Peak memory 205828 kb
Host smart-325e4039-72c2-4122-aa61-5eb38f11005e
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510139235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_
traffic.3510139235
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.3137105389
Short name T429
Test name
Test status
Simulation time 10217366963 ps
CPU time 13.4 seconds
Started Jun 07 08:43:16 PM PDT 24
Finished Jun 07 08:43:32 PM PDT 24
Peak memory 205840 kb
Host smart-677ceaa7-79d0-48a1-b786-847cf7264f75
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3137105389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.3137105389
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.2315042764
Short name T1729
Test name
Test status
Simulation time 10087050233 ps
CPU time 16.07 seconds
Started Jun 07 08:43:14 PM PDT 24
Finished Jun 07 08:43:33 PM PDT 24
Peak memory 205864 kb
Host smart-810de071-63d3-40c1-b00b-50fa400985ae
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2315042764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.2315042764
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.1282674245
Short name T931
Test name
Test status
Simulation time 10158816613 ps
CPU time 13.55 seconds
Started Jun 07 08:43:13 PM PDT 24
Finished Jun 07 08:43:28 PM PDT 24
Peak memory 205792 kb
Host smart-37ac19ae-ad57-4604-9466-b72a5b7807c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12826
74245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.1282674245
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.346236182
Short name T418
Test name
Test status
Simulation time 13889270106 ps
CPU time 19.42 seconds
Started Jun 07 08:43:00 PM PDT 24
Finished Jun 07 08:43:24 PM PDT 24
Peak memory 205724 kb
Host smart-eec551cf-a93c-4f1b-8987-3a40e9f5f4b0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=346236182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.346236182
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.3677097827
Short name T8
Test name
Test status
Simulation time 23267647681 ps
CPU time 27.11 seconds
Started Jun 07 08:43:00 PM PDT 24
Finished Jun 07 08:43:31 PM PDT 24
Peak memory 205816 kb
Host smart-cf0df3df-3455-4746-bab1-127c76abc82b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3677097827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.3677097827
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.995157134
Short name T1422
Test name
Test status
Simulation time 10069843268 ps
CPU time 15.6 seconds
Started Jun 07 08:43:02 PM PDT 24
Finished Jun 07 08:43:22 PM PDT 24
Peak memory 205808 kb
Host smart-e4a64aee-6d14-47d4-9055-48df339b4ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99515
7134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.995157134
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.3793914929
Short name T172
Test name
Test status
Simulation time 10477025888 ps
CPU time 13.02 seconds
Started Jun 07 08:43:00 PM PDT 24
Finished Jun 07 08:43:18 PM PDT 24
Peak memory 205776 kb
Host smart-2abd0987-9b79-4176-a427-79c041faf663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37939
14929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.3793914929
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.1319450135
Short name T1733
Test name
Test status
Simulation time 10046518186 ps
CPU time 13.23 seconds
Started Jun 07 08:43:01 PM PDT 24
Finished Jun 07 08:43:19 PM PDT 24
Peak memory 205824 kb
Host smart-6e1eb275-51e4-43ec-97f8-66af8d104434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13194
50135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.1319450135
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.1494824717
Short name T1564
Test name
Test status
Simulation time 10103602326 ps
CPU time 13.32 seconds
Started Jun 07 08:42:59 PM PDT 24
Finished Jun 07 08:43:17 PM PDT 24
Peak memory 205768 kb
Host smart-2cc5a70a-d957-4af7-bd5c-706060cb4dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14948
24717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1494824717
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.11183290
Short name T2013
Test name
Test status
Simulation time 10885267090 ps
CPU time 14.66 seconds
Started Jun 07 08:42:59 PM PDT 24
Finished Jun 07 08:43:18 PM PDT 24
Peak memory 205852 kb
Host smart-ddfa08a6-ef45-4eb3-b392-77ec882efd93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11183
290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.11183290
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.371840704
Short name T1621
Test name
Test status
Simulation time 10162683594 ps
CPU time 13.85 seconds
Started Jun 07 08:42:58 PM PDT 24
Finished Jun 07 08:43:16 PM PDT 24
Peak memory 205840 kb
Host smart-14e53da1-049f-42ea-bf82-d76ac9d6e1d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37184
0704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.371840704
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.4012241901
Short name T930
Test name
Test status
Simulation time 10074420454 ps
CPU time 13.12 seconds
Started Jun 07 08:43:14 PM PDT 24
Finished Jun 07 08:43:30 PM PDT 24
Peak memory 205844 kb
Host smart-86f37a57-2432-4036-a3f5-a53c5a039ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40122
41901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.4012241901
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.1987351955
Short name T1014
Test name
Test status
Simulation time 10052041414 ps
CPU time 13.11 seconds
Started Jun 07 08:43:11 PM PDT 24
Finished Jun 07 08:43:26 PM PDT 24
Peak memory 205748 kb
Host smart-1d9a573b-6605-427d-b2a0-7d9384bd6144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19873
51955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.1987351955
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.4275863841
Short name T913
Test name
Test status
Simulation time 10176349668 ps
CPU time 13.54 seconds
Started Jun 07 08:43:00 PM PDT 24
Finished Jun 07 08:43:18 PM PDT 24
Peak memory 205748 kb
Host smart-68da4075-a16f-497f-a5a2-c9d6986b43db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42758
63841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.4275863841
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.86699392
Short name T557
Test name
Test status
Simulation time 10056397556 ps
CPU time 12.69 seconds
Started Jun 07 08:43:04 PM PDT 24
Finished Jun 07 08:43:20 PM PDT 24
Peak memory 205768 kb
Host smart-9df02d1a-099e-459b-9c0d-8e143567864c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86699
392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.86699392
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.3968749451
Short name T1138
Test name
Test status
Simulation time 13213399762 ps
CPU time 15.32 seconds
Started Jun 07 08:43:03 PM PDT 24
Finished Jun 07 08:43:23 PM PDT 24
Peak memory 205848 kb
Host smart-589d0668-893c-477c-8362-2e1be920900b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39687
49451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.3968749451
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.4161723786
Short name T1574
Test name
Test status
Simulation time 10097751654 ps
CPU time 13.29 seconds
Started Jun 07 08:42:59 PM PDT 24
Finished Jun 07 08:43:16 PM PDT 24
Peak memory 205892 kb
Host smart-9540ebd1-073b-4e6a-b4af-251930a97cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41617
23786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.4161723786
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.1519454881
Short name T4
Test name
Test status
Simulation time 13899579382 ps
CPU time 45.86 seconds
Started Jun 07 08:43:07 PM PDT 24
Finished Jun 07 08:43:56 PM PDT 24
Peak memory 205848 kb
Host smart-7357b36b-2168-4fec-9721-7cb0d1698612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15194
54881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.1519454881
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.227882256
Short name T1968
Test name
Test status
Simulation time 10064203340 ps
CPU time 13.78 seconds
Started Jun 07 08:43:01 PM PDT 24
Finished Jun 07 08:43:19 PM PDT 24
Peak memory 205816 kb
Host smart-4b220e76-4487-4102-9f1a-b904a5b50da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22788
2256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.227882256
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.2249540914
Short name T1798
Test name
Test status
Simulation time 10105912888 ps
CPU time 15.04 seconds
Started Jun 07 08:43:07 PM PDT 24
Finished Jun 07 08:43:25 PM PDT 24
Peak memory 205776 kb
Host smart-73a68eac-f7db-4b31-bed2-81b2290e102d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22495
40914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2249540914
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.2941607147
Short name T451
Test name
Test status
Simulation time 10063751036 ps
CPU time 13.11 seconds
Started Jun 07 08:43:07 PM PDT 24
Finished Jun 07 08:43:23 PM PDT 24
Peak memory 205772 kb
Host smart-3b4a5a52-1fce-4bc1-b4b7-60f86e8b3409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29416
07147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.2941607147
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.37680388
Short name T1693
Test name
Test status
Simulation time 10071433841 ps
CPU time 14.89 seconds
Started Jun 07 08:43:07 PM PDT 24
Finished Jun 07 08:43:25 PM PDT 24
Peak memory 205728 kb
Host smart-26ee4430-018a-4b33-a372-5e7a83502bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37680
388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.37680388
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1242136234
Short name T756
Test name
Test status
Simulation time 10073851691 ps
CPU time 15.5 seconds
Started Jun 07 08:43:08 PM PDT 24
Finished Jun 07 08:43:26 PM PDT 24
Peak memory 205904 kb
Host smart-ca8b600b-3be4-4c88-8629-5047782f8f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12421
36234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1242136234
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_eop_single_bit_handling.3148208340
Short name T87
Test name
Test status
Simulation time 10095240654 ps
CPU time 14.41 seconds
Started Jun 07 08:43:07 PM PDT 24
Finished Jun 07 08:43:25 PM PDT 24
Peak memory 205988 kb
Host smart-01a87608-6a21-4bad-bb7f-5a69bdaae02a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31482
08340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_eop_single_bit_handling.3148208340
Directory /workspace/10.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3199849356
Short name T549
Test name
Test status
Simulation time 10067826355 ps
CPU time 15.31 seconds
Started Jun 07 08:43:07 PM PDT 24
Finished Jun 07 08:43:26 PM PDT 24
Peak memory 205852 kb
Host smart-83d30b7e-ad79-4b98-934f-c55fdc89a196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31998
49356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3199849356
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.2564991513
Short name T159
Test name
Test status
Simulation time 29639725646 ps
CPU time 54.94 seconds
Started Jun 07 08:43:07 PM PDT 24
Finished Jun 07 08:44:05 PM PDT 24
Peak memory 205764 kb
Host smart-75cce86f-1305-48dd-b02b-003aa8ba5088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25649
91513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.2564991513
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.3611541531
Short name T929
Test name
Test status
Simulation time 10051954431 ps
CPU time 13.6 seconds
Started Jun 07 08:43:07 PM PDT 24
Finished Jun 07 08:43:24 PM PDT 24
Peak memory 205872 kb
Host smart-bcc58f3e-478b-4d1a-811b-43a43d015eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36115
41531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.3611541531
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.1685766776
Short name T865
Test name
Test status
Simulation time 10058765714 ps
CPU time 13.22 seconds
Started Jun 07 08:43:07 PM PDT 24
Finished Jun 07 08:43:24 PM PDT 24
Peak memory 205876 kb
Host smart-31f618fd-bf93-4234-917d-2e818410696b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16857
66776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.1685766776
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.1477429432
Short name T30
Test name
Test status
Simulation time 10143146124 ps
CPU time 13.23 seconds
Started Jun 07 08:43:07 PM PDT 24
Finished Jun 07 08:43:24 PM PDT 24
Peak memory 205840 kb
Host smart-7dc82631-5ebd-47fc-bd54-39c1095070d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14774
29432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.1477429432
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.1130779148
Short name T962
Test name
Test status
Simulation time 10097709160 ps
CPU time 15.36 seconds
Started Jun 07 08:43:08 PM PDT 24
Finished Jun 07 08:43:27 PM PDT 24
Peak memory 205732 kb
Host smart-22c36b9c-ee9e-44f1-a4c2-9b78286d4891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11307
79148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.1130779148
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.4028077885
Short name T1563
Test name
Test status
Simulation time 10092499235 ps
CPU time 13.36 seconds
Started Jun 07 08:43:08 PM PDT 24
Finished Jun 07 08:43:24 PM PDT 24
Peak memory 205680 kb
Host smart-18a8451f-385f-4e5f-a9d5-aa57426791e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40280
77885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.4028077885
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.3493762261
Short name T138
Test name
Test status
Simulation time 10167466754 ps
CPU time 13.2 seconds
Started Jun 07 08:43:01 PM PDT 24
Finished Jun 07 08:43:19 PM PDT 24
Peak memory 205856 kb
Host smart-8484b510-f655-4d7b-bda4-6c47f3936f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34937
62261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.3493762261
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2261270230
Short name T1658
Test name
Test status
Simulation time 10077947110 ps
CPU time 13.27 seconds
Started Jun 07 08:43:09 PM PDT 24
Finished Jun 07 08:43:25 PM PDT 24
Peak memory 205880 kb
Host smart-9d44f22d-d1c7-42ba-8093-1fda18566697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22612
70230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2261270230
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.3782384616
Short name T612
Test name
Test status
Simulation time 10072552816 ps
CPU time 15.41 seconds
Started Jun 07 08:43:06 PM PDT 24
Finished Jun 07 08:43:25 PM PDT 24
Peak memory 205796 kb
Host smart-5813e20c-22bd-4a50-872d-bc45eb27c652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37823
84616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.3782384616
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.313629295
Short name T1893
Test name
Test status
Simulation time 20702403323 ps
CPU time 303.1 seconds
Started Jun 07 08:43:11 PM PDT 24
Finished Jun 07 08:48:16 PM PDT 24
Peak memory 205828 kb
Host smart-f102528f-e853-49ae-b9a7-7937486da3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31362
9295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.313629295
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.955830363
Short name T481
Test name
Test status
Simulation time 10139195926 ps
CPU time 14.54 seconds
Started Jun 07 08:43:22 PM PDT 24
Finished Jun 07 08:43:39 PM PDT 24
Peak memory 205796 kb
Host smart-af492d4d-757a-4308-97f3-77a159c68a0f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=955830363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.955830363
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.2334680750
Short name T1041
Test name
Test status
Simulation time 10089151644 ps
CPU time 13.16 seconds
Started Jun 07 08:43:22 PM PDT 24
Finished Jun 07 08:43:37 PM PDT 24
Peak memory 205792 kb
Host smart-b10e72af-8aa6-4144-895c-5930ccfe7aeb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2334680750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.2334680750
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.2479094667
Short name T608
Test name
Test status
Simulation time 10153207270 ps
CPU time 12.75 seconds
Started Jun 07 08:43:20 PM PDT 24
Finished Jun 07 08:43:35 PM PDT 24
Peak memory 205792 kb
Host smart-75d1a84f-61d6-4788-9de2-2e5656cfdc70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24790
94667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.2479094667
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.898570271
Short name T1252
Test name
Test status
Simulation time 13512169066 ps
CPU time 18.12 seconds
Started Jun 07 08:43:14 PM PDT 24
Finished Jun 07 08:43:35 PM PDT 24
Peak memory 205880 kb
Host smart-c89f1964-89dd-4fa2-97ba-a7e683cb3eb3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=898570271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.898570271
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.3727004011
Short name T1228
Test name
Test status
Simulation time 23340177044 ps
CPU time 31.87 seconds
Started Jun 07 08:43:18 PM PDT 24
Finished Jun 07 08:43:52 PM PDT 24
Peak memory 205900 kb
Host smart-c4099bd4-a13e-46f7-88cb-a6dc42d73c82
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3727004011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.3727004011
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.327635305
Short name T1198
Test name
Test status
Simulation time 10080073345 ps
CPU time 13.59 seconds
Started Jun 07 08:43:15 PM PDT 24
Finished Jun 07 08:43:31 PM PDT 24
Peak memory 205848 kb
Host smart-8fabefdb-36aa-496b-a64b-c8f488c65899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32763
5305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.327635305
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.2685936917
Short name T53
Test name
Test status
Simulation time 10137937324 ps
CPU time 13.62 seconds
Started Jun 07 08:43:14 PM PDT 24
Finished Jun 07 08:43:30 PM PDT 24
Peak memory 205860 kb
Host smart-2ad93761-08d9-4f12-ae52-af6acb2309b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26859
36917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.2685936917
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.1940418607
Short name T798
Test name
Test status
Simulation time 10075233752 ps
CPU time 12.75 seconds
Started Jun 07 08:43:13 PM PDT 24
Finished Jun 07 08:43:28 PM PDT 24
Peak memory 205812 kb
Host smart-9245a317-d002-443c-b192-7a2643e1312a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19404
18607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1940418607
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.1693704165
Short name T546
Test name
Test status
Simulation time 10055420196 ps
CPU time 14.32 seconds
Started Jun 07 08:43:15 PM PDT 24
Finished Jun 07 08:43:31 PM PDT 24
Peak memory 205756 kb
Host smart-f22cc522-3a64-41a2-ae99-d0860c3a8c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16937
04165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.1693704165
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.159354092
Short name T1794
Test name
Test status
Simulation time 10805441576 ps
CPU time 15.15 seconds
Started Jun 07 08:43:14 PM PDT 24
Finished Jun 07 08:43:31 PM PDT 24
Peak memory 205756 kb
Host smart-86310709-051d-4932-8e66-7e0d728c6fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15935
4092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.159354092
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.1906736298
Short name T1509
Test name
Test status
Simulation time 10285251228 ps
CPU time 14.64 seconds
Started Jun 07 08:43:14 PM PDT 24
Finished Jun 07 08:43:32 PM PDT 24
Peak memory 205828 kb
Host smart-c29f2eff-7445-4b69-8a81-8fdcdca33f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19067
36298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.1906736298
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.936272642
Short name T628
Test name
Test status
Simulation time 10122427468 ps
CPU time 14.12 seconds
Started Jun 07 08:43:20 PM PDT 24
Finished Jun 07 08:43:36 PM PDT 24
Peak memory 205800 kb
Host smart-db2c390d-0e05-455e-9671-a809b4c4b7f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93627
2642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.936272642
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.4286322481
Short name T812
Test name
Test status
Simulation time 10039006943 ps
CPU time 12.49 seconds
Started Jun 07 08:43:18 PM PDT 24
Finished Jun 07 08:43:33 PM PDT 24
Peak memory 205916 kb
Host smart-526dec54-2dd4-4e97-aa4e-bd624a16a2ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42863
22481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.4286322481
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.1242485551
Short name T468
Test name
Test status
Simulation time 10079122139 ps
CPU time 13.52 seconds
Started Jun 07 08:43:14 PM PDT 24
Finished Jun 07 08:43:31 PM PDT 24
Peak memory 205864 kb
Host smart-5c65605d-e4d1-41f5-b5a6-19050d55b805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12424
85551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1242485551
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.3294422467
Short name T1613
Test name
Test status
Simulation time 10146242155 ps
CPU time 13.41 seconds
Started Jun 07 08:43:13 PM PDT 24
Finished Jun 07 08:43:29 PM PDT 24
Peak memory 205972 kb
Host smart-d57f281e-afd0-4850-8da7-65f6b6f90936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32944
22467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.3294422467
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.113610393
Short name T891
Test name
Test status
Simulation time 13214123117 ps
CPU time 16.41 seconds
Started Jun 07 08:43:13 PM PDT 24
Finished Jun 07 08:43:31 PM PDT 24
Peak memory 205724 kb
Host smart-69166933-f0b6-4cff-98f8-3871ccb2ea30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11361
0393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.113610393
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.460685041
Short name T835
Test name
Test status
Simulation time 10126382156 ps
CPU time 13.63 seconds
Started Jun 07 08:43:14 PM PDT 24
Finished Jun 07 08:43:31 PM PDT 24
Peak memory 205852 kb
Host smart-22ac7c16-a10c-4761-b51e-22e7b9f5efea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46068
5041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.460685041
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.2074141312
Short name T1946
Test name
Test status
Simulation time 16131404095 ps
CPU time 54.8 seconds
Started Jun 07 08:43:12 PM PDT 24
Finished Jun 07 08:44:09 PM PDT 24
Peak memory 205920 kb
Host smart-7ba0fba6-66a6-440c-ab9d-1df05cfc03b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20741
41312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.2074141312
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.3262776578
Short name T553
Test name
Test status
Simulation time 10051769750 ps
CPU time 13.01 seconds
Started Jun 07 08:43:12 PM PDT 24
Finished Jun 07 08:43:27 PM PDT 24
Peak memory 205772 kb
Host smart-22005502-250d-4fd4-a86f-40b4b7d40df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32627
76578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.3262776578
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.3700991812
Short name T416
Test name
Test status
Simulation time 10098210629 ps
CPU time 14.75 seconds
Started Jun 07 08:43:21 PM PDT 24
Finished Jun 07 08:43:39 PM PDT 24
Peak memory 205828 kb
Host smart-e1d76eff-aa53-47da-bb73-7706812a8257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37009
91812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.3700991812
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.2302973230
Short name T782
Test name
Test status
Simulation time 10110099225 ps
CPU time 13.08 seconds
Started Jun 07 08:43:19 PM PDT 24
Finished Jun 07 08:43:34 PM PDT 24
Peak memory 205772 kb
Host smart-a07f3a61-6822-4ef8-80cf-cdfc6f31a628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23029
73230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.2302973230
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.2148310385
Short name T424
Test name
Test status
Simulation time 10068105956 ps
CPU time 12.83 seconds
Started Jun 07 08:43:22 PM PDT 24
Finished Jun 07 08:43:38 PM PDT 24
Peak memory 205852 kb
Host smart-2936be0b-0d43-4d02-aecd-8617de603a96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21483
10385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.2148310385
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_eop_single_bit_handling.2633234950
Short name T783
Test name
Test status
Simulation time 10077039418 ps
CPU time 13.09 seconds
Started Jun 07 08:43:25 PM PDT 24
Finished Jun 07 08:43:39 PM PDT 24
Peak memory 205772 kb
Host smart-9bce1c83-ba8e-4ab5-803b-a0bb4f92205d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26332
34950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_eop_single_bit_handling.2633234950
Directory /workspace/11.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.4248679308
Short name T439
Test name
Test status
Simulation time 10049277309 ps
CPU time 13.19 seconds
Started Jun 07 08:43:21 PM PDT 24
Finished Jun 07 08:43:36 PM PDT 24
Peak memory 205884 kb
Host smart-c47a91bb-8595-4196-b0df-9159d60d1f28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42486
79308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.4248679308
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1194345017
Short name T1977
Test name
Test status
Simulation time 10032158641 ps
CPU time 14.51 seconds
Started Jun 07 08:43:21 PM PDT 24
Finished Jun 07 08:43:38 PM PDT 24
Peak memory 205756 kb
Host smart-e368a20d-d2ad-40ee-af52-03abf5bfcba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11943
45017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1194345017
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.2745390292
Short name T177
Test name
Test status
Simulation time 25928998015 ps
CPU time 48.45 seconds
Started Jun 07 08:43:17 PM PDT 24
Finished Jun 07 08:44:08 PM PDT 24
Peak memory 205796 kb
Host smart-e451a6d2-35b6-43e0-8d77-8b3a6664d8da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27453
90292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.2745390292
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.2903424749
Short name T50
Test name
Test status
Simulation time 10090028619 ps
CPU time 13.17 seconds
Started Jun 07 08:43:18 PM PDT 24
Finished Jun 07 08:43:33 PM PDT 24
Peak memory 205852 kb
Host smart-b6d10e25-a814-4482-b979-145d2991ed86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29034
24749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.2903424749
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1391067613
Short name T127
Test name
Test status
Simulation time 10127398360 ps
CPU time 16.06 seconds
Started Jun 07 08:43:19 PM PDT 24
Finished Jun 07 08:43:37 PM PDT 24
Peak memory 205840 kb
Host smart-8b777f18-877b-488d-b080-7be2292a9b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13910
67613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1391067613
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.1453047264
Short name T1754
Test name
Test status
Simulation time 10066938948 ps
CPU time 12.73 seconds
Started Jun 07 08:43:24 PM PDT 24
Finished Jun 07 08:43:39 PM PDT 24
Peak memory 205872 kb
Host smart-4525372f-98f1-4298-a578-aeb4a360f3b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14530
47264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.1453047264
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.2921939199
Short name T630
Test name
Test status
Simulation time 10074483727 ps
CPU time 12.43 seconds
Started Jun 07 08:43:20 PM PDT 24
Finished Jun 07 08:43:35 PM PDT 24
Peak memory 205776 kb
Host smart-1455eb6e-6243-4810-9db6-901ceb54f3cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29219
39199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.2921939199
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.2898031887
Short name T157
Test name
Test status
Simulation time 10066052167 ps
CPU time 14.76 seconds
Started Jun 07 08:43:19 PM PDT 24
Finished Jun 07 08:43:36 PM PDT 24
Peak memory 205816 kb
Host smart-fdb10487-4eff-40d2-96dd-fe61d35c25f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28980
31887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.2898031887
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.1093462165
Short name T665
Test name
Test status
Simulation time 10048857235 ps
CPU time 13.31 seconds
Started Jun 07 08:43:24 PM PDT 24
Finished Jun 07 08:43:39 PM PDT 24
Peak memory 205772 kb
Host smart-6547da38-c442-429c-9ed2-070242637dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10934
62165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.1093462165
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.952264908
Short name T728
Test name
Test status
Simulation time 10097688556 ps
CPU time 16.12 seconds
Started Jun 07 08:43:13 PM PDT 24
Finished Jun 07 08:43:31 PM PDT 24
Peak memory 205848 kb
Host smart-4cfc09cf-b5c0-446b-9726-57053d1084c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95226
4908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.952264908
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.4038576357
Short name T463
Test name
Test status
Simulation time 10121171590 ps
CPU time 13.52 seconds
Started Jun 07 08:43:24 PM PDT 24
Finished Jun 07 08:43:40 PM PDT 24
Peak memory 205832 kb
Host smart-c6276c63-5aec-4edd-adc5-ea8b400586e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40385
76357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.4038576357
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.3648747286
Short name T1029
Test name
Test status
Simulation time 10107788343 ps
CPU time 13.69 seconds
Started Jun 07 08:43:22 PM PDT 24
Finished Jun 07 08:43:38 PM PDT 24
Peak memory 205884 kb
Host smart-04c78e85-a195-4fd3-ae3e-76e4716a52ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36487
47286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3648747286
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.1627586224
Short name T1347
Test name
Test status
Simulation time 25236237258 ps
CPU time 118.81 seconds
Started Jun 07 08:43:24 PM PDT 24
Finished Jun 07 08:45:25 PM PDT 24
Peak memory 205876 kb
Host smart-53636c80-ade6-4fd7-ad7d-22305f7b7ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16275
86224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.1627586224
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.2336887608
Short name T1626
Test name
Test status
Simulation time 10135079428 ps
CPU time 13.47 seconds
Started Jun 07 08:43:32 PM PDT 24
Finished Jun 07 08:43:49 PM PDT 24
Peak memory 205812 kb
Host smart-9cd23b82-904b-4a78-ba0c-633e7fcc84bb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2336887608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.2336887608
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.3038739471
Short name T814
Test name
Test status
Simulation time 10076676412 ps
CPU time 13.1 seconds
Started Jun 07 08:43:33 PM PDT 24
Finished Jun 07 08:43:49 PM PDT 24
Peak memory 205796 kb
Host smart-d0b164a6-ee54-4d49-a8e2-b68e40185ae0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3038739471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.3038739471
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.1484725812
Short name T381
Test name
Test status
Simulation time 10125959842 ps
CPU time 14.14 seconds
Started Jun 07 08:43:31 PM PDT 24
Finished Jun 07 08:43:47 PM PDT 24
Peak memory 205736 kb
Host smart-8267fe42-fb96-4f4b-9822-e470464da272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14847
25812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.1484725812
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.4293278907
Short name T764
Test name
Test status
Simulation time 13748267654 ps
CPU time 17.19 seconds
Started Jun 07 08:43:22 PM PDT 24
Finished Jun 07 08:43:41 PM PDT 24
Peak memory 205908 kb
Host smart-a5387ed8-1e77-426d-ad15-1a5c6716ccb9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4293278907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.4293278907
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.2480919018
Short name T682
Test name
Test status
Simulation time 23194060310 ps
CPU time 24.73 seconds
Started Jun 07 08:43:20 PM PDT 24
Finished Jun 07 08:43:47 PM PDT 24
Peak memory 205876 kb
Host smart-59300769-35c6-4b36-8980-82bacab42bc3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2480919018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.2480919018
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2186711262
Short name T515
Test name
Test status
Simulation time 10056537470 ps
CPU time 14.35 seconds
Started Jun 07 08:43:22 PM PDT 24
Finished Jun 07 08:43:39 PM PDT 24
Peak memory 205872 kb
Host smart-0ed89648-236c-4c65-9c49-c8ee8c5ab3f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21867
11262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2186711262
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.4290840194
Short name T1590
Test name
Test status
Simulation time 11253736840 ps
CPU time 15.15 seconds
Started Jun 07 08:43:28 PM PDT 24
Finished Jun 07 08:43:45 PM PDT 24
Peak memory 205820 kb
Host smart-cd32cbc4-17fa-4dad-b44a-1c8dac9825ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42908
40194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.4290840194
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.3470803213
Short name T1387
Test name
Test status
Simulation time 10054160074 ps
CPU time 12.39 seconds
Started Jun 07 08:43:28 PM PDT 24
Finished Jun 07 08:43:42 PM PDT 24
Peak memory 205776 kb
Host smart-bdad0c08-557a-4b4b-9da0-5d82c2255925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34708
03213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.3470803213
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.783135216
Short name T669
Test name
Test status
Simulation time 10055356637 ps
CPU time 15.43 seconds
Started Jun 07 08:43:33 PM PDT 24
Finished Jun 07 08:43:51 PM PDT 24
Peak memory 205768 kb
Host smart-fa607e4a-597e-4285-b546-44def412f296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78313
5216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.783135216
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.796370972
Short name T662
Test name
Test status
Simulation time 10808432384 ps
CPU time 15.16 seconds
Started Jun 07 08:43:26 PM PDT 24
Finished Jun 07 08:43:44 PM PDT 24
Peak memory 205720 kb
Host smart-4041d9e8-dda3-4414-9a55-1212ebdc5d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79637
0972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.796370972
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.161047587
Short name T1163
Test name
Test status
Simulation time 10207797335 ps
CPU time 16.64 seconds
Started Jun 07 08:43:30 PM PDT 24
Finished Jun 07 08:43:48 PM PDT 24
Peak memory 205816 kb
Host smart-600f8775-090e-44c0-b707-eeaf162cb835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16104
7587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.161047587
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.3468254266
Short name T1096
Test name
Test status
Simulation time 10129555334 ps
CPU time 13.11 seconds
Started Jun 07 08:43:31 PM PDT 24
Finished Jun 07 08:43:46 PM PDT 24
Peak memory 205852 kb
Host smart-4598c876-d5a2-43f9-be3c-803c6b372797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34682
54266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3468254266
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.2445530625
Short name T821
Test name
Test status
Simulation time 10056080579 ps
CPU time 13.17 seconds
Started Jun 07 08:43:36 PM PDT 24
Finished Jun 07 08:43:52 PM PDT 24
Peak memory 205848 kb
Host smart-67370635-a4dd-4fc4-8c09-033d1f9e8ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24455
30625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.2445530625
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.1767487909
Short name T670
Test name
Test status
Simulation time 10182713324 ps
CPU time 15.93 seconds
Started Jun 07 08:43:27 PM PDT 24
Finished Jun 07 08:43:45 PM PDT 24
Peak memory 205836 kb
Host smart-394dd47d-b83a-4870-be5d-692676b81841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17674
87909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.1767487909
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.2040115634
Short name T832
Test name
Test status
Simulation time 10075332477 ps
CPU time 15.66 seconds
Started Jun 07 08:43:27 PM PDT 24
Finished Jun 07 08:43:45 PM PDT 24
Peak memory 205832 kb
Host smart-9c3e21e1-c41d-4c27-ab07-35032eb519a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20401
15634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.2040115634
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.3373976969
Short name T872
Test name
Test status
Simulation time 13200131770 ps
CPU time 16.32 seconds
Started Jun 07 08:43:28 PM PDT 24
Finished Jun 07 08:43:46 PM PDT 24
Peak memory 205860 kb
Host smart-d19ff413-7164-481c-b9df-287bb36b1c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33739
76969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.3373976969
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.4194377146
Short name T721
Test name
Test status
Simulation time 10097881642 ps
CPU time 14.1 seconds
Started Jun 07 08:43:25 PM PDT 24
Finished Jun 07 08:43:41 PM PDT 24
Peak memory 205864 kb
Host smart-72a2fe3e-d2fb-421f-8f31-e6fdb6628a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41943
77146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.4194377146
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.1681201385
Short name T1301
Test name
Test status
Simulation time 14726165234 ps
CPU time 138.49 seconds
Started Jun 07 08:43:26 PM PDT 24
Finished Jun 07 08:45:47 PM PDT 24
Peak memory 205732 kb
Host smart-b45b6c1e-e489-47ae-92fa-f000d1e9499f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16812
01385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.1681201385
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.3839841044
Short name T1936
Test name
Test status
Simulation time 10080506541 ps
CPU time 12.68 seconds
Started Jun 07 08:43:28 PM PDT 24
Finished Jun 07 08:43:42 PM PDT 24
Peak memory 205804 kb
Host smart-816bbc58-645a-490e-a13c-1cf291180b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38398
41044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.3839841044
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.3401382040
Short name T79
Test name
Test status
Simulation time 10112955091 ps
CPU time 13.5 seconds
Started Jun 07 08:43:26 PM PDT 24
Finished Jun 07 08:43:41 PM PDT 24
Peak memory 205800 kb
Host smart-79862f9b-766d-48b3-8609-4f6a35fbbe2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34013
82040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.3401382040
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.233767265
Short name T1620
Test name
Test status
Simulation time 10047097108 ps
CPU time 15.68 seconds
Started Jun 07 08:43:29 PM PDT 24
Finished Jun 07 08:43:46 PM PDT 24
Peak memory 205788 kb
Host smart-5b52e25b-eda5-4f80-a4eb-0d0f83267f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23376
7265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.233767265
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.3439252455
Short name T1323
Test name
Test status
Simulation time 10090599929 ps
CPU time 12.76 seconds
Started Jun 07 08:43:27 PM PDT 24
Finished Jun 07 08:43:42 PM PDT 24
Peak memory 205916 kb
Host smart-1bae0dd6-141d-449f-b10d-b77e92ec78ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34392
52455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.3439252455
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1157818552
Short name T1988
Test name
Test status
Simulation time 10085900136 ps
CPU time 15.66 seconds
Started Jun 07 08:43:33 PM PDT 24
Finished Jun 07 08:43:51 PM PDT 24
Peak memory 205824 kb
Host smart-72565f5e-6cd0-4124-ae3c-855f6e3582f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11578
18552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1157818552
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_eop_single_bit_handling.2558491544
Short name T1500
Test name
Test status
Simulation time 10055796076 ps
CPU time 12.64 seconds
Started Jun 07 08:43:33 PM PDT 24
Finished Jun 07 08:43:49 PM PDT 24
Peak memory 205772 kb
Host smart-05b809ef-f223-4ff1-8fd8-ea1ba2d866b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25584
91544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_eop_single_bit_handling.2558491544
Directory /workspace/12.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1068652745
Short name T965
Test name
Test status
Simulation time 10047866351 ps
CPU time 13.04 seconds
Started Jun 07 08:43:27 PM PDT 24
Finished Jun 07 08:43:42 PM PDT 24
Peak memory 205860 kb
Host smart-baa54e9e-9526-4ad9-b647-8766198b7852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10686
52745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1068652745
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.186556050
Short name T908
Test name
Test status
Simulation time 10044484439 ps
CPU time 13.48 seconds
Started Jun 07 08:43:34 PM PDT 24
Finished Jun 07 08:43:51 PM PDT 24
Peak memory 205764 kb
Host smart-486a4427-1731-4cf8-84ec-46c966df6d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18655
6050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.186556050
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.372455373
Short name T1173
Test name
Test status
Simulation time 16729415714 ps
CPU time 25.76 seconds
Started Jun 07 08:43:27 PM PDT 24
Finished Jun 07 08:43:55 PM PDT 24
Peak memory 205780 kb
Host smart-6055cc3a-09c0-4e53-bceb-4f908743c341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37245
5373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.372455373
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.759000305
Short name T2000
Test name
Test status
Simulation time 10095144772 ps
CPU time 15.19 seconds
Started Jun 07 08:43:27 PM PDT 24
Finished Jun 07 08:43:44 PM PDT 24
Peak memory 205916 kb
Host smart-bddd9ca9-d078-4edf-a99e-9e1bec122dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75900
0305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.759000305
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.1376572147
Short name T1856
Test name
Test status
Simulation time 10174791861 ps
CPU time 15.3 seconds
Started Jun 07 08:43:25 PM PDT 24
Finished Jun 07 08:43:43 PM PDT 24
Peak memory 205840 kb
Host smart-5bc913e1-e1f8-4671-9e22-5606d440d5d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13765
72147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1376572147
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.2599260849
Short name T1775
Test name
Test status
Simulation time 10109779726 ps
CPU time 12.57 seconds
Started Jun 07 08:43:25 PM PDT 24
Finished Jun 07 08:43:39 PM PDT 24
Peak memory 205880 kb
Host smart-5a97c477-40dd-45eb-bd3b-9869f76317c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25992
60849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.2599260849
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.705500276
Short name T836
Test name
Test status
Simulation time 10056508843 ps
CPU time 13.97 seconds
Started Jun 07 08:43:26 PM PDT 24
Finished Jun 07 08:43:43 PM PDT 24
Peak memory 205700 kb
Host smart-aae4078b-43a0-4142-9da2-932ea6fcee59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70550
0276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.705500276
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.2882397472
Short name T1517
Test name
Test status
Simulation time 10052662802 ps
CPU time 14.16 seconds
Started Jun 07 08:43:37 PM PDT 24
Finished Jun 07 08:43:54 PM PDT 24
Peak memory 205764 kb
Host smart-6059e5cb-3b6e-410f-98de-ee2f598b6522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28823
97472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.2882397472
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.2527627590
Short name T386
Test name
Test status
Simulation time 10050561538 ps
CPU time 12.5 seconds
Started Jun 07 08:43:33 PM PDT 24
Finished Jun 07 08:43:49 PM PDT 24
Peak memory 205708 kb
Host smart-15ce04d2-2ab8-45ee-8961-c25e69787f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25276
27590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.2527627590
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.909336501
Short name T1660
Test name
Test status
Simulation time 10125882675 ps
CPU time 13.11 seconds
Started Jun 07 08:43:21 PM PDT 24
Finished Jun 07 08:43:37 PM PDT 24
Peak memory 205856 kb
Host smart-85271301-0f8c-45e5-9887-09b4b910f8ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90933
6501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.909336501
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.2206013409
Short name T318
Test name
Test status
Simulation time 10092141241 ps
CPU time 13.15 seconds
Started Jun 07 08:43:30 PM PDT 24
Finished Jun 07 08:43:45 PM PDT 24
Peak memory 205788 kb
Host smart-c4d38a62-1cdf-41b3-90bb-f4ab7ab8c0ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22060
13409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.2206013409
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.526278690
Short name T1649
Test name
Test status
Simulation time 10042692533 ps
CPU time 15.83 seconds
Started Jun 07 08:43:26 PM PDT 24
Finished Jun 07 08:43:44 PM PDT 24
Peak memory 205768 kb
Host smart-b45acaf6-8553-4265-9d7c-f7edf4c29290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52627
8690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.526278690
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.827135255
Short name T1833
Test name
Test status
Simulation time 22041288363 ps
CPU time 354.53 seconds
Started Jun 07 08:43:27 PM PDT 24
Finished Jun 07 08:49:24 PM PDT 24
Peak memory 205776 kb
Host smart-00d3db12-6188-4f8a-a5c1-4dfaffacf181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82713
5255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.827135255
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.2495447361
Short name T1808
Test name
Test status
Simulation time 10159549433 ps
CPU time 13.11 seconds
Started Jun 07 08:43:39 PM PDT 24
Finished Jun 07 08:43:55 PM PDT 24
Peak memory 205752 kb
Host smart-d8da11fc-a9ce-4534-97f0-da6b448aaf70
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2495447361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.2495447361
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.1934338082
Short name T588
Test name
Test status
Simulation time 10081435879 ps
CPU time 13.94 seconds
Started Jun 07 08:43:41 PM PDT 24
Finished Jun 07 08:43:57 PM PDT 24
Peak memory 204988 kb
Host smart-6a824013-2182-4404-ba07-8c89ea8da29c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1934338082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.1934338082
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.211208288
Short name T1261
Test name
Test status
Simulation time 10114521016 ps
CPU time 13.12 seconds
Started Jun 07 08:43:47 PM PDT 24
Finished Jun 07 08:44:03 PM PDT 24
Peak memory 205800 kb
Host smart-722195ac-fe42-4295-afa5-141cc0490116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21120
8288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.211208288
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.406518264
Short name T583
Test name
Test status
Simulation time 13965934312 ps
CPU time 16.16 seconds
Started Jun 07 08:43:35 PM PDT 24
Finished Jun 07 08:43:54 PM PDT 24
Peak memory 205732 kb
Host smart-1064bba8-4cbe-4f52-a111-8153a09c5ae7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=406518264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.406518264
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.3344941001
Short name T1318
Test name
Test status
Simulation time 23260555834 ps
CPU time 29.02 seconds
Started Jun 07 08:43:37 PM PDT 24
Finished Jun 07 08:44:09 PM PDT 24
Peak memory 205836 kb
Host smart-0c860567-eabe-4063-bce9-8267a8f176eb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3344941001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.3344941001
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.2153128349
Short name T1631
Test name
Test status
Simulation time 10057215980 ps
CPU time 16.31 seconds
Started Jun 07 08:43:34 PM PDT 24
Finished Jun 07 08:43:53 PM PDT 24
Peak memory 205844 kb
Host smart-5dc3eb1c-3685-476a-b635-4c3dbe63020a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21531
28349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2153128349
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.3846789976
Short name T1256
Test name
Test status
Simulation time 10097370582 ps
CPU time 13.83 seconds
Started Jun 07 08:43:38 PM PDT 24
Finished Jun 07 08:43:54 PM PDT 24
Peak memory 205816 kb
Host smart-b528186b-b114-4f6e-9462-9d1e14603c44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38467
89976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.3846789976
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.816903071
Short name T1948
Test name
Test status
Simulation time 10240634483 ps
CPU time 13.33 seconds
Started Jun 07 08:43:33 PM PDT 24
Finished Jun 07 08:43:49 PM PDT 24
Peak memory 205768 kb
Host smart-5e49ddaf-37df-4a88-9251-38dd8212ee6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81690
3071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.816903071
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.1195145861
Short name T397
Test name
Test status
Simulation time 10052728999 ps
CPU time 13.26 seconds
Started Jun 07 08:43:31 PM PDT 24
Finished Jun 07 08:43:46 PM PDT 24
Peak memory 205928 kb
Host smart-3a73a459-6589-4501-8ac9-1189929e2c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11951
45861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.1195145861
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.3331247726
Short name T305
Test name
Test status
Simulation time 10046278413 ps
CPU time 13.79 seconds
Started Jun 07 08:43:34 PM PDT 24
Finished Jun 07 08:43:51 PM PDT 24
Peak memory 205804 kb
Host smart-71d3c41b-1eec-47b8-94cf-2e93b8c8d088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33312
47726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.3331247726
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.130814271
Short name T634
Test name
Test status
Simulation time 10736270643 ps
CPU time 16.81 seconds
Started Jun 07 08:43:33 PM PDT 24
Finished Jun 07 08:43:53 PM PDT 24
Peak memory 205876 kb
Host smart-eb4926a5-e847-4d9d-a15c-35253790a697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13081
4271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.130814271
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2712495977
Short name T343
Test name
Test status
Simulation time 10205200622 ps
CPU time 15.28 seconds
Started Jun 07 08:43:32 PM PDT 24
Finished Jun 07 08:43:50 PM PDT 24
Peak memory 205820 kb
Host smart-a1fb1f0c-af30-49af-affa-5a7eeadf58c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27124
95977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2712495977
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.2579690400
Short name T1091
Test name
Test status
Simulation time 10191653839 ps
CPU time 15.26 seconds
Started Jun 07 08:43:48 PM PDT 24
Finished Jun 07 08:44:06 PM PDT 24
Peak memory 205192 kb
Host smart-f97d8a18-fe4a-4010-984b-112d2e73c825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25796
90400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.2579690400
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.238036962
Short name T1292
Test name
Test status
Simulation time 10057806187 ps
CPU time 13.53 seconds
Started Jun 07 08:43:41 PM PDT 24
Finished Jun 07 08:43:57 PM PDT 24
Peak memory 205868 kb
Host smart-e54025b6-173d-4676-b763-d485d5af7481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23803
6962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.238036962
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.2236815340
Short name T753
Test name
Test status
Simulation time 10154227178 ps
CPU time 16 seconds
Started Jun 07 08:43:37 PM PDT 24
Finished Jun 07 08:43:56 PM PDT 24
Peak memory 205808 kb
Host smart-7bf491d0-2af3-480a-a587-606994804a99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22368
15340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.2236815340
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.2587970160
Short name T1240
Test name
Test status
Simulation time 10107968038 ps
CPU time 15.49 seconds
Started Jun 07 08:43:33 PM PDT 24
Finished Jun 07 08:43:52 PM PDT 24
Peak memory 205684 kb
Host smart-4dd39b46-022b-4d4b-a257-b42de31e3462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25879
70160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.2587970160
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.3513897476
Short name T1891
Test name
Test status
Simulation time 13244769151 ps
CPU time 18.07 seconds
Started Jun 07 08:43:33 PM PDT 24
Finished Jun 07 08:43:54 PM PDT 24
Peak memory 205812 kb
Host smart-f4aaee21-076a-4a51-9fc4-2ce76a716a58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35138
97476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.3513897476
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.1715054629
Short name T337
Test name
Test status
Simulation time 10096377334 ps
CPU time 13.5 seconds
Started Jun 07 08:43:33 PM PDT 24
Finished Jun 07 08:43:50 PM PDT 24
Peak memory 205824 kb
Host smart-d8fc659d-a023-4a61-acee-a450a376303f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17150
54629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.1715054629
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.1672554529
Short name T594
Test name
Test status
Simulation time 22354420417 ps
CPU time 126.22 seconds
Started Jun 07 08:43:36 PM PDT 24
Finished Jun 07 08:45:45 PM PDT 24
Peak memory 205888 kb
Host smart-887a2f6b-7ec8-43af-b127-9750335c61cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16725
54529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.1672554529
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.401175587
Short name T414
Test name
Test status
Simulation time 10042448961 ps
CPU time 12.57 seconds
Started Jun 07 08:43:35 PM PDT 24
Finished Jun 07 08:43:50 PM PDT 24
Peak memory 205852 kb
Host smart-c9b46874-e592-4f6f-bf2b-4a30b5ad5559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40117
5587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.401175587
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.652376688
Short name T472
Test name
Test status
Simulation time 10062168007 ps
CPU time 12.61 seconds
Started Jun 07 08:43:43 PM PDT 24
Finished Jun 07 08:43:58 PM PDT 24
Peak memory 205800 kb
Host smart-8f40b6f7-4acf-40d1-ac48-a067ee09aa47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65237
6688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.652376688
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.3957329154
Short name T991
Test name
Test status
Simulation time 10155951629 ps
CPU time 12.67 seconds
Started Jun 07 08:43:44 PM PDT 24
Finished Jun 07 08:43:58 PM PDT 24
Peak memory 205880 kb
Host smart-fc66fd20-fc0b-4e62-babc-b5ab5df03fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39573
29154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3957329154
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.4239102973
Short name T1646
Test name
Test status
Simulation time 10111410589 ps
CPU time 13.45 seconds
Started Jun 07 08:43:48 PM PDT 24
Finished Jun 07 08:44:04 PM PDT 24
Peak memory 205216 kb
Host smart-e1590ea8-f726-4fc7-b611-85aa41a5edde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42391
02973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.4239102973
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.3937900565
Short name T1569
Test name
Test status
Simulation time 10059414228 ps
CPU time 13.69 seconds
Started Jun 07 08:43:46 PM PDT 24
Finished Jun 07 08:44:02 PM PDT 24
Peak memory 205832 kb
Host smart-58d16c2c-e17b-4045-a842-0c9ba4f494d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39379
00565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.3937900565
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_eop_single_bit_handling.1257388929
Short name T1879
Test name
Test status
Simulation time 10109298534 ps
CPU time 13.42 seconds
Started Jun 07 08:43:41 PM PDT 24
Finished Jun 07 08:43:57 PM PDT 24
Peak memory 205912 kb
Host smart-31af33c1-6ffe-433d-9b8f-140b48dd93ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12573
88929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_eop_single_bit_handling.1257388929
Directory /workspace/13.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.3695976814
Short name T1712
Test name
Test status
Simulation time 10035443102 ps
CPU time 12.7 seconds
Started Jun 07 08:43:39 PM PDT 24
Finished Jun 07 08:43:55 PM PDT 24
Peak memory 205920 kb
Host smart-c55c30d6-6aae-45da-9670-12863dbf7dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36959
76814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.3695976814
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.378765589
Short name T85
Test name
Test status
Simulation time 24187630188 ps
CPU time 42.64 seconds
Started Jun 07 08:43:41 PM PDT 24
Finished Jun 07 08:44:26 PM PDT 24
Peak memory 205024 kb
Host smart-6c4250d3-ab33-4adb-bde7-f35394482a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37876
5589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.378765589
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.3555168960
Short name T1231
Test name
Test status
Simulation time 10085444771 ps
CPU time 16.35 seconds
Started Jun 07 08:43:40 PM PDT 24
Finished Jun 07 08:43:59 PM PDT 24
Peak memory 205884 kb
Host smart-44060801-562f-40a4-a8bf-e2681039a467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35551
68960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.3555168960
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3057905083
Short name T1872
Test name
Test status
Simulation time 10107418029 ps
CPU time 12.64 seconds
Started Jun 07 08:43:42 PM PDT 24
Finished Jun 07 08:43:57 PM PDT 24
Peak memory 205776 kb
Host smart-737f914c-f699-440c-95fb-d7c70b294f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30579
05083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3057905083
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.3948411254
Short name T550
Test name
Test status
Simulation time 10056211737 ps
CPU time 14.23 seconds
Started Jun 07 08:43:38 PM PDT 24
Finished Jun 07 08:43:55 PM PDT 24
Peak memory 205768 kb
Host smart-70a51dc2-bb13-422c-98ef-58d7792740a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39484
11254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.3948411254
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.688475766
Short name T1528
Test name
Test status
Simulation time 10069981227 ps
CPU time 15.08 seconds
Started Jun 07 08:43:39 PM PDT 24
Finished Jun 07 08:43:56 PM PDT 24
Peak memory 205740 kb
Host smart-107946ea-d6d7-4898-8ff9-a0b239d93010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68847
5766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.688475766
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.1287136805
Short name T1651
Test name
Test status
Simulation time 10056199615 ps
CPU time 13.2 seconds
Started Jun 07 08:43:38 PM PDT 24
Finished Jun 07 08:43:54 PM PDT 24
Peak memory 205772 kb
Host smart-e60efdc9-e6cd-4483-8833-610984dec812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12871
36805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.1287136805
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.2164567136
Short name T155
Test name
Test status
Simulation time 10093171156 ps
CPU time 13.71 seconds
Started Jun 07 08:43:36 PM PDT 24
Finished Jun 07 08:43:53 PM PDT 24
Peak memory 205808 kb
Host smart-d39ec60c-7715-4996-9a57-26c37a4dfe0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21645
67136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.2164567136
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.3843264723
Short name T2024
Test name
Test status
Simulation time 10102437443 ps
CPU time 13.59 seconds
Started Jun 07 08:43:40 PM PDT 24
Finished Jun 07 08:43:56 PM PDT 24
Peak memory 205820 kb
Host smart-06ece8d3-5b55-4f4a-b14f-81ccb0ea6a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38432
64723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.3843264723
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.610346210
Short name T1219
Test name
Test status
Simulation time 10087155895 ps
CPU time 12.72 seconds
Started Jun 07 08:43:42 PM PDT 24
Finished Jun 07 08:43:57 PM PDT 24
Peak memory 205864 kb
Host smart-041caa68-f953-46b5-a406-5cb55b178210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61034
6210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.610346210
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.971385317
Short name T874
Test name
Test status
Simulation time 15268506838 ps
CPU time 62.59 seconds
Started Jun 07 08:43:40 PM PDT 24
Finished Jun 07 08:44:45 PM PDT 24
Peak memory 205876 kb
Host smart-ad5d9402-49c8-4320-aa5d-35002992ab07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97138
5317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.971385317
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.672168563
Short name T1939
Test name
Test status
Simulation time 10180257304 ps
CPU time 14 seconds
Started Jun 07 08:44:01 PM PDT 24
Finished Jun 07 08:44:16 PM PDT 24
Peak memory 205884 kb
Host smart-855f06d9-45d6-4ba4-be8c-18f931d7f48e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=672168563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.672168563
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.4217620467
Short name T818
Test name
Test status
Simulation time 10057874628 ps
CPU time 15.25 seconds
Started Jun 07 08:44:23 PM PDT 24
Finished Jun 07 08:44:41 PM PDT 24
Peak memory 205788 kb
Host smart-c7702d0b-9446-492d-a32c-5bcc173a436b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4217620467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.4217620467
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.643896203
Short name T1522
Test name
Test status
Simulation time 10122861698 ps
CPU time 15.25 seconds
Started Jun 07 08:43:51 PM PDT 24
Finished Jun 07 08:44:09 PM PDT 24
Peak memory 205696 kb
Host smart-0a11c796-f0f8-49e8-b822-701740174a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64389
6203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.643896203
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.1874674265
Short name T1802
Test name
Test status
Simulation time 14059391089 ps
CPU time 17.27 seconds
Started Jun 07 08:43:41 PM PDT 24
Finished Jun 07 08:44:01 PM PDT 24
Peak memory 205820 kb
Host smart-5581a33d-822d-473a-9528-7bca8d1ae9c0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1874674265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.1874674265
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.3953122240
Short name T1889
Test name
Test status
Simulation time 23283311216 ps
CPU time 24.52 seconds
Started Jun 07 08:43:47 PM PDT 24
Finished Jun 07 08:44:14 PM PDT 24
Peak memory 205856 kb
Host smart-02edeba7-071b-4ff8-8718-ef0d21776df5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3953122240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.3953122240
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.1107205658
Short name T363
Test name
Test status
Simulation time 10051771034 ps
CPU time 12.85 seconds
Started Jun 07 08:43:44 PM PDT 24
Finished Jun 07 08:43:59 PM PDT 24
Peak memory 205768 kb
Host smart-1be5688f-ba27-42f0-adf0-bcaaa1cb27df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11072
05658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.1107205658
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.3449406279
Short name T1655
Test name
Test status
Simulation time 10429631821 ps
CPU time 13.6 seconds
Started Jun 07 08:43:49 PM PDT 24
Finished Jun 07 08:44:06 PM PDT 24
Peak memory 205808 kb
Host smart-f3081db9-ba22-4764-acc8-eee14601b0f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34494
06279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.3449406279
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.2716779843
Short name T1481
Test name
Test status
Simulation time 10038851458 ps
CPU time 15.49 seconds
Started Jun 07 08:43:45 PM PDT 24
Finished Jun 07 08:44:03 PM PDT 24
Peak memory 205816 kb
Host smart-c37c073b-6070-4122-a00a-87b787ea506b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27167
79843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.2716779843
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.2281033753
Short name T2028
Test name
Test status
Simulation time 10059360625 ps
CPU time 12.85 seconds
Started Jun 07 08:43:47 PM PDT 24
Finished Jun 07 08:44:03 PM PDT 24
Peak memory 205760 kb
Host smart-2c9174c2-86ba-4909-99cb-d0ec85680766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22810
33753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.2281033753
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.3176941300
Short name T825
Test name
Test status
Simulation time 10879508110 ps
CPU time 15.13 seconds
Started Jun 07 08:43:47 PM PDT 24
Finished Jun 07 08:44:05 PM PDT 24
Peak memory 205864 kb
Host smart-e15dc64b-a404-4b53-a3f6-14896afcb233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31769
41300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.3176941300
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.4071988116
Short name T417
Test name
Test status
Simulation time 10249276094 ps
CPU time 15.18 seconds
Started Jun 07 08:43:46 PM PDT 24
Finished Jun 07 08:44:04 PM PDT 24
Peak memory 205736 kb
Host smart-60b03af0-6276-4884-8690-cbde1b0ff106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40719
88116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.4071988116
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.2410382464
Short name T937
Test name
Test status
Simulation time 10111048916 ps
CPU time 14.48 seconds
Started Jun 07 08:43:54 PM PDT 24
Finished Jun 07 08:44:10 PM PDT 24
Peak memory 205772 kb
Host smart-643b0b55-2a97-4aab-91bc-cf51bfe3190c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24103
82464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.2410382464
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3692118396
Short name T1470
Test name
Test status
Simulation time 10081152578 ps
CPU time 13.56 seconds
Started Jun 07 08:44:01 PM PDT 24
Finished Jun 07 08:44:16 PM PDT 24
Peak memory 205844 kb
Host smart-16bade57-0c02-48bd-b533-d4946411806d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36921
18396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3692118396
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.108097768
Short name T1431
Test name
Test status
Simulation time 10150318067 ps
CPU time 14.19 seconds
Started Jun 07 08:43:49 PM PDT 24
Finished Jun 07 08:44:06 PM PDT 24
Peak memory 205868 kb
Host smart-c874dda2-266c-4a2a-986f-bed255828be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10809
7768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.108097768
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.3164529976
Short name T1995
Test name
Test status
Simulation time 10099782236 ps
CPU time 13.45 seconds
Started Jun 07 08:43:47 PM PDT 24
Finished Jun 07 08:44:04 PM PDT 24
Peak memory 205836 kb
Host smart-25f557bc-26a0-4e13-9739-9962c9a3fa58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31645
29976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.3164529976
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.1733542211
Short name T200
Test name
Test status
Simulation time 13172052581 ps
CPU time 19.41 seconds
Started Jun 07 08:43:45 PM PDT 24
Finished Jun 07 08:44:07 PM PDT 24
Peak memory 205748 kb
Host smart-3172f3e0-5f45-4e47-a03b-9d0b7c9aa35c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17335
42211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.1733542211
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.427124283
Short name T1668
Test name
Test status
Simulation time 10091351936 ps
CPU time 13.5 seconds
Started Jun 07 08:43:47 PM PDT 24
Finished Jun 07 08:44:03 PM PDT 24
Peak memory 205876 kb
Host smart-95c2aef2-164d-45d3-bdb1-0fbc743a8ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42712
4283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.427124283
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.313211187
Short name T960
Test name
Test status
Simulation time 20033300699 ps
CPU time 102.66 seconds
Started Jun 07 08:43:46 PM PDT 24
Finished Jun 07 08:45:30 PM PDT 24
Peak memory 205848 kb
Host smart-9c9a8b5c-9675-4b7b-842f-42e2e9a10fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31321
1187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.313211187
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.2463454734
Short name T329
Test name
Test status
Simulation time 10045237337 ps
CPU time 14.09 seconds
Started Jun 07 08:43:47 PM PDT 24
Finished Jun 07 08:44:04 PM PDT 24
Peak memory 205792 kb
Host smart-aaf5d1e2-293e-43a0-961e-d9fa0a733227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24634
54734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.2463454734
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.2313380505
Short name T102
Test name
Test status
Simulation time 10111854367 ps
CPU time 13.3 seconds
Started Jun 07 08:43:46 PM PDT 24
Finished Jun 07 08:44:01 PM PDT 24
Peak memory 205888 kb
Host smart-2fe9adb7-74bf-4ed9-b680-f6daa7e59f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23133
80505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.2313380505
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.2095250453
Short name T806
Test name
Test status
Simulation time 10085957739 ps
CPU time 12.96 seconds
Started Jun 07 08:43:46 PM PDT 24
Finished Jun 07 08:44:01 PM PDT 24
Peak memory 205864 kb
Host smart-c788426e-67b1-4246-b4e8-21c7391f1f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20952
50453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.2095250453
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.390190297
Short name T1180
Test name
Test status
Simulation time 10056440056 ps
CPU time 13.58 seconds
Started Jun 07 08:43:46 PM PDT 24
Finished Jun 07 08:44:02 PM PDT 24
Peak memory 205856 kb
Host smart-b6204c21-d51a-4616-b607-f796735a89a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39019
0297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.390190297
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2576418065
Short name T1172
Test name
Test status
Simulation time 10094858759 ps
CPU time 16.45 seconds
Started Jun 07 08:43:46 PM PDT 24
Finished Jun 07 08:44:05 PM PDT 24
Peak memory 205924 kb
Host smart-25fc0011-ca40-41f1-8a11-07ee1785a7bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25764
18065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2576418065
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.3024134876
Short name T1628
Test name
Test status
Simulation time 10053846061 ps
CPU time 13.27 seconds
Started Jun 07 08:43:47 PM PDT 24
Finished Jun 07 08:44:03 PM PDT 24
Peak memory 205752 kb
Host smart-46ee0427-6bc1-4065-9c11-9b50885fca1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30241
34876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.3024134876
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_eop_single_bit_handling.4247440149
Short name T1060
Test name
Test status
Simulation time 10060369703 ps
CPU time 13.09 seconds
Started Jun 07 08:43:47 PM PDT 24
Finished Jun 07 08:44:02 PM PDT 24
Peak memory 205888 kb
Host smart-ef13d41d-a215-4b6f-9820-c2212d43963e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42474
40149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_eop_single_bit_handling.4247440149
Directory /workspace/14.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.1211503097
Short name T877
Test name
Test status
Simulation time 10051444454 ps
CPU time 13.04 seconds
Started Jun 07 08:43:47 PM PDT 24
Finished Jun 07 08:44:02 PM PDT 24
Peak memory 205808 kb
Host smart-8f2b6e26-58b9-4bfe-b7d3-fbf82c354276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12115
03097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.1211503097
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3365637622
Short name T1234
Test name
Test status
Simulation time 10038217577 ps
CPU time 12.31 seconds
Started Jun 07 08:43:53 PM PDT 24
Finished Jun 07 08:44:07 PM PDT 24
Peak memory 205788 kb
Host smart-93c00460-227f-4b15-8cac-3073b4c34e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33656
37622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3365637622
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.4109886517
Short name T1835
Test name
Test status
Simulation time 27134435412 ps
CPU time 48.34 seconds
Started Jun 07 08:43:46 PM PDT 24
Finished Jun 07 08:44:37 PM PDT 24
Peak memory 205792 kb
Host smart-709268d0-18d7-4f36-afbb-4e98bc1234ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41098
86517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.4109886517
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3607361148
Short name T1544
Test name
Test status
Simulation time 10079362763 ps
CPU time 14.06 seconds
Started Jun 07 08:43:48 PM PDT 24
Finished Jun 07 08:44:05 PM PDT 24
Peak memory 205776 kb
Host smart-7c13e65d-35a2-446b-aafd-e5475615a2e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36073
61148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3607361148
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.3344428218
Short name T664
Test name
Test status
Simulation time 10136584054 ps
CPU time 12.99 seconds
Started Jun 07 08:43:45 PM PDT 24
Finished Jun 07 08:44:00 PM PDT 24
Peak memory 205840 kb
Host smart-8396edd3-06dd-4d8e-b6c2-d0c79e39c61f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33444
28218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.3344428218
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.1460003008
Short name T1085
Test name
Test status
Simulation time 10057446034 ps
CPU time 13.17 seconds
Started Jun 07 08:43:46 PM PDT 24
Finished Jun 07 08:44:01 PM PDT 24
Peak memory 205768 kb
Host smart-f3f214c2-b1ec-434a-a0a3-400d56b7b2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14600
03008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.1460003008
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.3513620083
Short name T1897
Test name
Test status
Simulation time 10057456046 ps
CPU time 12.92 seconds
Started Jun 07 08:43:47 PM PDT 24
Finished Jun 07 08:44:02 PM PDT 24
Peak memory 205800 kb
Host smart-52aaf31b-1135-4a24-9daa-3b2dfa51281e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35136
20083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.3513620083
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.946841924
Short name T1485
Test name
Test status
Simulation time 10082473674 ps
CPU time 12.92 seconds
Started Jun 07 08:43:48 PM PDT 24
Finished Jun 07 08:44:04 PM PDT 24
Peak memory 205776 kb
Host smart-81e6d721-619d-4626-96a1-39e2360ef496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94684
1924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.946841924
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.605031666
Short name T580
Test name
Test status
Simulation time 10054845596 ps
CPU time 15.31 seconds
Started Jun 07 08:43:49 PM PDT 24
Finished Jun 07 08:44:07 PM PDT 24
Peak memory 205828 kb
Host smart-4be65a1e-8182-49ba-b10e-63008505083b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60503
1666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.605031666
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1506664750
Short name T1193
Test name
Test status
Simulation time 10129761484 ps
CPU time 13.79 seconds
Started Jun 07 08:43:38 PM PDT 24
Finished Jun 07 08:43:54 PM PDT 24
Peak memory 205768 kb
Host smart-3a6e1332-f220-4922-9284-d2b5572dc981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15066
64750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1506664750
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.3279924653
Short name T1400
Test name
Test status
Simulation time 10068920584 ps
CPU time 15.39 seconds
Started Jun 07 08:43:48 PM PDT 24
Finished Jun 07 08:44:06 PM PDT 24
Peak memory 205788 kb
Host smart-6c2c51da-9818-4a35-b595-bd7639ad9e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32799
24653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.3279924653
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.2012410420
Short name T1790
Test name
Test status
Simulation time 10093820285 ps
CPU time 12.55 seconds
Started Jun 07 08:43:47 PM PDT 24
Finished Jun 07 08:44:03 PM PDT 24
Peak memory 205852 kb
Host smart-ae3f72b7-82bb-40ba-9c4b-4dfa73a959b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20124
10420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.2012410420
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.147525910
Short name T1354
Test name
Test status
Simulation time 18932264060 ps
CPU time 262.48 seconds
Started Jun 07 08:43:48 PM PDT 24
Finished Jun 07 08:48:13 PM PDT 24
Peak memory 205740 kb
Host smart-b8378fc4-e2ca-492b-b3dd-14eb89b9b893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14752
5910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.147525910
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.2355085907
Short name T1640
Test name
Test status
Simulation time 10153383728 ps
CPU time 13.28 seconds
Started Jun 07 08:44:04 PM PDT 24
Finished Jun 07 08:44:19 PM PDT 24
Peak memory 205792 kb
Host smart-6f2a22e0-ee4a-4cb6-a0ab-9b9ff23706c8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2355085907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.2355085907
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.1850972830
Short name T1156
Test name
Test status
Simulation time 10060867343 ps
CPU time 13.7 seconds
Started Jun 07 08:44:04 PM PDT 24
Finished Jun 07 08:44:20 PM PDT 24
Peak memory 205856 kb
Host smart-2a65a604-e319-4586-97e8-8233f6d6ac76
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1850972830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.1850972830
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.2470334357
Short name T1670
Test name
Test status
Simulation time 10129779681 ps
CPU time 14.96 seconds
Started Jun 07 08:44:05 PM PDT 24
Finished Jun 07 08:44:22 PM PDT 24
Peak memory 205888 kb
Host smart-ac764cfa-d178-4623-8c07-9b18061f2d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24703
34357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.2470334357
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.3519953416
Short name T1493
Test name
Test status
Simulation time 13771635967 ps
CPU time 17.93 seconds
Started Jun 07 08:43:51 PM PDT 24
Finished Jun 07 08:44:12 PM PDT 24
Peak memory 205864 kb
Host smart-3c4f82f6-c5ed-4d44-8cb8-4c3419ba4769
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3519953416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.3519953416
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.979164877
Short name T405
Test name
Test status
Simulation time 23349519349 ps
CPU time 26.28 seconds
Started Jun 07 08:43:52 PM PDT 24
Finished Jun 07 08:44:20 PM PDT 24
Peak memory 205972 kb
Host smart-0bfcd162-587a-4718-839a-3d58af055894
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=979164877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.979164877
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.799838362
Short name T364
Test name
Test status
Simulation time 10059013268 ps
CPU time 14.65 seconds
Started Jun 07 08:44:01 PM PDT 24
Finished Jun 07 08:44:17 PM PDT 24
Peak memory 205876 kb
Host smart-747fa56b-3748-431f-94ae-6ff2c165a7a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79983
8362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.799838362
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.3817694889
Short name T1409
Test name
Test status
Simulation time 10047113707 ps
CPU time 12.42 seconds
Started Jun 07 08:43:57 PM PDT 24
Finished Jun 07 08:44:12 PM PDT 24
Peak memory 205888 kb
Host smart-1a0b5472-078b-411d-aa30-61935fddf883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38176
94889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.3817694889
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.3672037565
Short name T1362
Test name
Test status
Simulation time 10063329215 ps
CPU time 14.21 seconds
Started Jun 07 08:43:55 PM PDT 24
Finished Jun 07 08:44:11 PM PDT 24
Peak memory 205756 kb
Host smart-0ff9d588-a227-484d-8b24-b4637781ed64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36720
37565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.3672037565
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.1846793787
Short name T697
Test name
Test status
Simulation time 10786307100 ps
CPU time 14.57 seconds
Started Jun 07 08:43:52 PM PDT 24
Finished Jun 07 08:44:08 PM PDT 24
Peak memory 205848 kb
Host smart-1a169a12-616b-45d0-81ed-8d9546767844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18467
93787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.1846793787
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.3126432346
Short name T1901
Test name
Test status
Simulation time 10112375294 ps
CPU time 14.85 seconds
Started Jun 07 08:43:52 PM PDT 24
Finished Jun 07 08:44:09 PM PDT 24
Peak memory 205824 kb
Host smart-a067e115-d8e6-4739-b0cb-25fe20354f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31264
32346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.3126432346
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.3310044111
Short name T766
Test name
Test status
Simulation time 10133801949 ps
CPU time 13.23 seconds
Started Jun 07 08:43:57 PM PDT 24
Finished Jun 07 08:44:13 PM PDT 24
Peak memory 205780 kb
Host smart-fae23d1b-62c1-4584-b6ff-dca6a43aaafe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33100
44111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.3310044111
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.715824976
Short name T1001
Test name
Test status
Simulation time 10051150967 ps
CPU time 12.7 seconds
Started Jun 07 08:43:57 PM PDT 24
Finished Jun 07 08:44:12 PM PDT 24
Peak memory 205836 kb
Host smart-fc9dd133-748e-48d7-87d8-c575ac5de7ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71582
4976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.715824976
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2755136828
Short name T1627
Test name
Test status
Simulation time 10155931614 ps
CPU time 12.82 seconds
Started Jun 07 08:43:50 PM PDT 24
Finished Jun 07 08:44:06 PM PDT 24
Peak memory 205724 kb
Host smart-c6731ebc-d8b9-4535-b9ff-9ab8b559bd59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27551
36828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2755136828
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.3569687297
Short name T1694
Test name
Test status
Simulation time 10084299545 ps
CPU time 14.17 seconds
Started Jun 07 08:43:56 PM PDT 24
Finished Jun 07 08:44:13 PM PDT 24
Peak memory 205756 kb
Host smart-74317c23-f188-4d48-bb34-871a214df420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35696
87297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.3569687297
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.2182727636
Short name T1741
Test name
Test status
Simulation time 13175185650 ps
CPU time 17.91 seconds
Started Jun 07 08:44:06 PM PDT 24
Finished Jun 07 08:44:26 PM PDT 24
Peak memory 205736 kb
Host smart-5c56931e-5755-4fdf-9a3b-993fedf86449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21827
27636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.2182727636
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.2183550294
Short name T954
Test name
Test status
Simulation time 10088590207 ps
CPU time 13.73 seconds
Started Jun 07 08:43:57 PM PDT 24
Finished Jun 07 08:44:13 PM PDT 24
Peak memory 205780 kb
Host smart-0c06b9df-5f46-4366-a0bb-1f89ccd9dde7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21835
50294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.2183550294
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.965317914
Short name T699
Test name
Test status
Simulation time 14266149075 ps
CPU time 57.29 seconds
Started Jun 07 08:43:58 PM PDT 24
Finished Jun 07 08:44:57 PM PDT 24
Peak memory 205836 kb
Host smart-167b2822-5777-4c80-a14d-aa40e1ab4c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96531
7914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.965317914
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3724613018
Short name T520
Test name
Test status
Simulation time 10051215195 ps
CPU time 13.21 seconds
Started Jun 07 08:43:59 PM PDT 24
Finished Jun 07 08:44:14 PM PDT 24
Peak memory 205792 kb
Host smart-8afc844c-482e-400a-91c2-31707584acdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37246
13018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3724613018
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.804518438
Short name T1663
Test name
Test status
Simulation time 10102356916 ps
CPU time 13.48 seconds
Started Jun 07 08:44:00 PM PDT 24
Finished Jun 07 08:44:16 PM PDT 24
Peak memory 205820 kb
Host smart-76224c9d-2830-4f37-9949-29c5f9024886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80451
8438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.804518438
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1571184178
Short name T1702
Test name
Test status
Simulation time 10076393901 ps
CPU time 13.33 seconds
Started Jun 07 08:43:59 PM PDT 24
Finished Jun 07 08:44:14 PM PDT 24
Peak memory 205784 kb
Host smart-9d4e652d-58c9-4788-ae59-c4d47863dd1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15711
84178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1571184178
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3877134747
Short name T792
Test name
Test status
Simulation time 10079672300 ps
CPU time 12.69 seconds
Started Jun 07 08:43:59 PM PDT 24
Finished Jun 07 08:44:13 PM PDT 24
Peak memory 205824 kb
Host smart-bdcdc931-b504-4208-9242-92473dc68f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38771
34747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3877134747
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.3647227731
Short name T148
Test name
Test status
Simulation time 10057748616 ps
CPU time 14.15 seconds
Started Jun 07 08:44:03 PM PDT 24
Finished Jun 07 08:44:19 PM PDT 24
Peak memory 205880 kb
Host smart-3cf85049-c234-4210-9c55-895334d4cb37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36472
27731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.3647227731
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_eop_single_bit_handling.1360636431
Short name T24
Test name
Test status
Simulation time 10133510039 ps
CPU time 13.66 seconds
Started Jun 07 08:43:57 PM PDT 24
Finished Jun 07 08:44:13 PM PDT 24
Peak memory 205816 kb
Host smart-e7d27d07-e4d2-4b30-874a-776be69c3db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13606
36431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_eop_single_bit_handling.1360636431
Directory /workspace/15.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.2605059163
Short name T319
Test name
Test status
Simulation time 10038910554 ps
CPU time 15.86 seconds
Started Jun 07 08:43:58 PM PDT 24
Finished Jun 07 08:44:16 PM PDT 24
Peak memory 205852 kb
Host smart-62ac4b74-bc07-47e6-b767-7af07f158780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26050
59163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.2605059163
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.157961392
Short name T1756
Test name
Test status
Simulation time 10047133086 ps
CPU time 13.25 seconds
Started Jun 07 08:43:57 PM PDT 24
Finished Jun 07 08:44:12 PM PDT 24
Peak memory 205664 kb
Host smart-2aa6e38b-f803-46fc-b949-54ce0f66a900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15796
1392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.157961392
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.3225954936
Short name T234
Test name
Test status
Simulation time 31849686486 ps
CPU time 58.7 seconds
Started Jun 07 08:43:59 PM PDT 24
Finished Jun 07 08:44:59 PM PDT 24
Peak memory 205780 kb
Host smart-3988d5e3-6228-4ecb-8178-8c0ad2fcbedc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32259
54936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.3225954936
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.293541246
Short name T1102
Test name
Test status
Simulation time 10074893630 ps
CPU time 17.36 seconds
Started Jun 07 08:43:59 PM PDT 24
Finished Jun 07 08:44:18 PM PDT 24
Peak memory 205856 kb
Host smart-24cb3342-4e2d-489e-bb52-a3c564a89851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29354
1246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.293541246
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.2584829671
Short name T1686
Test name
Test status
Simulation time 10141010892 ps
CPU time 13.09 seconds
Started Jun 07 08:43:58 PM PDT 24
Finished Jun 07 08:44:13 PM PDT 24
Peak memory 205840 kb
Host smart-84b03fb2-cc90-453c-b6c7-af6cba23449e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25848
29671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2584829671
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.3033236495
Short name T1407
Test name
Test status
Simulation time 10129960607 ps
CPU time 14.79 seconds
Started Jun 07 08:43:57 PM PDT 24
Finished Jun 07 08:44:14 PM PDT 24
Peak memory 205756 kb
Host smart-bbdaeba7-fd6f-41d4-982e-be6467f39a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30332
36495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.3033236495
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.2066106890
Short name T1030
Test name
Test status
Simulation time 10040195460 ps
CPU time 12.98 seconds
Started Jun 07 08:43:59 PM PDT 24
Finished Jun 07 08:44:14 PM PDT 24
Peak memory 205732 kb
Host smart-bb54dc4e-83df-49e8-af08-56d7b12498b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20661
06890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.2066106890
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2259792269
Short name T568
Test name
Test status
Simulation time 10058582181 ps
CPU time 14.63 seconds
Started Jun 07 08:43:59 PM PDT 24
Finished Jun 07 08:44:15 PM PDT 24
Peak memory 205772 kb
Host smart-273c0169-471d-4f30-91d4-a3d8beb8ebd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22597
92269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2259792269
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.3418364394
Short name T402
Test name
Test status
Simulation time 10041561466 ps
CPU time 14.38 seconds
Started Jun 07 08:43:59 PM PDT 24
Finished Jun 07 08:44:16 PM PDT 24
Peak memory 205760 kb
Host smart-65bad89a-cd14-4271-8f9d-695b8c38d0c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34183
64394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.3418364394
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3470913364
Short name T146
Test name
Test status
Simulation time 10126184094 ps
CPU time 13.13 seconds
Started Jun 07 08:43:52 PM PDT 24
Finished Jun 07 08:44:07 PM PDT 24
Peak memory 205744 kb
Host smart-484efcc3-2175-470c-b2a2-8187c5392c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34709
13364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3470913364
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1883785228
Short name T379
Test name
Test status
Simulation time 10095048998 ps
CPU time 13.03 seconds
Started Jun 07 08:44:06 PM PDT 24
Finished Jun 07 08:44:21 PM PDT 24
Peak memory 205800 kb
Host smart-40cf81c0-44d0-4b57-8bdc-007391bb85f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18837
85228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1883785228
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.4016965027
Short name T1599
Test name
Test status
Simulation time 10076273316 ps
CPU time 14.46 seconds
Started Jun 07 08:43:59 PM PDT 24
Finished Jun 07 08:44:16 PM PDT 24
Peak memory 205908 kb
Host smart-35b87ac5-216a-4bb9-899b-6f66d055e4d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40169
65027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.4016965027
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.302347474
Short name T826
Test name
Test status
Simulation time 19058336008 ps
CPU time 99.19 seconds
Started Jun 07 08:43:57 PM PDT 24
Finished Jun 07 08:45:39 PM PDT 24
Peak memory 205896 kb
Host smart-5b85545e-aea4-499d-b714-ca20ba7b3e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30234
7474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.302347474
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.4156355509
Short name T2025
Test name
Test status
Simulation time 10144426252 ps
CPU time 13.25 seconds
Started Jun 07 08:44:12 PM PDT 24
Finished Jun 07 08:44:28 PM PDT 24
Peak memory 205764 kb
Host smart-ea087212-2f7b-4aac-bbde-832b38d70aab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4156355509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.4156355509
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.2682180952
Short name T1545
Test name
Test status
Simulation time 10053493924 ps
CPU time 12.53 seconds
Started Jun 07 08:44:12 PM PDT 24
Finished Jun 07 08:44:27 PM PDT 24
Peak memory 205752 kb
Host smart-4e772e61-fcad-48ee-bfac-e6f57b16c3dc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2682180952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.2682180952
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.1582534551
Short name T390
Test name
Test status
Simulation time 10144443497 ps
CPU time 13.36 seconds
Started Jun 07 08:44:12 PM PDT 24
Finished Jun 07 08:44:28 PM PDT 24
Peak memory 205796 kb
Host smart-2e662003-ab76-49bd-b312-ba91a0d63423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15825
34551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.1582534551
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.3693743692
Short name T1363
Test name
Test status
Simulation time 13874207643 ps
CPU time 17.05 seconds
Started Jun 07 08:44:06 PM PDT 24
Finished Jun 07 08:44:25 PM PDT 24
Peak memory 205776 kb
Host smart-1f40c457-ab3a-4e40-9a31-96d7241815d3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3693743692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.3693743692
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.1679469027
Short name T1277
Test name
Test status
Simulation time 23196398470 ps
CPU time 27.03 seconds
Started Jun 07 08:44:06 PM PDT 24
Finished Jun 07 08:44:35 PM PDT 24
Peak memory 205828 kb
Host smart-4bba5f95-6d2a-4d16-9d0e-63aa89fdd0a6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1679469027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.1679469027
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.410298894
Short name T1021
Test name
Test status
Simulation time 10045647006 ps
CPU time 13.44 seconds
Started Jun 07 08:44:05 PM PDT 24
Finished Jun 07 08:44:21 PM PDT 24
Peak memory 205824 kb
Host smart-5a6ab471-040a-4ecc-a4ae-7cf1b605559d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41029
8894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.410298894
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.4214328686
Short name T1147
Test name
Test status
Simulation time 10042126183 ps
CPU time 13.67 seconds
Started Jun 07 08:44:04 PM PDT 24
Finished Jun 07 08:44:20 PM PDT 24
Peak memory 205708 kb
Host smart-ab6cacd2-784f-42ec-955f-187e16bb41c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42143
28686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.4214328686
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.4214088103
Short name T1839
Test name
Test status
Simulation time 10778852951 ps
CPU time 16.78 seconds
Started Jun 07 08:44:04 PM PDT 24
Finished Jun 07 08:44:22 PM PDT 24
Peak memory 205768 kb
Host smart-e1929f77-6e7a-4814-8a33-0e591bbd8781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42140
88103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.4214088103
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.2309006967
Short name T852
Test name
Test status
Simulation time 10044438052 ps
CPU time 13.2 seconds
Started Jun 07 08:44:07 PM PDT 24
Finished Jun 07 08:44:22 PM PDT 24
Peak memory 205848 kb
Host smart-d31909ac-956b-482f-a7a0-3f171584719e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23090
06967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.2309006967
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1569104441
Short name T1125
Test name
Test status
Simulation time 10080200486 ps
CPU time 13.79 seconds
Started Jun 07 08:44:06 PM PDT 24
Finished Jun 07 08:44:22 PM PDT 24
Peak memory 205664 kb
Host smart-159fc45c-f465-4aa4-bf4b-d52e18feda04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15691
04441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1569104441
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.3976554810
Short name T1461
Test name
Test status
Simulation time 10810656547 ps
CPU time 15.8 seconds
Started Jun 07 08:44:04 PM PDT 24
Finished Jun 07 08:44:22 PM PDT 24
Peak memory 205776 kb
Host smart-b7ff6bbc-ec86-4762-b2a1-c7aa6b5a7c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39765
54810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.3976554810
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.4235304542
Short name T1725
Test name
Test status
Simulation time 10111614776 ps
CPU time 15.58 seconds
Started Jun 07 08:44:04 PM PDT 24
Finished Jun 07 08:44:21 PM PDT 24
Peak memory 205748 kb
Host smart-5325efa1-f61d-4d3e-b45b-bad2ccec5661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42353
04542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.4235304542
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3880488241
Short name T1924
Test name
Test status
Simulation time 10061251962 ps
CPU time 15.83 seconds
Started Jun 07 08:44:11 PM PDT 24
Finished Jun 07 08:44:30 PM PDT 24
Peak memory 205764 kb
Host smart-211e72ad-05ae-48bc-b14e-b5599661ba74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38804
88241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3880488241
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.1177941701
Short name T453
Test name
Test status
Simulation time 10040228255 ps
CPU time 13.17 seconds
Started Jun 07 08:44:11 PM PDT 24
Finished Jun 07 08:44:27 PM PDT 24
Peak memory 205868 kb
Host smart-d379f996-f0b0-4fd1-a03e-5a44dc0d5411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11779
41701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1177941701
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.1938133133
Short name T295
Test name
Test status
Simulation time 10138700213 ps
CPU time 12.93 seconds
Started Jun 07 08:44:06 PM PDT 24
Finished Jun 07 08:44:21 PM PDT 24
Peak memory 205740 kb
Host smart-c3f3a945-1aed-401a-92c0-71db4f323217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19381
33133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1938133133
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.2756490037
Short name T1150
Test name
Test status
Simulation time 10093652771 ps
CPU time 12.55 seconds
Started Jun 07 08:44:05 PM PDT 24
Finished Jun 07 08:44:20 PM PDT 24
Peak memory 205776 kb
Host smart-a266f9ec-6071-41eb-8a4e-2b2b5d8f75c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27564
90037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.2756490037
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.1332012655
Short name T1099
Test name
Test status
Simulation time 13212477906 ps
CPU time 17.44 seconds
Started Jun 07 08:44:05 PM PDT 24
Finished Jun 07 08:44:25 PM PDT 24
Peak memory 205752 kb
Host smart-b706b8a9-cf57-4b0f-a3d3-987406cc597a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13320
12655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.1332012655
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.902718566
Short name T747
Test name
Test status
Simulation time 10098687837 ps
CPU time 16.03 seconds
Started Jun 07 08:44:05 PM PDT 24
Finished Jun 07 08:44:23 PM PDT 24
Peak memory 205952 kb
Host smart-451a747f-d5a1-453d-b0fd-8b9f1b54eb30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90271
8566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.902718566
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.2553502638
Short name T772
Test name
Test status
Simulation time 23736158217 ps
CPU time 377.24 seconds
Started Jun 07 08:44:03 PM PDT 24
Finished Jun 07 08:50:22 PM PDT 24
Peak memory 205796 kb
Host smart-58ea6edf-872f-4300-8e9f-e42e17c22376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25535
02638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.2553502638
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.259332966
Short name T1389
Test name
Test status
Simulation time 10057871204 ps
CPU time 13.51 seconds
Started Jun 07 08:44:04 PM PDT 24
Finished Jun 07 08:44:19 PM PDT 24
Peak memory 205780 kb
Host smart-667df7c6-81c2-4c50-b3cb-371fbbd42209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25933
2966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.259332966
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3672882472
Short name T89
Test name
Test status
Simulation time 10147651366 ps
CPU time 13.65 seconds
Started Jun 07 08:44:03 PM PDT 24
Finished Jun 07 08:44:18 PM PDT 24
Peak memory 205976 kb
Host smart-cf1fac41-0685-444c-9b9e-a4f61fa89c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36728
82472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3672882472
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.3544095288
Short name T460
Test name
Test status
Simulation time 10103075095 ps
CPU time 15.34 seconds
Started Jun 07 08:44:07 PM PDT 24
Finished Jun 07 08:44:24 PM PDT 24
Peak memory 205848 kb
Host smart-6e01c120-d0dc-4c69-92f4-fcbf19e4609a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35440
95288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.3544095288
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.4074991904
Short name T1416
Test name
Test status
Simulation time 10088693207 ps
CPU time 13.12 seconds
Started Jun 07 08:44:04 PM PDT 24
Finished Jun 07 08:44:20 PM PDT 24
Peak memory 205844 kb
Host smart-30a21542-1a70-4e55-b7dd-19751b7f1b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40749
91904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.4074991904
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2280302741
Short name T1610
Test name
Test status
Simulation time 10083495294 ps
CPU time 13.87 seconds
Started Jun 07 08:44:06 PM PDT 24
Finished Jun 07 08:44:22 PM PDT 24
Peak memory 205840 kb
Host smart-7b8ea5de-afb2-4b98-a668-7c58421d4a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22803
02741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2280302741
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.786169514
Short name T885
Test name
Test status
Simulation time 10043045111 ps
CPU time 13.41 seconds
Started Jun 07 08:44:11 PM PDT 24
Finished Jun 07 08:44:27 PM PDT 24
Peak memory 205740 kb
Host smart-b3982476-4a62-4965-9971-f7706d53a792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78616
9514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.786169514
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_eop_single_bit_handling.626360498
Short name T1438
Test name
Test status
Simulation time 10083022288 ps
CPU time 14.89 seconds
Started Jun 07 08:44:09 PM PDT 24
Finished Jun 07 08:44:26 PM PDT 24
Peak memory 205900 kb
Host smart-5987f2c4-d67d-4acd-95a5-e93f7a183b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62636
0498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_eop_single_bit_handling.626360498
Directory /workspace/16.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1949272896
Short name T1279
Test name
Test status
Simulation time 10037539035 ps
CPU time 12.86 seconds
Started Jun 07 08:44:10 PM PDT 24
Finished Jun 07 08:44:25 PM PDT 24
Peak memory 205768 kb
Host smart-7e4fdf78-d483-48b0-8411-1cad5ff25871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19492
72896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1949272896
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.3390456438
Short name T1828
Test name
Test status
Simulation time 10129129519 ps
CPU time 13.82 seconds
Started Jun 07 08:44:13 PM PDT 24
Finished Jun 07 08:44:29 PM PDT 24
Peak memory 205788 kb
Host smart-08c9bda1-7176-4506-99e3-0860597723de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33904
56438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.3390456438
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.2904394280
Short name T1086
Test name
Test status
Simulation time 16393865521 ps
CPU time 27.92 seconds
Started Jun 07 08:44:02 PM PDT 24
Finished Jun 07 08:44:32 PM PDT 24
Peak memory 205772 kb
Host smart-b0bda773-d1d0-40df-aeeb-068a0f3acda2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29043
94280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.2904394280
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.657219574
Short name T1595
Test name
Test status
Simulation time 10044853517 ps
CPU time 13.26 seconds
Started Jun 07 08:44:04 PM PDT 24
Finished Jun 07 08:44:20 PM PDT 24
Peak memory 205836 kb
Host smart-6549c9f2-8cc1-42d0-b051-19566a8e589c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65721
9574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.657219574
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1078692878
Short name T371
Test name
Test status
Simulation time 10110173550 ps
CPU time 15.13 seconds
Started Jun 07 08:44:07 PM PDT 24
Finished Jun 07 08:44:24 PM PDT 24
Peak memory 205840 kb
Host smart-9a6f43eb-16ba-4805-b514-030f0790e18e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10786
92878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1078692878
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.1527799612
Short name T530
Test name
Test status
Simulation time 10077346913 ps
CPU time 13.41 seconds
Started Jun 07 08:44:04 PM PDT 24
Finished Jun 07 08:44:20 PM PDT 24
Peak memory 205824 kb
Host smart-a0c8c49e-4140-4ec3-8e56-9f4d23e9af6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15277
99612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.1527799612
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.1402237716
Short name T479
Test name
Test status
Simulation time 10117735597 ps
CPU time 16.3 seconds
Started Jun 07 08:44:12 PM PDT 24
Finished Jun 07 08:44:31 PM PDT 24
Peak memory 205772 kb
Host smart-3a208c33-fa41-4142-9729-99e53417c8e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14022
37716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.1402237716
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.4234187310
Short name T659
Test name
Test status
Simulation time 10095580981 ps
CPU time 13.26 seconds
Started Jun 07 08:44:13 PM PDT 24
Finished Jun 07 08:44:28 PM PDT 24
Peak memory 205720 kb
Host smart-3fef0b23-9beb-4ab0-a4df-a8418973e2be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42341
87310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.4234187310
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.284394152
Short name T1568
Test name
Test status
Simulation time 10090128625 ps
CPU time 13.8 seconds
Started Jun 07 08:44:11 PM PDT 24
Finished Jun 07 08:44:27 PM PDT 24
Peak memory 205800 kb
Host smart-baf08b84-be17-4f90-b1f3-ea75114316d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28439
4152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.284394152
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.1691944004
Short name T650
Test name
Test status
Simulation time 10081969114 ps
CPU time 12.79 seconds
Started Jun 07 08:44:10 PM PDT 24
Finished Jun 07 08:44:25 PM PDT 24
Peak memory 205768 kb
Host smart-914ae5ff-a8ae-4813-a616-b2b97e12db38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16919
44004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.1691944004
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.2812335056
Short name T718
Test name
Test status
Simulation time 10086408705 ps
CPU time 13.38 seconds
Started Jun 07 08:44:11 PM PDT 24
Finished Jun 07 08:44:27 PM PDT 24
Peak memory 205860 kb
Host smart-d3c809cc-7796-4efd-8753-f9f11acbc3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28123
35056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2812335056
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.1136900834
Short name T450
Test name
Test status
Simulation time 18451034031 ps
CPU time 242.84 seconds
Started Jun 07 08:44:13 PM PDT 24
Finished Jun 07 08:48:18 PM PDT 24
Peak memory 205756 kb
Host smart-9549391f-079f-4b8f-848d-76878feb17b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11369
00834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.1136900834
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.1247150064
Short name T372
Test name
Test status
Simulation time 10235137579 ps
CPU time 14.29 seconds
Started Jun 07 08:44:27 PM PDT 24
Finished Jun 07 08:44:44 PM PDT 24
Peak memory 205848 kb
Host smart-2ed55821-f5c2-4a58-af02-74510aeb4058
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1247150064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.1247150064
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.1192847144
Short name T409
Test name
Test status
Simulation time 10056357357 ps
CPU time 13.11 seconds
Started Jun 07 08:44:24 PM PDT 24
Finished Jun 07 08:44:40 PM PDT 24
Peak memory 205916 kb
Host smart-c4f7cb14-dbe8-4cfe-8b04-97655ab476b9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1192847144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.1192847144
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.3545598492
Short name T860
Test name
Test status
Simulation time 10129929860 ps
CPU time 13.93 seconds
Started Jun 07 08:44:25 PM PDT 24
Finished Jun 07 08:44:42 PM PDT 24
Peak memory 205876 kb
Host smart-395d78ee-0ba9-414a-b64f-79ecde493116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35455
98492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.3545598492
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.914573928
Short name T1679
Test name
Test status
Simulation time 13451840141 ps
CPU time 16.22 seconds
Started Jun 07 08:44:13 PM PDT 24
Finished Jun 07 08:44:31 PM PDT 24
Peak memory 205816 kb
Host smart-7e0dd490-b17d-4516-9154-304b0106a708
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=914573928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.914573928
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.3671187390
Short name T14
Test name
Test status
Simulation time 23211317425 ps
CPU time 30.87 seconds
Started Jun 07 08:44:11 PM PDT 24
Finished Jun 07 08:44:45 PM PDT 24
Peak memory 205820 kb
Host smart-ee32daf6-bd38-439b-9763-70ce1f67661b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3671187390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.3671187390
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.203138375
Short name T1987
Test name
Test status
Simulation time 10068626958 ps
CPU time 13.01 seconds
Started Jun 07 08:44:17 PM PDT 24
Finished Jun 07 08:44:31 PM PDT 24
Peak memory 205872 kb
Host smart-e4f267e7-9d78-493a-a3c9-b0679aecf393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20313
8375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.203138375
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.2451366656
Short name T1406
Test name
Test status
Simulation time 10057828130 ps
CPU time 15.58 seconds
Started Jun 07 08:44:11 PM PDT 24
Finished Jun 07 08:44:29 PM PDT 24
Peak memory 205868 kb
Host smart-f7300426-eabe-415a-8584-87eb0bc03842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24513
66656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.2451366656
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1859179342
Short name T1541
Test name
Test status
Simulation time 10914685929 ps
CPU time 14.24 seconds
Started Jun 07 08:44:22 PM PDT 24
Finished Jun 07 08:44:38 PM PDT 24
Peak memory 205800 kb
Host smart-11013664-e71b-4864-8c2f-890e52b0cca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18591
79342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1859179342
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.2102545004
Short name T528
Test name
Test status
Simulation time 10053590249 ps
CPU time 13.42 seconds
Started Jun 07 08:44:22 PM PDT 24
Finished Jun 07 08:44:38 PM PDT 24
Peak memory 205768 kb
Host smart-c281c411-079d-4830-9694-c16035ab7c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21025
45004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.2102545004
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.2507023246
Short name T1187
Test name
Test status
Simulation time 10057818991 ps
CPU time 13.51 seconds
Started Jun 07 08:44:23 PM PDT 24
Finished Jun 07 08:44:40 PM PDT 24
Peak memory 205756 kb
Host smart-558b69cf-ba84-407f-b32b-2f05f6725a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25070
23246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2507023246
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.2820096651
Short name T1135
Test name
Test status
Simulation time 10743474919 ps
CPU time 14.57 seconds
Started Jun 07 08:44:22 PM PDT 24
Finished Jun 07 08:44:40 PM PDT 24
Peak memory 205768 kb
Host smart-7db3b521-dacc-46f6-8122-082d07dc7635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28200
96651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.2820096651
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.3425913824
Short name T1947
Test name
Test status
Simulation time 10264776118 ps
CPU time 16.41 seconds
Started Jun 07 08:44:20 PM PDT 24
Finished Jun 07 08:44:37 PM PDT 24
Peak memory 205836 kb
Host smart-7b0fb5bd-5b31-477c-a25d-4ad1fb5228b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34259
13824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.3425913824
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.3623305678
Short name T733
Test name
Test status
Simulation time 10148276866 ps
CPU time 15.04 seconds
Started Jun 07 08:44:21 PM PDT 24
Finished Jun 07 08:44:37 PM PDT 24
Peak memory 205756 kb
Host smart-8ee25423-ea8e-47df-91d5-0a050758775f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36233
05678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.3623305678
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.913508420
Short name T1048
Test name
Test status
Simulation time 10042711815 ps
CPU time 13.45 seconds
Started Jun 07 08:44:24 PM PDT 24
Finished Jun 07 08:44:40 PM PDT 24
Peak memory 205792 kb
Host smart-5c1da443-de0a-4bfd-9a1f-c25c82c982f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91350
8420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.913508420
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.239181950
Short name T1108
Test name
Test status
Simulation time 10153452663 ps
CPU time 14.44 seconds
Started Jun 07 08:44:23 PM PDT 24
Finished Jun 07 08:44:41 PM PDT 24
Peak memory 205820 kb
Host smart-0b7da1cf-1d6b-41ea-8fc5-14c2c92cfa39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23918
1950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.239181950
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.2560865203
Short name T1578
Test name
Test status
Simulation time 10068972278 ps
CPU time 12.46 seconds
Started Jun 07 08:44:22 PM PDT 24
Finished Jun 07 08:44:37 PM PDT 24
Peak memory 205736 kb
Host smart-de5ee106-77bf-4a82-aee6-cfb367c1fbb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25608
65203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.2560865203
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.566313347
Short name T582
Test name
Test status
Simulation time 13223833784 ps
CPU time 15.29 seconds
Started Jun 07 08:44:22 PM PDT 24
Finished Jun 07 08:44:40 PM PDT 24
Peak memory 205768 kb
Host smart-7928acfb-775a-4b91-94c0-41924ed374b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56631
3347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.566313347
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.3765268083
Short name T639
Test name
Test status
Simulation time 10107061301 ps
CPU time 13.91 seconds
Started Jun 07 08:44:22 PM PDT 24
Finished Jun 07 08:44:39 PM PDT 24
Peak memory 205772 kb
Host smart-e9a34fc4-698a-43fb-82b0-8542353e26bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37652
68083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3765268083
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.1701853023
Short name T388
Test name
Test status
Simulation time 19809839845 ps
CPU time 103.52 seconds
Started Jun 07 08:44:21 PM PDT 24
Finished Jun 07 08:46:07 PM PDT 24
Peak memory 205776 kb
Host smart-b4614d19-9853-4ebc-8fd4-2baa65b8bdaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17018
53023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.1701853023
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1699540910
Short name T1650
Test name
Test status
Simulation time 10048067536 ps
CPU time 13.83 seconds
Started Jun 07 08:44:21 PM PDT 24
Finished Jun 07 08:44:36 PM PDT 24
Peak memory 205828 kb
Host smart-725d5722-2646-4ded-8b02-58ad1b701cd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16995
40910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1699540910
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.1482335263
Short name T1913
Test name
Test status
Simulation time 10101576627 ps
CPU time 15.96 seconds
Started Jun 07 08:44:22 PM PDT 24
Finished Jun 07 08:44:41 PM PDT 24
Peak memory 205844 kb
Host smart-e11b01f1-d1a0-46fa-997e-b2d77f5b0c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14823
35263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.1482335263
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1779066158
Short name T1926
Test name
Test status
Simulation time 10095193723 ps
CPU time 13.15 seconds
Started Jun 07 08:44:23 PM PDT 24
Finished Jun 07 08:44:39 PM PDT 24
Peak memory 205768 kb
Host smart-3d6bd835-d6c9-484d-a391-bd74dcaab1a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17790
66158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1779066158
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.3861590150
Short name T1392
Test name
Test status
Simulation time 10075203784 ps
CPU time 12.96 seconds
Started Jun 07 08:44:21 PM PDT 24
Finished Jun 07 08:44:36 PM PDT 24
Peak memory 205872 kb
Host smart-06dd7856-6202-44b9-bfbc-5ad31925a6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38615
90150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.3861590150
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_eop_single_bit_handling.3390678391
Short name T536
Test name
Test status
Simulation time 10097350155 ps
CPU time 13.03 seconds
Started Jun 07 08:44:23 PM PDT 24
Finished Jun 07 08:44:39 PM PDT 24
Peak memory 205812 kb
Host smart-580dde87-3292-4757-b3dc-c86b054954ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33906
78391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_eop_single_bit_handling.3390678391
Directory /workspace/17.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3440177198
Short name T2014
Test name
Test status
Simulation time 10051188263 ps
CPU time 13.26 seconds
Started Jun 07 08:44:26 PM PDT 24
Finished Jun 07 08:44:42 PM PDT 24
Peak memory 205896 kb
Host smart-f30f2ccd-5bdb-4c1d-90ff-f83c04aae2c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34401
77198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.3440177198
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2201318189
Short name T25
Test name
Test status
Simulation time 10062914650 ps
CPU time 14.55 seconds
Started Jun 07 08:44:22 PM PDT 24
Finished Jun 07 08:44:40 PM PDT 24
Peak memory 205788 kb
Host smart-76f135f2-d999-4155-a3dd-e9f42135a35a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22013
18189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2201318189
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.2988365277
Short name T1453
Test name
Test status
Simulation time 22234823137 ps
CPU time 41.82 seconds
Started Jun 07 08:44:27 PM PDT 24
Finished Jun 07 08:45:12 PM PDT 24
Peak memory 205780 kb
Host smart-9bea6822-a328-47d4-9e3f-591e81ef2e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29883
65277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.2988365277
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1017220937
Short name T1047
Test name
Test status
Simulation time 10068099245 ps
CPU time 13.45 seconds
Started Jun 07 08:44:22 PM PDT 24
Finished Jun 07 08:44:39 PM PDT 24
Peak memory 205848 kb
Host smart-894108d8-2d51-4e9e-b182-976bdc95a99e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10172
20937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1017220937
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2571432551
Short name T310
Test name
Test status
Simulation time 10065709452 ps
CPU time 12.68 seconds
Started Jun 07 08:44:24 PM PDT 24
Finished Jun 07 08:44:39 PM PDT 24
Peak memory 205696 kb
Host smart-3bf340c3-c28d-4a1c-9a1b-f1447aa80812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25714
32551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2571432551
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.1509195415
Short name T715
Test name
Test status
Simulation time 10085046292 ps
CPU time 12.97 seconds
Started Jun 07 08:44:21 PM PDT 24
Finished Jun 07 08:44:35 PM PDT 24
Peak memory 205868 kb
Host smart-777055c6-4654-4ef3-9098-37c30a5caef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15091
95415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.1509195415
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.3254198247
Short name T376
Test name
Test status
Simulation time 10044160313 ps
CPU time 13.49 seconds
Started Jun 07 08:44:23 PM PDT 24
Finished Jun 07 08:44:40 PM PDT 24
Peak memory 205764 kb
Host smart-4e5ac45f-c3dd-4a60-852e-79e3d0c619bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32541
98247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.3254198247
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.3820157998
Short name T2020
Test name
Test status
Simulation time 10064377453 ps
CPU time 13.18 seconds
Started Jun 07 08:44:25 PM PDT 24
Finished Jun 07 08:44:41 PM PDT 24
Peak memory 205836 kb
Host smart-5f3f98fa-2381-4330-85c3-52abae581e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38201
57998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.3820157998
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.173716649
Short name T543
Test name
Test status
Simulation time 10051331755 ps
CPU time 13.06 seconds
Started Jun 07 08:44:22 PM PDT 24
Finished Jun 07 08:44:38 PM PDT 24
Peak memory 205808 kb
Host smart-f506a856-e1e8-4ecc-a5b8-7110f07259f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17371
6649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.173716649
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3041316583
Short name T1248
Test name
Test status
Simulation time 10149489201 ps
CPU time 13.74 seconds
Started Jun 07 08:44:10 PM PDT 24
Finished Jun 07 08:44:26 PM PDT 24
Peak memory 205924 kb
Host smart-ad45887e-598f-4a68-8897-4f6f6208c98e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30413
16583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3041316583
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.43333538
Short name T336
Test name
Test status
Simulation time 10070170779 ps
CPU time 13.32 seconds
Started Jun 07 08:44:27 PM PDT 24
Finished Jun 07 08:44:43 PM PDT 24
Peak memory 205912 kb
Host smart-7ab22247-9c30-41d4-94c5-429bf83c691f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43333
538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.43333538
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2612036889
Short name T507
Test name
Test status
Simulation time 10061632663 ps
CPU time 12.63 seconds
Started Jun 07 08:44:22 PM PDT 24
Finished Jun 07 08:44:37 PM PDT 24
Peak memory 205752 kb
Host smart-7b01c225-5aaa-4fee-a3cd-45dc3119d38e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26120
36889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2612036889
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.158097482
Short name T1581
Test name
Test status
Simulation time 22737090484 ps
CPU time 135.26 seconds
Started Jun 07 08:44:24 PM PDT 24
Finished Jun 07 08:46:42 PM PDT 24
Peak memory 205880 kb
Host smart-39a2d5b8-d0c8-4c20-97fb-bda92249ee05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15809
7482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.158097482
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.1176192489
Short name T1965
Test name
Test status
Simulation time 10158047876 ps
CPU time 14.93 seconds
Started Jun 07 08:44:32 PM PDT 24
Finished Jun 07 08:44:50 PM PDT 24
Peak memory 205836 kb
Host smart-a997a908-0ef9-4c25-b691-0ef939e6e807
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1176192489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.1176192489
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.157633547
Short name T1094
Test name
Test status
Simulation time 10089487042 ps
CPU time 12.44 seconds
Started Jun 07 08:44:29 PM PDT 24
Finished Jun 07 08:44:45 PM PDT 24
Peak memory 205832 kb
Host smart-b7d5cb99-0f9f-406b-ad7a-54b6465aaa2d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=157633547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.157633547
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.4009582927
Short name T1708
Test name
Test status
Simulation time 10084923209 ps
CPU time 14.99 seconds
Started Jun 07 08:44:28 PM PDT 24
Finished Jun 07 08:44:47 PM PDT 24
Peak memory 205800 kb
Host smart-d57d0743-97ca-4797-aaf5-684d523c2ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40095
82927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.4009582927
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.2146932013
Short name T586
Test name
Test status
Simulation time 13641688506 ps
CPU time 17.23 seconds
Started Jun 07 08:44:27 PM PDT 24
Finished Jun 07 08:44:47 PM PDT 24
Peak memory 205844 kb
Host smart-5334918e-edce-4a7e-ac41-88a961d9a30e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2146932013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.2146932013
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.1811590747
Short name T1285
Test name
Test status
Simulation time 23272372763 ps
CPU time 26.37 seconds
Started Jun 07 08:44:26 PM PDT 24
Finished Jun 07 08:44:55 PM PDT 24
Peak memory 205936 kb
Host smart-3658d589-ec05-4f45-bf71-a4744f7ae11c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1811590747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.1811590747
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1254327024
Short name T312
Test name
Test status
Simulation time 10053773396 ps
CPU time 13.53 seconds
Started Jun 07 08:44:27 PM PDT 24
Finished Jun 07 08:44:44 PM PDT 24
Peak memory 205720 kb
Host smart-d777e879-8688-454f-80e7-a976636c90bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12543
27024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1254327024
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.2012802798
Short name T1664
Test name
Test status
Simulation time 10667613835 ps
CPU time 14.21 seconds
Started Jun 07 08:44:31 PM PDT 24
Finished Jun 07 08:44:48 PM PDT 24
Peak memory 205848 kb
Host smart-36aad301-0deb-4e13-af04-b1f274d85575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20128
02798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.2012802798
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.1218159668
Short name T1286
Test name
Test status
Simulation time 10088634973 ps
CPU time 12.94 seconds
Started Jun 07 08:44:30 PM PDT 24
Finished Jun 07 08:44:46 PM PDT 24
Peak memory 205848 kb
Host smart-6ced16d1-61d9-4fc0-80e2-e9ed920bfb34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12181
59668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.1218159668
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.1417179800
Short name T1383
Test name
Test status
Simulation time 10051244184 ps
CPU time 14.69 seconds
Started Jun 07 08:44:29 PM PDT 24
Finished Jun 07 08:44:47 PM PDT 24
Peak memory 205760 kb
Host smart-3368d931-be0f-4731-8e26-9fe91638171c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14171
79800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1417179800
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.4079245509
Short name T1474
Test name
Test status
Simulation time 10886864485 ps
CPU time 14.49 seconds
Started Jun 07 08:44:26 PM PDT 24
Finished Jun 07 08:44:44 PM PDT 24
Peak memory 205888 kb
Host smart-c5af6050-707b-4e27-b51f-2f263d3d9971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40792
45509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.4079245509
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2593497635
Short name T620
Test name
Test status
Simulation time 10064871313 ps
CPU time 15.57 seconds
Started Jun 07 08:44:29 PM PDT 24
Finished Jun 07 08:44:48 PM PDT 24
Peak memory 205656 kb
Host smart-459b39d9-cf24-4597-b9b2-3da58f2a8b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25934
97635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2593497635
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.3015211564
Short name T373
Test name
Test status
Simulation time 10091230212 ps
CPU time 13.77 seconds
Started Jun 07 08:44:28 PM PDT 24
Finished Jun 07 08:44:46 PM PDT 24
Peak memory 205704 kb
Host smart-22a090b9-b531-4b06-8252-4ee28be80ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30152
11564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.3015211564
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.1896889133
Short name T1681
Test name
Test status
Simulation time 10074062335 ps
CPU time 12.95 seconds
Started Jun 07 08:44:29 PM PDT 24
Finished Jun 07 08:44:46 PM PDT 24
Peak memory 205768 kb
Host smart-07be2467-e17d-44ec-b45b-40e19413e1b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18968
89133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1896889133
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.1608057772
Short name T686
Test name
Test status
Simulation time 10125642816 ps
CPU time 12.76 seconds
Started Jun 07 08:44:27 PM PDT 24
Finished Jun 07 08:44:43 PM PDT 24
Peak memory 205908 kb
Host smart-cd96e4f9-090a-4105-a8a3-940585fb5a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16080
57772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1608057772
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.166194963
Short name T1821
Test name
Test status
Simulation time 10106018229 ps
CPU time 15.43 seconds
Started Jun 07 08:44:27 PM PDT 24
Finished Jun 07 08:44:46 PM PDT 24
Peak memory 205836 kb
Host smart-89a08b7b-4738-4c84-b1e8-b77db88147bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16619
4963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.166194963
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.493504048
Short name T412
Test name
Test status
Simulation time 13299677133 ps
CPU time 16.64 seconds
Started Jun 07 08:44:24 PM PDT 24
Finished Jun 07 08:44:43 PM PDT 24
Peak memory 205812 kb
Host smart-cd0c5dfc-094c-45f7-b15e-7996908817d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49350
4048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.493504048
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1620850848
Short name T1523
Test name
Test status
Simulation time 10094963060 ps
CPU time 14.82 seconds
Started Jun 07 08:44:25 PM PDT 24
Finished Jun 07 08:44:43 PM PDT 24
Peak memory 205856 kb
Host smart-aa7215f1-dab7-4ae3-9110-d3472fc31f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16208
50848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1620850848
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.1168635818
Short name T1814
Test name
Test status
Simulation time 19099864904 ps
CPU time 271.38 seconds
Started Jun 07 08:44:28 PM PDT 24
Finished Jun 07 08:49:03 PM PDT 24
Peak memory 205756 kb
Host smart-bfb00bf8-41f7-4566-b49c-7e45c90510fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11686
35818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.1168635818
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2384849851
Short name T1561
Test name
Test status
Simulation time 10055031771 ps
CPU time 13.18 seconds
Started Jun 07 08:44:27 PM PDT 24
Finished Jun 07 08:44:44 PM PDT 24
Peak memory 205816 kb
Host smart-4e2ce38e-1f76-494c-b8ff-d7c9794d008d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23848
49851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2384849851
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.2151959783
Short name T1591
Test name
Test status
Simulation time 10100892317 ps
CPU time 14.93 seconds
Started Jun 07 08:44:26 PM PDT 24
Finished Jun 07 08:44:44 PM PDT 24
Peak memory 205776 kb
Host smart-b500799c-3186-4c39-9409-89b3477490c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21519
59783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.2151959783
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.843021300
Short name T794
Test name
Test status
Simulation time 10055110842 ps
CPU time 13.16 seconds
Started Jun 07 08:44:35 PM PDT 24
Finished Jun 07 08:44:52 PM PDT 24
Peak memory 205836 kb
Host smart-b5f22d07-44a1-4c0c-872e-51a2df4cb33d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84302
1300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.843021300
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1223171684
Short name T1109
Test name
Test status
Simulation time 10105379639 ps
CPU time 15.1 seconds
Started Jun 07 08:44:27 PM PDT 24
Finished Jun 07 08:44:45 PM PDT 24
Peak memory 205876 kb
Host smart-661fbbfa-9021-4f1b-b1c4-b4d5fd851c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12231
71684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1223171684
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1968443512
Short name T1691
Test name
Test status
Simulation time 10047509442 ps
CPU time 12.87 seconds
Started Jun 07 08:44:25 PM PDT 24
Finished Jun 07 08:44:40 PM PDT 24
Peak memory 205796 kb
Host smart-8cde229a-9052-4d60-a97f-9be3871c07c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19684
43512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1968443512
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_eop_single_bit_handling.2989469811
Short name T1602
Test name
Test status
Simulation time 10055055520 ps
CPU time 13.07 seconds
Started Jun 07 08:44:34 PM PDT 24
Finished Jun 07 08:44:51 PM PDT 24
Peak memory 205768 kb
Host smart-dd6423b5-9a2b-48bb-b43d-11be29db0d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29894
69811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_eop_single_bit_handling.2989469811
Directory /workspace/18.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.704012221
Short name T1536
Test name
Test status
Simulation time 10091901640 ps
CPU time 13.95 seconds
Started Jun 07 08:44:29 PM PDT 24
Finished Jun 07 08:44:46 PM PDT 24
Peak memory 205680 kb
Host smart-07d1e8fd-a35a-4931-a551-869055c02ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70401
2221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.704012221
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.124593732
Short name T1343
Test name
Test status
Simulation time 10053106235 ps
CPU time 13.82 seconds
Started Jun 07 08:44:28 PM PDT 24
Finished Jun 07 08:44:45 PM PDT 24
Peak memory 205840 kb
Host smart-616de74a-4514-4983-8541-7b957c1028a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12459
3732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.124593732
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.3384272469
Short name T1103
Test name
Test status
Simulation time 27810835210 ps
CPU time 47.29 seconds
Started Jun 07 08:44:28 PM PDT 24
Finished Jun 07 08:45:18 PM PDT 24
Peak memory 205788 kb
Host smart-2612e08f-62fa-4955-a270-a69bcecce9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33842
72469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.3384272469
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.259198514
Short name T603
Test name
Test status
Simulation time 10068189789 ps
CPU time 14.55 seconds
Started Jun 07 08:44:29 PM PDT 24
Finished Jun 07 08:44:47 PM PDT 24
Peak memory 205780 kb
Host smart-56bc2dd1-a98a-4b17-9ffd-9ded4b2ee1c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25919
8514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.259198514
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.3982749743
Short name T1133
Test name
Test status
Simulation time 10053628706 ps
CPU time 12.51 seconds
Started Jun 07 08:44:28 PM PDT 24
Finished Jun 07 08:44:44 PM PDT 24
Peak memory 205772 kb
Host smart-03cb82f1-255f-407f-baca-e496bbbb0eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39827
49743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.3982749743
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.2309938133
Short name T201
Test name
Test status
Simulation time 10073097721 ps
CPU time 12.92 seconds
Started Jun 07 08:44:29 PM PDT 24
Finished Jun 07 08:44:45 PM PDT 24
Peak memory 205744 kb
Host smart-0009ab75-ed66-4a14-a91e-5e8f8b4b0f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23099
38133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.2309938133
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.686214711
Short name T1226
Test name
Test status
Simulation time 10041882244 ps
CPU time 13.22 seconds
Started Jun 07 08:44:28 PM PDT 24
Finished Jun 07 08:44:44 PM PDT 24
Peak memory 205780 kb
Host smart-9dc76e00-32e0-48f1-a325-dae96e8b3535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68621
4711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.686214711
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.4187190873
Short name T471
Test name
Test status
Simulation time 10067492245 ps
CPU time 12.84 seconds
Started Jun 07 08:44:30 PM PDT 24
Finished Jun 07 08:44:46 PM PDT 24
Peak memory 205736 kb
Host smart-d1f98297-7e19-4f81-a670-97beb2b091ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41871
90873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.4187190873
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3582951226
Short name T445
Test name
Test status
Simulation time 10094290064 ps
CPU time 13.33 seconds
Started Jun 07 08:44:32 PM PDT 24
Finished Jun 07 08:44:48 PM PDT 24
Peak memory 205744 kb
Host smart-11168897-9343-42f1-be0b-38bbaed5e327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35829
51226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3582951226
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.498750467
Short name T743
Test name
Test status
Simulation time 10059928677 ps
CPU time 13.83 seconds
Started Jun 07 08:44:31 PM PDT 24
Finished Jun 07 08:44:48 PM PDT 24
Peak memory 205856 kb
Host smart-34e02156-0def-4f35-9be4-17a3da605a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49875
0467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.498750467
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.3198874419
Short name T1998
Test name
Test status
Simulation time 10093595805 ps
CPU time 14.38 seconds
Started Jun 07 08:44:35 PM PDT 24
Finished Jun 07 08:44:53 PM PDT 24
Peak memory 205792 kb
Host smart-a527cb98-c4ca-416a-b3b3-20e1a5090611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31988
74419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.3198874419
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.2598226509
Short name T1026
Test name
Test status
Simulation time 15990307153 ps
CPU time 184.97 seconds
Started Jun 07 08:44:26 PM PDT 24
Finished Jun 07 08:47:34 PM PDT 24
Peak memory 205804 kb
Host smart-e74d8636-d6e5-4bcd-9075-52c98edd4efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25982
26509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.2598226509
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.2998517848
Short name T1976
Test name
Test status
Simulation time 10151786156 ps
CPU time 13.18 seconds
Started Jun 07 08:44:34 PM PDT 24
Finished Jun 07 08:44:51 PM PDT 24
Peak memory 205740 kb
Host smart-898ecffa-4b8e-4e64-b828-54bcdc20db9b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2998517848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.2998517848
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.2498201242
Short name T533
Test name
Test status
Simulation time 10060525520 ps
CPU time 12.83 seconds
Started Jun 07 08:44:35 PM PDT 24
Finished Jun 07 08:44:52 PM PDT 24
Peak memory 205792 kb
Host smart-d0cd38b0-eb85-46fb-830e-7751817c05b6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2498201242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.2498201242
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.4141625031
Short name T1073
Test name
Test status
Simulation time 10158083892 ps
CPU time 13.06 seconds
Started Jun 07 08:44:36 PM PDT 24
Finished Jun 07 08:44:53 PM PDT 24
Peak memory 205772 kb
Host smart-276bd95c-00f6-47f5-9707-f7ba27f97496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41416
25031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.4141625031
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.133120830
Short name T1139
Test name
Test status
Simulation time 14390796499 ps
CPU time 19.67 seconds
Started Jun 07 08:44:27 PM PDT 24
Finished Jun 07 08:44:50 PM PDT 24
Peak memory 205784 kb
Host smart-f8c2ccee-7148-4266-b423-667c44901b86
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=133120830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.133120830
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.3023330428
Short name T1608
Test name
Test status
Simulation time 23214673089 ps
CPU time 26.01 seconds
Started Jun 07 08:44:31 PM PDT 24
Finished Jun 07 08:45:00 PM PDT 24
Peak memory 205876 kb
Host smart-2e9dcc03-7391-412b-aa6b-64b6a9f0647c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3023330428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.3023330428
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.2374635375
Short name T423
Test name
Test status
Simulation time 10050321125 ps
CPU time 12.47 seconds
Started Jun 07 08:44:36 PM PDT 24
Finished Jun 07 08:44:52 PM PDT 24
Peak memory 205852 kb
Host smart-347e6668-bfd7-4417-9455-14e6b0108791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23746
35375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.2374635375
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.2342872110
Short name T1031
Test name
Test status
Simulation time 10690401487 ps
CPU time 14.02 seconds
Started Jun 07 08:44:33 PM PDT 24
Finished Jun 07 08:44:51 PM PDT 24
Peak memory 205792 kb
Host smart-a51e6ed9-2b89-4fb1-996a-c2391f27eb3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23428
72110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.2342872110
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.920547842
Short name T1288
Test name
Test status
Simulation time 10038410159 ps
CPU time 14.79 seconds
Started Jun 07 08:44:33 PM PDT 24
Finished Jun 07 08:44:51 PM PDT 24
Peak memory 205796 kb
Host smart-9f5e1d2f-e035-4566-9e32-07b77abc9c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92054
7842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.920547842
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.2861209207
Short name T1511
Test name
Test status
Simulation time 10049297269 ps
CPU time 14.02 seconds
Started Jun 07 08:44:32 PM PDT 24
Finished Jun 07 08:44:49 PM PDT 24
Peak memory 205828 kb
Host smart-bbb0e49a-8c20-4ae4-a25d-2df1fe9f10b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28612
09207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2861209207
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1196822778
Short name T1010
Test name
Test status
Simulation time 10065465140 ps
CPU time 13.87 seconds
Started Jun 07 08:44:33 PM PDT 24
Finished Jun 07 08:44:51 PM PDT 24
Peak memory 205756 kb
Host smart-275afefc-5b5b-4b4d-883e-c50c27a909c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11968
22778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1196822778
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.1586530702
Short name T626
Test name
Test status
Simulation time 10110848969 ps
CPU time 14.08 seconds
Started Jun 07 08:44:34 PM PDT 24
Finished Jun 07 08:44:51 PM PDT 24
Peak memory 205916 kb
Host smart-4f943b6c-71d8-4c89-bacb-9a466a9fde01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15865
30702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.1586530702
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.859089271
Short name T1634
Test name
Test status
Simulation time 10071508644 ps
CPU time 12.75 seconds
Started Jun 07 08:44:32 PM PDT 24
Finished Jun 07 08:44:48 PM PDT 24
Peak memory 205844 kb
Host smart-c52bc683-01a0-4e75-a143-de12271aeaf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85908
9271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.859089271
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.3845847478
Short name T1933
Test name
Test status
Simulation time 10082856391 ps
CPU time 12.51 seconds
Started Jun 07 08:44:36 PM PDT 24
Finished Jun 07 08:44:52 PM PDT 24
Peak memory 205792 kb
Host smart-1010d997-3658-40cd-8ca7-35e952cd0949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38458
47478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.3845847478
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1684543995
Short name T1985
Test name
Test status
Simulation time 10115259543 ps
CPU time 13.47 seconds
Started Jun 07 08:44:35 PM PDT 24
Finished Jun 07 08:44:52 PM PDT 24
Peak memory 205744 kb
Host smart-ac29d3e6-5ca3-4187-8f6e-e1b06248ab00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16845
43995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1684543995
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.1578415789
Short name T1377
Test name
Test status
Simulation time 13249420331 ps
CPU time 16.4 seconds
Started Jun 07 08:44:36 PM PDT 24
Finished Jun 07 08:44:56 PM PDT 24
Peak memory 205880 kb
Host smart-6b17f8c6-0e46-4be9-9d2e-adf054e8f5df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15784
15789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.1578415789
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1941731391
Short name T419
Test name
Test status
Simulation time 10103976517 ps
CPU time 14.15 seconds
Started Jun 07 08:44:37 PM PDT 24
Finished Jun 07 08:44:54 PM PDT 24
Peak memory 205852 kb
Host smart-13cb01cf-a68a-455b-987c-f1cda9f668dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19417
31391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1941731391
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.1360163008
Short name T589
Test name
Test status
Simulation time 23030577526 ps
CPU time 378.69 seconds
Started Jun 07 08:44:32 PM PDT 24
Finished Jun 07 08:50:55 PM PDT 24
Peak memory 205740 kb
Host smart-d73fce22-0b38-475d-985d-3377f55630c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13601
63008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.1360163008
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.111186039
Short name T1888
Test name
Test status
Simulation time 10074772809 ps
CPU time 12.57 seconds
Started Jun 07 08:44:34 PM PDT 24
Finished Jun 07 08:44:50 PM PDT 24
Peak memory 205872 kb
Host smart-99f69da8-35de-4b0a-b44a-b11a6c518a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11118
6039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.111186039
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.1234339830
Short name T498
Test name
Test status
Simulation time 10073399877 ps
CPU time 12.69 seconds
Started Jun 07 08:44:35 PM PDT 24
Finished Jun 07 08:44:51 PM PDT 24
Peak memory 205840 kb
Host smart-a9a27456-d941-40a8-b206-8529f55735e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12343
39830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.1234339830
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.630485410
Short name T780
Test name
Test status
Simulation time 10152486944 ps
CPU time 12.87 seconds
Started Jun 07 08:44:33 PM PDT 24
Finished Jun 07 08:44:49 PM PDT 24
Peak memory 205868 kb
Host smart-757d786a-aa6a-470f-8b4f-ceb569243b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63048
5410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.630485410
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2802089778
Short name T1700
Test name
Test status
Simulation time 10046477245 ps
CPU time 12.95 seconds
Started Jun 07 08:44:35 PM PDT 24
Finished Jun 07 08:44:52 PM PDT 24
Peak memory 205876 kb
Host smart-492d6cbb-bace-4a0d-bfcc-b9a67a2c0163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28020
89778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2802089778
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_eop_single_bit_handling.1583893323
Short name T367
Test name
Test status
Simulation time 10070499839 ps
CPU time 12.82 seconds
Started Jun 07 08:44:35 PM PDT 24
Finished Jun 07 08:44:52 PM PDT 24
Peak memory 205752 kb
Host smart-5827e4e6-8929-4b74-ac70-66f5a1f4597f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15838
93323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_eop_single_bit_handling.1583893323
Directory /workspace/19.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.3132453710
Short name T551
Test name
Test status
Simulation time 10083501891 ps
CPU time 15.97 seconds
Started Jun 07 08:44:35 PM PDT 24
Finished Jun 07 08:44:55 PM PDT 24
Peak memory 205828 kb
Host smart-373fba3a-17d9-42b7-a3e3-89d3ef3884aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31324
53710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.3132453710
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1953159028
Short name T1635
Test name
Test status
Simulation time 10047186402 ps
CPU time 13.13 seconds
Started Jun 07 08:44:42 PM PDT 24
Finished Jun 07 08:44:58 PM PDT 24
Peak memory 205756 kb
Host smart-781a9e89-b9a0-4534-9b10-bb6e6633a74c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19531
59028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1953159028
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.1078334774
Short name T1642
Test name
Test status
Simulation time 22076159426 ps
CPU time 38.45 seconds
Started Jun 07 08:44:35 PM PDT 24
Finished Jun 07 08:45:18 PM PDT 24
Peak memory 205776 kb
Host smart-e42e3106-d333-4646-b26d-1af4e0c08150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10783
34774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.1078334774
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.3060959790
Short name T357
Test name
Test status
Simulation time 10119890194 ps
CPU time 12.75 seconds
Started Jun 07 08:44:34 PM PDT 24
Finished Jun 07 08:44:50 PM PDT 24
Peak memory 205700 kb
Host smart-b54cc4b0-7857-4300-bd72-f6f3f1f02ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30609
59790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3060959790
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1542498919
Short name T1356
Test name
Test status
Simulation time 10103791412 ps
CPU time 12.76 seconds
Started Jun 07 08:44:34 PM PDT 24
Finished Jun 07 08:44:50 PM PDT 24
Peak memory 205728 kb
Host smart-dd6a1821-dd15-49eb-9196-fff3211c099e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15424
98919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1542498919
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.294390626
Short name T711
Test name
Test status
Simulation time 10054186219 ps
CPU time 14.36 seconds
Started Jun 07 08:44:38 PM PDT 24
Finished Jun 07 08:44:55 PM PDT 24
Peak memory 205856 kb
Host smart-5eed4c97-185c-4ef6-87fc-d7a0ff93b6a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29439
0626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.294390626
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.1445908555
Short name T1006
Test name
Test status
Simulation time 10041666763 ps
CPU time 12.81 seconds
Started Jun 07 08:44:36 PM PDT 24
Finished Jun 07 08:44:52 PM PDT 24
Peak memory 205852 kb
Host smart-c532d191-44cf-4e09-ade0-9b9b9b485c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14459
08555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.1445908555
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.2403645587
Short name T1612
Test name
Test status
Simulation time 10050008495 ps
CPU time 14.75 seconds
Started Jun 07 08:44:32 PM PDT 24
Finished Jun 07 08:44:51 PM PDT 24
Peak memory 205928 kb
Host smart-906926fb-471f-4bb5-8234-545630e97140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24036
45587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.2403645587
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.2999407876
Short name T876
Test name
Test status
Simulation time 10055357004 ps
CPU time 14.16 seconds
Started Jun 07 08:44:37 PM PDT 24
Finished Jun 07 08:44:54 PM PDT 24
Peak memory 205708 kb
Host smart-0f6d98fd-882e-4ce0-bc38-4b7ad24ef71c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29994
07876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.2999407876
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.3706221083
Short name T1443
Test name
Test status
Simulation time 10131353384 ps
CPU time 14.07 seconds
Started Jun 07 08:44:27 PM PDT 24
Finished Jun 07 08:44:44 PM PDT 24
Peak memory 205792 kb
Host smart-49fd126e-c1c3-4a61-a844-46aaf2d44d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37062
21083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.3706221083
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.1353140732
Short name T1759
Test name
Test status
Simulation time 10079755536 ps
CPU time 13.82 seconds
Started Jun 07 08:44:35 PM PDT 24
Finished Jun 07 08:44:52 PM PDT 24
Peak memory 205872 kb
Host smart-eb6913fc-ba7c-48fb-bd55-a9db13baf55f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13531
40732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.1353140732
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.2078686176
Short name T422
Test name
Test status
Simulation time 10102460377 ps
CPU time 12.98 seconds
Started Jun 07 08:44:36 PM PDT 24
Finished Jun 07 08:44:52 PM PDT 24
Peak memory 205804 kb
Host smart-09fdbd5f-0203-4f22-8a5f-f73be372abe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20786
86176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.2078686176
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.1616343102
Short name T1232
Test name
Test status
Simulation time 21958079331 ps
CPU time 123.1 seconds
Started Jun 07 08:44:36 PM PDT 24
Finished Jun 07 08:46:43 PM PDT 24
Peak memory 205824 kb
Host smart-33a324da-dd54-45e6-b98d-a7504d4375dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16163
43102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.1616343102
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.1530797097
Short name T1308
Test name
Test status
Simulation time 10136234583 ps
CPU time 12.92 seconds
Started Jun 07 08:41:11 PM PDT 24
Finished Jun 07 08:41:27 PM PDT 24
Peak memory 205800 kb
Host smart-19567eac-f066-4237-9406-2a66e3c9a21b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1530797097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.1530797097
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.1072717930
Short name T1904
Test name
Test status
Simulation time 10072769944 ps
CPU time 12.8 seconds
Started Jun 07 08:41:14 PM PDT 24
Finished Jun 07 08:41:29 PM PDT 24
Peak memory 205904 kb
Host smart-e2b8c2df-2f25-4fa6-9899-5d426acf6383
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1072717930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.1072717930
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.62648424
Short name T333
Test name
Test status
Simulation time 10108995178 ps
CPU time 12.87 seconds
Started Jun 07 08:41:10 PM PDT 24
Finished Jun 07 08:41:26 PM PDT 24
Peak memory 205800 kb
Host smart-1cff8f74-50c4-4494-95ec-65168fbfb170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62648
424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.62648424
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.3101376673
Short name T541
Test name
Test status
Simulation time 13538165148 ps
CPU time 18.28 seconds
Started Jun 07 08:40:58 PM PDT 24
Finished Jun 07 08:41:18 PM PDT 24
Peak memory 205960 kb
Host smart-9e5bbd18-82de-4984-a38e-ba1aec39fcc5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3101376673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.3101376673
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.1793924555
Short name T1465
Test name
Test status
Simulation time 23213842181 ps
CPU time 24.04 seconds
Started Jun 07 08:40:57 PM PDT 24
Finished Jun 07 08:41:22 PM PDT 24
Peak memory 205808 kb
Host smart-d6688b70-3d33-4f1d-80c2-ece65de33339
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1793924555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.1793924555
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.3287183529
Short name T633
Test name
Test status
Simulation time 10065477811 ps
CPU time 12.52 seconds
Started Jun 07 08:40:58 PM PDT 24
Finished Jun 07 08:41:12 PM PDT 24
Peak memory 205768 kb
Host smart-1a92211a-34bf-4d53-92ad-c3f8a6e11414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32871
83529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.3287183529
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.1936275493
Short name T1765
Test name
Test status
Simulation time 10046240586 ps
CPU time 13.47 seconds
Started Jun 07 08:41:00 PM PDT 24
Finished Jun 07 08:41:15 PM PDT 24
Peak memory 205808 kb
Host smart-ec4ed332-2140-478d-ad41-6518292b105c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19362
75493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.1936275493
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.786101123
Short name T1182
Test name
Test status
Simulation time 10233947806 ps
CPU time 12.73 seconds
Started Jun 07 08:40:59 PM PDT 24
Finished Jun 07 08:41:13 PM PDT 24
Peak memory 205852 kb
Host smart-cbc39e13-5e4a-4050-a7bb-b81b452ffa25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78610
1123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.786101123
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.689208518
Short name T875
Test name
Test status
Simulation time 10065182462 ps
CPU time 13.99 seconds
Started Jun 07 08:41:04 PM PDT 24
Finished Jun 07 08:41:21 PM PDT 24
Peak memory 205844 kb
Host smart-3f063b6e-223e-4369-96ff-7361d36cd242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68920
8518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.689208518
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.387469
Short name T393
Test name
Test status
Simulation time 10052706098 ps
CPU time 13.37 seconds
Started Jun 07 08:41:00 PM PDT 24
Finished Jun 07 08:41:15 PM PDT 24
Peak memory 205736 kb
Host smart-d7b1b394-0156-4b50-85ed-2420b1a7dc19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38746
9 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.387469
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.3002008288
Short name T1971
Test name
Test status
Simulation time 10823912967 ps
CPU time 13.91 seconds
Started Jun 07 08:40:58 PM PDT 24
Finished Jun 07 08:41:13 PM PDT 24
Peak memory 205808 kb
Host smart-31db92ca-e690-4366-940f-02bc170e76fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30020
08288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.3002008288
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2915764660
Short name T767
Test name
Test status
Simulation time 10062001122 ps
CPU time 13.35 seconds
Started Jun 07 08:40:59 PM PDT 24
Finished Jun 07 08:41:14 PM PDT 24
Peak memory 205752 kb
Host smart-fd3a4382-2aaa-4588-a32f-54345c656f83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29157
64660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2915764660
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.2377682969
Short name T842
Test name
Test status
Simulation time 10147206375 ps
CPU time 13.37 seconds
Started Jun 07 08:41:09 PM PDT 24
Finished Jun 07 08:41:26 PM PDT 24
Peak memory 205844 kb
Host smart-a5d422aa-a378-4bf0-be51-f37e7c63d357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23776
82969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.2377682969
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2489522502
Short name T635
Test name
Test status
Simulation time 10046320715 ps
CPU time 13.75 seconds
Started Jun 07 08:41:09 PM PDT 24
Finished Jun 07 08:41:26 PM PDT 24
Peak memory 205908 kb
Host smart-468ccf84-c8df-41f1-9d41-da7c513a7bde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24895
22502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2489522502
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.83918387
Short name T383
Test name
Test status
Simulation time 10138386884 ps
CPU time 13 seconds
Started Jun 07 08:40:59 PM PDT 24
Finished Jun 07 08:41:14 PM PDT 24
Peak memory 205672 kb
Host smart-50ddf02c-7c12-4607-97b2-aba171c023db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83918
387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.83918387
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.2719014020
Short name T1294
Test name
Test status
Simulation time 10136599114 ps
CPU time 13.87 seconds
Started Jun 07 08:41:01 PM PDT 24
Finished Jun 07 08:41:17 PM PDT 24
Peak memory 205740 kb
Host smart-64b83ca6-0c32-4ce2-a1da-5ec598d56ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27190
14020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.2719014020
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.82743497
Short name T202
Test name
Test status
Simulation time 13161681689 ps
CPU time 16.03 seconds
Started Jun 07 08:40:59 PM PDT 24
Finished Jun 07 08:41:17 PM PDT 24
Peak memory 205816 kb
Host smart-a09506cc-24b8-409d-9198-cc6015d6bc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82743
497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.82743497
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.2173240295
Short name T602
Test name
Test status
Simulation time 10138786198 ps
CPU time 12.54 seconds
Started Jun 07 08:40:56 PM PDT 24
Finished Jun 07 08:41:10 PM PDT 24
Peak memory 205852 kb
Host smart-faaf2580-e3e6-42d5-9fd0-e749c089e465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21732
40295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2173240295
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.1360936454
Short name T672
Test name
Test status
Simulation time 19491210058 ps
CPU time 277.06 seconds
Started Jun 07 08:41:04 PM PDT 24
Finished Jun 07 08:45:43 PM PDT 24
Peak memory 205728 kb
Host smart-24dce7b0-b808-44ec-a093-ae5b65505986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13609
36454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.1360936454
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.953386821
Short name T1954
Test name
Test status
Simulation time 10044928020 ps
CPU time 12.44 seconds
Started Jun 07 08:41:06 PM PDT 24
Finished Jun 07 08:41:22 PM PDT 24
Peak memory 205860 kb
Host smart-8e334167-d135-4d6b-a050-a4f02931d83b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95338
6821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.953386821
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.395402999
Short name T1900
Test name
Test status
Simulation time 10083953962 ps
CPU time 12.8 seconds
Started Jun 07 08:41:04 PM PDT 24
Finished Jun 07 08:41:19 PM PDT 24
Peak memory 205940 kb
Host smart-dcbde7f3-d1a6-4988-af6a-7d9f9aa9c567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39540
2999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.395402999
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.1680751710
Short name T1145
Test name
Test status
Simulation time 10068373951 ps
CPU time 12.48 seconds
Started Jun 07 08:41:05 PM PDT 24
Finished Jun 07 08:41:20 PM PDT 24
Peak memory 205844 kb
Host smart-cae0a318-425f-4070-aa7e-50c6eda776fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16807
51710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.1680751710
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.4031017259
Short name T902
Test name
Test status
Simulation time 10073345463 ps
CPU time 13.98 seconds
Started Jun 07 08:41:10 PM PDT 24
Finished Jun 07 08:41:28 PM PDT 24
Peak memory 205744 kb
Host smart-9c110219-685a-4c4e-a58a-30f1e5e76b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40310
17259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.4031017259
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1971138276
Short name T615
Test name
Test status
Simulation time 10075348261 ps
CPU time 15.44 seconds
Started Jun 07 08:41:05 PM PDT 24
Finished Jun 07 08:41:23 PM PDT 24
Peak memory 205852 kb
Host smart-9127b76e-e92c-4276-b9aa-c15d5557acd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19711
38276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1971138276
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.2054135035
Short name T1426
Test name
Test status
Simulation time 10055406498 ps
CPU time 13.45 seconds
Started Jun 07 08:41:10 PM PDT 24
Finished Jun 07 08:41:27 PM PDT 24
Peak memory 205984 kb
Host smart-e97b1f2c-d498-4978-9d9f-8a01eaf6d8ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20541
35035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.2054135035
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_eop_single_bit_handling.2991351617
Short name T1329
Test name
Test status
Simulation time 10080144241 ps
CPU time 13.14 seconds
Started Jun 07 08:41:10 PM PDT 24
Finished Jun 07 08:41:26 PM PDT 24
Peak memory 205876 kb
Host smart-ea0edfeb-e0d4-4c9b-9d84-457fa5779649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29913
51617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_eop_single_bit_handling.2991351617
Directory /workspace/2.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.301196565
Short name T643
Test name
Test status
Simulation time 10063369658 ps
CPU time 12.94 seconds
Started Jun 07 08:41:10 PM PDT 24
Finished Jun 07 08:41:27 PM PDT 24
Peak memory 205856 kb
Host smart-f34bc295-25bc-4e2a-a26a-af025f0c5360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30119
6565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.301196565
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.3517061192
Short name T1090
Test name
Test status
Simulation time 10064807743 ps
CPU time 14.26 seconds
Started Jun 07 08:41:10 PM PDT 24
Finished Jun 07 08:41:28 PM PDT 24
Peak memory 205832 kb
Host smart-6e2a6999-3455-428a-a481-6e09ac25bbf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35170
61192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.3517061192
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.1544201753
Short name T1262
Test name
Test status
Simulation time 27939386048 ps
CPU time 53.98 seconds
Started Jun 07 08:41:09 PM PDT 24
Finished Jun 07 08:42:06 PM PDT 24
Peak memory 205824 kb
Host smart-b65e2b15-e2f5-4104-85e0-6caf1f2e9163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15442
01753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.1544201753
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.1451314569
Short name T392
Test name
Test status
Simulation time 10088146337 ps
CPU time 14.09 seconds
Started Jun 07 08:41:04 PM PDT 24
Finished Jun 07 08:41:20 PM PDT 24
Peak memory 205820 kb
Host smart-d83d8fdf-83c4-48d6-9759-6149ba4094f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14513
14569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.1451314569
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2379123575
Short name T1596
Test name
Test status
Simulation time 10066250378 ps
CPU time 12.53 seconds
Started Jun 07 08:41:05 PM PDT 24
Finished Jun 07 08:41:21 PM PDT 24
Peak memory 205748 kb
Host smart-b4ec36c5-367b-4267-bbed-e44d70d17b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23791
23575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2379123575
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.3626210275
Short name T1854
Test name
Test status
Simulation time 32416954354 ps
CPU time 191.62 seconds
Started Jun 07 08:41:03 PM PDT 24
Finished Jun 07 08:44:17 PM PDT 24
Peak memory 205916 kb
Host smart-1667db62-ec3b-4a7f-ad59-0d79e3218dc6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3626210275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.3626210275
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.1606902919
Short name T2030
Test name
Test status
Simulation time 28893327169 ps
CPU time 428.89 seconds
Started Jun 07 08:41:10 PM PDT 24
Finished Jun 07 08:48:23 PM PDT 24
Peak memory 205876 kb
Host smart-a45a77ed-47e0-4281-be08-5aa3ad367588
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1606902919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.1606902919
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.768990451
Short name T1310
Test name
Test status
Simulation time 26179274291 ps
CPU time 136.29 seconds
Started Jun 07 08:41:05 PM PDT 24
Finished Jun 07 08:43:24 PM PDT 24
Peak memory 205880 kb
Host smart-f96df157-7943-4cb5-928d-26e92271bbf3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=768990451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.768990451
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.1005461109
Short name T1398
Test name
Test status
Simulation time 10060554686 ps
CPU time 15.61 seconds
Started Jun 07 08:41:04 PM PDT 24
Finished Jun 07 08:41:22 PM PDT 24
Peak memory 205768 kb
Host smart-9bf0abad-c703-4bb5-b11b-a4c2ce23962e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10054
61109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.1005461109
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.1804425842
Short name T681
Test name
Test status
Simulation time 10057478390 ps
CPU time 13.26 seconds
Started Jun 07 08:41:04 PM PDT 24
Finished Jun 07 08:41:19 PM PDT 24
Peak memory 205748 kb
Host smart-1542d379-6193-40e9-ab11-f216042fce38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18044
25842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.1804425842
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.660502665
Short name T186
Test name
Test status
Simulation time 447167239 ps
CPU time 1.27 seconds
Started Jun 07 08:41:10 PM PDT 24
Finished Jun 07 08:41:15 PM PDT 24
Peak memory 221856 kb
Host smart-23c371f1-4416-446d-901f-5d30bfbc30dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=660502665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.660502665
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.3823038526
Short name T1537
Test name
Test status
Simulation time 10090107826 ps
CPU time 12.87 seconds
Started Jun 07 08:41:12 PM PDT 24
Finished Jun 07 08:41:28 PM PDT 24
Peak memory 205852 kb
Host smart-5cc993cb-f8c2-47fd-98d0-36805c6670d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38230
38526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.3823038526
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.2552678954
Short name T1606
Test name
Test status
Simulation time 10053463149 ps
CPU time 13.14 seconds
Started Jun 07 08:41:13 PM PDT 24
Finished Jun 07 08:41:29 PM PDT 24
Peak memory 205772 kb
Host smart-acca45de-9a61-4f22-88a6-e0bd266bb598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25526
78954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.2552678954
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.882808064
Short name T135
Test name
Test status
Simulation time 10141087119 ps
CPU time 15.11 seconds
Started Jun 07 08:40:58 PM PDT 24
Finished Jun 07 08:41:15 PM PDT 24
Peak memory 205840 kb
Host smart-1a0572e1-2ae4-45ac-9b96-a75fe1524a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88280
8064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.882808064
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.1844831815
Short name T703
Test name
Test status
Simulation time 10094085635 ps
CPU time 12.63 seconds
Started Jun 07 08:41:12 PM PDT 24
Finished Jun 07 08:41:28 PM PDT 24
Peak memory 205804 kb
Host smart-9adb32f9-dab3-4182-baf2-aa03d337e216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18448
31815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.1844831815
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.1247425508
Short name T1970
Test name
Test status
Simulation time 10112133605 ps
CPU time 13.38 seconds
Started Jun 07 08:41:10 PM PDT 24
Finished Jun 07 08:41:27 PM PDT 24
Peak memory 205772 kb
Host smart-d5a0ad2b-a72d-4737-9ec1-62e14648c0c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12474
25508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.1247425508
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.1561984175
Short name T442
Test name
Test status
Simulation time 24162115258 ps
CPU time 399.25 seconds
Started Jun 07 08:41:10 PM PDT 24
Finished Jun 07 08:47:53 PM PDT 24
Peak memory 205772 kb
Host smart-86d84b2d-6435-4bee-b2af-8c7205888c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15619
84175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.1561984175
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.2509055976
Short name T161
Test name
Test status
Simulation time 23976219381 ps
CPU time 113.14 seconds
Started Jun 07 08:41:02 PM PDT 24
Finished Jun 07 08:42:57 PM PDT 24
Peak memory 205856 kb
Host smart-a621b3ba-8aa4-429b-95bd-0744a94b3e60
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509055976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_
traffic.2509055976
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.622549673
Short name T535
Test name
Test status
Simulation time 10138562538 ps
CPU time 14.38 seconds
Started Jun 07 08:44:47 PM PDT 24
Finished Jun 07 08:45:04 PM PDT 24
Peak memory 205892 kb
Host smart-6b3a5109-7d65-43a7-9d8f-1d26176f6473
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=622549673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.622549673
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.1781935686
Short name T411
Test name
Test status
Simulation time 10075306318 ps
CPU time 14.35 seconds
Started Jun 07 08:44:40 PM PDT 24
Finished Jun 07 08:44:57 PM PDT 24
Peak memory 205904 kb
Host smart-97e5116f-2044-4285-bc64-424a7f3eecc9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1781935686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.1781935686
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.1217046117
Short name T1374
Test name
Test status
Simulation time 10072194152 ps
CPU time 12.71 seconds
Started Jun 07 08:44:41 PM PDT 24
Finished Jun 07 08:44:56 PM PDT 24
Peak memory 205888 kb
Host smart-d112b5f5-b88e-4e20-ae52-a5055d2bf8e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12170
46117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.1217046117
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.458338108
Short name T1703
Test name
Test status
Simulation time 13752270285 ps
CPU time 16.69 seconds
Started Jun 07 08:44:36 PM PDT 24
Finished Jun 07 08:44:56 PM PDT 24
Peak memory 205828 kb
Host smart-e6b00f54-db6a-4def-b484-88c73ae2e111
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=458338108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.458338108
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.2622573599
Short name T774
Test name
Test status
Simulation time 23213090001 ps
CPU time 23.83 seconds
Started Jun 07 08:44:43 PM PDT 24
Finished Jun 07 08:45:10 PM PDT 24
Peak memory 205820 kb
Host smart-8f4d7121-85a1-44a9-b2d3-caad64dab77a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2622573599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.2622573599
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3996410699
Short name T998
Test name
Test status
Simulation time 10059745597 ps
CPU time 13.08 seconds
Started Jun 07 08:44:43 PM PDT 24
Finished Jun 07 08:44:59 PM PDT 24
Peak memory 205876 kb
Host smart-886a29bd-7db7-41a5-afeb-5e0b4dcdd12e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39964
10699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3996410699
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.1888548575
Short name T1531
Test name
Test status
Simulation time 10059918649 ps
CPU time 13.33 seconds
Started Jun 07 08:44:42 PM PDT 24
Finished Jun 07 08:44:58 PM PDT 24
Peak memory 205852 kb
Host smart-3bca5e41-7017-48f4-bd4c-373aa0e127c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18885
48575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.1888548575
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.1815403029
Short name T323
Test name
Test status
Simulation time 10551917762 ps
CPU time 13.82 seconds
Started Jun 07 08:44:42 PM PDT 24
Finished Jun 07 08:44:57 PM PDT 24
Peak memory 205876 kb
Host smart-f9f3f09c-55a0-44b3-bb97-1827f2d51abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18154
03029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.1815403029
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.1855643674
Short name T457
Test name
Test status
Simulation time 10076798720 ps
CPU time 13.73 seconds
Started Jun 07 08:44:47 PM PDT 24
Finished Jun 07 08:45:02 PM PDT 24
Peak memory 205856 kb
Host smart-357cdd35-e2ce-4545-b0f3-5764d2cd7cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18556
43674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.1855643674
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.4286441751
Short name T1572
Test name
Test status
Simulation time 10063127244 ps
CPU time 13.96 seconds
Started Jun 07 08:44:42 PM PDT 24
Finished Jun 07 08:44:59 PM PDT 24
Peak memory 205724 kb
Host smart-4bd0da4b-5747-4924-8f9a-96f9604e86b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42864
41751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.4286441751
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.1246753957
Short name T1351
Test name
Test status
Simulation time 10778280425 ps
CPU time 15.18 seconds
Started Jun 07 08:44:43 PM PDT 24
Finished Jun 07 08:45:01 PM PDT 24
Peak memory 205912 kb
Host smart-eb96fb84-cd2e-42bf-849b-f70af505840d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12467
53957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.1246753957
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.3342312598
Short name T1464
Test name
Test status
Simulation time 10178985313 ps
CPU time 13.94 seconds
Started Jun 07 08:44:40 PM PDT 24
Finished Jun 07 08:44:56 PM PDT 24
Peak memory 205812 kb
Host smart-12485cbf-ec28-4674-a693-fb2a78f2c2da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33423
12598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3342312598
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.2638332529
Short name T1332
Test name
Test status
Simulation time 10080299494 ps
CPU time 13.03 seconds
Started Jun 07 08:44:43 PM PDT 24
Finished Jun 07 08:44:58 PM PDT 24
Peak memory 205732 kb
Host smart-68d8fdaa-2dea-4696-b5ad-f5ede897e16f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26383
32529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.2638332529
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.1862351084
Short name T1355
Test name
Test status
Simulation time 10133629088 ps
CPU time 12.69 seconds
Started Jun 07 08:44:41 PM PDT 24
Finished Jun 07 08:44:55 PM PDT 24
Peak memory 205900 kb
Host smart-ec60c719-862d-4995-b57c-c00a8991b129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18623
51084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.1862351084
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.3853189370
Short name T410
Test name
Test status
Simulation time 10124510965 ps
CPU time 14.03 seconds
Started Jun 07 08:44:39 PM PDT 24
Finished Jun 07 08:44:55 PM PDT 24
Peak memory 205812 kb
Host smart-9c5fcfd1-cce8-4b42-bafa-553e83bbe0a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38531
89370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3853189370
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.176327200
Short name T1699
Test name
Test status
Simulation time 13210040555 ps
CPU time 16.09 seconds
Started Jun 07 08:44:43 PM PDT 24
Finished Jun 07 08:45:02 PM PDT 24
Peak memory 205724 kb
Host smart-ac5385a1-4c8b-4eed-b7ae-c097a2b2f1e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17632
7200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.176327200
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1249331308
Short name T1552
Test name
Test status
Simulation time 10133221526 ps
CPU time 13.46 seconds
Started Jun 07 08:44:42 PM PDT 24
Finished Jun 07 08:44:58 PM PDT 24
Peak memory 205868 kb
Host smart-cc321666-720a-4fa6-ae21-b6c2ebc29525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12493
31308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1249331308
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.4098386169
Short name T1763
Test name
Test status
Simulation time 24659936822 ps
CPU time 435.27 seconds
Started Jun 07 08:44:42 PM PDT 24
Finished Jun 07 08:52:00 PM PDT 24
Peak memory 205788 kb
Host smart-e926afce-4643-487a-b65b-d024602bd8d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40983
86169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.4098386169
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1161164039
Short name T466
Test name
Test status
Simulation time 10050332142 ps
CPU time 14.69 seconds
Started Jun 07 08:44:46 PM PDT 24
Finished Jun 07 08:45:03 PM PDT 24
Peak memory 205780 kb
Host smart-6c8cfa80-4c40-43b8-8f29-a600d31ce591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11611
64039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1161164039
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.3573930584
Short name T115
Test name
Test status
Simulation time 10124323593 ps
CPU time 13.61 seconds
Started Jun 07 08:44:41 PM PDT 24
Finished Jun 07 08:44:56 PM PDT 24
Peak memory 205812 kb
Host smart-e1c146b8-090f-4556-9c67-b7cad7b36258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35739
30584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.3573930584
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.3719344094
Short name T1932
Test name
Test status
Simulation time 10052955769 ps
CPU time 12.26 seconds
Started Jun 07 08:44:38 PM PDT 24
Finished Jun 07 08:44:53 PM PDT 24
Peak memory 205752 kb
Host smart-51a80235-30f7-4a89-9f90-501af241196e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37193
44094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.3719344094
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.1568845475
Short name T935
Test name
Test status
Simulation time 10096459603 ps
CPU time 14.23 seconds
Started Jun 07 08:44:42 PM PDT 24
Finished Jun 07 08:44:58 PM PDT 24
Peak memory 205788 kb
Host smart-a0644e75-b6c4-46bb-83bc-d96f9c270c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15688
45475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1568845475
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.2863244082
Short name T496
Test name
Test status
Simulation time 10063400902 ps
CPU time 15.53 seconds
Started Jun 07 08:44:40 PM PDT 24
Finished Jun 07 08:44:58 PM PDT 24
Peak memory 205748 kb
Host smart-bd0b3459-6796-4958-8366-e6c0da62441a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28632
44082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.2863244082
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_eop_single_bit_handling.1022958921
Short name T1618
Test name
Test status
Simulation time 10078286862 ps
CPU time 13.43 seconds
Started Jun 07 08:44:42 PM PDT 24
Finished Jun 07 08:44:58 PM PDT 24
Peak memory 205788 kb
Host smart-d332e2f6-0805-49b0-a1e6-e009ee6f0fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10229
58921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_eop_single_bit_handling.1022958921
Directory /workspace/20.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1605603072
Short name T1435
Test name
Test status
Simulation time 10055901642 ps
CPU time 12.98 seconds
Started Jun 07 08:44:41 PM PDT 24
Finished Jun 07 08:44:56 PM PDT 24
Peak memory 205836 kb
Host smart-be8fd48d-5aa8-4933-8145-5ce792aa5535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16056
03072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.1605603072
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2507834841
Short name T27
Test name
Test status
Simulation time 10047220816 ps
CPU time 12.44 seconds
Started Jun 07 08:44:44 PM PDT 24
Finished Jun 07 08:44:59 PM PDT 24
Peak memory 205756 kb
Host smart-83c6a8ea-4fb7-4ef7-b566-bdbfe4e76ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25078
34841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2507834841
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3575185649
Short name T600
Test name
Test status
Simulation time 21645672980 ps
CPU time 38.56 seconds
Started Jun 07 08:44:40 PM PDT 24
Finished Jun 07 08:45:21 PM PDT 24
Peak memory 205824 kb
Host smart-5671896d-1591-455b-a007-72808653fd9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35751
85649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3575185649
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.1880156064
Short name T667
Test name
Test status
Simulation time 10085406533 ps
CPU time 14.58 seconds
Started Jun 07 08:44:42 PM PDT 24
Finished Jun 07 08:44:59 PM PDT 24
Peak memory 205932 kb
Host smart-12f8c9c8-1b49-41a9-afa6-7d14e2709ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18801
56064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.1880156064
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1790062216
Short name T719
Test name
Test status
Simulation time 10190025436 ps
CPU time 16.04 seconds
Started Jun 07 08:44:44 PM PDT 24
Finished Jun 07 08:45:03 PM PDT 24
Peak memory 205872 kb
Host smart-a017cad5-57d6-4dd8-9d88-a72fbfced788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17900
62216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1790062216
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.2481329929
Short name T726
Test name
Test status
Simulation time 10097235980 ps
CPU time 12.89 seconds
Started Jun 07 08:44:44 PM PDT 24
Finished Jun 07 08:44:59 PM PDT 24
Peak memory 205852 kb
Host smart-6253d4f5-7750-4e28-b2ad-ac9112824725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24813
29929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.2481329929
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.2950962547
Short name T841
Test name
Test status
Simulation time 10066047873 ps
CPU time 16.31 seconds
Started Jun 07 08:44:41 PM PDT 24
Finished Jun 07 08:45:00 PM PDT 24
Peak memory 205780 kb
Host smart-601fa84b-eb70-49ba-960b-6c6eabb82afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29509
62547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.2950962547
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1102747359
Short name T640
Test name
Test status
Simulation time 10102574831 ps
CPU time 12.56 seconds
Started Jun 07 08:44:43 PM PDT 24
Finished Jun 07 08:44:58 PM PDT 24
Peak memory 205800 kb
Host smart-66aeab76-a7cc-4fb5-b670-1177816ccafd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11027
47359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1102747359
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1834208640
Short name T959
Test name
Test status
Simulation time 10064443912 ps
CPU time 12.91 seconds
Started Jun 07 08:44:38 PM PDT 24
Finished Jun 07 08:44:54 PM PDT 24
Peak memory 205856 kb
Host smart-4c758b1f-aec5-4f30-9966-d9bbd46d004d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18342
08640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1834208640
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.3757497322
Short name T941
Test name
Test status
Simulation time 10114837876 ps
CPU time 14.23 seconds
Started Jun 07 08:44:34 PM PDT 24
Finished Jun 07 08:44:52 PM PDT 24
Peak memory 205692 kb
Host smart-3e2ce4d5-4068-4e50-94f0-b4791f50d523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37574
97322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.3757497322
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.2385681318
Short name T1714
Test name
Test status
Simulation time 10165348284 ps
CPU time 14.11 seconds
Started Jun 07 08:44:41 PM PDT 24
Finished Jun 07 08:44:57 PM PDT 24
Peak memory 205788 kb
Host smart-bcbc0a72-fc56-4f8d-bc4c-beb032d16316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23856
81318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.2385681318
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.4246688839
Short name T1300
Test name
Test status
Simulation time 10074759449 ps
CPU time 13.7 seconds
Started Jun 07 08:44:39 PM PDT 24
Finished Jun 07 08:44:55 PM PDT 24
Peak memory 205752 kb
Host smart-d44c0597-9d51-4f4c-8dd7-9865b612cac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42466
88839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.4246688839
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.2103810357
Short name T1807
Test name
Test status
Simulation time 22949749422 ps
CPU time 111.39 seconds
Started Jun 07 08:44:45 PM PDT 24
Finished Jun 07 08:46:39 PM PDT 24
Peak memory 205852 kb
Host smart-103f8b26-b971-4775-aad0-60a5c5e6a7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21038
10357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.2103810357
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.3108571760
Short name T1865
Test name
Test status
Simulation time 10140533383 ps
CPU time 13.54 seconds
Started Jun 07 08:44:55 PM PDT 24
Finished Jun 07 08:45:12 PM PDT 24
Peak memory 205600 kb
Host smart-6f3f8be7-112c-462e-94dd-c7815d2b0dc8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3108571760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.3108571760
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.1491949844
Short name T325
Test name
Test status
Simulation time 10064696683 ps
CPU time 14.4 seconds
Started Jun 07 08:44:52 PM PDT 24
Finished Jun 07 08:45:09 PM PDT 24
Peak memory 205828 kb
Host smart-a1fdfd7c-b718-4eb1-bc49-3f83bf946eb2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1491949844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.1491949844
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.2474187025
Short name T896
Test name
Test status
Simulation time 10156792588 ps
CPU time 14.52 seconds
Started Jun 07 08:44:54 PM PDT 24
Finished Jun 07 08:45:11 PM PDT 24
Peak memory 205844 kb
Host smart-6ff0967e-8b83-4caf-95ec-c8f4db008f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24741
87025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.2474187025
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.738511035
Short name T211
Test name
Test status
Simulation time 13643601612 ps
CPU time 20.12 seconds
Started Jun 07 08:44:48 PM PDT 24
Finished Jun 07 08:45:11 PM PDT 24
Peak memory 205160 kb
Host smart-afb897e4-48b9-4cac-8816-4d57417b7c91
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=738511035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.738511035
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.2486467191
Short name T1296
Test name
Test status
Simulation time 23286665367 ps
CPU time 23.49 seconds
Started Jun 07 08:44:47 PM PDT 24
Finished Jun 07 08:45:13 PM PDT 24
Peak memory 205840 kb
Host smart-278af6b0-2bb4-493f-a7cf-2df2c0e6aaf8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2486467191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.2486467191
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.1074736979
Short name T652
Test name
Test status
Simulation time 10058731467 ps
CPU time 14.16 seconds
Started Jun 07 08:44:48 PM PDT 24
Finished Jun 07 08:45:04 PM PDT 24
Peak memory 205840 kb
Host smart-e2cf17df-aa1d-41d9-8c06-0d0023b99c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10747
36979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.1074736979
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.1130949733
Short name T61
Test name
Test status
Simulation time 10054653574 ps
CPU time 16.27 seconds
Started Jun 07 08:44:46 PM PDT 24
Finished Jun 07 08:45:05 PM PDT 24
Peak memory 205768 kb
Host smart-c1bf2244-61ed-49c9-9121-cde163bebcc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11309
49733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.1130949733
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.563356280
Short name T1547
Test name
Test status
Simulation time 11070927530 ps
CPU time 15.04 seconds
Started Jun 07 08:44:50 PM PDT 24
Finished Jun 07 08:45:08 PM PDT 24
Peak memory 205856 kb
Host smart-ae31c280-4a62-45c5-9ac9-b47f9db90c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56335
6280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.563356280
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.1641957918
Short name T1259
Test name
Test status
Simulation time 10069403190 ps
CPU time 15.91 seconds
Started Jun 07 08:44:47 PM PDT 24
Finished Jun 07 08:45:05 PM PDT 24
Peak memory 205916 kb
Host smart-4693a8bf-1d07-445b-b077-bb99c18f080f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16419
57918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.1641957918
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.2878402934
Short name T1385
Test name
Test status
Simulation time 10086036281 ps
CPU time 12.56 seconds
Started Jun 07 08:44:49 PM PDT 24
Finished Jun 07 08:45:04 PM PDT 24
Peak memory 205828 kb
Host smart-78affcec-7b29-463e-a485-e16c123c3da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28784
02934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.2878402934
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.546526159
Short name T1462
Test name
Test status
Simulation time 10733525666 ps
CPU time 13.99 seconds
Started Jun 07 08:44:57 PM PDT 24
Finished Jun 07 08:45:14 PM PDT 24
Peak memory 205764 kb
Host smart-1ab6dc93-aa22-4149-881b-8dac9cfc1e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54652
6159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.546526159
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1763137890
Short name T610
Test name
Test status
Simulation time 10137236614 ps
CPU time 13.85 seconds
Started Jun 07 08:44:47 PM PDT 24
Finished Jun 07 08:45:03 PM PDT 24
Peak memory 205768 kb
Host smart-1b3567a6-3730-4738-a146-3be74c361119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17631
37890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1763137890
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.2983238938
Short name T707
Test name
Test status
Simulation time 10139367073 ps
CPU time 13.35 seconds
Started Jun 07 08:44:55 PM PDT 24
Finished Jun 07 08:45:11 PM PDT 24
Peak memory 205816 kb
Host smart-f8fe8810-054e-4ddf-b40f-6d7ebec41e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29832
38938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.2983238938
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.1206317770
Short name T690
Test name
Test status
Simulation time 10042238820 ps
CPU time 14.89 seconds
Started Jun 07 08:44:56 PM PDT 24
Finished Jun 07 08:45:14 PM PDT 24
Peak memory 205904 kb
Host smart-864dec2f-ff99-49a5-9abb-c71338bdda1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12063
17770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.1206317770
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.991180052
Short name T316
Test name
Test status
Simulation time 10093909634 ps
CPU time 13.08 seconds
Started Jun 07 08:44:47 PM PDT 24
Finished Jun 07 08:45:02 PM PDT 24
Peak memory 205800 kb
Host smart-ae9e3b1c-1ca5-4d25-a893-7a4a0ca3556b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99118
0052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.991180052
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.1289348942
Short name T1155
Test name
Test status
Simulation time 10083399170 ps
CPU time 14.73 seconds
Started Jun 07 08:44:47 PM PDT 24
Finished Jun 07 08:45:04 PM PDT 24
Peak memory 205804 kb
Host smart-3955c8d0-50e1-4dd7-8276-708325f1a25f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12893
48942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.1289348942
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.1222310852
Short name T688
Test name
Test status
Simulation time 13236477727 ps
CPU time 19.71 seconds
Started Jun 07 08:44:47 PM PDT 24
Finished Jun 07 08:45:09 PM PDT 24
Peak memory 205880 kb
Host smart-6f109db1-53e3-4ff6-bd52-ef04c726716a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12223
10852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.1222310852
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.3541671705
Short name T407
Test name
Test status
Simulation time 10086878230 ps
CPU time 14.07 seconds
Started Jun 07 08:44:49 PM PDT 24
Finished Jun 07 08:45:05 PM PDT 24
Peak memory 205776 kb
Host smart-c6f6e84c-f1b9-4670-bbbe-3cf735e6f38f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35416
71705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.3541671705
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.131325477
Short name T1482
Test name
Test status
Simulation time 19810360808 ps
CPU time 275.37 seconds
Started Jun 07 08:44:45 PM PDT 24
Finished Jun 07 08:49:23 PM PDT 24
Peak memory 205808 kb
Host smart-7df581d6-09f4-4b95-9a44-e1ef7a679c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13132
5477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.131325477
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.2753339968
Short name T1894
Test name
Test status
Simulation time 10079816886 ps
CPU time 12.79 seconds
Started Jun 07 08:44:49 PM PDT 24
Finished Jun 07 08:45:04 PM PDT 24
Peak memory 205868 kb
Host smart-53adc3fd-b88c-475d-a02c-c3ea157313c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27533
39968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.2753339968
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3247105616
Short name T109
Test name
Test status
Simulation time 10142338326 ps
CPU time 14.53 seconds
Started Jun 07 08:44:47 PM PDT 24
Finished Jun 07 08:45:04 PM PDT 24
Peak memory 205748 kb
Host smart-79953f41-6b46-41fb-ac51-3085f5827ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32471
05616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3247105616
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.2821736851
Short name T1002
Test name
Test status
Simulation time 10082614274 ps
CPU time 14.76 seconds
Started Jun 07 08:44:48 PM PDT 24
Finished Jun 07 08:45:05 PM PDT 24
Peak memory 205924 kb
Host smart-6c7e7968-98df-46ab-8f26-7ebd44d5f6c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28217
36851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.2821736851
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.381006169
Short name T1978
Test name
Test status
Simulation time 10115399941 ps
CPU time 13.67 seconds
Started Jun 07 08:44:57 PM PDT 24
Finished Jun 07 08:45:14 PM PDT 24
Peak memory 205868 kb
Host smart-0ebac5e6-8393-4fdc-8a24-84a950c09e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38100
6169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.381006169
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.810369697
Short name T542
Test name
Test status
Simulation time 10077929067 ps
CPU time 13.95 seconds
Started Jun 07 08:44:48 PM PDT 24
Finished Jun 07 08:45:05 PM PDT 24
Peak memory 205096 kb
Host smart-93174003-daaf-43ea-9a52-500852724684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81036
9697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.810369697
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.3482299073
Short name T1972
Test name
Test status
Simulation time 10058908014 ps
CPU time 13.14 seconds
Started Jun 07 08:44:55 PM PDT 24
Finished Jun 07 08:45:11 PM PDT 24
Peak memory 205828 kb
Host smart-49bd4b1c-0fe6-423b-837e-be6ae81f6c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34822
99073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.3482299073
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_eop_single_bit_handling.1931024737
Short name T988
Test name
Test status
Simulation time 10100680726 ps
CPU time 13.56 seconds
Started Jun 07 08:44:48 PM PDT 24
Finished Jun 07 08:45:04 PM PDT 24
Peak memory 205740 kb
Host smart-3e35299e-66bb-4bcb-8803-ec68de1b1ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19310
24737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_eop_single_bit_handling.1931024737
Directory /workspace/21.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.3133683409
Short name T1348
Test name
Test status
Simulation time 10087893148 ps
CPU time 15.35 seconds
Started Jun 07 08:44:50 PM PDT 24
Finished Jun 07 08:45:08 PM PDT 24
Peak memory 205836 kb
Host smart-58369428-a2b1-4925-a43d-8c9c5fde7dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31336
83409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.3133683409
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2155942549
Short name T37
Test name
Test status
Simulation time 10064409155 ps
CPU time 13.17 seconds
Started Jun 07 08:44:52 PM PDT 24
Finished Jun 07 08:45:08 PM PDT 24
Peak memory 205792 kb
Host smart-627012b6-c7d3-4d4f-bf52-9a8019045946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21559
42549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2155942549
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.1211393536
Short name T1845
Test name
Test status
Simulation time 33061268635 ps
CPU time 61.04 seconds
Started Jun 07 08:44:47 PM PDT 24
Finished Jun 07 08:45:50 PM PDT 24
Peak memory 205868 kb
Host smart-9a6a841a-9916-4043-96c5-e006840bf2fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12113
93536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.1211393536
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.1469011576
Short name T1940
Test name
Test status
Simulation time 10095889458 ps
CPU time 14.08 seconds
Started Jun 07 08:44:49 PM PDT 24
Finished Jun 07 08:45:06 PM PDT 24
Peak memory 205788 kb
Host smart-5445624f-ca8e-4615-ba4e-f41b366eb85d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14690
11576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.1469011576
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.854812035
Short name T779
Test name
Test status
Simulation time 10120950699 ps
CPU time 13.83 seconds
Started Jun 07 08:44:50 PM PDT 24
Finished Jun 07 08:45:06 PM PDT 24
Peak memory 205772 kb
Host smart-cb7182c5-29f4-4a80-bf8e-5d887d0ae4e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85481
2035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.854812035
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.570709609
Short name T1721
Test name
Test status
Simulation time 10130764434 ps
CPU time 13.05 seconds
Started Jun 07 08:44:48 PM PDT 24
Finished Jun 07 08:45:04 PM PDT 24
Peak memory 205736 kb
Host smart-9d4d89f9-5765-4bd3-8da0-e0ea4b9e1a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57070
9609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.570709609
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.1338493963
Short name T1238
Test name
Test status
Simulation time 10036979687 ps
CPU time 14.54 seconds
Started Jun 07 08:44:49 PM PDT 24
Finished Jun 07 08:45:06 PM PDT 24
Peak memory 205820 kb
Host smart-b8d52840-470a-4206-9d42-042960f123bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13384
93963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.1338493963
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.1932542162
Short name T700
Test name
Test status
Simulation time 10056520614 ps
CPU time 14.04 seconds
Started Jun 07 08:44:55 PM PDT 24
Finished Jun 07 08:45:11 PM PDT 24
Peak memory 205768 kb
Host smart-428e27ad-fc5d-494e-a014-89299ca71fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19325
42162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.1932542162
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.712485353
Short name T888
Test name
Test status
Simulation time 10046211662 ps
CPU time 15.86 seconds
Started Jun 07 08:44:50 PM PDT 24
Finished Jun 07 08:45:09 PM PDT 24
Peak memory 205868 kb
Host smart-6b39ad80-5660-4c99-8639-68a7e9db71c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71248
5353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.712485353
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1147243594
Short name T1413
Test name
Test status
Simulation time 10074404997 ps
CPU time 14.5 seconds
Started Jun 07 08:44:51 PM PDT 24
Finished Jun 07 08:45:08 PM PDT 24
Peak memory 205804 kb
Host smart-506adf55-3d81-4f62-b2f4-f65d122d856f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11472
43594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1147243594
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.4290374784
Short name T1141
Test name
Test status
Simulation time 10065957829 ps
CPU time 13.57 seconds
Started Jun 07 08:44:48 PM PDT 24
Finished Jun 07 08:45:04 PM PDT 24
Peak memory 205780 kb
Host smart-96e00ff4-4892-4a45-8015-c0858a46178c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42903
74784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.4290374784
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.849646125
Short name T1269
Test name
Test status
Simulation time 10117315335 ps
CPU time 16.14 seconds
Started Jun 07 08:44:49 PM PDT 24
Finished Jun 07 08:45:08 PM PDT 24
Peak memory 205908 kb
Host smart-420c6bfd-00cd-436d-b65a-e825be136153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84964
6125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.849646125
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.170875771
Short name T1809
Test name
Test status
Simulation time 14392079554 ps
CPU time 138.18 seconds
Started Jun 07 08:44:51 PM PDT 24
Finished Jun 07 08:47:12 PM PDT 24
Peak memory 205788 kb
Host smart-5bfab73d-36fe-43cd-b5e5-8a4705366871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17087
5771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.170875771
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.2014124191
Short name T65
Test name
Test status
Simulation time 10145680143 ps
CPU time 13.7 seconds
Started Jun 07 08:45:02 PM PDT 24
Finished Jun 07 08:45:19 PM PDT 24
Peak memory 205896 kb
Host smart-72ee8865-4a31-437b-a3b0-04ae0fafe6f9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2014124191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.2014124191
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.3579202688
Short name T1499
Test name
Test status
Simulation time 10089861583 ps
CPU time 12.75 seconds
Started Jun 07 08:45:01 PM PDT 24
Finished Jun 07 08:45:18 PM PDT 24
Peak memory 205724 kb
Host smart-41f07abe-8038-4a0f-b637-c7aba3559509
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3579202688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.3579202688
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.521603692
Short name T308
Test name
Test status
Simulation time 10168395390 ps
CPU time 12.98 seconds
Started Jun 07 08:44:59 PM PDT 24
Finished Jun 07 08:45:15 PM PDT 24
Peak memory 205716 kb
Host smart-64baa8d4-db98-4685-9170-7ae97186522a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52160
3692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.521603692
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.3658385605
Short name T1210
Test name
Test status
Simulation time 13846753419 ps
CPU time 19.56 seconds
Started Jun 07 08:44:56 PM PDT 24
Finished Jun 07 08:45:18 PM PDT 24
Peak memory 205904 kb
Host smart-3ea7bab9-a728-4c58-a7fe-0ce9dbb09454
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3658385605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.3658385605
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.4071433815
Short name T1847
Test name
Test status
Simulation time 23326156681 ps
CPU time 30.67 seconds
Started Jun 07 08:44:54 PM PDT 24
Finished Jun 07 08:45:27 PM PDT 24
Peak memory 205836 kb
Host smart-ec8b2f71-3636-41af-91b6-e712afed500a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4071433815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.4071433815
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3395725236
Short name T1116
Test name
Test status
Simulation time 10051638876 ps
CPU time 13.77 seconds
Started Jun 07 08:44:54 PM PDT 24
Finished Jun 07 08:45:11 PM PDT 24
Peak memory 205740 kb
Host smart-7427b89a-de87-4db6-a893-d22186c42f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33957
25236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3395725236
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.335865087
Short name T1424
Test name
Test status
Simulation time 10983098536 ps
CPU time 15.58 seconds
Started Jun 07 08:44:54 PM PDT 24
Finished Jun 07 08:45:12 PM PDT 24
Peak memory 205808 kb
Host smart-bfa0411c-2005-4c0c-be66-95ebfe297aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33586
5087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.335865087
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.2259475338
Short name T799
Test name
Test status
Simulation time 10098861473 ps
CPU time 13.22 seconds
Started Jun 07 08:44:56 PM PDT 24
Finished Jun 07 08:45:12 PM PDT 24
Peak memory 205880 kb
Host smart-0334acf9-08de-49b9-8b99-9fae415f9ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22594
75338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.2259475338
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.781430111
Short name T1316
Test name
Test status
Simulation time 10050693121 ps
CPU time 13.05 seconds
Started Jun 07 08:44:51 PM PDT 24
Finished Jun 07 08:45:07 PM PDT 24
Peak memory 205824 kb
Host smart-199fb9f2-ac85-4eb5-9749-be2667695094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78143
0111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.781430111
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.3925931266
Short name T1105
Test name
Test status
Simulation time 10875895725 ps
CPU time 15.57 seconds
Started Jun 07 08:45:02 PM PDT 24
Finished Jun 07 08:45:21 PM PDT 24
Peak memory 205884 kb
Host smart-5b31b306-0ba2-40ec-b419-b1e4d4b49a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39259
31266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.3925931266
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.3720928748
Short name T571
Test name
Test status
Simulation time 10222674828 ps
CPU time 18.35 seconds
Started Jun 07 08:44:56 PM PDT 24
Finished Jun 07 08:45:17 PM PDT 24
Peak memory 205836 kb
Host smart-18b0251d-e360-4234-8cc6-dbff0131a797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37209
28748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3720928748
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.3011452487
Short name T1388
Test name
Test status
Simulation time 10115229554 ps
CPU time 14.77 seconds
Started Jun 07 08:45:03 PM PDT 24
Finished Jun 07 08:45:21 PM PDT 24
Peak memory 205928 kb
Host smart-e994dc8d-aa12-408b-88ce-62c82d866c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30114
52487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.3011452487
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.1060048966
Short name T1171
Test name
Test status
Simulation time 10072181203 ps
CPU time 13.93 seconds
Started Jun 07 08:45:00 PM PDT 24
Finished Jun 07 08:45:16 PM PDT 24
Peak memory 205752 kb
Host smart-476137d7-b04c-4178-9b02-1eab6f66e5e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10600
48966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1060048966
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.882222459
Short name T1751
Test name
Test status
Simulation time 10158549413 ps
CPU time 14.28 seconds
Started Jun 07 08:44:52 PM PDT 24
Finished Jun 07 08:45:09 PM PDT 24
Peak memory 205756 kb
Host smart-790c5235-7ebb-4815-8e91-1c08dc115dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88222
2459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.882222459
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.1237457611
Short name T342
Test name
Test status
Simulation time 10186179876 ps
CPU time 15.66 seconds
Started Jun 07 08:44:56 PM PDT 24
Finished Jun 07 08:45:14 PM PDT 24
Peak memory 205776 kb
Host smart-4f4d9a74-b958-45f3-a624-4f97a253f801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12374
57611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.1237457611
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.3684425581
Short name T1366
Test name
Test status
Simulation time 13283619493 ps
CPU time 16.57 seconds
Started Jun 07 08:45:06 PM PDT 24
Finished Jun 07 08:45:26 PM PDT 24
Peak memory 205880 kb
Host smart-58c68209-7616-49f3-af07-524d52c76284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36844
25581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.3684425581
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.1730049225
Short name T428
Test name
Test status
Simulation time 10125068974 ps
CPU time 14.24 seconds
Started Jun 07 08:44:56 PM PDT 24
Finished Jun 07 08:45:13 PM PDT 24
Peak memory 205852 kb
Host smart-1178170b-8c08-4b7c-af34-a644b73fc488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17300
49225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1730049225
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.2879470828
Short name T1882
Test name
Test status
Simulation time 17817254796 ps
CPU time 87.81 seconds
Started Jun 07 08:44:54 PM PDT 24
Finished Jun 07 08:46:24 PM PDT 24
Peak memory 205832 kb
Host smart-a15409d1-0c26-4355-a62e-c108096adeec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28794
70828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.2879470828
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.4221805013
Short name T1255
Test name
Test status
Simulation time 10052969184 ps
CPU time 14.61 seconds
Started Jun 07 08:44:53 PM PDT 24
Finished Jun 07 08:45:10 PM PDT 24
Peak memory 205864 kb
Host smart-da7f7024-e198-4bcc-a322-846e0489aee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42218
05013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.4221805013
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.1738661933
Short name T531
Test name
Test status
Simulation time 10144627602 ps
CPU time 12.38 seconds
Started Jun 07 08:44:55 PM PDT 24
Finished Jun 07 08:45:10 PM PDT 24
Peak memory 205732 kb
Host smart-33d6f54f-99bf-4923-a7a4-23aa57a76dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17386
61933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.1738661933
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.1433632894
Short name T1929
Test name
Test status
Simulation time 10069185638 ps
CPU time 16.13 seconds
Started Jun 07 08:44:53 PM PDT 24
Finished Jun 07 08:45:12 PM PDT 24
Peak memory 205836 kb
Host smart-825955ca-1edf-4570-bf3e-dcd598264fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14336
32894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.1433632894
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.655489665
Short name T1571
Test name
Test status
Simulation time 10073719715 ps
CPU time 14.91 seconds
Started Jun 07 08:44:56 PM PDT 24
Finished Jun 07 08:45:14 PM PDT 24
Peak memory 205788 kb
Host smart-8ac09295-23b2-4cf8-89c8-bb8b4804fc8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65548
9665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.655489665
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.1116592801
Short name T661
Test name
Test status
Simulation time 10083831474 ps
CPU time 12.76 seconds
Started Jun 07 08:44:51 PM PDT 24
Finished Jun 07 08:45:06 PM PDT 24
Peak memory 205716 kb
Host smart-06f42d90-d89c-47a1-9d0d-d4e2ce1f1088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11165
92801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.1116592801
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.2981838081
Short name T1623
Test name
Test status
Simulation time 10047081410 ps
CPU time 16.04 seconds
Started Jun 07 08:45:08 PM PDT 24
Finished Jun 07 08:45:28 PM PDT 24
Peak memory 205880 kb
Host smart-45f3e094-f7be-4390-96d3-6472ce4fff76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29818
38081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.2981838081
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_eop_single_bit_handling.989909506
Short name T1411
Test name
Test status
Simulation time 10149156672 ps
CPU time 13.53 seconds
Started Jun 07 08:45:01 PM PDT 24
Finished Jun 07 08:45:18 PM PDT 24
Peak memory 205828 kb
Host smart-73f0e472-2c50-4b9a-9684-0864cced8a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98990
9506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_eop_single_bit_handling.989909506
Directory /workspace/22.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.3954644777
Short name T955
Test name
Test status
Simulation time 10051420161 ps
CPU time 12.97 seconds
Started Jun 07 08:44:59 PM PDT 24
Finished Jun 07 08:45:15 PM PDT 24
Peak memory 205752 kb
Host smart-e3a9e36f-1c2d-4154-a563-0759d67aed63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39546
44777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.3954644777
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3795158416
Short name T1542
Test name
Test status
Simulation time 10057373353 ps
CPU time 13.66 seconds
Started Jun 07 08:45:01 PM PDT 24
Finished Jun 07 08:45:18 PM PDT 24
Peak memory 205932 kb
Host smart-b7c81b67-0d98-40c4-b36d-3611306b32cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37951
58416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3795158416
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.615666270
Short name T744
Test name
Test status
Simulation time 15768235496 ps
CPU time 31.45 seconds
Started Jun 07 08:44:57 PM PDT 24
Finished Jun 07 08:45:31 PM PDT 24
Peak memory 205780 kb
Host smart-dc75a287-caef-4fa3-8f69-a1b9249a8b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61566
6270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.615666270
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.1013942652
Short name T593
Test name
Test status
Simulation time 10078979219 ps
CPU time 13.18 seconds
Started Jun 07 08:45:01 PM PDT 24
Finished Jun 07 08:45:18 PM PDT 24
Peak memory 205912 kb
Host smart-029dd756-2a86-417a-a5ce-87403707a2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10139
42652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.1013942652
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1261275034
Short name T698
Test name
Test status
Simulation time 10147321751 ps
CPU time 13.55 seconds
Started Jun 07 08:45:08 PM PDT 24
Finished Jun 07 08:45:25 PM PDT 24
Peak memory 205876 kb
Host smart-7e27674b-a9eb-42f8-a101-a07c92e789ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12612
75034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1261275034
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.2033465937
Short name T1917
Test name
Test status
Simulation time 10109092427 ps
CPU time 13.4 seconds
Started Jun 07 08:45:08 PM PDT 24
Finished Jun 07 08:45:25 PM PDT 24
Peak memory 205772 kb
Host smart-3e5a579b-60fb-41ec-8880-c137fe309e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20334
65937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.2033465937
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.1739118507
Short name T1034
Test name
Test status
Simulation time 10070122141 ps
CPU time 14.44 seconds
Started Jun 07 08:45:01 PM PDT 24
Finished Jun 07 08:45:19 PM PDT 24
Peak memory 205704 kb
Host smart-5583bff4-ba31-4dab-b5de-8499cce5a189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17391
18507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.1739118507
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1553847040
Short name T346
Test name
Test status
Simulation time 10056780822 ps
CPU time 14.06 seconds
Started Jun 07 08:45:01 PM PDT 24
Finished Jun 07 08:45:18 PM PDT 24
Peak memory 205812 kb
Host smart-7ddb0a7f-ba80-4451-9b70-34812ffd031b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15538
47040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1553847040
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.569615838
Short name T532
Test name
Test status
Simulation time 10122083114 ps
CPU time 14.01 seconds
Started Jun 07 08:44:56 PM PDT 24
Finished Jun 07 08:45:12 PM PDT 24
Peak memory 205884 kb
Host smart-48077391-8df2-4102-80a5-e1909909732d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56961
5838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.569615838
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.2958863831
Short name T1535
Test name
Test status
Simulation time 10076046922 ps
CPU time 12.96 seconds
Started Jun 07 08:45:00 PM PDT 24
Finished Jun 07 08:45:16 PM PDT 24
Peak memory 205780 kb
Host smart-4a0664f6-94df-4a7a-981a-4c00f61a72d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29588
63831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.2958863831
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2905837546
Short name T1196
Test name
Test status
Simulation time 10065617094 ps
CPU time 12.57 seconds
Started Jun 07 08:44:59 PM PDT 24
Finished Jun 07 08:45:15 PM PDT 24
Peak memory 205832 kb
Host smart-a0ecb586-9d4c-429e-b776-f7fb9233315f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29058
37546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2905837546
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.4256712734
Short name T1993
Test name
Test status
Simulation time 14460321340 ps
CPU time 58.33 seconds
Started Jun 07 08:45:01 PM PDT 24
Finished Jun 07 08:46:03 PM PDT 24
Peak memory 205876 kb
Host smart-47c79f83-8933-4f90-8c59-9554a94cbd0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42567
12734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.4256712734
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.670458485
Short name T597
Test name
Test status
Simulation time 10154047617 ps
CPU time 14.92 seconds
Started Jun 07 08:45:18 PM PDT 24
Finished Jun 07 08:45:35 PM PDT 24
Peak memory 205708 kb
Host smart-4b57df99-480c-4339-9b43-d4ed61e3b03e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=670458485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.670458485
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.1986086380
Short name T917
Test name
Test status
Simulation time 10075157842 ps
CPU time 13.29 seconds
Started Jun 07 08:45:15 PM PDT 24
Finished Jun 07 08:45:31 PM PDT 24
Peak memory 205964 kb
Host smart-2d88587f-e69f-4c2c-8f30-e04e971dcebe
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1986086380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.1986086380
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.887996995
Short name T440
Test name
Test status
Simulation time 10109384122 ps
CPU time 13.42 seconds
Started Jun 07 08:45:13 PM PDT 24
Finished Jun 07 08:45:29 PM PDT 24
Peak memory 205976 kb
Host smart-1b907c18-6ae6-4b74-9260-b8215086a8c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88799
6995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.887996995
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.2520427562
Short name T986
Test name
Test status
Simulation time 14196756443 ps
CPU time 16.42 seconds
Started Jun 07 08:45:00 PM PDT 24
Finished Jun 07 08:45:19 PM PDT 24
Peak memory 205912 kb
Host smart-b135c578-32e7-4231-ac0d-41b6f5344f15
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2520427562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.2520427562
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.377697361
Short name T1989
Test name
Test status
Simulation time 23285698788 ps
CPU time 29.01 seconds
Started Jun 07 08:45:01 PM PDT 24
Finished Jun 07 08:45:33 PM PDT 24
Peak memory 205876 kb
Host smart-22fe1992-3c3d-4920-8a53-86da6cbdc7a9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=377697361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.377697361
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3056087048
Short name T1704
Test name
Test status
Simulation time 10069518572 ps
CPU time 15.07 seconds
Started Jun 07 08:45:02 PM PDT 24
Finished Jun 07 08:45:20 PM PDT 24
Peak memory 205712 kb
Host smart-61b67c41-9070-491c-8dcb-f988933e660a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30560
87048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3056087048
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.4096432515
Short name T59
Test name
Test status
Simulation time 10065266147 ps
CPU time 14.23 seconds
Started Jun 07 08:45:00 PM PDT 24
Finished Jun 07 08:45:18 PM PDT 24
Peak memory 205756 kb
Host smart-45203b90-c27c-4319-a309-f55ba13a6acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40964
32515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.4096432515
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.4231087858
Short name T1305
Test name
Test status
Simulation time 11153125418 ps
CPU time 14.32 seconds
Started Jun 07 08:45:00 PM PDT 24
Finished Jun 07 08:45:17 PM PDT 24
Peak memory 205816 kb
Host smart-ddafe40d-9739-4cbb-9f78-e32b760cb28c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42310
87858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.4231087858
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.3447968002
Short name T1074
Test name
Test status
Simulation time 10082620175 ps
CPU time 14.49 seconds
Started Jun 07 08:45:07 PM PDT 24
Finished Jun 07 08:45:26 PM PDT 24
Peak memory 205800 kb
Host smart-53a241df-6641-4cbc-a042-56392e374f0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34479
68002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.3447968002
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.2948033655
Short name T797
Test name
Test status
Simulation time 10067432856 ps
CPU time 13.15 seconds
Started Jun 07 08:45:00 PM PDT 24
Finished Jun 07 08:45:17 PM PDT 24
Peak memory 205708 kb
Host smart-154e9301-8ff3-4da1-bbb5-6a287b2e0df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29480
33655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2948033655
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.2346166049
Short name T1322
Test name
Test status
Simulation time 10697141669 ps
CPU time 14.59 seconds
Started Jun 07 08:44:58 PM PDT 24
Finished Jun 07 08:45:16 PM PDT 24
Peak memory 205796 kb
Host smart-be36f376-d785-4b6f-a00e-c9786364d1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23461
66049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.2346166049
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.4124890760
Short name T977
Test name
Test status
Simulation time 10072611626 ps
CPU time 16.44 seconds
Started Jun 07 08:45:00 PM PDT 24
Finished Jun 07 08:45:20 PM PDT 24
Peak memory 205788 kb
Host smart-c31494e4-9714-445b-b94f-7b2278ec12dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41248
90760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.4124890760
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.3857502877
Short name T951
Test name
Test status
Simulation time 10156897492 ps
CPU time 13.44 seconds
Started Jun 07 08:45:09 PM PDT 24
Finished Jun 07 08:45:26 PM PDT 24
Peak memory 205876 kb
Host smart-e74b0651-fad7-499d-ade4-8b42d9e29ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38575
02877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.3857502877
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.2713691125
Short name T1776
Test name
Test status
Simulation time 10114390642 ps
CPU time 13.39 seconds
Started Jun 07 08:45:09 PM PDT 24
Finished Jun 07 08:45:26 PM PDT 24
Peak memory 205852 kb
Host smart-8409471e-fc39-4cd7-a93c-899fe2074dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27136
91125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.2713691125
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.845553043
Short name T31
Test name
Test status
Simulation time 10125350825 ps
CPU time 14.92 seconds
Started Jun 07 08:45:02 PM PDT 24
Finished Jun 07 08:45:20 PM PDT 24
Peak memory 205788 kb
Host smart-2045f10a-e086-4610-b58d-ce12b2e95f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84555
3043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.845553043
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.1546578150
Short name T887
Test name
Test status
Simulation time 10130053010 ps
CPU time 15.38 seconds
Started Jun 07 08:45:01 PM PDT 24
Finished Jun 07 08:45:19 PM PDT 24
Peak memory 205892 kb
Host smart-6198a43f-b9fa-49c4-8479-e68dc998792e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15465
78150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.1546578150
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.157836564
Short name T775
Test name
Test status
Simulation time 13187106814 ps
CPU time 16.16 seconds
Started Jun 07 08:45:08 PM PDT 24
Finished Jun 07 08:45:29 PM PDT 24
Peak memory 205772 kb
Host smart-67c6feea-7eff-45aa-9353-9b11bfb689ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15783
6564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.157836564
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2772076425
Short name T1812
Test name
Test status
Simulation time 10119591160 ps
CPU time 12.87 seconds
Started Jun 07 08:45:06 PM PDT 24
Finished Jun 07 08:45:23 PM PDT 24
Peak memory 205868 kb
Host smart-b05a2a5d-5b96-4953-8763-8e72e1e7c89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27720
76425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2772076425
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.1924957376
Short name T765
Test name
Test status
Simulation time 20758717933 ps
CPU time 118.83 seconds
Started Jun 07 08:45:07 PM PDT 24
Finished Jun 07 08:47:10 PM PDT 24
Peak memory 205864 kb
Host smart-5d637b3d-530f-4b92-a996-cbcf479eb2b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19249
57376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.1924957376
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3176106331
Short name T1008
Test name
Test status
Simulation time 10048833760 ps
CPU time 13.09 seconds
Started Jun 07 08:45:08 PM PDT 24
Finished Jun 07 08:45:26 PM PDT 24
Peak memory 205784 kb
Host smart-c18e6e71-e41b-4d35-8ff9-1dedd67674ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31761
06331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3176106331
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.4249663204
Short name T105
Test name
Test status
Simulation time 10112516139 ps
CPU time 12.93 seconds
Started Jun 07 08:45:07 PM PDT 24
Finished Jun 07 08:45:24 PM PDT 24
Peak memory 205832 kb
Host smart-d0a12106-e45c-4520-b9e8-88d932e6b06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42496
63204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.4249663204
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.3814198272
Short name T1797
Test name
Test status
Simulation time 10069609583 ps
CPU time 13.42 seconds
Started Jun 07 08:45:08 PM PDT 24
Finished Jun 07 08:45:25 PM PDT 24
Peak memory 205768 kb
Host smart-e04d4ab5-ac5e-4387-b4d4-c9d84381568b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38141
98272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.3814198272
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.1125014130
Short name T1344
Test name
Test status
Simulation time 10075981426 ps
CPU time 13.32 seconds
Started Jun 07 08:45:06 PM PDT 24
Finished Jun 07 08:45:23 PM PDT 24
Peak memory 205772 kb
Host smart-8a04a274-24df-4ebe-bce9-3d085a1a2356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11250
14130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.1125014130
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.563969021
Short name T854
Test name
Test status
Simulation time 10116640515 ps
CPU time 13.43 seconds
Started Jun 07 08:45:08 PM PDT 24
Finished Jun 07 08:45:25 PM PDT 24
Peak memory 205820 kb
Host smart-82fd01c4-e555-47be-9802-7d97f00da007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56396
9021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.563969021
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.4214688237
Short name T128
Test name
Test status
Simulation time 10063517638 ps
CPU time 16.36 seconds
Started Jun 07 08:45:12 PM PDT 24
Finished Jun 07 08:45:31 PM PDT 24
Peak memory 205792 kb
Host smart-54c33ba0-91aa-4550-910e-aac6d3224288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42146
88237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.4214688237
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_eop_single_bit_handling.272599467
Short name T1169
Test name
Test status
Simulation time 10096598335 ps
CPU time 16.46 seconds
Started Jun 07 08:45:06 PM PDT 24
Finished Jun 07 08:45:26 PM PDT 24
Peak memory 205892 kb
Host smart-8b86f373-bd90-4c89-911b-47850994b387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27259
9467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_eop_single_bit_handling.272599467
Directory /workspace/23.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.1231810903
Short name T395
Test name
Test status
Simulation time 10086296392 ps
CPU time 13.46 seconds
Started Jun 07 08:45:06 PM PDT 24
Finished Jun 07 08:45:22 PM PDT 24
Peak memory 205800 kb
Host smart-70c6bc79-5ebf-4d73-9ee1-c11b23018ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12318
10903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1231810903
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2694507230
Short name T1089
Test name
Test status
Simulation time 10110743722 ps
CPU time 12.99 seconds
Started Jun 07 08:45:08 PM PDT 24
Finished Jun 07 08:45:25 PM PDT 24
Peak memory 205904 kb
Host smart-2db1d9f5-afd7-4865-ab96-d484a4a16a58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26945
07230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2694507230
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.2144175020
Short name T1020
Test name
Test status
Simulation time 25743754933 ps
CPU time 48.52 seconds
Started Jun 07 08:45:08 PM PDT 24
Finished Jun 07 08:46:01 PM PDT 24
Peak memory 205748 kb
Host smart-fa88b784-85d5-461b-b25c-5b2caed3f5ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21441
75020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.2144175020
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.1766182469
Short name T851
Test name
Test status
Simulation time 10089460157 ps
CPU time 15.31 seconds
Started Jun 07 08:45:06 PM PDT 24
Finished Jun 07 08:45:25 PM PDT 24
Peak memory 205756 kb
Host smart-99b3ae94-0fa7-41e8-afdc-bafbdacc5e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17661
82469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.1766182469
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2364133372
Short name T1625
Test name
Test status
Simulation time 10058452832 ps
CPU time 14.38 seconds
Started Jun 07 08:45:07 PM PDT 24
Finished Jun 07 08:45:25 PM PDT 24
Peak memory 205724 kb
Host smart-2d851b21-2789-477a-b702-5cce0d2918de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23641
33372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2364133372
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.55719815
Short name T975
Test name
Test status
Simulation time 10071536092 ps
CPU time 15.46 seconds
Started Jun 07 08:45:07 PM PDT 24
Finished Jun 07 08:45:26 PM PDT 24
Peak memory 205844 kb
Host smart-cd15830d-4d1d-4927-a622-8f0167f7b93b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55719
815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.55719815
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2506211585
Short name T1326
Test name
Test status
Simulation time 10066567745 ps
CPU time 15.01 seconds
Started Jun 07 08:45:06 PM PDT 24
Finished Jun 07 08:45:24 PM PDT 24
Peak memory 205884 kb
Host smart-c6cb4d59-2261-4317-be6c-a466ca77f54e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25062
11585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2506211585
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.284438554
Short name T1810
Test name
Test status
Simulation time 10057014180 ps
CPU time 15.66 seconds
Started Jun 07 08:45:07 PM PDT 24
Finished Jun 07 08:45:26 PM PDT 24
Peak memory 205828 kb
Host smart-5cc413a2-1514-4061-9cca-935d4b83d22f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28443
8554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.284438554
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.1548389995
Short name T1614
Test name
Test status
Simulation time 10045253827 ps
CPU time 13.55 seconds
Started Jun 07 08:45:06 PM PDT 24
Finished Jun 07 08:45:24 PM PDT 24
Peak memory 205904 kb
Host smart-8f9ee6a4-b551-41f9-a971-9c91c3b58b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15483
89995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.1548389995
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.333382864
Short name T1375
Test name
Test status
Simulation time 10160088376 ps
CPU time 12.99 seconds
Started Jun 07 08:45:03 PM PDT 24
Finished Jun 07 08:45:19 PM PDT 24
Peak memory 205788 kb
Host smart-8b942986-d16d-4e45-b687-8413787d8c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33338
2864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.333382864
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3954210612
Short name T1831
Test name
Test status
Simulation time 10078156195 ps
CPU time 12.69 seconds
Started Jun 07 08:45:09 PM PDT 24
Finished Jun 07 08:45:25 PM PDT 24
Peak memory 205804 kb
Host smart-48052ccf-4988-4167-b7b2-d464e0098f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39542
10612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3954210612
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.2723181174
Short name T444
Test name
Test status
Simulation time 10059177817 ps
CPU time 14.01 seconds
Started Jun 07 08:45:10 PM PDT 24
Finished Jun 07 08:45:27 PM PDT 24
Peak memory 205848 kb
Host smart-659c1fb5-42c1-4b65-b990-6a1bf6573071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27231
81174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.2723181174
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.4062912331
Short name T1272
Test name
Test status
Simulation time 16803243725 ps
CPU time 196.04 seconds
Started Jun 07 08:45:07 PM PDT 24
Finished Jun 07 08:48:26 PM PDT 24
Peak memory 205836 kb
Host smart-b079dba7-395b-4cb8-b663-7005e52c9916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40629
12331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.4062912331
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.1758370668
Short name T1788
Test name
Test status
Simulation time 10141847622 ps
CPU time 12.96 seconds
Started Jun 07 08:45:25 PM PDT 24
Finished Jun 07 08:45:41 PM PDT 24
Peak memory 205836 kb
Host smart-53e2b1be-dc03-435b-a3c6-e159ca29c5c6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1758370668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.1758370668
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.3153385334
Short name T1816
Test name
Test status
Simulation time 10059917465 ps
CPU time 14.21 seconds
Started Jun 07 08:45:25 PM PDT 24
Finished Jun 07 08:45:42 PM PDT 24
Peak memory 205864 kb
Host smart-5123105d-48c8-4c01-a0bb-59c9d5d326df
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3153385334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.3153385334
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.4146458015
Short name T1567
Test name
Test status
Simulation time 10141804943 ps
CPU time 13.89 seconds
Started Jun 07 08:45:29 PM PDT 24
Finished Jun 07 08:45:46 PM PDT 24
Peak memory 205764 kb
Host smart-49ba7bea-9ebf-4915-acb1-09809fd8e4ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41464
58015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.4146458015
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.2799273947
Short name T396
Test name
Test status
Simulation time 14224005827 ps
CPU time 18.16 seconds
Started Jun 07 08:45:14 PM PDT 24
Finished Jun 07 08:45:35 PM PDT 24
Peak memory 205800 kb
Host smart-f47ed96f-fa44-4ed8-b66d-01f7eab7df69
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2799273947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.2799273947
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.1908913351
Short name T2010
Test name
Test status
Simulation time 23198117565 ps
CPU time 28.03 seconds
Started Jun 07 08:45:15 PM PDT 24
Finished Jun 07 08:45:46 PM PDT 24
Peak memory 205872 kb
Host smart-a09643be-232c-40f5-bcce-6889132e145a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1908913351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.1908913351
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3836145494
Short name T1011
Test name
Test status
Simulation time 10058020418 ps
CPU time 14.28 seconds
Started Jun 07 08:45:14 PM PDT 24
Finished Jun 07 08:45:31 PM PDT 24
Peak memory 205844 kb
Host smart-858f45d3-cf29-4185-91f1-3e2bcfd6c867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38361
45494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3836145494
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.3627128638
Short name T1607
Test name
Test status
Simulation time 10448170289 ps
CPU time 14.51 seconds
Started Jun 07 08:45:15 PM PDT 24
Finished Jun 07 08:45:32 PM PDT 24
Peak memory 205808 kb
Host smart-1842cc40-a31e-445b-98d8-883a112fd465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36271
28638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.3627128638
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.379963884
Short name T897
Test name
Test status
Simulation time 10068684728 ps
CPU time 14.3 seconds
Started Jun 07 08:45:14 PM PDT 24
Finished Jun 07 08:45:31 PM PDT 24
Peak memory 205880 kb
Host smart-f1ba7141-083c-4281-9c1a-78a39cae6859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37996
3884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.379963884
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.1684280090
Short name T1488
Test name
Test status
Simulation time 10072199407 ps
CPU time 13.19 seconds
Started Jun 07 08:45:15 PM PDT 24
Finished Jun 07 08:45:31 PM PDT 24
Peak memory 205728 kb
Host smart-cce691f7-03e2-4f66-a054-1d0ede4c2188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16842
80090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.1684280090
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.1199921334
Short name T1265
Test name
Test status
Simulation time 10913191871 ps
CPU time 16.7 seconds
Started Jun 07 08:45:16 PM PDT 24
Finished Jun 07 08:45:35 PM PDT 24
Peak memory 205808 kb
Host smart-e4d1e8ba-d065-4d78-a9b8-5b4eb0acd75d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11999
21334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.1199921334
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2700017525
Short name T1345
Test name
Test status
Simulation time 10211477857 ps
CPU time 15.32 seconds
Started Jun 07 08:45:17 PM PDT 24
Finished Jun 07 08:45:35 PM PDT 24
Peak memory 205772 kb
Host smart-2eb898cc-788b-497a-b975-c52f98ac2367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27000
17525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2700017525
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.341089705
Short name T590
Test name
Test status
Simulation time 10131116634 ps
CPU time 13.01 seconds
Started Jun 07 08:45:21 PM PDT 24
Finished Jun 07 08:45:37 PM PDT 24
Peak memory 205848 kb
Host smart-afe88f58-2b3c-49e4-bc21-7a0b927b97bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34108
9705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.341089705
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.3330316811
Short name T552
Test name
Test status
Simulation time 10065163106 ps
CPU time 13.94 seconds
Started Jun 07 08:45:21 PM PDT 24
Finished Jun 07 08:45:38 PM PDT 24
Peak memory 205804 kb
Host smart-fde9204e-4ced-417d-aa72-0bfb610ee5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33303
16811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.3330316811
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.2417399145
Short name T646
Test name
Test status
Simulation time 10175562823 ps
CPU time 13.83 seconds
Started Jun 07 08:45:18 PM PDT 24
Finished Jun 07 08:45:34 PM PDT 24
Peak memory 205780 kb
Host smart-fdc8ebb5-e414-49fc-bd0c-a438e5e119ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24173
99145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.2417399145
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.3246344607
Short name T1097
Test name
Test status
Simulation time 10142383825 ps
CPU time 14.53 seconds
Started Jun 07 08:45:13 PM PDT 24
Finished Jun 07 08:45:30 PM PDT 24
Peak memory 205812 kb
Host smart-4458db26-784c-4ceb-be83-409cba85621e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32463
44607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.3246344607
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.1350024911
Short name T1502
Test name
Test status
Simulation time 13237643477 ps
CPU time 16.68 seconds
Started Jun 07 08:45:13 PM PDT 24
Finished Jun 07 08:45:33 PM PDT 24
Peak memory 205888 kb
Host smart-2580afdd-c1fd-492c-b4b9-c7f6fce9b05c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13500
24911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.1350024911
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2816618850
Short name T1770
Test name
Test status
Simulation time 10105021661 ps
CPU time 15.22 seconds
Started Jun 07 08:45:35 PM PDT 24
Finished Jun 07 08:45:54 PM PDT 24
Peak memory 205804 kb
Host smart-f6085687-f825-46fd-8f07-60514458f2d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28166
18850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2816618850
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.2086236063
Short name T1732
Test name
Test status
Simulation time 20791905789 ps
CPU time 115.21 seconds
Started Jun 07 08:45:15 PM PDT 24
Finished Jun 07 08:47:13 PM PDT 24
Peak memory 205876 kb
Host smart-fc79f21c-30c8-4c0a-85c1-4fa8c36b5583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20862
36063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.2086236063
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.1700823085
Short name T1376
Test name
Test status
Simulation time 10067601022 ps
CPU time 12.7 seconds
Started Jun 07 08:45:14 PM PDT 24
Finished Jun 07 08:45:30 PM PDT 24
Peak memory 205768 kb
Host smart-604d9345-0cd1-45d7-a93d-888bcd1ffeb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17008
23085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.1700823085
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.1399608239
Short name T114
Test name
Test status
Simulation time 10122632833 ps
CPU time 14.18 seconds
Started Jun 07 08:45:24 PM PDT 24
Finished Jun 07 08:45:41 PM PDT 24
Peak memory 205764 kb
Host smart-a2ace0b9-0078-4e7f-aab6-ab6b6138f0a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13996
08239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1399608239
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.2853688386
Short name T1622
Test name
Test status
Simulation time 10073161558 ps
CPU time 13.7 seconds
Started Jun 07 08:45:21 PM PDT 24
Finished Jun 07 08:45:38 PM PDT 24
Peak memory 205848 kb
Host smart-a986bcae-19c4-4d85-a294-a03a0edee86b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28536
88386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.2853688386
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.2888180329
Short name T1321
Test name
Test status
Simulation time 10055934384 ps
CPU time 15.75 seconds
Started Jun 07 08:45:22 PM PDT 24
Finished Jun 07 08:45:41 PM PDT 24
Peak memory 205808 kb
Host smart-3e9b42bd-8571-4b83-8063-3c9aecbb3512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28881
80329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.2888180329
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2949197547
Short name T307
Test name
Test status
Simulation time 10132208989 ps
CPU time 14.78 seconds
Started Jun 07 08:45:26 PM PDT 24
Finished Jun 07 08:45:43 PM PDT 24
Peak memory 205768 kb
Host smart-bbb12edf-a5cd-4c6a-836c-26c59ffb7fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29491
97547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2949197547
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_eop_single_bit_handling.2697891779
Short name T705
Test name
Test status
Simulation time 10053090416 ps
CPU time 12.79 seconds
Started Jun 07 08:45:22 PM PDT 24
Finished Jun 07 08:45:38 PM PDT 24
Peak memory 205736 kb
Host smart-86e418a5-4d5f-498f-8438-39ab47d4fb56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26978
91779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_eop_single_bit_handling.2697891779
Directory /workspace/24.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.1757726550
Short name T1716
Test name
Test status
Simulation time 10059719944 ps
CPU time 16.79 seconds
Started Jun 07 08:45:29 PM PDT 24
Finished Jun 07 08:45:49 PM PDT 24
Peak memory 205840 kb
Host smart-17d2ed84-d44b-4090-b652-12e7f4c63f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17577
26550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.1757726550
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.463828985
Short name T971
Test name
Test status
Simulation time 10029729754 ps
CPU time 15.21 seconds
Started Jun 07 08:45:25 PM PDT 24
Finished Jun 07 08:45:43 PM PDT 24
Peak memory 205744 kb
Host smart-2eb65919-23ec-487f-94b7-2b9444aa797b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46382
8985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.463828985
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1704909680
Short name T1747
Test name
Test status
Simulation time 10076283708 ps
CPU time 15.97 seconds
Started Jun 07 08:45:27 PM PDT 24
Finished Jun 07 08:45:46 PM PDT 24
Peak memory 205880 kb
Host smart-33844af7-b904-4b5e-bf21-505caf6cd4ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17049
09680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1704909680
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.2097930497
Short name T527
Test name
Test status
Simulation time 10147326181 ps
CPU time 13.09 seconds
Started Jun 07 08:45:22 PM PDT 24
Finished Jun 07 08:45:38 PM PDT 24
Peak memory 205828 kb
Host smart-8bbcbe21-2ac3-404e-b548-ed98596be4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20979
30497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.2097930497
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.2969889122
Short name T807
Test name
Test status
Simulation time 10061952646 ps
CPU time 13.69 seconds
Started Jun 07 08:45:22 PM PDT 24
Finished Jun 07 08:45:38 PM PDT 24
Peak memory 205892 kb
Host smart-b159a974-9d53-4d9c-933d-4a8371f424fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29698
89122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.2969889122
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.114446229
Short name T759
Test name
Test status
Simulation time 10110153221 ps
CPU time 13.93 seconds
Started Jun 07 08:45:21 PM PDT 24
Finished Jun 07 08:45:38 PM PDT 24
Peak memory 205800 kb
Host smart-eed848fc-04a3-4593-85e1-4bd606d3a1a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11444
6229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.114446229
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.1291225716
Short name T1176
Test name
Test status
Simulation time 10053427273 ps
CPU time 16.77 seconds
Started Jun 07 08:45:20 PM PDT 24
Finished Jun 07 08:45:40 PM PDT 24
Peak memory 205764 kb
Host smart-45766324-4b23-4e36-88fd-fd619b43abc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12912
25716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1291225716
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.1351532776
Short name T77
Test name
Test status
Simulation time 10073989733 ps
CPU time 12.97 seconds
Started Jun 07 08:45:23 PM PDT 24
Finished Jun 07 08:45:39 PM PDT 24
Peak memory 205768 kb
Host smart-fb2f815a-e9d1-43c1-9c46-4838f3dfe9f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13515
32776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.1351532776
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.1949054927
Short name T69
Test name
Test status
Simulation time 10118047176 ps
CPU time 13.63 seconds
Started Jun 07 08:45:34 PM PDT 24
Finished Jun 07 08:45:52 PM PDT 24
Peak memory 205872 kb
Host smart-ff09cbdc-4371-45cb-a4e0-a043a99d47e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19490
54927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1949054927
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3464391638
Short name T354
Test name
Test status
Simulation time 10062083594 ps
CPU time 14.67 seconds
Started Jun 07 08:45:26 PM PDT 24
Finished Jun 07 08:45:43 PM PDT 24
Peak memory 205808 kb
Host smart-658ba617-01fd-4340-924d-5fe3ae477108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34643
91638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3464391638
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.4197398806
Short name T1168
Test name
Test status
Simulation time 10060059068 ps
CPU time 12.95 seconds
Started Jun 07 08:45:27 PM PDT 24
Finished Jun 07 08:45:42 PM PDT 24
Peak memory 205844 kb
Host smart-2d396b0a-84db-40a8-ac3e-eed1140fd2c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41973
98806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.4197398806
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.1257522286
Short name T645
Test name
Test status
Simulation time 22908678410 ps
CPU time 129.84 seconds
Started Jun 07 08:45:26 PM PDT 24
Finished Jun 07 08:47:39 PM PDT 24
Peak memory 205876 kb
Host smart-753c9f93-f757-4e34-b9ee-5b89e043ba3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12575
22286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.1257522286
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.1642988720
Short name T1784
Test name
Test status
Simulation time 10148493683 ps
CPU time 13.61 seconds
Started Jun 07 08:45:36 PM PDT 24
Finished Jun 07 08:45:53 PM PDT 24
Peak memory 205740 kb
Host smart-422dd9b8-8c17-488f-a2f7-861d450c5df7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1642988720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.1642988720
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.3099237332
Short name T231
Test name
Test status
Simulation time 10057712694 ps
CPU time 12.85 seconds
Started Jun 07 08:45:32 PM PDT 24
Finished Jun 07 08:45:48 PM PDT 24
Peak memory 205764 kb
Host smart-f49eeb8b-3991-4f0f-aa00-a6aed664a39d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3099237332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.3099237332
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.3573631773
Short name T1476
Test name
Test status
Simulation time 10086397122 ps
CPU time 13.41 seconds
Started Jun 07 08:45:27 PM PDT 24
Finished Jun 07 08:45:43 PM PDT 24
Peak memory 205800 kb
Host smart-417e9f93-e3de-43d5-92f1-5d7ea69e799e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35736
31773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.3573631773
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.3473749098
Short name T1992
Test name
Test status
Simulation time 13973301309 ps
CPU time 16.78 seconds
Started Jun 07 08:45:24 PM PDT 24
Finished Jun 07 08:45:44 PM PDT 24
Peak memory 205956 kb
Host smart-45599617-87be-4505-8eca-f5164011db52
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3473749098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.3473749098
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.3771967955
Short name T1382
Test name
Test status
Simulation time 23221605953 ps
CPU time 24.08 seconds
Started Jun 07 08:45:21 PM PDT 24
Finished Jun 07 08:45:48 PM PDT 24
Peak memory 205908 kb
Host smart-fddc266e-ebd5-4e42-aa05-e7fd7267176f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3771967955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.3771967955
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.3334999544
Short name T1451
Test name
Test status
Simulation time 10044921342 ps
CPU time 13.34 seconds
Started Jun 07 08:45:21 PM PDT 24
Finished Jun 07 08:45:38 PM PDT 24
Peak memory 205864 kb
Host smart-579a536f-e95b-4392-a3fd-689bdc5e8441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33349
99544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.3334999544
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.380249099
Short name T2031
Test name
Test status
Simulation time 10765180690 ps
CPU time 14.31 seconds
Started Jun 07 08:45:19 PM PDT 24
Finished Jun 07 08:45:36 PM PDT 24
Peak memory 205704 kb
Host smart-04968241-de30-4c06-a775-6cf4db504cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38024
9099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.380249099
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.3891407660
Short name T1908
Test name
Test status
Simulation time 10051553095 ps
CPU time 13.67 seconds
Started Jun 07 08:45:22 PM PDT 24
Finished Jun 07 08:45:39 PM PDT 24
Peak memory 205780 kb
Host smart-8d6352c0-8a52-4249-8e1e-19677be61274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38914
07660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.3891407660
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.2999198621
Short name T1925
Test name
Test status
Simulation time 10086936983 ps
CPU time 14.3 seconds
Started Jun 07 08:45:22 PM PDT 24
Finished Jun 07 08:45:40 PM PDT 24
Peak memory 205728 kb
Host smart-e228f2cb-7032-4cbd-a094-b6fc0ebe8d46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29991
98621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.2999198621
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1768148431
Short name T1184
Test name
Test status
Simulation time 10814125903 ps
CPU time 15 seconds
Started Jun 07 08:45:28 PM PDT 24
Finished Jun 07 08:45:46 PM PDT 24
Peak memory 205836 kb
Host smart-a26669e3-d207-4646-a7f5-5f748c1709f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17681
48431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1768148431
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.725033281
Short name T1641
Test name
Test status
Simulation time 10057862413 ps
CPU time 15.48 seconds
Started Jun 07 08:45:23 PM PDT 24
Finished Jun 07 08:45:41 PM PDT 24
Peak memory 205752 kb
Host smart-0628bcfe-1c4e-4d2e-abeb-b79ef99aae0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72503
3281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.725033281
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.91527212
Short name T334
Test name
Test status
Simulation time 10083488204 ps
CPU time 12.86 seconds
Started Jun 07 08:45:31 PM PDT 24
Finished Jun 07 08:45:47 PM PDT 24
Peak memory 205768 kb
Host smart-d2a5ed97-f6ef-4586-92bc-861ff520f213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91527
212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.91527212
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.3376802919
Short name T1942
Test name
Test status
Simulation time 10042936182 ps
CPU time 14.62 seconds
Started Jun 07 08:45:32 PM PDT 24
Finished Jun 07 08:45:50 PM PDT 24
Peak memory 205764 kb
Host smart-9524cb16-89e0-4f91-b702-336f7c491233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33768
02919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.3376802919
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3243529828
Short name T607
Test name
Test status
Simulation time 10124628551 ps
CPU time 13.11 seconds
Started Jun 07 08:45:24 PM PDT 24
Finished Jun 07 08:45:40 PM PDT 24
Peak memory 205796 kb
Host smart-6f453203-1ef2-4021-ab24-380c681c2750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32435
29828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3243529828
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.1185627525
Short name T1373
Test name
Test status
Simulation time 10123156417 ps
CPU time 13.1 seconds
Started Jun 07 08:45:24 PM PDT 24
Finished Jun 07 08:45:40 PM PDT 24
Peak memory 205736 kb
Host smart-20fc7ae5-0ad2-48c5-840d-83425badd927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11856
27525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.1185627525
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.524054366
Short name T452
Test name
Test status
Simulation time 13181979774 ps
CPU time 16.04 seconds
Started Jun 07 08:45:24 PM PDT 24
Finished Jun 07 08:45:43 PM PDT 24
Peak memory 205860 kb
Host smart-a42bdacc-a2b8-4ca5-a441-53cb4d284805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52405
4366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.524054366
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.3558311897
Short name T1526
Test name
Test status
Simulation time 10129856622 ps
CPU time 14.37 seconds
Started Jun 07 08:45:21 PM PDT 24
Finished Jun 07 08:45:38 PM PDT 24
Peak memory 205756 kb
Host smart-9e1e035f-bce6-4cc1-af8c-7bc8ffc91a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35583
11897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3558311897
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.13701564
Short name T1791
Test name
Test status
Simulation time 16275427045 ps
CPU time 193.71 seconds
Started Jun 07 08:45:29 PM PDT 24
Finished Jun 07 08:48:46 PM PDT 24
Peak memory 205804 kb
Host smart-8518496f-bd13-4065-bf9b-6d0ab4795b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13701
564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.13701564
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.906123079
Short name T1264
Test name
Test status
Simulation time 10100895860 ps
CPU time 13.15 seconds
Started Jun 07 08:45:18 PM PDT 24
Finished Jun 07 08:45:34 PM PDT 24
Peak memory 205848 kb
Host smart-3af3da22-1ff7-40ad-8ebb-da55e21939f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90612
3079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.906123079
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1273804246
Short name T1916
Test name
Test status
Simulation time 10096712974 ps
CPU time 15.57 seconds
Started Jun 07 08:45:23 PM PDT 24
Finished Jun 07 08:45:42 PM PDT 24
Peak memory 205808 kb
Host smart-bbf8d231-8e62-4056-8786-68a857ef3036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12738
04246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1273804246
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.2191540282
Short name T771
Test name
Test status
Simulation time 10088890936 ps
CPU time 12.66 seconds
Started Jun 07 08:45:26 PM PDT 24
Finished Jun 07 08:45:41 PM PDT 24
Peak memory 205816 kb
Host smart-28823b3a-a85e-4144-86ae-2f16bdcdb82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21915
40282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.2191540282
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3687337251
Short name T1556
Test name
Test status
Simulation time 10071629150 ps
CPU time 13.45 seconds
Started Jun 07 08:45:30 PM PDT 24
Finished Jun 07 08:45:47 PM PDT 24
Peak memory 205908 kb
Host smart-12dbd863-d59b-42c9-a99a-a192e81ff561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36873
37251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3687337251
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.2791697534
Short name T786
Test name
Test status
Simulation time 10088106243 ps
CPU time 15.01 seconds
Started Jun 07 08:45:29 PM PDT 24
Finished Jun 07 08:45:47 PM PDT 24
Peak memory 205760 kb
Host smart-ed1b0019-6f43-42db-9acf-c525089c5db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27916
97534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.2791697534
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.1292001724
Short name T679
Test name
Test status
Simulation time 10060853394 ps
CPU time 13.28 seconds
Started Jun 07 08:45:29 PM PDT 24
Finished Jun 07 08:45:46 PM PDT 24
Peak memory 205852 kb
Host smart-74594fb1-fa99-4f59-a524-193e26091a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12920
01724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.1292001724
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_eop_single_bit_handling.3673893420
Short name T993
Test name
Test status
Simulation time 10052083964 ps
CPU time 12.37 seconds
Started Jun 07 08:45:29 PM PDT 24
Finished Jun 07 08:45:45 PM PDT 24
Peak memory 205884 kb
Host smart-c7758ed0-dede-48b7-a40a-ffcfd15274a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36738
93420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_eop_single_bit_handling.3673893420
Directory /workspace/25.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.3275943311
Short name T1151
Test name
Test status
Simulation time 10044355170 ps
CPU time 12.82 seconds
Started Jun 07 08:45:30 PM PDT 24
Finished Jun 07 08:45:46 PM PDT 24
Peak memory 205832 kb
Host smart-f7db9411-2b19-4b10-af94-c74239c4960c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32759
43311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.3275943311
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2630386640
Short name T1390
Test name
Test status
Simulation time 10031344514 ps
CPU time 13.15 seconds
Started Jun 07 08:45:34 PM PDT 24
Finished Jun 07 08:45:51 PM PDT 24
Peak memory 205752 kb
Host smart-4595b6bd-621a-4b12-938f-3d9f407feb77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26303
86640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2630386640
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.678068379
Short name T1303
Test name
Test status
Simulation time 21796819123 ps
CPU time 39.98 seconds
Started Jun 07 08:45:33 PM PDT 24
Finished Jun 07 08:46:16 PM PDT 24
Peak memory 205776 kb
Host smart-c0310bab-1250-4cd3-a596-65ba25a42ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67806
8379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.678068379
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.456657509
Short name T1744
Test name
Test status
Simulation time 10058918703 ps
CPU time 14.45 seconds
Started Jun 07 08:45:29 PM PDT 24
Finished Jun 07 08:45:47 PM PDT 24
Peak memory 205784 kb
Host smart-8f4ccac7-9483-4e83-832c-f6bccff08cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45665
7509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.456657509
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1249204304
Short name T641
Test name
Test status
Simulation time 10109138550 ps
CPU time 12.97 seconds
Started Jun 07 08:45:28 PM PDT 24
Finished Jun 07 08:45:43 PM PDT 24
Peak memory 205856 kb
Host smart-51d89b32-432f-4bc1-8bfa-a92097b43674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12492
04304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1249204304
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.2826668294
Short name T1546
Test name
Test status
Simulation time 10088806869 ps
CPU time 12.17 seconds
Started Jun 07 08:45:25 PM PDT 24
Finished Jun 07 08:45:40 PM PDT 24
Peak memory 205888 kb
Host smart-8c8d7e54-1254-45a3-bb3d-e1b800a97ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28266
68294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.2826668294
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.258394911
Short name T1653
Test name
Test status
Simulation time 10062505295 ps
CPU time 12.99 seconds
Started Jun 07 08:45:28 PM PDT 24
Finished Jun 07 08:45:44 PM PDT 24
Peak memory 205796 kb
Host smart-380da711-d86c-48d2-9c91-2c2c389bebc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25839
4911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.258394911
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.714806291
Short name T1368
Test name
Test status
Simulation time 10047805977 ps
CPU time 12.89 seconds
Started Jun 07 08:45:36 PM PDT 24
Finished Jun 07 08:45:52 PM PDT 24
Peak memory 205784 kb
Host smart-1992d0cf-5093-4b8e-b5eb-43f1668902f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71480
6291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.714806291
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.443273450
Short name T34
Test name
Test status
Simulation time 10058695499 ps
CPU time 12.6 seconds
Started Jun 07 08:45:28 PM PDT 24
Finished Jun 07 08:45:43 PM PDT 24
Peak memory 205884 kb
Host smart-7506c17f-b9a2-463b-b6db-f27a00a051f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44327
3450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.443273450
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.367139911
Short name T151
Test name
Test status
Simulation time 10114805590 ps
CPU time 13.87 seconds
Started Jun 07 08:45:21 PM PDT 24
Finished Jun 07 08:45:38 PM PDT 24
Peak memory 205796 kb
Host smart-7b591cc2-5f7c-49d6-ac8a-e4cce3eab62f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36713
9911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.367139911
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.2616286015
Short name T1439
Test name
Test status
Simulation time 10094590349 ps
CPU time 15.73 seconds
Started Jun 07 08:45:31 PM PDT 24
Finished Jun 07 08:45:50 PM PDT 24
Peak memory 205860 kb
Host smart-d0e90746-60a7-4ae8-8dfc-564ee2a6a181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26162
86015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.2616286015
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.1471963121
Short name T883
Test name
Test status
Simulation time 10066233892 ps
CPU time 13.82 seconds
Started Jun 07 08:45:32 PM PDT 24
Finished Jun 07 08:45:49 PM PDT 24
Peak memory 205776 kb
Host smart-27e9a31c-836a-4ae6-ac34-56e84ddba39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14719
63121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.1471963121
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.3716810439
Short name T757
Test name
Test status
Simulation time 19733594294 ps
CPU time 97.81 seconds
Started Jun 07 08:45:30 PM PDT 24
Finished Jun 07 08:47:11 PM PDT 24
Peak memory 205852 kb
Host smart-b2b5eb3d-d92c-4e9f-85f7-6521b216f523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37168
10439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.3716810439
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.2877635147
Short name T932
Test name
Test status
Simulation time 10197412721 ps
CPU time 15.72 seconds
Started Jun 07 08:45:35 PM PDT 24
Finished Jun 07 08:45:55 PM PDT 24
Peak memory 205876 kb
Host smart-b875700a-295e-4b8f-8ede-e4c3e450cef7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2877635147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.2877635147
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.4285229433
Short name T1952
Test name
Test status
Simulation time 10061267468 ps
CPU time 16.37 seconds
Started Jun 07 08:45:33 PM PDT 24
Finished Jun 07 08:45:52 PM PDT 24
Peak memory 205768 kb
Host smart-cadeb6db-4d70-4818-b7b8-8fd8d3cff907
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4285229433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.4285229433
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.1505134410
Short name T1124
Test name
Test status
Simulation time 10062450504 ps
CPU time 13.68 seconds
Started Jun 07 08:45:37 PM PDT 24
Finished Jun 07 08:45:54 PM PDT 24
Peak memory 205820 kb
Host smart-4f60fa1a-c53c-433d-a9c4-eccdd17a186c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15051
34410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.1505134410
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.2595965739
Short name T12
Test name
Test status
Simulation time 13690768922 ps
CPU time 16.7 seconds
Started Jun 07 08:45:27 PM PDT 24
Finished Jun 07 08:45:47 PM PDT 24
Peak memory 205932 kb
Host smart-f9abdb3d-289a-445c-8bfe-f5a0c5b3f9a6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2595965739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.2595965739
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.3325513042
Short name T517
Test name
Test status
Simulation time 23280857038 ps
CPU time 26.28 seconds
Started Jun 07 08:45:34 PM PDT 24
Finished Jun 07 08:46:04 PM PDT 24
Peak memory 205788 kb
Host smart-8ea22725-4237-429b-a690-3df8c6724b15
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3325513042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.3325513042
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1216502101
Short name T309
Test name
Test status
Simulation time 10061424174 ps
CPU time 15.79 seconds
Started Jun 07 08:45:30 PM PDT 24
Finished Jun 07 08:45:49 PM PDT 24
Peak memory 205772 kb
Host smart-2c56295b-627c-4ead-ac02-0c9a05a4f976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12165
02101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1216502101
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.1756950901
Short name T1270
Test name
Test status
Simulation time 10067706351 ps
CPU time 13.46 seconds
Started Jun 07 08:45:30 PM PDT 24
Finished Jun 07 08:45:47 PM PDT 24
Peak memory 205860 kb
Host smart-1332288c-f78e-4e8a-ac83-448e87461ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17569
50901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.1756950901
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.807925911
Short name T1268
Test name
Test status
Simulation time 11285661602 ps
CPU time 17.47 seconds
Started Jun 07 08:45:29 PM PDT 24
Finished Jun 07 08:45:49 PM PDT 24
Peak memory 205752 kb
Host smart-ea5e00c3-70e6-43b9-b320-480d5cfb2350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80792
5911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.807925911
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.1486669211
Short name T1886
Test name
Test status
Simulation time 10038911513 ps
CPU time 14.93 seconds
Started Jun 07 08:45:29 PM PDT 24
Finished Jun 07 08:45:48 PM PDT 24
Peak memory 205840 kb
Host smart-0e06deee-5f21-4629-8646-b337a42fd572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14866
69211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.1486669211
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.4242518624
Short name T456
Test name
Test status
Simulation time 10048835852 ps
CPU time 14.08 seconds
Started Jun 07 08:45:32 PM PDT 24
Finished Jun 07 08:45:49 PM PDT 24
Peak memory 205756 kb
Host smart-a46604f3-478c-4a70-853e-56770655d799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42425
18624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.4242518624
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.2522354186
Short name T125
Test name
Test status
Simulation time 10783441376 ps
CPU time 16.95 seconds
Started Jun 07 08:45:28 PM PDT 24
Finished Jun 07 08:45:48 PM PDT 24
Peak memory 205856 kb
Host smart-3e1b2aac-8b18-4b1e-822a-81c191becca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25223
54186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.2522354186
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.2715066987
Short name T1468
Test name
Test status
Simulation time 10163452052 ps
CPU time 16.09 seconds
Started Jun 07 08:45:27 PM PDT 24
Finished Jun 07 08:45:45 PM PDT 24
Peak memory 205736 kb
Host smart-41176039-9133-4399-b72b-3cdfb4444515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27150
66987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.2715066987
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.694766642
Short name T1334
Test name
Test status
Simulation time 10067507414 ps
CPU time 14.24 seconds
Started Jun 07 08:45:34 PM PDT 24
Finished Jun 07 08:45:52 PM PDT 24
Peak memory 205768 kb
Host smart-79d58f04-3eb5-4b76-8001-53aff8cf3f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69476
6642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.694766642
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.3456888396
Short name T1737
Test name
Test status
Simulation time 10044551029 ps
CPU time 13.28 seconds
Started Jun 07 08:45:45 PM PDT 24
Finished Jun 07 08:46:03 PM PDT 24
Peak memory 205816 kb
Host smart-e956e3c1-8bb7-467b-85e2-96723c1faa3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34568
88396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.3456888396
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.2495761875
Short name T1672
Test name
Test status
Simulation time 10135443982 ps
CPU time 15.3 seconds
Started Jun 07 08:45:32 PM PDT 24
Finished Jun 07 08:45:50 PM PDT 24
Peak memory 205852 kb
Host smart-c2ba9292-90ae-4598-95f5-0114102650b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24957
61875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2495761875
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.2027896524
Short name T838
Test name
Test status
Simulation time 10123722910 ps
CPU time 14.77 seconds
Started Jun 07 08:45:30 PM PDT 24
Finished Jun 07 08:45:48 PM PDT 24
Peak memory 205764 kb
Host smart-2cedcdd9-a863-437e-9263-891930388152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20278
96524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.2027896524
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.1970522354
Short name T1534
Test name
Test status
Simulation time 13167164987 ps
CPU time 18.37 seconds
Started Jun 07 08:45:27 PM PDT 24
Finished Jun 07 08:45:49 PM PDT 24
Peak memory 205732 kb
Host smart-5468f11c-5c72-495c-ac14-0f988a5929c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19705
22354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.1970522354
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.2748240706
Short name T492
Test name
Test status
Simulation time 10104486089 ps
CPU time 12.79 seconds
Started Jun 07 08:45:30 PM PDT 24
Finished Jun 07 08:45:46 PM PDT 24
Peak memory 205852 kb
Host smart-b4947ce0-5602-436b-ab36-963fe72ef064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27482
40706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.2748240706
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.3056757737
Short name T1749
Test name
Test status
Simulation time 24616763529 ps
CPU time 119.74 seconds
Started Jun 07 08:45:36 PM PDT 24
Finished Jun 07 08:47:39 PM PDT 24
Peak memory 205796 kb
Host smart-13de191c-a295-49e7-8aff-0dcf52b07575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30567
57737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.3056757737
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2957610253
Short name T1746
Test name
Test status
Simulation time 10046102139 ps
CPU time 14.76 seconds
Started Jun 07 08:45:30 PM PDT 24
Finished Jun 07 08:45:48 PM PDT 24
Peak memory 205888 kb
Host smart-88cc4e60-51fa-4daf-b8cd-1e7610bcf8b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29576
10253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2957610253
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2335197219
Short name T110
Test name
Test status
Simulation time 10083334020 ps
CPU time 14.33 seconds
Started Jun 07 08:45:29 PM PDT 24
Finished Jun 07 08:45:47 PM PDT 24
Peak memory 205720 kb
Host smart-9b6921df-7a6e-4c64-8e02-83a444d2400d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23351
97219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2335197219
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.2202222240
Short name T614
Test name
Test status
Simulation time 10072399631 ps
CPU time 13.94 seconds
Started Jun 07 08:45:29 PM PDT 24
Finished Jun 07 08:45:47 PM PDT 24
Peak memory 205844 kb
Host smart-849c4374-c0e2-43d8-b986-4d775fdec0a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22022
22240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.2202222240
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.2415638754
Short name T1984
Test name
Test status
Simulation time 10081250953 ps
CPU time 13.84 seconds
Started Jun 07 08:45:27 PM PDT 24
Finished Jun 07 08:45:44 PM PDT 24
Peak memory 205884 kb
Host smart-c1520a47-22a4-4776-8e83-63f29d88e515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24156
38754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2415638754
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3378845104
Short name T808
Test name
Test status
Simulation time 10138584544 ps
CPU time 15.14 seconds
Started Jun 07 08:45:33 PM PDT 24
Finished Jun 07 08:45:51 PM PDT 24
Peak memory 205868 kb
Host smart-21bd9629-aa72-4c6e-921f-8ae89735aa2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33788
45104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3378845104
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.4095114007
Short name T1110
Test name
Test status
Simulation time 10046647475 ps
CPU time 15.65 seconds
Started Jun 07 08:45:43 PM PDT 24
Finished Jun 07 08:46:01 PM PDT 24
Peak memory 205848 kb
Host smart-2f82533b-5838-4b68-9b1f-fdac3e889394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40951
14007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.4095114007
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_eop_single_bit_handling.273101476
Short name T1843
Test name
Test status
Simulation time 10093972495 ps
CPU time 15.43 seconds
Started Jun 07 08:45:38 PM PDT 24
Finished Jun 07 08:45:56 PM PDT 24
Peak memory 205888 kb
Host smart-367efb6e-993a-45db-89cd-b1115dc06e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27310
1476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_eop_single_bit_handling.273101476
Directory /workspace/26.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.1649711798
Short name T1652
Test name
Test status
Simulation time 10038587288 ps
CPU time 13.01 seconds
Started Jun 07 08:45:47 PM PDT 24
Finished Jun 07 08:46:04 PM PDT 24
Peak memory 205824 kb
Host smart-1e7c472e-0632-4d04-be6b-42071c88d7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16497
11798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.1649711798
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.2278136425
Short name T893
Test name
Test status
Simulation time 10039127001 ps
CPU time 13.21 seconds
Started Jun 07 08:45:35 PM PDT 24
Finished Jun 07 08:45:52 PM PDT 24
Peak memory 205912 kb
Host smart-34124b03-1207-4e24-88c8-75a9d5e3a809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22781
36425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.2278136425
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3921711339
Short name T1245
Test name
Test status
Simulation time 23595254146 ps
CPU time 43.34 seconds
Started Jun 07 08:45:29 PM PDT 24
Finished Jun 07 08:46:16 PM PDT 24
Peak memory 205828 kb
Host smart-3145c1c3-697b-4046-b468-78f66dce679a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39217
11339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3921711339
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.1325677343
Short name T1529
Test name
Test status
Simulation time 10154880708 ps
CPU time 12.78 seconds
Started Jun 07 08:45:35 PM PDT 24
Finished Jun 07 08:45:51 PM PDT 24
Peak memory 205816 kb
Host smart-7858a56b-865f-424b-aaed-4b23fa717d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13256
77343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.1325677343
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.3377024005
Short name T296
Test name
Test status
Simulation time 10114638579 ps
CPU time 13.19 seconds
Started Jun 07 08:45:31 PM PDT 24
Finished Jun 07 08:45:47 PM PDT 24
Peak memory 205800 kb
Host smart-c6da6277-9f99-4de0-9ce1-d65937c20910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33770
24005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.3377024005
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.3243390580
Short name T284
Test name
Test status
Simulation time 10105693817 ps
CPU time 13.17 seconds
Started Jun 07 08:45:29 PM PDT 24
Finished Jun 07 08:45:45 PM PDT 24
Peak memory 205740 kb
Host smart-3c7632ac-8f6a-4c2b-952f-00b6d6bbe48a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32433
90580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.3243390580
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1240005117
Short name T1289
Test name
Test status
Simulation time 10064994714 ps
CPU time 13.09 seconds
Started Jun 07 08:45:30 PM PDT 24
Finished Jun 07 08:45:46 PM PDT 24
Peak memory 205812 kb
Host smart-84a86a59-da46-4fbb-9ac9-30b0b17af283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12400
05117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1240005117
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.2309210967
Short name T1088
Test name
Test status
Simulation time 10066723933 ps
CPU time 13.23 seconds
Started Jun 07 08:45:35 PM PDT 24
Finished Jun 07 08:45:52 PM PDT 24
Peak memory 205816 kb
Host smart-d3835b20-abb0-4440-9e4e-168c3a134563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23092
10967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.2309210967
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.3407783707
Short name T1399
Test name
Test status
Simulation time 10051965522 ps
CPU time 14.86 seconds
Started Jun 07 08:45:35 PM PDT 24
Finished Jun 07 08:45:53 PM PDT 24
Peak memory 205916 kb
Host smart-22609ede-885b-462f-bb6d-3514b78ca023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34077
83707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.3407783707
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.1071504839
Short name T1140
Test name
Test status
Simulation time 10139694943 ps
CPU time 13.19 seconds
Started Jun 07 08:45:25 PM PDT 24
Finished Jun 07 08:45:41 PM PDT 24
Peak memory 205796 kb
Host smart-d452a9b4-0efb-4927-af3c-9137b4697886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10715
04839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1071504839
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.2860400802
Short name T1433
Test name
Test status
Simulation time 10087881787 ps
CPU time 13.06 seconds
Started Jun 07 08:45:32 PM PDT 24
Finished Jun 07 08:45:48 PM PDT 24
Peak memory 205812 kb
Host smart-cea8332b-62c0-47dc-83ef-dd9fa67e5a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28604
00802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.2860400802
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.3435043295
Short name T1092
Test name
Test status
Simulation time 10140190330 ps
CPU time 13.62 seconds
Started Jun 07 08:45:35 PM PDT 24
Finished Jun 07 08:45:52 PM PDT 24
Peak memory 205760 kb
Host smart-5bcb5ec1-f940-4a65-b86d-a2724fb883fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34350
43295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.3435043295
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.323615082
Short name T1720
Test name
Test status
Simulation time 17698013109 ps
CPU time 70.67 seconds
Started Jun 07 08:45:29 PM PDT 24
Finished Jun 07 08:46:44 PM PDT 24
Peak memory 205856 kb
Host smart-4b7bc3b4-988e-41c4-a325-31c951d8ff21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32361
5082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.323615082
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.2751709570
Short name T788
Test name
Test status
Simulation time 10139165530 ps
CPU time 13.19 seconds
Started Jun 07 08:45:40 PM PDT 24
Finished Jun 07 08:45:55 PM PDT 24
Peak memory 205828 kb
Host smart-b9cd35cc-515e-4991-89ab-ef0b6e944151
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2751709570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.2751709570
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.3014648729
Short name T1258
Test name
Test status
Simulation time 10043759556 ps
CPU time 13 seconds
Started Jun 07 08:45:41 PM PDT 24
Finished Jun 07 08:45:56 PM PDT 24
Peak memory 205836 kb
Host smart-817303a3-2493-4539-beed-4b72222f069e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3014648729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.3014648729
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.4139783543
Short name T490
Test name
Test status
Simulation time 10065321553 ps
CPU time 13.08 seconds
Started Jun 07 08:45:46 PM PDT 24
Finished Jun 07 08:46:04 PM PDT 24
Peak memory 205788 kb
Host smart-ce17ec75-510b-4025-97f8-fb05c6b4ecf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41397
83543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.4139783543
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.1467812803
Short name T408
Test name
Test status
Simulation time 13815845113 ps
CPU time 20.51 seconds
Started Jun 07 08:45:34 PM PDT 24
Finished Jun 07 08:45:58 PM PDT 24
Peak memory 205880 kb
Host smart-c50beb34-1e71-4b61-8ea3-5c7bcd6abe0a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1467812803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.1467812803
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.3050393296
Short name T1909
Test name
Test status
Simulation time 23268283038 ps
CPU time 29.34 seconds
Started Jun 07 08:45:43 PM PDT 24
Finished Jun 07 08:46:15 PM PDT 24
Peak memory 205872 kb
Host smart-ec2e2fe0-21d1-43bf-95b7-a09be10023d4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3050393296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.3050393296
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.3469935994
Short name T636
Test name
Test status
Simulation time 10078055478 ps
CPU time 14.54 seconds
Started Jun 07 08:45:42 PM PDT 24
Finished Jun 07 08:46:00 PM PDT 24
Peak memory 205772 kb
Host smart-0c184df6-0169-4b50-b678-b32f85f727d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34699
35994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.3469935994
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.330985140
Short name T769
Test name
Test status
Simulation time 10425892605 ps
CPU time 15.28 seconds
Started Jun 07 08:45:34 PM PDT 24
Finished Jun 07 08:45:52 PM PDT 24
Peak memory 205760 kb
Host smart-8c650076-ebfe-4a70-8b50-e822f67b9b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33098
5140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.330985140
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.2166112792
Short name T431
Test name
Test status
Simulation time 10085099350 ps
CPU time 13.45 seconds
Started Jun 07 08:45:35 PM PDT 24
Finished Jun 07 08:45:52 PM PDT 24
Peak memory 205916 kb
Host smart-e5d3cad7-f2e5-41cb-9ac0-9ab446d91ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21661
12792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.2166112792
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.2976824466
Short name T1115
Test name
Test status
Simulation time 10075234932 ps
CPU time 12.88 seconds
Started Jun 07 08:45:36 PM PDT 24
Finished Jun 07 08:45:52 PM PDT 24
Peak memory 205856 kb
Host smart-c3d2ac2b-1bb1-4184-9d97-d6dba2cb4fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29768
24466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2976824466
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.4042851021
Short name T385
Test name
Test status
Simulation time 10555284484 ps
CPU time 16.9 seconds
Started Jun 07 08:45:35 PM PDT 24
Finished Jun 07 08:45:55 PM PDT 24
Peak memory 205848 kb
Host smart-537dd877-fdd7-42a1-a0eb-83e091eff558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40428
51021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.4042851021
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.3983958570
Short name T1298
Test name
Test status
Simulation time 10181628189 ps
CPU time 14.56 seconds
Started Jun 07 08:45:33 PM PDT 24
Finished Jun 07 08:45:51 PM PDT 24
Peak memory 205936 kb
Host smart-95a09512-8fb7-408c-ac26-fef8f66f6f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39839
58570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3983958570
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.332401303
Short name T1312
Test name
Test status
Simulation time 10080913891 ps
CPU time 13.36 seconds
Started Jun 07 08:46:00 PM PDT 24
Finished Jun 07 08:46:16 PM PDT 24
Peak memory 205764 kb
Host smart-0c493495-295d-4ded-a40c-107904830ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33240
1303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.332401303
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.107121793
Short name T1166
Test name
Test status
Simulation time 10074540305 ps
CPU time 13.17 seconds
Started Jun 07 08:45:41 PM PDT 24
Finished Jun 07 08:45:56 PM PDT 24
Peak memory 205816 kb
Host smart-1100e430-33b8-4828-8f9b-86c377d19b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10712
1793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.107121793
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.179486952
Short name T787
Test name
Test status
Simulation time 10115046148 ps
CPU time 13.94 seconds
Started Jun 07 08:45:33 PM PDT 24
Finished Jun 07 08:45:50 PM PDT 24
Peak memory 205740 kb
Host smart-1c0f1bdc-72d9-45aa-a76a-61ec68ee04ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17948
6952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.179486952
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.2381673389
Short name T1920
Test name
Test status
Simulation time 10114193279 ps
CPU time 13.25 seconds
Started Jun 07 08:45:35 PM PDT 24
Finished Jun 07 08:45:52 PM PDT 24
Peak memory 205796 kb
Host smart-480800d7-e798-47da-8af4-4e9032cfa95c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23816
73389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.2381673389
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.2639946565
Short name T735
Test name
Test status
Simulation time 13194882252 ps
CPU time 16.57 seconds
Started Jun 07 08:45:34 PM PDT 24
Finished Jun 07 08:45:55 PM PDT 24
Peak memory 205748 kb
Host smart-eaa8902f-996b-42a5-aa5e-22996effe966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26399
46565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.2639946565
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.3187270789
Short name T1057
Test name
Test status
Simulation time 10115446531 ps
CPU time 13.69 seconds
Started Jun 07 08:45:46 PM PDT 24
Finished Jun 07 08:46:05 PM PDT 24
Peak memory 205732 kb
Host smart-6030244a-1518-44b1-b602-74f19f6e4c25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31872
70789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.3187270789
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.824722776
Short name T506
Test name
Test status
Simulation time 22795144488 ps
CPU time 100.43 seconds
Started Jun 07 08:45:46 PM PDT 24
Finished Jun 07 08:47:32 PM PDT 24
Peak memory 205820 kb
Host smart-92fc4d10-ab80-4e23-80ac-4816d8f2bdfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82472
2776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.824722776
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.3298910561
Short name T1938
Test name
Test status
Simulation time 10093625360 ps
CPU time 15.54 seconds
Started Jun 07 08:45:42 PM PDT 24
Finished Jun 07 08:46:01 PM PDT 24
Peak memory 205776 kb
Host smart-2ea4c5d6-fc06-4c1f-bd89-67e0aab81bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32989
10561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.3298910561
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.3715645945
Short name T55
Test name
Test status
Simulation time 10160447166 ps
CPU time 14.88 seconds
Started Jun 07 08:45:37 PM PDT 24
Finished Jun 07 08:45:55 PM PDT 24
Peak memory 205736 kb
Host smart-5e0c19c0-abf6-46e9-b156-4cefb4cf29f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37156
45945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.3715645945
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.664501895
Short name T1022
Test name
Test status
Simulation time 10077687919 ps
CPU time 16.14 seconds
Started Jun 07 08:45:36 PM PDT 24
Finished Jun 07 08:45:56 PM PDT 24
Peak memory 205820 kb
Host smart-f22d1823-8848-478e-81c7-f57f04f10203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66450
1895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.664501895
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1040118106
Short name T1730
Test name
Test status
Simulation time 10097267765 ps
CPU time 12.68 seconds
Started Jun 07 08:45:33 PM PDT 24
Finished Jun 07 08:45:49 PM PDT 24
Peak memory 205872 kb
Host smart-70ba2e5e-0d51-4a04-8b40-846604532a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10401
18106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1040118106
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2100072182
Short name T1410
Test name
Test status
Simulation time 10062995261 ps
CPU time 13.68 seconds
Started Jun 07 08:45:42 PM PDT 24
Finished Jun 07 08:45:58 PM PDT 24
Peak memory 205844 kb
Host smart-88f50c0d-b401-4220-8fb3-f4d78350449c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21000
72182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2100072182
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.4148761612
Short name T140
Test name
Test status
Simulation time 10052701733 ps
CPU time 13.57 seconds
Started Jun 07 08:45:45 PM PDT 24
Finished Jun 07 08:46:03 PM PDT 24
Peak memory 205876 kb
Host smart-f42bf1be-7bd8-457d-89fc-941e191f9681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41487
61612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.4148761612
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_eop_single_bit_handling.160101969
Short name T919
Test name
Test status
Simulation time 10057787021 ps
CPU time 13.44 seconds
Started Jun 07 08:45:41 PM PDT 24
Finished Jun 07 08:45:57 PM PDT 24
Peak memory 205816 kb
Host smart-c4d7b074-3900-49e4-b05d-2eca574c5fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16010
1969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_eop_single_bit_handling.160101969
Directory /workspace/27.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.2671177212
Short name T611
Test name
Test status
Simulation time 10067312474 ps
CPU time 13.74 seconds
Started Jun 07 08:45:45 PM PDT 24
Finished Jun 07 08:46:03 PM PDT 24
Peak memory 205776 kb
Host smart-7d82324b-4c1f-455e-a288-4ac2749a56c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26711
77212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.2671177212
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.1630918782
Short name T731
Test name
Test status
Simulation time 10033691325 ps
CPU time 12.76 seconds
Started Jun 07 08:45:42 PM PDT 24
Finished Jun 07 08:45:58 PM PDT 24
Peak memory 205808 kb
Host smart-59bf6741-bb65-4517-9152-a463bfd1807d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16309
18782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.1630918782
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.933595904
Short name T236
Test name
Test status
Simulation time 20283062630 ps
CPU time 35.39 seconds
Started Jun 07 08:45:46 PM PDT 24
Finished Jun 07 08:46:26 PM PDT 24
Peak memory 205772 kb
Host smart-e40b0fce-f9d9-4007-a3ea-9050cf92d3b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93359
5904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.933595904
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.2852514665
Short name T509
Test name
Test status
Simulation time 10116719898 ps
CPU time 13.88 seconds
Started Jun 07 08:45:45 PM PDT 24
Finished Jun 07 08:46:04 PM PDT 24
Peak memory 205852 kb
Host smart-61e14652-77cd-4066-9a28-d763bd8dbb1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28525
14665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.2852514665
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.2240737203
Short name T1726
Test name
Test status
Simulation time 10117634140 ps
CPU time 15.48 seconds
Started Jun 07 08:45:37 PM PDT 24
Finished Jun 07 08:45:56 PM PDT 24
Peak memory 205876 kb
Host smart-aba5810a-baf0-44e7-a1ed-099bdb69542f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22407
37203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2240737203
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.771012914
Short name T848
Test name
Test status
Simulation time 10065800535 ps
CPU time 13.12 seconds
Started Jun 07 08:45:36 PM PDT 24
Finished Jun 07 08:45:52 PM PDT 24
Peak memory 205752 kb
Host smart-a5811fe9-f881-4010-ae3b-49bc106ac88c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77101
2914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.771012914
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.1202332302
Short name T578
Test name
Test status
Simulation time 10042351704 ps
CPU time 12.74 seconds
Started Jun 07 08:45:36 PM PDT 24
Finished Jun 07 08:45:52 PM PDT 24
Peak memory 205744 kb
Host smart-9a4aad77-8684-4bb4-86e7-a30d5796779f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12023
32302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.1202332302
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.1270059598
Short name T83
Test name
Test status
Simulation time 10078419871 ps
CPU time 12.2 seconds
Started Jun 07 08:45:42 PM PDT 24
Finished Jun 07 08:45:57 PM PDT 24
Peak memory 205808 kb
Host smart-87e9d4f0-6bb2-46b2-b0c8-6063b3e2809c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12700
59598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1270059598
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.2696507517
Short name T1489
Test name
Test status
Simulation time 10131978201 ps
CPU time 12.61 seconds
Started Jun 07 08:45:35 PM PDT 24
Finished Jun 07 08:45:52 PM PDT 24
Peak memory 205772 kb
Host smart-c7b7d6a5-c9b7-47fb-ac49-cf4d394fce96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26965
07517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.2696507517
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.4188670605
Short name T1713
Test name
Test status
Simulation time 10112903201 ps
CPU time 13.61 seconds
Started Jun 07 08:45:33 PM PDT 24
Finished Jun 07 08:45:50 PM PDT 24
Peak memory 205848 kb
Host smart-00f99f87-afda-416e-84e2-a26f6674d0b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41886
70605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.4188670605
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3507131529
Short name T1767
Test name
Test status
Simulation time 10055888850 ps
CPU time 13.35 seconds
Started Jun 07 08:45:39 PM PDT 24
Finished Jun 07 08:45:54 PM PDT 24
Peak memory 205832 kb
Host smart-d78fe447-f15d-423e-b5e6-9e837a1a5f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35071
31529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3507131529
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.3001512532
Short name T1695
Test name
Test status
Simulation time 10083098695 ps
CPU time 12.99 seconds
Started Jun 07 08:45:46 PM PDT 24
Finished Jun 07 08:46:04 PM PDT 24
Peak memory 205824 kb
Host smart-5bc3e592-fe2f-4741-9836-196a64d9396e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30015
12532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.3001512532
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.719277353
Short name T805
Test name
Test status
Simulation time 14861674735 ps
CPU time 57 seconds
Started Jun 07 08:45:47 PM PDT 24
Finished Jun 07 08:46:48 PM PDT 24
Peak memory 205848 kb
Host smart-ee0ea409-dd2a-4f4b-8fac-ab3eb2c81294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71927
7353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.719277353
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.2395231861
Short name T712
Test name
Test status
Simulation time 10135871506 ps
CPU time 13.82 seconds
Started Jun 07 08:45:48 PM PDT 24
Finished Jun 07 08:46:07 PM PDT 24
Peak memory 205832 kb
Host smart-75b55739-7633-406a-9ba7-e7435c60a227
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2395231861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.2395231861
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.1625511476
Short name T1690
Test name
Test status
Simulation time 10073527580 ps
CPU time 13.33 seconds
Started Jun 07 08:45:48 PM PDT 24
Finished Jun 07 08:46:06 PM PDT 24
Peak memory 205760 kb
Host smart-161791c3-bdfc-4bc6-b8ea-991387b01a18
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1625511476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.1625511476
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.2849509170
Short name T461
Test name
Test status
Simulation time 10133375118 ps
CPU time 12.98 seconds
Started Jun 07 08:45:50 PM PDT 24
Finished Jun 07 08:46:08 PM PDT 24
Peak memory 205720 kb
Host smart-e813008c-5c7e-4421-a0e7-e82638cc8a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28495
09170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.2849509170
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.2958789923
Short name T738
Test name
Test status
Simulation time 14101032509 ps
CPU time 17.54 seconds
Started Jun 07 08:45:43 PM PDT 24
Finished Jun 07 08:46:05 PM PDT 24
Peak memory 205908 kb
Host smart-a4d5e076-6237-4959-8c26-efb875f418a7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2958789923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.2958789923
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.1596205935
Short name T1910
Test name
Test status
Simulation time 23271781318 ps
CPU time 23.91 seconds
Started Jun 07 08:45:42 PM PDT 24
Finished Jun 07 08:46:09 PM PDT 24
Peak memory 205876 kb
Host smart-85fbad1e-0877-47c9-bd94-63c88101fa9f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1596205935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.1596205935
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.2272181653
Short name T1304
Test name
Test status
Simulation time 10056081850 ps
CPU time 13.65 seconds
Started Jun 07 08:45:40 PM PDT 24
Finished Jun 07 08:45:55 PM PDT 24
Peak memory 205748 kb
Host smart-6ef23992-c471-4559-a051-be27a3eddeed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22721
81653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.2272181653
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.1013713732
Short name T1083
Test name
Test status
Simulation time 10115282257 ps
CPU time 14.2 seconds
Started Jun 07 08:45:45 PM PDT 24
Finished Jun 07 08:46:04 PM PDT 24
Peak memory 205788 kb
Host smart-257871c7-6a7e-435a-8c99-1ead6ce07ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10137
13732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.1013713732
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.897801842
Short name T2008
Test name
Test status
Simulation time 11210954424 ps
CPU time 17.65 seconds
Started Jun 07 08:45:42 PM PDT 24
Finished Jun 07 08:46:02 PM PDT 24
Peak memory 205792 kb
Host smart-8d8f4728-683e-42b2-a350-0ed9276b5314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89780
1842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.897801842
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.110161871
Short name T1336
Test name
Test status
Simulation time 10045817706 ps
CPU time 12.79 seconds
Started Jun 07 08:45:45 PM PDT 24
Finished Jun 07 08:46:03 PM PDT 24
Peak memory 205472 kb
Host smart-2a57d152-23e8-44b2-8667-84cc15602f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11016
1871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.110161871
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.2949749068
Short name T746
Test name
Test status
Simulation time 10087979966 ps
CPU time 15.64 seconds
Started Jun 07 08:45:40 PM PDT 24
Finished Jun 07 08:45:57 PM PDT 24
Peak memory 205828 kb
Host smart-a671415c-a868-4558-be27-c369c10e393a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29497
49068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.2949749068
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.765472711
Short name T1444
Test name
Test status
Simulation time 10803935849 ps
CPU time 16.03 seconds
Started Jun 07 08:45:41 PM PDT 24
Finished Jun 07 08:45:59 PM PDT 24
Peak memory 205772 kb
Host smart-05e1689e-6251-4efd-bff4-05a949442178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76547
2711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.765472711
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.416025699
Short name T1053
Test name
Test status
Simulation time 10220962147 ps
CPU time 14.57 seconds
Started Jun 07 08:45:42 PM PDT 24
Finished Jun 07 08:45:59 PM PDT 24
Peak memory 205896 kb
Host smart-15ebdc10-b2e4-4f28-a03a-3812e20431d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41602
5699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.416025699
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.468195700
Short name T992
Test name
Test status
Simulation time 10122081343 ps
CPU time 13.19 seconds
Started Jun 07 08:45:46 PM PDT 24
Finished Jun 07 08:46:04 PM PDT 24
Peak memory 205776 kb
Host smart-694ab489-a9b0-44b4-be10-d7f3eda68703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46819
5700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.468195700
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.2198026627
Short name T1735
Test name
Test status
Simulation time 10073232299 ps
CPU time 12.71 seconds
Started Jun 07 08:45:47 PM PDT 24
Finished Jun 07 08:46:04 PM PDT 24
Peak memory 205844 kb
Host smart-6cd0225b-e8f8-4bab-bca0-a5c57830d7e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21980
26627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.2198026627
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.1593377204
Short name T928
Test name
Test status
Simulation time 10101525031 ps
CPU time 12.95 seconds
Started Jun 07 08:45:43 PM PDT 24
Finished Jun 07 08:45:58 PM PDT 24
Peak memory 205872 kb
Host smart-71dd6223-0e7d-4ce4-b818-da747aa928d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15933
77204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.1593377204
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.407615463
Short name T1973
Test name
Test status
Simulation time 10160415068 ps
CPU time 13.1 seconds
Started Jun 07 08:45:48 PM PDT 24
Finished Jun 07 08:46:06 PM PDT 24
Peak memory 205852 kb
Host smart-c3f5c27d-15bd-48ee-981a-f4dbfc7f014b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40761
5463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.407615463
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.1997305657
Short name T1898
Test name
Test status
Simulation time 13201948709 ps
CPU time 15.55 seconds
Started Jun 07 08:45:42 PM PDT 24
Finished Jun 07 08:46:00 PM PDT 24
Peak memory 205696 kb
Host smart-0859c28c-19b4-49b5-9831-c3d980f9e24c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19973
05657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.1997305657
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1244570818
Short name T969
Test name
Test status
Simulation time 10095240018 ps
CPU time 12.47 seconds
Started Jun 07 08:45:42 PM PDT 24
Finished Jun 07 08:45:57 PM PDT 24
Peak memory 205720 kb
Host smart-879a21ff-c156-4c52-83a9-70e6dc69a94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12445
70818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1244570818
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.3683540318
Short name T1000
Test name
Test status
Simulation time 17943919260 ps
CPU time 231.11 seconds
Started Jun 07 08:45:45 PM PDT 24
Finished Jun 07 08:49:41 PM PDT 24
Peak memory 205488 kb
Host smart-91c0cb66-fbc0-4f55-8532-8a49b1831236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36835
40318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.3683540318
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.498125911
Short name T1858
Test name
Test status
Simulation time 10072168796 ps
CPU time 13.24 seconds
Started Jun 07 08:45:45 PM PDT 24
Finished Jun 07 08:46:03 PM PDT 24
Peak memory 205680 kb
Host smart-e739f359-7fbc-4ff7-ba75-efae7f3c592e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49812
5911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.498125911
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.452496604
Short name T117
Test name
Test status
Simulation time 10144768788 ps
CPU time 13.73 seconds
Started Jun 07 08:45:43 PM PDT 24
Finished Jun 07 08:46:00 PM PDT 24
Peak memory 205848 kb
Host smart-ef4ec14f-b424-430b-a2a0-f24c9a3c148e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45249
6604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.452496604
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.3810673081
Short name T2021
Test name
Test status
Simulation time 10082490807 ps
CPU time 13.29 seconds
Started Jun 07 08:45:43 PM PDT 24
Finished Jun 07 08:45:59 PM PDT 24
Peak memory 205752 kb
Host smart-3b4992e2-6d72-4a30-943a-24bf5ab7e0a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38106
73081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.3810673081
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1269780631
Short name T1353
Test name
Test status
Simulation time 10049916670 ps
CPU time 15.2 seconds
Started Jun 07 08:45:43 PM PDT 24
Finished Jun 07 08:46:01 PM PDT 24
Peak memory 205844 kb
Host smart-ede13954-c8ad-450c-b4e5-8cf1e28712ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12697
80631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1269780631
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.753054509
Short name T926
Test name
Test status
Simulation time 10091640400 ps
CPU time 13.93 seconds
Started Jun 07 08:45:42 PM PDT 24
Finished Jun 07 08:45:59 PM PDT 24
Peak memory 205860 kb
Host smart-3d4b5619-ecf8-4827-b6da-a8600fb35563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75305
4509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.753054509
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1631672280
Short name T884
Test name
Test status
Simulation time 10091338654 ps
CPU time 13.85 seconds
Started Jun 07 08:45:46 PM PDT 24
Finished Jun 07 08:46:05 PM PDT 24
Peak memory 205912 kb
Host smart-f52e2aef-3cd4-493e-b356-07eca912829f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16316
72280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1631672280
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_eop_single_bit_handling.1391719712
Short name T1727
Test name
Test status
Simulation time 10087176918 ps
CPU time 12.92 seconds
Started Jun 07 08:45:48 PM PDT 24
Finished Jun 07 08:46:06 PM PDT 24
Peak memory 205772 kb
Host smart-88175973-0589-46f4-b70a-f0b61f11777e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13917
19712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_eop_single_bit_handling.1391719712
Directory /workspace/28.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.4045169054
Short name T286
Test name
Test status
Simulation time 10052849904 ps
CPU time 12.99 seconds
Started Jun 07 08:45:46 PM PDT 24
Finished Jun 07 08:46:04 PM PDT 24
Peak memory 205812 kb
Host smart-2d34afe9-e073-439e-9a33-d6689eaa860b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40451
69054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.4045169054
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.3903721771
Short name T800
Test name
Test status
Simulation time 10027780333 ps
CPU time 13.04 seconds
Started Jun 07 08:45:46 PM PDT 24
Finished Jun 07 08:46:04 PM PDT 24
Peak memory 205720 kb
Host smart-61563856-fec0-4c50-a2bb-d1c303049f02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39037
21771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.3903721771
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.4134740882
Short name T256
Test name
Test status
Simulation time 16363804087 ps
CPU time 29.91 seconds
Started Jun 07 08:45:45 PM PDT 24
Finished Jun 07 08:46:19 PM PDT 24
Peak memory 205768 kb
Host smart-5db68c3e-6c38-4045-a210-61f3b91ed435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41347
40882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.4134740882
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2702587741
Short name T360
Test name
Test status
Simulation time 10062457687 ps
CPU time 13 seconds
Started Jun 07 08:45:43 PM PDT 24
Finished Jun 07 08:46:00 PM PDT 24
Peak memory 205776 kb
Host smart-f2b8e59c-ad83-4132-bcff-3d3ad34f8f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27025
87741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2702587741
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2508693464
Short name T449
Test name
Test status
Simulation time 10064476969 ps
CPU time 13.99 seconds
Started Jun 07 08:45:48 PM PDT 24
Finished Jun 07 08:46:06 PM PDT 24
Peak memory 205764 kb
Host smart-9f4ad817-4b0e-46d9-87d0-91e4aa8b8125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25086
93464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2508693464
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.2433660934
Short name T1930
Test name
Test status
Simulation time 10081384205 ps
CPU time 13.55 seconds
Started Jun 07 08:45:47 PM PDT 24
Finished Jun 07 08:46:05 PM PDT 24
Peak memory 205752 kb
Host smart-c60d0e3a-779f-4ef5-bfe8-8f8c0c53b2ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24336
60934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.2433660934
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.2875915785
Short name T1174
Test name
Test status
Simulation time 10048606537 ps
CPU time 12.41 seconds
Started Jun 07 08:45:44 PM PDT 24
Finished Jun 07 08:46:01 PM PDT 24
Peak memory 205748 kb
Host smart-0855aa38-0345-49d1-a070-37c3857e84e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28759
15785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.2875915785
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2731072102
Short name T673
Test name
Test status
Simulation time 10055376654 ps
CPU time 13.11 seconds
Started Jun 07 08:45:51 PM PDT 24
Finished Jun 07 08:46:08 PM PDT 24
Peak memory 205784 kb
Host smart-a1ef7308-4bd0-4bff-a071-02795182700c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27310
72102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2731072102
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.2399896434
Short name T374
Test name
Test status
Simulation time 10056149223 ps
CPU time 13.06 seconds
Started Jun 07 08:45:49 PM PDT 24
Finished Jun 07 08:46:06 PM PDT 24
Peak memory 205788 kb
Host smart-2d828622-d21b-4bdc-88f0-37081b0590bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23998
96434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.2399896434
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3899320052
Short name T1449
Test name
Test status
Simulation time 10139228806 ps
CPU time 13.39 seconds
Started Jun 07 08:45:42 PM PDT 24
Finished Jun 07 08:45:58 PM PDT 24
Peak memory 205744 kb
Host smart-714c0bfa-b02a-4a3c-be96-d0207e6fa74f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38993
20052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3899320052
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.622977853
Short name T1815
Test name
Test status
Simulation time 10054733756 ps
CPU time 14.51 seconds
Started Jun 07 08:45:48 PM PDT 24
Finished Jun 07 08:46:07 PM PDT 24
Peak memory 205884 kb
Host smart-2ae6ece5-ccf4-4c9d-89bd-54eddaccd80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62297
7853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.622977853
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.2396419238
Short name T1923
Test name
Test status
Simulation time 10060814342 ps
CPU time 14 seconds
Started Jun 07 08:45:46 PM PDT 24
Finished Jun 07 08:46:05 PM PDT 24
Peak memory 205756 kb
Host smart-d36b4b28-db70-4aa1-be86-f7d77c87c4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23964
19238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2396419238
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.3524926588
Short name T1025
Test name
Test status
Simulation time 19065964579 ps
CPU time 258.24 seconds
Started Jun 07 08:45:46 PM PDT 24
Finished Jun 07 08:50:09 PM PDT 24
Peak memory 205772 kb
Host smart-fef93f28-6c59-4ac4-8173-4404ef6691b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35249
26588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.3524926588
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.639696054
Short name T678
Test name
Test status
Simulation time 10135038317 ps
CPU time 13.61 seconds
Started Jun 07 08:45:56 PM PDT 24
Finished Jun 07 08:46:12 PM PDT 24
Peak memory 205724 kb
Host smart-8291aae9-88db-45ed-9ed5-9e0c8e98c799
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=639696054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.639696054
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.2745265743
Short name T1507
Test name
Test status
Simulation time 10066359513 ps
CPU time 15.06 seconds
Started Jun 07 08:45:57 PM PDT 24
Finished Jun 07 08:46:15 PM PDT 24
Peak memory 205732 kb
Host smart-0c21eaa6-d0ff-4acf-a58a-ec18f32b6eda
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2745265743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.2745265743
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.3741681940
Short name T1731
Test name
Test status
Simulation time 10150678500 ps
CPU time 13.5 seconds
Started Jun 07 08:45:52 PM PDT 24
Finished Jun 07 08:46:10 PM PDT 24
Peak memory 205928 kb
Host smart-c2f5b56c-2bdf-49c4-a69d-d6c64b1e60df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37416
81940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.3741681940
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1214736681
Short name T1457
Test name
Test status
Simulation time 13890787666 ps
CPU time 18.6 seconds
Started Jun 07 08:45:49 PM PDT 24
Finished Jun 07 08:46:12 PM PDT 24
Peak memory 205808 kb
Host smart-c9aec298-3d52-47d5-bf9e-5300c31f315a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1214736681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.1214736681
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.2917383003
Short name T1004
Test name
Test status
Simulation time 23204925689 ps
CPU time 27.76 seconds
Started Jun 07 08:45:46 PM PDT 24
Finished Jun 07 08:46:19 PM PDT 24
Peak memory 205860 kb
Host smart-ca04b9d1-4731-4c3f-92ab-216951a4b64f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2917383003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.2917383003
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.285387650
Short name T1777
Test name
Test status
Simulation time 10066598777 ps
CPU time 14.62 seconds
Started Jun 07 08:45:48 PM PDT 24
Finished Jun 07 08:46:07 PM PDT 24
Peak memory 205876 kb
Host smart-c6409815-778d-4368-9703-d5b6b8305a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28538
7650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.285387650
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.3259350465
Short name T1520
Test name
Test status
Simulation time 10122422138 ps
CPU time 12.96 seconds
Started Jun 07 08:45:47 PM PDT 24
Finished Jun 07 08:46:04 PM PDT 24
Peak memory 205876 kb
Host smart-0d412604-f312-4ac5-a21e-25f3bce659ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32593
50465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.3259350465
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.667916566
Short name T1890
Test name
Test status
Simulation time 10038519968 ps
CPU time 12.59 seconds
Started Jun 07 08:45:48 PM PDT 24
Finished Jun 07 08:46:04 PM PDT 24
Peak memory 205848 kb
Host smart-09e6b90a-3be1-40d7-bece-9309be63ad4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66791
6566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.667916566
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.2768007301
Short name T1186
Test name
Test status
Simulation time 10088905465 ps
CPU time 12.06 seconds
Started Jun 07 08:45:48 PM PDT 24
Finished Jun 07 08:46:05 PM PDT 24
Peak memory 205800 kb
Host smart-bba8c2e6-0935-4cc2-8fd2-dadd53c60f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27680
07301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.2768007301
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.3589966919
Short name T1922
Test name
Test status
Simulation time 10663531453 ps
CPU time 15.08 seconds
Started Jun 07 08:45:48 PM PDT 24
Finished Jun 07 08:46:08 PM PDT 24
Peak memory 205768 kb
Host smart-29cbfec2-ded0-427b-93ab-8691f925ed10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35899
66919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3589966919
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1129145093
Short name T1159
Test name
Test status
Simulation time 10083549332 ps
CPU time 15.47 seconds
Started Jun 07 08:45:49 PM PDT 24
Finished Jun 07 08:46:09 PM PDT 24
Peak memory 205784 kb
Host smart-6fe4f56d-fa77-4aab-9525-fd3ec8552c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11291
45093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1129145093
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.3740834737
Short name T73
Test name
Test status
Simulation time 10059503889 ps
CPU time 14.49 seconds
Started Jun 07 08:45:55 PM PDT 24
Finished Jun 07 08:46:12 PM PDT 24
Peak memory 205856 kb
Host smart-7d30087d-d985-4f01-be02-c4d2b328e971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37408
34737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.3740834737
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.384635609
Short name T328
Test name
Test status
Simulation time 10044506909 ps
CPU time 12.85 seconds
Started Jun 07 08:45:54 PM PDT 24
Finished Jun 07 08:46:10 PM PDT 24
Peak memory 205732 kb
Host smart-d11460c7-c9aa-4897-9da1-44a317d87d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38463
5609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.384635609
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3352438258
Short name T1748
Test name
Test status
Simulation time 10132327901 ps
CPU time 14.17 seconds
Started Jun 07 08:45:47 PM PDT 24
Finished Jun 07 08:46:06 PM PDT 24
Peak memory 205828 kb
Host smart-43604acc-a572-4d2c-976c-9b2a7b77959a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33524
38258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3352438258
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.3899902694
Short name T906
Test name
Test status
Simulation time 10156529765 ps
CPU time 13.45 seconds
Started Jun 07 08:45:50 PM PDT 24
Finished Jun 07 08:46:07 PM PDT 24
Peak memory 205800 kb
Host smart-c1fb1e60-8e2b-4d87-8a6a-22000cfc7468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38999
02694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.3899902694
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.3189166319
Short name T795
Test name
Test status
Simulation time 13224842551 ps
CPU time 17.49 seconds
Started Jun 07 08:45:49 PM PDT 24
Finished Jun 07 08:46:11 PM PDT 24
Peak memory 205760 kb
Host smart-7759f803-e8eb-49c4-9776-76391724440c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31891
66319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.3189166319
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3863411409
Short name T80
Test name
Test status
Simulation time 10088173744 ps
CPU time 14.36 seconds
Started Jun 07 08:45:48 PM PDT 24
Finished Jun 07 08:46:07 PM PDT 24
Peak memory 205772 kb
Host smart-633959cf-f101-4b11-bd72-ad51423e63cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38634
11409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3863411409
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.1438563868
Short name T500
Test name
Test status
Simulation time 19729808268 ps
CPU time 78.69 seconds
Started Jun 07 08:45:45 PM PDT 24
Finished Jun 07 08:47:09 PM PDT 24
Peak memory 205788 kb
Host smart-3f4b9563-4db7-4a09-8791-bb32706aedb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14385
63868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.1438563868
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.1903428587
Short name T1319
Test name
Test status
Simulation time 10046143805 ps
CPU time 13.03 seconds
Started Jun 07 08:45:51 PM PDT 24
Finished Jun 07 08:46:08 PM PDT 24
Peak memory 205968 kb
Host smart-950a1462-53ce-4aea-b0af-acf60762e891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19034
28587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.1903428587
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.963300415
Short name T1589
Test name
Test status
Simulation time 10083253906 ps
CPU time 12.7 seconds
Started Jun 07 08:45:46 PM PDT 24
Finished Jun 07 08:46:04 PM PDT 24
Peak memory 205664 kb
Host smart-69101598-f4d7-481e-a932-92617bc9d421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96330
0415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.963300415
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.3993428794
Short name T306
Test name
Test status
Simulation time 10081346742 ps
CPU time 15.64 seconds
Started Jun 07 08:45:47 PM PDT 24
Finished Jun 07 08:46:07 PM PDT 24
Peak memory 205716 kb
Host smart-105bdb5c-522e-4f97-8ab3-d6ec9474d95e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39934
28794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.3993428794
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2237168482
Short name T1084
Test name
Test status
Simulation time 10082748996 ps
CPU time 12.78 seconds
Started Jun 07 08:45:53 PM PDT 24
Finished Jun 07 08:46:09 PM PDT 24
Peak memory 205872 kb
Host smart-33ca8896-4e8d-480f-8075-351821d302f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22371
68482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2237168482
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.4097963374
Short name T300
Test name
Test status
Simulation time 10052731494 ps
CPU time 13.25 seconds
Started Jun 07 08:45:55 PM PDT 24
Finished Jun 07 08:46:11 PM PDT 24
Peak memory 205668 kb
Host smart-2285fa50-8fe3-4809-a772-0c4c28879b10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40979
63374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.4097963374
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.211424403
Short name T1129
Test name
Test status
Simulation time 10066423347 ps
CPU time 13.12 seconds
Started Jun 07 08:45:52 PM PDT 24
Finished Jun 07 08:46:09 PM PDT 24
Peak memory 205816 kb
Host smart-7d406cf3-980c-4b29-8543-2fe682ca4d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21142
4403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.211424403
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_eop_single_bit_handling.3335514364
Short name T793
Test name
Test status
Simulation time 10071916946 ps
CPU time 14.61 seconds
Started Jun 07 08:45:56 PM PDT 24
Finished Jun 07 08:46:14 PM PDT 24
Peak memory 205888 kb
Host smart-c05cc8aa-c95b-45fd-926a-7059e75e0342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33355
14364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_eop_single_bit_handling.3335514364
Directory /workspace/29.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2350956830
Short name T592
Test name
Test status
Simulation time 10061783563 ps
CPU time 13 seconds
Started Jun 07 08:45:58 PM PDT 24
Finished Jun 07 08:46:13 PM PDT 24
Peak memory 205804 kb
Host smart-d5051c77-e68c-48c2-a675-29685196ea6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23509
56830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.2350956830
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2946883986
Short name T789
Test name
Test status
Simulation time 10082565046 ps
CPU time 13.14 seconds
Started Jun 07 08:45:53 PM PDT 24
Finished Jun 07 08:46:10 PM PDT 24
Peak memory 205804 kb
Host smart-3c510300-666d-4a13-9bdf-29147a50ec4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29468
83986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2946883986
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2482788631
Short name T1684
Test name
Test status
Simulation time 22916162247 ps
CPU time 47.6 seconds
Started Jun 07 08:45:53 PM PDT 24
Finished Jun 07 08:46:45 PM PDT 24
Peak memory 205764 kb
Host smart-daba7381-7045-45ba-8be1-866cb7e49acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24827
88631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2482788631
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.2200643633
Short name T1941
Test name
Test status
Simulation time 10057806553 ps
CPU time 15.26 seconds
Started Jun 07 08:45:53 PM PDT 24
Finished Jun 07 08:46:12 PM PDT 24
Peak memory 205948 kb
Host smart-410fc21f-8aec-46ce-b62e-2d27af767d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22006
43633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.2200643633
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.3999608591
Short name T1931
Test name
Test status
Simulation time 10175859101 ps
CPU time 14.09 seconds
Started Jun 07 08:46:07 PM PDT 24
Finished Jun 07 08:46:24 PM PDT 24
Peak memory 205792 kb
Host smart-2dcc2905-73cb-416c-82b0-db9da7020ed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39996
08591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.3999608591
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.2972862846
Short name T563
Test name
Test status
Simulation time 10067193363 ps
CPU time 12.71 seconds
Started Jun 07 08:46:07 PM PDT 24
Finished Jun 07 08:46:23 PM PDT 24
Peak memory 205768 kb
Host smart-bd7b0427-826f-4aba-b2c8-78ba0de57971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29728
62846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.2972862846
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.741551382
Short name T1081
Test name
Test status
Simulation time 10051000218 ps
CPU time 13.75 seconds
Started Jun 07 08:45:58 PM PDT 24
Finished Jun 07 08:46:15 PM PDT 24
Peak memory 205872 kb
Host smart-190c155c-77a6-49e3-9fa3-231268eb44a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74155
1382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.741551382
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.2255826709
Short name T1515
Test name
Test status
Simulation time 10071408039 ps
CPU time 13.35 seconds
Started Jun 07 08:45:53 PM PDT 24
Finished Jun 07 08:46:10 PM PDT 24
Peak memory 205716 kb
Host smart-166a3fbd-9df6-4bf2-94d8-08b5a0a72b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22558
26709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.2255826709
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3502963044
Short name T1674
Test name
Test status
Simulation time 10059588975 ps
CPU time 13.27 seconds
Started Jun 07 08:45:53 PM PDT 24
Finished Jun 07 08:46:10 PM PDT 24
Peak memory 205876 kb
Host smart-b1f7de0f-1a5a-425c-83cd-ab143596654b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35029
63044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3502963044
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1045793203
Short name T152
Test name
Test status
Simulation time 10111927768 ps
CPU time 16.07 seconds
Started Jun 07 08:45:44 PM PDT 24
Finished Jun 07 08:46:04 PM PDT 24
Peak memory 205796 kb
Host smart-a78f3452-ea08-4bc7-9f3c-dc8d5c6268cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10457
93203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1045793203
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.2679374789
Short name T1227
Test name
Test status
Simulation time 10051489856 ps
CPU time 14.61 seconds
Started Jun 07 08:45:55 PM PDT 24
Finished Jun 07 08:46:13 PM PDT 24
Peak memory 205864 kb
Host smart-8c2d95ff-d1fb-4b4e-852d-882f6b6c1a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26793
74789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.2679374789
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.1292363042
Short name T1378
Test name
Test status
Simulation time 10082646723 ps
CPU time 14.61 seconds
Started Jun 07 08:45:53 PM PDT 24
Finished Jun 07 08:46:11 PM PDT 24
Peak memory 205816 kb
Host smart-c520ae10-5517-4f66-ac10-9924eebdcb3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12923
63042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.1292363042
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.3365453848
Short name T1852
Test name
Test status
Simulation time 16420991874 ps
CPU time 72.44 seconds
Started Jun 07 08:45:58 PM PDT 24
Finished Jun 07 08:47:13 PM PDT 24
Peak memory 205844 kb
Host smart-a74bc829-4925-4aa3-a46c-222baa962fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33654
53848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.3365453848
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.1650842981
Short name T1801
Test name
Test status
Simulation time 10145382650 ps
CPU time 13.56 seconds
Started Jun 07 08:41:29 PM PDT 24
Finished Jun 07 08:41:45 PM PDT 24
Peak memory 205852 kb
Host smart-cd233774-a7f3-4ef7-993f-cb80326008ae
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1650842981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.1650842981
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.2060949069
Short name T845
Test name
Test status
Simulation time 10063243272 ps
CPU time 13.09 seconds
Started Jun 07 08:41:30 PM PDT 24
Finished Jun 07 08:41:45 PM PDT 24
Peak memory 205852 kb
Host smart-281e2323-d6c0-444f-9c0d-bca4f8c22d83
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2060949069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.2060949069
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.3558845854
Short name T1774
Test name
Test status
Simulation time 10083341711 ps
CPU time 13.84 seconds
Started Jun 07 08:41:29 PM PDT 24
Finished Jun 07 08:41:46 PM PDT 24
Peak memory 205844 kb
Host smart-feaad104-2367-4ac2-9fdf-2f28c53e9cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35588
45854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.3558845854
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.514012358
Short name T1796
Test name
Test status
Simulation time 13450685575 ps
CPU time 18.39 seconds
Started Jun 07 08:41:11 PM PDT 24
Finished Jun 07 08:41:33 PM PDT 24
Peak memory 205800 kb
Host smart-3f82c7fc-5a88-4743-9a7d-a3c4bec48bdb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=514012358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.514012358
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.4016427278
Short name T1586
Test name
Test status
Simulation time 23261773374 ps
CPU time 23.99 seconds
Started Jun 07 08:41:16 PM PDT 24
Finished Jun 07 08:41:44 PM PDT 24
Peak memory 205652 kb
Host smart-98d029fc-bafc-4c17-8d53-93f72d7c1858
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4016427278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.4016427278
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.3742345495
Short name T811
Test name
Test status
Simulation time 10059414170 ps
CPU time 16.09 seconds
Started Jun 07 08:41:16 PM PDT 24
Finished Jun 07 08:41:36 PM PDT 24
Peak memory 205828 kb
Host smart-b76f0a43-f7df-48af-bb99-f738a3b8a445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37423
45495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.3742345495
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.3294022572
Short name T1061
Test name
Test status
Simulation time 10325199944 ps
CPU time 15.3 seconds
Started Jun 07 08:41:17 PM PDT 24
Finished Jun 07 08:41:36 PM PDT 24
Peak memory 205736 kb
Host smart-0987f444-8c31-4f2a-97cf-508fb977d850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32940
22572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.3294022572
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.1994460480
Short name T1120
Test name
Test status
Simulation time 10070265940 ps
CPU time 14.13 seconds
Started Jun 07 08:41:22 PM PDT 24
Finished Jun 07 08:41:41 PM PDT 24
Peak memory 205804 kb
Host smart-3f0fb92b-e488-4761-9c36-8239a459df2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19944
60480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.1994460480
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.2628896818
Short name T359
Test name
Test status
Simulation time 10116263644 ps
CPU time 16.43 seconds
Started Jun 07 08:41:18 PM PDT 24
Finished Jun 07 08:41:38 PM PDT 24
Peak memory 205828 kb
Host smart-a69d7ebb-5b95-4f0c-8972-501c6f855aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26288
96818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.2628896818
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.3226608133
Short name T368
Test name
Test status
Simulation time 10672257785 ps
CPU time 13.42 seconds
Started Jun 07 08:41:16 PM PDT 24
Finished Jun 07 08:41:33 PM PDT 24
Peak memory 205772 kb
Host smart-bf4c0e4f-1a06-4feb-bc1b-572459e93eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32266
08133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.3226608133
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3356405831
Short name T619
Test name
Test status
Simulation time 10192669450 ps
CPU time 14.32 seconds
Started Jun 07 08:41:18 PM PDT 24
Finished Jun 07 08:41:36 PM PDT 24
Peak memory 205844 kb
Host smart-c1690ae4-0447-4346-9a24-1f5bed7602cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33564
05831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3356405831
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.2001992898
Short name T71
Test name
Test status
Simulation time 10147719546 ps
CPU time 14.64 seconds
Started Jun 07 08:41:31 PM PDT 24
Finished Jun 07 08:41:48 PM PDT 24
Peak memory 205928 kb
Host smart-a78d1133-5754-4be8-9207-ed67b66c52e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20019
92898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.2001992898
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.1831308897
Short name T660
Test name
Test status
Simulation time 10052041075 ps
CPU time 12.63 seconds
Started Jun 07 08:41:26 PM PDT 24
Finished Jun 07 08:41:42 PM PDT 24
Peak memory 205836 kb
Host smart-4f28d65f-b104-4786-9a21-f8b23887ece0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18313
08897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.1831308897
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1668877619
Short name T545
Test name
Test status
Simulation time 10136884926 ps
CPU time 13.76 seconds
Started Jun 07 08:41:19 PM PDT 24
Finished Jun 07 08:41:37 PM PDT 24
Peak memory 205880 kb
Host smart-731053cc-2025-48cd-8fed-6dd2cd6817e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16688
77619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1668877619
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.4269524547
Short name T631
Test name
Test status
Simulation time 10113601556 ps
CPU time 14.3 seconds
Started Jun 07 08:41:18 PM PDT 24
Finished Jun 07 08:41:36 PM PDT 24
Peak memory 205800 kb
Host smart-cf6e1554-6f92-46d5-891d-21908614a968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42695
24547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.4269524547
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.3898398082
Short name T953
Test name
Test status
Simulation time 13190687885 ps
CPU time 16.04 seconds
Started Jun 07 08:41:18 PM PDT 24
Finished Jun 07 08:41:37 PM PDT 24
Peak memory 205728 kb
Host smart-6d7d54fd-5471-44d6-8c78-3f8382a1911c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38983
98082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.3898398082
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1885584599
Short name T555
Test name
Test status
Simulation time 10088161769 ps
CPU time 12.68 seconds
Started Jun 07 08:41:15 PM PDT 24
Finished Jun 07 08:41:31 PM PDT 24
Peak memory 205704 kb
Host smart-c63f3eb2-346e-41cd-94e0-9af9aada5f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18855
84599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1885584599
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.1262641187
Short name T434
Test name
Test status
Simulation time 24884042696 ps
CPU time 116.59 seconds
Started Jun 07 08:41:23 PM PDT 24
Finished Jun 07 08:43:23 PM PDT 24
Peak memory 205832 kb
Host smart-1b94a7a2-2a43-49d4-ad6c-19e7da061d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12626
41187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.1262641187
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2766911681
Short name T894
Test name
Test status
Simulation time 10053766261 ps
CPU time 13.9 seconds
Started Jun 07 08:41:18 PM PDT 24
Finished Jun 07 08:41:35 PM PDT 24
Peak memory 205884 kb
Host smart-acc3da4a-b569-4d8c-a94a-0026e64b6f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27669
11681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2766911681
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.2727656030
Short name T116
Test name
Test status
Simulation time 10099379655 ps
CPU time 13.29 seconds
Started Jun 07 08:41:27 PM PDT 24
Finished Jun 07 08:41:44 PM PDT 24
Peak memory 205848 kb
Host smart-e8b557d8-ada9-4ee9-8a70-ccd38fb33625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27276
56030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2727656030
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.4115722257
Short name T1216
Test name
Test status
Simulation time 10081067993 ps
CPU time 13.4 seconds
Started Jun 07 08:41:21 PM PDT 24
Finished Jun 07 08:41:39 PM PDT 24
Peak memory 205740 kb
Host smart-0c3e6b2a-9a5e-483c-b3cc-178a5b9390d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41157
22257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.4115722257
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.927489386
Short name T378
Test name
Test status
Simulation time 10102177450 ps
CPU time 14.41 seconds
Started Jun 07 08:41:24 PM PDT 24
Finished Jun 07 08:41:43 PM PDT 24
Peak memory 205792 kb
Host smart-70f1c9b3-20d6-4a42-8acf-0f622d9895ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92748
9386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.927489386
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.115283474
Short name T1023
Test name
Test status
Simulation time 10099799102 ps
CPU time 12.77 seconds
Started Jun 07 08:41:31 PM PDT 24
Finished Jun 07 08:41:46 PM PDT 24
Peak memory 205852 kb
Host smart-2229c6ee-840d-4d2e-a441-c16ad7438abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11528
3474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.115283474
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.2272901782
Short name T143
Test name
Test status
Simulation time 10076168253 ps
CPU time 13.91 seconds
Started Jun 07 08:41:31 PM PDT 24
Finished Jun 07 08:41:47 PM PDT 24
Peak memory 205804 kb
Host smart-f232d0e7-c538-4cd0-a28e-3efcf086d687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22729
01782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.2272901782
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_eop_single_bit_handling.3540827087
Short name T1832
Test name
Test status
Simulation time 10067475031 ps
CPU time 14.22 seconds
Started Jun 07 08:41:22 PM PDT 24
Finished Jun 07 08:41:41 PM PDT 24
Peak memory 205892 kb
Host smart-42fa2ea1-84d1-4e52-9acd-f6c00ed6a275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35408
27087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_eop_single_bit_handling.3540827087
Directory /workspace/3.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2393862168
Short name T441
Test name
Test status
Simulation time 10059188973 ps
CPU time 15.79 seconds
Started Jun 07 08:41:24 PM PDT 24
Finished Jun 07 08:41:44 PM PDT 24
Peak memory 205856 kb
Host smart-70bfb4b8-97dd-4833-b6d9-b72506d7ee57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23938
62168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2393862168
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.644199435
Short name T656
Test name
Test status
Simulation time 10043047895 ps
CPU time 13.3 seconds
Started Jun 07 08:41:31 PM PDT 24
Finished Jun 07 08:41:47 PM PDT 24
Peak memory 205772 kb
Host smart-94fa9b3c-c1d2-40b4-8303-43fb2ea27723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64419
9435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.644199435
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.2070536484
Short name T176
Test name
Test status
Simulation time 26602596836 ps
CPU time 47.36 seconds
Started Jun 07 08:41:25 PM PDT 24
Finished Jun 07 08:42:16 PM PDT 24
Peak memory 205768 kb
Host smart-989aad1d-1879-40e9-911f-ed826a9ce8aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20705
36484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.2070536484
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.3757728772
Short name T1750
Test name
Test status
Simulation time 10119668153 ps
CPU time 13.13 seconds
Started Jun 07 08:41:25 PM PDT 24
Finished Jun 07 08:41:42 PM PDT 24
Peak memory 205880 kb
Host smart-d7312650-1890-4e21-a5a0-97a42cc65231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37577
28772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.3757728772
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1217959118
Short name T727
Test name
Test status
Simulation time 10138697208 ps
CPU time 13.23 seconds
Started Jun 07 08:41:26 PM PDT 24
Finished Jun 07 08:41:42 PM PDT 24
Peak memory 205724 kb
Host smart-c8842290-8168-44b4-83ee-05de2d2c3984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12179
59118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1217959118
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.1300389735
Short name T171
Test name
Test status
Simulation time 24214437065 ps
CPU time 372.19 seconds
Started Jun 07 08:41:22 PM PDT 24
Finished Jun 07 08:47:39 PM PDT 24
Peak memory 205732 kb
Host smart-353982de-984c-419b-97f5-52c93fa2172c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1300389735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.1300389735
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.851354511
Short name T167
Test name
Test status
Simulation time 32505085197 ps
CPU time 165.36 seconds
Started Jun 07 08:41:27 PM PDT 24
Finished Jun 07 08:44:16 PM PDT 24
Peak memory 205904 kb
Host smart-2a0da443-ed4b-46ce-95c1-e3fccaf89e65
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=851354511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.851354511
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.2561282145
Short name T834
Test name
Test status
Simulation time 23678383137 ps
CPU time 90.81 seconds
Started Jun 07 08:41:24 PM PDT 24
Finished Jun 07 08:42:59 PM PDT 24
Peak memory 205868 kb
Host smart-cb51e0f4-b977-43d5-9e8e-4a043aa11fe4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2561282145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2561282145
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.690190210
Short name T382
Test name
Test status
Simulation time 10065887917 ps
CPU time 12.48 seconds
Started Jun 07 08:41:24 PM PDT 24
Finished Jun 07 08:41:40 PM PDT 24
Peak memory 205852 kb
Host smart-5f6214fa-4658-4087-9f72-b1d0725747c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69019
0210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.690190210
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.1317106335
Short name T1557
Test name
Test status
Simulation time 10036392314 ps
CPU time 12.5 seconds
Started Jun 07 08:41:23 PM PDT 24
Finished Jun 07 08:41:40 PM PDT 24
Peak memory 205748 kb
Host smart-c86f8150-9e4f-4eb9-8759-8f69b88abe6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13171
06335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.1317106335
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2508027780
Short name T188
Test name
Test status
Simulation time 629428433 ps
CPU time 1.38 seconds
Started Jun 07 08:41:30 PM PDT 24
Finished Jun 07 08:41:34 PM PDT 24
Peak memory 222960 kb
Host smart-833826eb-343d-4e04-998b-bab9b5abc2c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2508027780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2508027780
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.2434579150
Short name T1282
Test name
Test status
Simulation time 10058725293 ps
CPU time 13.41 seconds
Started Jun 07 08:41:26 PM PDT 24
Finished Jun 07 08:41:43 PM PDT 24
Peak memory 205820 kb
Host smart-7d9090fa-9f62-4ed4-85eb-4d01b065b1ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24345
79150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.2434579150
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.1283214479
Short name T1144
Test name
Test status
Simulation time 10066562743 ps
CPU time 13.64 seconds
Started Jun 07 08:41:22 PM PDT 24
Finished Jun 07 08:41:40 PM PDT 24
Peak memory 205944 kb
Host smart-f9e9cd28-e37b-40d8-9ed8-420510763a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12832
14479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.1283214479
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.310051123
Short name T696
Test name
Test status
Simulation time 10111791128 ps
CPU time 13.07 seconds
Started Jun 07 08:41:13 PM PDT 24
Finished Jun 07 08:41:29 PM PDT 24
Peak memory 205832 kb
Host smart-db11f52c-7982-474b-8f29-7f6c0cd24499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31005
1123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.310051123
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.4038638481
Short name T1327
Test name
Test status
Simulation time 10098514847 ps
CPU time 13.08 seconds
Started Jun 07 08:41:30 PM PDT 24
Finished Jun 07 08:41:46 PM PDT 24
Peak memory 205888 kb
Host smart-9df7d8df-a8f5-4978-b6c8-14a350c92bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40386
38481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.4038638481
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.42467210
Short name T495
Test name
Test status
Simulation time 10069596530 ps
CPU time 12.28 seconds
Started Jun 07 08:41:26 PM PDT 24
Finished Jun 07 08:41:42 PM PDT 24
Peak memory 205776 kb
Host smart-733b0362-8af2-4471-8263-99f57318a3ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42467
210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.42467210
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.2366447476
Short name T1667
Test name
Test status
Simulation time 14094322504 ps
CPU time 125.18 seconds
Started Jun 07 08:41:30 PM PDT 24
Finished Jun 07 08:43:38 PM PDT 24
Peak memory 205800 kb
Host smart-978eec3b-4379-4507-bd68-17b180fbd516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23664
47476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.2366447476
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.1971708223
Short name T1037
Test name
Test status
Simulation time 10139144427 ps
CPU time 13.67 seconds
Started Jun 07 08:46:06 PM PDT 24
Finished Jun 07 08:46:23 PM PDT 24
Peak memory 205840 kb
Host smart-e3a21a8f-8f8a-4309-b918-6119065c23c2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1971708223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.1971708223
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.23902191
Short name T435
Test name
Test status
Simulation time 10062921982 ps
CPU time 13.13 seconds
Started Jun 07 08:46:00 PM PDT 24
Finished Jun 07 08:46:16 PM PDT 24
Peak memory 205772 kb
Host smart-8aa0860e-63df-496d-bfc4-15ff627dfebe
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=23902191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.23902191
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.948894336
Short name T1331
Test name
Test status
Simulation time 10137585802 ps
CPU time 13.24 seconds
Started Jun 07 08:46:02 PM PDT 24
Finished Jun 07 08:46:20 PM PDT 24
Peak memory 205852 kb
Host smart-1ac7d42d-ac33-4dbc-8751-1b582d773d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94889
4336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.948894336
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.724333487
Short name T685
Test name
Test status
Simulation time 14150579163 ps
CPU time 18.47 seconds
Started Jun 07 08:45:54 PM PDT 24
Finished Jun 07 08:46:16 PM PDT 24
Peak memory 205856 kb
Host smart-6a87fde3-2a8a-4d00-8c9a-21898a163263
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=724333487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.724333487
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.3273784305
Short name T944
Test name
Test status
Simulation time 23253028174 ps
CPU time 26.51 seconds
Started Jun 07 08:45:53 PM PDT 24
Finished Jun 07 08:46:23 PM PDT 24
Peak memory 205908 kb
Host smart-2b7757ec-b347-4776-ada5-e43450e89133
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3273784305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.3273784305
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.3798705543
Short name T655
Test name
Test status
Simulation time 10053376253 ps
CPU time 16.42 seconds
Started Jun 07 08:45:55 PM PDT 24
Finished Jun 07 08:46:14 PM PDT 24
Peak memory 205748 kb
Host smart-9684188f-d5ff-4409-8bb8-3423f36faba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37987
05543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.3798705543
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.4125582247
Short name T1548
Test name
Test status
Simulation time 10367477707 ps
CPU time 13.25 seconds
Started Jun 07 08:46:02 PM PDT 24
Finished Jun 07 08:46:19 PM PDT 24
Peak memory 205756 kb
Host smart-30c98781-0a2d-474f-bc62-795f3052c415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41255
82247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.4125582247
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.2843547493
Short name T17
Test name
Test status
Simulation time 10077241536 ps
CPU time 13.73 seconds
Started Jun 07 08:46:03 PM PDT 24
Finished Jun 07 08:46:21 PM PDT 24
Peak memory 205880 kb
Host smart-afeb3f43-2e69-4d60-9a8a-cbd1c6384c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28435
47493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.2843547493
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.3394102461
Short name T1429
Test name
Test status
Simulation time 10041660151 ps
CPU time 14.29 seconds
Started Jun 07 08:46:08 PM PDT 24
Finished Jun 07 08:46:25 PM PDT 24
Peak memory 205828 kb
Host smart-f1bf9c50-a24c-42fb-9af4-ece0851bbf67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33941
02461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.3394102461
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.4231736740
Short name T1148
Test name
Test status
Simulation time 10777579069 ps
CPU time 15.9 seconds
Started Jun 07 08:46:04 PM PDT 24
Finished Jun 07 08:46:25 PM PDT 24
Peak memory 205836 kb
Host smart-325dc2dc-55e4-4cea-857b-8c373828922b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42317
36740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.4231736740
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.1061840222
Short name T433
Test name
Test status
Simulation time 10177071239 ps
CPU time 14.41 seconds
Started Jun 07 08:46:02 PM PDT 24
Finished Jun 07 08:46:21 PM PDT 24
Peak memory 205844 kb
Host smart-19bb10b8-3248-4273-b672-7c9b27f06714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10618
40222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.1061840222
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.3396509519
Short name T1213
Test name
Test status
Simulation time 10103868864 ps
CPU time 13.51 seconds
Started Jun 07 08:46:06 PM PDT 24
Finished Jun 07 08:46:23 PM PDT 24
Peak memory 205820 kb
Host smart-984c1dc2-84e1-4a7d-91f0-269997d8d8f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33965
09519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.3396509519
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.2162956028
Short name T1994
Test name
Test status
Simulation time 10075364501 ps
CPU time 13.07 seconds
Started Jun 07 08:46:02 PM PDT 24
Finished Jun 07 08:46:20 PM PDT 24
Peak memory 205840 kb
Host smart-988b0528-b734-4b35-aea9-5398a1223843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21629
56028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.2162956028
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.2123929036
Short name T847
Test name
Test status
Simulation time 10098861839 ps
CPU time 15.13 seconds
Started Jun 07 08:46:02 PM PDT 24
Finished Jun 07 08:46:21 PM PDT 24
Peak memory 205816 kb
Host smart-72b8954b-5151-4dc9-bd5c-d2b74b1b6677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21239
29036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.2123929036
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.3389222610
Short name T464
Test name
Test status
Simulation time 10120601879 ps
CPU time 14.64 seconds
Started Jun 07 08:46:01 PM PDT 24
Finished Jun 07 08:46:20 PM PDT 24
Peak memory 205704 kb
Host smart-c632f662-699e-4a55-b3d4-1e331c8a1cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33892
22610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.3389222610
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.1017229205
Short name T330
Test name
Test status
Simulation time 13174049918 ps
CPU time 15.37 seconds
Started Jun 07 08:46:03 PM PDT 24
Finished Jun 07 08:46:22 PM PDT 24
Peak memory 205868 kb
Host smart-863cb0a5-2b96-41d4-809e-90b3015df5e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10172
29205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.1017229205
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1710971682
Short name T403
Test name
Test status
Simulation time 10121483853 ps
CPU time 14.96 seconds
Started Jun 07 08:46:00 PM PDT 24
Finished Jun 07 08:46:19 PM PDT 24
Peak memory 205832 kb
Host smart-6fbef7b3-5575-4455-8bb4-c6ce9f70512a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17109
71682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1710971682
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.2124442437
Short name T1766
Test name
Test status
Simulation time 22621938297 ps
CPU time 361.86 seconds
Started Jun 07 08:46:02 PM PDT 24
Finished Jun 07 08:52:09 PM PDT 24
Peak memory 205744 kb
Host smart-bcca8d1e-4e13-41d8-a7c8-f438d000d926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21244
42437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.2124442437
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.3988284983
Short name T742
Test name
Test status
Simulation time 10052173269 ps
CPU time 15.39 seconds
Started Jun 07 08:46:02 PM PDT 24
Finished Jun 07 08:46:21 PM PDT 24
Peak memory 205752 kb
Host smart-3f26a72b-62b3-4ff7-a94e-20d16a2dfb4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39882
84983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.3988284983
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3769358719
Short name T1830
Test name
Test status
Simulation time 10134924323 ps
CPU time 12.9 seconds
Started Jun 07 08:46:00 PM PDT 24
Finished Jun 07 08:46:16 PM PDT 24
Peak memory 205772 kb
Host smart-96c0e9b7-5cc8-4a88-843a-821c7cd994b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37693
58719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3769358719
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3327039476
Short name T544
Test name
Test status
Simulation time 10060078493 ps
CPU time 13.78 seconds
Started Jun 07 08:46:02 PM PDT 24
Finished Jun 07 08:46:21 PM PDT 24
Peak memory 205824 kb
Host smart-031adb50-b42d-4427-bd0b-fb3dc059bcaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33270
39476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3327039476
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.2093055033
Short name T791
Test name
Test status
Simulation time 10095684489 ps
CPU time 12.8 seconds
Started Jun 07 08:46:01 PM PDT 24
Finished Jun 07 08:46:18 PM PDT 24
Peak memory 205852 kb
Host smart-c94d1127-43d5-4a89-a6c4-179251cbfb9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20930
55033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2093055033
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1135762584
Short name T340
Test name
Test status
Simulation time 10077310104 ps
CPU time 14.17 seconds
Started Jun 07 08:46:03 PM PDT 24
Finished Jun 07 08:46:21 PM PDT 24
Peak memory 205856 kb
Host smart-3e4c1d5b-c104-4fc8-af87-ac674ac2d7bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11357
62584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1135762584
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.1130515383
Short name T129
Test name
Test status
Simulation time 10059233103 ps
CPU time 13.69 seconds
Started Jun 07 08:46:01 PM PDT 24
Finished Jun 07 08:46:19 PM PDT 24
Peak memory 205852 kb
Host smart-c2a77739-b848-46c2-89ea-a06a78480b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11305
15383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.1130515383
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_eop_single_bit_handling.3859372313
Short name T584
Test name
Test status
Simulation time 10152550035 ps
CPU time 15.02 seconds
Started Jun 07 08:45:59 PM PDT 24
Finished Jun 07 08:46:16 PM PDT 24
Peak memory 205888 kb
Host smart-fe781499-02ae-4767-b9e1-642b6ab5f261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38593
72313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_eop_single_bit_handling.3859372313
Directory /workspace/30.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.2514432155
Short name T473
Test name
Test status
Simulation time 10034061889 ps
CPU time 14.76 seconds
Started Jun 07 08:46:04 PM PDT 24
Finished Jun 07 08:46:23 PM PDT 24
Peak memory 205764 kb
Host smart-898c1546-f45b-4e56-a04c-ed55af70c07f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25144
32155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.2514432155
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2600193441
Short name T40
Test name
Test status
Simulation time 10035517865 ps
CPU time 15.04 seconds
Started Jun 07 08:46:01 PM PDT 24
Finished Jun 07 08:46:21 PM PDT 24
Peak memory 205836 kb
Host smart-ca134352-f70f-4e2f-a94e-b65332a21b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26001
93441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2600193441
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.1542714081
Short name T1617
Test name
Test status
Simulation time 26582288327 ps
CPU time 50.46 seconds
Started Jun 07 08:46:02 PM PDT 24
Finished Jun 07 08:46:57 PM PDT 24
Peak memory 205896 kb
Host smart-15d2a907-ca11-4dcf-a1dc-f22fb0f3f19d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15427
14081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.1542714081
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1779109362
Short name T1953
Test name
Test status
Simulation time 10121732232 ps
CPU time 13.73 seconds
Started Jun 07 08:46:02 PM PDT 24
Finished Jun 07 08:46:20 PM PDT 24
Peak memory 205780 kb
Host smart-cc5f946f-c8a1-4e90-8a3f-912fa56944c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17791
09362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1779109362
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.3046375050
Short name T1361
Test name
Test status
Simulation time 10125348448 ps
CPU time 13.49 seconds
Started Jun 07 08:46:00 PM PDT 24
Finished Jun 07 08:46:17 PM PDT 24
Peak memory 205828 kb
Host smart-584fa9a1-bf95-4e00-8664-bce86e52f207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30463
75050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.3046375050
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.2835660058
Short name T1903
Test name
Test status
Simulation time 10136913360 ps
CPU time 14.09 seconds
Started Jun 07 08:46:00 PM PDT 24
Finished Jun 07 08:46:18 PM PDT 24
Peak memory 205880 kb
Host smart-4c12b76e-24e4-4013-88c9-2e973cfa437a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28356
60058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.2835660058
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.3594509906
Short name T958
Test name
Test status
Simulation time 10050626678 ps
CPU time 13.98 seconds
Started Jun 07 08:46:03 PM PDT 24
Finished Jun 07 08:46:22 PM PDT 24
Peak memory 205712 kb
Host smart-0877eb2c-99e7-4a15-b7c4-61c13c3767d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35945
09906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.3594509906
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.797414026
Short name T1508
Test name
Test status
Simulation time 10056839753 ps
CPU time 15.82 seconds
Started Jun 07 08:46:01 PM PDT 24
Finished Jun 07 08:46:21 PM PDT 24
Peak memory 205744 kb
Host smart-deda8ec9-f516-47a4-af0b-d9f9651ca6d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79741
4026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.797414026
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1466795126
Short name T76
Test name
Test status
Simulation time 10079191943 ps
CPU time 13.63 seconds
Started Jun 07 08:46:02 PM PDT 24
Finished Jun 07 08:46:19 PM PDT 24
Peak memory 205876 kb
Host smart-2615bbd6-a3a8-4631-8eac-7d88a3b89574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14667
95126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1466795126
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3467650719
Short name T1829
Test name
Test status
Simulation time 10117937515 ps
CPU time 13.98 seconds
Started Jun 07 08:45:58 PM PDT 24
Finished Jun 07 08:46:15 PM PDT 24
Peak memory 205904 kb
Host smart-bb176d7d-9963-4867-90db-0b4390e9eece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34676
50719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3467650719
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.1180332397
Short name T554
Test name
Test status
Simulation time 10049519179 ps
CPU time 12.88 seconds
Started Jun 07 08:46:00 PM PDT 24
Finished Jun 07 08:46:16 PM PDT 24
Peak memory 205820 kb
Host smart-3955623d-00a1-41e7-bd04-cda426c46127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11803
32397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.1180332397
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.1644517921
Short name T213
Test name
Test status
Simulation time 10094791244 ps
CPU time 15.86 seconds
Started Jun 07 08:46:03 PM PDT 24
Finished Jun 07 08:46:23 PM PDT 24
Peak memory 205744 kb
Host smart-85916956-8938-4d05-ac17-a4d69c63bbda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16445
17921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.1644517921
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.281840969
Short name T1404
Test name
Test status
Simulation time 18863221592 ps
CPU time 95.06 seconds
Started Jun 07 08:46:08 PM PDT 24
Finished Jun 07 08:47:46 PM PDT 24
Peak memory 205844 kb
Host smart-d81ebfca-3201-4c6c-86f5-eefe5dabe8e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28184
0969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.281840969
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.1864967915
Short name T365
Test name
Test status
Simulation time 10166304915 ps
CPU time 13.61 seconds
Started Jun 07 08:46:17 PM PDT 24
Finished Jun 07 08:46:32 PM PDT 24
Peak memory 205840 kb
Host smart-5f5edf31-6f4c-46ca-99b2-7aee1f07fdda
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1864967915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.1864967915
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.2199662367
Short name T606
Test name
Test status
Simulation time 10068622428 ps
CPU time 14.22 seconds
Started Jun 07 08:46:15 PM PDT 24
Finished Jun 07 08:46:30 PM PDT 24
Peak memory 205736 kb
Host smart-75abbe1c-3c6d-4165-99e4-8c66f3f17fb2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2199662367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.2199662367
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.1508814481
Short name T2012
Test name
Test status
Simulation time 10104856433 ps
CPU time 13.34 seconds
Started Jun 07 08:46:17 PM PDT 24
Finished Jun 07 08:46:32 PM PDT 24
Peak memory 205684 kb
Host smart-f4daf5ee-d6da-4991-b65f-2fa71f53b82c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15088
14481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.1508814481
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.3244751014
Short name T890
Test name
Test status
Simulation time 13561375403 ps
CPU time 18.18 seconds
Started Jun 07 08:46:08 PM PDT 24
Finished Jun 07 08:46:30 PM PDT 24
Peak memory 205828 kb
Host smart-3accde7d-3958-4127-adc6-458fd08099d5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3244751014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.3244751014
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.585668216
Short name T1793
Test name
Test status
Simulation time 23198401896 ps
CPU time 27.67 seconds
Started Jun 07 08:46:07 PM PDT 24
Finished Jun 07 08:46:38 PM PDT 24
Peak memory 205868 kb
Host smart-c6aa8cfd-0634-46e5-84bb-43fba5d36240
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=585668216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.585668216
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1560942521
Short name T1792
Test name
Test status
Simulation time 10059617674 ps
CPU time 12.84 seconds
Started Jun 07 08:46:07 PM PDT 24
Finished Jun 07 08:46:23 PM PDT 24
Peak memory 205792 kb
Host smart-16961d47-81ec-4b40-9a56-4c90ea74d986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15609
42521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1560942521
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.2010011616
Short name T203
Test name
Test status
Simulation time 10069307476 ps
CPU time 12.96 seconds
Started Jun 07 08:46:12 PM PDT 24
Finished Jun 07 08:46:27 PM PDT 24
Peak memory 205848 kb
Host smart-5813bb58-3fcf-48a2-8a21-f03657a51da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20100
11616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.2010011616
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.2488051271
Short name T1706
Test name
Test status
Simulation time 10128845987 ps
CPU time 12.8 seconds
Started Jun 07 08:46:05 PM PDT 24
Finished Jun 07 08:46:22 PM PDT 24
Peak memory 205732 kb
Host smart-40e69def-f962-442b-8560-6ee54a093983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24880
51271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.2488051271
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.3379521936
Short name T691
Test name
Test status
Simulation time 10045916478 ps
CPU time 12.66 seconds
Started Jun 07 08:46:11 PM PDT 24
Finished Jun 07 08:46:26 PM PDT 24
Peak memory 205768 kb
Host smart-f26a4674-5a5e-43f2-81db-1ef7c2de5495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33795
21936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.3379521936
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.3980814419
Short name T271
Test name
Test status
Simulation time 10049148173 ps
CPU time 15.54 seconds
Started Jun 07 08:46:09 PM PDT 24
Finished Jun 07 08:46:27 PM PDT 24
Peak memory 205704 kb
Host smart-5529d15f-292f-41f3-a8dd-fb0a287a9a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39808
14419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.3980814419
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.2038947189
Short name T1878
Test name
Test status
Simulation time 10824239930 ps
CPU time 16.43 seconds
Started Jun 07 08:46:11 PM PDT 24
Finished Jun 07 08:46:30 PM PDT 24
Peak memory 205848 kb
Host smart-63a0c59f-88f8-474b-a22a-c4b8d948f8d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20389
47189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.2038947189
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.169752673
Short name T1215
Test name
Test status
Simulation time 10069826866 ps
CPU time 13.46 seconds
Started Jun 07 08:46:12 PM PDT 24
Finished Jun 07 08:46:27 PM PDT 24
Peak memory 205752 kb
Host smart-eb3ad459-90cf-414e-ba49-fabed743b512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16975
2673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.169752673
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.2910649840
Short name T964
Test name
Test status
Simulation time 10178891962 ps
CPU time 14.1 seconds
Started Jun 07 08:46:17 PM PDT 24
Finished Jun 07 08:46:33 PM PDT 24
Peak memory 205828 kb
Host smart-7cd5d81e-67c7-4564-a412-27b90b0bee64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29106
49840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.2910649840
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.617553766
Short name T579
Test name
Test status
Simulation time 10058021238 ps
CPU time 14.83 seconds
Started Jun 07 08:46:17 PM PDT 24
Finished Jun 07 08:46:35 PM PDT 24
Peak memory 205808 kb
Host smart-c4f9ba53-efec-43db-84d8-e4daa40ee24b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61755
3766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.617553766
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.2222469650
Short name T322
Test name
Test status
Simulation time 10061467125 ps
CPU time 13.05 seconds
Started Jun 07 08:46:08 PM PDT 24
Finished Jun 07 08:46:24 PM PDT 24
Peak memory 205884 kb
Host smart-7b98258b-23b0-4873-bafd-4c59c76980b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22224
69650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2222469650
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.3154996585
Short name T948
Test name
Test status
Simulation time 10106647913 ps
CPU time 14.45 seconds
Started Jun 07 08:46:09 PM PDT 24
Finished Jun 07 08:46:26 PM PDT 24
Peak memory 205764 kb
Host smart-d0d00174-657b-4af8-a86a-d7c4a6dff4f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31549
96585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.3154996585
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.3756738419
Short name T33
Test name
Test status
Simulation time 13235789566 ps
CPU time 19.64 seconds
Started Jun 07 08:46:10 PM PDT 24
Finished Jun 07 08:46:32 PM PDT 24
Peak memory 205776 kb
Host smart-6e853794-70ed-42e3-9425-aefa1baea73a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37567
38419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.3756738419
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.433314578
Short name T638
Test name
Test status
Simulation time 10103749344 ps
CPU time 15.96 seconds
Started Jun 07 08:46:12 PM PDT 24
Finished Jun 07 08:46:30 PM PDT 24
Peak memory 205772 kb
Host smart-d657f4ec-878f-43f8-9226-35aa37666419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43331
4578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.433314578
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.1929151928
Short name T1273
Test name
Test status
Simulation time 22778883439 ps
CPU time 393.46 seconds
Started Jun 07 08:46:07 PM PDT 24
Finished Jun 07 08:52:44 PM PDT 24
Peak memory 205800 kb
Host smart-ac8b422c-7e94-42f6-ac42-02df8b075e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19291
51928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.1929151928
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1508463491
Short name T990
Test name
Test status
Simulation time 10057511096 ps
CPU time 13.21 seconds
Started Jun 07 08:46:10 PM PDT 24
Finished Jun 07 08:46:25 PM PDT 24
Peak memory 205804 kb
Host smart-27d45d84-e8bb-4707-b36a-7ee7cebfe6e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15084
63491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1508463491
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.497069383
Short name T777
Test name
Test status
Simulation time 10081656025 ps
CPU time 14.41 seconds
Started Jun 07 08:46:06 PM PDT 24
Finished Jun 07 08:46:24 PM PDT 24
Peak memory 205872 kb
Host smart-e65372de-2f05-4003-9d37-ff51b5b40caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49706
9383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.497069383
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.2547414924
Short name T1419
Test name
Test status
Simulation time 10065695160 ps
CPU time 12.68 seconds
Started Jun 07 08:46:07 PM PDT 24
Finished Jun 07 08:46:23 PM PDT 24
Peak memory 205792 kb
Host smart-985aa8e7-ca40-44c7-bb1b-ec5e3f93d0d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25474
14924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.2547414924
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.2012979050
Short name T1850
Test name
Test status
Simulation time 10089943886 ps
CPU time 12.93 seconds
Started Jun 07 08:46:09 PM PDT 24
Finished Jun 07 08:46:25 PM PDT 24
Peak memory 205708 kb
Host smart-3cf7d7f9-b0b1-4fc1-a24d-48b66aea0123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20129
79050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.2012979050
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3330780471
Short name T1761
Test name
Test status
Simulation time 10055981354 ps
CPU time 13.93 seconds
Started Jun 07 08:46:16 PM PDT 24
Finished Jun 07 08:46:32 PM PDT 24
Peak memory 205860 kb
Host smart-7cac5b65-ece8-4184-8209-418f255734a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33307
80471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3330780471
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_eop_single_bit_handling.197739878
Short name T1352
Test name
Test status
Simulation time 10071128140 ps
CPU time 13.74 seconds
Started Jun 07 08:46:08 PM PDT 24
Finished Jun 07 08:46:25 PM PDT 24
Peak memory 205752 kb
Host smart-36e4e8ee-536b-46c3-a65a-1a5266835d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19773
9878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_eop_single_bit_handling.197739878
Directory /workspace/31.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.49846391
Short name T1605
Test name
Test status
Simulation time 10049353959 ps
CPU time 14.34 seconds
Started Jun 07 08:46:16 PM PDT 24
Finished Jun 07 08:46:32 PM PDT 24
Peak memory 205848 kb
Host smart-a5d276b0-cd64-441d-81ec-1e9743144a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49846
391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.49846391
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.293244254
Short name T1127
Test name
Test status
Simulation time 10055707954 ps
CPU time 13.13 seconds
Started Jun 07 08:46:17 PM PDT 24
Finished Jun 07 08:46:33 PM PDT 24
Peak memory 205768 kb
Host smart-c2dcaf35-62a9-43ed-93f6-91dd5591c202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29324
4254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.293244254
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.2873383133
Short name T1360
Test name
Test status
Simulation time 25029169892 ps
CPU time 46.67 seconds
Started Jun 07 08:46:08 PM PDT 24
Finished Jun 07 08:46:57 PM PDT 24
Peak memory 205728 kb
Host smart-23432e23-5478-464e-86ce-93d97aff695e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28733
83133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.2873383133
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2030527767
Short name T470
Test name
Test status
Simulation time 10077650512 ps
CPU time 14.62 seconds
Started Jun 07 08:46:07 PM PDT 24
Finished Jun 07 08:46:25 PM PDT 24
Peak memory 205948 kb
Host smart-9b58b281-5eee-43ee-8e9a-719d8dfc6d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20305
27767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2030527767
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.384584566
Short name T1553
Test name
Test status
Simulation time 10125300694 ps
CPU time 13.91 seconds
Started Jun 07 08:46:23 PM PDT 24
Finished Jun 07 08:46:42 PM PDT 24
Peak memory 205868 kb
Host smart-aa91bf63-ccde-4b29-b5cd-e46516d108d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38458
4566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.384584566
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.2196017311
Short name T1758
Test name
Test status
Simulation time 10062944063 ps
CPU time 14.26 seconds
Started Jun 07 08:46:07 PM PDT 24
Finished Jun 07 08:46:24 PM PDT 24
Peak memory 205788 kb
Host smart-e8aec7f7-2784-401e-9bed-b822950fdd6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21960
17311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.2196017311
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.1957567009
Short name T1880
Test name
Test status
Simulation time 10035768145 ps
CPU time 14.56 seconds
Started Jun 07 08:46:07 PM PDT 24
Finished Jun 07 08:46:25 PM PDT 24
Peak memory 205728 kb
Host smart-0c0ba31f-e406-4e94-a2cf-b96b78c9e3bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19575
67009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.1957567009
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.1003173806
Short name T68
Test name
Test status
Simulation time 10060861402 ps
CPU time 14.59 seconds
Started Jun 07 08:46:17 PM PDT 24
Finished Jun 07 08:46:34 PM PDT 24
Peak memory 205908 kb
Host smart-8d8fd5de-ba8a-49c2-a927-666b01994e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10031
73806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.1003173806
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3814443169
Short name T1009
Test name
Test status
Simulation time 10073099443 ps
CPU time 14.25 seconds
Started Jun 07 08:46:12 PM PDT 24
Finished Jun 07 08:46:29 PM PDT 24
Peak memory 205804 kb
Host smart-37a7a945-2a77-454b-91f9-cb85804f0cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38144
43169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3814443169
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.1226153453
Short name T863
Test name
Test status
Simulation time 10094587001 ps
CPU time 15.2 seconds
Started Jun 07 08:46:01 PM PDT 24
Finished Jun 07 08:46:20 PM PDT 24
Peak memory 205804 kb
Host smart-b1e9eeca-414b-4b1b-807c-8431d3ac4af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12261
53453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.1226153453
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.401523239
Short name T1778
Test name
Test status
Simulation time 10087783172 ps
CPU time 12.62 seconds
Started Jun 07 08:46:06 PM PDT 24
Finished Jun 07 08:46:22 PM PDT 24
Peak memory 205808 kb
Host smart-1183d701-ec40-497f-a0b9-e2a54c7ccaf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40152
3239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.401523239
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1681477047
Short name T1915
Test name
Test status
Simulation time 10075123417 ps
CPU time 13.4 seconds
Started Jun 07 08:46:11 PM PDT 24
Finished Jun 07 08:46:26 PM PDT 24
Peak memory 205744 kb
Host smart-ea9ae365-450b-485b-b981-9eea71898ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16814
77047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1681477047
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.2454894756
Short name T1412
Test name
Test status
Simulation time 21422466166 ps
CPU time 337.05 seconds
Started Jun 07 08:46:06 PM PDT 24
Finished Jun 07 08:51:47 PM PDT 24
Peak memory 205824 kb
Host smart-95458ec3-1449-414b-8957-01dc48732ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24548
94756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.2454894756
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.1313752205
Short name T819
Test name
Test status
Simulation time 10210751964 ps
CPU time 13.07 seconds
Started Jun 07 08:46:29 PM PDT 24
Finished Jun 07 08:46:49 PM PDT 24
Peak memory 205792 kb
Host smart-e20833af-4877-442f-975c-4595923c84d3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1313752205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.1313752205
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.1166220407
Short name T294
Test name
Test status
Simulation time 10057398933 ps
CPU time 13.49 seconds
Started Jun 07 08:46:28 PM PDT 24
Finished Jun 07 08:46:48 PM PDT 24
Peak memory 205896 kb
Host smart-2e90b1ed-57cc-4c25-a0ef-bb4cc503f6a0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1166220407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.1166220407
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.4084422572
Short name T1492
Test name
Test status
Simulation time 10138657105 ps
CPU time 15.79 seconds
Started Jun 07 08:46:28 PM PDT 24
Finished Jun 07 08:46:50 PM PDT 24
Peak memory 205928 kb
Host smart-05162695-ce26-47c3-aa79-c1ca70e564ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40844
22572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.4084422572
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.3445746133
Short name T1043
Test name
Test status
Simulation time 14291591732 ps
CPU time 21.03 seconds
Started Jun 07 08:46:18 PM PDT 24
Finished Jun 07 08:46:42 PM PDT 24
Peak memory 205852 kb
Host smart-2fed5553-2c3e-4533-95a4-79f112a4c442
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3445746133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.3445746133
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3408450388
Short name T1857
Test name
Test status
Simulation time 23231272556 ps
CPU time 24 seconds
Started Jun 07 08:46:21 PM PDT 24
Finished Jun 07 08:46:47 PM PDT 24
Peak memory 205900 kb
Host smart-4e4a7902-0c1a-4618-b109-a833233d1c21
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3408450388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3408450388
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2172855534
Short name T1475
Test name
Test status
Simulation time 10073858069 ps
CPU time 13.3 seconds
Started Jun 07 08:46:18 PM PDT 24
Finished Jun 07 08:46:34 PM PDT 24
Peak memory 205712 kb
Host smart-f8a9d253-d2a5-40a4-b61f-254623324c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21728
55534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2172855534
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1575619624
Short name T1217
Test name
Test status
Simulation time 10426095414 ps
CPU time 14.59 seconds
Started Jun 07 08:46:18 PM PDT 24
Finished Jun 07 08:46:36 PM PDT 24
Peak memory 205840 kb
Host smart-3531ee75-b0bc-44c3-a29e-10335c799d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15756
19624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1575619624
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.1634477725
Short name T1719
Test name
Test status
Simulation time 10036127992 ps
CPU time 12.99 seconds
Started Jun 07 08:46:23 PM PDT 24
Finished Jun 07 08:46:40 PM PDT 24
Peak memory 205856 kb
Host smart-7edb1c51-e9c9-4f7b-b414-4f69c6f36459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16344
77725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.1634477725
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2169026839
Short name T1175
Test name
Test status
Simulation time 10087055279 ps
CPU time 15.38 seconds
Started Jun 07 08:46:22 PM PDT 24
Finished Jun 07 08:46:42 PM PDT 24
Peak memory 205732 kb
Host smart-71e72e81-4a12-4ab6-ba53-332d970c1e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21690
26839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2169026839
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.2980696703
Short name T740
Test name
Test status
Simulation time 10722265476 ps
CPU time 15.16 seconds
Started Jun 07 08:46:18 PM PDT 24
Finished Jun 07 08:46:36 PM PDT 24
Peak memory 205800 kb
Host smart-a59c0d1b-f1a3-4b3a-b316-846aa59605a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29806
96703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.2980696703
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.4201126454
Short name T36
Test name
Test status
Simulation time 10106480829 ps
CPU time 16.55 seconds
Started Jun 07 08:46:18 PM PDT 24
Finished Jun 07 08:46:37 PM PDT 24
Peak memory 205820 kb
Host smart-c5752d88-cd24-4de0-8b3b-f7b954638f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42011
26454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.4201126454
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.2454072985
Short name T504
Test name
Test status
Simulation time 10129023056 ps
CPU time 16.13 seconds
Started Jun 07 08:46:28 PM PDT 24
Finished Jun 07 08:46:52 PM PDT 24
Peak memory 205736 kb
Host smart-42c261bd-3889-4802-b672-ff98a742a877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24540
72985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.2454072985
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.2539635159
Short name T1912
Test name
Test status
Simulation time 10058239980 ps
CPU time 13.31 seconds
Started Jun 07 08:46:24 PM PDT 24
Finished Jun 07 08:46:43 PM PDT 24
Peak memory 205740 kb
Host smart-439b866a-4d96-4309-b88e-69cb3a84b371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25396
35159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.2539635159
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.3229678560
Short name T1164
Test name
Test status
Simulation time 10153478503 ps
CPU time 13.21 seconds
Started Jun 07 08:46:17 PM PDT 24
Finished Jun 07 08:46:33 PM PDT 24
Peak memory 205860 kb
Host smart-5ad0bf81-dee3-44d0-9853-f96cfc4d5619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32296
78560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.3229678560
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.2283505867
Short name T1428
Test name
Test status
Simulation time 10078374128 ps
CPU time 15.68 seconds
Started Jun 07 08:46:23 PM PDT 24
Finished Jun 07 08:46:42 PM PDT 24
Peak memory 205732 kb
Host smart-bb5a0ed0-234f-447c-8638-d1488b2dfc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22835
05867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.2283505867
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.3634890284
Short name T1624
Test name
Test status
Simulation time 13249511112 ps
CPU time 18.96 seconds
Started Jun 07 08:46:16 PM PDT 24
Finished Jun 07 08:46:37 PM PDT 24
Peak memory 205860 kb
Host smart-abd4138f-ef61-4b0e-8e5a-03e0f17f55bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36348
90284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.3634890284
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.2467348495
Short name T1718
Test name
Test status
Simulation time 10085793255 ps
CPU time 12.83 seconds
Started Jun 07 08:46:16 PM PDT 24
Finished Jun 07 08:46:30 PM PDT 24
Peak memory 205812 kb
Host smart-f4855a05-fe72-476e-94d8-a97142b630dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24673
48495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2467348495
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.3672313135
Short name T5
Test name
Test status
Simulation time 21940572149 ps
CPU time 126.73 seconds
Started Jun 07 08:46:15 PM PDT 24
Finished Jun 07 08:48:23 PM PDT 24
Peak memory 205860 kb
Host smart-ee122329-dbcb-47a8-a8f0-901ed572cf90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36723
13135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.3672313135
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.2641938849
Short name T1247
Test name
Test status
Simulation time 10054061817 ps
CPU time 12.93 seconds
Started Jun 07 08:46:18 PM PDT 24
Finished Jun 07 08:46:34 PM PDT 24
Peak memory 205852 kb
Host smart-106de491-f2e5-445e-be13-2a36a517fa41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26419
38849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.2641938849
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.2252971726
Short name T1418
Test name
Test status
Simulation time 10086993174 ps
CPU time 15.38 seconds
Started Jun 07 08:46:18 PM PDT 24
Finished Jun 07 08:46:36 PM PDT 24
Peak memory 205856 kb
Host smart-5963fa8a-2341-4b4b-9af5-008c4dc871d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22529
71726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.2252971726
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1536882619
Short name T1710
Test name
Test status
Simulation time 10056357084 ps
CPU time 12.89 seconds
Started Jun 07 08:46:17 PM PDT 24
Finished Jun 07 08:46:32 PM PDT 24
Peak memory 205808 kb
Host smart-45a7f85a-a068-48a3-ba97-0c41199b66ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15368
82619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1536882619
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.2952676890
Short name T1597
Test name
Test status
Simulation time 10060024958 ps
CPU time 12.53 seconds
Started Jun 07 08:46:19 PM PDT 24
Finished Jun 07 08:46:34 PM PDT 24
Peak memory 205828 kb
Host smart-2b7261d7-0e60-4871-828b-6f37a8d51cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29526
76890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.2952676890
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.351344789
Short name T134
Test name
Test status
Simulation time 10051178953 ps
CPU time 12.88 seconds
Started Jun 07 08:46:28 PM PDT 24
Finished Jun 07 08:46:48 PM PDT 24
Peak memory 205756 kb
Host smart-ab7bc78c-811d-4166-9ee0-c4a71ac94d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35134
4789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.351344789
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_eop_single_bit_handling.581513466
Short name T1381
Test name
Test status
Simulation time 10076119304 ps
CPU time 14.25 seconds
Started Jun 07 08:46:26 PM PDT 24
Finished Jun 07 08:46:48 PM PDT 24
Peak memory 205812 kb
Host smart-1ea738d8-d99f-45e9-9c90-9fec2326e74f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58151
3466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_eop_single_bit_handling.581513466
Directory /workspace/32.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3446054055
Short name T459
Test name
Test status
Simulation time 10048832230 ps
CPU time 14.14 seconds
Started Jun 07 08:46:25 PM PDT 24
Finished Jun 07 08:46:45 PM PDT 24
Peak memory 205772 kb
Host smart-a0243ae1-5129-4a49-b6dd-5ff36d414b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34460
54055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.3446054055
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.3219382287
Short name T1979
Test name
Test status
Simulation time 10047347416 ps
CPU time 12.9 seconds
Started Jun 07 08:46:40 PM PDT 24
Finished Jun 07 08:46:57 PM PDT 24
Peak memory 205840 kb
Host smart-6fef056c-dc15-41a6-a23d-2c5159c1ac23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32193
82287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.3219382287
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.736862287
Short name T899
Test name
Test status
Simulation time 23626584189 ps
CPU time 40.89 seconds
Started Jun 07 08:46:18 PM PDT 24
Finished Jun 07 08:47:01 PM PDT 24
Peak memory 205752 kb
Host smart-d649b14d-38d7-457c-af72-566ddf5936ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73686
2287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.736862287
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.492235030
Short name T1072
Test name
Test status
Simulation time 10101622932 ps
CPU time 13.09 seconds
Started Jun 07 08:46:19 PM PDT 24
Finished Jun 07 08:46:35 PM PDT 24
Peak memory 205900 kb
Host smart-822e20df-a19a-45e8-96b7-dfc41d10b035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49223
5030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.492235030
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3957170220
Short name T1188
Test name
Test status
Simulation time 10145478256 ps
CPU time 14.45 seconds
Started Jun 07 08:46:22 PM PDT 24
Finished Jun 07 08:46:40 PM PDT 24
Peak memory 205832 kb
Host smart-1505baf2-8daa-4984-bc01-309ef3415920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39571
70220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3957170220
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.2488867375
Short name T648
Test name
Test status
Simulation time 10083618968 ps
CPU time 16.81 seconds
Started Jun 07 08:46:22 PM PDT 24
Finished Jun 07 08:46:43 PM PDT 24
Peak memory 205760 kb
Host smart-53134ae4-7bfc-4803-880d-d505803e6f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24888
67375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.2488867375
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.560697731
Short name T348
Test name
Test status
Simulation time 10039988235 ps
CPU time 15.3 seconds
Started Jun 07 08:46:26 PM PDT 24
Finished Jun 07 08:46:47 PM PDT 24
Peak memory 205828 kb
Host smart-b19f5544-f643-4fe7-a0b5-a09ba7b0f675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56069
7731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.560697731
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.1123599712
Short name T1516
Test name
Test status
Simulation time 10078133536 ps
CPU time 16.03 seconds
Started Jun 07 08:46:28 PM PDT 24
Finished Jun 07 08:46:52 PM PDT 24
Peak memory 205736 kb
Host smart-38c2ccd9-6136-4400-b7bb-368fcc7e3705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11235
99712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.1123599712
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.3002462668
Short name T1633
Test name
Test status
Simulation time 10061278949 ps
CPU time 13.12 seconds
Started Jun 07 08:46:27 PM PDT 24
Finished Jun 07 08:46:47 PM PDT 24
Peak memory 205752 kb
Host smart-de9f4fd5-6afc-4520-9114-4abfcb16f6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30024
62668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.3002462668
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2165651103
Short name T560
Test name
Test status
Simulation time 10159000818 ps
CPU time 14.84 seconds
Started Jun 07 08:46:17 PM PDT 24
Finished Jun 07 08:46:33 PM PDT 24
Peak memory 205876 kb
Host smart-6ac60ab2-7308-4871-9542-93398453b7ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21656
51103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2165651103
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.3495811508
Short name T1510
Test name
Test status
Simulation time 10060214423 ps
CPU time 13.45 seconds
Started Jun 07 08:46:39 PM PDT 24
Finished Jun 07 08:46:57 PM PDT 24
Peak memory 205808 kb
Host smart-763675f9-7fea-442e-bec3-0113e01f2c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34958
11508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.3495811508
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.3548558539
Short name T1349
Test name
Test status
Simulation time 10090819718 ps
CPU time 13.22 seconds
Started Jun 07 08:46:27 PM PDT 24
Finished Jun 07 08:46:47 PM PDT 24
Peak memory 205820 kb
Host smart-61d4174d-a07b-42c8-9a95-8620f2e653a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35485
58539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.3548558539
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.761102521
Short name T497
Test name
Test status
Simulation time 22239762051 ps
CPU time 370.82 seconds
Started Jun 07 08:46:28 PM PDT 24
Finished Jun 07 08:52:46 PM PDT 24
Peak memory 205796 kb
Host smart-f8141010-10d4-4ba4-8164-6192331e307a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76110
2521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.761102521
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.211304018
Short name T881
Test name
Test status
Simulation time 10153997353 ps
CPU time 13.74 seconds
Started Jun 07 08:46:31 PM PDT 24
Finished Jun 07 08:46:51 PM PDT 24
Peak memory 205740 kb
Host smart-ac41e70f-6a2c-4449-a80c-2b19e43420ba
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=211304018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.211304018
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.1263248448
Short name T486
Test name
Test status
Simulation time 10080189215 ps
CPU time 13.71 seconds
Started Jun 07 08:46:40 PM PDT 24
Finished Jun 07 08:46:59 PM PDT 24
Peak memory 205900 kb
Host smart-66d5878d-c490-423e-b328-6c85f0d6b14d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1263248448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.1263248448
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.89695139
Short name T477
Test name
Test status
Simulation time 10101539261 ps
CPU time 13.29 seconds
Started Jun 07 08:46:28 PM PDT 24
Finished Jun 07 08:46:49 PM PDT 24
Peak memory 205812 kb
Host smart-1d0217ca-6aa0-4c9a-a4e0-1f25944e0ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89695
139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.89695139
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.2536389363
Short name T10
Test name
Test status
Simulation time 14065936987 ps
CPU time 18.95 seconds
Started Jun 07 08:46:28 PM PDT 24
Finished Jun 07 08:46:54 PM PDT 24
Peak memory 205824 kb
Host smart-7cbfd83a-4ba7-45d2-9491-f9e4b66d7d0b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2536389363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.2536389363
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.1905760939
Short name T184
Test name
Test status
Simulation time 23297915568 ps
CPU time 26.82 seconds
Started Jun 07 08:46:29 PM PDT 24
Finished Jun 07 08:47:02 PM PDT 24
Peak memory 205900 kb
Host smart-822c814c-b710-4eff-95c0-64df0e4cc87e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1905760939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.1905760939
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.747389820
Short name T1826
Test name
Test status
Simulation time 10059589120 ps
CPU time 14.15 seconds
Started Jun 07 08:46:27 PM PDT 24
Finished Jun 07 08:46:48 PM PDT 24
Peak memory 205768 kb
Host smart-6d847076-8db1-42f3-8c8d-0fffb5fd8bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74738
9820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.747389820
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.1477462633
Short name T427
Test name
Test status
Simulation time 10049614319 ps
CPU time 14.63 seconds
Started Jun 07 08:46:28 PM PDT 24
Finished Jun 07 08:46:49 PM PDT 24
Peak memory 205768 kb
Host smart-e0d2c455-6298-429b-8799-216771f6b334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14774
62633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.1477462633
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.3999979098
Short name T867
Test name
Test status
Simulation time 10051922886 ps
CPU time 12.92 seconds
Started Jun 07 08:46:28 PM PDT 24
Finished Jun 07 08:46:48 PM PDT 24
Peak memory 205828 kb
Host smart-e5e6dc1c-4612-4353-a92c-1048ccb4d28b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39999
79098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.3999979098
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.1619736759
Short name T569
Test name
Test status
Simulation time 10773893775 ps
CPU time 18.3 seconds
Started Jun 07 08:46:39 PM PDT 24
Finished Jun 07 08:47:02 PM PDT 24
Peak memory 205884 kb
Host smart-b93f8c0d-4ba2-4a84-b753-4b3ea24ffde9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16197
36759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.1619736759
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1800823411
Short name T338
Test name
Test status
Simulation time 10201780825 ps
CPU time 14.52 seconds
Started Jun 07 08:46:25 PM PDT 24
Finished Jun 07 08:46:45 PM PDT 24
Peak memory 205876 kb
Host smart-1656dc36-8783-491a-b298-1c4304e549bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18008
23411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1800823411
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.251043234
Short name T1291
Test name
Test status
Simulation time 10111470523 ps
CPU time 15.77 seconds
Started Jun 07 08:46:28 PM PDT 24
Finished Jun 07 08:46:51 PM PDT 24
Peak memory 205880 kb
Host smart-9d02556d-978a-4712-b8e6-650b7d6e635c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25104
3234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.251043234
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2368717451
Short name T1860
Test name
Test status
Simulation time 10046972249 ps
CPU time 14.97 seconds
Started Jun 07 08:46:26 PM PDT 24
Finished Jun 07 08:46:48 PM PDT 24
Peak memory 205692 kb
Host smart-716781b3-a7bf-4622-81e7-99d6c36147fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23687
17451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2368717451
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.2655171105
Short name T784
Test name
Test status
Simulation time 10081084177 ps
CPU time 14.69 seconds
Started Jun 07 08:46:25 PM PDT 24
Finished Jun 07 08:46:45 PM PDT 24
Peak memory 205880 kb
Host smart-810fffb0-f654-4f2a-804d-7ae54df66f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26551
71105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.2655171105
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.3130504272
Short name T1892
Test name
Test status
Simulation time 10149611655 ps
CPU time 14.04 seconds
Started Jun 07 08:46:24 PM PDT 24
Finished Jun 07 08:46:44 PM PDT 24
Peak memory 205764 kb
Host smart-02e463f6-4eb3-49da-8e6f-bee85096206c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31305
04272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.3130504272
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.1354054826
Short name T2027
Test name
Test status
Simulation time 13209933728 ps
CPU time 16.83 seconds
Started Jun 07 08:46:25 PM PDT 24
Finished Jun 07 08:46:48 PM PDT 24
Peak memory 205856 kb
Host smart-33248217-e741-4956-9aeb-4764fc5ed7aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13540
54826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.1354054826
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.593368357
Short name T1049
Test name
Test status
Simulation time 10095084616 ps
CPU time 15.82 seconds
Started Jun 07 08:46:31 PM PDT 24
Finished Jun 07 08:46:53 PM PDT 24
Peak memory 205772 kb
Host smart-89d20c70-c463-4436-9e1a-76d2deab952b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59336
8357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.593368357
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.1349316356
Short name T839
Test name
Test status
Simulation time 19973099333 ps
CPU time 283.58 seconds
Started Jun 07 08:46:25 PM PDT 24
Finished Jun 07 08:51:15 PM PDT 24
Peak memory 205792 kb
Host smart-5e8457d6-230b-468f-a6ff-c6e644950117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13493
16356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.1349316356
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.2304048509
Short name T478
Test name
Test status
Simulation time 10055449199 ps
CPU time 13.42 seconds
Started Jun 07 08:46:28 PM PDT 24
Finished Jun 07 08:46:48 PM PDT 24
Peak memory 205936 kb
Host smart-f785dc30-c024-4c56-9b5f-0c62ac237b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23040
48509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2304048509
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.2633269791
Short name T1820
Test name
Test status
Simulation time 10137677321 ps
CPU time 12.97 seconds
Started Jun 07 08:46:40 PM PDT 24
Finished Jun 07 08:46:58 PM PDT 24
Peak memory 205796 kb
Host smart-7b725864-36bc-4cad-99a5-9ac36dcd325c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26332
69791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2633269791
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.788467770
Short name T339
Test name
Test status
Simulation time 10099442967 ps
CPU time 13.76 seconds
Started Jun 07 08:46:29 PM PDT 24
Finished Jun 07 08:46:50 PM PDT 24
Peak memory 205852 kb
Host smart-0f2d9e14-9387-4f49-9737-fdf3e5ae0b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78846
7770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.788467770
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3207162875
Short name T1126
Test name
Test status
Simulation time 10104448256 ps
CPU time 12.93 seconds
Started Jun 07 08:46:29 PM PDT 24
Finished Jun 07 08:46:48 PM PDT 24
Peak memory 205764 kb
Host smart-1dd3cfd1-080f-4093-8645-86a3fac5739b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32071
62875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3207162875
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.1945078875
Short name T1051
Test name
Test status
Simulation time 10070761643 ps
CPU time 12.62 seconds
Started Jun 07 08:46:25 PM PDT 24
Finished Jun 07 08:46:44 PM PDT 24
Peak memory 205760 kb
Host smart-025e3940-c7a6-45c5-9e10-6eef689d3fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19450
78875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.1945078875
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.698014559
Short name T1149
Test name
Test status
Simulation time 10058724576 ps
CPU time 13.57 seconds
Started Jun 07 08:46:39 PM PDT 24
Finished Jun 07 08:46:58 PM PDT 24
Peak memory 205852 kb
Host smart-e3841670-b5b1-4223-9e4e-b565db002c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69801
4559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.698014559
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_eop_single_bit_handling.2538193952
Short name T1275
Test name
Test status
Simulation time 10089734654 ps
CPU time 15.96 seconds
Started Jun 07 08:46:39 PM PDT 24
Finished Jun 07 08:47:00 PM PDT 24
Peak memory 205856 kb
Host smart-47d9dc03-33b9-4ca3-b2d0-23610b024d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25381
93952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_eop_single_bit_handling.2538193952
Directory /workspace/33.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.1098212234
Short name T1662
Test name
Test status
Simulation time 10042769786 ps
CPU time 13.43 seconds
Started Jun 07 08:46:26 PM PDT 24
Finished Jun 07 08:46:47 PM PDT 24
Peak memory 205884 kb
Host smart-36b136aa-fc06-41e7-acd5-304a32833e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10982
12234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.1098212234
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.3140979063
Short name T1478
Test name
Test status
Simulation time 10081588972 ps
CPU time 15.19 seconds
Started Jun 07 08:46:28 PM PDT 24
Finished Jun 07 08:46:50 PM PDT 24
Peak memory 205760 kb
Host smart-6ab91ec4-f459-4efd-af31-41007d25057b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31409
79063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.3140979063
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.3071717676
Short name T257
Test name
Test status
Simulation time 27904841100 ps
CPU time 52.03 seconds
Started Jun 07 08:46:32 PM PDT 24
Finished Jun 07 08:47:30 PM PDT 24
Peak memory 205796 kb
Host smart-10fa845d-91ac-4635-8535-60c0432496b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30717
17676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.3071717676
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.4293601847
Short name T1137
Test name
Test status
Simulation time 10085612157 ps
CPU time 12.82 seconds
Started Jun 07 08:46:25 PM PDT 24
Finished Jun 07 08:46:44 PM PDT 24
Peak memory 205816 kb
Host smart-b80164be-f801-4eea-a665-2b9daec816f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42936
01847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.4293601847
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2088551096
Short name T889
Test name
Test status
Simulation time 10123257054 ps
CPU time 13.25 seconds
Started Jun 07 08:46:25 PM PDT 24
Finished Jun 07 08:46:43 PM PDT 24
Peak memory 205804 kb
Host smart-745c9836-0f4f-4a0a-862a-efe3983b37f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20885
51096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2088551096
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.1024773056
Short name T1093
Test name
Test status
Simulation time 10071584305 ps
CPU time 12.63 seconds
Started Jun 07 08:46:30 PM PDT 24
Finished Jun 07 08:46:49 PM PDT 24
Peak memory 205708 kb
Host smart-ff236cea-3d7c-4287-b144-deddb064685a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10247
73056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.1024773056
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1491585005
Short name T572
Test name
Test status
Simulation time 10044290379 ps
CPU time 14.37 seconds
Started Jun 07 08:46:25 PM PDT 24
Finished Jun 07 08:46:45 PM PDT 24
Peak memory 205824 kb
Host smart-295401f7-f536-41e5-9bdf-5bcc81155395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14915
85005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1491585005
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.343832331
Short name T1158
Test name
Test status
Simulation time 10126711560 ps
CPU time 15.76 seconds
Started Jun 07 08:46:29 PM PDT 24
Finished Jun 07 08:46:51 PM PDT 24
Peak memory 205848 kb
Host smart-e4fb212f-9a21-458b-b35b-5c87c442796f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34383
2331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.343832331
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.4068382556
Short name T813
Test name
Test status
Simulation time 10058812082 ps
CPU time 13.73 seconds
Started Jun 07 08:46:29 PM PDT 24
Finished Jun 07 08:46:50 PM PDT 24
Peak memory 205792 kb
Host smart-f0d03ba5-113b-4c5d-b3da-49fd91f1e0ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40683
82556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.4068382556
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.1481985539
Short name T802
Test name
Test status
Simulation time 10094570837 ps
CPU time 14.94 seconds
Started Jun 07 08:46:31 PM PDT 24
Finished Jun 07 08:46:52 PM PDT 24
Peak memory 205760 kb
Host smart-c865804e-aa1a-4b5c-b3bd-fe3be24b7539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14819
85539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1481985539
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.1566913990
Short name T2016
Test name
Test status
Simulation time 10037284138 ps
CPU time 14.13 seconds
Started Jun 07 08:46:27 PM PDT 24
Finished Jun 07 08:46:48 PM PDT 24
Peak memory 205800 kb
Host smart-a194cd6d-0475-430d-86d7-2b1770e16e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15669
13990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.1566913990
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.3667955684
Short name T2029
Test name
Test status
Simulation time 10059319116 ps
CPU time 13.85 seconds
Started Jun 07 08:46:40 PM PDT 24
Finished Jun 07 08:46:58 PM PDT 24
Peak memory 205880 kb
Host smart-c0ee4f1a-73c1-414c-a611-42d4ba276fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36679
55684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.3667955684
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.3048241472
Short name T1491
Test name
Test status
Simulation time 16315271374 ps
CPU time 57.46 seconds
Started Jun 07 08:46:31 PM PDT 24
Finished Jun 07 08:47:35 PM PDT 24
Peak memory 205800 kb
Host smart-dca9275a-1f9b-4329-8059-7af1a518e09d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30482
41472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.3048241472
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.4137683235
Short name T2009
Test name
Test status
Simulation time 10191238253 ps
CPU time 16.71 seconds
Started Jun 07 08:46:34 PM PDT 24
Finished Jun 07 08:46:57 PM PDT 24
Peak memory 205896 kb
Host smart-5e7fdf41-a08f-4694-aab8-08685e95d695
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4137683235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.4137683235
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.3761091334
Short name T1899
Test name
Test status
Simulation time 10050370444 ps
CPU time 14.12 seconds
Started Jun 07 08:46:33 PM PDT 24
Finished Jun 07 08:46:53 PM PDT 24
Peak memory 205860 kb
Host smart-a9983ee0-d0b9-465f-b802-93849746301d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3761091334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.3761091334
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.2177770034
Short name T1873
Test name
Test status
Simulation time 10139883702 ps
CPU time 13.74 seconds
Started Jun 07 08:46:37 PM PDT 24
Finished Jun 07 08:46:56 PM PDT 24
Peak memory 205832 kb
Host smart-00cf33a0-6584-425f-b82d-937f93f45c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21777
70034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.2177770034
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.368562120
Short name T704
Test name
Test status
Simulation time 13667665961 ps
CPU time 18.98 seconds
Started Jun 07 08:46:30 PM PDT 24
Finished Jun 07 08:46:56 PM PDT 24
Peak memory 205768 kb
Host smart-212fb230-4154-425c-9a26-5ca96ce70992
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=368562120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.368562120
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.431288564
Short name T15
Test name
Test status
Simulation time 23263447862 ps
CPU time 23.7 seconds
Started Jun 07 08:46:30 PM PDT 24
Finished Jun 07 08:47:01 PM PDT 24
Peak memory 205828 kb
Host smart-549f61c5-a4ac-486e-8a19-19bde7b83dae
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=431288564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.431288564
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.699667741
Short name T82
Test name
Test status
Simulation time 10046958057 ps
CPU time 13.23 seconds
Started Jun 07 08:46:40 PM PDT 24
Finished Jun 07 08:46:58 PM PDT 24
Peak memory 205764 kb
Host smart-4c6d2f9c-b17f-47db-ac9c-04777fe71c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69966
7741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.699667741
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.2681881852
Short name T622
Test name
Test status
Simulation time 10090541745 ps
CPU time 16.09 seconds
Started Jun 07 08:46:33 PM PDT 24
Finished Jun 07 08:46:56 PM PDT 24
Peak memory 205736 kb
Host smart-2e046f18-b34d-4854-950c-bfb0000a56ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26818
81852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.2681881852
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.3024033221
Short name T1121
Test name
Test status
Simulation time 11054289936 ps
CPU time 15.92 seconds
Started Jun 07 08:46:32 PM PDT 24
Finished Jun 07 08:46:54 PM PDT 24
Peak memory 205868 kb
Host smart-fa394c25-1e9e-4cbd-88e8-0fe18a3262c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30240
33221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.3024033221
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.595240429
Short name T1539
Test name
Test status
Simulation time 10052775555 ps
CPU time 12.9 seconds
Started Jun 07 08:46:34 PM PDT 24
Finished Jun 07 08:46:53 PM PDT 24
Peak memory 205820 kb
Host smart-1ba19f65-bda9-4319-bc3c-5a7ffee9f86a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59524
0429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.595240429
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.1598302585
Short name T823
Test name
Test status
Simulation time 10091815390 ps
CPU time 12.68 seconds
Started Jun 07 08:46:30 PM PDT 24
Finished Jun 07 08:46:49 PM PDT 24
Peak memory 205836 kb
Host smart-d8a1d987-b770-48f3-89fc-2e295651b616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15983
02585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.1598302585
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.4235048865
Short name T204
Test name
Test status
Simulation time 10799650282 ps
CPU time 14.66 seconds
Started Jun 07 08:46:35 PM PDT 24
Finished Jun 07 08:46:55 PM PDT 24
Peak memory 205964 kb
Host smart-a8b8108c-4df8-4116-b3df-64ab43cf6c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42350
48865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.4235048865
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.448528855
Short name T1783
Test name
Test status
Simulation time 10113167865 ps
CPU time 13.89 seconds
Started Jun 07 08:46:36 PM PDT 24
Finished Jun 07 08:46:56 PM PDT 24
Peak memory 205868 kb
Host smart-278642af-29b9-4181-92ae-d1a37f188f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44852
8855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.448528855
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.215696915
Short name T1191
Test name
Test status
Simulation time 10150338049 ps
CPU time 13.91 seconds
Started Jun 07 08:46:41 PM PDT 24
Finished Jun 07 08:47:00 PM PDT 24
Peak memory 205848 kb
Host smart-61557adb-88d8-495c-baa4-54baaca0b8c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21569
6915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.215696915
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3158248402
Short name T1521
Test name
Test status
Simulation time 10041766691 ps
CPU time 13.5 seconds
Started Jun 07 08:46:35 PM PDT 24
Finished Jun 07 08:46:54 PM PDT 24
Peak memory 205880 kb
Host smart-d2a9e3a3-dde4-4723-b257-cde97bffa19a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31582
48402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3158248402
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.1383209262
Short name T934
Test name
Test status
Simulation time 10096776180 ps
CPU time 13.87 seconds
Started Jun 07 08:46:36 PM PDT 24
Finished Jun 07 08:46:55 PM PDT 24
Peak memory 205804 kb
Host smart-74064025-bde3-4b87-b08f-2002757151fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13832
09262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.1383209262
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.57798155
Short name T1276
Test name
Test status
Simulation time 10164131057 ps
CPU time 16.33 seconds
Started Jun 07 08:46:46 PM PDT 24
Finished Jun 07 08:47:05 PM PDT 24
Peak memory 205768 kb
Host smart-96844025-4934-442d-80ec-07bf0f62bd82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57798
155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.57798155
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.2068063912
Short name T1463
Test name
Test status
Simulation time 13198305632 ps
CPU time 16.22 seconds
Started Jun 07 08:46:31 PM PDT 24
Finished Jun 07 08:46:54 PM PDT 24
Peak memory 205744 kb
Host smart-a02e19aa-336b-4780-a93d-679844a8a952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20680
63912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.2068063912
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2271546762
Short name T1067
Test name
Test status
Simulation time 10130171056 ps
CPU time 13.43 seconds
Started Jun 07 08:46:34 PM PDT 24
Finished Jun 07 08:46:54 PM PDT 24
Peak memory 205436 kb
Host smart-7e2ea325-e2d4-4f65-98eb-2eccbfadd619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22715
46762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2271546762
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.2403103856
Short name T1840
Test name
Test status
Simulation time 17910646851 ps
CPU time 86.96 seconds
Started Jun 07 08:46:36 PM PDT 24
Finished Jun 07 08:48:08 PM PDT 24
Peak memory 205704 kb
Host smart-2a171506-2fd0-4442-8d95-3d3cacfba0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24031
03856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.2403103856
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3522842849
Short name T1315
Test name
Test status
Simulation time 10057557663 ps
CPU time 15.65 seconds
Started Jun 07 08:46:40 PM PDT 24
Finished Jun 07 08:47:01 PM PDT 24
Peak memory 205856 kb
Host smart-9b525f46-fb23-4d63-a8d2-28318d0c07c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35228
42849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3522842849
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.2967920710
Short name T119
Test name
Test status
Simulation time 10091259768 ps
CPU time 12.92 seconds
Started Jun 07 08:46:33 PM PDT 24
Finished Jun 07 08:46:52 PM PDT 24
Peak memory 205852 kb
Host smart-0ebfcd30-1598-490e-b09d-40bd217e28f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29679
20710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2967920710
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.3227959927
Short name T1728
Test name
Test status
Simulation time 10088380167 ps
CPU time 14.25 seconds
Started Jun 07 08:46:33 PM PDT 24
Finished Jun 07 08:46:54 PM PDT 24
Peak memory 205836 kb
Host smart-a52b5667-3242-4a4d-9bc8-0d4e25bdeebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32279
59927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.3227959927
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2004171912
Short name T1697
Test name
Test status
Simulation time 10091858541 ps
CPU time 16 seconds
Started Jun 07 08:46:34 PM PDT 24
Finished Jun 07 08:46:55 PM PDT 24
Peak memory 205796 kb
Host smart-6a11ecb6-68cb-4932-bb4c-06dbf0042f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20041
71912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2004171912
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2089200041
Short name T968
Test name
Test status
Simulation time 10074704870 ps
CPU time 12.76 seconds
Started Jun 07 08:46:34 PM PDT 24
Finished Jun 07 08:46:53 PM PDT 24
Peak memory 205848 kb
Host smart-809c8bb5-441e-4bde-8759-688857cb544f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20892
00041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2089200041
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.1833092605
Short name T153
Test name
Test status
Simulation time 10062633986 ps
CPU time 15.95 seconds
Started Jun 07 08:46:33 PM PDT 24
Finished Jun 07 08:46:55 PM PDT 24
Peak memory 205932 kb
Host smart-aa237c60-afde-4fdf-a7bf-08402ed787e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18330
92605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.1833092605
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_eop_single_bit_handling.980330242
Short name T1632
Test name
Test status
Simulation time 10066808440 ps
CPU time 13.35 seconds
Started Jun 07 08:46:33 PM PDT 24
Finished Jun 07 08:46:53 PM PDT 24
Peak memory 205752 kb
Host smart-38af01c5-c3d0-4e08-a790-9f429dede53f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98033
0242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_eop_single_bit_handling.980330242
Directory /workspace/34.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.334631663
Short name T1648
Test name
Test status
Simulation time 10040920778 ps
CPU time 15.77 seconds
Started Jun 07 08:46:36 PM PDT 24
Finished Jun 07 08:46:57 PM PDT 24
Peak memory 205768 kb
Host smart-05f2eeb5-ba75-45f8-a9ef-1eda7cd6963b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33463
1663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.334631663
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.1920342898
Short name T710
Test name
Test status
Simulation time 10039404877 ps
CPU time 14.01 seconds
Started Jun 07 08:46:35 PM PDT 24
Finished Jun 07 08:46:55 PM PDT 24
Peak memory 205844 kb
Host smart-8c901204-eb7e-4523-9ec5-4f16b8891349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19203
42898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.1920342898
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.399105119
Short name T1446
Test name
Test status
Simulation time 29508986393 ps
CPU time 54.9 seconds
Started Jun 07 08:46:33 PM PDT 24
Finished Jun 07 08:47:34 PM PDT 24
Peak memory 205700 kb
Host smart-00a83173-ac02-44b9-8c7a-99946aa6436f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39910
5119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.399105119
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.1300367184
Short name T1473
Test name
Test status
Simulation time 10074322502 ps
CPU time 12.59 seconds
Started Jun 07 08:46:34 PM PDT 24
Finished Jun 07 08:46:52 PM PDT 24
Peak memory 205736 kb
Host smart-816c946a-e867-47a2-b3e8-51279af08199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13003
67184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.1300367184
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.3246035384
Short name T1579
Test name
Test status
Simulation time 10119932026 ps
CPU time 13.15 seconds
Started Jun 07 08:46:33 PM PDT 24
Finished Jun 07 08:46:52 PM PDT 24
Peak memory 205760 kb
Host smart-324c44ca-9a8f-4c25-a44b-ae1a2b7d7bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32460
35384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.3246035384
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.3720852799
Short name T1342
Test name
Test status
Simulation time 10091249572 ps
CPU time 13.55 seconds
Started Jun 07 08:46:33 PM PDT 24
Finished Jun 07 08:46:53 PM PDT 24
Peak memory 205732 kb
Host smart-aa610cbf-e4dd-4235-b6de-606cb26da41c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37208
52799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.3720852799
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.3887616218
Short name T591
Test name
Test status
Simulation time 10045596618 ps
CPU time 12.9 seconds
Started Jun 07 08:46:34 PM PDT 24
Finished Jun 07 08:46:53 PM PDT 24
Peak memory 205404 kb
Host smart-f8762227-6326-4b7d-89f0-afaa1dbd2994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38876
16218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.3887616218
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.332733406
Short name T1736
Test name
Test status
Simulation time 10086364381 ps
CPU time 15.05 seconds
Started Jun 07 08:46:33 PM PDT 24
Finished Jun 07 08:46:54 PM PDT 24
Peak memory 205776 kb
Host smart-155656a8-5a1f-4a79-a1bf-cfbc4f425187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33273
3406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.332733406
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1779756038
Short name T1257
Test name
Test status
Simulation time 10102725605 ps
CPU time 15.38 seconds
Started Jun 07 08:46:33 PM PDT 24
Finished Jun 07 08:46:55 PM PDT 24
Peak memory 205840 kb
Host smart-5874238c-259c-4b02-92ba-efd2eacdf230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17797
56038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1779756038
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.3966002341
Short name T141
Test name
Test status
Simulation time 10113156036 ps
CPU time 14.09 seconds
Started Jun 07 08:46:31 PM PDT 24
Finished Jun 07 08:46:52 PM PDT 24
Peak memory 205792 kb
Host smart-0c6ce0c2-0e92-447c-b06f-73b942f92a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39660
02341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3966002341
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.533096404
Short name T1079
Test name
Test status
Simulation time 10045047603 ps
CPU time 13.3 seconds
Started Jun 07 08:46:36 PM PDT 24
Finished Jun 07 08:46:55 PM PDT 24
Peak memory 205736 kb
Host smart-a4801d61-9168-4db5-8bb3-07d28493ac52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53309
6404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.533096404
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.517466137
Short name T868
Test name
Test status
Simulation time 10116958218 ps
CPU time 14.07 seconds
Started Jun 07 08:46:35 PM PDT 24
Finished Jun 07 08:46:55 PM PDT 24
Peak memory 205756 kb
Host smart-9c0b412c-4143-44a2-8e88-bc02c6ca5411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51746
6137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.517466137
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.2827008257
Short name T938
Test name
Test status
Simulation time 18386833359 ps
CPU time 73.45 seconds
Started Jun 07 08:46:33 PM PDT 24
Finished Jun 07 08:47:53 PM PDT 24
Peak memory 205860 kb
Host smart-36384f47-f834-4084-9b98-1c0c1194b3ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28270
08257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.2827008257
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.2205539914
Short name T585
Test name
Test status
Simulation time 10164017973 ps
CPU time 13.58 seconds
Started Jun 07 08:46:40 PM PDT 24
Finished Jun 07 08:46:59 PM PDT 24
Peak memory 205776 kb
Host smart-a0a76d44-ed82-417d-a79e-17e1ebecea5f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2205539914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.2205539914
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.51115363
Short name T361
Test name
Test status
Simulation time 10072884689 ps
CPU time 13.31 seconds
Started Jun 07 08:46:52 PM PDT 24
Finished Jun 07 08:47:09 PM PDT 24
Peak memory 205788 kb
Host smart-925dda65-0e24-4c81-b25e-f2c28a667b18
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=51115363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.51115363
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.453373220
Short name T1058
Test name
Test status
Simulation time 10122959577 ps
CPU time 16.83 seconds
Started Jun 07 08:46:49 PM PDT 24
Finished Jun 07 08:47:08 PM PDT 24
Peak memory 205948 kb
Host smart-6103abed-944a-4a01-9832-d0151680147d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45337
3220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.453373220
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.1745651538
Short name T1112
Test name
Test status
Simulation time 13944270647 ps
CPU time 16.45 seconds
Started Jun 07 08:46:37 PM PDT 24
Finished Jun 07 08:46:58 PM PDT 24
Peak memory 205828 kb
Host smart-df0c559d-e41e-46fe-887d-71b170cf9360
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1745651538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.1745651538
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.809930932
Short name T1189
Test name
Test status
Simulation time 23352722658 ps
CPU time 25.7 seconds
Started Jun 07 08:46:41 PM PDT 24
Finished Jun 07 08:47:12 PM PDT 24
Peak memory 205824 kb
Host smart-cc00b8aa-fc8f-4f1d-a44b-05bc02c6ee3c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=809930932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.809930932
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.4283647492
Short name T1958
Test name
Test status
Simulation time 10073859862 ps
CPU time 13.99 seconds
Started Jun 07 08:46:39 PM PDT 24
Finished Jun 07 08:46:58 PM PDT 24
Peak memory 205888 kb
Host smart-fc0c9d9e-1c9a-4b76-9ed4-fe6549f2ec34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42836
47492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.4283647492
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.2931281994
Short name T617
Test name
Test status
Simulation time 10322653535 ps
CPU time 13.99 seconds
Started Jun 07 08:46:35 PM PDT 24
Finished Jun 07 08:46:55 PM PDT 24
Peak memory 205844 kb
Host smart-61e8466f-117c-453e-98ce-5758c78a59c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29312
81994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.2931281994
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.3154445841
Short name T1654
Test name
Test status
Simulation time 10031278335 ps
CPU time 14.11 seconds
Started Jun 07 08:46:45 PM PDT 24
Finished Jun 07 08:47:02 PM PDT 24
Peak memory 205744 kb
Host smart-7794dffa-521d-47dc-b6e5-95c9bc519ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31544
45841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.3154445841
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.3390200052
Short name T1781
Test name
Test status
Simulation time 10096920324 ps
CPU time 14.16 seconds
Started Jun 07 08:46:35 PM PDT 24
Finished Jun 07 08:46:55 PM PDT 24
Peak memory 205860 kb
Host smart-cf4a4a09-668b-45c2-b2c7-0557cfe6d5e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33902
00052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.3390200052
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.2521712723
Short name T489
Test name
Test status
Simulation time 10699991577 ps
CPU time 13.82 seconds
Started Jun 07 08:46:39 PM PDT 24
Finished Jun 07 08:46:58 PM PDT 24
Peak memory 205876 kb
Host smart-9c0a5a8e-80b0-411f-9f26-2d0eefeb4f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25217
12723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.2521712723
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.2533023494
Short name T1445
Test name
Test status
Simulation time 10073102779 ps
CPU time 14.71 seconds
Started Jun 07 08:46:39 PM PDT 24
Finished Jun 07 08:46:59 PM PDT 24
Peak memory 205792 kb
Host smart-96b7684a-6a89-4807-aae5-31760a221da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25330
23494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.2533023494
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.650227001
Short name T1448
Test name
Test status
Simulation time 10058623619 ps
CPU time 13.02 seconds
Started Jun 07 08:46:43 PM PDT 24
Finished Jun 07 08:47:00 PM PDT 24
Peak memory 205824 kb
Host smart-2766b3e9-e242-48c3-9d83-528892d79f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65022
7001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.650227001
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.3367694897
Short name T716
Test name
Test status
Simulation time 10039362675 ps
CPU time 14.23 seconds
Started Jun 07 08:46:46 PM PDT 24
Finished Jun 07 08:47:03 PM PDT 24
Peak memory 205872 kb
Host smart-5e238e7b-cbe2-432c-9d24-2bc08137c791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33676
94897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.3367694897
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3576216252
Short name T512
Test name
Test status
Simulation time 10145801923 ps
CPU time 13.54 seconds
Started Jun 07 08:46:35 PM PDT 24
Finished Jun 07 08:46:54 PM PDT 24
Peak memory 205872 kb
Host smart-2dd6693b-ac5f-49eb-b9e1-17f6848b13d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35762
16252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3576216252
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.2370356857
Short name T303
Test name
Test status
Simulation time 10095220087 ps
CPU time 13.04 seconds
Started Jun 07 08:46:33 PM PDT 24
Finished Jun 07 08:46:52 PM PDT 24
Peak memory 205872 kb
Host smart-56576874-ef8c-4928-9503-92dd0188f2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23703
56857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.2370356857
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.4269089785
Short name T577
Test name
Test status
Simulation time 13205818697 ps
CPU time 17.9 seconds
Started Jun 07 08:46:34 PM PDT 24
Finished Jun 07 08:46:58 PM PDT 24
Peak memory 205756 kb
Host smart-523a1164-5631-4e1f-9728-ceb19e86ad5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42690
89785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.4269089785
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.4131191901
Short name T314
Test name
Test status
Simulation time 10100705173 ps
CPU time 16.16 seconds
Started Jun 07 08:46:34 PM PDT 24
Finished Jun 07 08:46:56 PM PDT 24
Peak memory 205800 kb
Host smart-b53994f5-8181-4b2b-932b-839fa224e120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41311
91901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.4131191901
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.4096510378
Short name T1967
Test name
Test status
Simulation time 22550298981 ps
CPU time 381.34 seconds
Started Jun 07 08:46:42 PM PDT 24
Finished Jun 07 08:53:08 PM PDT 24
Peak memory 205544 kb
Host smart-7c01d65c-3702-47e2-a0ea-c605c225a051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40965
10378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.4096510378
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2556602365
Short name T476
Test name
Test status
Simulation time 10065544401 ps
CPU time 13.5 seconds
Started Jun 07 08:46:41 PM PDT 24
Finished Jun 07 08:46:59 PM PDT 24
Peak memory 205816 kb
Host smart-9e6abd99-3efb-4d99-97c7-3c40de1bdf31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25566
02365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2556602365
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2864501777
Short name T95
Test name
Test status
Simulation time 10132287057 ps
CPU time 16.03 seconds
Started Jun 07 08:46:41 PM PDT 24
Finished Jun 07 08:47:02 PM PDT 24
Peak memory 205860 kb
Host smart-fc31e006-862d-4839-ae1c-5931661e94d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28645
01777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2864501777
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.331056393
Short name T882
Test name
Test status
Simulation time 10094045742 ps
CPU time 13.63 seconds
Started Jun 07 08:46:41 PM PDT 24
Finished Jun 07 08:46:59 PM PDT 24
Peak memory 205852 kb
Host smart-5573927c-9ddd-4aa6-899d-12f0c57c22e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33105
6393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.331056393
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.4210969230
Short name T1822
Test name
Test status
Simulation time 10088072543 ps
CPU time 15.9 seconds
Started Jun 07 08:46:43 PM PDT 24
Finished Jun 07 08:47:03 PM PDT 24
Peak memory 205736 kb
Host smart-74822460-4003-4a78-8937-95a25c11c8e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42109
69230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.4210969230
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.2078851855
Short name T287
Test name
Test status
Simulation time 10059489369 ps
CPU time 15.68 seconds
Started Jun 07 08:46:41 PM PDT 24
Finished Jun 07 08:47:01 PM PDT 24
Peak memory 205828 kb
Host smart-5496f16b-5a47-491a-b25f-434629530e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20788
51855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.2078851855
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.1198136418
Short name T1669
Test name
Test status
Simulation time 10057693683 ps
CPU time 13 seconds
Started Jun 07 08:46:50 PM PDT 24
Finished Jun 07 08:47:05 PM PDT 24
Peak memory 205780 kb
Host smart-3b2f0046-2b6b-4052-8c0c-54bed96266c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11981
36418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.1198136418
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_eop_single_bit_handling.4076905472
Short name T713
Test name
Test status
Simulation time 10114644898 ps
CPU time 14.63 seconds
Started Jun 07 08:46:42 PM PDT 24
Finished Jun 07 08:47:01 PM PDT 24
Peak memory 205764 kb
Host smart-f9f44511-8b52-42fc-88eb-4e00c4e5fb0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40769
05472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_eop_single_bit_handling.4076905472
Directory /workspace/35.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.4155552886
Short name T1709
Test name
Test status
Simulation time 10055427109 ps
CPU time 13.9 seconds
Started Jun 07 08:46:39 PM PDT 24
Finished Jun 07 08:46:58 PM PDT 24
Peak memory 205804 kb
Host smart-5495cd6b-ed35-45d3-b626-1e710f797671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41555
52886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.4155552886
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.719226335
Short name T1075
Test name
Test status
Simulation time 10057579288 ps
CPU time 12.78 seconds
Started Jun 07 08:46:42 PM PDT 24
Finished Jun 07 08:46:59 PM PDT 24
Peak memory 205920 kb
Host smart-d9b17acf-d130-46c5-9dbd-b640308818ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71922
6335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.719226335
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.2587084183
Short name T1533
Test name
Test status
Simulation time 30524447408 ps
CPU time 64.58 seconds
Started Jun 07 08:46:41 PM PDT 24
Finished Jun 07 08:47:50 PM PDT 24
Peak memory 205780 kb
Host smart-e7135522-b9da-440d-acd3-295cf0f7ae5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25870
84183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.2587084183
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.1329116523
Short name T1287
Test name
Test status
Simulation time 10095864819 ps
CPU time 12.49 seconds
Started Jun 07 08:46:43 PM PDT 24
Finished Jun 07 08:46:59 PM PDT 24
Peak memory 205740 kb
Host smart-4ef93881-5db2-4660-a05f-4e5e734d5ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13291
16523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.1329116523
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.1774831904
Short name T1
Test name
Test status
Simulation time 10095379137 ps
CPU time 13.63 seconds
Started Jun 07 08:46:40 PM PDT 24
Finished Jun 07 08:46:59 PM PDT 24
Peak memory 205808 kb
Host smart-fc7e4c20-f97e-42f7-811d-4d5351eee695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17748
31904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.1774831904
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.815742118
Short name T521
Test name
Test status
Simulation time 10135293272 ps
CPU time 15.87 seconds
Started Jun 07 08:46:45 PM PDT 24
Finished Jun 07 08:47:04 PM PDT 24
Peak memory 205744 kb
Host smart-0d103229-e787-4a08-bf32-68edf6c96223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81574
2118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.815742118
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.3823671125
Short name T785
Test name
Test status
Simulation time 10036549844 ps
CPU time 12.34 seconds
Started Jun 07 08:46:40 PM PDT 24
Finished Jun 07 08:46:57 PM PDT 24
Peak memory 205844 kb
Host smart-cb9ea8bb-e353-4ea1-bb34-bebb687f02b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38236
71125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.3823671125
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.107467454
Short name T1440
Test name
Test status
Simulation time 10049217140 ps
CPU time 13.93 seconds
Started Jun 07 08:46:40 PM PDT 24
Finished Jun 07 08:46:59 PM PDT 24
Peak memory 205868 kb
Host smart-59b3d559-931b-4617-93d6-cd4cdcdc00c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10746
7454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.107467454
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3269357475
Short name T996
Test name
Test status
Simulation time 10062898017 ps
CPU time 13.09 seconds
Started Jun 07 08:46:49 PM PDT 24
Finished Jun 07 08:47:04 PM PDT 24
Peak memory 205780 kb
Host smart-e91e788c-24c5-462b-9f19-328b298b7370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32693
57475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3269357475
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.3680884192
Short name T1071
Test name
Test status
Simulation time 10127568699 ps
CPU time 14.52 seconds
Started Jun 07 08:46:32 PM PDT 24
Finished Jun 07 08:46:53 PM PDT 24
Peak memory 205868 kb
Host smart-77f378d9-3b0e-4a4b-8eed-ad540b8a7b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36808
84192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3680884192
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3327241157
Short name T1077
Test name
Test status
Simulation time 10064110682 ps
CPU time 13.79 seconds
Started Jun 07 08:46:42 PM PDT 24
Finished Jun 07 08:47:00 PM PDT 24
Peak memory 205844 kb
Host smart-b64bb135-d751-41a5-a2c4-3c86c738b547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33272
41157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3327241157
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.1684581227
Short name T321
Test name
Test status
Simulation time 10068510042 ps
CPU time 14.04 seconds
Started Jun 07 08:46:38 PM PDT 24
Finished Jun 07 08:46:57 PM PDT 24
Peak memory 205856 kb
Host smart-2f19f106-bf00-4ec5-8bf6-a8acc9c9f05b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16845
81227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.1684581227
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.3245657909
Short name T1527
Test name
Test status
Simulation time 21174210830 ps
CPU time 343.23 seconds
Started Jun 07 08:46:42 PM PDT 24
Finished Jun 07 08:52:30 PM PDT 24
Peak memory 205616 kb
Host smart-26853a57-5cef-4b72-a830-978ed7b961ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32456
57909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.3245657909
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.154640641
Short name T745
Test name
Test status
Simulation time 10164698060 ps
CPU time 13.07 seconds
Started Jun 07 08:47:01 PM PDT 24
Finished Jun 07 08:47:16 PM PDT 24
Peak memory 205884 kb
Host smart-b2e9f0d5-17d5-4844-b202-24640292d191
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=154640641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.154640641
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.665476237
Short name T627
Test name
Test status
Simulation time 10056141151 ps
CPU time 12.34 seconds
Started Jun 07 08:46:48 PM PDT 24
Finished Jun 07 08:47:02 PM PDT 24
Peak memory 205808 kb
Host smart-14960f40-28d7-4db0-8c78-e1672273dc30
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=665476237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.665476237
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.530786606
Short name T1919
Test name
Test status
Simulation time 10056561657 ps
CPU time 13.24 seconds
Started Jun 07 08:46:55 PM PDT 24
Finished Jun 07 08:47:12 PM PDT 24
Peak memory 205736 kb
Host smart-377fb85b-4200-4229-a9c7-994ecf2a34eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53078
6606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.530786606
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.1325075298
Short name T820
Test name
Test status
Simulation time 13918098246 ps
CPU time 18.42 seconds
Started Jun 07 08:46:41 PM PDT 24
Finished Jun 07 08:47:04 PM PDT 24
Peak memory 205932 kb
Host smart-52de2c63-8785-420d-9c0b-59e9239bf822
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1325075298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.1325075298
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.1594811130
Short name T47
Test name
Test status
Simulation time 23286099171 ps
CPU time 25.82 seconds
Started Jun 07 08:46:50 PM PDT 24
Finished Jun 07 08:47:19 PM PDT 24
Peak memory 205796 kb
Host smart-e8b69660-e7ac-4aef-a6d8-53b593f0f89f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1594811130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.1594811130
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.3154350328
Short name T315
Test name
Test status
Simulation time 10053023327 ps
CPU time 15.86 seconds
Started Jun 07 08:46:46 PM PDT 24
Finished Jun 07 08:47:05 PM PDT 24
Peak memory 205772 kb
Host smart-628375e6-8ff3-4101-8ab3-10f8f448f603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31543
50328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.3154350328
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.2224148388
Short name T1518
Test name
Test status
Simulation time 11224246382 ps
CPU time 15.12 seconds
Started Jun 07 08:46:39 PM PDT 24
Finished Jun 07 08:46:59 PM PDT 24
Peak memory 205672 kb
Host smart-ff0dbb11-cd93-4cdf-9593-28a73298864a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22241
48388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.2224148388
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.3959848246
Short name T1570
Test name
Test status
Simulation time 10078157899 ps
CPU time 13.46 seconds
Started Jun 07 08:46:54 PM PDT 24
Finished Jun 07 08:47:12 PM PDT 24
Peak memory 205756 kb
Host smart-430ba12f-9fea-4eff-abf3-05beb443a638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39598
48246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.3959848246
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.4293771860
Short name T709
Test name
Test status
Simulation time 10057029730 ps
CPU time 13.44 seconds
Started Jun 07 08:46:53 PM PDT 24
Finished Jun 07 08:47:10 PM PDT 24
Peak memory 205908 kb
Host smart-584e11f3-12cd-49a8-b4d9-15c9cadce737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42937
71860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.4293771860
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.2636880251
Short name T1688
Test name
Test status
Simulation time 10789359616 ps
CPU time 14.52 seconds
Started Jun 07 08:46:42 PM PDT 24
Finished Jun 07 08:47:01 PM PDT 24
Peak memory 205884 kb
Host smart-d371116c-9b81-4992-befc-f7c842e6b864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26368
80251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.2636880251
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1913721757
Short name T605
Test name
Test status
Simulation time 10070530315 ps
CPU time 13.13 seconds
Started Jun 07 08:46:55 PM PDT 24
Finished Jun 07 08:47:12 PM PDT 24
Peak memory 205656 kb
Host smart-3b901882-1b52-455e-80cd-de74ffb4d999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19137
21757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1913721757
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.3626266359
Short name T671
Test name
Test status
Simulation time 10062766417 ps
CPU time 12.47 seconds
Started Jun 07 08:46:49 PM PDT 24
Finished Jun 07 08:47:03 PM PDT 24
Peak memory 205732 kb
Host smart-bbfb0b33-d737-4ce4-bb45-4edcd58e36fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36262
66359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.3626266359
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.2064973914
Short name T561
Test name
Test status
Simulation time 10057877461 ps
CPU time 13.23 seconds
Started Jun 07 08:46:53 PM PDT 24
Finished Jun 07 08:47:10 PM PDT 24
Peak memory 205848 kb
Host smart-de879039-ca80-4e76-8fe1-782f359322e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20649
73914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.2064973914
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2646095495
Short name T1603
Test name
Test status
Simulation time 10150370823 ps
CPU time 12.99 seconds
Started Jun 07 08:46:50 PM PDT 24
Finished Jun 07 08:47:06 PM PDT 24
Peak memory 205848 kb
Host smart-5179bd06-defc-45dd-b6d4-87489281a36b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26460
95495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2646095495
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.2759185715
Short name T358
Test name
Test status
Simulation time 10091976239 ps
CPU time 15.08 seconds
Started Jun 07 08:46:50 PM PDT 24
Finished Jun 07 08:47:08 PM PDT 24
Peak memory 205796 kb
Host smart-d033c9f0-8022-4c38-900b-edc1ae7ff729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27591
85715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.2759185715
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.793870589
Short name T1722
Test name
Test status
Simulation time 13212405802 ps
CPU time 17.26 seconds
Started Jun 07 08:46:54 PM PDT 24
Finished Jun 07 08:47:15 PM PDT 24
Peak memory 205768 kb
Host smart-23998507-95f6-42ac-ba51-7b0ba84e597c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79387
0589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.793870589
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.797084259
Short name T618
Test name
Test status
Simulation time 10099713940 ps
CPU time 13.16 seconds
Started Jun 07 08:46:50 PM PDT 24
Finished Jun 07 08:47:05 PM PDT 24
Peak memory 205904 kb
Host smart-48d06039-d9c6-497e-8330-c53af109252a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79708
4259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.797084259
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.832211733
Short name T758
Test name
Test status
Simulation time 19964888143 ps
CPU time 292.32 seconds
Started Jun 07 08:46:50 PM PDT 24
Finished Jun 07 08:51:45 PM PDT 24
Peak memory 205764 kb
Host smart-ae0e1818-5cde-486b-a5c5-5c5929dbe8ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83221
1733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.832211733
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.416061129
Short name T482
Test name
Test status
Simulation time 10038795832 ps
CPU time 12.98 seconds
Started Jun 07 08:46:51 PM PDT 24
Finished Jun 07 08:47:07 PM PDT 24
Peak memory 205916 kb
Host smart-af4c38d2-8853-4d53-9b25-79704425cf5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41606
1129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.416061129
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.1332633367
Short name T100
Test name
Test status
Simulation time 10088883398 ps
CPU time 13.73 seconds
Started Jun 07 08:46:54 PM PDT 24
Finished Jun 07 08:47:11 PM PDT 24
Peak memory 205844 kb
Host smart-6b0ee371-de71-4db4-9eff-01f7e97d21b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13326
33367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1332633367
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.1338878486
Short name T895
Test name
Test status
Simulation time 10084452149 ps
CPU time 12.42 seconds
Started Jun 07 08:46:54 PM PDT 24
Finished Jun 07 08:47:10 PM PDT 24
Peak memory 205808 kb
Host smart-ab62e7fc-b118-447f-a2ce-0bc118867081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13388
78486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.1338878486
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3706266839
Short name T1956
Test name
Test status
Simulation time 10092337852 ps
CPU time 13.6 seconds
Started Jun 07 08:46:55 PM PDT 24
Finished Jun 07 08:47:13 PM PDT 24
Peak memory 205816 kb
Host smart-f6288cc6-3786-447d-a364-9801cdc1486b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37062
66839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3706266839
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1800558717
Short name T1324
Test name
Test status
Simulation time 10065014936 ps
CPU time 12.93 seconds
Started Jun 07 08:46:54 PM PDT 24
Finished Jun 07 08:47:12 PM PDT 24
Peak memory 205700 kb
Host smart-211cbe67-1305-4ed4-807b-f2899b5ee4af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18005
58717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1800558717
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.1000798619
Short name T1205
Test name
Test status
Simulation time 10081724052 ps
CPU time 14.1 seconds
Started Jun 07 08:46:51 PM PDT 24
Finished Jun 07 08:47:08 PM PDT 24
Peak memory 205876 kb
Host smart-37523698-c5af-47ee-b90a-99ac16fccb9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10007
98619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1000798619
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_eop_single_bit_handling.3269170556
Short name T810
Test name
Test status
Simulation time 10061800974 ps
CPU time 13.84 seconds
Started Jun 07 08:46:52 PM PDT 24
Finished Jun 07 08:47:09 PM PDT 24
Peak memory 205776 kb
Host smart-ae47784b-d3d7-4f92-8761-c99df8344fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32691
70556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_eop_single_bit_handling.3269170556
Directory /workspace/36.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.154654469
Short name T1339
Test name
Test status
Simulation time 10049542453 ps
CPU time 13.02 seconds
Started Jun 07 08:46:51 PM PDT 24
Finished Jun 07 08:47:07 PM PDT 24
Peak memory 205836 kb
Host smart-dc8437f5-2f2e-4325-8f47-fccc4254e67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15465
4469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.154654469
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.3069436580
Short name T1066
Test name
Test status
Simulation time 10035255106 ps
CPU time 13.68 seconds
Started Jun 07 08:46:53 PM PDT 24
Finished Jun 07 08:47:11 PM PDT 24
Peak memory 205804 kb
Host smart-a2a0d2eb-a840-4cda-8819-9238c813a8a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30694
36580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.3069436580
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.2121121793
Short name T1017
Test name
Test status
Simulation time 17329842702 ps
CPU time 30.13 seconds
Started Jun 07 08:46:52 PM PDT 24
Finished Jun 07 08:47:25 PM PDT 24
Peak memory 205796 kb
Host smart-6d36321b-110f-4f9e-a440-edbd00186fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21211
21793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.2121121793
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.378994582
Short name T420
Test name
Test status
Simulation time 10082371833 ps
CPU time 13.55 seconds
Started Jun 07 08:46:55 PM PDT 24
Finished Jun 07 08:47:12 PM PDT 24
Peak memory 205852 kb
Host smart-43b479f4-ffed-4aab-bf7b-620a92084382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37899
4582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.378994582
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1421144746
Short name T857
Test name
Test status
Simulation time 10158841920 ps
CPU time 13.58 seconds
Started Jun 07 08:46:55 PM PDT 24
Finished Jun 07 08:47:13 PM PDT 24
Peak memory 205864 kb
Host smart-752f5436-c5b8-4eef-93ec-ce52f31d38a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14211
44746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1421144746
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.4157195598
Short name T1659
Test name
Test status
Simulation time 10086487681 ps
CPU time 12.92 seconds
Started Jun 07 08:46:55 PM PDT 24
Finished Jun 07 08:47:13 PM PDT 24
Peak memory 205784 kb
Host smart-cbb8b5f8-4734-4015-9cf1-dfab2a123e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41571
95598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.4157195598
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.2066833294
Short name T299
Test name
Test status
Simulation time 10042436905 ps
CPU time 12.65 seconds
Started Jun 07 08:46:55 PM PDT 24
Finished Jun 07 08:47:12 PM PDT 24
Peak memory 205632 kb
Host smart-348b6770-182d-4d5a-883d-4b9d0add5f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20668
33294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.2066833294
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.1195823538
Short name T1421
Test name
Test status
Simulation time 10046465701 ps
CPU time 13.29 seconds
Started Jun 07 08:46:54 PM PDT 24
Finished Jun 07 08:47:11 PM PDT 24
Peak memory 205752 kb
Host smart-bba6073b-5051-4569-8a1e-a5eb0224281c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11958
23538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1195823538
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3707945775
Short name T1340
Test name
Test status
Simulation time 10051792775 ps
CPU time 13.47 seconds
Started Jun 07 08:46:49 PM PDT 24
Finished Jun 07 08:47:04 PM PDT 24
Peak memory 205892 kb
Host smart-77ba66f0-917a-4988-9d2f-cd668f4e0d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37079
45775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3707945775
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.1092949765
Short name T1955
Test name
Test status
Simulation time 10150458189 ps
CPU time 15.74 seconds
Started Jun 07 08:46:40 PM PDT 24
Finished Jun 07 08:47:00 PM PDT 24
Peak memory 205808 kb
Host smart-d2284c3a-1ee8-47b3-8a5e-44193eacbd62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10929
49765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.1092949765
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.1762635058
Short name T1685
Test name
Test status
Simulation time 10070406852 ps
CPU time 13.72 seconds
Started Jun 07 08:46:55 PM PDT 24
Finished Jun 07 08:47:13 PM PDT 24
Peak memory 205852 kb
Host smart-1b3edcb6-6757-43ae-b7bf-dd1dbc9c0616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17626
35058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.1762635058
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.220576297
Short name T1059
Test name
Test status
Simulation time 10144266819 ps
CPU time 15.45 seconds
Started Jun 07 08:46:54 PM PDT 24
Finished Jun 07 08:47:14 PM PDT 24
Peak memory 205792 kb
Host smart-40d2fb79-b8cf-47ac-852a-f6f1473452b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22057
6297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.220576297
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.3709092943
Short name T903
Test name
Test status
Simulation time 25444992515 ps
CPU time 158.3 seconds
Started Jun 07 08:46:56 PM PDT 24
Finished Jun 07 08:49:38 PM PDT 24
Peak memory 205876 kb
Host smart-5baaa115-d95f-4ac7-a8a4-1d0b29b851f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37090
92943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.3709092943
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.1542881593
Short name T1095
Test name
Test status
Simulation time 10167898296 ps
CPU time 13.15 seconds
Started Jun 07 08:47:00 PM PDT 24
Finished Jun 07 08:47:15 PM PDT 24
Peak memory 205768 kb
Host smart-916887d0-1e3f-42af-ac4c-7d62da1a234a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1542881593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.1542881593
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.1732147065
Short name T2007
Test name
Test status
Simulation time 10079634261 ps
CPU time 13.72 seconds
Started Jun 07 08:47:05 PM PDT 24
Finished Jun 07 08:47:20 PM PDT 24
Peak memory 205732 kb
Host smart-c465b2c9-b950-4816-8280-21b014b4a497
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1732147065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.1732147065
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.2942008257
Short name T2001
Test name
Test status
Simulation time 10068056811 ps
CPU time 14.06 seconds
Started Jun 07 08:47:02 PM PDT 24
Finished Jun 07 08:47:18 PM PDT 24
Peak memory 205848 kb
Host smart-2d97a836-ce1a-4ff1-b848-c5539e56b5d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29420
08257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.2942008257
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.1773776561
Short name T1271
Test name
Test status
Simulation time 13641208295 ps
CPU time 16.14 seconds
Started Jun 07 08:46:51 PM PDT 24
Finished Jun 07 08:47:10 PM PDT 24
Peak memory 205824 kb
Host smart-faa5d7ec-912b-485b-90b1-c3325ffbd061
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1773776561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.1773776561
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.784519521
Short name T1087
Test name
Test status
Simulation time 23261834990 ps
CPU time 24.44 seconds
Started Jun 07 08:46:54 PM PDT 24
Finished Jun 07 08:47:23 PM PDT 24
Peak memory 205820 kb
Host smart-d1e061b5-aad0-4617-ba7e-5f8b628a7ac0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=784519521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.784519521
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2489901470
Short name T1430
Test name
Test status
Simulation time 10061120364 ps
CPU time 13.55 seconds
Started Jun 07 08:46:51 PM PDT 24
Finished Jun 07 08:47:07 PM PDT 24
Peak memory 205732 kb
Host smart-dbeea8a4-34df-4c49-b035-cf043e35ff02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24899
01470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2489901470
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.990841980
Short name T739
Test name
Test status
Simulation time 10041696010 ps
CPU time 13.52 seconds
Started Jun 07 08:46:51 PM PDT 24
Finished Jun 07 08:47:07 PM PDT 24
Peak memory 205800 kb
Host smart-cc770175-f550-4737-ad43-5b7c8535b934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99084
1980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.990841980
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.2634364344
Short name T1346
Test name
Test status
Simulation time 10361895583 ps
CPU time 13.66 seconds
Started Jun 07 08:46:53 PM PDT 24
Finished Jun 07 08:47:11 PM PDT 24
Peak memory 205732 kb
Host smart-d63eb3ea-dfa2-4e7d-b72a-08e06c7106a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26343
64344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.2634364344
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_enable.1643374854
Short name T1183
Test name
Test status
Simulation time 10082559517 ps
CPU time 14.64 seconds
Started Jun 07 08:46:51 PM PDT 24
Finished Jun 07 08:47:08 PM PDT 24
Peak memory 205756 kb
Host smart-f40b4cfd-8dbd-4a21-9995-059c9b20e163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16433
74854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.1643374854
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.2094600233
Short name T717
Test name
Test status
Simulation time 10792295570 ps
CPU time 15.04 seconds
Started Jun 07 08:46:53 PM PDT 24
Finished Jun 07 08:47:13 PM PDT 24
Peak memory 205800 kb
Host smart-645b1e41-6872-4b8e-99e7-456dbb1aef59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20946
00233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.2094600233
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3277378329
Short name T182
Test name
Test status
Simulation time 10076779426 ps
CPU time 15.35 seconds
Started Jun 07 08:46:52 PM PDT 24
Finished Jun 07 08:47:11 PM PDT 24
Peak memory 205764 kb
Host smart-505b6d03-0076-47a2-ade5-ff37383ad18c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32773
78329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3277378329
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3593388216
Short name T729
Test name
Test status
Simulation time 10073783803 ps
CPU time 13.91 seconds
Started Jun 07 08:47:04 PM PDT 24
Finished Jun 07 08:47:20 PM PDT 24
Peak memory 205732 kb
Host smart-67f2e53e-176f-4dd1-b898-394ca6121e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35933
88216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3593388216
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.593535649
Short name T75
Test name
Test status
Simulation time 10042264065 ps
CPU time 14.5 seconds
Started Jun 07 08:47:01 PM PDT 24
Finished Jun 07 08:47:17 PM PDT 24
Peak memory 205760 kb
Host smart-b5f21d99-a9a8-4b5e-97c2-09d39951c37e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59353
5649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.593535649
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.2967041307
Short name T565
Test name
Test status
Simulation time 10109653155 ps
CPU time 13.33 seconds
Started Jun 07 08:46:50 PM PDT 24
Finished Jun 07 08:47:06 PM PDT 24
Peak memory 205744 kb
Host smart-a6a6f05d-18a1-45b6-a10e-a75e361f4879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29670
41307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.2967041307
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.2077618184
Short name T28
Test name
Test status
Simulation time 10072354257 ps
CPU time 12.75 seconds
Started Jun 07 08:46:55 PM PDT 24
Finished Jun 07 08:47:12 PM PDT 24
Peak memory 205672 kb
Host smart-517a222d-6aa9-4f7a-af71-b37b15f485e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20776
18184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.2077618184
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.1970105817
Short name T1401
Test name
Test status
Simulation time 13167125045 ps
CPU time 16.06 seconds
Started Jun 07 08:46:53 PM PDT 24
Finished Jun 07 08:47:13 PM PDT 24
Peak memory 205880 kb
Host smart-f4d915d6-0f88-403a-90a6-457516b56ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19701
05817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.1970105817
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.2340537297
Short name T1469
Test name
Test status
Simulation time 10135194074 ps
CPU time 15.59 seconds
Started Jun 07 08:46:52 PM PDT 24
Finished Jun 07 08:47:12 PM PDT 24
Peak memory 205728 kb
Host smart-a9bb4057-ba5a-4769-8606-c6577ed8ce0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23405
37297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.2340537297
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.3801211831
Short name T911
Test name
Test status
Simulation time 16513626664 ps
CPU time 188.1 seconds
Started Jun 07 08:46:51 PM PDT 24
Finished Jun 07 08:50:03 PM PDT 24
Peak memory 205792 kb
Host smart-aab52481-9482-4edf-a2ec-eb7be6f71122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38012
11831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.3801211831
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.2951380646
Short name T581
Test name
Test status
Simulation time 10040651921 ps
CPU time 13.46 seconds
Started Jun 07 08:46:49 PM PDT 24
Finished Jun 07 08:47:05 PM PDT 24
Peak memory 205736 kb
Host smart-8cff6c90-2246-4898-be95-d7b877fe1bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29513
80646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.2951380646
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.1964107147
Short name T94
Test name
Test status
Simulation time 10133831002 ps
CPU time 15.26 seconds
Started Jun 07 08:46:54 PM PDT 24
Finished Jun 07 08:47:13 PM PDT 24
Peak memory 205832 kb
Host smart-0a4169f6-8612-4290-bbec-c8315643bc3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19641
07147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.1964107147
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.3967019540
Short name T1869
Test name
Test status
Simulation time 10058379966 ps
CPU time 14.05 seconds
Started Jun 07 08:46:53 PM PDT 24
Finished Jun 07 08:47:11 PM PDT 24
Peak memory 205848 kb
Host smart-8b87638c-e1c8-4ce0-be9b-c93168fbf490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39670
19540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.3967019540
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.343973972
Short name T499
Test name
Test status
Simulation time 10082095851 ps
CPU time 14.76 seconds
Started Jun 07 08:46:53 PM PDT 24
Finished Jun 07 08:47:12 PM PDT 24
Peak memory 205692 kb
Host smart-53f39c6b-949b-4e21-a82c-f014f4727bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34397
3972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.343973972
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2558488184
Short name T1876
Test name
Test status
Simulation time 10092975553 ps
CPU time 13.29 seconds
Started Jun 07 08:47:02 PM PDT 24
Finished Jun 07 08:47:17 PM PDT 24
Peak memory 205768 kb
Host smart-734c94e5-f7e7-40f5-8ca8-f54c617ba603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25584
88184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2558488184
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.1307160050
Short name T1024
Test name
Test status
Simulation time 10053476661 ps
CPU time 12.82 seconds
Started Jun 07 08:46:54 PM PDT 24
Finished Jun 07 08:47:11 PM PDT 24
Peak memory 205776 kb
Host smart-b7e8f7f5-e87b-4cd0-828d-bac1fd7625b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13071
60050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.1307160050
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_eop_single_bit_handling.2867102837
Short name T1639
Test name
Test status
Simulation time 10100392371 ps
CPU time 15.77 seconds
Started Jun 07 08:46:53 PM PDT 24
Finished Jun 07 08:47:12 PM PDT 24
Peak memory 205816 kb
Host smart-722152b4-69ed-4390-9d6f-203eb8700fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28671
02837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_eop_single_bit_handling.2867102837
Directory /workspace/37.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.2243342401
Short name T880
Test name
Test status
Simulation time 10043804909 ps
CPU time 13.23 seconds
Started Jun 07 08:46:54 PM PDT 24
Finished Jun 07 08:47:11 PM PDT 24
Peak memory 205780 kb
Host smart-08444cc9-141b-4d8a-9230-3bb83bc968b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22433
42401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.2243342401
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.145016773
Short name T1209
Test name
Test status
Simulation time 10042745819 ps
CPU time 12.89 seconds
Started Jun 07 08:46:55 PM PDT 24
Finished Jun 07 08:47:12 PM PDT 24
Peak memory 205768 kb
Host smart-7094da93-2d04-4f5b-bb61-a1411de3e4aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14501
6773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.145016773
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.2993860648
Short name T675
Test name
Test status
Simulation time 20382876723 ps
CPU time 39.32 seconds
Started Jun 07 08:46:54 PM PDT 24
Finished Jun 07 08:47:38 PM PDT 24
Peak memory 205788 kb
Host smart-3830d2a2-6886-41a8-a96f-1698950c13a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29938
60648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.2993860648
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3399001120
Short name T558
Test name
Test status
Simulation time 10100312189 ps
CPU time 13.7 seconds
Started Jun 07 08:46:54 PM PDT 24
Finished Jun 07 08:47:12 PM PDT 24
Peak memory 205720 kb
Host smart-2a66e408-5b0f-4a35-8cb7-26edde6ba299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33990
01120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3399001120
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.782741613
Short name T651
Test name
Test status
Simulation time 10113893520 ps
CPU time 12.99 seconds
Started Jun 07 08:46:58 PM PDT 24
Finished Jun 07 08:47:14 PM PDT 24
Peak memory 205712 kb
Host smart-b6c74bb6-69b9-448c-a174-1a796dfe1f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78274
1613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.782741613
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.2265113318
Short name T754
Test name
Test status
Simulation time 10113672009 ps
CPU time 12.56 seconds
Started Jun 07 08:47:00 PM PDT 24
Finished Jun 07 08:47:14 PM PDT 24
Peak memory 205720 kb
Host smart-cdc74de1-6145-4dce-99da-508616105224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22651
13318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.2265113318
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.2472166005
Short name T48
Test name
Test status
Simulation time 10049766435 ps
CPU time 13.18 seconds
Started Jun 07 08:46:54 PM PDT 24
Finished Jun 07 08:47:12 PM PDT 24
Peak memory 205828 kb
Host smart-b5144228-404d-421a-9d8e-0b25d5a822d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24721
66005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.2472166005
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.40842992
Short name T144
Test name
Test status
Simulation time 10046533704 ps
CPU time 12.4 seconds
Started Jun 07 08:46:54 PM PDT 24
Finished Jun 07 08:47:10 PM PDT 24
Peak memory 205808 kb
Host smart-bfeb033d-5b9c-49d2-95fc-c1f7e214950b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40842
992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.40842992
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2163883135
Short name T484
Test name
Test status
Simulation time 10084987897 ps
CPU time 14.39 seconds
Started Jun 07 08:46:52 PM PDT 24
Finished Jun 07 08:47:11 PM PDT 24
Peak memory 205864 kb
Host smart-9d8c2164-42f7-4c43-ab72-111ce2b31d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21638
83135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2163883135
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.3647927017
Short name T1743
Test name
Test status
Simulation time 10142042889 ps
CPU time 15.42 seconds
Started Jun 07 08:46:54 PM PDT 24
Finished Jun 07 08:47:14 PM PDT 24
Peak memory 205780 kb
Host smart-83b0725b-4385-490d-ba90-e26c4b379f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36479
27017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3647927017
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.3286115868
Short name T1427
Test name
Test status
Simulation time 10070661471 ps
CPU time 13.41 seconds
Started Jun 07 08:46:54 PM PDT 24
Finished Jun 07 08:47:11 PM PDT 24
Peak memory 205804 kb
Host smart-1c704c90-1f1e-4f30-b634-859f493944ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32861
15868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.3286115868
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.4276920519
Short name T1575
Test name
Test status
Simulation time 10054287700 ps
CPU time 12.55 seconds
Started Jun 07 08:46:52 PM PDT 24
Finished Jun 07 08:47:08 PM PDT 24
Peak memory 205876 kb
Host smart-827aa7ac-56f4-48be-9ccf-41274dc0982f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42769
20519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.4276920519
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.3815957873
Short name T380
Test name
Test status
Simulation time 21731988073 ps
CPU time 92.06 seconds
Started Jun 07 08:46:56 PM PDT 24
Finished Jun 07 08:48:32 PM PDT 24
Peak memory 205796 kb
Host smart-71c77a25-12a3-4243-bdb0-141c284f98ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38159
57873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.3815957873
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.3147144149
Short name T488
Test name
Test status
Simulation time 10223684581 ps
CPU time 14.87 seconds
Started Jun 07 08:47:05 PM PDT 24
Finished Jun 07 08:47:22 PM PDT 24
Peak memory 205840 kb
Host smart-a6ad4922-a78b-4d1c-b7e8-a8c7220472b5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3147144149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.3147144149
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.3445891240
Short name T1680
Test name
Test status
Simulation time 10054224528 ps
CPU time 12.79 seconds
Started Jun 07 08:47:07 PM PDT 24
Finished Jun 07 08:47:21 PM PDT 24
Peak memory 205876 kb
Host smart-5b861cde-c688-4667-bdca-c0f1af4bf323
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3445891240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.3445891240
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.4193493206
Short name T522
Test name
Test status
Simulation time 10084901586 ps
CPU time 13.47 seconds
Started Jun 07 08:47:02 PM PDT 24
Finished Jun 07 08:47:18 PM PDT 24
Peak memory 205808 kb
Host smart-ab15d7c3-a32d-4132-8713-8730d5070fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41934
93206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.4193493206
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.1831507348
Short name T1046
Test name
Test status
Simulation time 23239566602 ps
CPU time 27.16 seconds
Started Jun 07 08:46:51 PM PDT 24
Finished Jun 07 08:47:21 PM PDT 24
Peak memory 205824 kb
Host smart-76f6c399-c0ab-434b-9338-35bdd5f33124
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1831507348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.1831507348
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3869236738
Short name T1874
Test name
Test status
Simulation time 10072627181 ps
CPU time 15.56 seconds
Started Jun 07 08:47:04 PM PDT 24
Finished Jun 07 08:47:22 PM PDT 24
Peak memory 205732 kb
Host smart-4b80a675-775a-4361-8142-01d1402c9520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38692
36738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3869236738
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.84649158
Short name T60
Test name
Test status
Simulation time 10061896999 ps
CPU time 12.89 seconds
Started Jun 07 08:47:03 PM PDT 24
Finished Jun 07 08:47:18 PM PDT 24
Peak memory 205744 kb
Host smart-a332371a-5f12-4e35-bfa8-9d283be34bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84649
158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.84649158
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.4042040532
Short name T169
Test name
Test status
Simulation time 11098231169 ps
CPU time 17.81 seconds
Started Jun 07 08:47:05 PM PDT 24
Finished Jun 07 08:47:24 PM PDT 24
Peak memory 205832 kb
Host smart-b86462d6-1faa-4d7b-a5d2-1751a52b76a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40420
40532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.4042040532
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.2936520246
Short name T437
Test name
Test status
Simulation time 10051073963 ps
CPU time 15.12 seconds
Started Jun 07 08:47:03 PM PDT 24
Finished Jun 07 08:47:20 PM PDT 24
Peak memory 205828 kb
Host smart-7ea96165-5ae0-471e-aa63-4da4d57e1def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29365
20246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.2936520246
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.3389916280
Short name T1990
Test name
Test status
Simulation time 10102404762 ps
CPU time 13.2 seconds
Started Jun 07 08:47:00 PM PDT 24
Finished Jun 07 08:47:15 PM PDT 24
Peak memory 205816 kb
Host smart-3ae9bae2-cad8-4146-a64f-0e8f54bfeaa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33899
16280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.3389916280
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.3093715190
Short name T1837
Test name
Test status
Simulation time 10651954109 ps
CPU time 16.63 seconds
Started Jun 07 08:47:03 PM PDT 24
Finished Jun 07 08:47:21 PM PDT 24
Peak memory 205852 kb
Host smart-8ac008d5-26ba-41a2-a32f-36ac40c4e127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30937
15190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.3093715190
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.207011122
Short name T1460
Test name
Test status
Simulation time 10174097557 ps
CPU time 15.64 seconds
Started Jun 07 08:46:57 PM PDT 24
Finished Jun 07 08:47:17 PM PDT 24
Peak memory 205788 kb
Host smart-d61c842b-7883-42bd-8cbf-7c60013216dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20701
1122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.207011122
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.3676009315
Short name T1280
Test name
Test status
Simulation time 10079409985 ps
CPU time 14.36 seconds
Started Jun 07 08:47:01 PM PDT 24
Finished Jun 07 08:47:18 PM PDT 24
Peak memory 205844 kb
Host smart-0377a1af-c3a7-4af1-b85c-5cda399d55c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36760
09315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.3676009315
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.2178393110
Short name T653
Test name
Test status
Simulation time 10041969231 ps
CPU time 13.45 seconds
Started Jun 07 08:47:08 PM PDT 24
Finished Jun 07 08:47:24 PM PDT 24
Peak memory 205764 kb
Host smart-6ae6e152-aa6b-4d47-8382-8bcbd5a42bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21783
93110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.2178393110
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.4294933710
Short name T1540
Test name
Test status
Simulation time 10072252542 ps
CPU time 14.57 seconds
Started Jun 07 08:46:59 PM PDT 24
Finished Jun 07 08:47:16 PM PDT 24
Peak memory 205876 kb
Host smart-af8e7292-9fda-452a-88c4-2b537b23c7aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42949
33710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.4294933710
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.65483836
Short name T871
Test name
Test status
Simulation time 10086407311 ps
CPU time 16.2 seconds
Started Jun 07 08:47:02 PM PDT 24
Finished Jun 07 08:47:20 PM PDT 24
Peak memory 205796 kb
Host smart-561fcb7d-2cfc-42a2-8207-6f4566deff77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65483
836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.65483836
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.1835394834
Short name T1195
Test name
Test status
Simulation time 13202528400 ps
CPU time 18.75 seconds
Started Jun 07 08:47:01 PM PDT 24
Finished Jun 07 08:47:22 PM PDT 24
Peak memory 205948 kb
Host smart-a049d6f6-32b9-43d0-a0cd-7e9a5282a2f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18353
94834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.1835394834
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.2095089444
Short name T1562
Test name
Test status
Simulation time 10112272143 ps
CPU time 14.61 seconds
Started Jun 07 08:47:01 PM PDT 24
Finished Jun 07 08:47:18 PM PDT 24
Peak memory 205780 kb
Host smart-24de450b-ef71-4ea7-9758-0ac1930d9221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20950
89444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.2095089444
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.1118004817
Short name T1487
Test name
Test status
Simulation time 15879990817 ps
CPU time 53.72 seconds
Started Jun 07 08:47:01 PM PDT 24
Finished Jun 07 08:47:57 PM PDT 24
Peak memory 205844 kb
Host smart-0bf67fd2-22b4-414e-9ae6-762327c5973c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11180
04817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.1118004817
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.413424030
Short name T1237
Test name
Test status
Simulation time 10059883597 ps
CPU time 13.35 seconds
Started Jun 07 08:47:01 PM PDT 24
Finished Jun 07 08:47:16 PM PDT 24
Peak memory 205860 kb
Host smart-58f6e955-797b-49d8-a7e3-f9805cc6d303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41342
4030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.413424030
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2090082696
Short name T90
Test name
Test status
Simulation time 10110380762 ps
CPU time 14.32 seconds
Started Jun 07 08:47:02 PM PDT 24
Finished Jun 07 08:47:19 PM PDT 24
Peak memory 205812 kb
Host smart-3c725cea-409a-476d-9c74-252fa99064c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20900
82696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2090082696
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.478358767
Short name T1250
Test name
Test status
Simulation time 10098825516 ps
CPU time 15.53 seconds
Started Jun 07 08:47:03 PM PDT 24
Finished Jun 07 08:47:20 PM PDT 24
Peak memory 205868 kb
Host smart-5e93cc72-3090-4952-9483-5e6c67bcd919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47835
8767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.478358767
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.3361499645
Short name T494
Test name
Test status
Simulation time 10065832593 ps
CPU time 13.82 seconds
Started Jun 07 08:47:13 PM PDT 24
Finished Jun 07 08:47:29 PM PDT 24
Peak memory 205756 kb
Host smart-ed2af906-2ac4-4f42-8c25-bef1579144e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33614
99645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3361499645
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.730244247
Short name T1104
Test name
Test status
Simulation time 10071614223 ps
CPU time 15.19 seconds
Started Jun 07 08:47:06 PM PDT 24
Finished Jun 07 08:47:23 PM PDT 24
Peak memory 205884 kb
Host smart-2d8a410b-3228-4332-a981-9b07ec397fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73024
4247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.730244247
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.3944855667
Short name T1107
Test name
Test status
Simulation time 10062770917 ps
CPU time 12.92 seconds
Started Jun 07 08:47:04 PM PDT 24
Finished Jun 07 08:47:18 PM PDT 24
Peak memory 205860 kb
Host smart-937f37f9-f861-4282-829a-24f64ab5a15b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39448
55667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.3944855667
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_eop_single_bit_handling.1719076016
Short name T1179
Test name
Test status
Simulation time 10047827150 ps
CPU time 13.55 seconds
Started Jun 07 08:47:03 PM PDT 24
Finished Jun 07 08:47:19 PM PDT 24
Peak memory 205668 kb
Host smart-f452db01-87f2-474f-be00-c0b5bf121f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17190
76016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_eop_single_bit_handling.1719076016
Directory /workspace/38.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.794746719
Short name T1013
Test name
Test status
Simulation time 10118353031 ps
CPU time 13.32 seconds
Started Jun 07 08:47:04 PM PDT 24
Finished Jun 07 08:47:19 PM PDT 24
Peak memory 205900 kb
Host smart-1d07deb4-56d8-4d06-bbea-1463638bd572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79474
6719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.794746719
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.381677770
Short name T1665
Test name
Test status
Simulation time 10035649586 ps
CPU time 13.81 seconds
Started Jun 07 08:47:02 PM PDT 24
Finished Jun 07 08:47:17 PM PDT 24
Peak memory 205796 kb
Host smart-c56ba9b9-5c59-4612-8256-dc13666f1880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38167
7770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.381677770
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.3031365892
Short name T1241
Test name
Test status
Simulation time 25410984391 ps
CPU time 48.62 seconds
Started Jun 07 08:47:07 PM PDT 24
Finished Jun 07 08:47:57 PM PDT 24
Peak memory 205788 kb
Host smart-91087f34-ff27-4602-ae19-7ab97be34842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30313
65892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.3031365892
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.3425093516
Short name T1760
Test name
Test status
Simulation time 10056405528 ps
CPU time 13.64 seconds
Started Jun 07 08:47:07 PM PDT 24
Finished Jun 07 08:47:23 PM PDT 24
Peak memory 205796 kb
Host smart-21684433-b66d-43a2-93dd-5306630f3e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34250
93516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3425093516
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1268669614
Short name T1131
Test name
Test status
Simulation time 10192807033 ps
CPU time 14.2 seconds
Started Jun 07 08:47:07 PM PDT 24
Finished Jun 07 08:47:23 PM PDT 24
Peak memory 205868 kb
Host smart-149e18c1-1252-41ac-9bf6-a052125bbfbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12686
69614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1268669614
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.2983829408
Short name T448
Test name
Test status
Simulation time 10076643819 ps
CPU time 15.57 seconds
Started Jun 07 08:47:07 PM PDT 24
Finished Jun 07 08:47:25 PM PDT 24
Peak memory 205796 kb
Host smart-980f8152-e2ce-4303-8504-515495cc43c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29838
29408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.2983829408
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.1310777579
Short name T1295
Test name
Test status
Simulation time 10076327741 ps
CPU time 13.65 seconds
Started Jun 07 08:47:01 PM PDT 24
Finished Jun 07 08:47:17 PM PDT 24
Peak memory 205844 kb
Host smart-4f7e129a-d376-42e5-bcd0-755d2dc257fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13107
77579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.1310777579
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.1336388464
Short name T1204
Test name
Test status
Simulation time 10055477848 ps
CPU time 13.27 seconds
Started Jun 07 08:47:04 PM PDT 24
Finished Jun 07 08:47:19 PM PDT 24
Peak memory 205752 kb
Host smart-cdf820a4-abc3-4cba-a37d-d9a61d341fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13363
88464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.1336388464
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.3355392237
Short name T1630
Test name
Test status
Simulation time 10067910510 ps
CPU time 13.18 seconds
Started Jun 07 08:47:07 PM PDT 24
Finished Jun 07 08:47:23 PM PDT 24
Peak memory 205832 kb
Host smart-5a57257b-6336-4e18-8562-12283310f62a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33553
92237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.3355392237
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.2239529955
Short name T1991
Test name
Test status
Simulation time 10140466055 ps
CPU time 13.6 seconds
Started Jun 07 08:46:55 PM PDT 24
Finished Jun 07 08:47:13 PM PDT 24
Peak memory 205836 kb
Host smart-6bca56db-d580-4052-9394-fff35cc2b969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22395
29955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.2239529955
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.1104547960
Short name T426
Test name
Test status
Simulation time 10069302729 ps
CPU time 16.01 seconds
Started Jun 07 08:47:07 PM PDT 24
Finished Jun 07 08:47:25 PM PDT 24
Peak memory 205704 kb
Host smart-a9633f1e-632a-46d2-82d9-4a70072c5d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11045
47960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.1104547960
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.1108011565
Short name T353
Test name
Test status
Simulation time 10096889301 ps
CPU time 13.27 seconds
Started Jun 07 08:47:05 PM PDT 24
Finished Jun 07 08:47:20 PM PDT 24
Peak memory 205744 kb
Host smart-5e8c8e19-c90b-4269-a656-beb243ef8a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11080
11565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1108011565
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.3417213764
Short name T556
Test name
Test status
Simulation time 23995823665 ps
CPU time 150.51 seconds
Started Jun 07 08:47:07 PM PDT 24
Finished Jun 07 08:49:39 PM PDT 24
Peak memory 205840 kb
Host smart-bb752936-ecd6-40e0-b024-5733277c5cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34172
13764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.3417213764
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.1474439652
Short name T1506
Test name
Test status
Simulation time 10187650897 ps
CPU time 13.9 seconds
Started Jun 07 08:47:15 PM PDT 24
Finished Jun 07 08:47:31 PM PDT 24
Peak memory 205756 kb
Host smart-d430c30d-4d3b-4df8-9b0e-13890eb9482a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1474439652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.1474439652
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.1717798933
Short name T1408
Test name
Test status
Simulation time 10062221955 ps
CPU time 13.24 seconds
Started Jun 07 08:47:09 PM PDT 24
Finished Jun 07 08:47:26 PM PDT 24
Peak memory 205900 kb
Host smart-fdbd46e9-2a11-4712-af95-b973bee48db1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1717798933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.1717798933
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.2717560112
Short name T289
Test name
Test status
Simulation time 10080367197 ps
CPU time 13.11 seconds
Started Jun 07 08:47:10 PM PDT 24
Finished Jun 07 08:47:26 PM PDT 24
Peak memory 205852 kb
Host smart-05d90136-c8cc-45f8-95ea-ac7debd9c5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27175
60112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.2717560112
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.1491429554
Short name T1434
Test name
Test status
Simulation time 13924417176 ps
CPU time 17.4 seconds
Started Jun 07 08:47:06 PM PDT 24
Finished Jun 07 08:47:25 PM PDT 24
Peak memory 205880 kb
Host smart-689f6e95-a4b0-49ff-9285-b1dcf108421f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1491429554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.1491429554
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.864869436
Short name T391
Test name
Test status
Simulation time 23290945366 ps
CPU time 29.35 seconds
Started Jun 07 08:47:03 PM PDT 24
Finished Jun 07 08:47:35 PM PDT 24
Peak memory 205896 kb
Host smart-69f4367b-e89a-436d-8eb5-879049cf2d96
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=864869436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.864869436
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1869890155
Short name T755
Test name
Test status
Simulation time 10072802159 ps
CPU time 14.97 seconds
Started Jun 07 08:47:03 PM PDT 24
Finished Jun 07 08:47:20 PM PDT 24
Peak memory 205792 kb
Host smart-6710758c-f250-4904-abcc-554e2658b8f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18698
90155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1869890155
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.3895297757
Short name T58
Test name
Test status
Simulation time 10076006379 ps
CPU time 14.16 seconds
Started Jun 07 08:47:13 PM PDT 24
Finished Jun 07 08:47:29 PM PDT 24
Peak memory 205772 kb
Host smart-72c7768f-d5de-40bd-bf7d-adb3f1b40f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38952
97757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.3895297757
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.4147904609
Short name T1806
Test name
Test status
Simulation time 10379066139 ps
CPU time 15.54 seconds
Started Jun 07 08:47:08 PM PDT 24
Finished Jun 07 08:47:25 PM PDT 24
Peak memory 205780 kb
Host smart-662ef3db-12e9-4b50-87a3-03ca2ea7968a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41479
04609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.4147904609
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.2933477506
Short name T957
Test name
Test status
Simulation time 10044177822 ps
CPU time 16.11 seconds
Started Jun 07 08:47:08 PM PDT 24
Finished Jun 07 08:47:27 PM PDT 24
Peak memory 205848 kb
Host smart-400f96a0-24b6-4af1-ac8f-4a88cffd3c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29334
77506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.2933477506
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.670591951
Short name T1981
Test name
Test status
Simulation time 10065456925 ps
CPU time 13.33 seconds
Started Jun 07 08:47:07 PM PDT 24
Finished Jun 07 08:47:22 PM PDT 24
Peak memory 205732 kb
Host smart-ac9c7129-7e9c-4fea-8798-468416c27b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67059
1951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.670591951
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.4200115804
Short name T1983
Test name
Test status
Simulation time 10815111930 ps
CPU time 15.01 seconds
Started Jun 07 08:47:13 PM PDT 24
Finished Jun 07 08:47:30 PM PDT 24
Peak memory 205760 kb
Host smart-48b16be7-9808-4301-b599-d2a80413c293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42001
15804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.4200115804
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.1950268399
Short name T1848
Test name
Test status
Simulation time 10210471774 ps
CPU time 14.67 seconds
Started Jun 07 08:47:06 PM PDT 24
Finished Jun 07 08:47:23 PM PDT 24
Peak memory 205844 kb
Host smart-71ce997e-4170-495d-aec5-479f0413dc97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19502
68399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.1950268399
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.1549281694
Short name T1604
Test name
Test status
Simulation time 10133912612 ps
CPU time 14.74 seconds
Started Jun 07 08:47:23 PM PDT 24
Finished Jun 07 08:47:40 PM PDT 24
Peak memory 205796 kb
Host smart-14e93cee-1525-49e1-9661-7e43ea87488c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15492
81694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.1549281694
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.638980099
Short name T1902
Test name
Test status
Simulation time 10038350551 ps
CPU time 16.48 seconds
Started Jun 07 08:47:10 PM PDT 24
Finished Jun 07 08:47:30 PM PDT 24
Peak memory 205844 kb
Host smart-f2165f0f-1a67-40fd-b791-ee2810f258ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63898
0099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.638980099
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.863064196
Short name T1208
Test name
Test status
Simulation time 10128798822 ps
CPU time 14.17 seconds
Started Jun 07 08:47:03 PM PDT 24
Finished Jun 07 08:47:19 PM PDT 24
Peak memory 205768 kb
Host smart-51681cbd-2d4a-4404-bebb-64e6b8353b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86306
4196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.863064196
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.4201989662
Short name T956
Test name
Test status
Simulation time 10084491010 ps
CPU time 13.19 seconds
Started Jun 07 08:47:03 PM PDT 24
Finished Jun 07 08:47:18 PM PDT 24
Peak memory 205728 kb
Host smart-75be4409-b329-428a-bdf3-8995cad32a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42019
89662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.4201989662
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.1950345566
Short name T801
Test name
Test status
Simulation time 13155972164 ps
CPU time 16.98 seconds
Started Jun 07 08:47:14 PM PDT 24
Finished Jun 07 08:47:32 PM PDT 24
Peak memory 205852 kb
Host smart-9374c3cc-a8ec-49cf-abbd-7df827f43f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19503
45566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.1950345566
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.3857757039
Short name T1397
Test name
Test status
Simulation time 10087594953 ps
CPU time 12.68 seconds
Started Jun 07 08:47:09 PM PDT 24
Finished Jun 07 08:47:25 PM PDT 24
Peak memory 205784 kb
Host smart-a4192eee-a121-422b-a4c1-ac7916a69064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38577
57039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.3857757039
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.3889094001
Short name T313
Test name
Test status
Simulation time 20480776782 ps
CPU time 85.18 seconds
Started Jun 07 08:47:09 PM PDT 24
Finished Jun 07 08:48:37 PM PDT 24
Peak memory 205920 kb
Host smart-7a5ba800-a6ad-48fb-b22f-bbc1ededd6c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38890
94001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.3889094001
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3214663568
Short name T1825
Test name
Test status
Simulation time 10050852689 ps
CPU time 13.92 seconds
Started Jun 07 08:47:10 PM PDT 24
Finished Jun 07 08:47:27 PM PDT 24
Peak memory 205764 kb
Host smart-b08a5d6e-49e9-4c3e-9734-b6c4c9d6609f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32146
63568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3214663568
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3111795757
Short name T122
Test name
Test status
Simulation time 10071001363 ps
CPU time 13.22 seconds
Started Jun 07 08:47:09 PM PDT 24
Finished Jun 07 08:47:25 PM PDT 24
Peak memory 205944 kb
Host smart-a6f78de5-85d4-4dac-b4da-28609ce6a157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31117
95757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3111795757
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.1831616654
Short name T1811
Test name
Test status
Simulation time 10056174530 ps
CPU time 13.39 seconds
Started Jun 07 08:47:09 PM PDT 24
Finished Jun 07 08:47:26 PM PDT 24
Peak memory 205704 kb
Host smart-5bd026cc-34ec-481c-9677-923e22201804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18316
16654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.1831616654
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1161683261
Short name T1683
Test name
Test status
Simulation time 10109195807 ps
CPU time 14.44 seconds
Started Jun 07 08:47:08 PM PDT 24
Finished Jun 07 08:47:24 PM PDT 24
Peak memory 205856 kb
Host smart-a4f497f7-b727-4165-9fe2-1caa738ddaad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11616
83261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1161683261
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.4051566261
Short name T2026
Test name
Test status
Simulation time 10094494164 ps
CPU time 13.24 seconds
Started Jun 07 08:47:07 PM PDT 24
Finished Jun 07 08:47:22 PM PDT 24
Peak memory 205880 kb
Host smart-00c89254-b5b8-4ae5-a6f8-78d0fcb0d009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40515
66261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.4051566261
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.3108008622
Short name T1202
Test name
Test status
Simulation time 10071418070 ps
CPU time 13.33 seconds
Started Jun 07 08:47:10 PM PDT 24
Finished Jun 07 08:47:26 PM PDT 24
Peak memory 205812 kb
Host smart-1b2630cb-1704-42a6-b2eb-2c44957ba74c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31080
08622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.3108008622
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_eop_single_bit_handling.3707461916
Short name T1819
Test name
Test status
Simulation time 10122504328 ps
CPU time 13.81 seconds
Started Jun 07 08:47:14 PM PDT 24
Finished Jun 07 08:47:29 PM PDT 24
Peak memory 205888 kb
Host smart-eb52d47c-becd-4c9a-9bc0-068982b2ad2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37074
61916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_eop_single_bit_handling.3707461916
Directory /workspace/39.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1691324207
Short name T915
Test name
Test status
Simulation time 10046873818 ps
CPU time 14.76 seconds
Started Jun 07 08:47:09 PM PDT 24
Finished Jun 07 08:47:26 PM PDT 24
Peak memory 205720 kb
Host smart-5e403806-4139-4f5f-910d-de8ee568a6f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16913
24207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.1691324207
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.2015086733
Short name T943
Test name
Test status
Simulation time 10042919065 ps
CPU time 14.24 seconds
Started Jun 07 08:47:07 PM PDT 24
Finished Jun 07 08:47:24 PM PDT 24
Peak memory 205804 kb
Host smart-ddcb82f0-f76b-4ac0-a9ac-c4ecedd095a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20150
86733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.2015086733
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.1513763947
Short name T1846
Test name
Test status
Simulation time 21673784318 ps
CPU time 37.94 seconds
Started Jun 07 08:47:10 PM PDT 24
Finished Jun 07 08:47:51 PM PDT 24
Peak memory 205804 kb
Host smart-9ecf5f8b-7f5b-4768-a75a-9edf5ebbb561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15137
63947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.1513763947
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.2303636271
Short name T1966
Test name
Test status
Simulation time 10061698763 ps
CPU time 12.87 seconds
Started Jun 07 08:47:09 PM PDT 24
Finished Jun 07 08:47:25 PM PDT 24
Peak memory 205832 kb
Host smart-dd45a017-8fde-4b5c-ab4b-c48079f3c5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23036
36271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2303636271
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1092706476
Short name T446
Test name
Test status
Simulation time 10105513686 ps
CPU time 14.42 seconds
Started Jun 07 08:47:10 PM PDT 24
Finished Jun 07 08:47:27 PM PDT 24
Peak memory 205692 kb
Host smart-28bbc635-5abb-46e7-a7b8-00ba49504855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10927
06476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1092706476
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.3692557837
Short name T1661
Test name
Test status
Simulation time 10091722065 ps
CPU time 16.02 seconds
Started Jun 07 08:47:09 PM PDT 24
Finished Jun 07 08:47:27 PM PDT 24
Peak memory 205804 kb
Host smart-8e681e85-158a-4b34-abad-936d3a84ea5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36925
57837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.3692557837
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.415013956
Short name T1905
Test name
Test status
Simulation time 10037809737 ps
CPU time 12.77 seconds
Started Jun 07 08:47:11 PM PDT 24
Finished Jun 07 08:47:26 PM PDT 24
Peak memory 205756 kb
Host smart-2bfe509f-d9af-488f-8cd0-408e2155a2f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41501
3956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.415013956
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.2981497502
Short name T910
Test name
Test status
Simulation time 10060920692 ps
CPU time 13.53 seconds
Started Jun 07 08:47:11 PM PDT 24
Finished Jun 07 08:47:27 PM PDT 24
Peak memory 205716 kb
Host smart-a521928d-a1f7-47ac-baf4-7c163e8809e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29814
97502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.2981497502
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.3766022315
Short name T1629
Test name
Test status
Simulation time 10057663763 ps
CPU time 12.46 seconds
Started Jun 07 08:47:11 PM PDT 24
Finished Jun 07 08:47:27 PM PDT 24
Peak memory 205836 kb
Host smart-eb0dd67a-8c69-424d-9ac2-f0c144d72d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37660
22315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.3766022315
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.328732769
Short name T1402
Test name
Test status
Simulation time 10136229629 ps
CPU time 13.73 seconds
Started Jun 07 08:47:13 PM PDT 24
Finished Jun 07 08:47:29 PM PDT 24
Peak memory 205880 kb
Host smart-c2b59e62-b2e3-40b6-ae9a-c65e85e9b8ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32873
2769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.328732769
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.1177158294
Short name T599
Test name
Test status
Simulation time 10078677061 ps
CPU time 14.88 seconds
Started Jun 07 08:47:11 PM PDT 24
Finished Jun 07 08:47:29 PM PDT 24
Peak memory 205844 kb
Host smart-e77d717d-7cd8-4975-9502-7fe5b3bf682c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11771
58294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.1177158294
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1122629836
Short name T595
Test name
Test status
Simulation time 10074703086 ps
CPU time 16.77 seconds
Started Jun 07 08:47:12 PM PDT 24
Finished Jun 07 08:47:31 PM PDT 24
Peak memory 205800 kb
Host smart-d145b3b7-075c-436f-8538-b31529db42b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11226
29836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1122629836
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.3163240591
Short name T946
Test name
Test status
Simulation time 22485493959 ps
CPU time 134.03 seconds
Started Jun 07 08:47:13 PM PDT 24
Finished Jun 07 08:49:29 PM PDT 24
Peak memory 205880 kb
Host smart-9cc08e58-ab5a-4b8c-9a74-c35ab1302026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31632
40591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.3163240591
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.2964097954
Short name T1052
Test name
Test status
Simulation time 10147728468 ps
CPU time 13.13 seconds
Started Jun 07 08:41:47 PM PDT 24
Finished Jun 07 08:42:04 PM PDT 24
Peak memory 205832 kb
Host smart-93eeb454-74fa-495a-9350-297fca6ee3db
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2964097954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.2964097954
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.4290274130
Short name T637
Test name
Test status
Simulation time 10065922689 ps
CPU time 15.06 seconds
Started Jun 07 08:41:46 PM PDT 24
Finished Jun 07 08:42:04 PM PDT 24
Peak memory 205752 kb
Host smart-243fb094-f669-432c-b36d-23e89e84da4f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4290274130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.4290274130
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.2885098597
Short name T1472
Test name
Test status
Simulation time 10134517632 ps
CPU time 14.09 seconds
Started Jun 07 08:41:47 PM PDT 24
Finished Jun 07 08:42:04 PM PDT 24
Peak memory 205840 kb
Host smart-6febd5c1-7fe0-42d9-aa8a-9ed6643084cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28850
98597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.2885098597
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.2717711016
Short name T1070
Test name
Test status
Simulation time 14042017366 ps
CPU time 17.51 seconds
Started Jun 07 08:41:29 PM PDT 24
Finished Jun 07 08:41:49 PM PDT 24
Peak memory 205880 kb
Host smart-37a6e88f-60b9-4d66-9cdc-bdb381294b47
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2717711016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.2717711016
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.420666634
Short name T1221
Test name
Test status
Simulation time 23287393762 ps
CPU time 23.55 seconds
Started Jun 07 08:41:29 PM PDT 24
Finished Jun 07 08:41:55 PM PDT 24
Peak memory 205820 kb
Host smart-e7263b52-1500-4eac-9249-9098f3e031c2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=420666634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.420666634
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.3208938013
Short name T616
Test name
Test status
Simulation time 10126949146 ps
CPU time 15.93 seconds
Started Jun 07 08:41:29 PM PDT 24
Finished Jun 07 08:41:48 PM PDT 24
Peak memory 205820 kb
Host smart-637dbbcf-d5b3-41ef-a318-02fe1d3cfcd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32089
38013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3208938013
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.603763917
Short name T1136
Test name
Test status
Simulation time 10769841971 ps
CPU time 15.45 seconds
Started Jun 07 08:41:35 PM PDT 24
Finished Jun 07 08:41:52 PM PDT 24
Peak memory 205756 kb
Host smart-a901aee0-006b-457e-ab1d-3bd60857af9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60376
3917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.603763917
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.688557237
Short name T734
Test name
Test status
Simulation time 10051661430 ps
CPU time 12.03 seconds
Started Jun 07 08:41:33 PM PDT 24
Finished Jun 07 08:41:47 PM PDT 24
Peak memory 205836 kb
Host smart-cd0bda77-713e-4fcf-adf9-c5815c753e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68855
7237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.688557237
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.3473021132
Short name T940
Test name
Test status
Simulation time 10052121563 ps
CPU time 15.42 seconds
Started Jun 07 08:41:34 PM PDT 24
Finished Jun 07 08:41:51 PM PDT 24
Peak memory 205784 kb
Host smart-85195430-5a54-404c-8e67-b95af8a340e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34730
21132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.3473021132
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.3592669359
Short name T850
Test name
Test status
Simulation time 10741019330 ps
CPU time 13.83 seconds
Started Jun 07 08:41:35 PM PDT 24
Finished Jun 07 08:41:51 PM PDT 24
Peak memory 205748 kb
Host smart-4103fd2e-005b-41f5-aea6-45a4010dc517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35926
69359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.3592669359
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1947731507
Short name T483
Test name
Test status
Simulation time 10317274371 ps
CPU time 15.03 seconds
Started Jun 07 08:41:35 PM PDT 24
Finished Jun 07 08:41:51 PM PDT 24
Peak memory 205908 kb
Host smart-56aaff3f-6e28-4628-89c3-370bdbe2ffb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19477
31507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1947731507
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.3344963765
Short name T1064
Test name
Test status
Simulation time 10093999826 ps
CPU time 15.77 seconds
Started Jun 07 08:41:47 PM PDT 24
Finished Jun 07 08:42:07 PM PDT 24
Peak memory 205768 kb
Host smart-b61f21f8-b065-45e6-9b55-0cd9b8975875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33449
63765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.3344963765
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.2642365613
Short name T1593
Test name
Test status
Simulation time 10061244268 ps
CPU time 12.77 seconds
Started Jun 07 08:41:48 PM PDT 24
Finished Jun 07 08:42:04 PM PDT 24
Peak memory 205768 kb
Host smart-c055f94b-daa2-45be-8e99-369009784766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26423
65613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.2642365613
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1843308249
Short name T469
Test name
Test status
Simulation time 10110397669 ps
CPU time 13.73 seconds
Started Jun 07 08:41:37 PM PDT 24
Finished Jun 07 08:41:52 PM PDT 24
Peak memory 205864 kb
Host smart-b80614b5-4671-4354-a531-cb571395137c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18433
08249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1843308249
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.4137300142
Short name T1423
Test name
Test status
Simulation time 10094073283 ps
CPU time 13.41 seconds
Started Jun 07 08:41:36 PM PDT 24
Finished Jun 07 08:41:51 PM PDT 24
Peak memory 205856 kb
Host smart-6e26b209-9041-41c8-a6e1-ad51470555a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41373
00142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.4137300142
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.3838616850
Short name T1153
Test name
Test status
Simulation time 13165168660 ps
CPU time 15.82 seconds
Started Jun 07 08:41:34 PM PDT 24
Finished Jun 07 08:41:51 PM PDT 24
Peak memory 205816 kb
Host smart-16723b81-5b40-46a1-9e14-44720f72ef09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38386
16850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.3838616850
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.1845588449
Short name T974
Test name
Test status
Simulation time 10123438240 ps
CPU time 14.26 seconds
Started Jun 07 08:41:34 PM PDT 24
Finished Jun 07 08:41:50 PM PDT 24
Peak memory 205756 kb
Host smart-e1edd4f1-458f-421c-be75-f53aee31559b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18455
88449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.1845588449
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.3685855841
Short name T1393
Test name
Test status
Simulation time 23267087571 ps
CPU time 374.04 seconds
Started Jun 07 08:41:35 PM PDT 24
Finished Jun 07 08:47:50 PM PDT 24
Peak memory 205760 kb
Host smart-0792c695-d9e3-46ad-925f-7bba0bf61a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36858
55841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.3685855841
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.3435815147
Short name T401
Test name
Test status
Simulation time 10041433195 ps
CPU time 13.24 seconds
Started Jun 07 08:41:37 PM PDT 24
Finished Jun 07 08:41:52 PM PDT 24
Peak memory 205740 kb
Host smart-efe914c1-f0c3-4fb9-bdfd-84d03728b6c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34358
15147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.3435815147
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3713904408
Short name T123
Test name
Test status
Simulation time 10101618316 ps
CPU time 13.66 seconds
Started Jun 07 08:41:34 PM PDT 24
Finished Jun 07 08:41:49 PM PDT 24
Peak memory 205880 kb
Host smart-24717989-1c14-46ca-8eb0-77d0dabee22a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37139
04408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3713904408
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.2772649462
Short name T503
Test name
Test status
Simulation time 10037416662 ps
CPU time 12.8 seconds
Started Jun 07 08:41:36 PM PDT 24
Finished Jun 07 08:41:50 PM PDT 24
Peak memory 205716 kb
Host smart-093a8e6d-f18f-4e3c-9267-8bfda8435153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27726
49462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.2772649462
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.4135902751
Short name T81
Test name
Test status
Simulation time 10089977319 ps
CPU time 13.44 seconds
Started Jun 07 08:41:37 PM PDT 24
Finished Jun 07 08:41:52 PM PDT 24
Peak memory 205796 kb
Host smart-eef660c2-8647-4e1f-907c-b0b4e30d666c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41359
02751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.4135902751
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.1514625265
Short name T548
Test name
Test status
Simulation time 10110458642 ps
CPU time 13.6 seconds
Started Jun 07 08:41:33 PM PDT 24
Finished Jun 07 08:41:49 PM PDT 24
Peak memory 205856 kb
Host smart-3382ad20-307b-4d7c-b5c1-6675df4630da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15146
25265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.1514625265
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3684442862
Short name T149
Test name
Test status
Simulation time 10044455093 ps
CPU time 16.81 seconds
Started Jun 07 08:41:46 PM PDT 24
Finished Jun 07 08:42:06 PM PDT 24
Peak memory 205768 kb
Host smart-c53e2f19-645b-4411-b67e-a396d2003bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36844
42862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3684442862
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_eop_single_bit_handling.1884289457
Short name T1513
Test name
Test status
Simulation time 10052292266 ps
CPU time 13.3 seconds
Started Jun 07 08:41:49 PM PDT 24
Finished Jun 07 08:42:05 PM PDT 24
Peak memory 205764 kb
Host smart-0e61e78a-c3c7-4abf-b78a-2dede5827a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18842
89457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_eop_single_bit_handling.1884289457
Directory /workspace/4.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.3188246003
Short name T1274
Test name
Test status
Simulation time 10044970504 ps
CPU time 13.24 seconds
Started Jun 07 08:41:49 PM PDT 24
Finished Jun 07 08:42:05 PM PDT 24
Peak memory 205892 kb
Host smart-1e95e513-aabd-4a67-8c74-47a62c8e5794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31882
46003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.3188246003
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.4200659956
Short name T1707
Test name
Test status
Simulation time 10043102563 ps
CPU time 13.65 seconds
Started Jun 07 08:41:48 PM PDT 24
Finished Jun 07 08:42:05 PM PDT 24
Peak memory 205820 kb
Host smart-148b616f-6cc3-4ba4-81c9-101400859f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42006
59956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.4200659956
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.1758156301
Short name T84
Test name
Test status
Simulation time 17024958322 ps
CPU time 34.23 seconds
Started Jun 07 08:41:42 PM PDT 24
Finished Jun 07 08:42:19 PM PDT 24
Peak memory 205800 kb
Host smart-3c527987-a391-4dff-9fcb-36d058e88330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17581
56301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.1758156301
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.4067460488
Short name T562
Test name
Test status
Simulation time 10081897762 ps
CPU time 13.79 seconds
Started Jun 07 08:41:42 PM PDT 24
Finished Jun 07 08:41:58 PM PDT 24
Peak memory 205756 kb
Host smart-e83d153a-072a-4ce4-bb23-eba22757c82d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40674
60488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.4067460488
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.958949259
Short name T1974
Test name
Test status
Simulation time 10128295003 ps
CPU time 16.03 seconds
Started Jun 07 08:41:45 PM PDT 24
Finished Jun 07 08:42:03 PM PDT 24
Peak memory 205800 kb
Host smart-46824173-e29b-41b3-8370-75d0ec97848b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95894
9259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.958949259
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.590689244
Short name T1396
Test name
Test status
Simulation time 14742172635 ps
CPU time 42.68 seconds
Started Jun 07 08:41:42 PM PDT 24
Finished Jun 07 08:42:27 PM PDT 24
Peak memory 205848 kb
Host smart-f1bd7ad8-f474-4e81-b3dc-7175dc58d977
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=590689244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.590689244
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.927311471
Short name T1861
Test name
Test status
Simulation time 30476976566 ps
CPU time 475.19 seconds
Started Jun 07 08:41:40 PM PDT 24
Finished Jun 07 08:49:37 PM PDT 24
Peak memory 205952 kb
Host smart-acc66198-475c-4605-999c-fee53ac500e5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=927311471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.927311471
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.2108428327
Short name T1870
Test name
Test status
Simulation time 36471890958 ps
CPU time 228.41 seconds
Started Jun 07 08:41:41 PM PDT 24
Finished Jun 07 08:45:32 PM PDT 24
Peak memory 205932 kb
Host smart-2dc1b501-e955-4bea-a305-a6f7862c2fff
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2108428327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.2108428327
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.668459396
Short name T1838
Test name
Test status
Simulation time 10070590013 ps
CPU time 12.66 seconds
Started Jun 07 08:41:41 PM PDT 24
Finished Jun 07 08:41:55 PM PDT 24
Peak memory 205848 kb
Host smart-d81ea9f3-bc65-43dc-863e-c93c0ac69959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66845
9396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.668459396
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.1244524213
Short name T1918
Test name
Test status
Simulation time 10048724462 ps
CPU time 13.35 seconds
Started Jun 07 08:41:41 PM PDT 24
Finished Jun 07 08:41:57 PM PDT 24
Peak memory 205848 kb
Host smart-cae3f108-622c-4756-96ce-52e0d8b04928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12445
24213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.1244524213
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.20402961
Short name T196
Test name
Test status
Simulation time 323516897 ps
CPU time 1.07 seconds
Started Jun 07 08:41:47 PM PDT 24
Finished Jun 07 08:41:51 PM PDT 24
Peak memory 221752 kb
Host smart-a70f12b8-9f65-4c0b-aa64-54a63f421c7d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=20402961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.20402961
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.1556630677
Short name T1160
Test name
Test status
Simulation time 10058179375 ps
CPU time 12.79 seconds
Started Jun 07 08:41:47 PM PDT 24
Finished Jun 07 08:42:03 PM PDT 24
Peak memory 205860 kb
Host smart-24feec19-adf3-4ec9-b343-03f79040a309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15566
30677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.1556630677
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.4238226144
Short name T487
Test name
Test status
Simulation time 10063446724 ps
CPU time 14.64 seconds
Started Jun 07 08:41:41 PM PDT 24
Finished Jun 07 08:41:58 PM PDT 24
Peak memory 205768 kb
Host smart-c699dd0f-935e-4bc7-86ab-1ac27e7f96e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42382
26144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.4238226144
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.3225421431
Short name T1490
Test name
Test status
Simulation time 10097280570 ps
CPU time 14.58 seconds
Started Jun 07 08:41:30 PM PDT 24
Finished Jun 07 08:41:48 PM PDT 24
Peak memory 205784 kb
Host smart-59fa3b7d-d00a-4110-aa3a-bf401d0bdc8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32254
21431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3225421431
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.141399273
Short name T377
Test name
Test status
Simulation time 10096494808 ps
CPU time 14.03 seconds
Started Jun 07 08:41:48 PM PDT 24
Finished Jun 07 08:42:05 PM PDT 24
Peak memory 205820 kb
Host smart-beca4082-7458-4d62-a7e3-eff3080234ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14139
9273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.141399273
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.1376349719
Short name T1577
Test name
Test status
Simulation time 10074304918 ps
CPU time 12.62 seconds
Started Jun 07 08:41:41 PM PDT 24
Finished Jun 07 08:41:55 PM PDT 24
Peak memory 205764 kb
Host smart-9ca00a25-5bb9-411e-8c57-647bc7b9e9c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13763
49719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1376349719
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.3552952264
Short name T674
Test name
Test status
Simulation time 19625321514 ps
CPU time 276.29 seconds
Started Jun 07 08:41:38 PM PDT 24
Finished Jun 07 08:46:16 PM PDT 24
Peak memory 205720 kb
Host smart-bc47e07e-efa0-4772-ac82-7dd42582a0e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35529
52264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.3552952264
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.1727337172
Short name T1862
Test name
Test status
Simulation time 32931295212 ps
CPU time 575.83 seconds
Started Jun 07 08:41:42 PM PDT 24
Finished Jun 07 08:51:20 PM PDT 24
Peak memory 205888 kb
Host smart-778b18ee-997f-4de9-af59-f8cf60c534d6
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727337172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_
traffic.1727337172
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.2694363947
Short name T689
Test name
Test status
Simulation time 10148609369 ps
CPU time 13.51 seconds
Started Jun 07 08:47:24 PM PDT 24
Finished Jun 07 08:47:39 PM PDT 24
Peak memory 205796 kb
Host smart-c18c09a5-9304-4a87-b77a-868f0f9bf7d1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2694363947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.2694363947
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.2331086209
Short name T1519
Test name
Test status
Simulation time 10057422588 ps
CPU time 13.02 seconds
Started Jun 07 08:47:25 PM PDT 24
Finished Jun 07 08:47:40 PM PDT 24
Peak memory 205788 kb
Host smart-c092c39b-8251-446a-8c67-c42c5dab960d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2331086209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.2331086209
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.4005225529
Short name T1157
Test name
Test status
Simulation time 10084400911 ps
CPU time 12.64 seconds
Started Jun 07 08:47:27 PM PDT 24
Finished Jun 07 08:47:41 PM PDT 24
Peak memory 205764 kb
Host smart-a8d410f7-f079-4327-951a-aa9b12941740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40052
25529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.4005225529
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.2491579734
Short name T1503
Test name
Test status
Simulation time 14008413004 ps
CPU time 18.32 seconds
Started Jun 07 08:47:07 PM PDT 24
Finished Jun 07 08:47:28 PM PDT 24
Peak memory 205764 kb
Host smart-798efa66-f146-484e-8642-467b523a4171
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2491579734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.2491579734
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.1670363482
Short name T1673
Test name
Test status
Simulation time 23231557472 ps
CPU time 28.76 seconds
Started Jun 07 08:47:12 PM PDT 24
Finished Jun 07 08:47:43 PM PDT 24
Peak memory 205900 kb
Host smart-a499bf9e-5fce-4844-b48c-21f55189597f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1670363482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.1670363482
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1679411293
Short name T1803
Test name
Test status
Simulation time 10067591447 ps
CPU time 15.85 seconds
Started Jun 07 08:47:10 PM PDT 24
Finished Jun 07 08:47:29 PM PDT 24
Peak memory 205828 kb
Host smart-cd980253-2215-4e56-b2c5-73f03973e63b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16794
11293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1679411293
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.4187698620
Short name T1573
Test name
Test status
Simulation time 11230434733 ps
CPU time 16.33 seconds
Started Jun 07 08:47:16 PM PDT 24
Finished Jun 07 08:47:34 PM PDT 24
Peak memory 205800 kb
Host smart-ebfd598e-a52d-4580-83f2-abcbace2299d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41876
98620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.4187698620
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.2225593737
Short name T1558
Test name
Test status
Simulation time 10043188024 ps
CPU time 13.44 seconds
Started Jun 07 08:47:18 PM PDT 24
Finished Jun 07 08:47:34 PM PDT 24
Peak memory 205852 kb
Host smart-c86c168a-e08b-4e13-8d02-a1ecb3f02ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22255
93737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.2225593737
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.864665635
Short name T1019
Test name
Test status
Simulation time 10107571125 ps
CPU time 13.02 seconds
Started Jun 07 08:47:19 PM PDT 24
Finished Jun 07 08:47:34 PM PDT 24
Peak memory 205836 kb
Host smart-9040c8ea-939e-4d0b-9a10-943fefde9987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86466
5635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.864665635
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.225056775
Short name T1192
Test name
Test status
Simulation time 10984922272 ps
CPU time 15.06 seconds
Started Jun 07 08:47:16 PM PDT 24
Finished Jun 07 08:47:33 PM PDT 24
Peak memory 205864 kb
Host smart-58dcb6b1-b34e-44e3-aca3-a5302e518967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22505
6775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.225056775
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.538339519
Short name T666
Test name
Test status
Simulation time 10253338425 ps
CPU time 14.42 seconds
Started Jun 07 08:47:18 PM PDT 24
Finished Jun 07 08:47:36 PM PDT 24
Peak memory 205808 kb
Host smart-63126d7e-d5ba-495b-86b3-da6d2d32893b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53833
9519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.538339519
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.1209497786
Short name T1723
Test name
Test status
Simulation time 10206113529 ps
CPU time 14.86 seconds
Started Jun 07 08:47:28 PM PDT 24
Finished Jun 07 08:47:44 PM PDT 24
Peak memory 205880 kb
Host smart-116a74b0-e6f4-4773-ad7d-61e33e3dcf43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12094
97786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.1209497786
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.2297638127
Short name T982
Test name
Test status
Simulation time 10058810117 ps
CPU time 12.64 seconds
Started Jun 07 08:47:23 PM PDT 24
Finished Jun 07 08:47:37 PM PDT 24
Peak memory 205772 kb
Host smart-b23b0d32-5df7-4e85-9680-b864eaebfb6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22976
38127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.2297638127
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.495188046
Short name T1206
Test name
Test status
Simulation time 10053914928 ps
CPU time 14.89 seconds
Started Jun 07 08:47:17 PM PDT 24
Finished Jun 07 08:47:35 PM PDT 24
Peak memory 205732 kb
Host smart-5056fbbe-d08f-4dc5-a10e-4f12f4d50e46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49518
8046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.495188046
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.1587752608
Short name T1113
Test name
Test status
Simulation time 10116132538 ps
CPU time 13.22 seconds
Started Jun 07 08:47:17 PM PDT 24
Finished Jun 07 08:47:33 PM PDT 24
Peak memory 205884 kb
Host smart-743d54c6-631a-4831-9da9-a133c56c4fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15877
52608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.1587752608
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.344240658
Short name T430
Test name
Test status
Simulation time 13180753499 ps
CPU time 19.13 seconds
Started Jun 07 08:47:18 PM PDT 24
Finished Jun 07 08:47:40 PM PDT 24
Peak memory 205772 kb
Host smart-63003e29-e41d-4e74-8689-b02ee88f43e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34424
0658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.344240658
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2434370215
Short name T920
Test name
Test status
Simulation time 10093225758 ps
CPU time 13.66 seconds
Started Jun 07 08:47:15 PM PDT 24
Finished Jun 07 08:47:31 PM PDT 24
Peak memory 205956 kb
Host smart-61fad7b4-e168-44e7-8178-4e34027892fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24343
70215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2434370215
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.4267975024
Short name T642
Test name
Test status
Simulation time 16376080428 ps
CPU time 188.74 seconds
Started Jun 07 08:47:19 PM PDT 24
Finished Jun 07 08:50:30 PM PDT 24
Peak memory 205868 kb
Host smart-27ed834e-c29d-4264-a2f5-5bf3a9f92733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42679
75024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.4267975024
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3000671582
Short name T1235
Test name
Test status
Simulation time 10090317194 ps
CPU time 13.92 seconds
Started Jun 07 08:47:15 PM PDT 24
Finished Jun 07 08:47:30 PM PDT 24
Peak memory 205852 kb
Host smart-3ee5e0e9-84f1-40e8-bd90-c399d118e4b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30006
71582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3000671582
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.196836780
Short name T1827
Test name
Test status
Simulation time 10096340243 ps
CPU time 12.62 seconds
Started Jun 07 08:47:19 PM PDT 24
Finished Jun 07 08:47:34 PM PDT 24
Peak memory 205820 kb
Host smart-3f123a3b-34fa-4fde-97f2-0a021fed9baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19683
6780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.196836780
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.2456285157
Short name T1817
Test name
Test status
Simulation time 10115697511 ps
CPU time 16.77 seconds
Started Jun 07 08:47:16 PM PDT 24
Finished Jun 07 08:47:35 PM PDT 24
Peak memory 205860 kb
Host smart-8b52a46d-71d9-4eae-941e-f8d82bf35101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24562
85157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.2456285157
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.1568373186
Short name T702
Test name
Test status
Simulation time 10061614770 ps
CPU time 14.2 seconds
Started Jun 07 08:47:16 PM PDT 24
Finished Jun 07 08:47:32 PM PDT 24
Peak memory 205888 kb
Host smart-7170ec6e-1157-4230-b660-82d1b8e70354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15683
73186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1568373186
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2510802488
Short name T1585
Test name
Test status
Simulation time 10054455754 ps
CPU time 13.99 seconds
Started Jun 07 08:47:14 PM PDT 24
Finished Jun 07 08:47:30 PM PDT 24
Peak memory 205856 kb
Host smart-ef01f88f-001e-4472-aa0d-d0ea0b172a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25108
02488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2510802488
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.3199140619
Short name T1177
Test name
Test status
Simulation time 10068001242 ps
CPU time 13.54 seconds
Started Jun 07 08:47:22 PM PDT 24
Finished Jun 07 08:47:38 PM PDT 24
Peak memory 205844 kb
Host smart-998654c1-b348-43be-980b-34d5049db583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31991
40619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.3199140619
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_eop_single_bit_handling.2194666773
Short name T1414
Test name
Test status
Simulation time 10105137241 ps
CPU time 13.68 seconds
Started Jun 07 08:47:26 PM PDT 24
Finished Jun 07 08:47:41 PM PDT 24
Peak memory 205752 kb
Host smart-de96683b-bb54-407a-a19a-7521d03cab4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21946
66773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_eop_single_bit_handling.2194666773
Directory /workspace/40.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.1705238266
Short name T1559
Test name
Test status
Simulation time 10044913028 ps
CPU time 14.02 seconds
Started Jun 07 08:47:18 PM PDT 24
Finished Jun 07 08:47:35 PM PDT 24
Peak memory 205860 kb
Host smart-0d51a4e3-8ada-4e9c-b7fd-6b94fc089e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17052
38266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.1705238266
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.786815338
Short name T1199
Test name
Test status
Simulation time 10039220019 ps
CPU time 13.17 seconds
Started Jun 07 08:47:23 PM PDT 24
Finished Jun 07 08:47:38 PM PDT 24
Peak memory 205896 kb
Host smart-5528a2af-ecb6-4b82-a3c1-6914f1d3d298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78681
5338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.786815338
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.2843241144
Short name T1525
Test name
Test status
Simulation time 31587896389 ps
CPU time 62.75 seconds
Started Jun 07 08:47:22 PM PDT 24
Finished Jun 07 08:48:27 PM PDT 24
Peak memory 205744 kb
Host smart-871c59d1-6960-4daf-aea6-990055a6b421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28432
41144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.2843241144
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2273998346
Short name T1944
Test name
Test status
Simulation time 10069488524 ps
CPU time 14.6 seconds
Started Jun 07 08:47:17 PM PDT 24
Finished Jun 07 08:47:34 PM PDT 24
Peak memory 205824 kb
Host smart-a9b91b30-e439-47b1-9100-6490b6836019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22739
98346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2273998346
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.1834844311
Short name T2
Test name
Test status
Simulation time 10161562465 ps
CPU time 14.03 seconds
Started Jun 07 08:47:18 PM PDT 24
Finished Jun 07 08:47:35 PM PDT 24
Peak memory 205788 kb
Host smart-a3c9f906-a775-4c24-b119-248bc76aed5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18348
44311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1834844311
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.3421891267
Short name T1677
Test name
Test status
Simulation time 10066095141 ps
CPU time 13.67 seconds
Started Jun 07 08:47:19 PM PDT 24
Finished Jun 07 08:47:35 PM PDT 24
Peak memory 205844 kb
Host smart-b1793bcd-9d87-4a9c-9ec5-88d5ffcf4b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34218
91267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.3421891267
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.4235449547
Short name T1859
Test name
Test status
Simulation time 10055339014 ps
CPU time 12.65 seconds
Started Jun 07 08:47:20 PM PDT 24
Finished Jun 07 08:47:35 PM PDT 24
Peak memory 205844 kb
Host smart-78c28893-cad6-47cd-89c2-f7d39a33c643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42354
49547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.4235449547
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.1399036480
Short name T1379
Test name
Test status
Simulation time 10088635200 ps
CPU time 15.59 seconds
Started Jun 07 08:47:24 PM PDT 24
Finished Jun 07 08:47:42 PM PDT 24
Peak memory 205816 kb
Host smart-9688a21c-8c68-4cbf-8081-96387428a4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13990
36480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.1399036480
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.2915346051
Short name T1320
Test name
Test status
Simulation time 10134665383 ps
CPU time 15.92 seconds
Started Jun 07 08:47:19 PM PDT 24
Finished Jun 07 08:47:37 PM PDT 24
Peak memory 205852 kb
Host smart-32a159ca-797e-47f8-a628-2d5b827409c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29153
46051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.2915346051
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2132752250
Short name T983
Test name
Test status
Simulation time 10146336384 ps
CPU time 15.34 seconds
Started Jun 07 08:47:09 PM PDT 24
Finished Jun 07 08:47:27 PM PDT 24
Peak memory 205872 kb
Host smart-bf33717a-8514-40ec-8366-33798ebd5439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21327
52250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2132752250
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.1499967112
Short name T501
Test name
Test status
Simulation time 10076798519 ps
CPU time 14.08 seconds
Started Jun 07 08:47:16 PM PDT 24
Finished Jun 07 08:47:32 PM PDT 24
Peak memory 205816 kb
Host smart-9e5397a1-2f26-48b4-a2bb-8050f773bf7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14999
67112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.1499967112
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1753005498
Short name T1656
Test name
Test status
Simulation time 10166401293 ps
CPU time 12.76 seconds
Started Jun 07 08:47:18 PM PDT 24
Finished Jun 07 08:47:33 PM PDT 24
Peak memory 205812 kb
Host smart-1c15f286-3a17-40a5-a7eb-001db992e60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17530
05498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1753005498
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.4024870106
Short name T1538
Test name
Test status
Simulation time 19392371484 ps
CPU time 267.04 seconds
Started Jun 07 08:47:17 PM PDT 24
Finished Jun 07 08:51:46 PM PDT 24
Peak memory 205772 kb
Host smart-03f4f260-17fd-4e45-b515-44b96ff116a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40248
70106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.4024870106
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.1944660906
Short name T749
Test name
Test status
Simulation time 10139910235 ps
CPU time 13.73 seconds
Started Jun 07 08:47:33 PM PDT 24
Finished Jun 07 08:47:50 PM PDT 24
Peak memory 205900 kb
Host smart-b45e33f6-064a-4513-b2ad-456f6380cb89
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1944660906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.1944660906
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.1366529548
Short name T936
Test name
Test status
Simulation time 10098172466 ps
CPU time 13.15 seconds
Started Jun 07 08:47:43 PM PDT 24
Finished Jun 07 08:48:04 PM PDT 24
Peak memory 205760 kb
Host smart-bbc9e18b-347b-4b15-a7e9-3124075e2191
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1366529548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.1366529548
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.1876076917
Short name T1391
Test name
Test status
Simulation time 10104852751 ps
CPU time 12.76 seconds
Started Jun 07 08:47:39 PM PDT 24
Finished Jun 07 08:47:59 PM PDT 24
Peak memory 205764 kb
Host smart-d47853e8-fec6-445e-919a-79fd79394a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18760
76917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.1876076917
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.1223645352
Short name T1134
Test name
Test status
Simulation time 14229435249 ps
CPU time 17.01 seconds
Started Jun 07 08:47:23 PM PDT 24
Finished Jun 07 08:47:42 PM PDT 24
Peak memory 205888 kb
Host smart-41bfa24b-58ca-4ad6-a250-569d64754668
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1223645352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.1223645352
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.1346280664
Short name T13
Test name
Test status
Simulation time 23192754300 ps
CPU time 24.76 seconds
Started Jun 07 08:47:25 PM PDT 24
Finished Jun 07 08:47:52 PM PDT 24
Peak memory 205820 kb
Host smart-65cc7421-e50f-4a68-9550-885574ae7f12
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1346280664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.1346280664
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.4111507982
Short name T695
Test name
Test status
Simulation time 10058060574 ps
CPU time 13.3 seconds
Started Jun 07 08:47:27 PM PDT 24
Finished Jun 07 08:47:42 PM PDT 24
Peak memory 205844 kb
Host smart-95af1383-5796-413f-bca8-bbce069c0dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41115
07982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.4111507982
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.880369420
Short name T491
Test name
Test status
Simulation time 10081805203 ps
CPU time 13.95 seconds
Started Jun 07 08:47:28 PM PDT 24
Finished Jun 07 08:47:44 PM PDT 24
Peak memory 205744 kb
Host smart-8a90a490-c2a5-4e5e-901e-fb225cf5e066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88036
9420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.880369420
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.2628827216
Short name T1824
Test name
Test status
Simulation time 10077329188 ps
CPU time 14.06 seconds
Started Jun 07 08:47:25 PM PDT 24
Finished Jun 07 08:47:42 PM PDT 24
Peak memory 205796 kb
Host smart-a7bd545f-39f0-4890-b30b-0ea5ff132281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26288
27216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.2628827216
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.2218829402
Short name T980
Test name
Test status
Simulation time 10656126248 ps
CPU time 14.66 seconds
Started Jun 07 08:47:24 PM PDT 24
Finished Jun 07 08:47:41 PM PDT 24
Peak memory 205848 kb
Host smart-6e4f577f-bd84-4a52-a68c-7e44eca37471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22188
29402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.2218829402
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.4158769330
Short name T462
Test name
Test status
Simulation time 10157308339 ps
CPU time 16.6 seconds
Started Jun 07 08:47:24 PM PDT 24
Finished Jun 07 08:47:42 PM PDT 24
Peak memory 205912 kb
Host smart-d290c903-52dd-4e49-879f-0f5b1a75e81f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41587
69330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.4158769330
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.403737069
Short name T1842
Test name
Test status
Simulation time 10151144030 ps
CPU time 13.13 seconds
Started Jun 07 08:47:35 PM PDT 24
Finished Jun 07 08:47:51 PM PDT 24
Peak memory 205828 kb
Host smart-12760b3c-9bd7-439a-8f6f-0975b1e7276c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40373
7069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.403737069
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.3550593219
Short name T1242
Test name
Test status
Simulation time 10045499896 ps
CPU time 13.26 seconds
Started Jun 07 08:47:34 PM PDT 24
Finished Jun 07 08:47:51 PM PDT 24
Peak memory 205728 kb
Host smart-fb998f09-6450-4798-a18a-7e7018277ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35505
93219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.3550593219
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.307886821
Short name T1687
Test name
Test status
Simulation time 10197579233 ps
CPU time 14.41 seconds
Started Jun 07 08:47:26 PM PDT 24
Finished Jun 07 08:47:42 PM PDT 24
Peak memory 205764 kb
Host smart-0f510707-7b9f-4b84-b0a3-35687d411d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30788
6821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.307886821
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.2763861154
Short name T205
Test name
Test status
Simulation time 10088945176 ps
CPU time 12.81 seconds
Started Jun 07 08:47:24 PM PDT 24
Finished Jun 07 08:47:39 PM PDT 24
Peak memory 205732 kb
Host smart-e9c788b0-bb85-4425-bbb7-e1567372bb6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27638
61154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2763861154
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.3392981392
Short name T1645
Test name
Test status
Simulation time 13196803889 ps
CPU time 16.25 seconds
Started Jun 07 08:47:27 PM PDT 24
Finished Jun 07 08:47:45 PM PDT 24
Peak memory 205888 kb
Host smart-1a428bde-5c60-4851-9dfc-765aa79a28b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33929
81392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.3392981392
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.1148845390
Short name T447
Test name
Test status
Simulation time 10105898860 ps
CPU time 15.55 seconds
Started Jun 07 08:47:27 PM PDT 24
Finished Jun 07 08:47:45 PM PDT 24
Peak memory 205904 kb
Host smart-cd8e29fa-1ac6-4d20-8991-a6568ef288fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11488
45390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.1148845390
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.3992815116
Short name T1225
Test name
Test status
Simulation time 15883989712 ps
CPU time 56.19 seconds
Started Jun 07 08:47:27 PM PDT 24
Finished Jun 07 08:48:25 PM PDT 24
Peak memory 205856 kb
Host smart-a9b0c69c-4900-4f32-a923-98383f3fcfeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39928
15116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.3992815116
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1258287427
Short name T1799
Test name
Test status
Simulation time 10043912937 ps
CPU time 14.38 seconds
Started Jun 07 08:47:25 PM PDT 24
Finished Jun 07 08:47:42 PM PDT 24
Peak memory 205892 kb
Host smart-50149412-cc34-4fdb-93b6-d1db3c6472a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12582
87427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1258287427
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3678095611
Short name T103
Test name
Test status
Simulation time 10077890791 ps
CPU time 13.79 seconds
Started Jun 07 08:47:25 PM PDT 24
Finished Jun 07 08:47:41 PM PDT 24
Peak memory 205884 kb
Host smart-888b5262-1cf7-4657-a068-70115cf45037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36780
95611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3678095611
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.1141582270
Short name T1975
Test name
Test status
Simulation time 10064071081 ps
CPU time 13.35 seconds
Started Jun 07 08:47:30 PM PDT 24
Finished Jun 07 08:47:45 PM PDT 24
Peak memory 205384 kb
Host smart-a2899f36-49e9-4acc-80ec-9004b6cc847d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11415
82270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.1141582270
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.4256452663
Short name T1432
Test name
Test status
Simulation time 10055211376 ps
CPU time 12.95 seconds
Started Jun 07 08:47:27 PM PDT 24
Finished Jun 07 08:47:42 PM PDT 24
Peak memory 205928 kb
Host smart-9866bf94-979d-41b6-a8f0-8393e3a716c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42564
52663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.4256452663
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.1225007075
Short name T1152
Test name
Test status
Simulation time 10062393687 ps
CPU time 12.79 seconds
Started Jun 07 08:47:30 PM PDT 24
Finished Jun 07 08:47:44 PM PDT 24
Peak memory 205348 kb
Host smart-66e8ca40-2232-4f9c-8f98-6073b43df835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12250
07075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.1225007075
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.48394333
Short name T137
Test name
Test status
Simulation time 10058209344 ps
CPU time 13.81 seconds
Started Jun 07 08:47:33 PM PDT 24
Finished Jun 07 08:47:50 PM PDT 24
Peak memory 205868 kb
Host smart-9af9d3bf-82e7-41d3-a709-be32df2a7bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48394
333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.48394333
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_eop_single_bit_handling.2116028140
Short name T596
Test name
Test status
Simulation time 10080425962 ps
CPU time 12.98 seconds
Started Jun 07 08:47:30 PM PDT 24
Finished Jun 07 08:47:45 PM PDT 24
Peak memory 205768 kb
Host smart-0684e200-5300-485f-a7f3-8e4ccc01e496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21160
28140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_eop_single_bit_handling.2116028140
Directory /workspace/41.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.1596107027
Short name T42
Test name
Test status
Simulation time 10060992090 ps
CPU time 12.74 seconds
Started Jun 07 08:47:30 PM PDT 24
Finished Jun 07 08:47:44 PM PDT 24
Peak memory 205720 kb
Host smart-155b5b81-d319-4948-8262-0cca452cf820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15961
07027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.1596107027
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.4187322537
Short name T997
Test name
Test status
Simulation time 10066493705 ps
CPU time 12.48 seconds
Started Jun 07 08:47:35 PM PDT 24
Finished Jun 07 08:47:50 PM PDT 24
Peak memory 205796 kb
Host smart-b3f258d3-9849-4324-8542-a5aaea608c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41873
22537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.4187322537
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1114644078
Short name T1594
Test name
Test status
Simulation time 16442621185 ps
CPU time 26.34 seconds
Started Jun 07 08:47:39 PM PDT 24
Finished Jun 07 08:48:12 PM PDT 24
Peak memory 205728 kb
Host smart-36d1cdba-134f-4c93-a807-24a8da59602c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11146
44078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1114644078
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.3175244435
Short name T1600
Test name
Test status
Simulation time 10079841353 ps
CPU time 13.03 seconds
Started Jun 07 08:47:31 PM PDT 24
Finished Jun 07 08:47:46 PM PDT 24
Peak memory 205828 kb
Host smart-21e59e05-c687-4c67-a3d5-89cf47612226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31752
44435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.3175244435
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3594583946
Short name T844
Test name
Test status
Simulation time 10143509399 ps
CPU time 13.01 seconds
Started Jun 07 08:47:34 PM PDT 24
Finished Jun 07 08:47:50 PM PDT 24
Peak memory 205716 kb
Host smart-fd701fe0-96fe-4f4a-a201-008e52dd9173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35945
83946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3594583946
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.2918424103
Short name T215
Test name
Test status
Simulation time 10089364277 ps
CPU time 14.14 seconds
Started Jun 07 08:47:46 PM PDT 24
Finished Jun 07 08:48:08 PM PDT 24
Peak memory 205880 kb
Host smart-db5a8c04-3fe1-40c1-b13d-09be78c467da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29184
24103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.2918424103
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.2495836688
Short name T1762
Test name
Test status
Simulation time 10054706550 ps
CPU time 13.67 seconds
Started Jun 07 08:47:34 PM PDT 24
Finished Jun 07 08:47:50 PM PDT 24
Peak memory 205848 kb
Host smart-ad251763-a7d9-4c7d-9b61-33b9073b7c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24958
36688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.2495836688
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.484042007
Short name T1943
Test name
Test status
Simulation time 10131415396 ps
CPU time 13.5 seconds
Started Jun 07 08:47:43 PM PDT 24
Finished Jun 07 08:48:04 PM PDT 24
Peak memory 205824 kb
Host smart-2017a9a6-4d26-4740-a844-3830ae5ab955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48404
2007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.484042007
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.611984761
Short name T524
Test name
Test status
Simulation time 10045584327 ps
CPU time 13.38 seconds
Started Jun 07 08:47:35 PM PDT 24
Finished Jun 07 08:47:51 PM PDT 24
Peak memory 205864 kb
Host smart-f53ed630-e7ef-4c74-ba0a-d7c5afe8f37e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61198
4761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.611984761
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3351991449
Short name T1836
Test name
Test status
Simulation time 10143563042 ps
CPU time 14.25 seconds
Started Jun 07 08:47:25 PM PDT 24
Finished Jun 07 08:47:41 PM PDT 24
Peak memory 205764 kb
Host smart-31d0cb20-c9e8-4b62-a7b7-702330be5277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33519
91449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3351991449
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2421001282
Short name T904
Test name
Test status
Simulation time 10113744385 ps
CPU time 15.63 seconds
Started Jun 07 08:47:31 PM PDT 24
Finished Jun 07 08:47:48 PM PDT 24
Peak memory 205748 kb
Host smart-87f29120-dbe6-4bc4-a04d-51b51898479a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24210
01282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2421001282
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.24778450
Short name T1015
Test name
Test status
Simulation time 10083064391 ps
CPU time 13.23 seconds
Started Jun 07 08:47:32 PM PDT 24
Finished Jun 07 08:47:48 PM PDT 24
Peak memory 205888 kb
Host smart-57dbda39-949b-4bea-9a33-0444247630b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24778
450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.24778450
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.512276315
Short name T1757
Test name
Test status
Simulation time 15302073262 ps
CPU time 64.69 seconds
Started Jun 07 08:47:35 PM PDT 24
Finished Jun 07 08:48:42 PM PDT 24
Peak memory 205820 kb
Host smart-141a1787-edc3-4058-893c-0e5f39533de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51227
6315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.512276315
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.2536000677
Short name T304
Test name
Test status
Simulation time 10158768758 ps
CPU time 13.52 seconds
Started Jun 07 08:47:39 PM PDT 24
Finished Jun 07 08:47:58 PM PDT 24
Peak memory 205864 kb
Host smart-8092cc53-6635-455a-89e3-6fbf2c69d9fe
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2536000677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.2536000677
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.572303287
Short name T1220
Test name
Test status
Simulation time 10085001493 ps
CPU time 14.38 seconds
Started Jun 07 08:47:37 PM PDT 24
Finished Jun 07 08:47:56 PM PDT 24
Peak memory 205852 kb
Host smart-838255b1-c23b-4ef3-aefe-1a11bacfc672
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=572303287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.572303287
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.3801255875
Short name T1249
Test name
Test status
Simulation time 10097700811 ps
CPU time 13.81 seconds
Started Jun 07 08:47:37 PM PDT 24
Finished Jun 07 08:47:56 PM PDT 24
Peak memory 205812 kb
Host smart-d2a7cdb8-5982-4fcf-8432-6d3842aafc0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38012
55875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.3801255875
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.925252895
Short name T1554
Test name
Test status
Simulation time 13997328776 ps
CPU time 19.06 seconds
Started Jun 07 08:47:43 PM PDT 24
Finished Jun 07 08:48:10 PM PDT 24
Peak memory 205856 kb
Host smart-17b04b44-3494-4bab-9ac0-7b879e65b6ff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=925252895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.925252895
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.3760752720
Short name T1576
Test name
Test status
Simulation time 23245497683 ps
CPU time 24.97 seconds
Started Jun 07 08:47:34 PM PDT 24
Finished Jun 07 08:48:02 PM PDT 24
Peak memory 205820 kb
Host smart-e5600bd9-848f-4363-91d0-058c52d226d3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3760752720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3760752720
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2658827288
Short name T293
Test name
Test status
Simulation time 10054457541 ps
CPU time 15.58 seconds
Started Jun 07 08:47:31 PM PDT 24
Finished Jun 07 08:47:48 PM PDT 24
Peak memory 205872 kb
Host smart-925d76af-64b0-44b1-959c-cc5a702c95d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26588
27288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2658827288
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.2287157007
Short name T1486
Test name
Test status
Simulation time 10324786172 ps
CPU time 13.19 seconds
Started Jun 07 08:47:41 PM PDT 24
Finished Jun 07 08:48:02 PM PDT 24
Peak memory 205828 kb
Host smart-2143da0c-e0dd-48a5-8f5e-670340a24de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22871
57007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.2287157007
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.3990957619
Short name T970
Test name
Test status
Simulation time 10049678041 ps
CPU time 12.94 seconds
Started Jun 07 08:47:37 PM PDT 24
Finished Jun 07 08:47:54 PM PDT 24
Peak memory 205820 kb
Host smart-3f35b18d-ab54-49c4-bb0d-35c1ffe9b629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39909
57619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.3990957619
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.2729263762
Short name T1251
Test name
Test status
Simulation time 10053190390 ps
CPU time 16.02 seconds
Started Jun 07 08:47:36 PM PDT 24
Finished Jun 07 08:47:55 PM PDT 24
Peak memory 205756 kb
Host smart-71cd7dc3-8bdc-46e9-87de-f325ac5bdb06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27292
63762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.2729263762
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.751962247
Short name T967
Test name
Test status
Simulation time 10769244330 ps
CPU time 16.25 seconds
Started Jun 07 08:47:35 PM PDT 24
Finished Jun 07 08:47:54 PM PDT 24
Peak memory 205880 kb
Host smart-aedda73d-abc2-4a7d-a0e2-2717a28958db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75196
2247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.751962247
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.960837341
Short name T1364
Test name
Test status
Simulation time 10133851793 ps
CPU time 13.91 seconds
Started Jun 07 08:47:33 PM PDT 24
Finished Jun 07 08:47:50 PM PDT 24
Peak memory 205832 kb
Host smart-b4d2d356-2616-4a5b-a6d1-9c1f02891987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96083
7341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.960837341
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.1314607662
Short name T493
Test name
Test status
Simulation time 10115107170 ps
CPU time 13.42 seconds
Started Jun 07 08:47:40 PM PDT 24
Finished Jun 07 08:48:00 PM PDT 24
Peak memory 205800 kb
Host smart-8cde4cc8-012a-48a4-bd6d-640ed4d92104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13146
07662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.1314607662
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.63421068
Short name T458
Test name
Test status
Simulation time 10036371811 ps
CPU time 12.67 seconds
Started Jun 07 08:47:37 PM PDT 24
Finished Jun 07 08:47:55 PM PDT 24
Peak memory 205660 kb
Host smart-23af41b2-07d0-4cf8-a06c-7cdf47f35dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63421
068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.63421068
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2084549855
Short name T1957
Test name
Test status
Simulation time 10063909186 ps
CPU time 13.3 seconds
Started Jun 07 08:47:36 PM PDT 24
Finished Jun 07 08:47:53 PM PDT 24
Peak memory 205800 kb
Host smart-b82cbfd1-570f-4ae9-8d24-00f48778c00f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20845
49855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2084549855
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.4189323014
Short name T803
Test name
Test status
Simulation time 10083858243 ps
CPU time 13.65 seconds
Started Jun 07 08:47:35 PM PDT 24
Finished Jun 07 08:47:51 PM PDT 24
Peak memory 205792 kb
Host smart-13c06850-2549-4723-a992-e7b533802af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41893
23014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.4189323014
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.2475739218
Short name T1907
Test name
Test status
Simulation time 13235011504 ps
CPU time 19.15 seconds
Started Jun 07 08:47:34 PM PDT 24
Finished Jun 07 08:47:56 PM PDT 24
Peak memory 205744 kb
Host smart-9b1da67d-5141-404e-b014-ec964134caef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24757
39218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.2475739218
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.2268574326
Short name T285
Test name
Test status
Simulation time 10111593482 ps
CPU time 13.46 seconds
Started Jun 07 08:47:41 PM PDT 24
Finished Jun 07 08:48:02 PM PDT 24
Peak memory 205936 kb
Host smart-ad8c8516-668d-497e-8eaf-3a086e9387fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22685
74326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.2268574326
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.175711434
Short name T1753
Test name
Test status
Simulation time 17127580537 ps
CPU time 217.17 seconds
Started Jun 07 08:47:34 PM PDT 24
Finished Jun 07 08:51:15 PM PDT 24
Peak memory 205632 kb
Host smart-d9132660-8ad8-4a17-9892-522d7408002a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17571
1434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.175711434
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.4286448988
Short name T302
Test name
Test status
Simulation time 10047660309 ps
CPU time 15.22 seconds
Started Jun 07 08:47:35 PM PDT 24
Finished Jun 07 08:47:53 PM PDT 24
Peak memory 205780 kb
Host smart-f45b969d-4f18-41bd-b09f-63d953324845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42864
48988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.4286448988
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.2637238592
Short name T106
Test name
Test status
Simulation time 10108795454 ps
CPU time 14.88 seconds
Started Jun 07 08:47:37 PM PDT 24
Finished Jun 07 08:47:57 PM PDT 24
Peak memory 205804 kb
Host smart-2e087531-fbeb-4c09-8648-99d17a9f12f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26372
38592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.2637238592
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.2180238983
Short name T534
Test name
Test status
Simulation time 10079542730 ps
CPU time 14.04 seconds
Started Jun 07 08:47:35 PM PDT 24
Finished Jun 07 08:47:52 PM PDT 24
Peak memory 205772 kb
Host smart-42baf0b0-dfea-4f98-9686-5b17f9258fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21802
38983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.2180238983
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.2877654622
Short name T370
Test name
Test status
Simulation time 10092098007 ps
CPU time 13.28 seconds
Started Jun 07 08:47:34 PM PDT 24
Finished Jun 07 08:47:50 PM PDT 24
Peak memory 205796 kb
Host smart-1b6e5ec1-46fc-4094-b2ab-a19b5eea55a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28776
54622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.2877654622
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.2875674617
Short name T320
Test name
Test status
Simulation time 10086098817 ps
CPU time 13.41 seconds
Started Jun 07 08:47:37 PM PDT 24
Finished Jun 07 08:47:55 PM PDT 24
Peak memory 205732 kb
Host smart-99acde3d-ad1a-4b10-8ccb-86d4babf4797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28756
74617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2875674617
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3998803497
Short name T1452
Test name
Test status
Simulation time 10093838403 ps
CPU time 14.78 seconds
Started Jun 07 08:47:35 PM PDT 24
Finished Jun 07 08:47:52 PM PDT 24
Peak memory 205600 kb
Host smart-07f5e103-9dc3-48a5-9a23-a67674710813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39988
03497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3998803497
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_eop_single_bit_handling.2646151049
Short name T1335
Test name
Test status
Simulation time 10080131240 ps
CPU time 12.91 seconds
Started Jun 07 08:47:32 PM PDT 24
Finished Jun 07 08:47:47 PM PDT 24
Peak memory 205804 kb
Host smart-3a6b253f-dde2-4b4f-891d-61a102799e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26461
51049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_eop_single_bit_handling.2646151049
Directory /workspace/42.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.586464443
Short name T927
Test name
Test status
Simulation time 10042838890 ps
CPU time 12.64 seconds
Started Jun 07 08:47:36 PM PDT 24
Finished Jun 07 08:47:52 PM PDT 24
Peak memory 205804 kb
Host smart-e4e66231-0420-401d-ab5a-8ab17cc21955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58646
4443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.586464443
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.3420278894
Short name T751
Test name
Test status
Simulation time 10051432197 ps
CPU time 15.18 seconds
Started Jun 07 08:47:39 PM PDT 24
Finished Jun 07 08:48:00 PM PDT 24
Peak memory 205752 kb
Host smart-c753f444-4545-4b0e-a3aa-a840f2607084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34202
78894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.3420278894
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.1961367550
Short name T173
Test name
Test status
Simulation time 25194630221 ps
CPU time 45.18 seconds
Started Jun 07 08:47:33 PM PDT 24
Finished Jun 07 08:48:20 PM PDT 24
Peak memory 205704 kb
Host smart-c15b6de9-4bda-4c33-aed4-ac8ee9df1db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19613
67550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.1961367550
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.2963836711
Short name T680
Test name
Test status
Simulation time 10086253513 ps
CPU time 12.74 seconds
Started Jun 07 08:47:36 PM PDT 24
Finished Jun 07 08:47:52 PM PDT 24
Peak memory 205804 kb
Host smart-f8671753-bd63-4c83-997c-7672bdd35751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29638
36711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2963836711
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2305245318
Short name T1233
Test name
Test status
Simulation time 10137078269 ps
CPU time 15.49 seconds
Started Jun 07 08:47:36 PM PDT 24
Finished Jun 07 08:47:54 PM PDT 24
Peak memory 205860 kb
Host smart-cb943475-a7da-41a8-9522-f8c9452e52b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23052
45318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2305245318
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.1782222312
Short name T1197
Test name
Test status
Simulation time 10112461448 ps
CPU time 12.95 seconds
Started Jun 07 08:47:41 PM PDT 24
Finished Jun 07 08:48:01 PM PDT 24
Peak memory 205728 kb
Host smart-0a8ec50c-68c4-4d24-a1b9-cc64f0879be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17822
22312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.1782222312
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.146876813
Short name T1786
Test name
Test status
Simulation time 10042541648 ps
CPU time 15.84 seconds
Started Jun 07 08:47:37 PM PDT 24
Finished Jun 07 08:47:58 PM PDT 24
Peak memory 205772 kb
Host smart-20fa85d0-c1ee-4d84-b3fd-0b95a46c9edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14687
6813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.146876813
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.480351717
Short name T1130
Test name
Test status
Simulation time 10077663224 ps
CPU time 14.77 seconds
Started Jun 07 08:47:34 PM PDT 24
Finished Jun 07 08:47:52 PM PDT 24
Peak memory 205828 kb
Host smart-a7d39255-05b7-4a0f-ae55-9c9c6e4f0c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48035
1717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.480351717
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.529220373
Short name T925
Test name
Test status
Simulation time 10094649964 ps
CPU time 13.97 seconds
Started Jun 07 08:47:35 PM PDT 24
Finished Jun 07 08:47:52 PM PDT 24
Peak memory 205764 kb
Host smart-1b12f7f5-8613-4078-b57a-1aea13768360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52922
0373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.529220373
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.595248381
Short name T51
Test name
Test status
Simulation time 10129423326 ps
CPU time 16.78 seconds
Started Jun 07 08:47:32 PM PDT 24
Finished Jun 07 08:47:52 PM PDT 24
Peak memory 205808 kb
Host smart-891f22d7-a68e-4c38-bd85-2da3a0a8e2cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59524
8381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.595248381
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.3052151353
Short name T985
Test name
Test status
Simulation time 10183879478 ps
CPU time 14.85 seconds
Started Jun 07 08:47:34 PM PDT 24
Finished Jun 07 08:47:51 PM PDT 24
Peak memory 205928 kb
Host smart-981d88a3-92c0-40d4-a38b-b351ef292bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30521
51353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.3052151353
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.2495076762
Short name T878
Test name
Test status
Simulation time 10099170929 ps
CPU time 13.02 seconds
Started Jun 07 08:47:34 PM PDT 24
Finished Jun 07 08:47:51 PM PDT 24
Peak memory 205948 kb
Host smart-494bfeb3-9612-4cbf-9445-24cd8e955131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24950
76762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.2495076762
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.3920134167
Short name T1999
Test name
Test status
Simulation time 19741120589 ps
CPU time 88.79 seconds
Started Jun 07 08:47:36 PM PDT 24
Finished Jun 07 08:49:07 PM PDT 24
Peak memory 205876 kb
Host smart-f30cfde7-8273-44f0-864f-735cb2825cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39201
34167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.3920134167
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.772919852
Short name T1068
Test name
Test status
Simulation time 10141804568 ps
CPU time 16.41 seconds
Started Jun 07 08:47:44 PM PDT 24
Finished Jun 07 08:48:08 PM PDT 24
Peak memory 205672 kb
Host smart-987a456e-bfd6-420f-8156-a2bf705097c7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=772919852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.772919852
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.846110818
Short name T298
Test name
Test status
Simulation time 10104350994 ps
CPU time 13.85 seconds
Started Jun 07 08:47:44 PM PDT 24
Finished Jun 07 08:48:05 PM PDT 24
Peak memory 205740 kb
Host smart-666d2d03-400f-4c07-af10-fdf20809d591
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=846110818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.846110818
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.1010849011
Short name T1229
Test name
Test status
Simulation time 10129465683 ps
CPU time 14.53 seconds
Started Jun 07 08:47:44 PM PDT 24
Finished Jun 07 08:48:07 PM PDT 24
Peak memory 205732 kb
Host smart-d3920afe-aca6-40b5-917e-4f5eaca769ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10108
49011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.1010849011
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.486732936
Short name T1114
Test name
Test status
Simulation time 13282072367 ps
CPU time 15.97 seconds
Started Jun 07 08:47:42 PM PDT 24
Finished Jun 07 08:48:05 PM PDT 24
Peak memory 205756 kb
Host smart-cd5e92c5-ecc4-4eaa-9248-25808b299f26
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=486732936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.486732936
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.1691384724
Short name T658
Test name
Test status
Simulation time 23302971913 ps
CPU time 24.21 seconds
Started Jun 07 08:47:39 PM PDT 24
Finished Jun 07 08:48:09 PM PDT 24
Peak memory 205956 kb
Host smart-30998c44-b5be-4a23-a220-0d09dd8f22e1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1691384724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.1691384724
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.549777886
Short name T1263
Test name
Test status
Simulation time 10063070240 ps
CPU time 13.3 seconds
Started Jun 07 08:47:40 PM PDT 24
Finished Jun 07 08:48:00 PM PDT 24
Peak memory 205804 kb
Host smart-a0f97ade-2161-4ad6-8866-cde8499baf17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54977
7886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.549777886
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.1874656243
Short name T1190
Test name
Test status
Simulation time 10464429674 ps
CPU time 16.8 seconds
Started Jun 07 08:47:40 PM PDT 24
Finished Jun 07 08:48:04 PM PDT 24
Peak memory 205764 kb
Host smart-98abfeca-1a1d-4293-9c6c-d6744a8cef5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18746
56243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.1874656243
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.3992498601
Short name T676
Test name
Test status
Simulation time 10035726861 ps
CPU time 13.55 seconds
Started Jun 07 08:47:39 PM PDT 24
Finished Jun 07 08:47:59 PM PDT 24
Peak memory 205756 kb
Host smart-50d9e249-058b-4b31-a33e-ea60c90e3bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39924
98601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.3992498601
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.1716700403
Short name T1437
Test name
Test status
Simulation time 10092282072 ps
CPU time 16.4 seconds
Started Jun 07 08:47:38 PM PDT 24
Finished Jun 07 08:47:59 PM PDT 24
Peak memory 205776 kb
Host smart-bb017f2d-4869-4a51-ad15-05ca5dc41e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17167
00403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1716700403
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.3840484445
Short name T1243
Test name
Test status
Simulation time 11041319786 ps
CPU time 14.89 seconds
Started Jun 07 08:47:42 PM PDT 24
Finished Jun 07 08:48:04 PM PDT 24
Peak memory 205932 kb
Host smart-d88fd08e-fd27-4107-90cc-c9a56a059b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38404
84445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.3840484445
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.2377577215
Short name T1246
Test name
Test status
Simulation time 10160597279 ps
CPU time 13.58 seconds
Started Jun 07 08:47:39 PM PDT 24
Finished Jun 07 08:47:59 PM PDT 24
Peak memory 205960 kb
Host smart-1bf6e99d-04fe-42fb-9383-c13e30638aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23775
77215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.2377577215
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.198602766
Short name T1154
Test name
Test status
Simulation time 10103958728 ps
CPU time 14.64 seconds
Started Jun 07 08:47:44 PM PDT 24
Finished Jun 07 08:48:06 PM PDT 24
Peak memory 205768 kb
Host smart-b391ca6c-19b9-4e2b-ba0d-fd726885393e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19860
2766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.198602766
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.2022628224
Short name T474
Test name
Test status
Simulation time 10040078599 ps
CPU time 12.9 seconds
Started Jun 07 08:47:40 PM PDT 24
Finished Jun 07 08:48:01 PM PDT 24
Peak memory 205880 kb
Host smart-894ff707-c464-4a2a-9553-e414c39d4716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20226
28224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2022628224
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1260529120
Short name T684
Test name
Test status
Simulation time 10075930682 ps
CPU time 13.06 seconds
Started Jun 07 08:47:39 PM PDT 24
Finished Jun 07 08:47:59 PM PDT 24
Peak memory 205804 kb
Host smart-da699f66-87c5-47db-9ec1-79da355a76be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12605
29120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1260529120
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.24990586
Short name T933
Test name
Test status
Simulation time 10163013346 ps
CPU time 15.49 seconds
Started Jun 07 08:47:40 PM PDT 24
Finished Jun 07 08:48:02 PM PDT 24
Peak memory 205768 kb
Host smart-636789ed-583f-4a5f-86ac-559750d61f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24990
586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.24990586
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.1323434202
Short name T1101
Test name
Test status
Simulation time 13239713798 ps
CPU time 18.09 seconds
Started Jun 07 08:47:38 PM PDT 24
Finished Jun 07 08:48:01 PM PDT 24
Peak memory 205688 kb
Host smart-1e86a8a1-fe2f-46d9-bfd7-6549feba8a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13234
34202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.1323434202
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.591743098
Short name T1495
Test name
Test status
Simulation time 10089323154 ps
CPU time 13.92 seconds
Started Jun 07 08:47:36 PM PDT 24
Finished Jun 07 08:47:54 PM PDT 24
Peak memory 205876 kb
Host smart-99a0901b-fc38-493f-9cd0-af6280172a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59174
3098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.591743098
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.588739963
Short name T649
Test name
Test status
Simulation time 19849094900 ps
CPU time 300.6 seconds
Started Jun 07 08:47:42 PM PDT 24
Finished Jun 07 08:52:50 PM PDT 24
Peak memory 205712 kb
Host smart-af97d962-bfd5-49ed-9824-613571a3c2ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58873
9963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.588739963
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.4077068685
Short name T362
Test name
Test status
Simulation time 10043001780 ps
CPU time 12.54 seconds
Started Jun 07 08:47:38 PM PDT 24
Finished Jun 07 08:47:56 PM PDT 24
Peak memory 205808 kb
Host smart-a05dad93-83b8-48f6-bff4-b4cb9bf57312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40770
68685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.4077068685
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2037073263
Short name T1818
Test name
Test status
Simulation time 10088820687 ps
CPU time 13.53 seconds
Started Jun 07 08:47:43 PM PDT 24
Finished Jun 07 08:48:04 PM PDT 24
Peak memory 205816 kb
Host smart-e90ba600-d402-44a8-8b88-8d67faada42c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20370
73263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2037073263
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.1373559568
Short name T1950
Test name
Test status
Simulation time 10049912064 ps
CPU time 13.64 seconds
Started Jun 07 08:47:41 PM PDT 24
Finished Jun 07 08:48:02 PM PDT 24
Peak memory 205780 kb
Host smart-d157bc6e-5ed6-4308-aca5-4768071a8273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13735
59568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.1373559568
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.754480975
Short name T909
Test name
Test status
Simulation time 10082406524 ps
CPU time 12.92 seconds
Started Jun 07 08:47:41 PM PDT 24
Finished Jun 07 08:48:02 PM PDT 24
Peak memory 205880 kb
Host smart-54735efe-e9c8-4687-bbb3-4e620122e984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75448
0975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.754480975
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.3816240980
Short name T142
Test name
Test status
Simulation time 10065130075 ps
CPU time 13.31 seconds
Started Jun 07 08:47:43 PM PDT 24
Finished Jun 07 08:48:04 PM PDT 24
Peak memory 205844 kb
Host smart-cf18f347-6f8f-43ca-801a-39f5541382af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38162
40980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.3816240980
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_eop_single_bit_handling.2255700321
Short name T730
Test name
Test status
Simulation time 10105534543 ps
CPU time 15.54 seconds
Started Jun 07 08:47:45 PM PDT 24
Finished Jun 07 08:48:09 PM PDT 24
Peak memory 205852 kb
Host smart-bb729bd8-030c-4063-9dd7-df6954dff9c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22557
00321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_eop_single_bit_handling.2255700321
Directory /workspace/43.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.1785561666
Short name T1588
Test name
Test status
Simulation time 10037274187 ps
CPU time 13.32 seconds
Started Jun 07 08:47:41 PM PDT 24
Finished Jun 07 08:48:02 PM PDT 24
Peak memory 205772 kb
Host smart-48e7da99-6d2d-413d-9b22-80fbe3e62929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17855
61666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.1785561666
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.1135059102
Short name T1056
Test name
Test status
Simulation time 10074976015 ps
CPU time 12.85 seconds
Started Jun 07 08:47:41 PM PDT 24
Finished Jun 07 08:48:01 PM PDT 24
Peak memory 205716 kb
Host smart-ae614229-b5fb-4e58-9d53-0b3696d2084c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11350
59102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.1135059102
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.2818424931
Short name T179
Test name
Test status
Simulation time 31026061276 ps
CPU time 62.06 seconds
Started Jun 07 08:47:41 PM PDT 24
Finished Jun 07 08:48:51 PM PDT 24
Peak memory 205728 kb
Host smart-cde75cbf-7d7c-4090-8ccc-49b9945d5c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28184
24931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.2818424931
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.1968904893
Short name T1844
Test name
Test status
Simulation time 10079480262 ps
CPU time 13.17 seconds
Started Jun 07 08:47:41 PM PDT 24
Finished Jun 07 08:48:02 PM PDT 24
Peak memory 205812 kb
Host smart-c7f7dd67-e0c5-4c5a-a63c-531be3bdbb58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19689
04893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.1968904893
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2136815278
Short name T654
Test name
Test status
Simulation time 10127285356 ps
CPU time 13.84 seconds
Started Jun 07 08:47:42 PM PDT 24
Finished Jun 07 08:48:04 PM PDT 24
Peak memory 205780 kb
Host smart-1edfc6ef-cd9b-46a4-853d-e6d7dd4cd0d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21368
15278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2136815278
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.714114181
Short name T1458
Test name
Test status
Simulation time 10050152394 ps
CPU time 14.68 seconds
Started Jun 07 08:47:39 PM PDT 24
Finished Jun 07 08:48:00 PM PDT 24
Peak memory 205780 kb
Host smart-48cf8437-0b7f-464d-a609-76965be42f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71411
4181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.714114181
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.3304140670
Short name T1007
Test name
Test status
Simulation time 10045672761 ps
CPU time 12.75 seconds
Started Jun 07 08:47:38 PM PDT 24
Finished Jun 07 08:47:56 PM PDT 24
Peak memory 205820 kb
Host smart-8ac96b51-6958-428a-9aa6-7ae2a0605d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33041
40670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.3304140670
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.702401529
Short name T150
Test name
Test status
Simulation time 10085861046 ps
CPU time 14.49 seconds
Started Jun 07 08:47:44 PM PDT 24
Finished Jun 07 08:48:07 PM PDT 24
Peak memory 205816 kb
Host smart-959889e8-d3d7-4007-839a-1fcee084ad2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70240
1529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.702401529
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.1032821930
Short name T398
Test name
Test status
Simulation time 10062054916 ps
CPU time 15.93 seconds
Started Jun 07 08:47:42 PM PDT 24
Finished Jun 07 08:48:06 PM PDT 24
Peak memory 205712 kb
Host smart-9c1973b7-63d8-4f90-8102-7b606483951c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10328
21930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.1032821930
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.2651220545
Short name T147
Test name
Test status
Simulation time 10103233109 ps
CPU time 14.19 seconds
Started Jun 07 08:47:37 PM PDT 24
Finished Jun 07 08:47:56 PM PDT 24
Peak memory 205872 kb
Host smart-c3533497-0d87-47ad-b9c6-23d9bcf8c633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26512
20545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2651220545
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.4199505145
Short name T2023
Test name
Test status
Simulation time 10078988618 ps
CPU time 13.21 seconds
Started Jun 07 08:47:42 PM PDT 24
Finished Jun 07 08:48:02 PM PDT 24
Peak memory 205852 kb
Host smart-f5059e02-9507-4efa-86ca-95908686bd12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41995
05145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.4199505145
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.2676404229
Short name T519
Test name
Test status
Simulation time 10057775985 ps
CPU time 12.44 seconds
Started Jun 07 08:47:43 PM PDT 24
Finished Jun 07 08:48:03 PM PDT 24
Peak memory 205736 kb
Host smart-e6962bd4-e2fb-4ce8-bf24-cd33bc6c0f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26764
04229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2676404229
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.2902369718
Short name T1787
Test name
Test status
Simulation time 13945387860 ps
CPU time 51.04 seconds
Started Jun 07 08:47:41 PM PDT 24
Finished Jun 07 08:48:40 PM PDT 24
Peak memory 205780 kb
Host smart-b13e521c-6b9d-43f6-8e76-ce3a4f2daaa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29023
69718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.2902369718
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.1703609423
Short name T1076
Test name
Test status
Simulation time 10137342895 ps
CPU time 13.3 seconds
Started Jun 07 08:47:58 PM PDT 24
Finished Jun 07 08:48:16 PM PDT 24
Peak memory 205868 kb
Host smart-32804a08-ace5-409b-9177-f113a7e2ecad
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1703609423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.1703609423
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.862406670
Short name T574
Test name
Test status
Simulation time 10054450576 ps
CPU time 13.99 seconds
Started Jun 07 08:47:45 PM PDT 24
Finished Jun 07 08:48:07 PM PDT 24
Peak memory 205892 kb
Host smart-bc48fa5d-d0ab-4daa-bad3-dc5cb9b9db2d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=862406670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.862406670
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.1320635315
Short name T1016
Test name
Test status
Simulation time 10092351273 ps
CPU time 15.88 seconds
Started Jun 07 08:47:49 PM PDT 24
Finished Jun 07 08:48:12 PM PDT 24
Peak memory 205880 kb
Host smart-d05e2ece-9869-4bd6-9de2-6aa539e4612d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13206
35315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.1320635315
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.1655514087
Short name T1524
Test name
Test status
Simulation time 13554942705 ps
CPU time 17.71 seconds
Started Jun 07 08:47:45 PM PDT 24
Finished Jun 07 08:48:10 PM PDT 24
Peak memory 205792 kb
Host smart-f2137a2f-5797-494b-9d25-fd91a6d5833c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1655514087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.1655514087
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.1046646364
Short name T1167
Test name
Test status
Simulation time 23307226522 ps
CPU time 27.32 seconds
Started Jun 07 08:47:45 PM PDT 24
Finished Jun 07 08:48:20 PM PDT 24
Peak memory 205836 kb
Host smart-0de59e48-a7f9-45a6-b857-aaf594f4c334
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1046646364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.1046646364
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.1654570887
Short name T1961
Test name
Test status
Simulation time 10064207876 ps
CPU time 13.41 seconds
Started Jun 07 08:47:37 PM PDT 24
Finished Jun 07 08:47:56 PM PDT 24
Peak memory 205668 kb
Host smart-57cc5b88-4f60-495e-b600-d3a120f41331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16545
70887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.1654570887
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.3967823304
Short name T1178
Test name
Test status
Simulation time 11341027447 ps
CPU time 14.89 seconds
Started Jun 07 08:47:40 PM PDT 24
Finished Jun 07 08:48:02 PM PDT 24
Peak memory 205824 kb
Host smart-4eae9e18-f403-4f85-bc55-c0895580a098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39678
23304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.3967823304
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.3917126264
Short name T1297
Test name
Test status
Simulation time 10057964413 ps
CPU time 13.19 seconds
Started Jun 07 08:47:44 PM PDT 24
Finished Jun 07 08:48:05 PM PDT 24
Peak memory 205856 kb
Host smart-3dd7ce94-2517-4b89-89ff-824407b02af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39171
26264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.3917126264
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.1890401802
Short name T1028
Test name
Test status
Simulation time 10075583312 ps
CPU time 13.46 seconds
Started Jun 07 08:47:41 PM PDT 24
Finished Jun 07 08:48:02 PM PDT 24
Peak memory 205756 kb
Host smart-b01bfee1-3d86-4afe-b38f-61314cf60fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18904
01802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.1890401802
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.3637467719
Short name T537
Test name
Test status
Simulation time 10730730413 ps
CPU time 14.28 seconds
Started Jun 07 08:47:44 PM PDT 24
Finished Jun 07 08:48:06 PM PDT 24
Peak memory 205796 kb
Host smart-c27d4bb3-4746-413f-b7c7-ecdd9109a3de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36374
67719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.3637467719
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.508448300
Short name T1203
Test name
Test status
Simulation time 10075860791 ps
CPU time 14.94 seconds
Started Jun 07 08:47:50 PM PDT 24
Finished Jun 07 08:48:12 PM PDT 24
Peak memory 205816 kb
Host smart-1eedc13f-eb83-401b-9253-cd7477b3842c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50844
8300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.508448300
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.3219525884
Short name T1100
Test name
Test status
Simulation time 10106166738 ps
CPU time 13.07 seconds
Started Jun 07 08:47:47 PM PDT 24
Finished Jun 07 08:48:08 PM PDT 24
Peak memory 205856 kb
Host smart-7b6291aa-7c65-47a0-9357-19b88ead0ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32195
25884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3219525884
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.1164588468
Short name T1711
Test name
Test status
Simulation time 10046009226 ps
CPU time 15.58 seconds
Started Jun 07 08:47:58 PM PDT 24
Finished Jun 07 08:48:19 PM PDT 24
Peak memory 205844 kb
Host smart-afb51756-3848-4b6d-9f3d-1eefb342c33f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11645
88468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.1164588468
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.4082929379
Short name T1592
Test name
Test status
Simulation time 10130991710 ps
CPU time 12.81 seconds
Started Jun 07 08:47:42 PM PDT 24
Finished Jun 07 08:48:02 PM PDT 24
Peak memory 205744 kb
Host smart-dc02ebe2-5a77-48f4-935e-69e39a7f147a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40829
29379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.4082929379
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.166650315
Short name T1065
Test name
Test status
Simulation time 10080521877 ps
CPU time 13.4 seconds
Started Jun 07 08:47:43 PM PDT 24
Finished Jun 07 08:48:04 PM PDT 24
Peak memory 205856 kb
Host smart-51c36102-dc77-426d-9a76-c305e629668e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16665
0315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.166650315
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.2900588091
Short name T1045
Test name
Test status
Simulation time 13199814550 ps
CPU time 17.42 seconds
Started Jun 07 08:47:51 PM PDT 24
Finished Jun 07 08:48:15 PM PDT 24
Peak memory 205880 kb
Host smart-09c4283f-5425-43ea-8d51-3643af0f0459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29005
88091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.2900588091
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1733260177
Short name T1420
Test name
Test status
Simulation time 10114955985 ps
CPU time 14.52 seconds
Started Jun 07 08:47:46 PM PDT 24
Finished Jun 07 08:48:09 PM PDT 24
Peak memory 205852 kb
Host smart-6a11ff21-f69f-4d9c-a67f-9d63e876992a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17332
60177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1733260177
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.3411797216
Short name T1543
Test name
Test status
Simulation time 23232105527 ps
CPU time 395.28 seconds
Started Jun 07 08:47:57 PM PDT 24
Finished Jun 07 08:54:38 PM PDT 24
Peak memory 205804 kb
Host smart-a8b171e8-8afc-40c9-b69c-36ac21d9d6dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34117
97216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.3411797216
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1134965701
Short name T369
Test name
Test status
Simulation time 10079840173 ps
CPU time 13.11 seconds
Started Jun 07 08:47:58 PM PDT 24
Finished Jun 07 08:48:16 PM PDT 24
Peak memory 205808 kb
Host smart-5e87bf81-214f-4368-8ccd-e1b85e3d0453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11349
65701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1134965701
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.4058708866
Short name T121
Test name
Test status
Simulation time 10100466811 ps
CPU time 13.09 seconds
Started Jun 07 08:47:45 PM PDT 24
Finished Jun 07 08:48:06 PM PDT 24
Peak memory 205840 kb
Host smart-c8da6aaf-654a-4303-a6df-cd9ae2b39fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40587
08866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.4058708866
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.602895143
Short name T914
Test name
Test status
Simulation time 10063140081 ps
CPU time 12.87 seconds
Started Jun 07 08:47:43 PM PDT 24
Finished Jun 07 08:48:04 PM PDT 24
Peak memory 205804 kb
Host smart-a74c4472-76b0-461a-b8e7-648eac5dc4a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60289
5143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.602895143
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.4026393838
Short name T559
Test name
Test status
Simulation time 10070541083 ps
CPU time 14.61 seconds
Started Jun 07 08:47:44 PM PDT 24
Finished Jun 07 08:48:07 PM PDT 24
Peak memory 205776 kb
Host smart-a1dd2037-9c01-456e-b64e-602c6375b42c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40263
93838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.4026393838
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.2648987218
Short name T1609
Test name
Test status
Simulation time 10077167683 ps
CPU time 13.66 seconds
Started Jun 07 08:47:52 PM PDT 24
Finished Jun 07 08:48:12 PM PDT 24
Peak memory 205904 kb
Host smart-77e6e516-d49a-4238-a035-2491718823e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26489
87218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.2648987218
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.3948515038
Short name T1122
Test name
Test status
Simulation time 10062804353 ps
CPU time 13.61 seconds
Started Jun 07 08:47:47 PM PDT 24
Finished Jun 07 08:48:08 PM PDT 24
Peak memory 205776 kb
Host smart-a6ceed3c-4b5c-448c-9dae-e6a9f5791054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39485
15038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.3948515038
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_eop_single_bit_handling.3026964781
Short name T1881
Test name
Test status
Simulation time 10058984894 ps
CPU time 15.64 seconds
Started Jun 07 08:47:59 PM PDT 24
Finished Jun 07 08:48:19 PM PDT 24
Peak memory 205856 kb
Host smart-beb013ee-2f7b-4559-8779-2bdd89df543e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30269
64781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_eop_single_bit_handling.3026964781
Directory /workspace/44.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.234818563
Short name T41
Test name
Test status
Simulation time 10051322856 ps
CPU time 12.85 seconds
Started Jun 07 08:47:44 PM PDT 24
Finished Jun 07 08:48:05 PM PDT 24
Peak memory 205752 kb
Host smart-2b5a7a75-2800-44b0-978f-7cbd87a17e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23481
8563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.234818563
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3556642060
Short name T1185
Test name
Test status
Simulation time 10037929014 ps
CPU time 13.43 seconds
Started Jun 07 08:47:48 PM PDT 24
Finished Jun 07 08:48:09 PM PDT 24
Peak memory 205756 kb
Host smart-ab3605fd-4439-416c-83c8-953d225ccb06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35566
42060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3556642060
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2612529452
Short name T752
Test name
Test status
Simulation time 19554222361 ps
CPU time 34.52 seconds
Started Jun 07 08:47:45 PM PDT 24
Finished Jun 07 08:48:28 PM PDT 24
Peak memory 205768 kb
Host smart-9aa0b391-0faf-4e3f-adeb-21e8e8d3722d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26125
29452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2612529452
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.807081267
Short name T859
Test name
Test status
Simulation time 10094938056 ps
CPU time 13.46 seconds
Started Jun 07 08:47:51 PM PDT 24
Finished Jun 07 08:48:12 PM PDT 24
Peak memory 205912 kb
Host smart-1a591070-1f6f-441a-bda9-a0910c621e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80708
1267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.807081267
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.677918162
Short name T1118
Test name
Test status
Simulation time 10124688614 ps
CPU time 12.95 seconds
Started Jun 07 08:47:47 PM PDT 24
Finished Jun 07 08:48:08 PM PDT 24
Peak memory 205848 kb
Host smart-d2c96545-1b89-4433-b8fb-a6bdc397799c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67791
8162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.677918162
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.3437909399
Short name T1580
Test name
Test status
Simulation time 10052900104 ps
CPU time 13.51 seconds
Started Jun 07 08:47:48 PM PDT 24
Finished Jun 07 08:48:10 PM PDT 24
Peak memory 205744 kb
Host smart-758ac37a-0343-4496-8bb8-4f1821d15267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34379
09399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.3437909399
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.2463072178
Short name T999
Test name
Test status
Simulation time 10033134379 ps
CPU time 12.43 seconds
Started Jun 07 08:47:48 PM PDT 24
Finished Jun 07 08:48:08 PM PDT 24
Peak memory 205812 kb
Host smart-0d35b23b-f951-4005-8ddb-a80e1b009399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24630
72178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.2463072178
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.2987366690
Short name T1566
Test name
Test status
Simulation time 10080327397 ps
CPU time 13.6 seconds
Started Jun 07 08:47:58 PM PDT 24
Finished Jun 07 08:48:17 PM PDT 24
Peak memory 205880 kb
Host smart-ee628a97-e239-4a9a-9885-42041a9a096d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29873
66690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2987366690
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.2997812436
Short name T1337
Test name
Test status
Simulation time 10106663314 ps
CPU time 15.22 seconds
Started Jun 07 08:47:50 PM PDT 24
Finished Jun 07 08:48:13 PM PDT 24
Peak memory 205780 kb
Host smart-9a883490-9887-4944-9c65-6fee964026e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29978
12436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.2997812436
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.140762423
Short name T1278
Test name
Test status
Simulation time 10148685056 ps
CPU time 12.81 seconds
Started Jun 07 08:47:39 PM PDT 24
Finished Jun 07 08:47:59 PM PDT 24
Peak memory 205856 kb
Host smart-8204df3a-c8cb-4e3e-847e-7c6bfa80758f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14076
2423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.140762423
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2041012634
Short name T292
Test name
Test status
Simulation time 10079703084 ps
CPU time 15.5 seconds
Started Jun 07 08:47:49 PM PDT 24
Finished Jun 07 08:48:12 PM PDT 24
Peak memory 205808 kb
Host smart-1ebe452c-066a-437a-a9a7-e2c3d59cfbdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20410
12634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2041012634
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.1471213972
Short name T1895
Test name
Test status
Simulation time 10071608593 ps
CPU time 13.56 seconds
Started Jun 07 08:47:59 PM PDT 24
Finished Jun 07 08:48:17 PM PDT 24
Peak memory 205784 kb
Host smart-9e85ac8b-3213-453d-83cf-c13097a091b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14712
13972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.1471213972
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.1051942801
Short name T722
Test name
Test status
Simulation time 17130515829 ps
CPU time 215.09 seconds
Started Jun 07 08:47:43 PM PDT 24
Finished Jun 07 08:51:25 PM PDT 24
Peak memory 205824 kb
Host smart-15389eb3-2447-4b06-937f-8a4006faac67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10519
42801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.1051942801
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.3471986678
Short name T1293
Test name
Test status
Simulation time 10136995852 ps
CPU time 14.33 seconds
Started Jun 07 08:47:59 PM PDT 24
Finished Jun 07 08:48:18 PM PDT 24
Peak memory 205792 kb
Host smart-a307d4e4-82ec-45e3-b3d7-e43b692049dd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3471986678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.3471986678
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.3856360978
Short name T624
Test name
Test status
Simulation time 10071998976 ps
CPU time 12.48 seconds
Started Jun 07 08:47:52 PM PDT 24
Finished Jun 07 08:48:12 PM PDT 24
Peak memory 205876 kb
Host smart-fa59b76f-e60d-401e-8f94-c34ce109f68d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3856360978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.3856360978
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.289899040
Short name T1866
Test name
Test status
Simulation time 10154956613 ps
CPU time 14.15 seconds
Started Jun 07 08:47:54 PM PDT 24
Finished Jun 07 08:48:15 PM PDT 24
Peak memory 205876 kb
Host smart-692965a5-6ccf-4889-888b-4fa99a8d9913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28989
9040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.289899040
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.947418178
Short name T1855
Test name
Test status
Simulation time 14048304154 ps
CPU time 18.22 seconds
Started Jun 07 08:47:51 PM PDT 24
Finished Jun 07 08:48:16 PM PDT 24
Peak memory 205912 kb
Host smart-5cb5cc22-f146-4c4d-bc88-5be099886e6f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=947418178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.947418178
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.723758803
Short name T1512
Test name
Test status
Simulation time 23301042333 ps
CPU time 26.2 seconds
Started Jun 07 08:47:52 PM PDT 24
Finished Jun 07 08:48:25 PM PDT 24
Peak memory 205884 kb
Host smart-ae49873e-7521-48ec-b7a3-09089ded910f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=723758803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.723758803
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.1091847853
Short name T1883
Test name
Test status
Simulation time 10049815082 ps
CPU time 12.75 seconds
Started Jun 07 08:47:53 PM PDT 24
Finished Jun 07 08:48:12 PM PDT 24
Peak memory 205852 kb
Host smart-bcf3b289-267d-4747-9e18-cd8096c6a910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10918
47853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.1091847853
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.2327253165
Short name T952
Test name
Test status
Simulation time 10516149508 ps
CPU time 13.79 seconds
Started Jun 07 08:47:55 PM PDT 24
Finished Jun 07 08:48:15 PM PDT 24
Peak memory 205836 kb
Host smart-28f570b5-4b82-4422-8223-b6c47b45a581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23272
53165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.2327253165
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.3992742079
Short name T1494
Test name
Test status
Simulation time 10033317582 ps
CPU time 13.15 seconds
Started Jun 07 08:47:55 PM PDT 24
Finished Jun 07 08:48:14 PM PDT 24
Peak memory 205724 kb
Host smart-79efdc26-032d-443f-a6f2-89a367d61897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39927
42079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.3992742079
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.844196477
Short name T979
Test name
Test status
Simulation time 10065862269 ps
CPU time 13.08 seconds
Started Jun 07 08:47:55 PM PDT 24
Finished Jun 07 08:48:14 PM PDT 24
Peak memory 205808 kb
Host smart-c235cf27-2d27-479b-80de-717293ed4194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84419
6477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.844196477
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.1740567982
Short name T400
Test name
Test status
Simulation time 10610251304 ps
CPU time 15.05 seconds
Started Jun 07 08:48:07 PM PDT 24
Finished Jun 07 08:48:25 PM PDT 24
Peak memory 205716 kb
Host smart-47c9b464-7ac8-4fd4-a2d8-fc475924c882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17405
67982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.1740567982
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1836075823
Short name T1230
Test name
Test status
Simulation time 10089033474 ps
CPU time 15.26 seconds
Started Jun 07 08:47:53 PM PDT 24
Finished Jun 07 08:48:15 PM PDT 24
Peak memory 205728 kb
Host smart-2286ad7d-4b1d-4da6-b234-7774aaca4c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18360
75823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1836075823
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.29272681
Short name T1676
Test name
Test status
Simulation time 10182272997 ps
CPU time 14.89 seconds
Started Jun 07 08:47:56 PM PDT 24
Finished Jun 07 08:48:16 PM PDT 24
Peak memory 205848 kb
Host smart-8d5754a6-ed87-4b4d-bb40-49616f6a7103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29272
681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.29272681
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2526650200
Short name T1969
Test name
Test status
Simulation time 10115086096 ps
CPU time 13.41 seconds
Started Jun 07 08:47:53 PM PDT 24
Finished Jun 07 08:48:13 PM PDT 24
Peak memory 205744 kb
Host smart-fde39a88-bd23-4e01-95a6-261dd24e85fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25266
50200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2526650200
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.1838068243
Short name T770
Test name
Test status
Simulation time 10120875515 ps
CPU time 14.16 seconds
Started Jun 07 08:47:52 PM PDT 24
Finished Jun 07 08:48:13 PM PDT 24
Peak memory 205796 kb
Host smart-9b135d03-27c6-4b9d-bec6-027ba7137c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18380
68243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.1838068243
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.718218737
Short name T438
Test name
Test status
Simulation time 13209031526 ps
CPU time 16.55 seconds
Started Jun 07 08:47:52 PM PDT 24
Finished Jun 07 08:48:15 PM PDT 24
Peak memory 205844 kb
Host smart-16638b89-d76e-46d9-8236-a11bd2a51d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71821
8737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.718218737
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.4085280969
Short name T1218
Test name
Test status
Simulation time 10091454509 ps
CPU time 15.46 seconds
Started Jun 07 08:47:58 PM PDT 24
Finished Jun 07 08:48:19 PM PDT 24
Peak memory 205720 kb
Host smart-4e5a9582-875c-4081-8221-09bb8e55f313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40852
80969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.4085280969
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.3323219173
Short name T399
Test name
Test status
Simulation time 17059103364 ps
CPU time 211.07 seconds
Started Jun 07 08:47:52 PM PDT 24
Finished Jun 07 08:51:30 PM PDT 24
Peak memory 205728 kb
Host smart-848a86a1-85b5-4471-8fdc-0a7711f1a064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33232
19173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.3323219173
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.1393302438
Short name T862
Test name
Test status
Simulation time 10101974354 ps
CPU time 13.39 seconds
Started Jun 07 08:47:53 PM PDT 24
Finished Jun 07 08:48:13 PM PDT 24
Peak memory 205820 kb
Host smart-549ecc18-e452-4a81-86e4-3b2b48d86fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13933
02438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.1393302438
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2049019337
Short name T1834
Test name
Test status
Simulation time 10125695103 ps
CPU time 15.79 seconds
Started Jun 07 08:47:57 PM PDT 24
Finished Jun 07 08:48:18 PM PDT 24
Peak memory 205872 kb
Host smart-8c646c29-273e-4404-9b11-ad2e933a4e6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20490
19337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2049019337
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.3703859384
Short name T78
Test name
Test status
Simulation time 10082008382 ps
CPU time 15.3 seconds
Started Jun 07 08:47:53 PM PDT 24
Finished Jun 07 08:48:15 PM PDT 24
Peak memory 205876 kb
Host smart-b4cdffe9-1801-449e-b5ec-bc52d2907175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37038
59384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.3703859384
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.3441966163
Short name T345
Test name
Test status
Simulation time 10095475440 ps
CPU time 13.09 seconds
Started Jun 07 08:47:53 PM PDT 24
Finished Jun 07 08:48:13 PM PDT 24
Peak memory 205908 kb
Host smart-f4327b98-cebc-459b-a37a-142a420e2b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34419
66163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.3441966163
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.754593144
Short name T1877
Test name
Test status
Simulation time 10073244164 ps
CPU time 14.72 seconds
Started Jun 07 08:47:50 PM PDT 24
Finished Jun 07 08:48:12 PM PDT 24
Peak memory 205776 kb
Host smart-056ea194-7301-4dd8-8360-aee7170821b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75459
3144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.754593144
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1594261102
Short name T827
Test name
Test status
Simulation time 10062297965 ps
CPU time 13.65 seconds
Started Jun 07 08:47:54 PM PDT 24
Finished Jun 07 08:48:14 PM PDT 24
Peak memory 205728 kb
Host smart-ffc81841-2974-499a-8e03-37db4667485f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15942
61102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1594261102
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_eop_single_bit_handling.2201274702
Short name T29
Test name
Test status
Simulation time 10056121686 ps
CPU time 12.16 seconds
Started Jun 07 08:47:53 PM PDT 24
Finished Jun 07 08:48:12 PM PDT 24
Peak memory 205884 kb
Host smart-1bc55ad6-6cd3-483a-a49e-9bdece3b04b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22012
74702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_eop_single_bit_handling.2201274702
Directory /workspace/45.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3273250848
Short name T1222
Test name
Test status
Simulation time 10083834369 ps
CPU time 12.89 seconds
Started Jun 07 08:48:01 PM PDT 24
Finished Jun 07 08:48:17 PM PDT 24
Peak memory 205860 kb
Host smart-d7df4689-f8ae-41ad-b22d-d7e0f7eac0f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32732
50848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.3273250848
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.1319565028
Short name T1768
Test name
Test status
Simulation time 10056636077 ps
CPU time 14.59 seconds
Started Jun 07 08:47:54 PM PDT 24
Finished Jun 07 08:48:15 PM PDT 24
Peak memory 205868 kb
Host smart-46751f50-e678-4f3d-97a9-00c6db222f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13195
65028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.1319565028
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.2885361949
Short name T1380
Test name
Test status
Simulation time 22709101728 ps
CPU time 44.33 seconds
Started Jun 07 08:47:54 PM PDT 24
Finished Jun 07 08:48:45 PM PDT 24
Peak memory 205772 kb
Host smart-81d9d825-8de8-494e-8e30-342f21500bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28853
61949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.2885361949
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.209251420
Short name T939
Test name
Test status
Simulation time 10120280904 ps
CPU time 16.59 seconds
Started Jun 07 08:47:56 PM PDT 24
Finished Jun 07 08:48:19 PM PDT 24
Peak memory 205772 kb
Host smart-258dc38d-0834-477a-b395-70bca0989bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20925
1420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.209251420
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.651158807
Short name T1211
Test name
Test status
Simulation time 10138473426 ps
CPU time 16.17 seconds
Started Jun 07 08:47:51 PM PDT 24
Finished Jun 07 08:48:14 PM PDT 24
Peak memory 205836 kb
Host smart-1043c226-1bf5-46bb-a40f-c6615b21e0a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65115
8807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.651158807
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.1274907605
Short name T853
Test name
Test status
Simulation time 10128055862 ps
CPU time 12.85 seconds
Started Jun 07 08:47:55 PM PDT 24
Finished Jun 07 08:48:14 PM PDT 24
Peak memory 205848 kb
Host smart-9e9bc340-6e2e-4168-b74c-6f3e79863957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12749
07605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.1274907605
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.627633464
Short name T978
Test name
Test status
Simulation time 10042528451 ps
CPU time 15.42 seconds
Started Jun 07 08:47:55 PM PDT 24
Finished Jun 07 08:48:17 PM PDT 24
Peak memory 205856 kb
Host smart-94c6e638-33ed-4ed4-a281-5f0e3cc78cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62763
3464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.627633464
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.4253936799
Short name T598
Test name
Test status
Simulation time 10058376519 ps
CPU time 15.21 seconds
Started Jun 07 08:47:52 PM PDT 24
Finished Jun 07 08:48:14 PM PDT 24
Peak memory 205828 kb
Host smart-62207b4e-479e-430b-ba2c-7337fd7ed741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42539
36799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.4253936799
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.695811643
Short name T1514
Test name
Test status
Simulation time 10096750225 ps
CPU time 13.47 seconds
Started Jun 07 08:47:52 PM PDT 24
Finished Jun 07 08:48:12 PM PDT 24
Peak memory 205944 kb
Host smart-a90b279e-12f3-4aed-920d-dba7d4129711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69581
1643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.695811643
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2517496663
Short name T1254
Test name
Test status
Simulation time 10124242496 ps
CPU time 15.82 seconds
Started Jun 07 08:47:43 PM PDT 24
Finished Jun 07 08:48:06 PM PDT 24
Peak memory 205824 kb
Host smart-1311803b-5113-4979-9c0a-539e7ca2cf6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25174
96663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2517496663
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.1388982837
Short name T1283
Test name
Test status
Simulation time 10057106218 ps
CPU time 13.77 seconds
Started Jun 07 08:47:56 PM PDT 24
Finished Jun 07 08:48:16 PM PDT 24
Peak memory 205776 kb
Host smart-59359b21-5d43-4d32-895a-121299211f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13889
82837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.1388982837
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.438722624
Short name T714
Test name
Test status
Simulation time 10052730516 ps
CPU time 14.17 seconds
Started Jun 07 08:47:53 PM PDT 24
Finished Jun 07 08:48:14 PM PDT 24
Peak memory 205864 kb
Host smart-ab820a64-ce1b-4ebe-9691-ad75033f293c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43872
2624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.438722624
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.1115404820
Short name T773
Test name
Test status
Simulation time 23246977639 ps
CPU time 104.5 seconds
Started Jun 07 08:47:58 PM PDT 24
Finished Jun 07 08:49:48 PM PDT 24
Peak memory 205828 kb
Host smart-0524aef3-ca00-45f9-81f3-4b80a7ef3b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11154
04820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.1115404820
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.2211972693
Short name T1325
Test name
Test status
Simulation time 10167771071 ps
CPU time 13.86 seconds
Started Jun 07 08:47:58 PM PDT 24
Finished Jun 07 08:48:17 PM PDT 24
Peak memory 205828 kb
Host smart-9e54d59e-81ee-4bc7-8f98-22f3efcac853
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2211972693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.2211972693
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.3821845005
Short name T858
Test name
Test status
Simulation time 10060562718 ps
CPU time 13.09 seconds
Started Jun 07 08:48:01 PM PDT 24
Finished Jun 07 08:48:18 PM PDT 24
Peak memory 205884 kb
Host smart-e1fb47c6-fc5a-48f8-bea1-1a4c86f6cc7c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3821845005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.3821845005
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.1803186191
Short name T1484
Test name
Test status
Simulation time 10131051306 ps
CPU time 16.72 seconds
Started Jun 07 08:48:01 PM PDT 24
Finished Jun 07 08:48:21 PM PDT 24
Peak memory 205936 kb
Host smart-e5459c06-89ad-49c8-9b67-a3f9a88c6306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18031
86191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.1803186191
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.2833533401
Short name T1111
Test name
Test status
Simulation time 14169696494 ps
CPU time 18.86 seconds
Started Jun 07 08:47:55 PM PDT 24
Finished Jun 07 08:48:20 PM PDT 24
Peak memory 205860 kb
Host smart-05adb588-92e5-4beb-bd4a-976a7660fe12
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2833533401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.2833533401
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.3379140345
Short name T1194
Test name
Test status
Simulation time 23228423014 ps
CPU time 31.59 seconds
Started Jun 07 08:47:57 PM PDT 24
Finished Jun 07 08:48:34 PM PDT 24
Peak memory 205824 kb
Host smart-b6c04869-ea48-4ed5-93e4-9907fe57d1ca
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3379140345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.3379140345
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.4061984003
Short name T1055
Test name
Test status
Simulation time 10079131399 ps
CPU time 13.54 seconds
Started Jun 07 08:47:54 PM PDT 24
Finished Jun 07 08:48:14 PM PDT 24
Peak memory 205764 kb
Host smart-3812ceea-dc7a-45ce-8b56-b9215a32fdf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40619
84003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.4061984003
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.904090225
Short name T518
Test name
Test status
Simulation time 10063642494 ps
CPU time 13.99 seconds
Started Jun 07 08:47:56 PM PDT 24
Finished Jun 07 08:48:16 PM PDT 24
Peak memory 205884 kb
Host smart-3963cffc-2836-4151-ae7b-d65c5a454155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90409
0225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.904090225
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.2714118648
Short name T566
Test name
Test status
Simulation time 10624252596 ps
CPU time 14.66 seconds
Started Jun 07 08:48:07 PM PDT 24
Finished Jun 07 08:48:24 PM PDT 24
Peak memory 205776 kb
Host smart-504b2a57-4b4c-4da8-8bf3-fec70b10862a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27141
18648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.2714118648
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.3199697993
Short name T1394
Test name
Test status
Simulation time 10037268319 ps
CPU time 14.28 seconds
Started Jun 07 08:47:54 PM PDT 24
Finished Jun 07 08:48:14 PM PDT 24
Peak memory 205736 kb
Host smart-c6390d1f-94b7-417d-b0fb-636717c3593a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31996
97993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.3199697993
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.3859278616
Short name T945
Test name
Test status
Simulation time 10070607616 ps
CPU time 15.59 seconds
Started Jun 07 08:47:58 PM PDT 24
Finished Jun 07 08:48:19 PM PDT 24
Peak memory 205836 kb
Host smart-030dfb9a-eda8-4ebd-9bbf-e97831a0af06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38592
78616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3859278616
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.201376647
Short name T1358
Test name
Test status
Simulation time 10803929896 ps
CPU time 16.51 seconds
Started Jun 07 08:47:55 PM PDT 24
Finished Jun 07 08:48:18 PM PDT 24
Peak memory 205884 kb
Host smart-df4d0dc0-4357-49d5-b306-1cc93905139c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20137
6647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.201376647
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.1924381318
Short name T1142
Test name
Test status
Simulation time 10138329171 ps
CPU time 14.65 seconds
Started Jun 07 08:47:52 PM PDT 24
Finished Jun 07 08:48:14 PM PDT 24
Peak memory 205836 kb
Host smart-bd830f96-87aa-491e-b12c-f473fbee73fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19243
81318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.1924381318
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.1393729066
Short name T973
Test name
Test status
Simulation time 10157254995 ps
CPU time 12.98 seconds
Started Jun 07 08:48:07 PM PDT 24
Finished Jun 07 08:48:22 PM PDT 24
Peak memory 205812 kb
Host smart-974e974b-1f2a-4cee-852b-4c0f8b1b71af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13937
29066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.1393729066
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.2852607502
Short name T1384
Test name
Test status
Simulation time 10044340002 ps
CPU time 14.12 seconds
Started Jun 07 08:48:01 PM PDT 24
Finished Jun 07 08:48:19 PM PDT 24
Peak memory 205820 kb
Host smart-b403e4d5-72fc-421b-947c-e558e937a80b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28526
07502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.2852607502
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.2413831752
Short name T1395
Test name
Test status
Simulation time 10110220189 ps
CPU time 14.56 seconds
Started Jun 07 08:47:57 PM PDT 24
Finished Jun 07 08:48:17 PM PDT 24
Peak memory 205864 kb
Host smart-af027ad0-bfb4-4911-965a-d79b6e5e7e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24138
31752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.2413831752
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.3671837368
Short name T350
Test name
Test status
Simulation time 10104960049 ps
CPU time 13.54 seconds
Started Jun 07 08:47:59 PM PDT 24
Finished Jun 07 08:48:17 PM PDT 24
Peak memory 205764 kb
Host smart-085f7afb-57c4-4039-92aa-56583802d78b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36718
37368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.3671837368
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.836585993
Short name T1281
Test name
Test status
Simulation time 13212325690 ps
CPU time 15.28 seconds
Started Jun 07 08:47:58 PM PDT 24
Finished Jun 07 08:48:19 PM PDT 24
Peak memory 205712 kb
Host smart-1c662fcb-ed56-45d8-b61c-480b36c4d867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83658
5993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.836585993
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.169977391
Short name T510
Test name
Test status
Simulation time 10142725067 ps
CPU time 13.43 seconds
Started Jun 07 08:47:59 PM PDT 24
Finished Jun 07 08:48:17 PM PDT 24
Peak memory 205848 kb
Host smart-f3ffad86-0f0b-43fa-bfc9-ce9e0aa49eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16997
7391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.169977391
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.1975855835
Short name T1244
Test name
Test status
Simulation time 15757383070 ps
CPU time 56.25 seconds
Started Jun 07 08:47:59 PM PDT 24
Finished Jun 07 08:49:00 PM PDT 24
Peak memory 205848 kb
Host smart-417000c1-3afb-41d6-b6c9-b2df7f7e815e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19758
55835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.1975855835
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3250344922
Short name T1054
Test name
Test status
Simulation time 10072821111 ps
CPU time 13.17 seconds
Started Jun 07 08:47:53 PM PDT 24
Finished Jun 07 08:48:13 PM PDT 24
Peak memory 205860 kb
Host smart-0402de43-be47-45e8-9b97-d94c4b89b2a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32503
44922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3250344922
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.2076511006
Short name T96
Test name
Test status
Simulation time 10097992829 ps
CPU time 14.12 seconds
Started Jun 07 08:47:59 PM PDT 24
Finished Jun 07 08:48:18 PM PDT 24
Peak memory 205848 kb
Host smart-fc7ab815-09e4-48a4-8a78-cc9c3fd6550f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20765
11006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.2076511006
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.946925391
Short name T879
Test name
Test status
Simulation time 10062030825 ps
CPU time 13.05 seconds
Started Jun 07 08:47:59 PM PDT 24
Finished Jun 07 08:48:17 PM PDT 24
Peak memory 205880 kb
Host smart-6c0efd2d-3718-458b-ae7a-1eac600cff41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94692
5391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.946925391
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.561149853
Short name T1447
Test name
Test status
Simulation time 10055097508 ps
CPU time 16.31 seconds
Started Jun 07 08:47:58 PM PDT 24
Finished Jun 07 08:48:19 PM PDT 24
Peak memory 205864 kb
Host smart-0389650e-7eab-4a58-99cc-2eebc6255acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56114
9853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.561149853
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1477600363
Short name T23
Test name
Test status
Simulation time 10063033241 ps
CPU time 13.04 seconds
Started Jun 07 08:48:01 PM PDT 24
Finished Jun 07 08:48:18 PM PDT 24
Peak memory 205840 kb
Host smart-36946968-de2d-44ce-89fa-de016fea7dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14776
00363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1477600363
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.3791005101
Short name T1365
Test name
Test status
Simulation time 10116779380 ps
CPU time 14.72 seconds
Started Jun 07 08:47:59 PM PDT 24
Finished Jun 07 08:48:18 PM PDT 24
Peak memory 205804 kb
Host smart-6d35d4a5-978d-4147-a103-3d205c140b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37910
05101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.3791005101
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_eop_single_bit_handling.789066913
Short name T1752
Test name
Test status
Simulation time 10113583838 ps
CPU time 13.76 seconds
Started Jun 07 08:47:59 PM PDT 24
Finished Jun 07 08:48:18 PM PDT 24
Peak memory 205808 kb
Host smart-cb22b1a0-65f3-4df4-b0c7-846c562629cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78906
6913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_eop_single_bit_handling.789066913
Directory /workspace/46.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.2674797473
Short name T1239
Test name
Test status
Simulation time 10117945552 ps
CPU time 12.43 seconds
Started Jun 07 08:47:59 PM PDT 24
Finished Jun 07 08:48:16 PM PDT 24
Peak memory 205724 kb
Host smart-1b048af4-2a18-44f9-8d17-0ea35beab8fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26747
97473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.2674797473
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3777394800
Short name T421
Test name
Test status
Simulation time 10085678984 ps
CPU time 12.7 seconds
Started Jun 07 08:48:02 PM PDT 24
Finished Jun 07 08:48:18 PM PDT 24
Peak memory 205728 kb
Host smart-7f221c26-ae02-4286-bc2c-98295abb8fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37773
94800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3777394800
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.1580694406
Short name T2011
Test name
Test status
Simulation time 16739268866 ps
CPU time 26.45 seconds
Started Jun 07 08:48:00 PM PDT 24
Finished Jun 07 08:48:31 PM PDT 24
Peak memory 205764 kb
Host smart-47be8526-a20b-4d4a-a3e3-b28f09f3fe45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15806
94406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.1580694406
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.1344841894
Short name T2004
Test name
Test status
Simulation time 10088300945 ps
CPU time 14.85 seconds
Started Jun 07 08:48:02 PM PDT 24
Finished Jun 07 08:48:20 PM PDT 24
Peak memory 205848 kb
Host smart-7dc13773-58a4-478b-bc15-94589cd11328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13448
41894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.1344841894
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.1615108254
Short name T1928
Test name
Test status
Simulation time 10172387154 ps
CPU time 15.07 seconds
Started Jun 07 08:48:07 PM PDT 24
Finished Jun 07 08:48:25 PM PDT 24
Peak memory 205844 kb
Host smart-be8dbd71-6cff-41ec-9810-ff354e3d6fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16151
08254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.1615108254
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.1099092666
Short name T750
Test name
Test status
Simulation time 10053301633 ps
CPU time 13.4 seconds
Started Jun 07 08:48:07 PM PDT 24
Finished Jun 07 08:48:23 PM PDT 24
Peak memory 205656 kb
Host smart-2767d15a-7f63-4164-9488-6919710c48f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10990
92666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.1099092666
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.3035228439
Short name T317
Test name
Test status
Simulation time 10035892447 ps
CPU time 12.69 seconds
Started Jun 07 08:47:59 PM PDT 24
Finished Jun 07 08:48:17 PM PDT 24
Peak memory 205764 kb
Host smart-296dbfc2-bc95-4f46-8e3e-519f192fbe90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30352
28439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.3035228439
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.3288493904
Short name T1813
Test name
Test status
Simulation time 10052435636 ps
CPU time 15.23 seconds
Started Jun 07 08:48:06 PM PDT 24
Finished Jun 07 08:48:24 PM PDT 24
Peak memory 205576 kb
Host smart-44717d53-d519-408f-a73c-b85ec83af4ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32884
93904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.3288493904
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.976567530
Short name T1951
Test name
Test status
Simulation time 10047931443 ps
CPU time 14.61 seconds
Started Jun 07 08:48:07 PM PDT 24
Finished Jun 07 08:48:24 PM PDT 24
Peak memory 205712 kb
Host smart-2a40dedf-558f-4a5f-9165-00ad6cafc636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97656
7530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.976567530
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.1397089662
Short name T130
Test name
Test status
Simulation time 10144485763 ps
CPU time 13.38 seconds
Started Jun 07 08:47:54 PM PDT 24
Finished Jun 07 08:48:14 PM PDT 24
Peak memory 205748 kb
Host smart-c9310536-d421-4eef-bc42-d6f2d94872e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13970
89662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.1397089662
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.828638737
Short name T413
Test name
Test status
Simulation time 10093961960 ps
CPU time 15.58 seconds
Started Jun 07 08:47:58 PM PDT 24
Finished Jun 07 08:48:18 PM PDT 24
Peak memory 205856 kb
Host smart-e515a39f-1d9c-45bd-bd50-1bd7230dc821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82863
8737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.828638737
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.1046892044
Short name T613
Test name
Test status
Simulation time 10076618084 ps
CPU time 14.59 seconds
Started Jun 07 08:47:59 PM PDT 24
Finished Jun 07 08:48:18 PM PDT 24
Peak memory 205948 kb
Host smart-85c1abae-4114-49b3-8274-5136aed78492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10468
92044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1046892044
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.3149332849
Short name T1682
Test name
Test status
Simulation time 18360632058 ps
CPU time 74.18 seconds
Started Jun 07 08:47:59 PM PDT 24
Finished Jun 07 08:49:18 PM PDT 24
Peak memory 205904 kb
Host smart-c4cba5c2-d809-4265-9a2e-a17a04d30411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31493
32849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.3149332849
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.3652522749
Short name T1333
Test name
Test status
Simulation time 10142419238 ps
CPU time 14.48 seconds
Started Jun 07 08:48:06 PM PDT 24
Finished Jun 07 08:48:22 PM PDT 24
Peak memory 205876 kb
Host smart-d7d93b8d-977c-43e0-923f-fda359efb071
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3652522749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.3652522749
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.53005922
Short name T1785
Test name
Test status
Simulation time 10054970262 ps
CPU time 16.5 seconds
Started Jun 07 08:48:11 PM PDT 24
Finished Jun 07 08:48:28 PM PDT 24
Peak memory 205728 kb
Host smart-a2bb1281-683d-42e9-8bd4-f2360fe19aef
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=53005922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.53005922
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.3467935811
Short name T523
Test name
Test status
Simulation time 10134670243 ps
CPU time 13.25 seconds
Started Jun 07 08:48:09 PM PDT 24
Finished Jun 07 08:48:24 PM PDT 24
Peak memory 205804 kb
Host smart-7778c32d-7d74-4dc7-8cbb-5eea61412b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34679
35811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.3467935811
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.2529668719
Short name T9
Test name
Test status
Simulation time 14041740325 ps
CPU time 19.43 seconds
Started Jun 07 08:48:02 PM PDT 24
Finished Jun 07 08:48:24 PM PDT 24
Peak memory 205884 kb
Host smart-104e77ae-2a2d-4b38-a76e-1549d5c9b72e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2529668719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.2529668719
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.224664370
Short name T1657
Test name
Test status
Simulation time 23242533627 ps
CPU time 24.95 seconds
Started Jun 07 08:47:59 PM PDT 24
Finished Jun 07 08:48:29 PM PDT 24
Peak memory 205944 kb
Host smart-f69bb003-266b-4a04-b262-f1b73b679f90
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=224664370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.224664370
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2466559013
Short name T526
Test name
Test status
Simulation time 10095948836 ps
CPU time 13.72 seconds
Started Jun 07 08:48:03 PM PDT 24
Finished Jun 07 08:48:19 PM PDT 24
Peak memory 205844 kb
Host smart-4a2ad152-be57-4678-b599-e78b5f5ac72b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24665
59013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2466559013
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.1213843953
Short name T344
Test name
Test status
Simulation time 10317685680 ps
CPU time 13.92 seconds
Started Jun 07 08:48:07 PM PDT 24
Finished Jun 07 08:48:23 PM PDT 24
Peak memory 205872 kb
Host smart-fe8a5fc9-4fe8-44d8-a38f-f36b03cf0ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12138
43953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.1213843953
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.4217710519
Short name T2022
Test name
Test status
Simulation time 10042705293 ps
CPU time 13.29 seconds
Started Jun 07 08:48:00 PM PDT 24
Finished Jun 07 08:48:18 PM PDT 24
Peak memory 205720 kb
Host smart-674d4511-21ee-4997-bd4a-ee84c8cbf3a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42177
10519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.4217710519
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.2957300577
Short name T828
Test name
Test status
Simulation time 10057677224 ps
CPU time 16.46 seconds
Started Jun 07 08:48:06 PM PDT 24
Finished Jun 07 08:48:24 PM PDT 24
Peak memory 205728 kb
Host smart-f451d090-828a-4b10-a93a-7da287b75d4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29573
00577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2957300577
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.2738244724
Short name T1696
Test name
Test status
Simulation time 10773188374 ps
CPU time 15.47 seconds
Started Jun 07 08:48:07 PM PDT 24
Finished Jun 07 08:48:25 PM PDT 24
Peak memory 205828 kb
Host smart-e286bb69-8e6e-451e-84c7-9889e12df3a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27382
44724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.2738244724
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3788271070
Short name T1350
Test name
Test status
Simulation time 10243570216 ps
CPU time 14.84 seconds
Started Jun 07 08:48:00 PM PDT 24
Finished Jun 07 08:48:19 PM PDT 24
Peak memory 205804 kb
Host smart-66a85a90-c89a-43dc-ac0a-9deb1acad0f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37882
71070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3788271070
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.1022011372
Short name T480
Test name
Test status
Simulation time 10191720896 ps
CPU time 15.59 seconds
Started Jun 07 08:48:08 PM PDT 24
Finished Jun 07 08:48:26 PM PDT 24
Peak memory 205852 kb
Host smart-d1fdbb7d-2bd9-413d-a139-1e892568da3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10220
11372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.1022011372
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.3189670037
Short name T2032
Test name
Test status
Simulation time 10095892328 ps
CPU time 14.87 seconds
Started Jun 07 08:48:06 PM PDT 24
Finished Jun 07 08:48:24 PM PDT 24
Peak memory 205760 kb
Host smart-271c7f36-a1ab-4e9e-ad10-abcc0afd6c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31896
70037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.3189670037
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.443035767
Short name T809
Test name
Test status
Simulation time 10077918266 ps
CPU time 14.36 seconds
Started Jun 07 08:47:58 PM PDT 24
Finished Jun 07 08:48:18 PM PDT 24
Peak memory 205768 kb
Host smart-a91ce118-e974-4b98-8a7b-adce5c20d665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44303
5767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.443035767
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.2961859435
Short name T1415
Test name
Test status
Simulation time 10124422668 ps
CPU time 13.51 seconds
Started Jun 07 08:48:07 PM PDT 24
Finished Jun 07 08:48:23 PM PDT 24
Peak memory 205768 kb
Host smart-b9f5c086-c72a-4069-92f7-d0c7db671e54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29618
59435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.2961859435
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.1380466234
Short name T1911
Test name
Test status
Simulation time 13173974949 ps
CPU time 17.72 seconds
Started Jun 07 08:48:06 PM PDT 24
Finished Jun 07 08:48:26 PM PDT 24
Peak memory 205852 kb
Host smart-987e12f1-869e-435b-a362-558f9c497732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13804
66234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.1380466234
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.3401716608
Short name T760
Test name
Test status
Simulation time 10093589743 ps
CPU time 13.37 seconds
Started Jun 07 08:48:07 PM PDT 24
Finished Jun 07 08:48:23 PM PDT 24
Peak memory 205788 kb
Host smart-aa5ddd52-48b3-4d50-8856-7b168335c338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34017
16608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.3401716608
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.2629834116
Short name T6
Test name
Test status
Simulation time 15934602883 ps
CPU time 175.91 seconds
Started Jun 07 08:48:07 PM PDT 24
Finished Jun 07 08:51:06 PM PDT 24
Peak memory 205688 kb
Host smart-2be474aa-903f-441b-92b5-1a7e1b3303f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26298
34116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.2629834116
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.1970995276
Short name T855
Test name
Test status
Simulation time 10077743617 ps
CPU time 14.8 seconds
Started Jun 07 08:48:07 PM PDT 24
Finished Jun 07 08:48:25 PM PDT 24
Peak memory 205720 kb
Host smart-8a86667d-77c1-4c23-a888-ccb95430c40e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19709
95276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.1970995276
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.563711962
Short name T1498
Test name
Test status
Simulation time 10105721706 ps
CPU time 15.09 seconds
Started Jun 07 08:48:06 PM PDT 24
Finished Jun 07 08:48:24 PM PDT 24
Peak memory 205764 kb
Host smart-e6ce4ad5-3b33-4848-bed2-af2b5a18065f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56371
1962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.563711962
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.3759604007
Short name T1601
Test name
Test status
Simulation time 10088847290 ps
CPU time 13.95 seconds
Started Jun 07 08:48:05 PM PDT 24
Finished Jun 07 08:48:20 PM PDT 24
Peak memory 205820 kb
Host smart-577e0431-d840-4cc9-ad4e-163252d7b48c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37596
04007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.3759604007
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.4148916879
Short name T720
Test name
Test status
Simulation time 10083874131 ps
CPU time 13.25 seconds
Started Jun 07 08:48:06 PM PDT 24
Finished Jun 07 08:48:22 PM PDT 24
Peak memory 205608 kb
Host smart-90e91f01-ceda-4580-a47e-383175b82849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41489
16879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.4148916879
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.753198127
Short name T1313
Test name
Test status
Simulation time 10094792449 ps
CPU time 13.58 seconds
Started Jun 07 08:48:11 PM PDT 24
Finished Jun 07 08:48:26 PM PDT 24
Peak memory 205740 kb
Host smart-bae003ba-59f9-4540-8db1-585e88fe289a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75319
8127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.753198127
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.3664421897
Short name T567
Test name
Test status
Simulation time 10078398677 ps
CPU time 12.7 seconds
Started Jun 07 08:48:06 PM PDT 24
Finished Jun 07 08:48:20 PM PDT 24
Peak memory 205876 kb
Host smart-d9ba7c87-10d9-4e6a-8ebd-ab43022a6e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36644
21897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.3664421897
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_eop_single_bit_handling.267899003
Short name T1804
Test name
Test status
Simulation time 10055797199 ps
CPU time 13.14 seconds
Started Jun 07 08:48:07 PM PDT 24
Finished Jun 07 08:48:23 PM PDT 24
Peak memory 205768 kb
Host smart-c7774d9c-655c-4d87-92a4-f97068a88012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26789
9003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_eop_single_bit_handling.267899003
Directory /workspace/47.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.3766823545
Short name T511
Test name
Test status
Simulation time 10052932877 ps
CPU time 13.97 seconds
Started Jun 07 08:48:06 PM PDT 24
Finished Jun 07 08:48:22 PM PDT 24
Peak memory 205792 kb
Host smart-2b30c057-89d9-4e6f-96a5-50be9d73eba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37668
23545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.3766823545
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.1242536675
Short name T1314
Test name
Test status
Simulation time 10050601076 ps
CPU time 15.27 seconds
Started Jun 07 08:48:13 PM PDT 24
Finished Jun 07 08:48:29 PM PDT 24
Peak memory 205808 kb
Host smart-41dc8aba-9884-4425-9054-a248d1acac05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12425
36675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.1242536675
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.3195980546
Short name T43
Test name
Test status
Simulation time 27295958445 ps
CPU time 51.21 seconds
Started Jun 07 08:48:06 PM PDT 24
Finished Jun 07 08:48:59 PM PDT 24
Peak memory 205896 kb
Host smart-9b7b1617-ee4f-4ea8-81ea-41b74b41cb71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31959
80546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.3195980546
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1040712687
Short name T1960
Test name
Test status
Simulation time 10060602967 ps
CPU time 13.15 seconds
Started Jun 07 08:48:06 PM PDT 24
Finished Jun 07 08:48:21 PM PDT 24
Peak memory 205880 kb
Host smart-8c173fe4-e0a3-447d-9e3c-d18420c6ac8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10407
12687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1040712687
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.348998827
Short name T1224
Test name
Test status
Simulation time 10075389855 ps
CPU time 14.43 seconds
Started Jun 07 08:48:06 PM PDT 24
Finished Jun 07 08:48:22 PM PDT 24
Peak memory 205688 kb
Host smart-ad737a14-9c00-4782-9aec-61c99cd63fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34899
8827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.348998827
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.2913055181
Short name T351
Test name
Test status
Simulation time 10066293335 ps
CPU time 13.38 seconds
Started Jun 07 08:48:08 PM PDT 24
Finished Jun 07 08:48:24 PM PDT 24
Peak memory 205884 kb
Host smart-aa5f021a-af92-4d69-955a-ab3279a21dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29130
55181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.2913055181
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.357873641
Short name T1587
Test name
Test status
Simulation time 10066850457 ps
CPU time 16.31 seconds
Started Jun 07 08:48:09 PM PDT 24
Finished Jun 07 08:48:27 PM PDT 24
Peak memory 205780 kb
Host smart-1cb41f0d-104e-497b-8386-3cfa499f025a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35787
3641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.357873641
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.953456919
Short name T1598
Test name
Test status
Simulation time 10055873049 ps
CPU time 13.85 seconds
Started Jun 07 08:48:05 PM PDT 24
Finished Jun 07 08:48:21 PM PDT 24
Peak memory 205816 kb
Host smart-4665e404-e109-4b96-8caf-5c800c226445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95345
6919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.953456919
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.3567154322
Short name T609
Test name
Test status
Simulation time 10057560868 ps
CPU time 12.66 seconds
Started Jun 07 08:48:06 PM PDT 24
Finished Jun 07 08:48:21 PM PDT 24
Peak memory 205860 kb
Host smart-6f797461-428e-473d-9b5b-9c0e3eb6635b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35671
54322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.3567154322
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.190651339
Short name T154
Test name
Test status
Simulation time 10118369929 ps
CPU time 12.59 seconds
Started Jun 07 08:48:06 PM PDT 24
Finished Jun 07 08:48:21 PM PDT 24
Peak memory 205784 kb
Host smart-29182317-6aac-49c8-93ef-5d526dc9512b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19065
1339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.190651339
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.2835263268
Short name T1863
Test name
Test status
Simulation time 10075188255 ps
CPU time 12.85 seconds
Started Jun 07 08:48:08 PM PDT 24
Finished Jun 07 08:48:24 PM PDT 24
Peak memory 205780 kb
Host smart-61ab0546-dd3f-4261-bf7c-d4bad1ca6d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28352
63268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.2835263268
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.716425320
Short name T1044
Test name
Test status
Simulation time 10115875630 ps
CPU time 13.71 seconds
Started Jun 07 08:48:08 PM PDT 24
Finished Jun 07 08:48:24 PM PDT 24
Peak memory 205760 kb
Host smart-66c15502-1622-4778-b967-1e01948a5ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71642
5320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.716425320
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.1311037687
Short name T1223
Test name
Test status
Simulation time 15884388235 ps
CPU time 187.2 seconds
Started Jun 07 08:48:06 PM PDT 24
Finished Jun 07 08:51:15 PM PDT 24
Peak memory 205776 kb
Host smart-73623e93-bec3-4db0-99b8-196c0df18851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13110
37687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.1311037687
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.2944662305
Short name T465
Test name
Test status
Simulation time 10161573628 ps
CPU time 12.78 seconds
Started Jun 07 08:48:42 PM PDT 24
Finished Jun 07 08:49:00 PM PDT 24
Peak memory 205900 kb
Host smart-858d5764-89da-4585-bd76-c1cfbac00cd4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2944662305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.2944662305
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.3239239773
Short name T1027
Test name
Test status
Simulation time 10103539456 ps
CPU time 13.63 seconds
Started Jun 07 08:48:50 PM PDT 24
Finished Jun 07 08:49:15 PM PDT 24
Peak memory 205900 kb
Host smart-1aaac249-58c8-4ab3-ad22-916fd28a9313
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3239239773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.3239239773
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.1311288262
Short name T924
Test name
Test status
Simulation time 10126709305 ps
CPU time 15.18 seconds
Started Jun 07 08:48:44 PM PDT 24
Finished Jun 07 08:49:06 PM PDT 24
Peak memory 205756 kb
Host smart-1e77ea50-536a-40fd-9aaa-ff0a2d6f1578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13112
88262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.1311288262
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.1868268178
Short name T540
Test name
Test status
Simulation time 13336188158 ps
CPU time 16.7 seconds
Started Jun 07 08:48:07 PM PDT 24
Finished Jun 07 08:48:27 PM PDT 24
Peak memory 205824 kb
Host smart-f0e0946c-5c56-480e-94f8-523e6a1ddcc9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1868268178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.1868268178
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.1997351374
Short name T1643
Test name
Test status
Simulation time 23265687787 ps
CPU time 24.95 seconds
Started Jun 07 08:48:05 PM PDT 24
Finished Jun 07 08:48:31 PM PDT 24
Peak memory 205872 kb
Host smart-20825578-4f0b-4f60-bf1b-787ea2176dce
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1997351374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.1997351374
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.735659216
Short name T824
Test name
Test status
Simulation time 10088031287 ps
CPU time 14.58 seconds
Started Jun 07 08:48:04 PM PDT 24
Finished Jun 07 08:48:20 PM PDT 24
Peak memory 205808 kb
Host smart-8a64a7c1-f1c9-4a4a-8eb4-45a7614454c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73565
9216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.735659216
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.3975410950
Short name T1005
Test name
Test status
Simulation time 10078802117 ps
CPU time 13.01 seconds
Started Jun 07 08:48:08 PM PDT 24
Finished Jun 07 08:48:23 PM PDT 24
Peak memory 205752 kb
Host smart-84ea7150-f2cb-4f35-a267-86d3abbfda55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39754
10950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.3975410950
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.82616563
Short name T1921
Test name
Test status
Simulation time 10314919947 ps
CPU time 13.45 seconds
Started Jun 07 08:48:08 PM PDT 24
Finished Jun 07 08:48:24 PM PDT 24
Peak memory 205744 kb
Host smart-3cf2721d-e17f-446a-a98d-03955d79a2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82616
563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.82616563
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.3283918690
Short name T683
Test name
Test status
Simulation time 10045972152 ps
CPU time 14.96 seconds
Started Jun 07 08:48:05 PM PDT 24
Finished Jun 07 08:48:22 PM PDT 24
Peak memory 205884 kb
Host smart-dd28a801-6e37-4533-9056-8e814324816f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32839
18690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.3283918690
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.2132706307
Short name T1132
Test name
Test status
Simulation time 10067019853 ps
CPU time 13.54 seconds
Started Jun 07 08:48:12 PM PDT 24
Finished Jun 07 08:48:27 PM PDT 24
Peak memory 205728 kb
Host smart-e1b72aa6-b255-443c-a42b-e4764bd12631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21327
06307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.2132706307
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.4237521998
Short name T514
Test name
Test status
Simulation time 10805540806 ps
CPU time 14.2 seconds
Started Jun 07 08:48:07 PM PDT 24
Finished Jun 07 08:48:24 PM PDT 24
Peak memory 205764 kb
Host smart-3fdb2098-5650-4ea2-8e88-9a3b70f4d6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42375
21998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.4237521998
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3219342405
Short name T1309
Test name
Test status
Simulation time 10276919396 ps
CPU time 14.49 seconds
Started Jun 07 08:48:08 PM PDT 24
Finished Jun 07 08:48:25 PM PDT 24
Peak memory 205788 kb
Host smart-6d3fd4de-2980-4d29-b599-4afb9ac99f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32193
42405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3219342405
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.859623788
Short name T1638
Test name
Test status
Simulation time 10144475058 ps
CPU time 15.18 seconds
Started Jun 07 08:48:47 PM PDT 24
Finished Jun 07 08:49:11 PM PDT 24
Peak memory 205848 kb
Host smart-d6c25115-a98c-4c37-a9a2-2041db1fbd84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85962
3788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.859623788
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.4105603935
Short name T432
Test name
Test status
Simulation time 10044228310 ps
CPU time 13.54 seconds
Started Jun 07 08:48:46 PM PDT 24
Finished Jun 07 08:49:09 PM PDT 24
Peak memory 205844 kb
Host smart-fccf43bf-8824-4262-9a88-576d68780fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41056
03935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.4105603935
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.2549604338
Short name T1459
Test name
Test status
Simulation time 10105740030 ps
CPU time 16.04 seconds
Started Jun 07 08:48:14 PM PDT 24
Finished Jun 07 08:48:31 PM PDT 24
Peak memory 205792 kb
Host smart-b90bf6c0-97d6-445c-81cf-b0cd61514adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25496
04338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.2549604338
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.111901883
Short name T995
Test name
Test status
Simulation time 10132507930 ps
CPU time 16 seconds
Started Jun 07 08:48:10 PM PDT 24
Finished Jun 07 08:48:28 PM PDT 24
Peak memory 205804 kb
Host smart-f6fc89b9-e5a6-42a4-8b21-f005551d6379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11190
1883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.111901883
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.504174732
Short name T1772
Test name
Test status
Simulation time 13223679874 ps
CPU time 16.88 seconds
Started Jun 07 08:48:07 PM PDT 24
Finished Jun 07 08:48:26 PM PDT 24
Peak memory 205668 kb
Host smart-18f371b9-585b-42f9-9767-da57676bf649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50417
4732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.504174732
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.1601451531
Short name T1875
Test name
Test status
Simulation time 10174414176 ps
CPU time 14.4 seconds
Started Jun 07 08:48:08 PM PDT 24
Finished Jun 07 08:48:25 PM PDT 24
Peak memory 205800 kb
Host smart-99569316-9140-4fea-af5e-c8861638f6d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16014
51531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.1601451531
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.3249322543
Short name T1962
Test name
Test status
Simulation time 21020063195 ps
CPU time 125.81 seconds
Started Jun 07 08:48:12 PM PDT 24
Finished Jun 07 08:50:19 PM PDT 24
Peak memory 205832 kb
Host smart-acf8f18d-ae88-4ee8-abe2-1c3ff3a01c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32493
22543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.3249322543
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.630807414
Short name T989
Test name
Test status
Simulation time 10061375996 ps
CPU time 14.17 seconds
Started Jun 07 08:48:13 PM PDT 24
Finished Jun 07 08:48:29 PM PDT 24
Peak memory 205848 kb
Host smart-ca521f2b-931a-461c-909e-ae475376bf22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63080
7414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.630807414
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.89590601
Short name T99
Test name
Test status
Simulation time 10086548927 ps
CPU time 14.06 seconds
Started Jun 07 08:48:12 PM PDT 24
Finished Jun 07 08:48:27 PM PDT 24
Peak memory 205808 kb
Host smart-82cca49c-056a-4b7e-9239-e34aa4a2adf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89590
601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.89590601
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.3437482907
Short name T916
Test name
Test status
Simulation time 10081296165 ps
CPU time 13.64 seconds
Started Jun 07 08:48:11 PM PDT 24
Finished Jun 07 08:48:26 PM PDT 24
Peak memory 205772 kb
Host smart-675c0bdb-8b1b-430d-9379-c730d8bcc27a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34374
82907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.3437482907
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3041226530
Short name T1212
Test name
Test status
Simulation time 10096436740 ps
CPU time 12.91 seconds
Started Jun 07 08:48:07 PM PDT 24
Finished Jun 07 08:48:22 PM PDT 24
Peak memory 205688 kb
Host smart-e51f3642-fee5-404b-81ad-0103d4c9e131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30412
26530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3041226530
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.452055637
Short name T1698
Test name
Test status
Simulation time 10080909956 ps
CPU time 13.09 seconds
Started Jun 07 08:48:13 PM PDT 24
Finished Jun 07 08:48:27 PM PDT 24
Peak memory 205756 kb
Host smart-78543a90-3e7e-49a4-ab59-ea521474cf93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45205
5637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.452055637
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.4289648173
Short name T1328
Test name
Test status
Simulation time 10055789539 ps
CPU time 15.82 seconds
Started Jun 07 08:48:37 PM PDT 24
Finished Jun 07 08:48:56 PM PDT 24
Peak memory 205812 kb
Host smart-e57e17a7-d9f3-4b91-9ca7-a0ebbee92b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42896
48173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.4289648173
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_eop_single_bit_handling.3882083057
Short name T394
Test name
Test status
Simulation time 10093028123 ps
CPU time 15.05 seconds
Started Jun 07 08:48:37 PM PDT 24
Finished Jun 07 08:48:55 PM PDT 24
Peak memory 205852 kb
Host smart-df13b6a3-cb8f-4237-a07b-f1287ff98de5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38820
83057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_eop_single_bit_handling.3882083057
Directory /workspace/48.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.3201469266
Short name T1560
Test name
Test status
Simulation time 10047232461 ps
CPU time 15.21 seconds
Started Jun 07 08:48:52 PM PDT 24
Finished Jun 07 08:49:20 PM PDT 24
Peak memory 205856 kb
Host smart-96c6cca8-6f87-49ba-861d-3a005255a0f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32014
69266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.3201469266
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.551032267
Short name T1871
Test name
Test status
Simulation time 10043552253 ps
CPU time 12.66 seconds
Started Jun 07 08:48:41 PM PDT 24
Finished Jun 07 08:49:00 PM PDT 24
Peak memory 205788 kb
Host smart-37c09ee9-28e3-445e-969c-920aad28d104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55103
2267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.551032267
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1169561347
Short name T1927
Test name
Test status
Simulation time 28056499501 ps
CPU time 55.09 seconds
Started Jun 07 08:48:07 PM PDT 24
Finished Jun 07 08:49:05 PM PDT 24
Peak memory 205696 kb
Host smart-acea9391-8a7d-4fe1-9a41-4b072a7ac88a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11695
61347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1169561347
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2260477560
Short name T1306
Test name
Test status
Simulation time 10110407297 ps
CPU time 15.32 seconds
Started Jun 07 08:48:13 PM PDT 24
Finished Jun 07 08:48:30 PM PDT 24
Peak memory 205788 kb
Host smart-8fa83494-7c81-4b1d-ab1b-4c7e48c70369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22604
77560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2260477560
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.1214047696
Short name T840
Test name
Test status
Simulation time 10062406350 ps
CPU time 16.6 seconds
Started Jun 07 08:48:08 PM PDT 24
Finished Jun 07 08:48:27 PM PDT 24
Peak memory 205856 kb
Host smart-cc6b9d37-8af2-4a62-a358-1939ef5b706c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12140
47696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.1214047696
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.2503649727
Short name T949
Test name
Test status
Simulation time 10056328039 ps
CPU time 14.84 seconds
Started Jun 07 08:48:37 PM PDT 24
Finished Jun 07 08:48:55 PM PDT 24
Peak memory 205832 kb
Host smart-60445326-bd28-4343-83f9-60ba39e3f827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25036
49727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.2503649727
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.3024789449
Short name T1039
Test name
Test status
Simulation time 10055405996 ps
CPU time 14.4 seconds
Started Jun 07 08:49:07 PM PDT 24
Finished Jun 07 08:49:31 PM PDT 24
Peak memory 205764 kb
Host smart-e25cee0a-d82e-4773-a83f-bef9c80d95c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30247
89449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.3024789449
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.1038746123
Short name T1906
Test name
Test status
Simulation time 10051761500 ps
CPU time 14.41 seconds
Started Jun 07 08:48:36 PM PDT 24
Finished Jun 07 08:48:54 PM PDT 24
Peak memory 205772 kb
Host smart-6fc07dfd-ec1a-417f-9598-6a8bf4ba05fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10387
46123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.1038746123
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3970564118
Short name T736
Test name
Test status
Simulation time 10052113814 ps
CPU time 12.65 seconds
Started Jun 07 08:48:35 PM PDT 24
Finished Jun 07 08:48:51 PM PDT 24
Peak memory 205824 kb
Host smart-d22f07a8-4ddc-4395-93b4-227bba10be4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39705
64118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3970564118
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1331590940
Short name T1551
Test name
Test status
Simulation time 10153483768 ps
CPU time 13.19 seconds
Started Jun 07 08:48:08 PM PDT 24
Finished Jun 07 08:48:24 PM PDT 24
Peak memory 205876 kb
Host smart-8b4fa98b-a685-41df-8ca7-3bbb39e63705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13315
90940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1331590940
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.350680748
Short name T124
Test name
Test status
Simulation time 10052554239 ps
CPU time 13.66 seconds
Started Jun 07 08:48:39 PM PDT 24
Finished Jun 07 08:48:57 PM PDT 24
Peak memory 205784 kb
Host smart-bfa6aaa0-bb7b-4f21-9a7d-ee6c203b2b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35068
0748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.350680748
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.1728081840
Short name T529
Test name
Test status
Simulation time 10074437319 ps
CPU time 13.91 seconds
Started Jun 07 08:48:39 PM PDT 24
Finished Jun 07 08:48:57 PM PDT 24
Peak memory 205844 kb
Host smart-938ea741-3847-493e-b3e2-53270341f19a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17280
81840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.1728081840
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.2438056852
Short name T384
Test name
Test status
Simulation time 17132113181 ps
CPU time 212.02 seconds
Started Jun 07 08:48:36 PM PDT 24
Finished Jun 07 08:52:12 PM PDT 24
Peak memory 205744 kb
Host smart-50cb5e9f-d81b-4317-9a18-1ba4157a2e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24380
56852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.2438056852
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.2553044776
Short name T1040
Test name
Test status
Simulation time 10152557256 ps
CPU time 12.93 seconds
Started Jun 07 08:48:40 PM PDT 24
Finished Jun 07 08:48:57 PM PDT 24
Peak memory 205880 kb
Host smart-0a811161-bf5c-4f83-a518-56376f1dc22b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2553044776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.2553044776
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.4121549949
Short name T976
Test name
Test status
Simulation time 10098657288 ps
CPU time 12.99 seconds
Started Jun 07 08:48:39 PM PDT 24
Finished Jun 07 08:48:56 PM PDT 24
Peak memory 205872 kb
Host smart-4a127b6c-7f19-44b0-94ff-c4a7c615730f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4121549949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.4121549949
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.3073761221
Short name T837
Test name
Test status
Simulation time 10171862986 ps
CPU time 14.02 seconds
Started Jun 07 08:48:38 PM PDT 24
Finished Jun 07 08:48:56 PM PDT 24
Peak memory 205856 kb
Host smart-4297a500-1135-4f71-9d85-bdebfaf40b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30737
61221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.3073761221
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.3580410102
Short name T663
Test name
Test status
Simulation time 13981134815 ps
CPU time 17.89 seconds
Started Jun 07 08:48:39 PM PDT 24
Finished Jun 07 08:49:01 PM PDT 24
Peak memory 205888 kb
Host smart-69c8cc50-1bc5-48c6-bd35-8e4d6115993f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3580410102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.3580410102
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.3521222868
Short name T183
Test name
Test status
Simulation time 23252917759 ps
CPU time 28.7 seconds
Started Jun 07 08:48:50 PM PDT 24
Finished Jun 07 08:49:30 PM PDT 24
Peak memory 205872 kb
Host smart-433d69e8-c51a-49eb-926c-f9bd03a8f89f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3521222868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.3521222868
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3763906046
Short name T621
Test name
Test status
Simulation time 10087356550 ps
CPU time 13.25 seconds
Started Jun 07 08:48:41 PM PDT 24
Finished Jun 07 08:48:59 PM PDT 24
Peak memory 205732 kb
Host smart-38021af2-d153-4948-882e-ad8f7e1d1c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37639
06046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3763906046
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.2819845400
Short name T2033
Test name
Test status
Simulation time 10046232974 ps
CPU time 13.05 seconds
Started Jun 07 08:48:48 PM PDT 24
Finished Jun 07 08:49:12 PM PDT 24
Peak memory 205856 kb
Host smart-6ca3cceb-b68b-42b4-8126-ec0cdbdd05c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28198
45400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.2819845400
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.3737011762
Short name T164
Test name
Test status
Simulation time 10854905108 ps
CPU time 14.57 seconds
Started Jun 07 08:48:35 PM PDT 24
Finished Jun 07 08:48:52 PM PDT 24
Peak memory 205872 kb
Host smart-c457d055-aece-4ad6-9121-cb8fcfa82c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37370
11762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.3737011762
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.2264494532
Short name T1012
Test name
Test status
Simulation time 10046916076 ps
CPU time 12.89 seconds
Started Jun 07 08:48:52 PM PDT 24
Finished Jun 07 08:49:17 PM PDT 24
Peak memory 205884 kb
Host smart-07666226-99fa-429b-9135-24fdb34e1f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22644
94532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.2264494532
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.1980010124
Short name T2005
Test name
Test status
Simulation time 10046295670 ps
CPU time 12.66 seconds
Started Jun 07 08:48:48 PM PDT 24
Finished Jun 07 08:49:10 PM PDT 24
Peak memory 205784 kb
Host smart-0544446d-4896-4ce5-94d9-337aafb149c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19800
10124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.1980010124
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.3253795922
Short name T1253
Test name
Test status
Simulation time 10717350029 ps
CPU time 18.91 seconds
Started Jun 07 08:48:44 PM PDT 24
Finished Jun 07 08:49:10 PM PDT 24
Peak memory 205768 kb
Host smart-71a005be-1ae5-4034-9000-2ff7c3956c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32537
95922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.3253795922
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.3755350300
Short name T901
Test name
Test status
Simulation time 10078287768 ps
CPU time 17.84 seconds
Started Jun 07 08:48:49 PM PDT 24
Finished Jun 07 08:49:17 PM PDT 24
Peak memory 205764 kb
Host smart-4c35ae3b-d162-4ae0-9fba-dd332fbdc56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37553
50300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3755350300
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.175194186
Short name T436
Test name
Test status
Simulation time 10122691276 ps
CPU time 12.6 seconds
Started Jun 07 08:48:42 PM PDT 24
Finished Jun 07 08:49:02 PM PDT 24
Peak memory 205772 kb
Host smart-098cdb59-42fc-4b04-aafb-82a387b6e5f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17519
4186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.175194186
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.4037328797
Short name T708
Test name
Test status
Simulation time 10051319901 ps
CPU time 12.59 seconds
Started Jun 07 08:48:43 PM PDT 24
Finished Jun 07 08:49:02 PM PDT 24
Peak memory 205840 kb
Host smart-628077c5-67c1-4b97-a7e5-309db949cb4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40373
28797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.4037328797
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.4009152691
Short name T1367
Test name
Test status
Simulation time 10147598709 ps
CPU time 16.39 seconds
Started Jun 07 08:48:37 PM PDT 24
Finished Jun 07 08:48:56 PM PDT 24
Peak memory 205804 kb
Host smart-568c4fb3-14d6-478e-a84c-caf9846be588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40091
52691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.4009152691
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.4201382145
Short name T1885
Test name
Test status
Simulation time 10092267844 ps
CPU time 13.21 seconds
Started Jun 07 08:48:34 PM PDT 24
Finished Jun 07 08:48:51 PM PDT 24
Peak memory 205884 kb
Host smart-d3274e72-7171-40a5-8023-f8c311c69627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42013
82145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.4201382145
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.358417156
Short name T485
Test name
Test status
Simulation time 13227453700 ps
CPU time 15.05 seconds
Started Jun 07 08:48:42 PM PDT 24
Finished Jun 07 08:49:03 PM PDT 24
Peak memory 205732 kb
Host smart-fc1dccb9-6dad-4852-8201-889b07e9e3bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35841
7156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.358417156
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2013903768
Short name T856
Test name
Test status
Simulation time 10106426659 ps
CPU time 13.6 seconds
Started Jun 07 08:48:44 PM PDT 24
Finished Jun 07 08:49:04 PM PDT 24
Peak memory 205876 kb
Host smart-b8effac0-67e0-4b4b-98b1-4264db1d2ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20139
03768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2013903768
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.3368181849
Short name T1456
Test name
Test status
Simulation time 18790504391 ps
CPU time 264.52 seconds
Started Jun 07 08:48:37 PM PDT 24
Finished Jun 07 08:53:04 PM PDT 24
Peak memory 205804 kb
Host smart-05bb7977-ce01-4f30-bd28-42079365d8dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33681
81849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.3368181849
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3554581077
Short name T290
Test name
Test status
Simulation time 10055700073 ps
CPU time 12.77 seconds
Started Jun 07 08:48:44 PM PDT 24
Finished Jun 07 08:49:03 PM PDT 24
Peak memory 205740 kb
Host smart-25af448e-cc7d-4fe1-b7aa-2e845de722fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35545
81077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3554581077
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.1873608551
Short name T111
Test name
Test status
Simulation time 10113454926 ps
CPU time 13.96 seconds
Started Jun 07 08:48:48 PM PDT 24
Finished Jun 07 08:49:13 PM PDT 24
Peak memory 205772 kb
Host smart-de11083a-03b1-4bbf-a6d9-5ec424141b55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18736
08551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1873608551
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.2929789733
Short name T1949
Test name
Test status
Simulation time 10084801306 ps
CPU time 13.25 seconds
Started Jun 07 08:48:53 PM PDT 24
Finished Jun 07 08:49:19 PM PDT 24
Peak memory 205868 kb
Host smart-64a04209-6adc-43b5-90bb-f5e861b690ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29297
89733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.2929789733
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1058323640
Short name T331
Test name
Test status
Simulation time 10063151512 ps
CPU time 13.6 seconds
Started Jun 07 08:48:43 PM PDT 24
Finished Jun 07 08:49:04 PM PDT 24
Peak memory 205852 kb
Host smart-ed2b5d4a-417c-484e-b57c-ae8e0e76bf4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10583
23640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1058323640
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.4140531739
Short name T1471
Test name
Test status
Simulation time 10069683914 ps
CPU time 13.38 seconds
Started Jun 07 08:48:44 PM PDT 24
Finished Jun 07 08:49:04 PM PDT 24
Peak memory 205768 kb
Host smart-68d68a48-d9e9-4751-8b09-df851c4a78eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41405
31739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.4140531739
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.1200792498
Short name T132
Test name
Test status
Simulation time 10111776346 ps
CPU time 13.33 seconds
Started Jun 07 08:48:41 PM PDT 24
Finished Jun 07 08:48:59 PM PDT 24
Peak memory 205944 kb
Host smart-153e7a4b-f9bc-4fa2-9c1b-9f54de00279b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12007
92498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.1200792498
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_eop_single_bit_handling.639553723
Short name T1689
Test name
Test status
Simulation time 10074070485 ps
CPU time 12.86 seconds
Started Jun 07 08:48:47 PM PDT 24
Finished Jun 07 08:49:11 PM PDT 24
Peak memory 205740 kb
Host smart-79742b18-f24f-4250-8af8-50e33fba1a28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63955
3723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_eop_single_bit_handling.639553723
Directory /workspace/49.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3542411635
Short name T366
Test name
Test status
Simulation time 10050075125 ps
CPU time 12.44 seconds
Started Jun 07 08:48:45 PM PDT 24
Finished Jun 07 08:49:07 PM PDT 24
Peak memory 205804 kb
Host smart-4c4c3587-b007-42ed-b15a-497dedb52c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35424
11635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3542411635
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.2213478221
Short name T1033
Test name
Test status
Simulation time 10062734876 ps
CPU time 12.65 seconds
Started Jun 07 08:48:41 PM PDT 24
Finished Jun 07 08:49:00 PM PDT 24
Peak memory 205824 kb
Host smart-45b26adf-ea75-4d6e-9555-d2c6f062fcad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22134
78221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.2213478221
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.151175516
Short name T905
Test name
Test status
Simulation time 27798773893 ps
CPU time 56.56 seconds
Started Jun 07 08:48:44 PM PDT 24
Finished Jun 07 08:49:47 PM PDT 24
Peak memory 205780 kb
Host smart-25a03f91-2524-4fb0-893c-58a772d96c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15117
5516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.151175516
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3593923631
Short name T1980
Test name
Test status
Simulation time 10104642218 ps
CPU time 13.08 seconds
Started Jun 07 08:48:43 PM PDT 24
Finished Jun 07 08:49:03 PM PDT 24
Peak memory 205768 kb
Host smart-c268dadb-dc5f-4d86-824f-73b380cc9435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35939
23631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3593923631
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1861368519
Short name T1417
Test name
Test status
Simulation time 10149464199 ps
CPU time 14.4 seconds
Started Jun 07 08:48:49 PM PDT 24
Finished Jun 07 08:49:15 PM PDT 24
Peak memory 205820 kb
Host smart-83a41973-4faf-4d45-af2a-76022ddd1ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18613
68519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1861368519
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.3468274262
Short name T3
Test name
Test status
Simulation time 10083647901 ps
CPU time 13.86 seconds
Started Jun 07 08:48:45 PM PDT 24
Finished Jun 07 08:49:08 PM PDT 24
Peak memory 205880 kb
Host smart-289bf938-c405-46b8-bc37-cc96f016f6da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34682
74262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.3468274262
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.367141535
Short name T1236
Test name
Test status
Simulation time 10042594031 ps
CPU time 15.41 seconds
Started Jun 07 08:48:46 PM PDT 24
Finished Jun 07 08:49:10 PM PDT 24
Peak memory 205856 kb
Host smart-51d6adb6-0a25-4d37-a363-b0d78773c536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36714
1535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.367141535
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.293620905
Short name T1501
Test name
Test status
Simulation time 10083043964 ps
CPU time 13.41 seconds
Started Jun 07 08:48:37 PM PDT 24
Finished Jun 07 08:48:54 PM PDT 24
Peak memory 205748 kb
Host smart-ee66e40b-b6f9-4e13-b166-9b268ee0f4f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29362
0905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.293620905
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.923697347
Short name T1755
Test name
Test status
Simulation time 10051630227 ps
CPU time 13.01 seconds
Started Jun 07 08:48:47 PM PDT 24
Finished Jun 07 08:49:11 PM PDT 24
Peak memory 205816 kb
Host smart-4f9aa506-3bbd-4ed2-b934-7bb9927d14ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92369
7347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.923697347
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.2423333882
Short name T831
Test name
Test status
Simulation time 10100272502 ps
CPU time 12.93 seconds
Started Jun 07 08:48:37 PM PDT 24
Finished Jun 07 08:48:54 PM PDT 24
Peak memory 205792 kb
Host smart-d47794b7-1424-4c20-827d-511e29d9d743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24233
33882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.2423333882
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.2392131331
Short name T233
Test name
Test status
Simulation time 10058713262 ps
CPU time 12.96 seconds
Started Jun 07 08:48:44 PM PDT 24
Finished Jun 07 08:49:04 PM PDT 24
Peak memory 205928 kb
Host smart-7e6dd007-8897-4a7a-8e4e-0bc70aba9a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23921
31331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.2392131331
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.3541084543
Short name T1370
Test name
Test status
Simulation time 10083819188 ps
CPU time 12.79 seconds
Started Jun 07 08:48:45 PM PDT 24
Finished Jun 07 08:49:07 PM PDT 24
Peak memory 205944 kb
Host smart-c1a39f4a-c5c9-404b-b2d6-c4a143925547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35410
84543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.3541084543
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.406502512
Short name T1647
Test name
Test status
Simulation time 24814202571 ps
CPU time 153.97 seconds
Started Jun 07 08:48:52 PM PDT 24
Finished Jun 07 08:51:39 PM PDT 24
Peak memory 205880 kb
Host smart-a5336a07-41ae-48c5-ba85-b58fad39744d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40650
2512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.406502512
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.4237467129
Short name T1200
Test name
Test status
Simulation time 10146746553 ps
CPU time 14.33 seconds
Started Jun 07 08:42:05 PM PDT 24
Finished Jun 07 08:42:22 PM PDT 24
Peak memory 205856 kb
Host smart-faba2a90-737c-4c26-9552-5381dda71eab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4237467129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.4237467129
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.1797500707
Short name T1062
Test name
Test status
Simulation time 10102264038 ps
CPU time 13.32 seconds
Started Jun 07 08:42:06 PM PDT 24
Finished Jun 07 08:42:22 PM PDT 24
Peak memory 205848 kb
Host smart-479c4875-6bbb-4335-b8d1-ae5e3a4a9f1b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1797500707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.1797500707
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.914319153
Short name T1082
Test name
Test status
Simulation time 10121611346 ps
CPU time 13.95 seconds
Started Jun 07 08:42:06 PM PDT 24
Finished Jun 07 08:42:22 PM PDT 24
Peak memory 205856 kb
Host smart-72ba708b-bc37-427c-9f47-1bf8c90b84d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91431
9153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.914319153
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.1048147779
Short name T1644
Test name
Test status
Simulation time 13883965137 ps
CPU time 17.84 seconds
Started Jun 07 08:41:45 PM PDT 24
Finished Jun 07 08:42:05 PM PDT 24
Peak memory 205748 kb
Host smart-845afdfd-b1fb-4485-b4e8-dcf5e6b8d7ec
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1048147779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.1048147779
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.3562984352
Short name T1123
Test name
Test status
Simulation time 23275839832 ps
CPU time 23.87 seconds
Started Jun 07 08:41:49 PM PDT 24
Finished Jun 07 08:42:16 PM PDT 24
Peak memory 205876 kb
Host smart-1b3cb804-b13a-4c04-9c09-8e48e57724a7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3562984352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.3562984352
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.579303208
Short name T625
Test name
Test status
Simulation time 10051566519 ps
CPU time 14.76 seconds
Started Jun 07 08:41:49 PM PDT 24
Finished Jun 07 08:42:07 PM PDT 24
Peak memory 205792 kb
Host smart-3c04b847-0a1d-431d-8065-18f1de116356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57930
3208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.579303208
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.3718544155
Short name T1738
Test name
Test status
Simulation time 10735993429 ps
CPU time 14.8 seconds
Started Jun 07 08:41:54 PM PDT 24
Finished Jun 07 08:42:11 PM PDT 24
Peak memory 205756 kb
Host smart-4904f6c5-aca8-4e93-a7fb-91133b05a9ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37185
44155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.3718544155
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.490057814
Short name T45
Test name
Test status
Simulation time 10100165637 ps
CPU time 13.92 seconds
Started Jun 07 08:41:53 PM PDT 24
Finished Jun 07 08:42:08 PM PDT 24
Peak memory 205700 kb
Host smart-a282da75-353e-495a-8f24-80b6c404cee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49005
7814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.490057814
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.2853926493
Short name T1963
Test name
Test status
Simulation time 10052187031 ps
CPU time 13.64 seconds
Started Jun 07 08:41:50 PM PDT 24
Finished Jun 07 08:42:06 PM PDT 24
Peak memory 205788 kb
Host smart-b05b3719-d8e9-4ab3-998a-ebca01477362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28539
26493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2853926493
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.853277630
Short name T2017
Test name
Test status
Simulation time 10704026657 ps
CPU time 16.12 seconds
Started Jun 07 08:41:53 PM PDT 24
Finished Jun 07 08:42:10 PM PDT 24
Peak memory 205852 kb
Host smart-7c2337f8-edbc-4c35-b2c9-4b35ee3ec9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85327
7630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.853277630
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.2806677256
Short name T830
Test name
Test status
Simulation time 10144863730 ps
CPU time 15.42 seconds
Started Jun 07 08:41:53 PM PDT 24
Finished Jun 07 08:42:11 PM PDT 24
Peak memory 205836 kb
Host smart-e80ba756-ee1e-4292-99e0-42d16df01533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28066
77256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.2806677256
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.1727181029
Short name T1692
Test name
Test status
Simulation time 10108571948 ps
CPU time 13.51 seconds
Started Jun 07 08:42:08 PM PDT 24
Finished Jun 07 08:42:24 PM PDT 24
Peak memory 205840 kb
Host smart-c3c94da0-7ab0-4bee-9996-1fb04c3fd757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17271
81029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.1727181029
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.2966766339
Short name T1372
Test name
Test status
Simulation time 10043024687 ps
CPU time 13.42 seconds
Started Jun 07 08:41:58 PM PDT 24
Finished Jun 07 08:42:12 PM PDT 24
Peak memory 205880 kb
Host smart-20c34d1e-bbd7-4252-ace4-16164c3a78bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29667
66339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.2966766339
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.173538585
Short name T1317
Test name
Test status
Simulation time 10064656298 ps
CPU time 14.09 seconds
Started Jun 07 08:41:55 PM PDT 24
Finished Jun 07 08:42:11 PM PDT 24
Peak memory 205872 kb
Host smart-7c8b8629-efe8-4783-8291-935dd0040239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17353
8585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.173538585
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.1899918589
Short name T632
Test name
Test status
Simulation time 10135185132 ps
CPU time 13.56 seconds
Started Jun 07 08:41:54 PM PDT 24
Finished Jun 07 08:42:09 PM PDT 24
Peak memory 205664 kb
Host smart-71b6f20b-61f7-49a5-969d-dae2239fe690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18999
18589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.1899918589
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.1229532538
Short name T126
Test name
Test status
Simulation time 13182361024 ps
CPU time 15.28 seconds
Started Jun 07 08:41:54 PM PDT 24
Finished Jun 07 08:42:12 PM PDT 24
Peak memory 205780 kb
Host smart-cb02f4b4-33a2-4a19-b328-d592eedcf683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12295
32538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.1229532538
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3883967880
Short name T232
Test name
Test status
Simulation time 10124873435 ps
CPU time 12.81 seconds
Started Jun 07 08:41:51 PM PDT 24
Finished Jun 07 08:42:06 PM PDT 24
Peak memory 205780 kb
Host smart-1db780aa-cd9d-4d0a-b3f9-113d3b342ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38839
67880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3883967880
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.200175583
Short name T701
Test name
Test status
Simulation time 23317193088 ps
CPU time 129.46 seconds
Started Jun 07 08:41:51 PM PDT 24
Finished Jun 07 08:44:03 PM PDT 24
Peak memory 205852 kb
Host smart-d3bce07e-de01-4b43-af75-ba97bf48fe28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20017
5583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.200175583
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.203466624
Short name T1359
Test name
Test status
Simulation time 10047252328 ps
CPU time 12.83 seconds
Started Jun 07 08:41:53 PM PDT 24
Finished Jun 07 08:42:08 PM PDT 24
Peak memory 205808 kb
Host smart-fc228ea2-3d39-4ece-b93e-a0a6dd6d69ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20346
6624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.203466624
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.22566289
Short name T1267
Test name
Test status
Simulation time 10125920153 ps
CPU time 12.89 seconds
Started Jun 07 08:41:51 PM PDT 24
Finished Jun 07 08:42:06 PM PDT 24
Peak memory 205820 kb
Host smart-d833f3da-2afa-48ca-a168-d24863513523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22566
289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.22566289
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.2780680405
Short name T677
Test name
Test status
Simulation time 10093007336 ps
CPU time 13.88 seconds
Started Jun 07 08:41:53 PM PDT 24
Finished Jun 07 08:42:09 PM PDT 24
Peak memory 205844 kb
Host smart-265dd06a-196d-4fec-b865-0f561ba30b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27806
80405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.2780680405
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.3954680157
Short name T1724
Test name
Test status
Simulation time 10074333999 ps
CPU time 14.15 seconds
Started Jun 07 08:41:51 PM PDT 24
Finished Jun 07 08:42:08 PM PDT 24
Peak memory 205756 kb
Host smart-e67a615d-45bf-4123-a9ab-83719b25df6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39546
80157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3954680157
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.1317494055
Short name T475
Test name
Test status
Simulation time 10070653162 ps
CPU time 12.81 seconds
Started Jun 07 08:41:54 PM PDT 24
Finished Jun 07 08:42:09 PM PDT 24
Peak memory 205756 kb
Host smart-3b35c56a-7280-4799-af82-1f3bd5271aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13174
94055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.1317494055
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.2525563336
Short name T156
Test name
Test status
Simulation time 10059259649 ps
CPU time 12.96 seconds
Started Jun 07 08:41:58 PM PDT 24
Finished Jun 07 08:42:12 PM PDT 24
Peak memory 205856 kb
Host smart-4cbf0727-8567-4fe1-9e3c-4fff540716df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25255
63336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.2525563336
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_eop_single_bit_handling.3534688531
Short name T538
Test name
Test status
Simulation time 10052522653 ps
CPU time 13.68 seconds
Started Jun 07 08:42:01 PM PDT 24
Finished Jun 07 08:42:16 PM PDT 24
Peak memory 205840 kb
Host smart-0a2a68f2-627d-4072-849b-a1fcb93f5ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35346
88531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_eop_single_bit_handling.3534688531
Directory /workspace/5.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.3108909274
Short name T1497
Test name
Test status
Simulation time 10039201319 ps
CPU time 14.91 seconds
Started Jun 07 08:42:00 PM PDT 24
Finished Jun 07 08:42:16 PM PDT 24
Peak memory 205904 kb
Host smart-3612001e-ab08-4e68-a11d-f632155c636c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31089
09274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.3108909274
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.1675169579
Short name T1162
Test name
Test status
Simulation time 10105931986 ps
CPU time 12.52 seconds
Started Jun 07 08:41:59 PM PDT 24
Finished Jun 07 08:42:12 PM PDT 24
Peak memory 205724 kb
Host smart-a3d053cd-12f7-4490-9907-ef4f95529bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16751
69579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.1675169579
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.683083238
Short name T332
Test name
Test status
Simulation time 10072296354 ps
CPU time 12.62 seconds
Started Jun 07 08:41:54 PM PDT 24
Finished Jun 07 08:42:08 PM PDT 24
Peak memory 205776 kb
Host smart-bb99a8ee-3a98-401a-b6cf-2498a31d55cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68308
3238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.683083238
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.3723846001
Short name T981
Test name
Test status
Simulation time 10192108681 ps
CPU time 12.66 seconds
Started Jun 07 08:41:54 PM PDT 24
Finished Jun 07 08:42:09 PM PDT 24
Peak memory 205676 kb
Host smart-28a7e425-2161-481e-9407-0ebff1adcb18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37238
46001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.3723846001
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.453412182
Short name T1565
Test name
Test status
Simulation time 24491020262 ps
CPU time 411.8 seconds
Started Jun 07 08:41:55 PM PDT 24
Finished Jun 07 08:48:48 PM PDT 24
Peak memory 205880 kb
Host smart-f4e9aaef-9aa3-4f57-8324-30229d0b2145
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=453412182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.453412182
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.3917542971
Short name T1584
Test name
Test status
Simulation time 25164251671 ps
CPU time 102.28 seconds
Started Jun 07 08:41:53 PM PDT 24
Finished Jun 07 08:43:37 PM PDT 24
Peak memory 205904 kb
Host smart-4d30ea48-3a31-4326-adaa-f01776e0d081
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3917542971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.3917542971
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.2707020627
Short name T950
Test name
Test status
Simulation time 31012602095 ps
CPU time 179.3 seconds
Started Jun 07 08:41:58 PM PDT 24
Finished Jun 07 08:44:59 PM PDT 24
Peak memory 205904 kb
Host smart-7f7079cb-e289-4ae7-9e76-2d516d510ddb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2707020627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.2707020627
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.3895506447
Short name T352
Test name
Test status
Simulation time 10099338939 ps
CPU time 13.62 seconds
Started Jun 07 08:42:00 PM PDT 24
Finished Jun 07 08:42:15 PM PDT 24
Peak memory 205716 kb
Host smart-40cfa2ad-fdd1-446a-9fe4-ed764ad6aa5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38955
06447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.3895506447
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.1096345469
Short name T601
Test name
Test status
Simulation time 10041652873 ps
CPU time 13.84 seconds
Started Jun 07 08:41:59 PM PDT 24
Finished Jun 07 08:42:14 PM PDT 24
Peak memory 205836 kb
Host smart-8e52b847-2876-4a08-9401-0555d812c5d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10963
45469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.1096345469
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.831508721
Short name T1532
Test name
Test status
Simulation time 10062595490 ps
CPU time 15.2 seconds
Started Jun 07 08:42:01 PM PDT 24
Finished Jun 07 08:42:17 PM PDT 24
Peak memory 205948 kb
Host smart-534bf89d-b8bb-4ba4-bd2b-ae5700f6d880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83150
8721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.831508721
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3942288189
Short name T776
Test name
Test status
Simulation time 10045759255 ps
CPU time 13.75 seconds
Started Jun 07 08:41:58 PM PDT 24
Finished Jun 07 08:42:13 PM PDT 24
Peak memory 205764 kb
Host smart-65d9c530-da63-47b7-9f83-15999501cfc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39422
88189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3942288189
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.3306969685
Short name T1849
Test name
Test status
Simulation time 10164859745 ps
CPU time 13.04 seconds
Started Jun 07 08:41:46 PM PDT 24
Finished Jun 07 08:42:02 PM PDT 24
Peak memory 205888 kb
Host smart-8a8957c2-d71b-436f-8c1e-055cc55262fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33069
69685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.3306969685
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.1918108900
Short name T1769
Test name
Test status
Simulation time 10074713970 ps
CPU time 13.96 seconds
Started Jun 07 08:41:59 PM PDT 24
Finished Jun 07 08:42:14 PM PDT 24
Peak memory 205892 kb
Host smart-f1c9f942-d258-406c-a0ec-b5a2504e18fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19181
08900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1918108900
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.1773596798
Short name T513
Test name
Test status
Simulation time 10059783912 ps
CPU time 15.12 seconds
Started Jun 07 08:41:58 PM PDT 24
Finished Jun 07 08:42:14 PM PDT 24
Peak memory 205820 kb
Host smart-c6f3648a-42a3-40e6-841a-c222c79e1745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17735
96798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.1773596798
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.1182156112
Short name T1450
Test name
Test status
Simulation time 15639553826 ps
CPU time 64.73 seconds
Started Jun 07 08:41:59 PM PDT 24
Finished Jun 07 08:43:06 PM PDT 24
Peak memory 205888 kb
Host smart-b610b364-5c2c-441e-878c-242a36173f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11821
56112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.1182156112
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.3368739789
Short name T1128
Test name
Test status
Simulation time 10158062251 ps
CPU time 13.08 seconds
Started Jun 07 08:42:26 PM PDT 24
Finished Jun 07 08:42:41 PM PDT 24
Peak memory 205884 kb
Host smart-376634b0-2c9f-4624-9541-b4a18998f866
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3368739789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.3368739789
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.382024304
Short name T1455
Test name
Test status
Simulation time 10077767138 ps
CPU time 15.02 seconds
Started Jun 07 08:42:22 PM PDT 24
Finished Jun 07 08:42:40 PM PDT 24
Peak memory 205740 kb
Host smart-5f145e96-5477-421d-b5d5-db3304a06aa7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=382024304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.382024304
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.1280552012
Short name T52
Test name
Test status
Simulation time 10143134270 ps
CPU time 13.41 seconds
Started Jun 07 08:42:25 PM PDT 24
Finished Jun 07 08:42:41 PM PDT 24
Peak memory 205780 kb
Host smart-f718c3aa-39ce-4cec-97c6-7e0f92d1f327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12805
52012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.1280552012
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.3951111715
Short name T892
Test name
Test status
Simulation time 14152991844 ps
CPU time 17.94 seconds
Started Jun 07 08:42:12 PM PDT 24
Finished Jun 07 08:42:32 PM PDT 24
Peak memory 205848 kb
Host smart-1da327c5-4751-4360-8ae1-24c486f2c9da
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3951111715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.3951111715
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.4101778758
Short name T11
Test name
Test status
Simulation time 23270128851 ps
CPU time 25.48 seconds
Started Jun 07 08:42:09 PM PDT 24
Finished Jun 07 08:42:37 PM PDT 24
Peak memory 205072 kb
Host smart-426daf8e-7001-4e12-beba-ac46c461cbc8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4101778758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.4101778758
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2209953536
Short name T966
Test name
Test status
Simulation time 10068946349 ps
CPU time 12.63 seconds
Started Jun 07 08:42:07 PM PDT 24
Finished Jun 07 08:42:23 PM PDT 24
Peak memory 205736 kb
Host smart-935d8023-c780-4bb0-a0ea-68ac618f73ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22099
53536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2209953536
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.3397275502
Short name T1636
Test name
Test status
Simulation time 10233986834 ps
CPU time 12.93 seconds
Started Jun 07 08:42:09 PM PDT 24
Finished Jun 07 08:42:25 PM PDT 24
Peak memory 205804 kb
Host smart-7a6ff73c-c6b4-49b5-b37e-90489c5cea21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33972
75502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.3397275502
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.2254972896
Short name T1701
Test name
Test status
Simulation time 10090823218 ps
CPU time 12.66 seconds
Started Jun 07 08:42:19 PM PDT 24
Finished Jun 07 08:42:34 PM PDT 24
Peak memory 205880 kb
Host smart-dfd35d08-302c-4290-8e3f-912b3b49f847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22549
72896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2254972896
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.3567232002
Short name T1080
Test name
Test status
Simulation time 10054645951 ps
CPU time 13.44 seconds
Started Jun 07 08:42:07 PM PDT 24
Finished Jun 07 08:42:23 PM PDT 24
Peak memory 205760 kb
Host smart-5e794cde-bac9-4416-a99c-13e0c1d633fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35672
32002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3567232002
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.2644509351
Short name T1773
Test name
Test status
Simulation time 10814287872 ps
CPU time 17.37 seconds
Started Jun 07 08:42:05 PM PDT 24
Finished Jun 07 08:42:24 PM PDT 24
Peak memory 205736 kb
Host smart-7fd67c5f-bd2a-4f0b-ab1f-49c88aac2785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26445
09351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.2644509351
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.211762754
Short name T1671
Test name
Test status
Simulation time 10275528758 ps
CPU time 14.71 seconds
Started Jun 07 08:42:09 PM PDT 24
Finished Jun 07 08:42:26 PM PDT 24
Peak memory 205748 kb
Host smart-ca5e515c-a3bf-4704-9261-3d0326bf8080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21176
2754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.211762754
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.73742653
Short name T972
Test name
Test status
Simulation time 10138165843 ps
CPU time 15.79 seconds
Started Jun 07 08:42:21 PM PDT 24
Finished Jun 07 08:42:40 PM PDT 24
Peak memory 205824 kb
Host smart-df3573fd-bdfd-4f6b-99c6-c85733b07bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73742
653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.73742653
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.3475301257
Short name T1341
Test name
Test status
Simulation time 10050596896 ps
CPU time 14.94 seconds
Started Jun 07 08:42:18 PM PDT 24
Finished Jun 07 08:42:35 PM PDT 24
Peak memory 205912 kb
Host smart-b6c23f0e-0fee-42d6-a5ee-9d756488d74d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34753
01257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3475301257
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.1648368694
Short name T1201
Test name
Test status
Simulation time 10122832973 ps
CPU time 12.88 seconds
Started Jun 07 08:42:06 PM PDT 24
Finished Jun 07 08:42:20 PM PDT 24
Peak memory 205880 kb
Host smart-7a67837f-f044-40e1-8407-6a01fd779d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16483
68694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1648368694
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.3551171332
Short name T1069
Test name
Test status
Simulation time 10110114691 ps
CPU time 14.21 seconds
Started Jun 07 08:42:06 PM PDT 24
Finished Jun 07 08:42:23 PM PDT 24
Peak memory 205716 kb
Host smart-6eba916b-dacc-4b70-8f0b-cae769425a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35511
71332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.3551171332
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.2169104690
Short name T1466
Test name
Test status
Simulation time 13201505370 ps
CPU time 15.94 seconds
Started Jun 07 08:42:07 PM PDT 24
Finished Jun 07 08:42:25 PM PDT 24
Peak memory 205760 kb
Host smart-8455640b-d409-4d1f-9825-0d6314b30140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21691
04690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.2169104690
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1189007819
Short name T1307
Test name
Test status
Simulation time 10099415640 ps
CPU time 13.42 seconds
Started Jun 07 08:42:06 PM PDT 24
Finished Jun 07 08:42:22 PM PDT 24
Peak memory 205852 kb
Host smart-c56dd0e5-2e0b-433d-8813-6cd5e1baeaf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11890
07819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1189007819
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.355231870
Short name T804
Test name
Test status
Simulation time 15195661310 ps
CPU time 158.83 seconds
Started Jun 07 08:42:18 PM PDT 24
Finished Jun 07 08:44:59 PM PDT 24
Peak memory 205836 kb
Host smart-4666bc59-bfe6-4441-a9d3-e082f16b61c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35523
1870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.355231870
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.4107438516
Short name T1914
Test name
Test status
Simulation time 10068244333 ps
CPU time 12.8 seconds
Started Jun 07 08:42:17 PM PDT 24
Finished Jun 07 08:42:32 PM PDT 24
Peak memory 205804 kb
Host smart-b2248694-5fd4-444f-a817-65c981f2dea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41074
38516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.4107438516
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2335475268
Short name T1425
Test name
Test status
Simulation time 10142703929 ps
CPU time 14.37 seconds
Started Jun 07 08:42:13 PM PDT 24
Finished Jun 07 08:42:29 PM PDT 24
Peak memory 205868 kb
Host smart-d4c17307-6a3f-4b3e-a40e-45b74a69c0e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23354
75268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2335475268
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.344555021
Short name T1996
Test name
Test status
Simulation time 10071535609 ps
CPU time 13.56 seconds
Started Jun 07 08:42:14 PM PDT 24
Finished Jun 07 08:42:29 PM PDT 24
Peak memory 205844 kb
Host smart-fb56bbfd-30c7-4c64-b62c-171117696fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34455
5021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.344555021
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.2260650911
Short name T763
Test name
Test status
Simulation time 10101027760 ps
CPU time 13.78 seconds
Started Jun 07 08:42:19 PM PDT 24
Finished Jun 07 08:42:35 PM PDT 24
Peak memory 205780 kb
Host smart-118808e0-fddb-4b1d-a223-31a404c636bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22606
50911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.2260650911
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1233789818
Short name T1442
Test name
Test status
Simulation time 10073598948 ps
CPU time 14.87 seconds
Started Jun 07 08:42:17 PM PDT 24
Finished Jun 07 08:42:34 PM PDT 24
Peak memory 205844 kb
Host smart-89bb2982-980b-4c16-b200-f06da58af501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12337
89818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1233789818
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.4152876448
Short name T1098
Test name
Test status
Simulation time 10056671477 ps
CPU time 12.95 seconds
Started Jun 07 08:42:17 PM PDT 24
Finished Jun 07 08:42:32 PM PDT 24
Peak memory 205836 kb
Host smart-4088c62d-bc9a-4d19-837b-4d55f43bc81b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41528
76448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.4152876448
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_eop_single_bit_handling.453351101
Short name T796
Test name
Test status
Simulation time 10081507021 ps
CPU time 13.96 seconds
Started Jun 07 08:42:17 PM PDT 24
Finished Jun 07 08:42:34 PM PDT 24
Peak memory 205812 kb
Host smart-57adfe83-d5f6-4abd-a454-fe66df62bfee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45335
1101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_eop_single_bit_handling.453351101
Directory /workspace/6.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.4087791249
Short name T1619
Test name
Test status
Simulation time 10044186606 ps
CPU time 16.2 seconds
Started Jun 07 08:42:18 PM PDT 24
Finished Jun 07 08:42:37 PM PDT 24
Peak memory 205832 kb
Host smart-0413e281-3981-4f54-b927-c87bae43acf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40877
91249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.4087791249
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.3543803794
Short name T2006
Test name
Test status
Simulation time 10062109154 ps
CPU time 13.17 seconds
Started Jun 07 08:42:15 PM PDT 24
Finished Jun 07 08:42:30 PM PDT 24
Peak memory 205712 kb
Host smart-f107aecf-cb67-4344-9d8b-afd90ef77719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35438
03794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.3543803794
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.4269162360
Short name T166
Test name
Test status
Simulation time 26594905256 ps
CPU time 47.24 seconds
Started Jun 07 08:42:16 PM PDT 24
Finished Jun 07 08:43:05 PM PDT 24
Peak memory 205784 kb
Host smart-d5b9e548-99ee-4c55-a5b1-e67c30fc6b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42691
62360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.4269162360
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.2958865261
Short name T815
Test name
Test status
Simulation time 10073745630 ps
CPU time 13.29 seconds
Started Jun 07 08:42:15 PM PDT 24
Finished Jun 07 08:42:30 PM PDT 24
Peak memory 205776 kb
Host smart-17bc364c-719c-4de3-9037-a253ddbc9d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29588
65261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.2958865261
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2403659808
Short name T1405
Test name
Test status
Simulation time 10060173510 ps
CPU time 12.93 seconds
Started Jun 07 08:42:16 PM PDT 24
Finished Jun 07 08:42:32 PM PDT 24
Peak memory 205976 kb
Host smart-4c7eced9-765d-4e2a-9cfd-fd6351fe2b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24036
59808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2403659808
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.2637048518
Short name T1823
Test name
Test status
Simulation time 32566020582 ps
CPU time 621.48 seconds
Started Jun 07 08:42:14 PM PDT 24
Finished Jun 07 08:52:37 PM PDT 24
Peak memory 205888 kb
Host smart-e2478709-79f8-4497-9a72-a2cc75a2970c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2637048518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.2637048518
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.2453301406
Short name T768
Test name
Test status
Simulation time 45495772416 ps
CPU time 235.58 seconds
Started Jun 07 08:42:17 PM PDT 24
Finished Jun 07 08:46:15 PM PDT 24
Peak memory 205820 kb
Host smart-fe4fe6c7-ad87-4d43-bd73-8518a98ed685
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2453301406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.2453301406
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.1809463104
Short name T849
Test name
Test status
Simulation time 10093474557 ps
CPU time 14.44 seconds
Started Jun 07 08:42:18 PM PDT 24
Finished Jun 07 08:42:35 PM PDT 24
Peak memory 205880 kb
Host smart-d2bbaa6e-736d-4ccd-bf8f-019959ab1199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18094
63104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.1809463104
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.563594278
Short name T1986
Test name
Test status
Simulation time 10041673021 ps
CPU time 14.65 seconds
Started Jun 07 08:42:18 PM PDT 24
Finished Jun 07 08:42:35 PM PDT 24
Peak memory 205732 kb
Host smart-dca618e3-9097-42ad-ba27-9fd2d512c773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56359
4278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.563594278
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.2149309414
Short name T1530
Test name
Test status
Simulation time 10046724157 ps
CPU time 13.79 seconds
Started Jun 07 08:42:17 PM PDT 24
Finished Jun 07 08:42:33 PM PDT 24
Peak memory 205792 kb
Host smart-2f5c7746-34d4-4fc8-8d67-4cfc34c29b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21493
09414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.2149309414
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.4170145517
Short name T1003
Test name
Test status
Simulation time 10057121047 ps
CPU time 12.53 seconds
Started Jun 07 08:42:16 PM PDT 24
Finished Jun 07 08:42:30 PM PDT 24
Peak memory 205868 kb
Host smart-8b095203-a56e-4f93-ad5a-05cf2d06b662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41701
45517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.4170145517
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1045415924
Short name T732
Test name
Test status
Simulation time 10175108911 ps
CPU time 12.87 seconds
Started Jun 07 08:42:09 PM PDT 24
Finished Jun 07 08:42:24 PM PDT 24
Peak memory 205008 kb
Host smart-c69a6361-ef4b-43b9-8925-4dea3eac0d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10454
15924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1045415924
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.1247334757
Short name T1146
Test name
Test status
Simulation time 10082980336 ps
CPU time 14.4 seconds
Started Jun 07 08:42:16 PM PDT 24
Finished Jun 07 08:42:33 PM PDT 24
Peak memory 205852 kb
Host smart-f64f9131-f160-4e38-ab80-dae5df94e291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12473
34757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.1247334757
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.2197946788
Short name T1117
Test name
Test status
Simulation time 10056462978 ps
CPU time 13.02 seconds
Started Jun 07 08:42:18 PM PDT 24
Finished Jun 07 08:42:34 PM PDT 24
Peak memory 205872 kb
Host smart-b8bc4ee9-9ae6-40a4-80bd-a0be71f0a451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21979
46788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.2197946788
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.4213060070
Short name T1717
Test name
Test status
Simulation time 15222665606 ps
CPU time 62.57 seconds
Started Jun 07 08:42:16 PM PDT 24
Finished Jun 07 08:43:20 PM PDT 24
Peak memory 205860 kb
Host smart-8420ef09-37d2-455b-9d17-32adce3a298e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42130
60070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.4213060070
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.16746764
Short name T1143
Test name
Test status
Simulation time 10148460251 ps
CPU time 13.66 seconds
Started Jun 07 08:42:34 PM PDT 24
Finished Jun 07 08:42:50 PM PDT 24
Peak memory 205724 kb
Host smart-dda806c5-6d54-40ed-b58c-8557cd322abe
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=16746764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.16746764
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.355342727
Short name T942
Test name
Test status
Simulation time 10059276842 ps
CPU time 14 seconds
Started Jun 07 08:42:31 PM PDT 24
Finished Jun 07 08:42:47 PM PDT 24
Peak memory 205936 kb
Host smart-deb0a5c6-c985-4fdf-a8c6-ad30038f5985
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=355342727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.355342727
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.2230242293
Short name T961
Test name
Test status
Simulation time 10165466601 ps
CPU time 14.6 seconds
Started Jun 07 08:42:34 PM PDT 24
Finished Jun 07 08:42:50 PM PDT 24
Peak memory 205820 kb
Host smart-d9a20fef-e288-4fd9-a36b-8f74e13d4c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22302
42293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.2230242293
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.3332463929
Short name T1266
Test name
Test status
Simulation time 13600314333 ps
CPU time 16.46 seconds
Started Jun 07 08:42:21 PM PDT 24
Finished Jun 07 08:42:40 PM PDT 24
Peak memory 205764 kb
Host smart-1050a90c-5edd-48c8-9f8d-6449e1ce4f6f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3332463929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.3332463929
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.209166700
Short name T900
Test name
Test status
Simulation time 23341691121 ps
CPU time 26.83 seconds
Started Jun 07 08:42:20 PM PDT 24
Finished Jun 07 08:42:50 PM PDT 24
Peak memory 205872 kb
Host smart-ac41ff78-4a9b-4a29-a59e-946b13949510
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=209166700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.209166700
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.1380438231
Short name T587
Test name
Test status
Simulation time 10058119870 ps
CPU time 14.35 seconds
Started Jun 07 08:42:19 PM PDT 24
Finished Jun 07 08:42:36 PM PDT 24
Peak memory 205840 kb
Host smart-c32d0047-01c2-4ff4-8d6e-38df506e2d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13804
38231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.1380438231
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.3782976827
Short name T861
Test name
Test status
Simulation time 10083185015 ps
CPU time 13.05 seconds
Started Jun 07 08:42:23 PM PDT 24
Finished Jun 07 08:42:39 PM PDT 24
Peak memory 205768 kb
Host smart-21ad7477-ebde-40e1-acdf-1d2adcf5c80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37829
76827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.3782976827
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.759790649
Short name T67
Test name
Test status
Simulation time 10195760805 ps
CPU time 14.89 seconds
Started Jun 07 08:42:19 PM PDT 24
Finished Jun 07 08:42:36 PM PDT 24
Peak memory 205696 kb
Host smart-6da6b355-d904-42a3-a683-51c00b2eb31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75979
0649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.759790649
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.319610612
Short name T1780
Test name
Test status
Simulation time 10046874393 ps
CPU time 12.59 seconds
Started Jun 07 08:42:21 PM PDT 24
Finished Jun 07 08:42:37 PM PDT 24
Peak memory 205828 kb
Host smart-79287170-86b5-4c45-a7e7-3e24849e0869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31961
0612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.319610612
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.3608004241
Short name T923
Test name
Test status
Simulation time 10045485804 ps
CPU time 12.68 seconds
Started Jun 07 08:42:26 PM PDT 24
Finished Jun 07 08:42:41 PM PDT 24
Peak memory 205832 kb
Host smart-50731a0c-8eba-4238-931b-352977705d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36080
04241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3608004241
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.1136944019
Short name T629
Test name
Test status
Simulation time 10900571965 ps
CPU time 14.11 seconds
Started Jun 07 08:42:25 PM PDT 24
Finished Jun 07 08:42:41 PM PDT 24
Peak memory 205836 kb
Host smart-17acd118-acaa-4d75-bd26-b4b632db981b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11369
44019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.1136944019
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.545783832
Short name T1403
Test name
Test status
Simulation time 10249237318 ps
CPU time 14.05 seconds
Started Jun 07 08:42:21 PM PDT 24
Finished Jun 07 08:42:37 PM PDT 24
Peak memory 205848 kb
Host smart-7887a547-9359-479a-9b0a-0eacf32a8b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54578
3832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.545783832
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.3353346530
Short name T898
Test name
Test status
Simulation time 10102092935 ps
CPU time 15.47 seconds
Started Jun 07 08:42:29 PM PDT 24
Finished Jun 07 08:42:46 PM PDT 24
Peak memory 205744 kb
Host smart-4647c603-f452-492f-bad4-81ff55ef3ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33533
46530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.3353346530
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.2153192818
Short name T1666
Test name
Test status
Simulation time 10058781071 ps
CPU time 12.98 seconds
Started Jun 07 08:42:30 PM PDT 24
Finished Jun 07 08:42:45 PM PDT 24
Peak memory 205748 kb
Host smart-071a3f93-f103-4294-9206-9bbf7caf497e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21531
92818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.2153192818
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3574185698
Short name T1207
Test name
Test status
Simulation time 10194322573 ps
CPU time 16.02 seconds
Started Jun 07 08:42:21 PM PDT 24
Finished Jun 07 08:42:40 PM PDT 24
Peak memory 205872 kb
Host smart-0435aa80-3931-41a5-bd58-101d323f8b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35741
85698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3574185698
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.2288899686
Short name T547
Test name
Test status
Simulation time 10071842537 ps
CPU time 13.34 seconds
Started Jun 07 08:42:21 PM PDT 24
Finished Jun 07 08:42:38 PM PDT 24
Peak memory 205908 kb
Host smart-f69876d8-8026-47cd-9ca0-e49ad9145524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22888
99686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.2288899686
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.3935749807
Short name T454
Test name
Test status
Simulation time 13286007048 ps
CPU time 16.02 seconds
Started Jun 07 08:42:21 PM PDT 24
Finished Jun 07 08:42:40 PM PDT 24
Peak memory 205880 kb
Host smart-9fe4af9c-d99f-4919-974e-e6e941953aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39357
49807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.3935749807
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.1884362946
Short name T1805
Test name
Test status
Simulation time 10124704726 ps
CPU time 13.81 seconds
Started Jun 07 08:42:22 PM PDT 24
Finished Jun 07 08:42:39 PM PDT 24
Peak memory 205712 kb
Host smart-05951f9f-37c2-478c-9896-82bc2c13352d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18843
62946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.1884362946
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.883290308
Short name T1299
Test name
Test status
Simulation time 19396434051 ps
CPU time 278.34 seconds
Started Jun 07 08:42:20 PM PDT 24
Finished Jun 07 08:47:01 PM PDT 24
Peak memory 205676 kb
Host smart-5cd1c865-831b-4491-aaf5-5e1bf467a321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88329
0308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.883290308
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2205318854
Short name T199
Test name
Test status
Simulation time 10050241600 ps
CPU time 12.63 seconds
Started Jun 07 08:42:23 PM PDT 24
Finished Jun 07 08:42:38 PM PDT 24
Peak memory 205852 kb
Host smart-787a3cf5-e7cb-4846-88cb-068642e2ad1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22053
18854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2205318854
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.119118040
Short name T97
Test name
Test status
Simulation time 10091242028 ps
CPU time 13.01 seconds
Started Jun 07 08:42:26 PM PDT 24
Finished Jun 07 08:42:41 PM PDT 24
Peak memory 205844 kb
Host smart-6a0aa9e6-c013-42f6-98c6-8a649c78c29d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11911
8040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.119118040
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.3095678687
Short name T575
Test name
Test status
Simulation time 10096104545 ps
CPU time 12.98 seconds
Started Jun 07 08:42:19 PM PDT 24
Finished Jun 07 08:42:34 PM PDT 24
Peak memory 205792 kb
Host smart-fd1b9c7c-364e-441d-aaa7-1a4a6d2643cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30956
78687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.3095678687
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.4115490052
Short name T870
Test name
Test status
Simulation time 10098273140 ps
CPU time 15.97 seconds
Started Jun 07 08:42:27 PM PDT 24
Finished Jun 07 08:42:45 PM PDT 24
Peak memory 205848 kb
Host smart-d28bc8e9-9ca2-4de3-b687-e7705639acc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41154
90052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.4115490052
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.1677517803
Short name T404
Test name
Test status
Simulation time 10067282828 ps
CPU time 13.89 seconds
Started Jun 07 08:42:28 PM PDT 24
Finished Jun 07 08:42:44 PM PDT 24
Peak memory 205888 kb
Host smart-174a7196-ce5f-41e3-b074-7c815bae2c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16775
17803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.1677517803
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.346603314
Short name T644
Test name
Test status
Simulation time 10050510246 ps
CPU time 16.15 seconds
Started Jun 07 08:42:30 PM PDT 24
Finished Jun 07 08:42:48 PM PDT 24
Peak memory 205860 kb
Host smart-265c6b7c-d9d3-4d87-aebd-d5b06fff26d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34660
3314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.346603314
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_eop_single_bit_handling.124405387
Short name T1119
Test name
Test status
Simulation time 10060858074 ps
CPU time 12.84 seconds
Started Jun 07 08:42:29 PM PDT 24
Finished Jun 07 08:42:44 PM PDT 24
Peak memory 205824 kb
Host smart-e6ac9497-b1d8-4395-871c-c022e4b312da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12440
5387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_eop_single_bit_handling.124405387
Directory /workspace/7.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2052131876
Short name T335
Test name
Test status
Simulation time 10097166781 ps
CPU time 15.6 seconds
Started Jun 07 08:42:30 PM PDT 24
Finished Jun 07 08:42:47 PM PDT 24
Peak memory 205852 kb
Host smart-15d07356-420b-464d-b88f-d8b900738a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20521
31876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2052131876
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.173126959
Short name T1290
Test name
Test status
Simulation time 10030783153 ps
CPU time 12.84 seconds
Started Jun 07 08:42:35 PM PDT 24
Finished Jun 07 08:42:50 PM PDT 24
Peak memory 205760 kb
Host smart-8bf34921-780d-4d43-973e-8908cfc1cb9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17312
6959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.173126959
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.635549563
Short name T235
Test name
Test status
Simulation time 17738461945 ps
CPU time 29.06 seconds
Started Jun 07 08:42:26 PM PDT 24
Finished Jun 07 08:42:57 PM PDT 24
Peak memory 205792 kb
Host smart-d617791e-e506-4f23-921f-96378e5c570d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63554
9563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.635549563
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.2171313499
Short name T1496
Test name
Test status
Simulation time 10145066429 ps
CPU time 14.47 seconds
Started Jun 07 08:42:27 PM PDT 24
Finished Jun 07 08:42:43 PM PDT 24
Peak memory 205856 kb
Host smart-f4a6ddec-5f24-40ec-ac02-3405de58237e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21713
13499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.2171313499
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.4148051721
Short name T1505
Test name
Test status
Simulation time 10122418452 ps
CPU time 16.65 seconds
Started Jun 07 08:42:30 PM PDT 24
Finished Jun 07 08:42:48 PM PDT 24
Peak memory 205864 kb
Host smart-5eeeadaf-c0d8-4f5f-a4a5-999d6643e358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41480
51721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.4148051721
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.3474476255
Short name T1771
Test name
Test status
Simulation time 38180250723 ps
CPU time 725.08 seconds
Started Jun 07 08:42:29 PM PDT 24
Finished Jun 07 08:54:36 PM PDT 24
Peak memory 205912 kb
Host smart-b41fecde-c95d-4dd0-a513-408fa89ab68f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3474476255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.3474476255
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.3573947303
Short name T1959
Test name
Test status
Simulation time 31955527580 ps
CPU time 143.68 seconds
Started Jun 07 08:42:29 PM PDT 24
Finished Jun 07 08:44:55 PM PDT 24
Peak memory 205820 kb
Host smart-22eeb6b9-ab37-486d-af10-c9dd4e9553f7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3573947303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.3573947303
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.2186190589
Short name T1789
Test name
Test status
Simulation time 22390061192 ps
CPU time 256.61 seconds
Started Jun 07 08:42:32 PM PDT 24
Finished Jun 07 08:46:51 PM PDT 24
Peak memory 205876 kb
Host smart-8c5589ad-f57f-4218-98ef-e79d31f61095
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2186190589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.2186190589
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.2293567846
Short name T912
Test name
Test status
Simulation time 10119944732 ps
CPU time 12.45 seconds
Started Jun 07 08:42:28 PM PDT 24
Finished Jun 07 08:42:42 PM PDT 24
Peak memory 205812 kb
Host smart-6bbe34ed-5b4f-4bff-8d03-19bf3be7c1e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22935
67846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.2293567846
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.51688682
Short name T49
Test name
Test status
Simulation time 10091062302 ps
CPU time 14.05 seconds
Started Jun 07 08:42:28 PM PDT 24
Finished Jun 07 08:42:44 PM PDT 24
Peak memory 205804 kb
Host smart-5e557ada-3c1d-4fc2-bfa9-de1e32223f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51688
682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.51688682
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.3118103553
Short name T133
Test name
Test status
Simulation time 10046692832 ps
CPU time 12.55 seconds
Started Jun 07 08:42:30 PM PDT 24
Finished Jun 07 08:42:44 PM PDT 24
Peak memory 205756 kb
Host smart-d88820d6-2f2e-4f51-99c5-a77d64111701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31181
03553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.3118103553
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3721962887
Short name T349
Test name
Test status
Simulation time 10051829388 ps
CPU time 12.73 seconds
Started Jun 07 08:42:27 PM PDT 24
Finished Jun 07 08:42:42 PM PDT 24
Peak memory 205944 kb
Host smart-442a3e4d-3ca8-4281-8753-1bee79b310d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37219
62887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3721962887
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.3626968248
Short name T922
Test name
Test status
Simulation time 10126593224 ps
CPU time 12.59 seconds
Started Jun 07 08:42:22 PM PDT 24
Finished Jun 07 08:42:38 PM PDT 24
Peak memory 205800 kb
Host smart-02ce8458-e61b-459a-9de0-72f5306eda0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36269
68248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.3626968248
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.3675198865
Short name T301
Test name
Test status
Simulation time 10044470243 ps
CPU time 13.78 seconds
Started Jun 07 08:42:30 PM PDT 24
Finished Jun 07 08:42:46 PM PDT 24
Peak memory 205904 kb
Host smart-68e700fd-353f-435c-b2bf-ef8c83df39c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36751
98865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.3675198865
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.2194339490
Short name T2018
Test name
Test status
Simulation time 10068097646 ps
CPU time 14.42 seconds
Started Jun 07 08:42:27 PM PDT 24
Finished Jun 07 08:42:43 PM PDT 24
Peak memory 205736 kb
Host smart-8d5a08dd-6a32-4ae7-a925-a48ba5fd014b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21943
39490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.2194339490
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.2240919662
Short name T576
Test name
Test status
Simulation time 21732571795 ps
CPU time 121.76 seconds
Started Jun 07 08:42:30 PM PDT 24
Finished Jun 07 08:44:33 PM PDT 24
Peak memory 205832 kb
Host smart-a00d95e6-c606-4512-8d49-e51287cda55a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22409
19662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.2240919662
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.3528058010
Short name T425
Test name
Test status
Simulation time 10145090326 ps
CPU time 12.63 seconds
Started Jun 07 08:42:47 PM PDT 24
Finished Jun 07 08:43:01 PM PDT 24
Peak memory 205776 kb
Host smart-b69b4998-af62-494a-b955-6b83b4b0d6b3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3528058010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.3528058010
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.3990071215
Short name T1050
Test name
Test status
Simulation time 10059729012 ps
CPU time 13.71 seconds
Started Jun 07 08:42:48 PM PDT 24
Finished Jun 07 08:43:04 PM PDT 24
Peak memory 205844 kb
Host smart-a00d93b9-41ba-4653-9926-838ed681bd04
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3990071215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.3990071215
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.2861833712
Short name T1357
Test name
Test status
Simulation time 10100471525 ps
CPU time 15.84 seconds
Started Jun 07 08:42:48 PM PDT 24
Finished Jun 07 08:43:07 PM PDT 24
Peak memory 205888 kb
Host smart-35664a41-9ffe-4d68-b27b-8e6e0bd33267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28618
33712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.2861833712
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.949466815
Short name T1896
Test name
Test status
Simulation time 13345924995 ps
CPU time 15.96 seconds
Started Jun 07 08:42:36 PM PDT 24
Finished Jun 07 08:42:54 PM PDT 24
Peak memory 205736 kb
Host smart-938d22b2-bbbc-43c8-820a-c2ab3c92692f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=949466815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.949466815
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.1307671365
Short name T886
Test name
Test status
Simulation time 23197667460 ps
CPU time 23.82 seconds
Started Jun 07 08:42:37 PM PDT 24
Finished Jun 07 08:43:03 PM PDT 24
Peak memory 205776 kb
Host smart-f83d22b5-6aff-4f20-b948-7d29778fd7e0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1307671365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.1307671365
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.2647202922
Short name T694
Test name
Test status
Simulation time 10092866490 ps
CPU time 13.28 seconds
Started Jun 07 08:42:37 PM PDT 24
Finished Jun 07 08:42:53 PM PDT 24
Peak memory 205812 kb
Host smart-4927a652-6f1d-4cf9-b194-82e4809f1bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26472
02922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.2647202922
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.1408263368
Short name T1467
Test name
Test status
Simulation time 10945929102 ps
CPU time 14.15 seconds
Started Jun 07 08:42:37 PM PDT 24
Finished Jun 07 08:42:54 PM PDT 24
Peak memory 205720 kb
Host smart-692c8f87-5883-47e8-8529-d64081d4c844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14082
63368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.1408263368
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.2787631237
Short name T1369
Test name
Test status
Simulation time 10079346550 ps
CPU time 14.26 seconds
Started Jun 07 08:42:35 PM PDT 24
Finished Jun 07 08:42:52 PM PDT 24
Peak memory 205816 kb
Host smart-15c4fb36-f821-4631-8d15-0ab2ac72b139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27876
31237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.2787631237
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.3331318576
Short name T455
Test name
Test status
Simulation time 10050140430 ps
CPU time 15.38 seconds
Started Jun 07 08:42:38 PM PDT 24
Finished Jun 07 08:42:55 PM PDT 24
Peak memory 205832 kb
Host smart-dbf31a95-3308-48f6-aa41-53b74a5977a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33313
18576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3331318576
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.4029540894
Short name T604
Test name
Test status
Simulation time 10891380201 ps
CPU time 14.97 seconds
Started Jun 07 08:42:35 PM PDT 24
Finished Jun 07 08:42:52 PM PDT 24
Peak memory 205836 kb
Host smart-246e6d8d-c49b-466e-8087-2a648907da92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40295
40894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.4029540894
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.4099530810
Short name T198
Test name
Test status
Simulation time 10190263273 ps
CPU time 14.41 seconds
Started Jun 07 08:42:33 PM PDT 24
Finished Jun 07 08:42:49 PM PDT 24
Peak memory 205844 kb
Host smart-98f8f535-cdbf-4e04-b53e-32f594bb93e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40995
30810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.4099530810
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.3440681133
Short name T1795
Test name
Test status
Simulation time 10110037614 ps
CPU time 12.51 seconds
Started Jun 07 08:42:46 PM PDT 24
Finished Jun 07 08:43:00 PM PDT 24
Peak memory 205712 kb
Host smart-a0e3ae49-0afb-4e90-b62c-653f93715775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34406
81133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.3440681133
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.961678687
Short name T1330
Test name
Test status
Simulation time 10074207691 ps
CPU time 13.92 seconds
Started Jun 07 08:42:49 PM PDT 24
Finished Jun 07 08:43:06 PM PDT 24
Peak memory 205828 kb
Host smart-171f3942-f361-4329-88eb-e81570d6bdd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96167
8687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.961678687
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3773536482
Short name T1302
Test name
Test status
Simulation time 10138569996 ps
CPU time 13.17 seconds
Started Jun 07 08:42:35 PM PDT 24
Finished Jun 07 08:42:51 PM PDT 24
Peak memory 205880 kb
Host smart-ce2ad9c8-1938-42ca-bc8f-ed95ae49a46d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37735
36482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3773536482
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.3067976914
Short name T706
Test name
Test status
Simulation time 10061273649 ps
CPU time 13.81 seconds
Started Jun 07 08:42:36 PM PDT 24
Finished Jun 07 08:42:53 PM PDT 24
Peak memory 205700 kb
Host smart-59fe540f-c5af-4bb4-95ee-d8c3d4787a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30679
76914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.3067976914
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.1868583664
Short name T1582
Test name
Test status
Simulation time 13201479949 ps
CPU time 18.02 seconds
Started Jun 07 08:42:36 PM PDT 24
Finished Jun 07 08:42:57 PM PDT 24
Peak memory 205852 kb
Host smart-aff21658-84b9-4331-9948-b38145dfab4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18685
83664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.1868583664
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3306808318
Short name T1841
Test name
Test status
Simulation time 10098258798 ps
CPU time 13.53 seconds
Started Jun 07 08:42:40 PM PDT 24
Finished Jun 07 08:42:56 PM PDT 24
Peak memory 205316 kb
Host smart-1bc03cf6-8fdc-413d-8cdf-10f110f1a160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33068
08318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3306808318
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.3638740708
Short name T829
Test name
Test status
Simulation time 18120111293 ps
CPU time 72.12 seconds
Started Jun 07 08:42:46 PM PDT 24
Finished Jun 07 08:44:00 PM PDT 24
Peak memory 205880 kb
Host smart-487b5ef5-91d1-4e56-9601-1aca2f973b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36387
40708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.3638740708
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.491024241
Short name T1935
Test name
Test status
Simulation time 10058842410 ps
CPU time 13.25 seconds
Started Jun 07 08:42:36 PM PDT 24
Finished Jun 07 08:42:52 PM PDT 24
Peak memory 205756 kb
Host smart-8ba927bf-9eb7-4ab7-a03b-97cc9f40207c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49102
4241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.491024241
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.1995711848
Short name T107
Test name
Test status
Simulation time 10110929080 ps
CPU time 13.11 seconds
Started Jun 07 08:42:46 PM PDT 24
Finished Jun 07 08:43:01 PM PDT 24
Peak memory 205772 kb
Host smart-e6d47699-3bac-466c-baab-5fb660176c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19957
11848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.1995711848
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.1500453947
Short name T778
Test name
Test status
Simulation time 10076066635 ps
CPU time 13.17 seconds
Started Jun 07 08:42:41 PM PDT 24
Finished Jun 07 08:42:57 PM PDT 24
Peak memory 205844 kb
Host smart-721be71e-57f5-4a28-bfae-dfa346b734cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15004
53947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.1500453947
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.1013218155
Short name T1884
Test name
Test status
Simulation time 10087490987 ps
CPU time 15.89 seconds
Started Jun 07 08:42:42 PM PDT 24
Finished Jun 07 08:43:00 PM PDT 24
Peak memory 205888 kb
Host smart-d8b08af6-aeb7-41f2-af03-9a1c68aea86b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10132
18155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1013218155
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.4058146040
Short name T22
Test name
Test status
Simulation time 10075617011 ps
CPU time 12.73 seconds
Started Jun 07 08:42:46 PM PDT 24
Finished Jun 07 08:43:00 PM PDT 24
Peak memory 205772 kb
Host smart-31ecaf08-764f-4891-b886-e1d25c914d5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40581
46040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.4058146040
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.68305850
Short name T180
Test name
Test status
Simulation time 10056208722 ps
CPU time 13.53 seconds
Started Jun 07 08:42:41 PM PDT 24
Finished Jun 07 08:42:57 PM PDT 24
Peak memory 205800 kb
Host smart-7b9645c6-1c06-435f-b4d7-cd03b3e0203a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68305
850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.68305850
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_eop_single_bit_handling.2431431678
Short name T291
Test name
Test status
Simulation time 10058459081 ps
CPU time 15.96 seconds
Started Jun 07 08:42:42 PM PDT 24
Finished Jun 07 08:43:00 PM PDT 24
Peak memory 205868 kb
Host smart-f489f706-7bb4-4c51-a177-eb73c1f1f2b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24314
31678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_eop_single_bit_handling.2431431678
Directory /workspace/8.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.1827365128
Short name T1042
Test name
Test status
Simulation time 10043354924 ps
CPU time 13.83 seconds
Started Jun 07 08:42:39 PM PDT 24
Finished Jun 07 08:42:55 PM PDT 24
Peak memory 205840 kb
Host smart-c922c008-b426-440c-9d93-71c743911927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18273
65128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.1827365128
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3714400058
Short name T1678
Test name
Test status
Simulation time 10039511764 ps
CPU time 13.98 seconds
Started Jun 07 08:42:47 PM PDT 24
Finished Jun 07 08:43:03 PM PDT 24
Peak memory 205836 kb
Host smart-bbce5c50-9385-426c-a415-769cb1e0d0a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37144
00058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3714400058
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.264823917
Short name T178
Test name
Test status
Simulation time 19536746198 ps
CPU time 30.74 seconds
Started Jun 07 08:42:40 PM PDT 24
Finished Jun 07 08:43:13 PM PDT 24
Peak memory 205848 kb
Host smart-b0a67b31-fbb9-43aa-aec5-bec2be061c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26482
3917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.264823917
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.3077021006
Short name T873
Test name
Test status
Simulation time 10102327662 ps
CPU time 15.15 seconds
Started Jun 07 08:42:43 PM PDT 24
Finished Jun 07 08:43:00 PM PDT 24
Peak memory 205856 kb
Host smart-f4e6664f-6401-496e-99b6-06924d82222b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30770
21006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.3077021006
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3942597366
Short name T1637
Test name
Test status
Simulation time 10135822273 ps
CPU time 14.14 seconds
Started Jun 07 08:42:40 PM PDT 24
Finished Jun 07 08:42:56 PM PDT 24
Peak memory 205832 kb
Host smart-91fd7d1b-fbdc-456b-b219-6fa8e574d659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39425
97366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3942597366
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.1706695023
Short name T1764
Test name
Test status
Simulation time 29050281818 ps
CPU time 166.69 seconds
Started Jun 07 08:42:40 PM PDT 24
Finished Jun 07 08:45:29 PM PDT 24
Peak memory 205908 kb
Host smart-e8077936-77fb-4e42-a9bf-41b3e90013ef
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1706695023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.1706695023
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.1304258647
Short name T1504
Test name
Test status
Simulation time 21167485752 ps
CPU time 71.51 seconds
Started Jun 07 08:42:43 PM PDT 24
Finished Jun 07 08:43:56 PM PDT 24
Peak memory 205836 kb
Host smart-9ec85233-f8d1-4e9a-8839-2117170c823f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1304258647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.1304258647
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.990512268
Short name T1436
Test name
Test status
Simulation time 38116302233 ps
CPU time 727.53 seconds
Started Jun 07 08:42:40 PM PDT 24
Finished Jun 07 08:54:50 PM PDT 24
Peak memory 205988 kb
Host smart-9d2fa4fa-d616-4d70-889f-c49100ee80c3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=990512268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.990512268
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.1897055350
Short name T1734
Test name
Test status
Simulation time 10094805288 ps
CPU time 12.97 seconds
Started Jun 07 08:42:43 PM PDT 24
Finished Jun 07 08:42:58 PM PDT 24
Peak memory 205736 kb
Host smart-9cfaeb97-99b6-41a7-a4fb-eb293fc8b118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18970
55350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.1897055350
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.2898434833
Short name T1715
Test name
Test status
Simulation time 10055153477 ps
CPU time 13.87 seconds
Started Jun 07 08:42:42 PM PDT 24
Finished Jun 07 08:42:58 PM PDT 24
Peak memory 205760 kb
Host smart-5404193b-d21e-46e7-9d31-41afd1d6ec92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28984
34833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.2898434833
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.2736470308
Short name T963
Test name
Test status
Simulation time 10059337500 ps
CPU time 12.92 seconds
Started Jun 07 08:42:46 PM PDT 24
Finished Jun 07 08:43:00 PM PDT 24
Peak memory 205848 kb
Host smart-f030fc6c-304e-40cf-9f0a-956c9dda2a62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27364
70308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.2736470308
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.1481171811
Short name T1036
Test name
Test status
Simulation time 10048547000 ps
CPU time 13.21 seconds
Started Jun 07 08:42:40 PM PDT 24
Finished Jun 07 08:42:56 PM PDT 24
Peak memory 205748 kb
Host smart-c28159b4-0f8d-4542-b453-268e8e604de0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14811
71811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.1481171811
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.2914168574
Short name T1038
Test name
Test status
Simulation time 10102744843 ps
CPU time 14.31 seconds
Started Jun 07 08:42:34 PM PDT 24
Finished Jun 07 08:42:50 PM PDT 24
Peak memory 205948 kb
Host smart-25e7c9e2-c602-475d-8e75-17952f2dbf39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29141
68574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2914168574
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.169273842
Short name T20
Test name
Test status
Simulation time 10067771020 ps
CPU time 13.65 seconds
Started Jun 07 08:42:41 PM PDT 24
Finished Jun 07 08:42:57 PM PDT 24
Peak memory 205852 kb
Host smart-b9b498e7-e22f-4553-84a2-da720e0a7880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16927
3842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.169273842
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.817319824
Short name T761
Test name
Test status
Simulation time 10102212549 ps
CPU time 14.67 seconds
Started Jun 07 08:42:39 PM PDT 24
Finished Jun 07 08:42:56 PM PDT 24
Peak memory 205856 kb
Host smart-9524dae7-2fcb-4032-9a14-15210143ecf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81731
9824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.817319824
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.53472167
Short name T1851
Test name
Test status
Simulation time 25083773224 ps
CPU time 115.81 seconds
Started Jun 07 08:42:40 PM PDT 24
Finished Jun 07 08:44:38 PM PDT 24
Peak memory 205904 kb
Host smart-90b54425-e5eb-4e58-88e4-98e1e402bd3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53472
167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.53472167
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.3418509038
Short name T1078
Test name
Test status
Simulation time 10131593385 ps
CPU time 14.3 seconds
Started Jun 07 08:43:00 PM PDT 24
Finished Jun 07 08:43:19 PM PDT 24
Peak memory 205752 kb
Host smart-5510350a-b216-471f-803f-94a84c0496d4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3418509038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.3418509038
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.1956666342
Short name T984
Test name
Test status
Simulation time 10055561994 ps
CPU time 13.5 seconds
Started Jun 07 08:43:02 PM PDT 24
Finished Jun 07 08:43:20 PM PDT 24
Peak memory 205892 kb
Host smart-8ccadbce-315c-44e1-b5a5-8ce6ac074680
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1956666342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.1956666342
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.3764685768
Short name T623
Test name
Test status
Simulation time 10161371143 ps
CPU time 12.68 seconds
Started Jun 07 08:42:53 PM PDT 24
Finished Jun 07 08:43:08 PM PDT 24
Peak memory 205840 kb
Host smart-b018a2e6-6ab7-45f8-9c64-52e3897687e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37646
85768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.3764685768
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.3196093794
Short name T443
Test name
Test status
Simulation time 13925884948 ps
CPU time 16.73 seconds
Started Jun 07 08:42:49 PM PDT 24
Finished Jun 07 08:43:08 PM PDT 24
Peak memory 205780 kb
Host smart-56e46c5a-8dd0-48d9-89b1-e96ae8464afd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3196093794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.3196093794
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2107039936
Short name T326
Test name
Test status
Simulation time 10091478544 ps
CPU time 13.09 seconds
Started Jun 07 08:42:49 PM PDT 24
Finished Jun 07 08:43:05 PM PDT 24
Peak memory 205756 kb
Host smart-4bd0c930-a026-4590-b189-6d1ab378fdf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21070
39936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2107039936
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.1334601286
Short name T64
Test name
Test status
Simulation time 10818293247 ps
CPU time 13.84 seconds
Started Jun 07 08:42:49 PM PDT 24
Finished Jun 07 08:43:05 PM PDT 24
Peak memory 205852 kb
Host smart-f240b276-eea6-4c61-855b-7caba2209ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13346
01286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.1334601286
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.4107994115
Short name T866
Test name
Test status
Simulation time 10048987173 ps
CPU time 15.08 seconds
Started Jun 07 08:42:48 PM PDT 24
Finished Jun 07 08:43:05 PM PDT 24
Peak memory 205836 kb
Host smart-95a3a66c-a39c-4199-952a-97ccef37790f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41079
94115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.4107994115
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.1444108853
Short name T324
Test name
Test status
Simulation time 10116308977 ps
CPU time 15.71 seconds
Started Jun 07 08:42:50 PM PDT 24
Finished Jun 07 08:43:08 PM PDT 24
Peak memory 205728 kb
Host smart-3d46811b-dd58-4c07-baba-efb60448e7fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14441
08853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.1444108853
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.1050294900
Short name T918
Test name
Test status
Simulation time 10575345699 ps
CPU time 14.25 seconds
Started Jun 07 08:42:48 PM PDT 24
Finished Jun 07 08:43:04 PM PDT 24
Peak memory 205844 kb
Host smart-4c60799b-dfe9-4b8b-a7fb-97ae66350104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10502
94900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.1050294900
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1389452884
Short name T822
Test name
Test status
Simulation time 10091747626 ps
CPU time 13.06 seconds
Started Jun 07 08:42:50 PM PDT 24
Finished Jun 07 08:43:06 PM PDT 24
Peak memory 205672 kb
Host smart-5a8983a1-93f3-4bdf-8e35-d309825bc1bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13894
52884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1389452884
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.122702972
Short name T816
Test name
Test status
Simulation time 10113362872 ps
CPU time 13.52 seconds
Started Jun 07 08:42:56 PM PDT 24
Finished Jun 07 08:43:13 PM PDT 24
Peak memory 205856 kb
Host smart-46c66fff-0c35-46bb-80f6-188066cfa60a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12270
2972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.122702972
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.1217002231
Short name T1170
Test name
Test status
Simulation time 10040614907 ps
CPU time 12.54 seconds
Started Jun 07 08:42:51 PM PDT 24
Finished Jun 07 08:43:06 PM PDT 24
Peak memory 205816 kb
Host smart-2fdac378-e998-4651-9ce8-95aea4252e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12170
02231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1217002231
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3468036376
Short name T1779
Test name
Test status
Simulation time 10060234876 ps
CPU time 15.51 seconds
Started Jun 07 08:42:50 PM PDT 24
Finished Jun 07 08:43:08 PM PDT 24
Peak memory 205852 kb
Host smart-bbbd5829-7ca7-464a-b30a-95ba867df23b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34680
36376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3468036376
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.3028193005
Short name T668
Test name
Test status
Simulation time 10094922311 ps
CPU time 14.06 seconds
Started Jun 07 08:42:46 PM PDT 24
Finished Jun 07 08:43:02 PM PDT 24
Peak memory 205732 kb
Host smart-09019292-ed51-4fe6-8eb3-9c134f692e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30281
93005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.3028193005
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.2075582900
Short name T2003
Test name
Test status
Simulation time 13181261542 ps
CPU time 15.95 seconds
Started Jun 07 08:42:47 PM PDT 24
Finished Jun 07 08:43:06 PM PDT 24
Peak memory 205884 kb
Host smart-d120ebb9-3468-4996-aac1-fe7c1ba95bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20755
82900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.2075582900
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.4237955510
Short name T1311
Test name
Test status
Simulation time 10085837218 ps
CPU time 13.46 seconds
Started Jun 07 08:42:47 PM PDT 24
Finished Jun 07 08:43:03 PM PDT 24
Peak memory 205812 kb
Host smart-80d9b01d-b8ba-4d04-a91f-bdd890939c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42379
55510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.4237955510
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.3975967392
Short name T1181
Test name
Test status
Simulation time 16727987538 ps
CPU time 201.34 seconds
Started Jun 07 08:42:45 PM PDT 24
Finished Jun 07 08:46:08 PM PDT 24
Peak memory 205736 kb
Host smart-48d9334c-6fd4-4c15-80ad-c19a0058ea25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39759
67392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.3975967392
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.786043909
Short name T356
Test name
Test status
Simulation time 10131024967 ps
CPU time 14.92 seconds
Started Jun 07 08:42:49 PM PDT 24
Finished Jun 07 08:43:07 PM PDT 24
Peak memory 205772 kb
Host smart-761aed37-1fdf-4cef-828d-fadffefcc09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78604
3909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.786043909
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.3036766467
Short name T1800
Test name
Test status
Simulation time 10107610227 ps
CPU time 12.91 seconds
Started Jun 07 08:42:49 PM PDT 24
Finished Jun 07 08:43:04 PM PDT 24
Peak memory 205728 kb
Host smart-65e7dc67-ddc4-4efd-b27c-5e9eacefce5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30367
66467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.3036766467
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2776260010
Short name T297
Test name
Test status
Simulation time 10066753859 ps
CPU time 14.29 seconds
Started Jun 07 08:42:47 PM PDT 24
Finished Jun 07 08:43:04 PM PDT 24
Peak memory 205824 kb
Host smart-31a76a91-3f5d-48fa-9412-ebfadaeeab48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27762
60010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2776260010
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.4004244444
Short name T833
Test name
Test status
Simulation time 10061813775 ps
CPU time 14.3 seconds
Started Jun 07 08:42:48 PM PDT 24
Finished Jun 07 08:43:04 PM PDT 24
Peak memory 205848 kb
Host smart-1504bb5e-38da-4d0e-acec-0b173ab040f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40042
44444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.4004244444
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.3990453909
Short name T1386
Test name
Test status
Simulation time 10089975522 ps
CPU time 12.56 seconds
Started Jun 07 08:42:55 PM PDT 24
Finished Jun 07 08:43:10 PM PDT 24
Peak memory 205800 kb
Host smart-efc03a62-7f1e-4009-a8da-4dbf3ffb9025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39904
53909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.3990453909
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.723171018
Short name T1338
Test name
Test status
Simulation time 10068909641 ps
CPU time 13.13 seconds
Started Jun 07 08:42:55 PM PDT 24
Finished Jun 07 08:43:12 PM PDT 24
Peak memory 205812 kb
Host smart-f28795b0-5e83-4842-bf11-b211cd5ef061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72317
1018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.723171018
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_eop_single_bit_handling.2171751366
Short name T737
Test name
Test status
Simulation time 10085030895 ps
CPU time 12.62 seconds
Started Jun 07 08:42:58 PM PDT 24
Finished Jun 07 08:43:15 PM PDT 24
Peak memory 205888 kb
Host smart-fc2c0675-d77f-4b0a-8984-b92cf1e37123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21717
51366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_eop_single_bit_handling.2171751366
Directory /workspace/9.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.3152133454
Short name T1441
Test name
Test status
Simulation time 10059563969 ps
CPU time 12.93 seconds
Started Jun 07 08:42:55 PM PDT 24
Finished Jun 07 08:43:12 PM PDT 24
Peak memory 205876 kb
Host smart-94cb398d-1c95-4d71-8672-a5f1f537b6eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31521
33454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3152133454
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.3764970992
Short name T1742
Test name
Test status
Simulation time 10037654006 ps
CPU time 12.71 seconds
Started Jun 07 08:42:54 PM PDT 24
Finished Jun 07 08:43:10 PM PDT 24
Peak memory 205756 kb
Host smart-d21c75f8-baad-4876-b22e-bfe98ed2a68f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37649
70992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.3764970992
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.3028077482
Short name T163
Test name
Test status
Simulation time 29680877547 ps
CPU time 57.97 seconds
Started Jun 07 08:42:53 PM PDT 24
Finished Jun 07 08:43:53 PM PDT 24
Peak memory 205700 kb
Host smart-e740244b-9577-4d71-9c70-ed4ff8fbc396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30280
77482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.3028077482
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.3518523295
Short name T341
Test name
Test status
Simulation time 10072014401 ps
CPU time 14.34 seconds
Started Jun 07 08:42:56 PM PDT 24
Finished Jun 07 08:43:14 PM PDT 24
Peak memory 205860 kb
Host smart-cd20bf6d-78a7-498c-bd5e-4667b0a9790b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35185
23295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3518523295
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.2687241985
Short name T1260
Test name
Test status
Simulation time 10130636031 ps
CPU time 12.95 seconds
Started Jun 07 08:42:57 PM PDT 24
Finished Jun 07 08:43:13 PM PDT 24
Peak memory 205788 kb
Host smart-49872b63-3014-4a6c-b1a7-a1eafa2edb41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26872
41985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.2687241985
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.1487242118
Short name T864
Test name
Test status
Simulation time 18302996453 ps
CPU time 144.53 seconds
Started Jun 07 08:42:53 PM PDT 24
Finished Jun 07 08:45:20 PM PDT 24
Peak memory 205884 kb
Host smart-40a950ba-5893-4d4b-bf0e-bdf70b220d2b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1487242118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.1487242118
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.507709596
Short name T165
Test name
Test status
Simulation time 32005653015 ps
CPU time 208.62 seconds
Started Jun 07 08:42:55 PM PDT 24
Finished Jun 07 08:46:27 PM PDT 24
Peak memory 205908 kb
Host smart-029e4c67-8a5c-4811-ab0c-93e8301079e9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=507709596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.507709596
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.1382951502
Short name T748
Test name
Test status
Simulation time 42495890251 ps
CPU time 211.2 seconds
Started Jun 07 08:42:55 PM PDT 24
Finished Jun 07 08:46:29 PM PDT 24
Peak memory 205828 kb
Host smart-c33dde7b-1cac-475a-94d9-e7e37ebaca3c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1382951502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.1382951502
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.1970286775
Short name T741
Test name
Test status
Simulation time 10082387428 ps
CPU time 12.82 seconds
Started Jun 07 08:42:54 PM PDT 24
Finished Jun 07 08:43:09 PM PDT 24
Peak memory 205852 kb
Host smart-a8392d1d-3049-4f40-b8b8-075ac8cced47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19702
86775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.1970286775
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.3891246056
Short name T1479
Test name
Test status
Simulation time 10039172163 ps
CPU time 12.49 seconds
Started Jun 07 08:42:56 PM PDT 24
Finished Jun 07 08:43:11 PM PDT 24
Peak memory 205800 kb
Host smart-cb3f27e2-af3e-4f75-ab25-a1172883a0dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38912
46056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.3891246056
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.3058267142
Short name T1106
Test name
Test status
Simulation time 10071008209 ps
CPU time 13.86 seconds
Started Jun 07 08:42:53 PM PDT 24
Finished Jun 07 08:43:10 PM PDT 24
Peak memory 205776 kb
Host smart-b510494d-6fc6-4d0a-9765-484d0d54104a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30582
67142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.3058267142
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2212363145
Short name T1615
Test name
Test status
Simulation time 10081930390 ps
CPU time 15.73 seconds
Started Jun 07 08:42:52 PM PDT 24
Finished Jun 07 08:43:10 PM PDT 24
Peak memory 205804 kb
Host smart-5a26f4b4-87c1-4510-89fd-c33c1a6a730f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22123
63145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2212363145
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2407864281
Short name T131
Test name
Test status
Simulation time 10212351771 ps
CPU time 14.57 seconds
Started Jun 07 08:42:49 PM PDT 24
Finished Jun 07 08:43:06 PM PDT 24
Peak memory 205772 kb
Host smart-b85dff7b-d96f-40bf-b263-c3186650802d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24078
64281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2407864281
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.4009050701
Short name T1032
Test name
Test status
Simulation time 10090274931 ps
CPU time 14 seconds
Started Jun 07 08:42:55 PM PDT 24
Finished Jun 07 08:43:12 PM PDT 24
Peak memory 205704 kb
Host smart-ff3fc438-7f3d-41ff-8e4c-61c4eca9d794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40090
50701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.4009050701
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.3221553181
Short name T570
Test name
Test status
Simulation time 10091236563 ps
CPU time 12.56 seconds
Started Jun 07 08:42:53 PM PDT 24
Finished Jun 07 08:43:08 PM PDT 24
Peak memory 205940 kb
Host smart-194b0bc6-75e0-4a90-a89d-4c4635271f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32215
53181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3221553181
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.2900627360
Short name T762
Test name
Test status
Simulation time 23773756355 ps
CPU time 107.26 seconds
Started Jun 07 08:42:59 PM PDT 24
Finished Jun 07 08:44:51 PM PDT 24
Peak memory 205876 kb
Host smart-3fb0ee53-bb35-4030-b8da-b756c768e826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29006
27360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.2900627360
Directory /workspace/9.usbdev_streaming_out/latest
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