Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	39394	1		T1	4		T2	3		T3	2
all_values[1]	39394	1		T1	4		T2	3		T3	2
all_values[2]	39394	1		T1	4		T2	3		T3	2
all_values[3]	39394	1		T1	4		T2	3		T3	2
all_values[4]	39394	1		T1	4		T2	3		T3	2
all_values[5]	39394	1		T1	4		T2	3		T3	2
all_values[6]	39394	1		T1	4		T2	3		T3	2
all_values[7]	39394	1		T1	4		T2	3		T3	2
all_values[8]	39394	1		T1	4		T2	3		T3	2
all_values[9]	39394	1		T1	4		T2	3		T3	2
all_values[10]	39394	1		T1	4		T2	3		T3	2
all_values[11]	39394	1		T1	4		T2	3		T3	2
all_values[12]	39394	1		T1	4		T2	3		T3	2
all_values[13]	39394	1		T1	4		T2	3		T3	2
all_values[14]	39394	1		T1	4		T2	3		T3	2
all_values[15]	39394	1		T1	4		T2	3		T3	2
all_values[16]	39394	1		T1	4		T2	3		T3	2
all_values[17]	39394	1		T1	4		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	703058	1		T1	72		T2	54		T3	36
auto[1]	6034	1		T35	2		T36	2		T37	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	704240	1		T1	72		T2	54		T3	36
auto[1]	4852	1		T116	69		T117	133		T118	74

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	38601	1		T1	4		T2	3		T3	2
all_values[0]	auto[0]	auto[1]	140	1		T116	2		T117	1		T118	3
all_values[0]	auto[1]	auto[0]	519	1		T37	3		T20	3		T24	3
all_values[0]	auto[1]	auto[1]	134	1		T116	3		T117	4		T119	5
all_values[1]	auto[0]	auto[0]	36686	1		T1	4		T2	3		T3	2
all_values[1]	auto[0]	auto[1]	142	1		T116	1		T117	3		T118	4
all_values[1]	auto[1]	auto[0]	2440	1		T7	4		T8	4		T22	4
all_values[1]	auto[1]	auto[1]	126	1		T116	4		T117	5		T118	1
all_values[2]	auto[0]	auto[0]	39001	1		T1	4		T2	3		T3	2
all_values[2]	auto[0]	auto[1]	147	1		T117	5		T118	5		T119	2
all_values[2]	auto[1]	auto[0]	133	1		T36	2		T17	2		T42	2
all_values[2]	auto[1]	auto[1]	113	1		T117	3		T119	5		T274	6
all_values[3]	auto[0]	auto[0]	39099	1		T1	4		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	136	1		T116	1		T117	3		T118	1
all_values[3]	auto[1]	auto[0]	34	1		T117	1		T121	2		T275	2
all_values[3]	auto[1]	auto[1]	125	1		T116	4		T117	4		T118	4
all_values[4]	auto[0]	auto[0]	39090	1		T1	4		T2	3		T3	2
all_values[4]	auto[0]	auto[1]	127	1		T116	4		T117	5		T119	7
all_values[4]	auto[1]	auto[0]	25	1		T118	1		T120	2		T121	1
all_values[4]	auto[1]	auto[1]	152	1		T116	1		T117	3		T118	4
all_values[5]	auto[0]	auto[0]	39101	1		T1	4		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	130	1		T116	3		T117	1		T118	4
all_values[5]	auto[1]	auto[0]	21	1		T116	1		T119	2		T276	3
all_values[5]	auto[1]	auto[1]	142	1		T117	7		T118	1		T119	1
all_values[6]	auto[0]	auto[0]	39081	1		T1	4		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	125	1		T116	4		T117	3		T119	7
all_values[6]	auto[1]	auto[0]	23	1		T117	1		T118	4		T119	1
all_values[6]	auto[1]	auto[1]	165	1		T116	1		T117	4		T274	4
all_values[7]	auto[0]	auto[0]	39104	1		T1	4		T2	3		T3	2
all_values[7]	auto[0]	auto[1]	120	1		T117	6		T118	3		T119	3
all_values[7]	auto[1]	auto[0]	29	1		T119	1		T120	1		T275	1
all_values[7]	auto[1]	auto[1]	141	1		T116	4		T117	2		T118	2
all_values[8]	auto[0]	auto[0]	39096	1		T1	4		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	129	1		T116	3		T117	4		T118	3
all_values[8]	auto[1]	auto[0]	27	1		T116	1		T117	1		T121	5
all_values[8]	auto[1]	auto[1]	142	1		T116	1		T117	3		T118	2
all_values[9]	auto[0]	auto[0]	39113	1		T1	4		T2	3		T3	2
all_values[9]	auto[0]	auto[1]	126	1		T117	2		T118	1		T119	6
all_values[9]	auto[1]	auto[0]	28	1		T118	1		T119	1		T277	3
all_values[9]	auto[1]	auto[1]	127	1		T116	3		T117	6		T118	3
all_values[10]	auto[0]	auto[0]	39095	1		T1	4		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	127	1		T116	5		T117	8		T118	4
all_values[10]	auto[1]	auto[0]	20	1		T278	1		T279	1		T280	1
all_values[10]	auto[1]	auto[1]	152	1		T118	1		T119	5		T120	3
all_values[11]	auto[0]	auto[0]	38996	1		T1	4		T2	3		T3	2
all_values[11]	auto[0]	auto[1]	150	1		T117	4		T118	5		T119	4
all_values[11]	auto[1]	auto[0]	133	1		T35	2		T60	2		T61	2
all_values[11]	auto[1]	auto[1]	115	1		T116	5		T117	4		T119	3
all_values[12]	auto[0]	auto[0]	39090	1		T1	4		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	128	1		T116	4		T117	7		T118	5
all_values[12]	auto[1]	auto[0]	32	1		T116	1		T120	4		T275	1
all_values[12]	auto[1]	auto[1]	144	1		T117	1		T119	1		T274	5
all_values[13]	auto[0]	auto[0]	39090	1		T1	4		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	152	1		T116	1		T117	1		T119	4
all_values[13]	auto[1]	auto[0]	22	1		T118	1		T119	2		T120	1
all_values[13]	auto[1]	auto[1]	130	1		T116	3		T117	7		T118	4
all_values[14]	auto[0]	auto[0]	39095	1		T1	4		T2	3		T3	2
all_values[14]	auto[0]	auto[1]	139	1		T116	1		T117	4		T119	4
all_values[14]	auto[1]	auto[0]	18	1		T117	1		T119	2		T120	1
all_values[14]	auto[1]	auto[1]	142	1		T116	3		T117	3		T118	5
all_values[15]	auto[0]	auto[0]	39104	1		T1	4		T2	3		T3	2
all_values[15]	auto[0]	auto[1]	129	1		T116	4		T117	6		T118	1
all_values[15]	auto[1]	auto[0]	31	1		T116	1		T117	1		T118	1
all_values[15]	auto[1]	auto[1]	130	1		T117	1		T118	3		T119	5
all_values[16]	auto[0]	auto[0]	39111	1		T1	4		T2	3		T3	2
all_values[16]	auto[0]	auto[1]	130	1		T117	2		T118	3		T119	6
all_values[16]	auto[1]	auto[0]	29	1		T116	1		T120	2		T274	1
all_values[16]	auto[1]	auto[1]	124	1		T117	4		T118	2		T119	2
all_values[17]	auto[0]	auto[0]	39091	1		T1	4		T2	3		T3	2
all_values[17]	auto[0]	auto[1]	137	1		T116	3		T117	5		T119	6
all_values[17]	auto[1]	auto[0]	32	1		T116	1		T117	1		T118	1
all_values[17]	auto[1]	auto[1]	134	1		T116	1		T117	2		T119	2