Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	39394	1		T1	4		T2	3		T3	2
all_pins[1]	39394	1		T1	4		T2	3		T3	2
all_pins[2]	39394	1		T1	4		T2	3		T3	2
all_pins[3]	39394	1		T1	4		T2	3		T3	2
all_pins[4]	39394	1		T1	4		T2	3		T3	2
all_pins[5]	39394	1		T1	4		T2	3		T3	2
all_pins[6]	39394	1		T1	4		T2	3		T3	2
all_pins[7]	39394	1		T1	4		T2	3		T3	2
all_pins[8]	39394	1		T1	4		T2	3		T3	2
all_pins[9]	39394	1		T1	4		T2	3		T3	2
all_pins[10]	39394	1		T1	4		T2	3		T3	2
all_pins[11]	39394	1		T1	4		T2	3		T3	2
all_pins[12]	39394	1		T1	4		T2	3		T3	2
all_pins[13]	39394	1		T1	4		T2	3		T3	2
all_pins[14]	39394	1		T1	4		T2	3		T3	2
all_pins[15]	39394	1		T1	4		T2	3		T3	2
all_pins[16]	39394	1		T1	4		T2	3		T3	2
all_pins[17]	39394	1		T1	4		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	706591	1		T1	72		T2	54		T3	36
values[0x1]	2501	1		T35	1		T36	1		T7	1
transitions[0x0=>0x1]	2224	1		T35	1		T36	1		T7	1
transitions[0x1=>0x0]	2234	1		T35	1		T36	1		T7	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	39285	1		T1	4		T2	3		T3	2
all_pins[0]	values[0x1]	109	1		T49	1		T281	1		T282	1
all_pins[0]	transitions[0x0=>0x1]	99	1		T49	1		T281	1		T282	1
all_pins[0]	transitions[0x1=>0x0]	1259	1		T7	1		T8	1		T22	2
all_pins[1]	values[0x0]	38125	1		T1	4		T2	3		T3	2
all_pins[1]	values[0x1]	1269	1		T7	1		T8	1		T22	2
all_pins[1]	transitions[0x0=>0x1]	1255	1		T7	1		T8	1		T22	2
all_pins[1]	transitions[0x1=>0x0]	91	1		T36	1		T17	1		T42	1
all_pins[2]	values[0x0]	39289	1		T1	4		T2	3		T3	2
all_pins[2]	values[0x1]	105	1		T36	1		T17	1		T42	1
all_pins[2]	transitions[0x0=>0x1]	92	1		T36	1		T17	1		T42	1
all_pins[2]	transitions[0x1=>0x0]	53	1		T116	1		T117	3		T118	3
all_pins[3]	values[0x0]	39328	1		T1	4		T2	3		T3	2
all_pins[3]	values[0x1]	66	1		T116	1		T117	3		T118	3
all_pins[3]	transitions[0x0=>0x1]	44	1		T117	3		T118	1		T274	3
all_pins[3]	transitions[0x1=>0x0]	53	1		T117	2		T119	1		T274	1
all_pins[4]	values[0x0]	39319	1		T1	4		T2	3		T3	2
all_pins[4]	values[0x1]	75	1		T116	1		T117	2		T118	2
all_pins[4]	transitions[0x0=>0x1]	56	1		T116	1		T117	2		T118	2
all_pins[4]	transitions[0x1=>0x0]	52	1		T117	5		T118	1		T120	3
all_pins[5]	values[0x0]	39323	1		T1	4		T2	3		T3	2
all_pins[5]	values[0x1]	71	1		T117	5		T118	1		T119	1
all_pins[5]	transitions[0x0=>0x1]	44	1		T117	2		T118	1		T119	1
all_pins[5]	transitions[0x1=>0x0]	55	1		T116	1		T274	2		T121	2
all_pins[6]	values[0x0]	39312	1		T1	4		T2	3		T3	2
all_pins[6]	values[0x1]	82	1		T116	1		T117	3		T274	2
all_pins[6]	transitions[0x0=>0x1]	72	1		T117	3		T274	2		T121	2
all_pins[6]	transitions[0x1=>0x0]	47	1		T117	2		T118	1		T119	1
all_pins[7]	values[0x0]	39337	1		T1	4		T2	3		T3	2
all_pins[7]	values[0x1]	57	1		T116	1		T117	2		T118	1
all_pins[7]	transitions[0x0=>0x1]	43	1		T117	2		T119	1		T121	1
all_pins[7]	transitions[0x1=>0x0]	39	1		T118	1		T119	2		T120	1
all_pins[8]	values[0x0]	39341	1		T1	4		T2	3		T3	2
all_pins[8]	values[0x1]	53	1		T116	1		T118	2		T119	2
all_pins[8]	transitions[0x0=>0x1]	38	1		T116	1		T118	2		T119	2
all_pins[8]	transitions[0x1=>0x0]	47	1		T116	2		T117	1		T119	1
all_pins[9]	values[0x0]	39332	1		T1	4		T2	3		T3	2
all_pins[9]	values[0x1]	62	1		T116	2		T117	1		T119	1
all_pins[9]	transitions[0x0=>0x1]	48	1		T116	2		T117	1		T121	1
all_pins[9]	transitions[0x1=>0x0]	57	1		T118	1		T119	1		T120	2
all_pins[10]	values[0x0]	39323	1		T1	4		T2	3		T3	2
all_pins[10]	values[0x1]	71	1		T118	1		T119	2		T120	2
all_pins[10]	transitions[0x0=>0x1]	61	1		T118	1		T119	2		T274	1
all_pins[10]	transitions[0x1=>0x0]	99	1		T35	1		T60	1		T61	1
all_pins[11]	values[0x0]	39285	1		T1	4		T2	3		T3	2
all_pins[11]	values[0x1]	109	1		T35	1		T60	1		T61	1
all_pins[11]	transitions[0x0=>0x1]	90	1		T35	1		T60	1		T61	1
all_pins[11]	transitions[0x1=>0x0]	50	1		T119	1		T274	2		T121	3
all_pins[12]	values[0x0]	39325	1		T1	4		T2	3		T3	2
all_pins[12]	values[0x1]	69	1		T117	1		T119	1		T274	3
all_pins[12]	transitions[0x0=>0x1]	55	1		T119	1		T121	3		T273	4
all_pins[12]	transitions[0x1=>0x0]	51	1		T117	4		T118	1		T120	3
all_pins[13]	values[0x0]	39329	1		T1	4		T2	3		T3	2
all_pins[13]	values[0x1]	65	1		T117	5		T118	1		T120	3
all_pins[13]	transitions[0x0=>0x1]	49	1		T117	5		T120	2		T274	3
all_pins[13]	transitions[0x1=>0x0]	51	1		T116	2		T117	1		T118	3
all_pins[14]	values[0x0]	39327	1		T1	4		T2	3		T3	2
all_pins[14]	values[0x1]	67	1		T116	2		T117	1		T118	4
all_pins[14]	transitions[0x0=>0x1]	52	1		T116	2		T118	2		T119	1
all_pins[14]	transitions[0x1=>0x0]	36	1		T119	4		T274	1		T275	1
all_pins[15]	values[0x0]	39343	1		T1	4		T2	3		T3	2
all_pins[15]	values[0x1]	51	1		T117	1		T118	2		T119	4
all_pins[15]	transitions[0x0=>0x1]	42	1		T117	1		T118	2		T119	4
all_pins[15]	transitions[0x1=>0x0]	49	1		T118	2		T119	1		T273	4
all_pins[16]	values[0x0]	39336	1		T1	4		T2	3		T3	2
all_pins[16]	values[0x1]	58	1		T118	2		T119	1		T273	4
all_pins[16]	transitions[0x0=>0x1]	49	1		T118	2		T119	1		T273	4
all_pins[16]	transitions[0x1=>0x0]	53	1		T116	1		T117	1		T119	1
all_pins[17]	values[0x0]	39332	1		T1	4		T2	3		T3	2
all_pins[17]	values[0x1]	62	1		T116	1		T117	1		T119	1
all_pins[17]	transitions[0x0=>0x1]	35	1		T116	1		T119	1		T275	2
all_pins[17]	transitions[0x1=>0x0]	92	1		T49	1		T281	1		T282	1